ARMmbed
/
mbed-os
mirror of https://github.com/ARMmbed/mbed-os.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

STM32F2 baremetal support

pull/13091/head
jeromecoutant 2020-05-15 18:13:34 +02:00
parent a28e809122
commit adbd936cbc
5 changed files with 162 additions and 118 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

71
targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/TOOLCHAIN_ARM/stm32f207xx.sct
View File

@ -1,74 +1,53 @@
#! armcc -E #! armcc -E
; Scatter-Loading Description File ; Scatter-Loading Description File
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Copyright (c) 2016, STMicroelectronics
; All rights reserved.
; ;
; Redistribution and use in source and binary forms, with or without ; SPDX-License-Identifier: BSD-3-Clause
; modification, are permitted provided that the following conditions are met: ;******************************************************************************
; ;* @attention
; 1. Redistributions of source code must retain the above copyright notice, ;*
; this list of conditions and the following disclaimer. ;* Copyright (c) 2016-2020 STMicroelectronics.
; 2. Redistributions in binary form must reproduce the above copyright notice, ;* All rights reserved.
; this list of conditions and the following disclaimer in the documentation ;*
; and/or other materials provided with the distribution. ;* This software component is licensed by ST under BSD 3-Clause license,
; 3. Neither the name of STMicroelectronics nor the names of its contributors ;* the "License"; You may not use this file except in compliance with the
; may be used to endorse or promote products derived from this software ;* License. You may obtain a copy of the License at:
; without specific prior written permission. ;* opensource.org/licenses/BSD-3-Clause
; ;*
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ;******************************************************************************
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE #include "../cmsis_nvic.h"
; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
#if !defined(MBED_APP_START) #if !defined(MBED_APP_START)
#define MBED_APP_START 0x08000000 #define MBED_APP_START MBED_ROM_START
#endif #endif
#if !defined(MBED_APP_SIZE) #if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE 0x100000 #define MBED_APP_SIZE MBED_ROM_SIZE
#endif #endif
#if !defined(MBED_RAM_START)
#define MBED_RAM_START 0x20000000
#endif
#if !defined(MBED_RAM_SIZE)
#define MBED_RAM_SIZE 0x00020000
#endif
#if !defined(MBED_BOOT_STACK_SIZE) #if !defined(MBED_BOOT_STACK_SIZE)
/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */
#define MBED_BOOT_STACK_SIZE 0x400 #define MBED_BOOT_STACK_SIZE 0x400
#endif #endif
; 97 vectors * 4 bytes = 388 bytes to reserve (0x184) 8-byte aligned = 0x188 (0x184 + 0x4) /* Round up VECTORS_SIZE to 8 bytes */
#define VECTOR_SIZE 0x188 #define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) AND ~7)
#define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+VECTOR_SIZE) LR_IROM1 MBED_APP_START MBED_APP_SIZE {
LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region ER_IROM1 MBED_APP_START MBED_APP_SIZE {
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
*.o (RESET, +First) *.o (RESET, +First)
*(InRoot$$Sections) *(InRoot$$Sections)
.ANY (+RO) .ANY (+RO)
} }
RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data RW_IRAM1 (MBED_RAM_START + VECTORS_SIZE) { ; RW data
.ANY (+RW +ZI) .ANY (+RW +ZI)
} }
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) { ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up
} }
ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; Stack region growing down
} }
} }

55
targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/TOOLCHAIN_GCC_ARM/STM32F207ZGTx_FLASH.ld
View File

@ -1,24 +1,44 @@
/* Linker script to configure memory regions. */
/*
* SPDX-License-Identifier: BSD-3-Clause
******************************************************************************
* @attention
*
* Copyright (c) 2016-2020 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
#include "../cmsis_nvic.h"
#if !defined(MBED_APP_START) #if !defined(MBED_APP_START)
#define MBED_APP_START 0x8000000 #define MBED_APP_START MBED_ROM_START
#endif #endif
#if !defined(MBED_APP_SIZE) #if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE 1024k #define MBED_APP_SIZE MBED_ROM_SIZE
#endif #endif
#if !defined(MBED_BOOT_STACK_SIZE) #if !defined(MBED_BOOT_STACK_SIZE)
/* This value is normally defined by the tools
to 0x1000 for bare metal and 0x400 for RTOS */
#define MBED_BOOT_STACK_SIZE 0x400 #define MBED_BOOT_STACK_SIZE 0x400
#endif #endif
STACK_SIZE = MBED_BOOT_STACK_SIZE; /* Round up VECTORS_SIZE to 8 bytes */
#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8)
/* Linker script to configure memory regions. */
/* 97 vectors * 4 bytes = 388 bytes to reserve (0x184) */
/* 8-byte aligned(0x184) = 0x188 */
MEMORY MEMORY
{ {
FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
RAM (rwx) : ORIGIN = 0x20000188, LENGTH = 128K - 0x188 RAM (rwx) : ORIGIN = MBED_RAM_START + VECTORS_SIZE, LENGTH = MBED_RAM_SIZE - VECTORS_SIZE
} }
/* Linker script to place sections and symbol values. Should be used together /* Linker script to place sections and symbol values. Should be used together
@ -56,6 +76,7 @@ SECTIONS
{ {
KEEP(*(.isr_vector)) KEEP(*(.isr_vector))
*(.text*) *(.text*)
KEEP(*(.init)) KEEP(*(.init))
KEEP(*(.fini)) KEEP(*(.fini))
@ -113,7 +134,6 @@ SECTIONS
KEEP(*(.init_array)) KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .); PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(8); . = ALIGN(8);
/* finit data */ /* finit data */
PROVIDE_HIDDEN (__fini_array_start = .); PROVIDE_HIDDEN (__fini_array_start = .);
@ -129,6 +149,19 @@ SECTIONS
} > RAM } > RAM
/* Uninitialized data section
* This region is not initialized by the C/C++ library and can be used to
* store state across soft reboots. */
.uninitialized (NOLOAD):
{
. = ALIGN(32);
__uninitialized_start = .;
*(.uninitialized)
KEEP(*(.keep.uninitialized))
. = ALIGN(32);
__uninitialized_end = .;
} > RAM
.bss : .bss :
{ {
. = ALIGN(8); . = ALIGN(8);
@ -144,9 +177,9 @@ SECTIONS
.heap (COPY): .heap (COPY):
{ {
__end__ = .; __end__ = .;
end = __end__; PROVIDE(end = .);
*(.heap*) *(.heap*)
. = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE; . = ORIGIN(RAM) + LENGTH(RAM) - MBED_BOOT_STACK_SIZE;
__HeapLimit = .; __HeapLimit = .;
} > RAM } > RAM
@ -162,7 +195,7 @@ SECTIONS
* size of stack_dummy section */ * size of stack_dummy section */
__StackTop = ORIGIN(RAM) + LENGTH(RAM); __StackTop = ORIGIN(RAM) + LENGTH(RAM);
_estack = __StackTop; _estack = __StackTop;
__StackLimit = __StackTop - STACK_SIZE; __StackLimit = __StackTop - MBED_BOOT_STACK_SIZE;
PROVIDE(__stack = __StackTop); PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */ /* Check if data + heap + stack exceeds RAM limit */

71
targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/TOOLCHAIN_IAR/stm32f207xx.icf
View File

@ -1,36 +1,59 @@
if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x08000000; } /* Linker script to configure memory regions.
if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x100000; } *
* SPDX-License-Identifier: BSD-3-Clause
******************************************************************************
* @attention
*
* Copyright (c) 2016-2020 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Device specific values */
/* [ROM = 1024kb = 0x100000] */ /* Tools provide -DMBED_ROM_START=xxx -DMBED_ROM_SIZE=xxx -DMBED_RAM_START=xxx -DMBED_RAM_SIZE=xxx */
define symbol __intvec_start__ = MBED_APP_START;
define symbol __region_ROM_start__ = 0x08000000;
define symbol __region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1;
/* [RAM = 128kb = 0x20000] Vector table dynamic copy: 97 vectors = 388 bytes (0x184) to be reserved in RAM */ define symbol VECTORS = 97; /* This value must match NVIC_NUM_VECTORS in cmsis_nvic.h */
define symbol __NVIC_start__ = 0x20000000; define symbol HEAP_SIZE = 0xa000;
define symbol __NVIC_end__ = 0x20000187; /*aligned on 8 bytes */
define symbol __region_RAM_start__ = 0x20000188;
define symbol __region_RAM_end__ = 0x2001FFFF;
/* Memory regions */ /* Common - Do not change */
define memory mem with size = 4G;
define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__]; if (!isdefinedsymbol(MBED_APP_START)) {
define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__]; define symbol MBED_APP_START = MBED_ROM_START;
}
if (!isdefinedsymbol(MBED_APP_SIZE)) {
define symbol MBED_APP_SIZE = MBED_ROM_SIZE;
}
/* Stack and Heap */
if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
/* This value is normally defined by the tools
to 0x1000 for bare metal and 0x400 for RTOS */
define symbol MBED_BOOT_STACK_SIZE = 0x400; define symbol MBED_BOOT_STACK_SIZE = 0x400;
} }
define symbol __size_cstack__ = MBED_BOOT_STACK_SIZE;
define symbol __size_heap__ = 0xF000;
define block CSTACK with alignment = 8, size = __size_cstack__ { };
define block HEAP with alignment = 8, size = __size_heap__ { };
define block STACKHEAP with fixed order { block HEAP, block CSTACK };
initialize by copy with packing = zeros { readwrite }; /* Round up VECTORS_SIZE to 8 bytes */
define symbol VECTORS_SIZE = ((VECTORS * 4) + 7) & ~7;
define symbol RAM_REGION_START = MBED_RAM_START + VECTORS_SIZE;
define symbol RAM_REGION_SIZE = MBED_RAM_SIZE - VECTORS_SIZE;
define memory mem with size = 4G;
define region ROM_region = mem:[from MBED_APP_START size MBED_APP_SIZE];
define region RAM_region = mem:[from RAM_REGION_START size RAM_REGION_SIZE];
define block CSTACK with alignment = 8, size = MBED_BOOT_STACK_SIZE { };
define block HEAP with alignment = 8, size = HEAP_SIZE { };
initialize by copy { readwrite };
do not initialize { section .noinit }; do not initialize { section .noinit };
place at address mem:__intvec_start__ { readonly section .intvec }; place at address mem: MBED_APP_START { readonly section .intvec };
place in ROM_region { readonly }; place in ROM_region { readonly };
place in RAM_region { readwrite, block STACKHEAP }; place in RAM_region { readwrite,
block CSTACK, block HEAP };

55
targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/cmsis_nvic.h
View File

@ -1,40 +1,39 @@
/* mbed Microcontroller Library /* mbed Microcontroller Library
******************************************************************************* * SPDX-License-Identifier: BSD-3-Clause
* Copyright (c) 2016, STMicroelectronics ******************************************************************************
* All rights reserved. * @attention
* *
* Redistribution and use in source and binary forms, with or without * <h2><center>&copy; Copyright (c) 2016-2020 STMicroelectronics.
* modification, are permitted provided that the following conditions are met: * All rights reserved.</center></h2>
* *
* 1. Redistributions of source code must retain the above copyright notice, * This software component is licensed by ST under BSD 3-Clause license,
* this list of conditions and the following disclaimer. * the "License"; You may not use this file except in compliance with the
* 2. Redistributions in binary form must reproduce the above copyright notice, * License. You may obtain a copy of the License at:
* this list of conditions and the following disclaimer in the documentation * opensource.org/licenses/BSD-3-Clause
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ******************************************************************************
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/ */
#ifndef MBED_CMSIS_NVIC_H #ifndef MBED_CMSIS_NVIC_H
#define MBED_CMSIS_NVIC_H #define MBED_CMSIS_NVIC_H
// CORE: 16 vectors (= 64 bytes from 0x00 to 0x3F) #if !defined(MBED_ROM_START)
// MCU Peripherals: 81 vectors #define MBED_ROM_START 0x8000000
// Total: 388 bytes to be reserved in RAM (see scatter file) #endif
#if !defined(MBED_ROM_SIZE)
#define MBED_ROM_SIZE 0x100000 // 1.0 MB
#endif
#if !defined(MBED_RAM_START)
#define MBED_RAM_START 0x20000000
#endif
#if !defined(MBED_RAM_SIZE)
#define MBED_RAM_SIZE 0x20000 // 128 KB
#endif
#define NVIC_NUM_VECTORS 97 #define NVIC_NUM_VECTORS 97
#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Vectors positioned at start of RAM #define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_START
#endif #endif

10
targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/system_clock.c
View File

@ -147,6 +147,11 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
regarding system frequency refer to product datasheet. */ regarding system frequency refer to product datasheet. */
__HAL_RCC_PWR_CLK_ENABLE(); __HAL_RCC_PWR_CLK_ENABLE();
// Select HSI as system clock source to allow modification of the PLL configuration
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
// Enable HSE oscillator and activate PLL with HSE as source // Enable HSE oscillator and activate PLL with HSE as source
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
if (bypass == 0) { if (bypass == 0) {
@ -194,6 +199,11 @@ uint8_t SetSysClock_PLL_HSI(void)
regarding system frequency refer to product datasheet. */ regarding system frequency refer to product datasheet. */
__HAL_RCC_PWR_CLK_ENABLE(); __HAL_RCC_PWR_CLK_ENABLE();
// Select HSI as system clock source to allow modification of the PLL configuration
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
RCC_OscInitStruct.HSIState = RCC_HSI_ON; RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;