Target_Atmel: Add ARM_LIB_STACK and ARM_LIB_HEAP section

Instead of user defined symbols in assembly files or C files,
use linker scripts to add heap and stack - this is inconsistent
with ARM std linker scripts

targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device/TOOLCHAIN_ARM_MICRO/SAMD21G18A.sct

@@ -1,19 +1,44 @@
+#! armcc -E
+
 ;SAMD21G18A
 ; 256KB FLASH (0x40000) @ 0x000000000
-;2KB RAM (0x8000) @ 0x20000000
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START            0x00000000
+#endif
 
+; SAMD21G18A: 256KB FLASH (0x40000)
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE             0x40000
+#endif
 
-;SAMD21G18A: 256KB FLASH (0x40000) + 32KB RAM (0x8000)
+; 32KB RAM (0x8000) @ 0x20000000
-LR_IROM1 0x00000000 0x40000  {    ; load region size_region
+#define MBED_RAM_START              0x20000000
-    ER_IROM1 0x00000000 0x40000  {  ; load address = execution address 
+#define MBED_RAM_SIZE               0x8000
+
+#if !defined(MBED_BOOT_STACK_SIZE)
+  #define MBED_BOOT_STACK_SIZE      0x400
+#endif
+
+; [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4 +0x4) 8-byte alignment
+#define VECTOR_SIZE                 0xB8
+
+#define RAM_FIXED_SIZE              (MBED_BOOT_STACK_SIZE+VECTOR_SIZE)
+
+LR_IROM1  MBED_APP_START  MBED_APP_SIZE  {    ; load region size_region
+
+  ER_IROM1  MBED_APP_START  MBED_APP_SIZE  {  ; load address = execution address
    *.o (RESET, +First)
    *(InRoot$$Sections)
    .ANY (+RO)
   }
 
-    ; [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4+0x4) 8-byte alignment
+  RW_IRAM1  (MBED_RAM_START+VECTOR_SIZE)  (MBED_RAM_SIZE-VECTOR_SIZE)  {  ; RW data
-    RW_IRAM1 (0x20000000+0xB8) (0x8000-0xB8)  {  ; RW data
    .ANY (+RW +ZI)
   }
 
+  ARM_LIB_HEAP  AlignExpr(+0, 16)  EMPTY  (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16))  {
+  }
+
+  ARM_LIB_STACK  (MBED_RAM_START+MBED_RAM_SIZE)  EMPTY  -MBED_BOOT_STACK_SIZE { ; stack
+  }
 }

targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device/TOOLCHAIN_ARM_MICRO/SAMD21J18A.sct

@@ -1,19 +1,44 @@
+#! armcc -E
+
 ;SAMD21J18A
 ; 256KB FLASH (0x40000) @ 0x000000000
-;2KB RAM (0x8000) @ 0x20000000
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START            0x00000000
+#endif
 
+; SAMD21J18A: 256KB FLASH (0x40000)
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE             0x40000
+#endif
 
-;SAMD21J18A: 256KB FLASH (0x40000) + 32KB RAM (0x8000)
+; 32KB RAM (0x8000) @ 0x20000000
-LR_IROM1 0x00000000 0x40000  {    ; load region size_region
+#define MBED_RAM_START              0x20000000
-    ER_IROM1 0x00000000 0x40000  {  ; load address = execution address 
+#define MBED_RAM_SIZE               0x8000
+
+#if !defined(MBED_BOOT_STACK_SIZE)
+  #define MBED_BOOT_STACK_SIZE      0x400
+#endif
+
+; [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4 +0x4) 8-byte alignment
+#define VECTOR_SIZE                 0xB8
+
+#define RAM_FIXED_SIZE              (MBED_BOOT_STACK_SIZE+VECTOR_SIZE)
+
+LR_IROM1  MBED_APP_START  MBED_APP_SIZE  {    ; load region size_region
+
+  ER_IROM1  MBED_APP_START  MBED_APP_SIZE  {  ; load address = execution address
    *.o (RESET, +First)
    *(InRoot$$Sections)
    .ANY (+RO)
   }
 
-    ; [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4 +0x4) 8-byte alignment
+  RW_IRAM1  (MBED_RAM_START+VECTOR_SIZE)  (MBED_RAM_SIZE-VECTOR_SIZE)  {  ; RW data
-    RW_IRAM1 (0x20000000+0xB8) (0x8000-0xB8)  {  ; RW data
    .ANY (+RW +ZI)
   }
 
+  ARM_LIB_HEAP  AlignExpr(+0, 16)  EMPTY  (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16))  {
+  }
+
+  ARM_LIB_STACK  (MBED_RAM_START+MBED_RAM_SIZE)  EMPTY  -MBED_BOOT_STACK_SIZE { ; stack
+  }
 }

targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device/TOOLCHAIN_ARM_MICRO/SAML21J18A.sct

@@ -1,29 +1,44 @@
-;
+#! armcc -E
-SAML21J18A
-;
-256KB FLASH (0x40000) @ 0x000000000
-;
-2KB RAM (0x8000) @ 0x20000000
 
+;SAMD21J18A
+; 256KB FLASH (0x40000) @ 0x000000000
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START            0x00000000
+#endif
 
-;
+; SAMD21J18A: 256KB FLASH (0x40000)
-SAML21J18A: 256KB FLASH (0x40000) + 32KB RAM (0x8000)
+#if !defined(MBED_APP_SIZE)
-LR_IROM1 0x00000000 0x40000  {    ;
+  #define MBED_APP_SIZE             0x40000
-    load region size_region
+#endif
-    ER_IROM1 0x00000000 0x40000  {  ;
+
-                                    load address = execution address
+; 32KB RAM (0x8000) @ 0x20000000
+#define MBED_RAM_START              0x20000000
+#define MBED_RAM_SIZE               0x8000
+
+#if !defined(MBED_BOOT_STACK_SIZE)
+  #define MBED_BOOT_STACK_SIZE      0x400
+#endif
+
+; [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4 +0x4) 8-byte alignment
+#define VECTOR_SIZE                 0xB8
+
+#define RAM_FIXED_SIZE              (MBED_BOOT_STACK_SIZE+VECTOR_SIZE)
+
+LR_IROM1  MBED_APP_START  MBED_APP_SIZE  {    ; load region size_region
+
+  ER_IROM1  MBED_APP_START  MBED_APP_SIZE  {  ; load address = execution address
    *.o (RESET, +First)
    *(InRoot$$Sections)
    .ANY (+RO)
   }
 
-    ;
+  RW_IRAM1  (MBED_RAM_START+VECTOR_SIZE)  (MBED_RAM_SIZE-VECTOR_SIZE)  {  ; RW data
-    [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4+0x4) 8-byte alignment
-            RW_IRAM1 (0x20000000+0xB8) (0x8000-0xB8)
-    {
-        ;
-        RW data
    .ANY (+RW +ZI)
   }
 
+  ARM_LIB_HEAP  AlignExpr(+0, 16)  EMPTY  (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16))  {
+  }
+
+  ARM_LIB_STACK  (MBED_RAM_START+MBED_RAM_SIZE)  EMPTY  -MBED_BOOT_STACK_SIZE { ; stack
+  }
 }

targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device/TOOLCHAIN_ARM_MICRO/SAMR21G18A.sct

@@ -1,19 +1,44 @@
+#! armcc -E
+
 ;SAMR21G18A
 ; 256KB FLASH (0x40000) @ 0x000000000
-;2KB RAM (0x8000) @ 0x20000000
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START            0x00000000
+#endif
 
+; SAMR21G18A: 256KB FLASH (0x40000)
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE             0x40000
+#endif
 
-;SAMR21G18A: 256KB FLASH (0x40000) + 32KB RAM (0x8000)
+; 32KB RAM (0x8000) @ 0x20000000
-LR_IROM1 0x00000000 0x40000  {    ; load region size_region
+#define MBED_RAM_START              0x20000000
-    ER_IROM1 0x00000000 0x40000  {  ; load address = execution address 
+#define MBED_RAM_SIZE               0x8000
+
+#if !defined(MBED_BOOT_STACK_SIZE)
+  #define MBED_BOOT_STACK_SIZE      0x400
+#endif
+
+; [RAM] Vector table dynamic copy: 44 vectors * 4 bytes = (0xB0) - alignment
+#define VECTOR_SIZE                 0xB0
+
+#define RAM_FIXED_SIZE              (MBED_BOOT_STACK_SIZE+VECTOR_SIZE)
+
+LR_IROM1  MBED_APP_START  MBED_APP_SIZE  {    ; load region size_region
+
+  ER_IROM1  MBED_APP_START  MBED_APP_SIZE  {  ; load address = execution address
    *.o (RESET, +First)
    *(InRoot$$Sections)
    .ANY (+RO)
   }
 
-    ; [RAM] Vector table dynamic copy: 44 vectors * 4 bytes = (0xB0) - alignment
+  RW_IRAM1  (MBED_RAM_START+VECTOR_SIZE)  (MBED_RAM_SIZE-VECTOR_SIZE)  {  ; RW data
-    RW_IRAM1 (0x20000000+0xB0) (0x8000-0xB0)  {  ; RW data
    .ANY (+RW +ZI)
   }
 
+  ARM_LIB_HEAP  AlignExpr(+0, 16)  EMPTY  (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16))  {
+  }
+
+  ARM_LIB_STACK  (MBED_RAM_START+MBED_RAM_SIZE)  EMPTY  -MBED_BOOT_STACK_SIZE { ; stack
+  }
 }