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Enable SDIO DeepSleep Callback

pull/11367/head
Kyle Kearney 2019-08-23 16:54:21 -07:00
parent 0164ddcc80
commit ad6e833450
21 changed files with 1052 additions and 602 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

78
targets/TARGET_Cypress/TARGET_PSOC6/PinNamesTypes.h
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@ -19,14 +19,83 @@
#ifndef MBED_PINNAMESTYPES_H
#define MBED_PINNAMESTYPES_H
#include "cmsis.h"
#include "cyhal_gpio.h"
#include "cybsp_types.h"
// Pin Modes
#define PullNone CYHAL_GPIO_DRIVE_STRONG
#define PullDefault CYHAL_GPIO_DRIVE_ANALOG
#define PullDefault CYHAL_GPIO_DRIVE_NONE
#define PullDown CYHAL_GPIO_DRIVE_PULLDOWN
#define PullUp CYHAL_GPIO_DRIVE_PULLUP
// Arduino Headers
#ifdef CYBSP_A0
#define A0 CYBSP_A0
#endif
#ifdef CYBSP_A1
#define A1 CYBSP_A1
#endif
#ifdef CYBSP_A2
#define A2 CYBSP_A2
#endif
#ifdef CYBSP_A3
#define A3 CYBSP_A3
#endif
#ifdef CYBSP_A4
#define A4 CYBSP_A4
#endif
#ifdef CYBSP_A5
#define A5 CYBSP_A5
#endif
#ifdef CYBSP_D0
#define D0 CYBSP_D0
#endif
#ifdef CYBSP_D1
#define D1 CYBSP_D1
#endif
#ifdef CYBSP_D2
#define D2 CYBSP_D2
#endif
#ifdef CYBSP_D3
#define D3 CYBSP_D3
#endif
#ifdef CYBSP_D4
#define D4 CYBSP_D4
#endif
#ifdef CYBSP_D5
#define D5 CYBSP_D5
#endif
#ifdef CYBSP_D6
#define D6 CYBSP_D6
#endif
#ifdef CYBSP_D7
#define D7 CYBSP_D7
#endif
#ifdef CYBSP_D8
#define D8 CYBSP_D8
#endif
#ifdef CYBSP_D9
#define D9 CYBSP_D9
#endif
#ifdef CYBSP_D10
#define D10 CYBSP_D10
#endif
#ifdef CYBSP_D11
#define D11 CYBSP_D11
#endif
#ifdef CYBSP_D12
#define D12 CYBSP_D12
#endif
#ifdef CYBSP_D13
#define D13 CYBSP_D13
#endif
#ifdef CYBSP_D14
#define D14 CYBSP_D14
#endif
#ifdef CYBSP_D15
#define D15 CYBSP_D15
#endif
#ifdef __cplusplus
extern "C" {
#endif
@ -37,6 +106,11 @@ typedef enum {
} PinDirection;
typedef cyhal_gpio_drive_mode_t PinMode;
typedef cyhal_gpio_t PinName;
static inline PinName cyhal_gpio_to_rtos(cyhal_gpio_t pin)
{
return pin;
}
#ifdef __cplusplus
}

94
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/PinNames.h
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@ -20,39 +20,8 @@
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#include "PinNamesTypes.h"
#include "PortNames.h"
#include "cyhal_pin_package.h"
#include "cyhal_utils.h"
typedef cyhal_gpio_t PinName;
// Arduino connector namings
#define A0 P10_0
#define A1 P10_1
#define A2 P10_2
#define A3 P10_3
#define A4 P10_4
#define A5 P10_5
#define D0 P5_0
#define D1 P5_1
#define D2 P5_2
#define D3 P5_3
#define D4 P5_4
#define D5 P5_5
#define D6 P5_6
#define D7 P0_2
#define D8 P13_0
#define D9 P13_1
#define D10 P12_3
#define D11 P12_0
#define D12 P12_1
#define D13 P12_2
#define D14 P6_1
#define D15 P6_0
// Generic signal names
@ -64,46 +33,23 @@ typedef cyhal_gpio_t PinName;
#define UART_RTS P5_2
#define UART_CTS P5_3
#define SPI_MOSI P12_0
#define SPI_MISO P12_1
#define SPI_CLK P12_2
#define SPI_CS P12_4
#define UART_RX P5_0
#define UART_TX P5_1
#define UART_RTS P5_2
#define UART_CTS P5_3
#define BT_UART_RX P3_0
#define BT_UART_TX P3_1
#define BT_UART_CTS P3_3
#define BT_UART_RTS P3_2
#define BT_PIN_POWER P3_4
#define BT_PIN_HOST_WAKE P3_5
#define BT_PIN_DEVICE_WAKE P4_0
// Reset pin unavailable
#define SWITCH2 P0_4
#define LED1 P13_7
#define LED2 NC
#define LED3 NC
#define LED4 NC
#define LED1 P1_1
#define LED2 P0_5
#define LED3 P7_3
#define LED4 P1_5
#define LED5 P11_1
#define LED_RED LED1
#define LED_GREEN LED2
#define LED_BLUE LED3
// Reset pin unavailable
#define SWITCH2 P0_4
#define SWITCH4 P1_4
#define USER_BUTTON SWITCH2
#define BUTTON1 USER_BUTTON
#define BUTTON2 SWITCH4
#define PDM_DATA P10_5
#define PDM_CLK P10_4
#define THERM_OUT_1 P10_1
#define THERM_OUT_2 P10_2
#define THERM_OUT THERM_OUT_1
#define THERM_VDD P10_3
#define THERM_GND P10_0
#define CARD_DETECT_1 P13_5
#define CARD_DETECT_2 P12_1
#define CARD_DETECT_1 P13_7
#define CARD_DETECT CARD_DETECT_1
#define SD_CMD P12_4
#define SD_CLK P12_5
@ -132,23 +78,7 @@ typedef cyhal_gpio_t PinName;
#define STDIO_UART_CTS UART_CTS
#define STDIO_UART_RTS UART_RTS
#define CY_STDIO_UART_RX STDIO_UART_RX
#define CY_STDIO_UART_TX STDIO_UART_TX
#define CY_STDIO_UART_CTS STDIO_UART_CTS
#define CY_STDIO_UART_RTS STDIO_UART_RTS
#define CY_BT_UART_RX BT_UART_RX
#define CY_BT_UART_TX BT_UART_TX
#define CY_BT_UART_CTS BT_UART_CTS
#define CY_BT_UART_RTS BT_UART_RTS
#define CY_BT_PIN_POWER BT_PIN_POWER
#define CY_BT_PIN_HOST_WAKE BT_PIN_HOST_WAKE
#define CY_BT_PIN_DEVICE_WAKE BT_PIN_DEVICE_WAKE
#define USBTX UART_TX
#define USBRX UART_RX
#define CY_WIFI_HOST_WAKE P2_7
#endif

45
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/cybsp_types.h
View File

@ -23,14 +23,6 @@
* limitations under the License.
*******************************************************************************/
/**
* \addtogroup group_bsp_cy8ckit_062s2_43012 CY8CKIT-062S2-43012
* \ingroup group_bsp
* \{
* \defgroup group_bsp_cy8ckit_062s2_43012_macros Macros
* \defgroup group_bsp_cy8ckit_062s2_43012_enums Enumerated Types
*/
#pragma once
#include "cyhal.h"
@ -39,9 +31,8 @@
extern "C" {
#endif
/**
* \addtogroup group_bsp_cy8ckit_062s2_43012_macros
* \addtogroup group_bsp_pins Pin Mappings
* \{
*/
@ -98,18 +89,25 @@ extern "C" {
#define CYBSP_WCO_OUT P0_1
/** Pin: WIFI SDIO D0 */
/* Corresponds to: ioss[0].port[2].pin[0], sdhc[0] */
#define CYBSP_WIFI_SDIO_D0 P2_0
/** Pin: WIFI SDIO D1 */
/* Corresponds to: ioss[0].port[2].pin[1], sdhc[0] */
#define CYBSP_WIFI_SDIO_D1 P2_1
/** Pin: WIFI SDIO D2 */
/* Corresponds to: ioss[0].port[2].pin[2], sdhc[0] */
#define CYBSP_WIFI_SDIO_D2 P2_2
/** Pin: WIFI SDIO D3 */
/* Corresponds to: ioss[0].port[2].pin[3], sdhc[0] */
#define CYBSP_WIFI_SDIO_D3 P2_3
/** Pin: WIFI SDIO CMD */
/* Corresponds to: ioss[0].port[2].pin[4], sdhc[0] */
#define CYBSP_WIFI_SDIO_CMD P2_4
/** Pin: WIFI SDIO CLK */
/* Corresponds to: ioss[0].port[2].pin[5], sdhc[0] */
#define CYBSP_WIFI_SDIO_CLK P2_5
/** Pin: WIFI ON */
/* Corresponds to: ioss[0].port[2].pin[6], sdhc[0] */
#define CYBSP_WIFI_WL_REG_ON P2_6
/** Pin: WIFI Host Wakeup */
#define CYBSP_WIFI_HOST_WAKE P4_1
@ -125,17 +123,21 @@ extern "C" {
/** Pin: BT Power */
#define CYBSP_BT_POWER P3_4
/** Pin: BT Host Wakeup */
#define CYBSP_BT_HOST_WAKE P3_5
#define CYBSP_BT_HOST_WAKE P4_0
/** Pin: BT Device Wakeup */
#define CYBSP_BT_DEVICE_WAKE P4_0
#define CYBSP_BT_DEVICE_WAKE P3_5
/** Pin: UART RX */
/* Corresponds to: ioss[0].port[5].pin[0], scb[5] */
#define CYBSP_DEBUG_UART_RX P5_0
/** Pin: UART TX */
/* Corresponds to: ioss[0].port[5].pin[1], scb[5] */
#define CYBSP_DEBUG_UART_TX P5_1
/** Pin: UART RX */
/* Corresponds to: ioss[0].port[5].pin[2], scb[5] */
#define CYBSP_DEBUG_UART_RTS P5_2
/** Pin: UART TX */
/* Corresponds to: ioss[0].port[5].pin[3], scb[5] */
#define CYBSP_DEBUG_UART_CTS P5_3
/** Pin: I2C SCL */
@ -150,8 +152,8 @@ extern "C" {
/** Pin: SWDCK */
#define CYBSP_SWDCK P6_7
/** Pin: CapSesnse TX */
#define CYBSP_CSD_TX P1_0
/** Pin: CapSesnse RX */
#define CYBSP_CSD_RX P1_0
/** Pin: CapSesnse CINA */
#define CYBSP_CINA P7_1
/** Pin: CapSesnse CINB */
@ -218,10 +220,10 @@ extern "C" {
#define SW4 P1_4
/** \} group_bsp_cy8ckit_062s2_43012_macros */
/** \} group_bsp_cy8ckit_pins */
/**
* \addtogroup group_bsp_cy8ckit_062s2_43012_enums
* \addtogroup group_bsp_enums Enumerated Types
* \{
*/
@ -247,10 +249,15 @@ typedef enum
CYBSP_LED_RGB_GREEN = LED5_RGB_G,
CYBSP_LED_RGB_BLUE = LED5_RGB_B,
/* Corresponds to: ioss[0].port[11].pin[1] */
CYBSP_USER_LED1 = LED9_R,
/* Corresponds to: ioss[0].port[1].pin[5] */
CYBSP_USER_LED2 = LED8_O,
/* Corresponds to: ioss[0].port[1].pin[1] */
CYBSP_USER_LED3 = CYBSP_LED_RGB_RED,
/* Corresponds to: ioss[0].port[0].pin[5] */
CYBSP_USER_LED4 = CYBSP_LED_RGB_GREEN,
/* Corresponds to: ioss[0].port[7].pin[3] */
CYBSP_USER_LED5 = CYBSP_LED_RGB_BLUE,
CYBSP_USER_LED = CYBSP_USER_LED1,
} cybsp_led_t;
@ -259,16 +266,16 @@ typedef enum
/** Enum defining the different user buttons available on the board. */
typedef enum
{
/* Corresponds to: ioss[0].port[0].pin[4] */
CYBSP_USER_BTN1 = SW2,
/* Corresponds to: ioss[0].port[1].pin[4] */
CYBSP_USER_BTN2 = SW4,
CYBSP_USER_BTN = CYBSP_USER_BTN1,
} cybsp_btn_t;
/** \} group_bsp_cy8ckit_062s2_43012_enums */
/** \} group_bsp_enums */
#if defined(__cplusplus)
}
#endif
/** \} group_bsp_cy8ckit_062s2_43012 */

14
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/PeripheralPins.c
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@ -91,7 +91,9 @@ const PinMap PinMap_I2C_SCL[] = {
{P1_0, I2C_7, CYHAL_PIN_OD_FUNCTION(P1_0_SCB7_I2C_SCL)},
{P5_0, I2C_5, CYHAL_PIN_OD_FUNCTION(P5_0_SCB5_I2C_SCL)},
{P6_0, I2C_3, CYHAL_PIN_OD_FUNCTION(P6_0_SCB3_I2C_SCL)},
{P6_0, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_0_SCB8_I2C_SCL)},
{P6_4, I2C_6, CYHAL_PIN_OD_FUNCTION(P6_4_SCB6_I2C_SCL)},
{P6_4, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_4_SCB8_I2C_SCL)},
{P7_0, I2C_4, CYHAL_PIN_OD_FUNCTION(P7_0_SCB4_I2C_SCL)},
{P8_0, I2C_4, CYHAL_PIN_OD_FUNCTION(P8_0_SCB4_I2C_SCL)},
{P9_0, I2C_2, CYHAL_PIN_OD_FUNCTION(P9_0_SCB2_I2C_SCL)},
@ -106,7 +108,9 @@ const PinMap PinMap_I2C_SDA[] = {
{P1_1, I2C_7, CYHAL_PIN_OD_FUNCTION(P1_1_SCB7_I2C_SDA)},
{P5_1, I2C_5, CYHAL_PIN_OD_FUNCTION(P5_1_SCB5_I2C_SDA)},
{P6_1, I2C_3, CYHAL_PIN_OD_FUNCTION(P6_1_SCB3_I2C_SDA)},
{P6_1, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_1_SCB8_I2C_SDA)},
{P6_5, I2C_6, CYHAL_PIN_OD_FUNCTION(P6_5_SCB6_I2C_SDA)},
{P6_5, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_5_SCB8_I2C_SDA)},
{P7_1, I2C_4, CYHAL_PIN_OD_FUNCTION(P7_1_SCB4_I2C_SDA)},
{P8_1, I2C_4, CYHAL_PIN_OD_FUNCTION(P8_1_SCB4_I2C_SDA)},
{P9_1, I2C_2, CYHAL_PIN_OD_FUNCTION(P9_1_SCB2_I2C_SDA)},
@ -125,7 +129,9 @@ const PinMap PinMap_SPI_MOSI[] = {
{P1_0, SPI_7, CYHAL_PIN_OUT_FUNCTION(P1_0_SCB7_SPI_MOSI)},
{P5_0, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_0_SCB5_SPI_MOSI)},
{P6_0, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_0_SCB3_SPI_MOSI)},
{P6_0, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_0_SCB8_SPI_MOSI)},
{P6_4, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB6_SPI_MOSI)},
{P6_4, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB8_SPI_MOSI)},
{P7_0, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_0_SCB4_SPI_MOSI)},
{P8_0, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_0_SCB4_SPI_MOSI)},
{P9_0, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_0_SCB2_SPI_MOSI)},
@ -140,7 +146,9 @@ const PinMap PinMap_SPI_MISO[] = {
{P1_1, SPI_7, CYHAL_PIN_IN_FUNCTION(P1_1_SCB7_SPI_MISO)},
{P5_1, SPI_5, CYHAL_PIN_IN_FUNCTION(P5_1_SCB5_SPI_MISO)},
{P6_1, SPI_3, CYHAL_PIN_IN_FUNCTION(P6_1_SCB3_SPI_MISO)},
{P6_1, SPI_8, CYHAL_PIN_IN_FUNCTION(P6_1_SCB8_SPI_MISO)},
{P6_5, SPI_6, CYHAL_PIN_IN_FUNCTION(P6_5_SCB6_SPI_MISO)},
{P6_5, SPI_8, CYHAL_PIN_IN_FUNCTION(P6_5_SCB8_SPI_MISO)},
{P7_1, SPI_4, CYHAL_PIN_IN_FUNCTION(P7_1_SCB4_SPI_MISO)},
{P8_1, SPI_4, CYHAL_PIN_IN_FUNCTION(P8_1_SCB4_SPI_MISO)},
{P9_1, SPI_2, CYHAL_PIN_IN_FUNCTION(P9_1_SCB2_SPI_MISO)},
@ -155,9 +163,10 @@ const PinMap PinMap_SPI_SCLK[] = {
{P1_2, SPI_7, CYHAL_PIN_OUT_FUNCTION(P1_2_SCB7_SPI_CLK)},
{P5_2, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_2_SCB5_SPI_CLK)},
{P6_2, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB3_SPI_CLK)},
{P6_2, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB8_SPI_CLK)},
{P6_6, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB6_SPI_CLK)},
{P6_6, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB8_SPI_CLK)},
{P7_2, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_2_SCB4_SPI_CLK)},
{P8_2, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_2_SCB4_SPI_CLK)},
{P9_2, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_2_SCB2_SPI_CLK)},
{P10_2, SPI_1, CYHAL_PIN_OUT_FUNCTION(P10_2_SCB1_SPI_CLK)},
@ -170,7 +179,9 @@ const PinMap PinMap_SPI_SSEL[] = {
{P1_3, SPI_7, CYHAL_PIN_OUT_FUNCTION(P1_3_SCB7_SPI_SELECT0)},
{P5_3, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_3_SCB5_SPI_SELECT0)},
{P6_3, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB3_SPI_SELECT0)},
{P6_3, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB8_SPI_SELECT0)},
{P6_7, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB6_SPI_SELECT0)},
{P6_7, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB8_SPI_SELECT0)},
{P7_3, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_3_SCB4_SPI_SELECT0)},
{P8_3, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_3_SCB4_SPI_SELECT0)},
{P9_3, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_3_SCB2_SPI_SELECT0)},
@ -360,7 +371,6 @@ const PinMap PinMap_ADC[] = {
#if DEVICE_ANALOGOUT
const PinMap PinMap_DAC[] = {
{P9_6, DAC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
{P10_5, DAC_0, CY_GPIO_CFG_CREATE(HSIOM_SEL_AMUXA, CY_GPIO_DM_ANALOG)}, // CTDAC connects to the P10_5 pin through the AMUXA bus
{NC, NC, 0}
};
#endif // DEVICE_ANALOGIN

38
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/PinNames.h
View File

@ -20,38 +20,8 @@
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#include "PinNamesTypes.h"
#include "PortNames.h"
#include "cyhal_pin_package.h"
#include "cyhal_utils.h"
typedef cyhal_gpio_t PinName;
// Arduino connector namings
#define A0 P10_0
#define A1 P10_1
#define A2 P10_2
#define A3 P10_3
#define A4 P10_4
#define A5 P10_5
#define D0 P5_0
#define D1 P5_1
#define D2 P5_2
#define D3 P5_3
#define D4 P5_4
#define D5 P5_5
#define D6 P5_6
#define D7 P0_2
#define D8 P13_0
#define D9 P13_1
#define D10 P12_3
#define D11 P12_0
#define D12 P12_1
#define D13 P12_2
#define D14 P6_1
#define D15 P6_0
// Generic signal names
@ -68,17 +38,16 @@ typedef cyhal_gpio_t PinName;
#define UART_RTS P5_2
#define UART_CTS P5_3
#define SWITCH2 P0_4
#define LED1 P0_3
#define LED2 P1_1
#define LED3 P11_1
#define LED4 P1_5
#define LED5 P13_7
#define LED_RED LED1
#define LED_BLUE LED3
#define LED_GREEN LED2
#define SWITCH2 P0_4
#define USER_BUTTON SWITCH2
#define BUTTON1 USER_BUTTON
@ -102,11 +71,6 @@ typedef cyhal_gpio_t PinName;
#define STDIO_UART_CTS UART_CTS
#define STDIO_UART_RTS UART_RTS
#define CY_STDIO_UART_RX STDIO_UART_RX
#define CY_STDIO_UART_TX STDIO_UART_TX
#define CY_STDIO_UART_CTS STDIO_UART_CTS
#define CY_STDIO_UART_RTS STDIO_UART_RTS
#define USBTX UART_TX
#define USBRX UART_RX

74
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/cybsp_types.h Normal file → Executable file
View File

@ -23,27 +23,65 @@
* limitations under the License.
*******************************************************************************/
/**
* \addtogroup group_bsp_cy8ckit_062_ble CY8CKIT-062-BLE
* \ingroup group_bsp
* \{
* \defgroup group_bsp_cy8ckit_062_ble_macros Macros
* \defgroup group_bsp_cy8ckit_062_ble_enums Enumerated Types
*/
#pragma once
#include "cyhal.h"
#include "cyhal_pin_package.h"
#if defined(__cplusplus)
extern "C" {
#endif
/**
* \addtogroup group_bsp_cy8ckit_062_ble_macros
* \addtogroup group_bsp_pins Pin Mappings
* \{
*/
// Arduino connector namings
/** Arduino A0 */
#define CYBSP_A0 P10_0
/** Arduino A1 */
#define CYBSP_A1 P10_1
/** Arduino A2 */
#define CYBSP_A2 P10_2
/** Arduino A3 */
#define CYBSP_A3 P10_3
/** Arduino A4 */
#define CYBSP_A4 P10_4
/** Arduino A5 */
#define CYBSP_A5 P10_5
/** Arduino D0 */
#define CYBSP_D0 P5_0
/** Arduino D1 */
#define CYBSP_D1 P5_1
/** Arduino D2 */
#define CYBSP_D2 P5_2
/** Arduino D3 */
#define CYBSP_D3 P5_3
/** Arduino D4 */
#define CYBSP_D4 P5_4
/** Arduino D5 */
#define CYBSP_D5 P5_5
/** Arduino D6 */
#define CYBSP_D6 P5_6
/** Arduino D7 */
#define CYBSP_D7 P0_2
/** Arduino D8 */
#define CYBSP_D8 P13_0
/** Arduino D9 */
#define CYBSP_D9 P13_1
/** Arduino D10 */
#define CYBSP_D10 P12_3
/** Arduino D11 */
#define CYBSP_D11 P12_0
/** Arduino D12 */
#define CYBSP_D12 P12_1
/** Arduino D13 */
#define CYBSP_D13 P12_2
/** Arduino D14 */
#define CYBSP_D14 P6_1
/** Arduino D15 */
#define CYBSP_D15 P6_0
// Generic signal names
/** Pin: WCO input */
#define CYBSP_WCO_IN P0_0
@ -51,8 +89,10 @@ extern "C" {
#define CYBSP_WCO_OUT P0_1
/** Pin: UART RX */
/* Corresponds to: ioss[0].port[5].pin[0], scb[5] */
#define CYBSP_DEBUG_UART_RX P5_0
/** Pin: UART TX */
/* Corresponds to: ioss[0].port[5].pin[1], scb[5] */
#define CYBSP_DEBUG_UART_TX P5_1
/** Pin: I2C SCL */
@ -103,10 +143,10 @@ extern "C" {
/** Pin: QUAD SPI SCK */
#define CYBSP_QSPI_SCK P11_7
/** \} group_bsp_cy8ckit_062_ble_macros */
/** \} group_bsp_pins */
/**
* \addtogroup group_bsp_cy8ckit_062_ble_enums
* \addtogroup group_bsp_enums Enumerated Types
* \{
*/
@ -133,10 +173,15 @@ typedef enum
CYBSP_LED_RGB_GREEN = P1_1,
CYBSP_LED_RGB_BLUE = P11_1,
/* Corresponds to: ioss[0].port[1].pin[5] */
CYBSP_USER_LED1 = CYBSP_LED8,
/* Corresponds to: ioss[0].port[13].pin[7] */
CYBSP_USER_LED2 = CYBSP_LED9,
/* Corresponds to: ioss[0].port[0].pin[3] */
CYBSP_USER_LED3 = CYBSP_LED_RGB_RED,
/* Corresponds to: ioss[0].port[1].pin[1] */
CYBSP_USER_LED4 = CYBSP_LED_RGB_GREEN,
/* Corresponds to: ioss[0].port[11].pin[1] */
CYBSP_USER_LED5 = CYBSP_LED_RGB_BLUE,
CYBSP_USER_LED = CYBSP_USER_LED1,
} cybsp_led_t;
@ -146,14 +191,13 @@ typedef enum
{
CYBSP_SW2 = P0_4,
/* Corresponds to: ioss[0].port[0].pin[4] */
CYBSP_USER_BTN1 = CYBSP_SW2,
CYBSP_USER_BTN = CYBSP_USER_BTN1,
} cybsp_btn_t;
/** \} group_bsp_cy8ckit_062_ble_enums */
/** \} group_bsp_enums */
#if defined(__cplusplus)
}
#endif
/** \} group_bsp_cy8ckit_062_ble */

13
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/PeripheralPins.c
View File

@ -104,7 +104,9 @@ const PinMap PinMap_I2C_SCL[] = {
{P4_0, I2C_7, CYHAL_PIN_OD_FUNCTION(P4_0_SCB7_I2C_SCL)},
{P5_0, I2C_5, CYHAL_PIN_OD_FUNCTION(P5_0_SCB5_I2C_SCL)},
{P6_0, I2C_3, CYHAL_PIN_OD_FUNCTION(P6_0_SCB3_I2C_SCL)},
{P6_0, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_0_SCB8_I2C_SCL)},
{P6_4, I2C_6, CYHAL_PIN_OD_FUNCTION(P6_4_SCB6_I2C_SCL)},
{P6_4, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_4_SCB8_I2C_SCL)},
{P7_0, I2C_4, CYHAL_PIN_OD_FUNCTION(P7_0_SCB4_I2C_SCL)},
{P8_0, I2C_4, CYHAL_PIN_OD_FUNCTION(P8_0_SCB4_I2C_SCL)},
{P9_0, I2C_2, CYHAL_PIN_OD_FUNCTION(P9_0_SCB2_I2C_SCL)},
@ -122,7 +124,9 @@ const PinMap PinMap_I2C_SDA[] = {
{P4_1, I2C_7, CYHAL_PIN_OD_FUNCTION(P4_1_SCB7_I2C_SDA)},
{P5_1, I2C_5, CYHAL_PIN_OD_FUNCTION(P5_1_SCB5_I2C_SDA)},
{P6_1, I2C_3, CYHAL_PIN_OD_FUNCTION(P6_1_SCB3_I2C_SDA)},
{P6_1, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_1_SCB8_I2C_SDA)},
{P6_5, I2C_6, CYHAL_PIN_OD_FUNCTION(P6_5_SCB6_I2C_SDA)},
{P6_5, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_5_SCB8_I2C_SDA)},
{P7_1, I2C_4, CYHAL_PIN_OD_FUNCTION(P7_1_SCB4_I2C_SDA)},
{P8_1, I2C_4, CYHAL_PIN_OD_FUNCTION(P8_1_SCB4_I2C_SDA)},
{P9_1, I2C_2, CYHAL_PIN_OD_FUNCTION(P9_1_SCB2_I2C_SDA)},
@ -144,7 +148,9 @@ const PinMap PinMap_SPI_MOSI[] = {
{P4_0, SPI_7, CYHAL_PIN_OUT_FUNCTION(P4_0_SCB7_SPI_MOSI)},
{P5_0, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_0_SCB5_SPI_MOSI)},
{P6_0, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_0_SCB3_SPI_MOSI)},
{P6_0, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_0_SCB8_SPI_MOSI)},
{P6_4, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB6_SPI_MOSI)},
{P6_4, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB8_SPI_MOSI)},
{P7_0, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_0_SCB4_SPI_MOSI)},
{P8_0, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_0_SCB4_SPI_MOSI)},
{P9_0, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_0_SCB2_SPI_MOSI)},
@ -162,7 +168,9 @@ const PinMap PinMap_SPI_MISO[] = {
{P4_1, SPI_7, CYHAL_PIN_IN_FUNCTION(P4_1_SCB7_SPI_MISO)},
{P5_1, SPI_5, CYHAL_PIN_IN_FUNCTION(P5_1_SCB5_SPI_MISO)},
{P6_1, SPI_3, CYHAL_PIN_IN_FUNCTION(P6_1_SCB3_SPI_MISO)},
{P6_1, SPI_8, CYHAL_PIN_IN_FUNCTION(P6_1_SCB8_SPI_MISO)},
{P6_5, SPI_6, CYHAL_PIN_IN_FUNCTION(P6_5_SCB6_SPI_MISO)},
{P6_5, SPI_8, CYHAL_PIN_IN_FUNCTION(P6_5_SCB8_SPI_MISO)},
{P7_1, SPI_4, CYHAL_PIN_IN_FUNCTION(P7_1_SCB4_SPI_MISO)},
{P8_1, SPI_4, CYHAL_PIN_IN_FUNCTION(P8_1_SCB4_SPI_MISO)},
{P9_1, SPI_2, CYHAL_PIN_IN_FUNCTION(P9_1_SCB2_SPI_MISO)},
@ -179,7 +187,9 @@ const PinMap PinMap_SPI_SCLK[] = {
{P3_2, SPI_2, CYHAL_PIN_OUT_FUNCTION(P3_2_SCB2_SPI_CLK)},
{P5_2, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_2_SCB5_SPI_CLK)},
{P6_2, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB3_SPI_CLK)},
{P6_2, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB8_SPI_CLK)},
{P6_6, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB6_SPI_CLK)},
{P6_6, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB8_SPI_CLK)},
{P7_2, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_2_SCB4_SPI_CLK)},
{P8_2, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_2_SCB4_SPI_CLK)},
{P9_2, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_2_SCB2_SPI_CLK)},
@ -195,7 +205,9 @@ const PinMap PinMap_SPI_SSEL[] = {
{P3_3, SPI_2, CYHAL_PIN_OUT_FUNCTION(P3_3_SCB2_SPI_SELECT0)},
{P5_3, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_3_SCB5_SPI_SELECT0)},
{P6_3, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB3_SPI_SELECT0)},
{P6_3, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB8_SPI_SELECT0)},
{P6_7, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB6_SPI_SELECT0)},
{P6_7, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB8_SPI_SELECT0)},
{P7_3, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_3_SCB4_SPI_SELECT0)},
{P8_3, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_3_SCB4_SPI_SELECT0)},
{P9_3, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_3_SCB2_SPI_SELECT0)},
@ -430,7 +442,6 @@ const PinMap PinMap_ADC[] = {
#if DEVICE_ANALOGOUT
const PinMap PinMap_DAC[] = {
{P9_6, DAC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
{P10_5, DAC_0, CY_GPIO_CFG_CREATE(HSIOM_SEL_AMUXA, CY_GPIO_DM_ANALOG)}, // CTDAC connects to the P10_5 pin through the AMUXA bus
{NC, NC, 0}
};
#endif // DEVICE_ANALOGIN

70
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/PinNames.h
View File

@ -20,38 +20,8 @@
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#include "PinNamesTypes.h"
#include "PortNames.h"
#include "cyhal_pin_package.h"
#include "cyhal_utils.h"
typedef cyhal_gpio_t PinName;
// Arduino connector namings
#define A0 P10_0
#define A1 P10_1
#define A2 P10_2
#define A3 P10_3
#define A4 P10_4
#define A5 P10_5
#define D0 P5_0
#define D1 P5_1
#define D2 P5_2
#define D3 P5_3
#define D4 P5_4
#define D5 P5_5
#define D6 P5_6
#define D7 P0_2
#define D8 P13_0
#define D9 P13_1
#define D10 P12_3
#define D11 P12_0
#define D12 P12_1
#define D13 P12_2
#define D14 P6_1
#define D15 P6_0
// Generic signal names
@ -68,28 +38,17 @@ typedef cyhal_gpio_t PinName;
#define UART_RTS P5_2
#define UART_CTS P5_3
#define BT_UART_RX P3_0
#define BT_UART_TX P3_1
#define BT_UART_CTS P3_3
#define BT_UART_RTS P3_2
#define BT_PIN_POWER P3_4
#define BT_PIN_HOST_WAKE P3_5
#define BT_PIN_DEVICE_WAKE P4_0
// Reset pin unavailable
#define SWITCH2 P0_4
#define LED1 P0_3
#define LED2 P1_1
#define LED3 P11_1
#define LED2 P11_1
#define LED3 P1_1
#define LED4 P1_5
#define LED5 P13_7
#define LED_RED LED1
#define LED_BLUE LED3
#define LED_GREEN LED2
#define LED_BLUE LED2
#define LED_GREEN LED3
// Reset pin unavailable
#define SWITCH2 P0_4
#define USER_BUTTON SWITCH2
#define BUTTON1 USER_BUTTON
@ -113,26 +72,9 @@ typedef cyhal_gpio_t PinName;
#define STDIO_UART_CTS UART_CTS
#define STDIO_UART_RTS UART_RTS
#define CY_STDIO_UART_RX STDIO_UART_RX
#define CY_STDIO_UART_TX STDIO_UART_TX
#define CY_STDIO_UART_CTS STDIO_UART_CTS
#define CY_STDIO_UART_RTS STDIO_UART_RTS
#define CY_BT_UART_RX BT_UART_RX
#define CY_BT_UART_TX BT_UART_TX
#define CY_BT_UART_CTS BT_UART_CTS
#define CY_BT_UART_RTS BT_UART_RTS
#define CY_BT_PIN_POWER BT_PIN_POWER
#define CY_BT_PIN_HOST_WAKE BT_PIN_HOST_WAKE
#define CY_BT_PIN_DEVICE_WAKE BT_PIN_DEVICE_WAKE
#define USBTX UART_TX
#define USBRX UART_RX
#define CY_WIFI_HOST_WAKE P2_7
#define AOUT P9_6
#endif

272
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST.c
View File

@ -28,13 +28,23 @@
extern "C" {
#endif
#ifdef SEMAPHORE
#include "cyabs_rtos.h"
#ifdef CY_RTOS_AWARE
#define NEVER_TIMEOUT ( (uint32_t)0xffffffffUL )
static cy_semaphore_t sdio_transfer_finished_semaphore;
#include "cyabs_rtos.h"
#define NEVER_TIMEOUT ( (uint32_t)0xffffffffUL )
static cy_semaphore_t sdio_transfer_finished_semaphore;
static bool sema_initialized = false;
#endif
/* Backup struct used to store and restore non retention UDB registers */
typedef struct
{
uint32_t CY_SDIO_UDB_WRKMULT_CTL_0;
uint32_t CY_SDIO_UDB_WRKMULT_CTL_1;
uint32_t CY_SDIO_UDB_WRKMULT_CTL_2;
uint32_t CY_SDIO_UDB_WRKMULT_CTL_3;
} stc_sdio_backup_regs_t;
/*Globals Needed for DMA */
/*DMA channel structures*/
@ -61,14 +71,63 @@ static uint8_t crcTable[256];
static uint32_t yCountRemainder;
static uint32_t yCounts;
/* Global value for card interrupt */
static uint8_t pfnCardInt_count = 0;
/*Global structure to store UDB registers */
static stc_sdio_backup_regs_t regs;
static uint32_t udb_initialized = 0;
cy_stc_syspm_callback_params_t sdio_pm_callback_params;
cy_stc_syspm_callback_t sdio_pm_callback_handler;
/* Deep Sleep Mode API Support */
static void SDIO_SaveConfig(void);
static void SDIO_RestoreConfig(void);
/*******************************************************************************
* Function Name: SDIO_DeepSleepCallback
****************************************************************************//**
*
* Callback executed during Deep Sleep entry/exit
*
* \note
* Saves/Restores SDIO UDB registers
*******************************************************************************/
cy_en_syspm_status_t SDIO_DeepSleepCallback(cy_stc_syspm_callback_params_t *params, cy_en_syspm_callback_mode_t mode)
{
cy_en_syspm_status_t status = CY_SYSPM_FAIL;
switch (mode)
{
case CY_SYSPM_CHECK_READY:
case CY_SYSPM_CHECK_FAIL:
status = CY_SYSPM_SUCCESS;
break;
case CY_SYSPM_BEFORE_TRANSITION:
SDIO_SaveConfig();
status = CY_SYSPM_SUCCESS;
break;
case CY_SYSPM_AFTER_TRANSITION:
SDIO_RestoreConfig();
status = CY_SYSPM_SUCCESS;
break;
default:
break;
}
return status;
}
/*******************************************************************************
* Function Name: SDIO_Init
****************************************************************************//**
*
* Initializes the SDIO hardware, and register the callback
* Initializes the SDIO hardware
*
* \param pfuCb
* Pointer to structure that holds pointers to callback function
@ -132,11 +191,6 @@ void SDIO_Init(stc_sdio_irq_cb_t* pfuCb)
SDIO_SetSdClkFrequency(400000);
SDIO_EnableIntClock();
SDIO_EnableSdClk();
/*Initalize the semaphore*/
#ifdef SEMAPHORE
cy_rtos_init_semaphore( &sdio_transfer_finished_semaphore, 1, 1 );
#endif
}
@ -560,41 +614,49 @@ void SDIO_InitDataTransfer(stc_sdio_data_config_t *pstcDataConfig)
*******************************************************************************/
en_sdio_result_t SDIO_SendCommandAndWait(stc_sdio_cmd_t *pstcCmd)
{
/*Store the command and data configurations*/
/* Store the command and data configurations*/
stc_sdio_cmd_config_t stcCmdConfig;
stc_sdio_data_config_t stcDataConfig;
#ifdef SEMAPHORE
en_sdio_result_t result;
#endif
/*variable used for holding timeout value*/
#ifndef SEMAPHORE
uint32_t u32Timeout = 0;
#endif
#ifndef SEMAPHORE_CMD
uint32_t u32CmdTimeout = 0;
#endif
/*Returns from various function calls*/
en_sdio_result_t enRet = Error;
en_sdio_result_t enRetTmp = Ok;
/*Hold value of if these checks are needed*/
/* Hold value of if these checks are needed */
uint8_t bCmdIndexCheck;
uint8_t bCmdCrcCheck;
static uint8_t u8responseBuf[6];
/*Clear statuses*/
/* Clear statuses */
gstcInternalData.stcEvents.u8CmdComplete = 0;
gstcInternalData.stcEvents.u8TransComplete = 0;
gstcInternalData.stcEvents.u8CRCError = 0;
/*Setup the command configuration*/
/* Setup the command configuration */
stcCmdConfig.u8CmdIndex = (uint8_t)pstcCmd->u32CmdIdx;
stcCmdConfig.u32Argument = pstcCmd->u32Arg;
#ifdef CY_RTOS_AWARE
cy_rslt_t result;
/* Initialize the semaphore. This is not done in init because init is called
* in interrupt thread. cy_rtos_init_semaphore call is prohibited in
* interrupt thread.
*/
if(!sema_initialized)
{
cy_rtos_init_semaphore( &sdio_transfer_finished_semaphore, 1, 0 );
sema_initialized = true;
}
#else
/* Variable used for holding timeout value */
uint32_t u32Timeout = 0;
#endif
/*Determine the type of response and if we need to do any checks*/
/*Command 0 and 8 have no response, so don't wait for one*/
if (pstcCmd->u32CmdIdx == 0 || pstcCmd->u32CmdIdx == 8)
@ -694,28 +756,39 @@ en_sdio_result_t SDIO_SendCommandAndWait(stc_sdio_cmd_t *pstcCmd)
SDIO_CONTROL_REG |= SDIO_CTRL_ENABLE_WRITE;
}
#ifndef SEMAPHORE
/*Wait for the transfer to finish*/
#ifdef CY_RTOS_AWARE
/* Wait for the transfer to finish.
* Acquire semaphore and wait until it will be released
* in SDIO_IRQ:
* 1. sdio_transfer_finished_semaphore count is equal to
* zero. cy_rtos_get_semaphore waits until semaphore
* count is increased by cy_rtos_set_semaphore() in
* SDIO_IRQ.
* 2. The cy_rtos_set_semaphore() increases
* sdio_transfer_finished_semaphore count.
* 3. The cy_rtos_get_semaphore() function decreases
* sdio_transfer_finished_semaphore back to zero
* and exit. Or timeout occurs
*/
result = cy_rtos_get_semaphore( &sdio_transfer_finished_semaphore, 10, false );
enRetTmp = SDIO_CheckForEvent(SdCmdEventTransferDone);
if (result != CY_RSLT_SUCCESS)
#else
/* Wait for the transfer to finish */
do
{
u32Timeout++;
enRetTmp = SDIO_CheckForEvent(SdCmdEventTransferDone);
} while (!((enRetTmp == Ok) || (enRetTmp == DataCrcError) || (u32Timeout >= SDIO_DAT_TIMEOUT)));
/*if it was a read it is possible there is still extra data hanging out, trigger the
DMA again. This can result in extra data being transfered so the read buffer should be
3 bytes bigger than needed*/
if (pstcCmd->bRead == true)
{
Cy_TrigMux_SwTrigger((uint32_t)SDIO_HOST_Read_DMA_DW__TR_IN, 2);
}
if (u32Timeout == SDIO_DAT_TIMEOUT)
#else
result = cy_rtos_get_semaphore( &sdio_transfer_finished_semaphore, 10, false );
enRetTmp = SDIO_CheckForEvent(SdCmdEventTransferDone);
#endif
{
enRet |= DataTimeout;
}
/* if it was a read it is possible there is still extra data hanging out, trigger the
DMA again. This can result in extra data being transfered so the read buffer should be
@ -725,12 +798,6 @@ en_sdio_result_t SDIO_SendCommandAndWait(stc_sdio_cmd_t *pstcCmd)
Cy_TrigMux_SwTrigger((uint32_t)SDIO_HOST_Read_DMA_DW__TR_IN, 2);
}
if (result != Ok)
#endif
{
enRet |= DataTimeout;
}
if (enRetTmp == DataCrcError)
{
enRet |= DataCrcError;
@ -741,8 +808,7 @@ en_sdio_result_t SDIO_SendCommandAndWait(stc_sdio_cmd_t *pstcCmd)
} /*No Response Required, thus no CMD53*/
} /*CMD Passed*/
#ifndef SEMAPHORE
#ifndef CY_RTOS_AWARE
u32Timeout = 0;
#endif
@ -1161,63 +1227,72 @@ void SDIO_IRQ(void)
{
uint8_t u8Status;
/*first read the status register*/
/* First read the status register */
u8Status = SDIO_STATUS_REG;
/*Check card interrupt*/
/* Check card interrupt */
if (u8Status & SDIO_STS_CARD_INT )
{
pfnCardInt_count++;
}
/* Execute card interrupt callback if neccesary */
if (0 != pfnCardInt_count)
{
if (NULL != gstcInternalData.pstcCallBacks.pfnCardIntCb)
{
gstcInternalData.pstcCallBacks.pfnCardIntCb();
}
pfnCardInt_count--;
}
/*If the command is complete set the flag*/
/* If the command is complete set the flag */
if (u8Status & SDIO_STS_CMD_DONE)
{
gstcInternalData.stcEvents.u8CmdComplete++;
}
/*Check if a write is complete*/
/* Check if a write is complete */
if (u8Status & SDIO_STS_WRITE_DONE )
{
/*Clear the Write flag and CMD53 flag*/
/* Clear the Write flag and CMD53 flag */
SDIO_CONTROL_REG &= ~(SDIO_CTRL_ENABLE_WRITE | SDIO_CTRL_ENABLE_INT);
/*Check if the CRC status return was bad*/
if (u8Status & SDIO_STS_CRC_ERR )
{
/*CRC was bad, set the flag*/
gstcInternalData.stcEvents.u8CRCError++;
}
/*set the done flag*/
#ifdef SEMAPHORE
cy_rtos_set_semaphore( &sdio_transfer_finished_semaphore, true );
#else
gstcInternalData.stcEvents.u8TransComplete++;
#endif
}
/*Check if a read is complete*/
if (u8Status & SDIO_STS_READ_DONE)
{
/*Clear the read flag*/
SDIO_CONTROL_REG &= ~(SDIO_CTRL_ENABLE_READ| SDIO_CTRL_ENABLE_INT);
/*check the CRC*/
/* Check if the CRC status return was bad */
if (u8Status & SDIO_STS_CRC_ERR)
{
/*CRC was bad, set the flag*/
/* CRC was bad, set the flag */
gstcInternalData.stcEvents.u8CRCError++;
}
/*Okay we're done so set the done flag*/
#ifdef SEMAPHORE
/* Set the done flag */
#ifdef CY_RTOS_AWARE
cy_rtos_set_semaphore( &sdio_transfer_finished_semaphore, true );
#else
#else
gstcInternalData.stcEvents.u8TransComplete++;
#endif
#endif
}
/* Check if a read is complete */
if (u8Status & SDIO_STS_READ_DONE)
{
/* Clear the read flag */
SDIO_CONTROL_REG &= ~(SDIO_CTRL_ENABLE_READ| SDIO_CTRL_ENABLE_INT);
/* Check the CRC */
if (u8Status & SDIO_STS_CRC_ERR)
{
/* CRC was bad, set the flag */
gstcInternalData.stcEvents.u8CRCError++;
}
/* Okay we're done so set the done flag */
#ifdef CY_RTOS_AWARE
cy_rtos_set_semaphore( &sdio_transfer_finished_semaphore, true );
#else
gstcInternalData.stcEvents.u8TransComplete++;
#endif
}
NVIC_ClearPendingIRQ((IRQn_Type) SDIO_HOST_sdio_int__INTC_NUMBER);
@ -1286,7 +1361,6 @@ void SDIO_READ_DMA_IRQ(void)
yCounts--;
}
void SDIO_WRITE_DMA_IRQ(void)
{
/*We shouldn't have to change anything unless it is the last descriptor*/
@ -1348,6 +1422,46 @@ void SDIO_WRITE_DMA_IRQ(void)
yCounts--;
}
void SDIO_Free(void)
{
#ifdef CY_RTOS_AWARE
cy_rtos_deinit_semaphore(&sdio_transfer_finished_semaphore);
#endif
}
/*******************************************************************************
* Function Name: SDIO_SaveConfig
********************************************************************************
*
* Saves the user configuration of the SDIO UDB non-retention registers. Call the
* SDIO_SaveConfig() function before the Cy_SysPm_CpuEnterDeepSleep() function.
*
*******************************************************************************/
static void SDIO_SaveConfig(void)
{
regs.CY_SDIO_UDB_WRKMULT_CTL_0 = UDB->WRKMULT.CTL[0];
regs.CY_SDIO_UDB_WRKMULT_CTL_1 = UDB->WRKMULT.CTL[1];
regs.CY_SDIO_UDB_WRKMULT_CTL_2 = UDB->WRKMULT.CTL[2];
regs.CY_SDIO_UDB_WRKMULT_CTL_3 = UDB->WRKMULT.CTL[3];
}
/*******************************************************************************
* Function Name: SDIO_RestoreConfig
********************************************************************************
*
* Restores the user configuration of the SDIO UDB non-retention registers. Call
* the SDIO_Wakeup() function after the Cy_SysPm_CpuEnterDeepSleep() function.
*
*******************************************************************************/
static void SDIO_RestoreConfig(void)
{
UDB->WRKMULT.CTL[0] = regs.CY_SDIO_UDB_WRKMULT_CTL_0;
UDB->WRKMULT.CTL[1] = regs.CY_SDIO_UDB_WRKMULT_CTL_1;
UDB->WRKMULT.CTL[2] = regs.CY_SDIO_UDB_WRKMULT_CTL_2;
UDB->WRKMULT.CTL[3] = regs.CY_SDIO_UDB_WRKMULT_CTL_3;
}
#if defined(__cplusplus)
}
#endif

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST.h
View File

@ -35,7 +35,6 @@
/**
* \defgroup group_udb_sdio UDB_SDIO
* \ingroup group_bsp
* \{
* SDIO - Secure Digital Input Output Is a standard for communicating with various
external devices such as Wifi and bluetooth devices.
@ -272,6 +271,7 @@ void SDIO_SetSdClkFrequency(uint32_t u32SdClkFreqHz);
void SDIO_Reset(void);
void SDIO_EnableChipInt(void);
void SDIO_DisableChipInt(void);
void SDIO_Free(void);
/*Low Level Functions*/
void SDIO_SendCommand(stc_sdio_cmd_config_t *pstcCmdConfig);
@ -293,6 +293,8 @@ void SDIO_WRITE_DMA_IRQ(void);
void SDIO_Crc7Init(void);
cy_en_syspm_status_t SDIO_DeepSleepCallback(cy_stc_syspm_callback_params_t *params, cy_en_syspm_callback_mode_t mode);
/** \endcond */
/** \} group_udb_sdio_functions */

79
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/cybsp_types.h
View File

@ -23,14 +23,6 @@
* limitations under the License.
*******************************************************************************/
/**
* \addtogroup group_bsp_cy8ckit_062_wifi_bt CY8CKIT-062-WIFI-BT
* \ingroup group_bsp
* \{
* \defgroup group_bsp_cy8ckit_062_wifi_bt_macros Macros
* \defgroup group_bsp_cy8ckit_062_wifi_bt_enums Enumerated Types
*/
#pragma once
#include "cyhal.h"
@ -40,10 +32,56 @@ extern "C" {
#endif
/**
* \addtogroup group_bsp_cy8ckit_062_wifi_bt_macros
* \addtogroup group_bsp_pins Pin Mappings
* \{
*/
// Arduino connector namings
/** Arduino A0 */
#define CYBSP_A0 P10_0
/** Arduino A1 */
#define CYBSP_A1 P10_1
/** Arduino A2 */
#define CYBSP_A2 P10_2
/** Arduino A3 */
#define CYBSP_A3 P10_3
/** Arduino A4 */
#define CYBSP_A4 P10_4
/** Arduino A5 */
#define CYBSP_A5 P10_5
/** Arduino D0 */
#define CYBSP_D0 P5_0
/** Arduino D1 */
#define CYBSP_D1 P5_1
/** Arduino D2 */
#define CYBSP_D2 P5_2
/** Arduino D3 */
#define CYBSP_D3 P5_3
/** Arduino D4 */
#define CYBSP_D4 P5_4
/** Arduino D5 */
#define CYBSP_D5 P5_5
/** Arduino D6 */
#define CYBSP_D6 P5_6
/** Arduino D7 */
#define CYBSP_D7 P0_2
/** Arduino D8 */
#define CYBSP_D8 P13_0
/** Arduino D9 */
#define CYBSP_D9 P13_1
/** Arduino D10 */
#define CYBSP_D10 P12_3
/** Arduino D11 */
#define CYBSP_D11 P12_0
/** Arduino D12 */
#define CYBSP_D12 P12_1
/** Arduino D13 */
#define CYBSP_D13 P12_2
/** Arduino D14 */
#define CYBSP_D14 P6_1
/** Arduino D15 */
#define CYBSP_D15 P6_0
// Generic signal names
/** Pin: WCO input */
#define CYBSP_WCO_IN P0_0
@ -51,18 +89,25 @@ extern "C" {
#define CYBSP_WCO_OUT P0_1
/** Pin: WIFI SDIO D0 */
/* Corresponds to: ioss[0].port[2].pin[0], udb[0] */
#define CYBSP_WIFI_SDIO_D0 P2_0
/** Pin: WIFI SDIO D1 */
/* Corresponds to: ioss[0].port[2].pin[1], udb[0] */
#define CYBSP_WIFI_SDIO_D1 P2_1
/** Pin: WIFI SDIO D2 */
/* Corresponds to: ioss[0].port[2].pin[2], udb[0] */
#define CYBSP_WIFI_SDIO_D2 P2_2
/** Pin: WIFI SDIO D3 */
/* Corresponds to: ioss[0].port[2].pin[3], udb[0] */
#define CYBSP_WIFI_SDIO_D3 P2_3
/** Pin: WIFI SDIO CMD */
/* Corresponds to: ioss[0].port[2].pin[4], udb[0] */
#define CYBSP_WIFI_SDIO_CMD P2_4
/** Pin: WIFI SDIO CLK */
/* Corresponds to: ioss[0].port[2].pin[5], udb[0] */
#define CYBSP_WIFI_SDIO_CLK P2_5
/** Pin: WIFI ON */
/* Corresponds to: ioss[0].port[2].pin[6], udb[0] */
#define CYBSP_WIFI_WL_REG_ON P2_6
/** Pin: WIFI Host Wakeup */
#define CYBSP_WIFI_HOST_WAKE P2_7
@ -84,8 +129,10 @@ extern "C" {
#define CYBSP_BT_DEVICE_WAKE P4_0
/** Pin: UART RX */
/* Corresponds to: ioss[0].port[5].pin[0], scb[5] */
#define CYBSP_DEBUG_UART_RX P5_0
/** Pin: UART TX */
/* Corresponds to: ioss[0].port[5].pin[1], scb[5] */
#define CYBSP_DEBUG_UART_TX P5_1
/** Pin: I2C SCL */
@ -141,10 +188,10 @@ extern "C" {
/** Host-wake IRQ event */
#define CYBSP_WIFI_HOST_WAKE_IRQ_EVENT CYHAL_GPIO_IRQ_RISE
/** \} group_bsp_cy8ckit_062_wifi_bt_macros */
/** \} group_bsp_pins */
/**
* \addtogroup group_bsp_cy8ckit_062_wifi_bt_enums
* \addtogroup group_bsp_enums Enumerated Types
* \{
*/
@ -171,10 +218,15 @@ typedef enum
CYBSP_LED_RGB_GREEN = P1_1,
CYBSP_LED_RGB_BLUE = P11_1,
/* Corresponds to: ioss[0].port[1].pin[5] */
CYBSP_USER_LED1 = CYBSP_LED8,
/* Corresponds to: ioss[0].port[13].pin[7] */
CYBSP_USER_LED2 = CYBSP_LED9,
/* Corresponds to: ioss[0].port[0].pin[3] */
CYBSP_USER_LED3 = CYBSP_LED_RGB_RED,
/* Corresponds to: ioss[0].port[1].pin[1] */
CYBSP_USER_LED4 = CYBSP_LED_RGB_GREEN,
/* Corresponds to: ioss[0].port[11].pin[1] */
CYBSP_USER_LED5 = CYBSP_LED_RGB_BLUE,
CYBSP_USER_LED = CYBSP_USER_LED1,
} cybsp_led_t;
@ -184,14 +236,13 @@ typedef enum
{
CYBSP_SW2 = P0_4,
/* Corresponds to: ioss[0].port[0].pin[4] */
CYBSP_USER_BTN1 = CYBSP_SW2,
CYBSP_USER_BTN = CYBSP_USER_BTN1,
} cybsp_btn_t;
/** \} group_bsp_cy8ckit_062_wifi_bt_enums */
/** \} group_bsp_enums */
#if defined(__cplusplus)
}
#endif
/** \} group_bsp_cy8ckit_062_wifi_bt */

42
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/PeripheralPins.c
View File

@ -124,7 +124,9 @@ const PinMap PinMap_I2C_SCL[] = {
{P5_0, I2C_5, CYHAL_PIN_OD_FUNCTION(P5_0_SCB5_I2C_SCL)},
{P5_4, I2C_10, CYHAL_PIN_OD_FUNCTION(P5_4_SCB10_I2C_SCL)},
{P6_0, I2C_3, CYHAL_PIN_OD_FUNCTION(P6_0_SCB3_I2C_SCL)},
{P6_0, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_0_SCB8_I2C_SCL)},
{P6_4, I2C_6, CYHAL_PIN_OD_FUNCTION(P6_4_SCB6_I2C_SCL)},
{P6_4, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_4_SCB8_I2C_SCL)},
{P7_0, I2C_4, CYHAL_PIN_OD_FUNCTION(P7_0_SCB4_I2C_SCL)},
{P8_0, I2C_4, CYHAL_PIN_OD_FUNCTION(P8_0_SCB4_I2C_SCL)},
{P8_4, I2C_11, CYHAL_PIN_OD_FUNCTION(P8_4_SCB11_I2C_SCL)},
@ -146,7 +148,9 @@ const PinMap PinMap_I2C_SDA[] = {
{P5_1, I2C_5, CYHAL_PIN_OD_FUNCTION(P5_1_SCB5_I2C_SDA)},
{P5_5, I2C_10, CYHAL_PIN_OD_FUNCTION(P5_5_SCB10_I2C_SDA)},
{P6_1, I2C_3, CYHAL_PIN_OD_FUNCTION(P6_1_SCB3_I2C_SDA)},
{P6_1, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_1_SCB8_I2C_SDA)},
{P6_5, I2C_6, CYHAL_PIN_OD_FUNCTION(P6_5_SCB6_I2C_SDA)},
{P6_5, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_5_SCB8_I2C_SDA)},
{P7_1, I2C_4, CYHAL_PIN_OD_FUNCTION(P7_1_SCB4_I2C_SDA)},
{P8_1, I2C_4, CYHAL_PIN_OD_FUNCTION(P8_1_SCB4_I2C_SDA)},
{P8_5, I2C_11, CYHAL_PIN_OD_FUNCTION(P8_5_SCB11_I2C_SDA)},
@ -170,7 +174,9 @@ const PinMap PinMap_SPI_MOSI[] = {
{P4_0, SPI_7, CYHAL_PIN_OUT_FUNCTION(P4_0_SCB7_SPI_MOSI)},
{P5_0, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_0_SCB5_SPI_MOSI)},
{P6_0, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_0_SCB3_SPI_MOSI)},
{P6_0, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_0_SCB8_SPI_MOSI)},
{P6_4, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB6_SPI_MOSI)},
{P6_4, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB8_SPI_MOSI)},
{P7_0, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_0_SCB4_SPI_MOSI)},
{P8_0, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_0_SCB4_SPI_MOSI)},
{P9_0, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_0_SCB2_SPI_MOSI)},
@ -188,7 +194,9 @@ const PinMap PinMap_SPI_MISO[] = {
{P4_1, SPI_7, CYHAL_PIN_IN_FUNCTION(P4_1_SCB7_SPI_MISO)},
{P5_1, SPI_5, CYHAL_PIN_IN_FUNCTION(P5_1_SCB5_SPI_MISO)},
{P6_1, SPI_3, CYHAL_PIN_IN_FUNCTION(P6_1_SCB3_SPI_MISO)},
{P6_1, SPI_8, CYHAL_PIN_IN_FUNCTION(P6_1_SCB8_SPI_MISO)},
{P6_5, SPI_6, CYHAL_PIN_IN_FUNCTION(P6_5_SCB6_SPI_MISO)},
{P6_5, SPI_8, CYHAL_PIN_IN_FUNCTION(P6_5_SCB8_SPI_MISO)},
{P7_1, SPI_4, CYHAL_PIN_IN_FUNCTION(P7_1_SCB4_SPI_MISO)},
{P8_1, SPI_4, CYHAL_PIN_IN_FUNCTION(P8_1_SCB4_SPI_MISO)},
{P9_1, SPI_2, CYHAL_PIN_IN_FUNCTION(P9_1_SCB2_SPI_MISO)},
@ -205,7 +213,9 @@ const PinMap PinMap_SPI_SCLK[] = {
{P3_2, SPI_2, CYHAL_PIN_OUT_FUNCTION(P3_2_SCB2_SPI_CLK)},
{P5_2, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_2_SCB5_SPI_CLK)},
{P6_2, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB3_SPI_CLK)},
{P6_2, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB8_SPI_CLK)},
{P6_6, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB6_SPI_CLK)},
{P6_6, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB8_SPI_CLK)},
{P7_2, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_2_SCB4_SPI_CLK)},
{P8_2, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_2_SCB4_SPI_CLK)},
{P9_2, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_2_SCB2_SPI_CLK)},
@ -222,7 +232,9 @@ const PinMap PinMap_SPI_SSEL[] = {
{P3_3, SPI_2, CYHAL_PIN_OUT_FUNCTION(P3_3_SCB2_SPI_SELECT0)},
{P5_3, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_3_SCB5_SPI_SELECT0)},
{P6_3, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB3_SPI_SELECT0)},
{P6_3, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB8_SPI_SELECT0)},
{P6_7, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB6_SPI_SELECT0)},
{P6_7, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB8_SPI_SELECT0)},
{P7_3, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_3_SCB4_SPI_SELECT0)},
{P8_3, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_3_SCB4_SPI_SELECT0)},
{P9_3, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_3_SCB2_SPI_SELECT0)},
@ -445,30 +457,23 @@ const PinMap PinMap_PWM_OUT[] = {
#if DEVICE_ANALOGIN
const PinMap PinMap_ADC[] = {
{P9_0, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input connects to the P9_0 pin through the AMUXA bus
{P9_1, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input connects to the P9_1 pin through the AMUXA bus
{P9_2, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input connects to the P9_2 pin through the AMUXA bus
{P9_4, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input connects to the P9_4 pin through the AMUXA bus
{P9_5, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input connects to the P9_5 pin through the AMUXA bus
{P9_6, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input connects to the P9_6 pin through the AMUXA bus
{P10_0, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_0 pin
{P10_1, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_1 pin
{P10_2, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_2 pin
{P10_3, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_3 pin
{P10_4, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_4 pin
{P10_5, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_5 pin
{P10_6, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_6 pin
{P10_7, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_7 pin
{P10_0, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
{P10_1, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
{P10_2, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
{P10_3, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
{P10_4, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
{P10_5, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
{P10_6, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
{P10_7, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
{NC, NC, 0}
};
#endif // DEVICE_ANALOGIN
#if DEVICE_QSPI
const PinMap PinMap_QSPI_SCLK[] = { // does not use PERI clock, uses HFCLK2
const PinMap PinMap_QSPI_SCLK[] = {
{P11_7, QSPI_0, CY_GPIO_CFG_CREATE(P11_7_SMIF_SPI_CLK, CY_GPIO_DM_STRONG_IN_OFF)},
{NC, NC, 0}
{NC, NC, 0},
};
const PinMap PinMap_QSPI_SSEL[] = {
{P11_2, QSPI_0, CY_GPIO_CFG_CREATE(P11_2_SMIF_SPI_SELECT0, CY_GPIO_DM_STRONG_IN_OFF)},
{NC, NC, 0},
@ -488,6 +493,5 @@ const PinMap PinMap_QSPI_DATA2[] = {
const PinMap PinMap_QSPI_DATA3[] = {
{P11_3, QSPI_0, CY_GPIO_CFG_CREATE(P11_3_SMIF_SPI_DATA3, CY_GPIO_DM_STRONG)},
{NC, NC, 0},
};
};
#endif // DEVICE_QSPI

34
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/PeripheralPins.c
View File

@ -124,7 +124,9 @@ const PinMap PinMap_I2C_SCL[] = {
{P5_0, I2C_5, CYHAL_PIN_OD_FUNCTION(P5_0_SCB5_I2C_SCL)},
{P5_4, I2C_10, CYHAL_PIN_OD_FUNCTION(P5_4_SCB10_I2C_SCL)},
{P6_0, I2C_3, CYHAL_PIN_OD_FUNCTION(P6_0_SCB3_I2C_SCL)},
{P6_0, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_0_SCB8_I2C_SCL)},
{P6_4, I2C_6, CYHAL_PIN_OD_FUNCTION(P6_4_SCB6_I2C_SCL)},
{P6_4, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_4_SCB8_I2C_SCL)},
{P7_0, I2C_4, CYHAL_PIN_OD_FUNCTION(P7_0_SCB4_I2C_SCL)},
{P8_0, I2C_4, CYHAL_PIN_OD_FUNCTION(P8_0_SCB4_I2C_SCL)},
{P8_4, I2C_11, CYHAL_PIN_OD_FUNCTION(P8_4_SCB11_I2C_SCL)},
@ -146,7 +148,9 @@ const PinMap PinMap_I2C_SDA[] = {
{P5_1, I2C_5, CYHAL_PIN_OD_FUNCTION(P5_1_SCB5_I2C_SDA)},
{P5_5, I2C_10, CYHAL_PIN_OD_FUNCTION(P5_5_SCB10_I2C_SDA)},
{P6_1, I2C_3, CYHAL_PIN_OD_FUNCTION(P6_1_SCB3_I2C_SDA)},
{P6_1, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_1_SCB8_I2C_SDA)},
{P6_5, I2C_6, CYHAL_PIN_OD_FUNCTION(P6_5_SCB6_I2C_SDA)},
{P6_5, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_5_SCB8_I2C_SDA)},
{P7_1, I2C_4, CYHAL_PIN_OD_FUNCTION(P7_1_SCB4_I2C_SDA)},
{P8_1, I2C_4, CYHAL_PIN_OD_FUNCTION(P8_1_SCB4_I2C_SDA)},
{P8_5, I2C_11, CYHAL_PIN_OD_FUNCTION(P8_5_SCB11_I2C_SDA)},
@ -170,7 +174,9 @@ const PinMap PinMap_SPI_MOSI[] = {
{P4_0, SPI_7, CYHAL_PIN_OUT_FUNCTION(P4_0_SCB7_SPI_MOSI)},
{P5_0, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_0_SCB5_SPI_MOSI)},
{P6_0, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_0_SCB3_SPI_MOSI)},
{P6_0, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_0_SCB8_SPI_MOSI)},
{P6_4, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB6_SPI_MOSI)},
{P6_4, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB8_SPI_MOSI)},
{P7_0, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_0_SCB4_SPI_MOSI)},
{P8_0, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_0_SCB4_SPI_MOSI)},
{P9_0, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_0_SCB2_SPI_MOSI)},
@ -188,7 +194,9 @@ const PinMap PinMap_SPI_MISO[] = {
{P4_1, SPI_7, CYHAL_PIN_IN_FUNCTION(P4_1_SCB7_SPI_MISO)},
{P5_1, SPI_5, CYHAL_PIN_IN_FUNCTION(P5_1_SCB5_SPI_MISO)},
{P6_1, SPI_3, CYHAL_PIN_IN_FUNCTION(P6_1_SCB3_SPI_MISO)},
{P6_1, SPI_8, CYHAL_PIN_IN_FUNCTION(P6_1_SCB8_SPI_MISO)},
{P6_5, SPI_6, CYHAL_PIN_IN_FUNCTION(P6_5_SCB6_SPI_MISO)},
{P6_5, SPI_8, CYHAL_PIN_IN_FUNCTION(P6_5_SCB8_SPI_MISO)},
{P7_1, SPI_4, CYHAL_PIN_IN_FUNCTION(P7_1_SCB4_SPI_MISO)},
{P8_1, SPI_4, CYHAL_PIN_IN_FUNCTION(P8_1_SCB4_SPI_MISO)},
{P9_1, SPI_2, CYHAL_PIN_IN_FUNCTION(P9_1_SCB2_SPI_MISO)},
@ -205,7 +213,9 @@ const PinMap PinMap_SPI_SCLK[] = {
{P3_2, SPI_2, CYHAL_PIN_OUT_FUNCTION(P3_2_SCB2_SPI_CLK)},
{P5_2, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_2_SCB5_SPI_CLK)},
{P6_2, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB3_SPI_CLK)},
{P6_2, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB8_SPI_CLK)},
{P6_6, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB6_SPI_CLK)},
{P6_6, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB8_SPI_CLK)},
{P7_2, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_2_SCB4_SPI_CLK)},
{P8_2, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_2_SCB4_SPI_CLK)},
{P9_2, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_2_SCB2_SPI_CLK)},
@ -222,7 +232,9 @@ const PinMap PinMap_SPI_SSEL[] = {
{P3_3, SPI_2, CYHAL_PIN_OUT_FUNCTION(P3_3_SCB2_SPI_SELECT0)},
{P5_3, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_3_SCB5_SPI_SELECT0)},
{P6_3, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB3_SPI_SELECT0)},
{P6_3, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB8_SPI_SELECT0)},
{P6_7, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB6_SPI_SELECT0)},
{P6_7, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB8_SPI_SELECT0)},
{P7_3, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_3_SCB4_SPI_SELECT0)},
{P8_3, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_3_SCB4_SPI_SELECT0)},
{P9_3, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_3_SCB2_SPI_SELECT0)},
@ -445,20 +457,14 @@ const PinMap PinMap_PWM_OUT[] = {
#if DEVICE_ANALOGIN
const PinMap PinMap_ADC[] = {
{P9_0, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input connects to the P9_0 pin through the AMUXA bus
{P9_1, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input connects to the P9_1 pin through the AMUXA bus
{P9_2, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input connects to the P9_2 pin through the AMUXA bus
{P9_4, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input connects to the P9_4 pin through the AMUXA bus
{P9_5, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input connects to the P9_5 pin through the AMUXA bus
{P9_6, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input connects to the P9_6 pin through the AMUXA bus
{P10_0, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_0 pin
{P10_1, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_1 pin
{P10_2, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_2 pin
{P10_3, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_3 pin
{P10_4, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_4 pin
{P10_5, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_5 pin
{P10_6, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_6 pin
{P10_7, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_7 pin
{P10_0, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
{P10_1, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
{P10_2, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
{P10_3, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
{P10_4, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
{P10_5, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
{P10_6, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
{P10_7, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
{NC, NC, 0}
};
#endif // DEVICE_ANALOGIN

31
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/PinNames.h
View File

@ -20,13 +20,8 @@
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#include "PinNamesTypes.h"
#include "PortNames.h"
#include "cyhal_pin_package.h"
#include "cyhal_utils.h"
typedef cyhal_gpio_t PinName;
// Generic signal names
@ -38,23 +33,15 @@ typedef cyhal_gpio_t PinName;
#define UART_RTS P5_2
#define UART_CTS P5_3
#define BT_UART_RX P3_0
#define BT_UART_TX P3_1
#define BT_UART_CTS P3_3
#define BT_UART_RTS P3_2
#define BT_PIN_POWER P3_4
#define BT_PIN_HOST_WAKE P3_5
#define BT_PIN_DEVICE_WAKE P4_0
// Reset pin unavailable
#define SWITCH2 P0_4
#define LED1 P13_7
#define LED2 NC
#define LED3 NC
#define LED4 NC
#define LED_RED LED1
#define SWITCH2 P0_4
#define USER_BUTTON SWITCH2
#define BUTTON1 USER_BUTTON
@ -96,23 +83,7 @@ typedef cyhal_gpio_t PinName;
#define STDIO_UART_CTS UART_CTS
#define STDIO_UART_RTS UART_RTS
#define CY_STDIO_UART_RX STDIO_UART_RX
#define CY_STDIO_UART_TX STDIO_UART_TX
#define CY_STDIO_UART_CTS STDIO_UART_CTS
#define CY_STDIO_UART_RTS STDIO_UART_RTS
#define CY_BT_UART_RX BT_UART_RX
#define CY_BT_UART_TX BT_UART_TX
#define CY_BT_UART_CTS BT_UART_CTS
#define CY_BT_UART_RTS BT_UART_RTS
#define CY_BT_PIN_POWER BT_PIN_POWER
#define CY_BT_PIN_HOST_WAKE BT_PIN_HOST_WAKE
#define CY_BT_PIN_DEVICE_WAKE BT_PIN_DEVICE_WAKE
#define USBTX UART_TX
#define USBRX UART_RX
#define CY_WIFI_HOST_WAKE P2_7
#endif

60
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/cybsp_types.h
View File

@ -23,14 +23,6 @@
* limitations under the License.
*******************************************************************************/
/**
* \addtogroup group_bsp_cy8cproto_062_4343w CY8CPROTO-062-4343W
* \ingroup group_bsp
* \{
* \defgroup group_bsp_cy8cproto_062_4343w_macros Macros
* \defgroup group_bsp_cy8cproto_062_4343w_enums Enumerated Types
*/
#pragma once
#include "cyhal.h"
@ -40,41 +32,79 @@ extern "C" {
#endif
/**
* \addtogroup group_bsp_cy8cproto_062_4343w_macros
* \addtogroup group_bsp_pins Pin Mappings
* \{
*/
/** Pin: WIFI SDIO D0 */
/* Corresponds to: ioss[0].port[2].pin[0], sdhc[0] */
#define CYBSP_WIFI_SDIO_D0 P2_0
/** Pin: WIFI SDIO D1 */
/* Corresponds to: ioss[0].port[2].pin[1], sdhc[0] */
#define CYBSP_WIFI_SDIO_D1 P2_1
/** Pin: WIFI SDIO D2 */
/* Corresponds to: ioss[0].port[2].pin[2], sdhc[0] */
#define CYBSP_WIFI_SDIO_D2 P2_2
/** Pin: WIFI SDIO D3 */
/* Corresponds to: ioss[0].port[2].pin[3], sdhc[0] */
#define CYBSP_WIFI_SDIO_D3 P2_3
/** Pin: WIFI SDIO CMD */
/* Corresponds to: ioss[0].port[2].pin[4], sdhc[0] */
#define CYBSP_WIFI_SDIO_CMD P2_4
/** Pin: WIFI SDIO CLK */
/* Corresponds to: ioss[0].port[2].pin[5], sdhc[0] */
#define CYBSP_WIFI_SDIO_CLK P2_5
/** Pin: WIFI ON */
/* Corresponds to: ioss[0].port[2].pin[6], sdhc[0] */
#define CYBSP_WIFI_WL_REG_ON P2_6
/** Pin: WIFI Host Wakeup */
#define CYBSP_WIFI_HOST_WAKE P1_4
#define CYBSP_WIFI_HOST_WAKE P0_4
/** Pin: BT UART RX */
#define CYBSP_BT_UART_RX P3_0
/** Pin: BT UART TX */
#define CYBSP_BT_UART_TX P3_1
/** Pin: BT UART RTS */
#define CYBSP_BT_UART_RTS P3_2
/** Pin: BT UART CTS */
#define CYBSP_BT_UART_CTS P3_3
/** Pin: BT Power */
#define CYBSP_BT_POWER P3_4
/** Pin: BT Host Wakeup */
#define CYBSP_BT_HOST_WAKE P4_0
/** Pin: BT Device Wakeup */
#define CYBSP_BT_DEVICE_WAKE P3_5
/** Pin: UART RX */
/* Corresponds to: ioss[0].port[5].pin[0], scb[5] */
#define CYBSP_DEBUG_UART_RX P5_0
/** Pin: UART TX */
/* Corresponds to: ioss[0].port[5].pin[1], scb[5] */
#define CYBSP_DEBUG_UART_TX P5_1
/** Pin: QUAD SPI SS */
#define CYBSP_QSPI_SS P11_2
/** Pin: QUAD SPI D3 */
#define CYBSP_QSPI_D3 P11_3
/** Pin: QUAD SPI D2 */
#define CYBSP_QSPI_D2 P11_4
/** Pin: QUAD SPI D1 */
#define CYBSP_QSPI_D1 P11_5
/** Pin: QUAD SPI D0 */
#define CYBSP_QSPI_D0 P11_6
/** Pin: QUAD SPI SCK */
#define CYBSP_QSPI_SCK P11_7
/** Host-wake GPIO drive mode */
#define CYBSP_WIFI_HOST_WAKE_GPIO_DM CYHAL_GPIO_DRIVE_ANALOG
/** Host-wake IRQ event */
#define CYBSP_WIFI_HOST_WAKE_IRQ_EVENT CYHAL_GPIO_IRQ_RISE
/** \} group_bsp_cy8cproto_062_4343w_macros */
/** \} group_bsp_pins */
/**
* \addtogroup group_bsp_cy8cproto_062_4343w_enums
* \addtogroup group_bsp_enums Enumerated Types
* \{
*/
@ -97,6 +127,7 @@ typedef enum
{
CYBSP_LED_RED = P13_7,
/* Corresponds to: ioss[0].port[13].pin[7] */
CYBSP_USER_LED1 = CYBSP_LED_RED,
CYBSP_USER_LED = CYBSP_USER_LED1,
} cybsp_led_t;
@ -106,14 +137,13 @@ typedef enum
{
CYBSP_SW2 = P0_4,
/* Corresponds to: ioss[0].port[0].pin[4] */
CYBSP_USER_BTN1 = CYBSP_SW2,
CYBSP_USER_BTN = CYBSP_USER_BTN1,
} cybsp_btn_t;
/** \} group_bsp_cy8cproto_062_4343w_enums */
/** \} group_bsp_enums */
#if defined(__cplusplus)
}
#endif
/** \} group_bsp_cy8cproto_062_4343w */

13
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/PeripheralPins.c
View File

@ -104,7 +104,9 @@ const PinMap PinMap_I2C_SCL[] = {
{P4_0, I2C_7, CYHAL_PIN_OD_FUNCTION(P4_0_SCB7_I2C_SCL)},
{P5_0, I2C_5, CYHAL_PIN_OD_FUNCTION(P5_0_SCB5_I2C_SCL)},
{P6_0, I2C_3, CYHAL_PIN_OD_FUNCTION(P6_0_SCB3_I2C_SCL)},
{P6_0, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_0_SCB8_I2C_SCL)},
{P6_4, I2C_6, CYHAL_PIN_OD_FUNCTION(P6_4_SCB6_I2C_SCL)},
{P6_4, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_4_SCB8_I2C_SCL)},
{P7_0, I2C_4, CYHAL_PIN_OD_FUNCTION(P7_0_SCB4_I2C_SCL)},
{P8_0, I2C_4, CYHAL_PIN_OD_FUNCTION(P8_0_SCB4_I2C_SCL)},
{P9_0, I2C_2, CYHAL_PIN_OD_FUNCTION(P9_0_SCB2_I2C_SCL)},
@ -122,7 +124,9 @@ const PinMap PinMap_I2C_SDA[] = {
{P4_1, I2C_7, CYHAL_PIN_OD_FUNCTION(P4_1_SCB7_I2C_SDA)},
{P5_1, I2C_5, CYHAL_PIN_OD_FUNCTION(P5_1_SCB5_I2C_SDA)},
{P6_1, I2C_3, CYHAL_PIN_OD_FUNCTION(P6_1_SCB3_I2C_SDA)},
{P6_1, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_1_SCB8_I2C_SDA)},
{P6_5, I2C_6, CYHAL_PIN_OD_FUNCTION(P6_5_SCB6_I2C_SDA)},
{P6_5, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_5_SCB8_I2C_SDA)},
{P7_1, I2C_4, CYHAL_PIN_OD_FUNCTION(P7_1_SCB4_I2C_SDA)},
{P8_1, I2C_4, CYHAL_PIN_OD_FUNCTION(P8_1_SCB4_I2C_SDA)},
{P9_1, I2C_2, CYHAL_PIN_OD_FUNCTION(P9_1_SCB2_I2C_SDA)},
@ -144,7 +148,9 @@ const PinMap PinMap_SPI_MOSI[] = {
{P4_0, SPI_7, CYHAL_PIN_OUT_FUNCTION(P4_0_SCB7_SPI_MOSI)},
{P5_0, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_0_SCB5_SPI_MOSI)},
{P6_0, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_0_SCB3_SPI_MOSI)},
{P6_0, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_0_SCB8_SPI_MOSI)},
{P6_4, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB6_SPI_MOSI)},
{P6_4, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB8_SPI_MOSI)},
{P7_0, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_0_SCB4_SPI_MOSI)},
{P8_0, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_0_SCB4_SPI_MOSI)},
{P9_0, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_0_SCB2_SPI_MOSI)},
@ -162,7 +168,9 @@ const PinMap PinMap_SPI_MISO[] = {
{P4_1, SPI_7, CYHAL_PIN_IN_FUNCTION(P4_1_SCB7_SPI_MISO)},
{P5_1, SPI_5, CYHAL_PIN_IN_FUNCTION(P5_1_SCB5_SPI_MISO)},
{P6_1, SPI_3, CYHAL_PIN_IN_FUNCTION(P6_1_SCB3_SPI_MISO)},
{P6_1, SPI_8, CYHAL_PIN_IN_FUNCTION(P6_1_SCB8_SPI_MISO)},
{P6_5, SPI_6, CYHAL_PIN_IN_FUNCTION(P6_5_SCB6_SPI_MISO)},
{P6_5, SPI_8, CYHAL_PIN_IN_FUNCTION(P6_5_SCB8_SPI_MISO)},
{P7_1, SPI_4, CYHAL_PIN_IN_FUNCTION(P7_1_SCB4_SPI_MISO)},
{P8_1, SPI_4, CYHAL_PIN_IN_FUNCTION(P8_1_SCB4_SPI_MISO)},
{P9_1, SPI_2, CYHAL_PIN_IN_FUNCTION(P9_1_SCB2_SPI_MISO)},
@ -179,7 +187,9 @@ const PinMap PinMap_SPI_SCLK[] = {
{P3_2, SPI_2, CYHAL_PIN_OUT_FUNCTION(P3_2_SCB2_SPI_CLK)},
{P5_2, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_2_SCB5_SPI_CLK)},
{P6_2, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB3_SPI_CLK)},
{P6_2, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB8_SPI_CLK)},
{P6_6, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB6_SPI_CLK)},
{P6_6, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB8_SPI_CLK)},
{P7_2, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_2_SCB4_SPI_CLK)},
{P8_2, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_2_SCB4_SPI_CLK)},
{P9_2, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_2_SCB2_SPI_CLK)},
@ -195,7 +205,9 @@ const PinMap PinMap_SPI_SSEL[] = {
{P3_3, SPI_2, CYHAL_PIN_OUT_FUNCTION(P3_3_SCB2_SPI_SELECT0)},
{P5_3, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_3_SCB5_SPI_SELECT0)},
{P6_3, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB3_SPI_SELECT0)},
{P6_3, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB8_SPI_SELECT0)},
{P6_7, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB6_SPI_SELECT0)},
{P6_7, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB8_SPI_SELECT0)},
{P7_3, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_3_SCB4_SPI_SELECT0)},
{P8_3, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_3_SCB4_SPI_SELECT0)},
{P9_3, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_3_SCB2_SPI_SELECT0)},
@ -430,7 +442,6 @@ const PinMap PinMap_ADC[] = {
#if DEVICE_ANALOGOUT
const PinMap PinMap_DAC[] = {
{P9_6, DAC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
{P10_5, DAC_0, CY_GPIO_CFG_CREATE(HSIOM_SEL_AMUXA, CY_GPIO_DM_ANALOG)}, // CTDAC connects to the P10_5 pin through the AMUXA bus
{NC, NC, 0}
};
#endif // DEVICE_ANALOGIN

35
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/PinNames.h
View File

@ -20,13 +20,8 @@
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#include "PinNamesTypes.h"
#include "PortNames.h"
#include "cyhal_pin_package.h"
#include "cyhal_utils.h"
typedef cyhal_gpio_t PinName;
// Generic signal names
@ -43,25 +38,14 @@ typedef cyhal_gpio_t PinName;
#define UART_RTS P13_2
#define UART_CTS P13_3
#define BT_UART_RX P3_0
#define BT_UART_TX P3_1
#define BT_UART_CTS P3_3
#define BT_UART_RTS P3_2
#define BT_PIN_POWER P3_4
#define BT_PIN_HOST_WAKE P4_0
#define BT_PIN_DEVICE_WAKE P3_5
#define BT_PIN_DEVICE_RESET P4_1
#define SWITCH2 P0_4
#define LED1 P0_3
#define LED2 P1_1
#define LED3 P10_6
#define LED_RED LED1
#define LED_BLUE LED3
#define LED_GREEN LED2
#define LED_BLUE LED3
#define SWITCH2 P0_4
#define USER_BUTTON SWITCH2
#define BUTTON1 USER_BUTTON
@ -85,23 +69,8 @@ typedef cyhal_gpio_t PinName;
#define STDIO_UART_CTS UART_CTS
#define STDIO_UART_RTS UART_RTS
#define CY_STDIO_UART_RX STDIO_UART_RX
#define CY_STDIO_UART_TX STDIO_UART_TX
#define CY_STDIO_UART_CTS STDIO_UART_CTS
#define CY_STDIO_UART_RTS STDIO_UART_RTS
#define CY_BT_UART_RX BT_UART_RX
#define CY_BT_UART_TX BT_UART_TX
#define CY_BT_UART_CTS BT_UART_CTS
#define CY_BT_UART_RTS BT_UART_RTS
#define CY_BT_PIN_POWER BT_PIN_POWER
#define CY_BT_PIN_HOST_WAKE BT_PIN_HOST_WAKE
#define CY_BT_PIN_DEVICE_WAKE BT_PIN_DEVICE_WAKE
#define USBTX UART_TX
#define USBRX UART_RX
#define CY_WIFI_HOST_WAKE P2_7
#endif

272
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST.c
View File

@ -28,13 +28,23 @@
extern "C" {
#endif
#ifdef SEMAPHORE
#include "cyabs_rtos.h"
#ifdef CY_RTOS_AWARE
#define NEVER_TIMEOUT ( (uint32_t)0xffffffffUL )
static cy_semaphore_t sdio_transfer_finished_semaphore;
#include "cyabs_rtos.h"
#define NEVER_TIMEOUT ( (uint32_t)0xffffffffUL )
static cy_semaphore_t sdio_transfer_finished_semaphore;
static bool sema_initialized = false;
#endif
/* Backup struct used to store and restore non retention UDB registers */
typedef struct
{
uint32_t CY_SDIO_UDB_WRKMULT_CTL_0;
uint32_t CY_SDIO_UDB_WRKMULT_CTL_1;
uint32_t CY_SDIO_UDB_WRKMULT_CTL_2;
uint32_t CY_SDIO_UDB_WRKMULT_CTL_3;
} stc_sdio_backup_regs_t;
/*Globals Needed for DMA */
/*DMA channel structures*/
@ -61,14 +71,63 @@ static uint8_t crcTable[256];
static uint32_t yCountRemainder;
static uint32_t yCounts;
/* Global value for card interrupt */
static uint8_t pfnCardInt_count = 0;
/*Global structure to store UDB registers */
static stc_sdio_backup_regs_t regs;
static uint32_t udb_initialized = 0;
cy_stc_syspm_callback_params_t sdio_pm_callback_params;
cy_stc_syspm_callback_t sdio_pm_callback_handler;
/* Deep Sleep Mode API Support */
static void SDIO_SaveConfig(void);
static void SDIO_RestoreConfig(void);
/*******************************************************************************
* Function Name: SDIO_DeepSleepCallback
****************************************************************************//**
*
* Callback executed during Deep Sleep entry/exit
*
* \note
* Saves/Restores SDIO UDB registers
*******************************************************************************/
cy_en_syspm_status_t SDIO_DeepSleepCallback(cy_stc_syspm_callback_params_t *params, cy_en_syspm_callback_mode_t mode)
{
cy_en_syspm_status_t status = CY_SYSPM_FAIL;
switch (mode)
{
case CY_SYSPM_CHECK_READY:
case CY_SYSPM_CHECK_FAIL:
status = CY_SYSPM_SUCCESS;
break;
case CY_SYSPM_BEFORE_TRANSITION:
SDIO_SaveConfig();
status = CY_SYSPM_SUCCESS;
break;
case CY_SYSPM_AFTER_TRANSITION:
SDIO_RestoreConfig();
status = CY_SYSPM_SUCCESS;
break;
default:
break;
}
return status;
}
/*******************************************************************************
* Function Name: SDIO_Init
****************************************************************************//**
*
* Initializes the SDIO hardware, and register the callback
* Initializes the SDIO hardware
*
* \param pfuCb
* Pointer to structure that holds pointers to callback function
@ -132,11 +191,6 @@ void SDIO_Init(stc_sdio_irq_cb_t* pfuCb)
SDIO_SetSdClkFrequency(400000);
SDIO_EnableIntClock();
SDIO_EnableSdClk();
/*Initalize the semaphore*/
#ifdef SEMAPHORE
cy_rtos_init_semaphore( &sdio_transfer_finished_semaphore, 1, 1 );
#endif
}
@ -560,41 +614,49 @@ void SDIO_InitDataTransfer(stc_sdio_data_config_t *pstcDataConfig)
*******************************************************************************/
en_sdio_result_t SDIO_SendCommandAndWait(stc_sdio_cmd_t *pstcCmd)
{
/*Store the command and data configurations*/
/* Store the command and data configurations*/
stc_sdio_cmd_config_t stcCmdConfig;
stc_sdio_data_config_t stcDataConfig;
#ifdef SEMAPHORE
en_sdio_result_t result;
#endif
/*variable used for holding timeout value*/
#ifndef SEMAPHORE
uint32_t u32Timeout = 0;
#endif
#ifndef SEMAPHORE_CMD
uint32_t u32CmdTimeout = 0;
#endif
/*Returns from various function calls*/
en_sdio_result_t enRet = Error;
en_sdio_result_t enRetTmp = Ok;
/*Hold value of if these checks are needed*/
/* Hold value of if these checks are needed */
uint8_t bCmdIndexCheck;
uint8_t bCmdCrcCheck;
static uint8_t u8responseBuf[6];
/*Clear statuses*/
/* Clear statuses */
gstcInternalData.stcEvents.u8CmdComplete = 0;
gstcInternalData.stcEvents.u8TransComplete = 0;
gstcInternalData.stcEvents.u8CRCError = 0;
/*Setup the command configuration*/
/* Setup the command configuration */
stcCmdConfig.u8CmdIndex = (uint8_t)pstcCmd->u32CmdIdx;
stcCmdConfig.u32Argument = pstcCmd->u32Arg;
#ifdef CY_RTOS_AWARE
cy_rslt_t result;
/* Initialize the semaphore. This is not done in init because init is called
* in interrupt thread. cy_rtos_init_semaphore call is prohibited in
* interrupt thread.
*/
if(!sema_initialized)
{
cy_rtos_init_semaphore( &sdio_transfer_finished_semaphore, 1, 0 );
sema_initialized = true;
}
#else
/* Variable used for holding timeout value */
uint32_t u32Timeout = 0;
#endif
/*Determine the type of response and if we need to do any checks*/
/*Command 0 and 8 have no response, so don't wait for one*/
if (pstcCmd->u32CmdIdx == 0 || pstcCmd->u32CmdIdx == 8)
@ -694,28 +756,39 @@ en_sdio_result_t SDIO_SendCommandAndWait(stc_sdio_cmd_t *pstcCmd)
SDIO_CONTROL_REG |= SDIO_CTRL_ENABLE_WRITE;
}
#ifndef SEMAPHORE
/*Wait for the transfer to finish*/
#ifdef CY_RTOS_AWARE
/* Wait for the transfer to finish.
* Acquire semaphore and wait until it will be released
* in SDIO_IRQ:
* 1. sdio_transfer_finished_semaphore count is equal to
* zero. cy_rtos_get_semaphore waits until semaphore
* count is increased by cy_rtos_set_semaphore() in
* SDIO_IRQ.
* 2. The cy_rtos_set_semaphore() increases
* sdio_transfer_finished_semaphore count.
* 3. The cy_rtos_get_semaphore() function decreases
* sdio_transfer_finished_semaphore back to zero
* and exit. Or timeout occurs
*/
result = cy_rtos_get_semaphore( &sdio_transfer_finished_semaphore, 10, false );
enRetTmp = SDIO_CheckForEvent(SdCmdEventTransferDone);
if (result != CY_RSLT_SUCCESS)
#else
/* Wait for the transfer to finish */
do
{
u32Timeout++;
enRetTmp = SDIO_CheckForEvent(SdCmdEventTransferDone);
} while (!((enRetTmp == Ok) || (enRetTmp == DataCrcError) || (u32Timeout >= SDIO_DAT_TIMEOUT)));
/*if it was a read it is possible there is still extra data hanging out, trigger the
DMA again. This can result in extra data being transfered so the read buffer should be
3 bytes bigger than needed*/
if (pstcCmd->bRead == true)
{
Cy_TrigMux_SwTrigger((uint32_t)SDIO_HOST_Read_DMA_DW__TR_IN, 2);
}
if (u32Timeout == SDIO_DAT_TIMEOUT)
#else
result = cy_rtos_get_semaphore( &sdio_transfer_finished_semaphore, 10, false );
enRetTmp = SDIO_CheckForEvent(SdCmdEventTransferDone);
#endif
{
enRet |= DataTimeout;
}
/* if it was a read it is possible there is still extra data hanging out, trigger the
DMA again. This can result in extra data being transfered so the read buffer should be
@ -725,12 +798,6 @@ en_sdio_result_t SDIO_SendCommandAndWait(stc_sdio_cmd_t *pstcCmd)
Cy_TrigMux_SwTrigger((uint32_t)SDIO_HOST_Read_DMA_DW__TR_IN, 2);
}
if (result != Ok)
#endif
{
enRet |= DataTimeout;
}
if (enRetTmp == DataCrcError)
{
enRet |= DataCrcError;
@ -741,8 +808,7 @@ en_sdio_result_t SDIO_SendCommandAndWait(stc_sdio_cmd_t *pstcCmd)
} /*No Response Required, thus no CMD53*/
} /*CMD Passed*/
#ifndef SEMAPHORE
#ifndef CY_RTOS_AWARE
u32Timeout = 0;
#endif
@ -1161,63 +1227,72 @@ void SDIO_IRQ(void)
{
uint8_t u8Status;
/*first read the status register*/
/* First read the status register */
u8Status = SDIO_STATUS_REG;
/*Check card interrupt*/
/* Check card interrupt */
if (u8Status & SDIO_STS_CARD_INT )
{
pfnCardInt_count++;
}
/* Execute card interrupt callback if neccesary */
if (0 != pfnCardInt_count)
{
if (NULL != gstcInternalData.pstcCallBacks.pfnCardIntCb)
{
gstcInternalData.pstcCallBacks.pfnCardIntCb();
}
pfnCardInt_count--;
}
/*If the command is complete set the flag*/
/* If the command is complete set the flag */
if (u8Status & SDIO_STS_CMD_DONE)
{
gstcInternalData.stcEvents.u8CmdComplete++;
}
/*Check if a write is complete*/
/* Check if a write is complete */
if (u8Status & SDIO_STS_WRITE_DONE )
{
/*Clear the Write flag and CMD53 flag*/
/* Clear the Write flag and CMD53 flag */
SDIO_CONTROL_REG &= ~(SDIO_CTRL_ENABLE_WRITE | SDIO_CTRL_ENABLE_INT);
/*Check if the CRC status return was bad*/
if (u8Status & SDIO_STS_CRC_ERR )
{
/*CRC was bad, set the flag*/
gstcInternalData.stcEvents.u8CRCError++;
}
/*set the done flag*/
#ifdef SEMAPHORE
cy_rtos_set_semaphore( &sdio_transfer_finished_semaphore, true );
#else
gstcInternalData.stcEvents.u8TransComplete++;
#endif
}
/*Check if a read is complete*/
if (u8Status & SDIO_STS_READ_DONE)
{
/*Clear the read flag*/
SDIO_CONTROL_REG &= ~(SDIO_CTRL_ENABLE_READ| SDIO_CTRL_ENABLE_INT);
/*check the CRC*/
/* Check if the CRC status return was bad */
if (u8Status & SDIO_STS_CRC_ERR)
{
/*CRC was bad, set the flag*/
/* CRC was bad, set the flag */
gstcInternalData.stcEvents.u8CRCError++;
}
/*Okay we're done so set the done flag*/
#ifdef SEMAPHORE
/* Set the done flag */
#ifdef CY_RTOS_AWARE
cy_rtos_set_semaphore( &sdio_transfer_finished_semaphore, true );
#else
#else
gstcInternalData.stcEvents.u8TransComplete++;
#endif
#endif
}
/* Check if a read is complete */
if (u8Status & SDIO_STS_READ_DONE)
{
/* Clear the read flag */
SDIO_CONTROL_REG &= ~(SDIO_CTRL_ENABLE_READ| SDIO_CTRL_ENABLE_INT);
/* Check the CRC */
if (u8Status & SDIO_STS_CRC_ERR)
{
/* CRC was bad, set the flag */
gstcInternalData.stcEvents.u8CRCError++;
}
/* Okay we're done so set the done flag */
#ifdef CY_RTOS_AWARE
cy_rtos_set_semaphore( &sdio_transfer_finished_semaphore, true );
#else
gstcInternalData.stcEvents.u8TransComplete++;
#endif
}
NVIC_ClearPendingIRQ((IRQn_Type) SDIO_HOST_sdio_int__INTC_NUMBER);
@ -1286,7 +1361,6 @@ void SDIO_READ_DMA_IRQ(void)
yCounts--;
}
void SDIO_WRITE_DMA_IRQ(void)
{
/*We shouldn't have to change anything unless it is the last descriptor*/
@ -1348,6 +1422,46 @@ void SDIO_WRITE_DMA_IRQ(void)
yCounts--;
}
void SDIO_Free(void)
{
#ifdef CY_RTOS_AWARE
cy_rtos_deinit_semaphore(&sdio_transfer_finished_semaphore);
#endif
}
/*******************************************************************************
* Function Name: SDIO_SaveConfig
********************************************************************************
*
* Saves the user configuration of the SDIO UDB non-retention registers. Call the
* SDIO_SaveConfig() function before the Cy_SysPm_CpuEnterDeepSleep() function.
*
*******************************************************************************/
static void SDIO_SaveConfig(void)
{
regs.CY_SDIO_UDB_WRKMULT_CTL_0 = UDB->WRKMULT.CTL[0];
regs.CY_SDIO_UDB_WRKMULT_CTL_1 = UDB->WRKMULT.CTL[1];
regs.CY_SDIO_UDB_WRKMULT_CTL_2 = UDB->WRKMULT.CTL[2];
regs.CY_SDIO_UDB_WRKMULT_CTL_3 = UDB->WRKMULT.CTL[3];
}
/*******************************************************************************
* Function Name: SDIO_RestoreConfig
********************************************************************************
*
* Restores the user configuration of the SDIO UDB non-retention registers. Call
* the SDIO_Wakeup() function after the Cy_SysPm_CpuEnterDeepSleep() function.
*
*******************************************************************************/
static void SDIO_RestoreConfig(void)
{
UDB->WRKMULT.CTL[0] = regs.CY_SDIO_UDB_WRKMULT_CTL_0;
UDB->WRKMULT.CTL[1] = regs.CY_SDIO_UDB_WRKMULT_CTL_1;
UDB->WRKMULT.CTL[2] = regs.CY_SDIO_UDB_WRKMULT_CTL_2;
UDB->WRKMULT.CTL[3] = regs.CY_SDIO_UDB_WRKMULT_CTL_3;
}
#if defined(__cplusplus)
}
#endif

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST.h
View File

@ -35,7 +35,6 @@
/**
* \defgroup group_udb_sdio UDB_SDIO
* \ingroup group_bsp
* \{
* SDIO - Secure Digital Input Output Is a standard for communicating with various
external devices such as Wifi and bluetooth devices.
@ -272,6 +271,7 @@ void SDIO_SetSdClkFrequency(uint32_t u32SdClkFreqHz);
void SDIO_Reset(void);
void SDIO_EnableChipInt(void);
void SDIO_DisableChipInt(void);
void SDIO_Free(void);
/*Low Level Functions*/
void SDIO_SendCommand(stc_sdio_cmd_config_t *pstcCmdConfig);
@ -293,6 +293,8 @@ void SDIO_WRITE_DMA_IRQ(void);
void SDIO_Crc7Init(void);
cy_en_syspm_status_t SDIO_DeepSleepCallback(cy_stc_syspm_callback_params_t *params, cy_en_syspm_callback_mode_t mode);
/** \endcond */
/** \} group_udb_sdio_functions */

91
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/cybsp_types.h
View File

@ -3,7 +3,7 @@
*
* Description:
* Provides APIs for interacting with the hardware contained on the Cypress
* CYW943012P6EVB-01 pioneer kit.
* CYW943012P6EVB-01 evaluation kit.
*
********************************************************************************
* \copyright
@ -23,14 +23,6 @@
* limitations under the License.
*******************************************************************************/
/**
* \addtogroup group_bsp_cyw943012p6evb_01 CYW943012P6EVB-01
* \ingroup group_bsp
* \{
* \defgroup group_bsp_cyw943012p6evb_01_macros Macros
* \defgroup group_bsp_cyw943012p6evb_01_enums Enumerated Types
*/
#pragma once
#include "cyhal.h"
@ -40,10 +32,56 @@ extern "C" {
#endif
/**
* \addtogroup group_bsp_cyw943012p6evb_01_macros
* \addtogroup group_bsp_pins Pin Mappings
* \{
*/
// Arduino connector namings
/** Arduino A0 */
#define CYBSP_A0 P10_0
/** Arduino A1 */
#define CYBSP_A1 P10_1
/** Arduino A2 */
#define CYBSP_A2 P6_4
/** Arduino A3 */
#define CYBSP_A3 P6_5
/** Arduino A4 */
#define CYBSP_A4 P10_4
/** Arduino A5 */
#define CYBSP_A5 P10_5
/** Arduino D0 */
#define CYBSP_D0 P5_0
/** Arduino D1 */
#define CYBSP_D1 P5_1
/** Arduino D2 */
#define CYBSP_D2 P5_2
/** Arduino D3 */
#define CYBSP_D3 P5_3
/** Arduino D4 */
#define CYBSP_D4 P5_4
/** Arduino D5 */
#define CYBSP_D5 P5_5
/** Arduino D6 */
#define CYBSP_D6 P5_6
/** Arduino D7 */
#define CYBSP_D7 P5_7
/** Arduino D8 */
#define CYBSP_D8 NC
/** Arduino D9 */
#define CYBSP_D9 NC
/** Arduino D10 */
#define CYBSP_D10 P0_5
/** Arduino D11 */
#define CYBSP_D11 P0_2
/** Arduino D12 */
#define CYBSP_D12 P0_3
/** Arduino D13 */
#define CYBSP_D13 P0_4
/** Arduino D14 */
#define CYBSP_D14 P1_0
/** Arduino D15 */
#define CYBSP_D15 P1_1
// Generic signal names
/** Pin: CYBSP_WCO_IN */
#define CYBSP_WCO_IN P0_0
@ -62,18 +100,25 @@ extern "C" {
#define CYBSP_WL_SECI_OUT P1_5
/** Pin: CYBSP_WIFI_SDIO_D0 */
/* Corresponds to: ioss[0].port[2].pin[0], udb[0] */
#define CYBSP_WIFI_SDIO_D0 P2_0
/** Pin: CYBSP_WIFI_SDIO_D1 */
/* Corresponds to: ioss[0].port[2].pin[1], udb[0] */
#define CYBSP_WIFI_SDIO_D1 P2_1
/** Pin: CYBSP_WIFI_SDIO_D2 */
/* Corresponds to: ioss[0].port[2].pin[2], udb[0] */
#define CYBSP_WIFI_SDIO_D2 P2_2
/** Pin: CYBSP_WIFI_SDIO_D3 */
/* Corresponds to: ioss[0].port[2].pin[3], udb[0] */
#define CYBSP_WIFI_SDIO_D3 P2_3
/** Pin: CYBSP_WIFI_SDIO_CMD */
/* Corresponds to: ioss[0].port[2].pin[4], udb[0] */
#define CYBSP_WIFI_SDIO_CMD P2_4
/** Pin: CYBSP_WIFI_SDIO_CLK */
/* Corresponds to: ioss[0].port[2].pin[5], udb[0] */
#define CYBSP_WIFI_SDIO_CLK P2_5
/** Pin: CYBSP_WIFI_WL_REG_ON */
/* Corresponds to: ioss[0].port[2].pin[6], udb[0] */
#define CYBSP_WIFI_WL_REG_ON P2_6
/** Pin: CYBSP_WIFI_HOST_WAKE */
#define CYBSP_WIFI_HOST_WAKE P2_7
@ -90,20 +135,22 @@ extern "C" {
#define CYBSP_BT_UART_RTS P3_2
/** Pin: CYBSP_BT_UART_CTS */
#define CYBSP_BT_UART_CTS P3_3
/** Pin: CYBSP_BT_REG_ON */
#define CYBSP_BT_REG_ON P3_4
/** Pin: BT Power */
#define CYBSP_BT_POWER P3_4
/** Pin: CYBSP_BT_HOST_WAKE */
#define CYBSP_BT_HOST_WAKE P3_5
/** Pin: CYBSP_BT_DEVICE_WAKE */
#define CYBSP_BT_DEVICE_WAKE P4_0
/** Pin: CYBSP_BT_RST */
#define CYBSP_BT_RST P4_1
/** Pin: UART RX */
#define CYBSP_DEBUG_UART_RX P5_0
/* Corresponds to: ioss[0].port[13].pin[0], scb[6] */
#define CYBSP_DEBUG_UART_RX P13_0
/** Pin: UART TX */
#define CYBSP_DEBUG_UART_TX P5_1
/* Corresponds to: ioss[0].port[13].pin[1], scb[6] */
#define CYBSP_DEBUG_UART_TX P13_1
/** Pin: CYBSP_I2C_SCL */
#define CYBSP_I2C_SCL P6_0
@ -193,8 +240,10 @@ extern "C" {
#define CYBSP_ECO_OUT P12_7
/** Pin: CYBSP_P6_UART_RX */
/* Corresponds to: ioss[0].port[13].pin[0], scb[6] */
#define CYBSP_P6_UART_RX P13_0
/** Pin: CYBSP_P6_UART_TX */
/* Corresponds to: ioss[0].port[13].pin[1], scb[6] */
#define CYBSP_P6_UART_TX P13_1
/** Pin: CYBSP_USB_DEV_VBUS_DET */
#define CYBSP_USB_DEV_VBUS_DET P13_4
@ -208,10 +257,10 @@ extern "C" {
/** Pin: CYBSP_USB_DM */
#define CYBSP_USB_DM P14_1
/** \} group_bsp_cyw943012p6evb_01_macros */
/** \} group_bsp_pins */
/**
* \addtogroup group_bsp_cyw943012p6evb_01_enums
* \addtogroup group_bsp_enums Enumerated Types
* \{
*/
@ -236,8 +285,11 @@ typedef enum
CYBSP_LED_RGB_GREEN = P1_1,
CYBSP_LED_RGB_BLUE = P10_6,
/* Corresponds to: ioss[0].port[0].pin[3] */
CYBSP_USER_LED1 = CYBSP_LED_RGB_RED,
/* Corresponds to: ioss[0].port[1].pin[1] */
CYBSP_USER_LED2 = CYBSP_LED_RGB_GREEN,
/* Corresponds to: ioss[0].port[10].pin[6] */
CYBSP_USER_LED3 = CYBSP_LED_RGB_BLUE,
CYBSP_USER_LED = CYBSP_USER_LED1,
} cybsp_led_t;
@ -247,14 +299,13 @@ typedef enum
{
CYBSP_SW6 = P0_4,
/* Corresponds to: ioss[0].port[0].pin[4] */
CYBSP_USER_BTN1 = CYBSP_SW6,
CYBSP_USER_BTN = CYBSP_USER_BTN1,
} cybsp_btn_t;
/** \} group_bsp_cyw943012p6evb_01_enums */
/** \} group_bsp_enums */
#if defined(__cplusplus)
}
#endif
/** \} group_bsp_cyw943012p6evb_01 */

147
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_udb_sdio.c
View File

@ -129,6 +129,99 @@ const cy_stc_gpio_pin_config_t pin_clk_config =
* Internal functions
*******************************************************************************/
static void cyhal_free_pins(cyhal_sdio_t *obj);
static cy_en_syspm_status_t cyhal_sdio_ds_callback(cy_stc_syspm_callback_params_t *callbackParams, cy_en_syspm_callback_mode_t mode);
/******************************************************************************
* Parameter structure for Deep Sleep callback function
******************************************************************************/
static cy_stc_syspm_callback_params_t cyhal_sdio_pm_callback_params =
{
NULL,
NULL
};
/******************************************************************************
* Deep Sleep callback
******************************************************************************/
static cy_stc_syspm_callback_t cyhal_sdio_pm_callback =
{
&cyhal_sdio_ds_callback,
CY_SYSPM_DEEPSLEEP,
0U,
&cyhal_sdio_pm_callback_params,
NULL,
NULL,
CYHAL_SDIO_DS_CB_ORDER
};
/* Internal deep sleep callback, which does following:
* 1. Save/restore not retained configuration registers in the Deep Sleep
* 2. Execute registered callback with CYHAL_SDIO_GOING_DOWN event, before
* entering into Deep Sleep
* 3. Execute registered callback with CYHAL_SDIO_COMING_UP event, after
* exit from Deep Sleep
* */
cy_en_syspm_status_t cyhal_sdio_ds_callback(cy_stc_syspm_callback_params_t *callbackParams, cy_en_syspm_callback_mode_t mode)
{
cy_en_syspm_status_t retVal = SDIO_DeepSleepCallback(callbackParams, mode);
if (retVal == CY_SYSPM_SUCCESS)
{
switch (mode)
{
case CY_SYSPM_CHECK_READY:
{
/* Check if transfer is pending */
if (!op_pending)
{
/* Execute callback to indicate that interface is going down */
if ((cyhal_sdio_callback != NULL) && (0U != (cyhal_sdio_config_struct->events & (uint32_t) CYHAL_SDIO_GOING_DOWN)))
{
(void)(cyhal_sdio_callback)(cyhal_sdio_callback_args, CYHAL_SDIO_GOING_DOWN);
}
/* Indicate Deep Sleep entering */
deep_sleep_pending = true;
}
else
{
retVal = CY_SYSPM_FAIL;
}
break;
}
case CY_SYSPM_BEFORE_TRANSITION:
{
/* Nothing to do in this mode */
break;
}
case CY_SYSPM_AFTER_TRANSITION:
case CY_SYSPM_CHECK_FAIL:
{
/* Execute this only if check ready case was executed */
if (deep_sleep_pending)
{
/* Execute callback to indicate that interface is coming up */
if ((cyhal_sdio_callback != NULL) && (0U != (cyhal_sdio_config_struct->events & (uint32_t) CYHAL_SDIO_COMING_UP)))
{
(void)(cyhal_sdio_callback)(cyhal_sdio_callback_args, CYHAL_SDIO_COMING_UP);
}
/* Indicate Deep Sleep exit */
deep_sleep_pending = false;
}
break;
}
default:
break;
}
}
return retVal;
}
/*******************************************************************************
* Dispatcher Interrupt Callbacks Service Routine
@ -392,6 +485,15 @@ cy_rslt_t cyhal_sdio_init(cyhal_sdio_t *obj, cyhal_gpio_t cmd, cyhal_gpio_t clk,
/* Initialize interrupt cause and events */
obj->irq_cause = 0u;
obj->events = 0u;
/* Register SDIO Deep Sleep Callback */
if (retVal == CY_RSLT_SUCCESS)
{
if (!Cy_SysPm_RegisterCallback(&cyhal_sdio_pm_callback))
{
retVal = CY_RSLT_TYPE_ERROR;
}
}
}
}
@ -415,6 +517,10 @@ void cyhal_sdio_free(cyhal_sdio_t *obj)
cyhal_free_clocks(obj);
cyhal_free_dmas(obj);
cyhal_hwmgr_free(&(obj->resource));
SDIO_Free();
/* Unregister SDIO Deep Sleep Callback */
(void)Cy_SysPm_UnregisterCallback(&cyhal_sdio_pm_callback);
}
cy_rslt_t cyhal_sdio_configure(cyhal_sdio_t *obj, const cyhal_sdio_cfg_t *config)
@ -437,6 +543,7 @@ cy_rslt_t cyhal_sdio_configure(cyhal_sdio_t *obj, const cyhal_sdio_cfg_t *config
return CY_RSLT_SUCCESS;
}
cy_rslt_t cyhal_sdio_send_cmd(const cyhal_sdio_t *obj, cyhal_transfer_t direction, cyhal_sdio_command_t command, uint32_t argument, uint32_t* response)
{
CY_ASSERT(NULL != obj);
@ -448,7 +555,13 @@ cy_rslt_t cyhal_sdio_send_cmd(const cyhal_sdio_t *obj, cyhal_transfer_t directio
uint32_t cmdResponse;
stc_sdio_cmd_t cmd;
en_sdio_result_t status;
cy_rslt_t retVal = CY_RSLT_SUCCESS;
cy_rslt_t retVal = CYHAL_SDIO_RSLT_CANCELED;
/* Check other pending operations */
if (!op_pending)
{
/* Indicate pending operation to prevent entering into Deep Sleep */
op_pending = true;
if (response != NULL)
{
@ -463,17 +576,29 @@ cy_rslt_t cyhal_sdio_send_cmd(const cyhal_sdio_t *obj, cyhal_transfer_t directio
cmd.u16BlockCnt = 0U; /* Not used */
cmd.u16BlockSize = 0U; /* Not used */
/* Send command only if there is no attempts to enter into Deep Sleep */
if (!deep_sleep_pending)
{
status = SDIO_SendCommandAndWait(&cmd);
if (Ok != status)
{
retVal = CYHAL_SDIO_RSLT_ERR_FUNC_RET(status);
}
else
{
retVal = CY_RSLT_SUCCESS;
}
if (response != NULL)
{
*response = cmdResponse;
}
}
/* Indicate finished operation */
op_pending = false;
}
return retVal;
}
@ -481,11 +606,16 @@ cy_rslt_t cyhal_sdio_send_cmd(const cyhal_sdio_t *obj, cyhal_transfer_t directio
cy_rslt_t cyhal_sdio_bulk_transfer(cyhal_sdio_t *obj, cyhal_transfer_t direction, uint32_t argument, const uint32_t* data, uint16_t length, uint32_t* response)
{
CY_ASSERT(NULL != obj);
cy_rslt_t retVal = CYHAL_SDIO_RSLT_CANCELED;
/* Check other pending operations */
if (!op_pending)
{
/* Indicate pending operation to prevent entering into Deep Sleep */
op_pending = true;
stc_sdio_cmd_t cmd;
en_sdio_result_t status;
uint32_t cmdResponse;
cy_rslt_t retVal = CY_RSLT_SUCCESS;
if (response != NULL)
{
@ -512,17 +642,30 @@ cy_rslt_t cyhal_sdio_bulk_transfer(cyhal_sdio_t *obj, cyhal_transfer_t direction
cmd.u16BlockSize = length;
}
/* Start transfer only if there is no attempts to enter into Deep Sleep */
if (!deep_sleep_pending)
{
status = SDIO_SendCommandAndWait(&cmd);
if (Ok != status)
{
retVal = CYHAL_SDIO_RSLT_ERR_FUNC_RET(status);
}
else
{
retVal = CY_RSLT_SUCCESS;
}
if (response != NULL)
{
*response = cmdResponse;
}
}
/* Indicate finished transfer */
op_pending = false;
}
return retVal;
}