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Avoid the FPGA tester using hardware CS which is not supported 

Also implement rudimentary spi_free...
pull/11110/head
Steven Cooreman 2019-07-09 22:48:37 +01:00 committed by Evelyne Donnaes
parent a5cb9d47ac
commit ace88aa880
1 changed files with 9 additions and 1 deletions
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10
targets/TARGET_Silicon_Labs/TARGET_EFM32/spi_api.c
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@ -274,6 +274,12 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName clk, PinName cs)
spi_enable(obj, true); spi_enable(obj, true);
} }
void spi_free(spi_t *obj)
{
spi_enable(obj, false);
USART_Reset(obj->spi.spi);
}
void spi_enable_event(spi_t *obj, uint32_t event, uint8_t enable) void spi_enable_event(spi_t *obj, uint32_t event, uint8_t enable)
{ {
if(enable) obj->spi.event |= event; if(enable) obj->spi.event |= event;
@ -1434,7 +1440,9 @@ const PinMap *spi_master_miso_pinmap()
const PinMap *spi_master_clk_pinmap() const PinMap *spi_master_clk_pinmap()
{ {
return PinMap_SPI_CLK; // We don't currently support hardware CS in master mode.
static const PinMap PinMap_SPI_CLK_mod[] = {NC , NC , NC};
return PinMap_SPI_CLK_mod;
} }
const PinMap *spi_master_cs_pinmap() const PinMap *spi_master_cs_pinmap()