mirror of https://github.com/ARMmbed/mbed-os.git
Add support for GCC ARM
Michael Brudevold
parent
5d6ee64bf1
commit
ac7da3e5d8
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@ -0,0 +1,151 @@
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/* Linker script for STM32F405 */
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/* Linker script to configure memory regions. */
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MEMORY
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{
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FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
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CCM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K
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RAM (rwx) : ORIGIN = 0x20000188, LENGTH = 128K - 0x188
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}
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/* Linker script to place sections and symbol values. Should be used together
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* with other linker script that defines memory regions FLASH and RAM.
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* It references following symbols, which must be defined in code:
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* Reset_Handler : Entry of reset handler
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*
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* It defines following symbols, which code can use without definition:
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* __exidx_start
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* __exidx_end
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* __etext
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* __data_start__
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* __preinit_array_start
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* __preinit_array_end
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* __init_array_start
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* __init_array_end
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* __fini_array_start
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* __fini_array_end
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* __data_end__
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* __bss_start__
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* __bss_end__
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* __end__
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* end
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* __HeapLimit
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* __StackLimit
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* __StackTop
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* __stack
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*/
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ENTRY(Reset_Handler)
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SECTIONS
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{
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.text :
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{
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KEEP(*(.isr_vector))
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*(.text*)
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KEEP(*(.init))
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KEEP(*(.fini))
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/* .ctors */
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*crtbegin.o(.ctors)
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*crtbegin?.o(.ctors)
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*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
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*(SORT(.ctors.*))
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*(.ctors)
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/* .dtors */
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*crtbegin.o(.dtors)
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*crtbegin?.o(.dtors)
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*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
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*(SORT(.dtors.*))
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*(.dtors)
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*(.rodata*)
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KEEP(*(.eh_frame*))
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} > FLASH
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.ARM.extab :
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{
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*(.ARM.extab* .gnu.linkonce.armextab.*)
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} > FLASH
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__exidx_start = .;
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.ARM.exidx :
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{
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*(.ARM.exidx* .gnu.linkonce.armexidx.*)
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} > FLASH
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__exidx_end = .;
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__etext = .;
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.data : AT (__etext)
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{
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__data_start__ = .;
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*(vtable)
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*(.data*)
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. = ALIGN(4);
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/* preinit data */
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PROVIDE_HIDDEN (__preinit_array_start = .);
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KEEP(*(.preinit_array))
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PROVIDE_HIDDEN (__preinit_array_end = .);
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. = ALIGN(4);
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/* init data */
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PROVIDE_HIDDEN (__init_array_start = .);
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KEEP(*(SORT(.init_array.*)))
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KEEP(*(.init_array))
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PROVIDE_HIDDEN (__init_array_end = .);
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. = ALIGN(4);
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/* finit data */
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PROVIDE_HIDDEN (__fini_array_start = .);
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KEEP(*(SORT(.fini_array.*)))
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KEEP(*(.fini_array))
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PROVIDE_HIDDEN (__fini_array_end = .);
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KEEP(*(.jcr*))
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. = ALIGN(4);
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/* All data end */
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__data_end__ = .;
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} > RAM
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.bss :
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{
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. = ALIGN(4);
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__bss_start__ = .;
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*(.bss*)
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*(COMMON)
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. = ALIGN(4);
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__bss_end__ = .;
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} > RAM
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.heap (COPY):
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{
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__end__ = .;
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end = __end__;
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*(.heap*)
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__HeapLimit = .;
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} > RAM
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/* .stack_dummy section doesn't contains any symbols. It is only
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* used for linker to calculate size of stack sections, and assign
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* values to stack symbols later */
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.stack_dummy (COPY):
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{
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*(.stack*)
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} > RAM
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/* Set stack top to end of RAM, and stack limit move down by
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* size of stack_dummy section */
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__StackTop = ORIGIN(RAM) + LENGTH(RAM);
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__StackLimit = __StackTop - SIZEOF(.stack_dummy);
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PROVIDE(__stack = __StackTop);
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/* Check if data + heap + stack exceeds RAM limit */
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ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
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}
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@ -0,0 +1,316 @@
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/* File: startup_STM32F40x.S
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* Purpose: startup file for Cortex-M4 devices. Should use with
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* GCC for ARM Embedded Processors
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* Version: V1.4
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* Date: 09 July 2012
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*
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* Copyright (c) 2011, 2012, ARM Limited
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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* Neither the name of the ARM Limited nor the
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names of its contributors may be used to endorse or promote products
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derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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.syntax unified
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.arch armv7-m
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.section .stack
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.align 3
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#ifdef __STACK_SIZE
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.equ Stack_Size, __STACK_SIZE
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#else
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.equ Stack_Size, 0xc00
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#endif
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.globl __StackTop
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.globl __StackLimit
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__StackLimit:
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.space Stack_Size
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.size __StackLimit, . - __StackLimit
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__StackTop:
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.size __StackTop, . - __StackTop
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.section .heap
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.align 3
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#ifdef __HEAP_SIZE
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.equ Heap_Size, __HEAP_SIZE
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#else
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.equ Heap_Size, 0
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#endif
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.globl __HeapBase
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.globl __HeapLimit
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__HeapBase:
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.if Heap_Size
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.space Heap_Size
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.endif
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.size __HeapBase, . - __HeapBase
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__HeapLimit:
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.size __HeapLimit, . - __HeapLimit
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.section .isr_vector
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.align 2
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.globl __isr_vector
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__isr_vector:
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.long __StackTop /* Top of Stack */
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.long Reset_Handler /* Reset Handler */
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.long NMI_Handler /* NMI Handler */
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.long HardFault_Handler /* Hard Fault Handler */
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.long MemManage_Handler /* MPU Fault Handler */
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.long BusFault_Handler /* Bus Fault Handler */
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.long UsageFault_Handler /* Usage Fault Handler */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long SVC_Handler /* SVCall Handler */
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.long DebugMon_Handler /* Debug Monitor Handler */
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.long 0 /* Reserved */
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.long PendSV_Handler /* PendSV Handler */
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.long SysTick_Handler /* SysTick Handler */
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/* External interrupts */
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.long WWDG_IRQHandler /* Window WatchDog */
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.long PVD_IRQHandler /* PVD through EXTI Line detection */
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.long TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
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.long RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
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.long FLASH_IRQHandler /* FLASH */
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.long RCC_IRQHandler /* RCC */
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.long EXTI0_IRQHandler /* EXTI Line0 */
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.long EXTI1_IRQHandler /* EXTI Line1 */
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.long EXTI2_IRQHandler /* EXTI Line2 */
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.long EXTI3_IRQHandler /* EXTI Line3 */
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.long EXTI4_IRQHandler /* EXTI Line4 */
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.long DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
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.long DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
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.long DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
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.long DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
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.long DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
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.long DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
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.long DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
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.long ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
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.long CAN1_TX_IRQHandler /* CAN1 TX */
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.long CAN1_RX0_IRQHandler /* CAN1 RX0 */
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.long CAN1_RX1_IRQHandler /* CAN1 RX1 */
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.long CAN1_SCE_IRQHandler /* CAN1 SCE */
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.long EXTI9_5_IRQHandler /* External Line[9:5]s */
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.long TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
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.long TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
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.long TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
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.long TIM1_CC_IRQHandler /* TIM1 Capture Compare */
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.long TIM2_IRQHandler /* TIM2 */
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.long TIM3_IRQHandler /* TIM3 */
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.long TIM4_IRQHandler /* TIM4 */
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.long I2C1_EV_IRQHandler /* I2C1 Event */
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.long I2C1_ER_IRQHandler /* I2C1 Error */
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.long I2C2_EV_IRQHandler /* I2C2 Event */
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.long I2C2_ER_IRQHandler /* I2C2 Error */
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.long SPI1_IRQHandler /* SPI1 */
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.long SPI2_IRQHandler /* SPI2 */
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.long USART1_IRQHandler /* USART1 */
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.long USART2_IRQHandler /* USART2 */
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.long USART3_IRQHandler /* USART3 */
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.long EXTI15_10_IRQHandler /* External Line[15:10]s */
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.long RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
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.long OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
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.long TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
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.long TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
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.long TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
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.long TIM8_CC_IRQHandler /* TIM8 Capture Compare */
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.long DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
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.long FSMC_IRQHandler /* FSMC */
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.long SDIO_IRQHandler /* SDIO */
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.long TIM5_IRQHandler /* TIM5 */
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.long SPI3_IRQHandler /* SPI3 */
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.long UART4_IRQHandler /* UART4 */
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.long UART5_IRQHandler /* UART5 */
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.long TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
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.long TIM7_IRQHandler /* TIM7 */
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.long DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
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.long DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
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.long DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
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.long DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
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.long DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long CAN2_TX_IRQHandler /* CAN2 TX */
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.long CAN2_RX0_IRQHandler /* CAN2 RX0 */
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.long CAN2_RX1_IRQHandler /* CAN2 RX1 */
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.long CAN2_SCE_IRQHandler /* CAN2 SCE */
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.long OTG_FS_IRQHandler /* USB OTG FS */
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.long DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
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.long DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
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.long DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
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.long USART6_IRQHandler /* USART6 */
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.long I2C3_EV_IRQHandler /* I2C3 event */
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.long I2C3_ER_IRQHandler /* I2C3 error */
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.long OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
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.long OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
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.long OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
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.long OTG_HS_IRQHandler /* USB OTG HS */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long HASH_RNG_IRQHandler /* Hash and Rng */
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.long FPU_IRQHandler /* FPU */
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.size __isr_vector, . - __isr_vector
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.text
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.thumb
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.thumb_func
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.align 2
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.globl Reset_Handler
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.type Reset_Handler, %function
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Reset_Handler:
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/* Loop to copy data from read only memory to RAM. The ranges
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* of copy from/to are specified by following symbols evaluated in
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* linker script.
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* __etext: End of code section, i.e., begin of data sections to copy from.
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* __data_start__/__data_end__: RAM address range that data should be
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* copied to. Both must be aligned to 4 bytes boundary. */
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ldr r1, =__etext
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ldr r2, =__data_start__
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ldr r3, =__data_end__
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.LC0:
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cmp r2, r3
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ittt lt
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ldrlt r0, [r1], #4
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strlt r0, [r2], #4
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blt .LC0
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ldr r0, =SystemInit
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blx r0
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ldr r0, =_start
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bx r0
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.pool
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.size Reset_Handler, . - Reset_Handler
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.text
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/* Macro to define default handlers. Default handler
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* will be weak symbol and just dead loops. They can be
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* overwritten by other handlers */
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.macro def_default_handler handler_name
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.align 1
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.thumb_func
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.weak \handler_name
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.type \handler_name, %function
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\handler_name :
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b .
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.size \handler_name, . - \handler_name
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.endm
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def_default_handler NMI_Handler
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def_default_handler HardFault_Handler
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def_default_handler MemManage_Handler
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||||||
|
def_default_handler BusFault_Handler
|
||||||
|
def_default_handler UsageFault_Handler
|
||||||
|
def_default_handler SVC_Handler
|
||||||
|
def_default_handler DebugMon_Handler
|
||||||
|
def_default_handler PendSV_Handler
|
||||||
|
def_default_handler SysTick_Handler
|
||||||
|
def_default_handler Default_Handler
|
||||||
|
|
||||||
|
.macro def_irq_default_handler handler_name
|
||||||
|
.weak \handler_name
|
||||||
|
.set \handler_name, Default_Handler
|
||||||
|
.endm
|
||||||
|
|
||||||
|
def_irq_default_handler WWDG_IRQHandler
|
||||||
|
def_irq_default_handler PVD_IRQHandler
|
||||||
|
def_irq_default_handler TAMP_STAMP_IRQHandler
|
||||||
|
def_irq_default_handler RTC_WKUP_IRQHandler
|
||||||
|
def_irq_default_handler FLASH_IRQHandler
|
||||||
|
def_irq_default_handler RCC_IRQHandler
|
||||||
|
def_irq_default_handler EXTI0_IRQHandler
|
||||||
|
def_irq_default_handler EXTI1_IRQHandler
|
||||||
|
def_irq_default_handler EXTI2_IRQHandler
|
||||||
|
def_irq_default_handler EXTI3_IRQHandler
|
||||||
|
def_irq_default_handler EXTI4_IRQHandler
|
||||||
|
def_irq_default_handler DMA1_Stream0_IRQHandler
|
||||||
|
def_irq_default_handler DMA1_Stream1_IRQHandler
|
||||||
|
def_irq_default_handler DMA1_Stream2_IRQHandler
|
||||||
|
def_irq_default_handler DMA1_Stream3_IRQHandler
|
||||||
|
def_irq_default_handler DMA1_Stream4_IRQHandler
|
||||||
|
def_irq_default_handler DMA1_Stream5_IRQHandler
|
||||||
|
def_irq_default_handler DMA1_Stream6_IRQHandler
|
||||||
|
def_irq_default_handler ADC_IRQHandler
|
||||||
|
def_irq_default_handler CAN1_TX_IRQHandler
|
||||||
|
def_irq_default_handler CAN1_RX0_IRQHandler
|
||||||
|
def_irq_default_handler CAN1_RX1_IRQHandler
|
||||||
|
def_irq_default_handler CAN1_SCE_IRQHandler
|
||||||
|
def_irq_default_handler EXTI9_5_IRQHandler
|
||||||
|
def_irq_default_handler TIM1_BRK_TIM9_IRQHandler
|
||||||
|
def_irq_default_handler TIM1_UP_TIM10_IRQHandler
|
||||||
|
def_irq_default_handler TIM1_TRG_COM_TIM11_IRQHandler
|
||||||
|
def_irq_default_handler TIM1_CC_IRQHandler
|
||||||
|
def_irq_default_handler TIM2_IRQHandler
|
||||||
|
def_irq_default_handler TIM3_IRQHandler
|
||||||
|
def_irq_default_handler TIM4_IRQHandler
|
||||||
|
def_irq_default_handler I2C1_EV_IRQHandler
|
||||||
|
def_irq_default_handler I2C1_ER_IRQHandler
|
||||||
|
def_irq_default_handler I2C2_EV_IRQHandler
|
||||||
|
def_irq_default_handler I2C2_ER_IRQHandler
|
||||||
|
def_irq_default_handler SPI1_IRQHandler
|
||||||
|
def_irq_default_handler SPI2_IRQHandler
|
||||||
|
def_irq_default_handler USART1_IRQHandler
|
||||||
|
def_irq_default_handler USART2_IRQHandler
|
||||||
|
def_irq_default_handler USART3_IRQHandler
|
||||||
|
def_irq_default_handler EXTI15_10_IRQHandler
|
||||||
|
def_irq_default_handler RTC_Alarm_IRQHandler
|
||||||
|
def_irq_default_handler OTG_FS_WKUP_IRQHandler
|
||||||
|
def_irq_default_handler TIM8_BRK_TIM12_IRQHandler
|
||||||
|
def_irq_default_handler TIM8_UP_TIM13_IRQHandler
|
||||||
|
def_irq_default_handler TIM8_TRG_COM_TIM14_IRQHandler
|
||||||
|
def_irq_default_handler TIM8_CC_IRQHandler
|
||||||
|
def_irq_default_handler DMA1_Stream7_IRQHandler
|
||||||
|
def_irq_default_handler FSMC_IRQHandler
|
||||||
|
def_irq_default_handler SDIO_IRQHandler
|
||||||
|
def_irq_default_handler TIM5_IRQHandler
|
||||||
|
def_irq_default_handler SPI3_IRQHandler
|
||||||
|
def_irq_default_handler UART4_IRQHandler
|
||||||
|
def_irq_default_handler UART5_IRQHandler
|
||||||
|
def_irq_default_handler TIM6_DAC_IRQHandler
|
||||||
|
def_irq_default_handler TIM7_IRQHandler
|
||||||
|
def_irq_default_handler DMA2_Stream0_IRQHandler
|
||||||
|
def_irq_default_handler DMA2_Stream1_IRQHandler
|
||||||
|
def_irq_default_handler DMA2_Stream2_IRQHandler
|
||||||
|
def_irq_default_handler DMA2_Stream3_IRQHandler
|
||||||
|
def_irq_default_handler DMA2_Stream4_IRQHandler
|
||||||
|
def_irq_default_handler CAN2_TX_IRQHandler
|
||||||
|
def_irq_default_handler CAN2_RX0_IRQHandler
|
||||||
|
def_irq_default_handler CAN2_RX1_IRQHandler
|
||||||
|
def_irq_default_handler CAN2_SCE_IRQHandler
|
||||||
|
def_irq_default_handler OTG_FS_IRQHandler
|
||||||
|
def_irq_default_handler DMA2_Stream5_IRQHandler
|
||||||
|
def_irq_default_handler DMA2_Stream6_IRQHandler
|
||||||
|
def_irq_default_handler DMA2_Stream7_IRQHandler
|
||||||
|
def_irq_default_handler USART6_IRQHandler
|
||||||
|
def_irq_default_handler I2C3_EV_IRQHandler
|
||||||
|
def_irq_default_handler I2C3_ER_IRQHandler
|
||||||
|
def_irq_default_handler OTG_HS_EP1_OUT_IRQHandler
|
||||||
|
def_irq_default_handler OTG_HS_EP1_IN_IRQHandler
|
||||||
|
def_irq_default_handler OTG_HS_WKUP_IRQHandler
|
||||||
|
def_irq_default_handler OTG_HS_IRQHandler
|
||||||
|
def_irq_default_handler HASH_RNG_IRQHandler
|
||||||
|
def_irq_default_handler FPU_IRQHandler
|
||||||
|
def_irq_default_handler DEF_IRQHandler
|
||||||
|
|
||||||
|
.end
|
||||||
|
|
@ -137,7 +137,7 @@
|
||||||
variable is updated automatically.
|
variable is updated automatically.
|
||||||
*/
|
*/
|
||||||
uint32_t SystemCoreClock = 48000000;
|
uint32_t SystemCoreClock = 48000000;
|
||||||
__IO const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
|
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,77 @@
|
||||||
|
# This file was automagically generated by mbed.org. For more information,
|
||||||
|
# see http://mbed.org/handbook/Exporting-to-GCC-ARM-Embedded
|
||||||
|
|
||||||
|
GCC_BIN =
|
||||||
|
PROJECT = {{name}}
|
||||||
|
OBJECTS = {% for f in to_be_compiled %}{{f}} {% endfor %}
|
||||||
|
SYS_OBJECTS = {% for f in object_files %}{{f}} {% endfor %}
|
||||||
|
INCLUDE_PATHS = {% for p in include_paths %}-I{{p}} {% endfor %}
|
||||||
|
LIBRARY_PATHS = {% for p in library_paths %}-L{{p}} {% endfor %}
|
||||||
|
LIBRARIES = {% for lib in libraries %}-l{{lib}} {% endfor %}
|
||||||
|
LINKER_SCRIPT = {{linker_script}}
|
||||||
|
|
||||||
|
###############################################################################
|
||||||
|
AS = $(GCC_BIN)arm-none-eabi-as
|
||||||
|
CC = $(GCC_BIN)arm-none-eabi-gcc
|
||||||
|
CPP = $(GCC_BIN)arm-none-eabi-g++
|
||||||
|
LD = $(GCC_BIN)arm-none-eabi-gcc
|
||||||
|
OBJCOPY = $(GCC_BIN)arm-none-eabi-objcopy
|
||||||
|
OBJDUMP = $(GCC_BIN)arm-none-eabi-objdump
|
||||||
|
SIZE = $(GCC_BIN)arm-none-eabi-size
|
||||||
|
|
||||||
|
CPU = -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=$(FLOAT_ABI)
|
||||||
|
CC_FLAGS = $(CPU) -c -g -fno-common -fmessage-length=0 -Wall -fno-exceptions -ffunction-sections -fdata-sections -fno-rtti
|
||||||
|
CC_FLAGS += -MMD -MP
|
||||||
|
CC_SYMBOLS = {% for s in symbols %}-D{{s}} {% endfor %}
|
||||||
|
|
||||||
|
LD_FLAGS = $(CPU) -Wl,--gc-sections --specs=nano.specs -u _printf_float -u _scanf_float
|
||||||
|
LD_FLAGS += -Wl,-Map=$(PROJECT).map,--cref
|
||||||
|
LD_SYS_LIBS = -lstdc++ -lsupc++ -lm -lc -lgcc -lnosys
|
||||||
|
|
||||||
|
ifeq ($(HARDFP),1)
|
||||||
|
FLOAT_ABI = hard
|
||||||
|
else
|
||||||
|
FLOAT_ABI = softfp
|
||||||
|
endif
|
||||||
|
|
||||||
|
ifeq ($(DEBUG), 1)
|
||||||
|
CC_FLAGS += -DDEBUG -O0
|
||||||
|
else
|
||||||
|
CC_FLAGS += -DNDEBUG -Os
|
||||||
|
endif
|
||||||
|
|
||||||
|
all: $(PROJECT).bin $(PROJECT).hex size
|
||||||
|
|
||||||
|
clean:
|
||||||
|
rm -f $(PROJECT).bin $(PROJECT).elf $(PROJECT).hex $(PROJECT).map $(PROJECT).lst $(OBJECTS) $(DEPS)
|
||||||
|
|
||||||
|
.s.o:
|
||||||
|
$(AS) $(CPU) -o $@ $<
|
||||||
|
|
||||||
|
.c.o:
|
||||||
|
$(CC) $(CC_FLAGS) $(CC_SYMBOLS) -std=gnu99 $(INCLUDE_PATHS) -o $@ $<
|
||||||
|
|
||||||
|
.cpp.o:
|
||||||
|
$(CPP) $(CC_FLAGS) $(CC_SYMBOLS) -std=gnu++98 $(INCLUDE_PATHS) -o $@ $<
|
||||||
|
|
||||||
|
|
||||||
|
$(PROJECT).elf: $(OBJECTS) $(SYS_OBJECTS)
|
||||||
|
$(LD) $(LD_FLAGS) -T$(LINKER_SCRIPT) $(LIBRARY_PATHS) -o $@ $^ $(LIBRARIES) $(LD_SYS_LIBS) $(LIBRARIES) $(LD_SYS_LIBS)
|
||||||
|
|
||||||
|
$(PROJECT).bin: $(PROJECT).elf
|
||||||
|
@$(OBJCOPY) -O binary $< $@
|
||||||
|
|
||||||
|
$(PROJECT).hex: $(PROJECT).elf
|
||||||
|
@$(OBJCOPY) -O ihex $< $@
|
||||||
|
|
||||||
|
$(PROJECT).lst: $(PROJECT).elf
|
||||||
|
@$(OBJDUMP) -Sdh $< > $@
|
||||||
|
|
||||||
|
lst: $(PROJECT).lst
|
||||||
|
|
||||||
|
size:
|
||||||
|
$(SIZE) $(PROJECT).elf
|
||||||
|
|
||||||
|
DEPS = $(OBJECTS:.o=.d) $(SYS_OBJECTS:.o=.d)
|
||||||
|
-include $(DEPS)
|
||||||
|
|
||||||
|
|
@ -60,6 +60,7 @@ class GccArm(Exporter):
|
||||||
'DISCO_L053C8',
|
'DISCO_L053C8',
|
||||||
'NUCLEO_L053R8',
|
'NUCLEO_L053R8',
|
||||||
'DISCO_F334C8',
|
'DISCO_F334C8',
|
||||||
|
'MTS_MDOT',
|
||||||
]
|
]
|
||||||
|
|
||||||
DOT_IN_RELATIVE_PATH = True
|
DOT_IN_RELATIVE_PATH = True
|
||||||
|
|
|
||||||
|
|
@ -594,9 +594,10 @@ class MTS_MDOT(Target):
|
||||||
Target.__init__(self)
|
Target.__init__(self)
|
||||||
self.core = "Cortex-M4F"
|
self.core = "Cortex-M4F"
|
||||||
self.extra_labels = ['STM', 'STM32F4', 'STM32F405RG']
|
self.extra_labels = ['STM', 'STM32F4', 'STM32F405RG']
|
||||||
self.supported_toolchains = ["IAR"]
|
self.macros = ['HSE_VALUE=26000000']
|
||||||
|
self.supported_toolchains = ["GCC_ARM", "IAR"]
|
||||||
self.is_disk_virtual = True
|
self.is_disk_virtual = True
|
||||||
self.default_toolchain = "IAR"
|
self.default_toolchain = "GCC_ARM"
|
||||||
|
|
||||||
|
|
||||||
### Nordic ###
|
### Nordic ###
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue