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STM32F4 bypass PLL configuration when already done by bootloader

pull/12924/head
jeromecoutant 2020-05-05 18:06:10 +02:00
parent 918d679b06
commit ab80e30bfe
2 changed files with 46 additions and 32 deletions
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7
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_NUCLEO_F411RE/system_clock.c
View File

@ -98,6 +98,12 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
__HAL_RCC_PWR_CLK_ENABLE(); __HAL_RCC_PWR_CLK_ENABLE();
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2); __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
/* Get the Clocks configuration according to the internal RCC registers */
HAL_RCC_GetOscConfig(&RCC_OscInitStruct);
/* PLL could be already configured by bootlader */
if (RCC_OscInitStruct.PLL.PLLState != RCC_PLL_ON) {
// Enable HSE oscillator and activate PLL with HSE as source // Enable HSE oscillator and activate PLL with HSE as source
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
if (bypass == 0) { if (bypass == 0) {
@ -119,6 +125,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
return 0; // FAIL return 0; // FAIL
} }
}
// Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;

7
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/system_clock.c
View File

@ -95,6 +95,12 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
__HAL_RCC_PWR_CLK_ENABLE(); __HAL_RCC_PWR_CLK_ENABLE();
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
/* Get the Clocks configuration according to the internal RCC registers */
HAL_RCC_GetOscConfig(&RCC_OscInitStruct);
/* PLL could be already configured by bootlader */
if (RCC_OscInitStruct.PLL.PLLState != RCC_PLL_ON) {
// Enable HSE oscillator and activate PLL with HSE as source // Enable HSE oscillator and activate PLL with HSE as source
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
if (bypass == 0) { if (bypass == 0) {
@ -116,6 +122,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
return 0; // FAIL return 0; // FAIL
} }
}
// Activate the OverDrive to reach the 180 MHz Frequency // Activate the OverDrive to reach the 180 MHz Frequency
if (HAL_PWREx_EnableOverDrive() != HAL_OK) { if (HAL_PWREx_EnableOverDrive() != HAL_OK) {