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reformat coding styles based on coding guidelines

pull/6862/head
Qinghao Shi 2018-05-18 15:52:55 +01:00
parent 953a735129
commit aab82a78b3
48 changed files with 3675 additions and 3440 deletions
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2
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/PeripheralNames.h
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@ -55,7 +55,7 @@ typedef enum {
typedef enum { typedef enum {
SPI_0 = (int)MPS2_SSP1_BASE, SPI_0 = (int)MPS2_SSP1_BASE,
SPI_1 = (int)MPS2_SSP0_BASE, SPI_1 = (int)MPS2_SSP0_BASE,
SPI_2 = (int)MPS2_SSP2_BASE, SPI_2 = (int)MPS2_SSP2_BASE,
SPI_3 = (int)MPS2_SSP3_BASE, SPI_3 = (int)MPS2_SSP3_BASE,
SPI_4 = (int)MPS2_SSP4_BASE SPI_4 = (int)MPS2_SSP4_BASE
} SPIName; } SPIName;

354
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/PinNames.h
View File

@ -23,206 +23,206 @@ extern "C" {
#endif #endif
typedef enum { typedef enum {
PIN_INPUT, PIN_INPUT,
PIN_OUTPUT PIN_OUTPUT
} PinDirection; } PinDirection;
#define PORT_SHIFT 5 #define PORT_SHIFT 5
typedef enum { typedef enum {
// MPS2 EXP Pin Names // MPS2 EXP Pin Names
EXP0 = 0, EXP0 = 0,
EXP1 = 1, EXP1 = 1,
EXP2 = 2, EXP2 = 2,
EXP3 = 3, EXP3 = 3,
EXP4 = 4, EXP4 = 4,
EXP5 = 5, EXP5 = 5,
EXP6 = 6, EXP6 = 6,
EXP7 = 7, EXP7 = 7,
EXP8 = 8, EXP8 = 8,
EXP9 = 9, EXP9 = 9,
EXP10 = 10, EXP10 = 10,
EXP11 = 11, EXP11 = 11,
EXP12 = 12, EXP12 = 12,
EXP13 = 13, EXP13 = 13,
EXP14 = 14, EXP14 = 14,
EXP15 = 15, EXP15 = 15,
EXP16 = 16, EXP16 = 16,
EXP17 = 17, EXP17 = 17,
EXP18 = 18, EXP18 = 18,
EXP19 = 19, EXP19 = 19,
EXP20 = 20, EXP20 = 20,
EXP21 = 21, EXP21 = 21,
EXP22 = 22, EXP22 = 22,
EXP23 = 23, EXP23 = 23,
EXP24 = 24, EXP24 = 24,
EXP25 = 25, EXP25 = 25,
EXP26 = 26, EXP26 = 26,
EXP27 = 27, EXP27 = 27,
EXP28 = 28, EXP28 = 28,
EXP29 = 29, EXP29 = 29,
EXP30 = 30, EXP30 = 30,
EXP31 = 31, EXP31 = 31,
EXP32 = 32, EXP32 = 32,
EXP33 = 33, EXP33 = 33,
EXP34 = 34, EXP34 = 34,
EXP35 = 35, EXP35 = 35,
EXP36 = 36, EXP36 = 36,
EXP37 = 37, EXP37 = 37,
EXP38 = 38, EXP38 = 38,
EXP39 = 39, EXP39 = 39,
EXP40 = 40, EXP40 = 40,
EXP41 = 41, EXP41 = 41,
EXP42 = 42, EXP42 = 42,
EXP43 = 43, EXP43 = 43,
EXP44 = 44, EXP44 = 44,
EXP45 = 45, EXP45 = 45,
EXP46 = 46, EXP46 = 46,
EXP47 = 47, EXP47 = 47,
EXP48 = 48, EXP48 = 48,
EXP49 = 49, EXP49 = 49,
EXP50 = 50, EXP50 = 50,
EXP51 = 51, EXP51 = 51,
// Other mbed Pin Names // Other mbed Pin Names
//LEDs on mps2 //LEDs on mps2
//user leds //user leds
USERLED1 = 100, USERLED1 = 100,
USERLED2 = 101, USERLED2 = 101,
//user switches //user switches
USERSW1 = 110, USERSW1 = 110,
USERSW2 = 111, USERSW2 = 111,
//mcc leds //mcc leds
LED1 = 200, LED1 = 200,
LED2 = 201, LED2 = 201,
LED3 = 202, LED3 = 202,
LED4 = 203, LED4 = 203,
LED5 = 204, LED5 = 204,
LED6 = 205, LED6 = 205,
LED7 = 206, LED7 = 206,
LED8 = 207, LED8 = 207,
//MCC Switches //MCC Switches
SW1 = 210, SW1 = 210,
SW2 = 211, SW2 = 211,
SW3 = 212, SW3 = 212,
SW4 = 213, SW4 = 213,
SW5 = 214, SW5 = 214,
SW6 = 215, SW6 = 215,
SW7 = 216, SW7 = 216,
SW8 = 217, SW8 = 217,
//MPS2 SPI header pins j21 //MPS2 SPI header pins j21
MOSI_SPI = 300, MOSI_SPI = 300,
MISO_SPI = 301, MISO_SPI = 301,
SCLK_SPI = 302, SCLK_SPI = 302,
SSEL_SPI = 303, SSEL_SPI = 303,
//MPS2 CLCD SPI //MPS2 CLCD SPI
CLCD_MOSI = 304, CLCD_MOSI = 304,
CLCD_MISO = 305, CLCD_MISO = 305,
CLCD_SCLK = 306, CLCD_SCLK = 306,
CLCD_SSEL = 307, CLCD_SSEL = 307,
CLCD_RESET = 308, CLCD_RESET = 308,
CLCD_RS = 309, CLCD_RS = 309,
CLCD_RD = 310, CLCD_RD = 310,
CLCD_BL_CTRL = 311, CLCD_BL_CTRL = 311,
//MPS2 shield 0 SPI //MPS2 shield 0 SPI
SHIELD_0_SPI_SCK = 320, SHIELD_0_SPI_SCK = 320,
SHIELD_0_SPI_MOSI = 321, SHIELD_0_SPI_MOSI = 321,
SHIELD_0_SPI_MISO = 322, SHIELD_0_SPI_MISO = 322,
SHIELD_0_SPI_nCS = 323, SHIELD_0_SPI_nCS = 323,
//MPS2 shield 1 SPI //MPS2 shield 1 SPI
SHIELD_1_SPI_SCK = 331, SHIELD_1_SPI_SCK = 331,
SHIELD_1_SPI_MOSI = 332, SHIELD_1_SPI_MOSI = 332,
SHIELD_1_SPI_MISO = 333, SHIELD_1_SPI_MISO = 333,
SHIELD_1_SPI_nCS = 334, SHIELD_1_SPI_nCS = 334,
//MPS2 shield ADC SPI //MPS2 shield ADC SPI
ADC_MOSI = 650, ADC_MOSI = 650,
ADC_MISO = 651, ADC_MISO = 651,
ADC_SCLK = 652, ADC_SCLK = 652,
ADC_SSEL = 653, ADC_SSEL = 653,
//MPS2 Uart //MPS2 Uart
USBTX = 400, USBTX = 400,
USBRX = 401, USBRX = 401,
XB_TX = 402, XB_TX = 402,
XB_RX = 403, XB_RX = 403,
UART_TX2 = 404, UART_TX2 = 404,
UART_RX2 = 405, UART_RX2 = 405,
SH0_TX = 406, SH0_TX = 406,
SH0_RX = 407, SH0_RX = 407,
SH1_TX = 408, SH1_TX = 408,
SH1_RX = 409, SH1_RX = 409,
//MPS2 I2C touchscreen and audio //MPS2 I2C touchscreen and audio
TSC_SDA = 500, TSC_SDA = 500,
TSC_SCL = 501, TSC_SCL = 501,
AUD_SDA = 502, AUD_SDA = 502,
AUD_SCL = 503, AUD_SCL = 503,
//MPS2 I2C for shield //MPS2 I2C for shield
SHIELD_0_SDA = 504, SHIELD_0_SDA = 504,
SHIELD_0_SCL = 505, SHIELD_0_SCL = 505,
SHIELD_1_SDA = 506, SHIELD_1_SDA = 506,
SHIELD_1_SCL = 507, SHIELD_1_SCL = 507,
//MPS2 shield Analog pins //MPS2 shield Analog pins
A0_0 = 600, A0_0 = 600,
A0_1 = 601, A0_1 = 601,
A0_2 = 602, A0_2 = 602,
A0_3 = 603, A0_3 = 603,
A0_4 = 604, A0_4 = 604,
A0_5 = 605, A0_5 = 605,
A1_0 = 606, A1_0 = 606,
A1_1 = 607, A1_1 = 607,
A1_2 = 608, A1_2 = 608,
A1_3 = 609, A1_3 = 609,
A1_4 = 610, A1_4 = 610,
A1_5 = 611, A1_5 = 611,
//MPS2 Shield Digital pins //MPS2 Shield Digital pins
D0_0 = EXP0, D0_0 = EXP0,
D0_1 = EXP4, D0_1 = EXP4,
D0_2 = EXP2, D0_2 = EXP2,
D0_3 = EXP3, D0_3 = EXP3,
D0_4 = EXP1, D0_4 = EXP1,
D0_5 = EXP6, D0_5 = EXP6,
D0_6 = EXP7, D0_6 = EXP7,
D0_7 = EXP8, D0_7 = EXP8,
D0_8 = EXP9, D0_8 = EXP9,
D0_9 = EXP10, D0_9 = EXP10,
D0_10 = EXP12, D0_10 = EXP12,
D0_11 = EXP13, D0_11 = EXP13,
D0_12 = EXP14, D0_12 = EXP14,
D0_13 = EXP11, D0_13 = EXP11,
D0_14 = EXP15, D0_14 = EXP15,
D0_15 = EXP5, D0_15 = EXP5,
D1_0 = EXP26, D1_0 = EXP26,
D1_1 = EXP30, D1_1 = EXP30,
D1_2 = EXP28, D1_2 = EXP28,
D1_3 = EXP29, D1_3 = EXP29,
D1_4 = EXP27, D1_4 = EXP27,
D1_5 = EXP32, D1_5 = EXP32,
D1_6 = EXP33, D1_6 = EXP33,
D1_7 = EXP34, D1_7 = EXP34,
D1_8 = EXP35, D1_8 = EXP35,
D1_9 = EXP36, D1_9 = EXP36,
D1_10 = EXP38, D1_10 = EXP38,
D1_11 = EXP39, D1_11 = EXP39,
D1_12 = EXP40, D1_12 = EXP40,
D1_13 = EXP44, D1_13 = EXP44,
D1_14 = EXP41, D1_14 = EXP41,
D1_15 = EXP31, D1_15 = EXP31,
// Not connected // Not connected
NC = (int)0xFFFFFFFF, NC = (int)0xFFFFFFFF,
} PinName; } PinName;

85
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/ETH_MPS2.c
View File

@ -47,7 +47,7 @@ unsigned int smsc9220_mac_regread(unsigned char regoffset, unsigned int *data)
error = 0; error = 0;
val = SMSC9220->MAC_CSR_CMD; val = SMSC9220->MAC_CSR_CMD;
if(!(val & ((unsigned int)1 << 31))) { // Make sure there's no pending operation if (!(val & ((unsigned int)1 << 31))) { // Make sure there's no pending operation
maccmd = 0; maccmd = 0;
maccmd |= regoffset; maccmd |= regoffset;
maccmd |= ((unsigned int)1 << 30); // Indicates read maccmd |= ((unsigned int)1 << 30); // Indicates read
@ -59,13 +59,13 @@ unsigned int smsc9220_mac_regread(unsigned char regoffset, unsigned int *data)
val = SMSC9220->BYTE_TEST; // A no-op read. val = SMSC9220->BYTE_TEST; // A no-op read.
wait_ms(1); wait_ms(1);
timedout--; timedout--;
} while(timedout && (SMSC9220->MAC_CSR_CMD & ((unsigned int)1 << 31))); } while (timedout && (SMSC9220->MAC_CSR_CMD & ((unsigned int)1 << 31)));
if(!timedout) { if (!timedout) {
error = 1; error = 1;
} } else {
else
*data = SMSC9220->MAC_CSR_DATA; *data = SMSC9220->MAC_CSR_DATA;
}
} else { } else {
*data = 0; *data = 0;
} }
@ -80,7 +80,7 @@ unsigned int smsc9220_mac_regwrite(unsigned char regoffset, unsigned int data)
error = 0; error = 0;
read = SMSC9220->MAC_CSR_CMD; read = SMSC9220->MAC_CSR_CMD;
if(!(read & ((unsigned int)1 << 31))) { // Make sure there's no pending operation if (!(read & ((unsigned int)1 << 31))) { // Make sure there's no pending operation
SMSC9220->MAC_CSR_DATA = data; // Store data. SMSC9220->MAC_CSR_DATA = data; // Store data.
maccmd = 0; maccmd = 0;
maccmd |= regoffset; maccmd |= regoffset;
@ -93,27 +93,28 @@ unsigned int smsc9220_mac_regwrite(unsigned char regoffset, unsigned int data)
read = SMSC9220->BYTE_TEST; // A no-op read. read = SMSC9220->BYTE_TEST; // A no-op read.
wait_ms(1); wait_ms(1);
timedout--; timedout--;
} while(timedout && (SMSC9220->MAC_CSR_CMD & ((unsigned int)1 << 31))); } while (timedout && (SMSC9220->MAC_CSR_CMD & ((unsigned int)1 << 31)));
if(!timedout) { if (!timedout) {
error = 1; error = 1;
} }
} else { } else {
printf("Warning: SMSC9220 MAC CSR is busy. No data written.\n"); printf("Warning: SMSC9220 MAC CSR is busy. No data written.\n");
} }
return error; return error;
} }
unsigned int smsc9220_phy_regread(unsigned char regoffset, unsigned short *data) unsigned int smsc9220_phy_regread(unsigned char regoffset, unsigned short *data)
{ {
unsigned int val, phycmd; int error; unsigned int val, phycmd;
int error;
int timedout; int timedout;
error = 0; error = 0;
smsc9220_mac_regread(SMSC9220_MAC_MII_ACC, &val); smsc9220_mac_regread(SMSC9220_MAC_MII_ACC, &val);
if(!(val & 1)) { // Not busy if (!(val & 1)) { // Not busy
phycmd = 0; phycmd = 0;
phycmd |= (1 << 11); // 1 to [15:11] phycmd |= (1 << 11); // 1 to [15:11]
phycmd |= ((regoffset & 0x1F) << 6); // Put regoffset to [10:6] phycmd |= ((regoffset & 0x1F) << 6); // Put regoffset to [10:6]
@ -127,14 +128,14 @@ unsigned int smsc9220_phy_regread(unsigned char regoffset, unsigned short *data)
do { do {
wait_ms(1); wait_ms(1);
timedout--; timedout--;
smsc9220_mac_regread(SMSC9220_MAC_MII_ACC,&val); smsc9220_mac_regread(SMSC9220_MAC_MII_ACC, &val);
} while(timedout && (val & ((unsigned int)1 << 0))); } while (timedout && (val & ((unsigned int)1 << 0)));
if(!timedout) { if (!timedout) {
error = 1; error = 1;
} } else {
else
smsc9220_mac_regread(SMSC9220_MAC_MII_DATA, (unsigned int *)data); smsc9220_mac_regread(SMSC9220_MAC_MII_DATA, (unsigned int *)data);
}
} else { } else {
*data = 0; *data = 0;
@ -144,14 +145,15 @@ unsigned int smsc9220_phy_regread(unsigned char regoffset, unsigned short *data)
unsigned int smsc9220_phy_regwrite(unsigned char regoffset, unsigned short data) unsigned int smsc9220_phy_regwrite(unsigned char regoffset, unsigned short data)
{ {
unsigned int val, phycmd; int error; unsigned int val, phycmd;
int error;
int timedout; int timedout;
error = 0; error = 0;
smsc9220_mac_regread(SMSC9220_MAC_MII_ACC, &val); smsc9220_mac_regread(SMSC9220_MAC_MII_ACC, &val);
if(!(val & 1)) { // Not busy if (!(val & 1)) { // Not busy
smsc9220_mac_regwrite(SMSC9220_MAC_MII_DATA, (data & 0xFFFF)); // Load the data smsc9220_mac_regwrite(SMSC9220_MAC_MII_DATA, (data & 0xFFFF)); // Load the data
phycmd = 0; phycmd = 0;
phycmd |= (1 << 11); // 1 to [15:11] phycmd |= (1 << 11); // 1 to [15:11]
@ -168,9 +170,9 @@ unsigned int smsc9220_phy_regwrite(unsigned char regoffset, unsigned short data)
wait_ms(1); wait_ms(1);
timedout--; timedout--;
smsc9220_mac_regread(SMSC9220_MAC_MII_ACC, &phycmd); smsc9220_mac_regread(SMSC9220_MAC_MII_ACC, &phycmd);
} while(timedout && (phycmd & (1 << 0))); } while (timedout && (phycmd & (1 << 0)));
if(!timedout) { if (!timedout) {
error = 1; error = 1;
} }
@ -198,10 +200,11 @@ unsigned int smsc9220_soft_reset(void)
do { do {
wait_ms(1); wait_ms(1);
timedout--; timedout--;
} while(timedout && (SMSC9220->HW_CFG & 1)); } while (timedout && (SMSC9220->HW_CFG & 1));
if(!timedout) if (!timedout) {
return 1; return 1;
}
return 0; return 0;
} }
@ -209,8 +212,9 @@ unsigned int smsc9220_soft_reset(void)
void smsc9220_set_txfifo(unsigned int val) void smsc9220_set_txfifo(unsigned int val)
{ {
// 2kb minimum, 14kb maximum // 2kb minimum, 14kb maximum
if(val < 2 || val > 14) if (val < 2 || val > 14) {
return; return;
}
SMSC9220->HW_CFG = val << 16; SMSC9220->HW_CFG = val << 16;
} }
@ -226,10 +230,11 @@ unsigned int smsc9220_wait_eeprom(void)
wait_ms(1); wait_ms(1);
timedout--; timedout--;
} while(timedout && (SMSC9220->E2P_CMD & ((unsigned int) 1 << 31))); } while (timedout && (SMSC9220->E2P_CMD & ((unsigned int) 1 << 31)));
if(!timedout) if (!timedout) {
return 1; return 1;
}
return 0; return 0;
} }
@ -246,8 +251,8 @@ unsigned int smsc9220_check_phy(void)
{ {
unsigned short phyid1, phyid2; unsigned short phyid1, phyid2;
smsc9220_phy_regread(SMSC9220_PHY_ID1,&phyid1); smsc9220_phy_regread(SMSC9220_PHY_ID1, &phyid1);
smsc9220_phy_regread(SMSC9220_PHY_ID2,&phyid2); smsc9220_phy_regread(SMSC9220_PHY_ID2, &phyid2);
return ((phyid1 == 0xFFFF && phyid2 == 0xFFFF) || return ((phyid1 == 0xFFFF && phyid2 == 0xFFFF) ||
(phyid1 == 0x0 && phyid2 == 0x0)); (phyid1 == 0x0 && phyid2 == 0x0));
} }
@ -258,13 +263,13 @@ unsigned int smsc9220_reset_phy(void)
int error; int error;
error = 0; error = 0;
if(smsc9220_phy_regread(SMSC9220_PHY_BCONTROL, &read)) { if (smsc9220_phy_regread(SMSC9220_PHY_BCONTROL, &read)) {
error = 1; error = 1;
return error; return error;
} }
read |= (1 << 15); read |= (1 << 15);
if(smsc9220_phy_regwrite(SMSC9220_PHY_BCONTROL, read)) { if (smsc9220_phy_regwrite(SMSC9220_PHY_BCONTROL, read)) {
error = 1; error = 1;
return error; return error;
} }
@ -370,11 +375,11 @@ unsigned int smsc9220_recv_packet(unsigned int *recvbuf, unsigned int *index)
rxfifo_inf = SMSC9220->RX_FIFO_INF; rxfifo_inf = SMSC9220->RX_FIFO_INF;
if(rxfifo_inf & 0xFFFF) { // If there's data if (rxfifo_inf & 0xFFFF) { // If there's data
rxfifo_stat = SMSC9220->RX_STAT_PORT; rxfifo_stat = SMSC9220->RX_STAT_PORT;
if(rxfifo_stat != 0) { // Fetch status of this packet if (rxfifo_stat != 0) { // Fetch status of this packet
pktsize = ((rxfifo_stat >> 16) & 0x3FFF); pktsize = ((rxfifo_stat >> 16) & 0x3FFF);
if(rxfifo_stat & (1 << 15)) { if (rxfifo_stat & (1 << 15)) {
printf("Error occured during receiving of packets on the bus.\n"); printf("Error occured during receiving of packets on the bus.\n");
return 1; return 1;
} else { } else {
@ -384,7 +389,7 @@ unsigned int smsc9220_recv_packet(unsigned int *recvbuf, unsigned int *index)
*/ */
dwords_to_read = (pktsize + 3) >> 2; dwords_to_read = (pktsize + 3) >> 2;
// PIO copy of data received: // PIO copy of data received:
while(dwords_to_read > 0) { while (dwords_to_read > 0) {
recvbuf[*index] = SMSC9220->RX_DATA_PORT; recvbuf[*index] = SMSC9220->RX_DATA_PORT;
(*index)++; (*index)++;
dwords_to_read--; dwords_to_read--;
@ -407,7 +412,7 @@ unsigned int smsc9220_recv_packet(unsigned int *recvbuf, unsigned int *index)
// Does the actual transfer of data to FIFO, note it does no // Does the actual transfer of data to FIFO, note it does no
// fifo availability checking. This should be done by caller. // fifo availability checking. This should be done by caller.
// Assumes the whole frame is transferred at once as a single segment // Assumes the whole frame is transferred at once as a single segment
void smsc9220_xmit_packet(unsigned char * pkt, unsigned int length) void smsc9220_xmit_packet(unsigned char *pkt, unsigned int length)
{ {
unsigned int txcmd_a, txcmd_b; unsigned int txcmd_a, txcmd_b;
unsigned int dwords_to_write; unsigned int dwords_to_write;
@ -432,18 +437,18 @@ void smsc9220_xmit_packet(unsigned char * pkt, unsigned int length)
dwritten = dwords_to_write = (length + 3) >> 2; dwritten = dwords_to_write = (length + 3) >> 2;
// PIO Copy to FIFO. Could replace this with DMA. // PIO Copy to FIFO. Could replace this with DMA.
while(dwords_to_write > 0) { while (dwords_to_write > 0) {
SMSC9220->TX_DATA_PORT = *pktptr; SMSC9220->TX_DATA_PORT = *pktptr;
pktptr++; pktptr++;
dwords_to_write--; dwords_to_write--;
} }
xmit_stat = SMSC9220->TX_STAT_PORT; xmit_stat = SMSC9220->TX_STAT_PORT;
xmit_stat2 = SMSC9220->TX_STAT_PORT; xmit_stat2 = SMSC9220->TX_STAT_PORT;
xmit_inf = SMSC9220->TX_FIFO_INF; xmit_inf = SMSC9220->TX_FIFO_INF;
if(xmit_stat2 != 0 ) { if (xmit_stat2 != 0) {
for(i = 0; i < 6; i++) { for (i = 0; i < 6; i++) {
xmit_stat2 = SMSC9220->TX_STAT_PORT; xmit_stat2 = SMSC9220->TX_STAT_PORT;
} }
} }

2
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/ETH_MPS2.h
View File

@ -60,6 +60,6 @@ void smsc9220_set_soft_int(void);
void smsc9220_clear_soft_int(void); void smsc9220_clear_soft_int(void);
unsigned int smsc9220_recv_packet(unsigned int *recvbuf, unsigned int *index); unsigned int smsc9220_recv_packet(unsigned int *recvbuf, unsigned int *index);
void smsc9220_xmit_packet(unsigned char * pkt, unsigned int length); void smsc9220_xmit_packet(unsigned char *pkt, unsigned int length);
#endif #endif

21
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/fpga.c
View File

@ -34,12 +34,9 @@ void i2c_delay(unsigned int tick)
start = MPS2_FPGAIO->COUNTER; start = MPS2_FPGAIO->COUNTER;
end = start + (tick); end = start + (tick);
if(end >= start) if (end >= start) {
{
while (MPS2_FPGAIO->COUNTER >= start && MPS2_FPGAIO->COUNTER < end); while (MPS2_FPGAIO->COUNTER >= start && MPS2_FPGAIO->COUNTER < end);
} } else {
else
{
while (MPS2_FPGAIO->COUNTER >= start); while (MPS2_FPGAIO->COUNTER >= start);
while (MPS2_FPGAIO->COUNTER < end); while (MPS2_FPGAIO->COUNTER < end);
} }
@ -56,12 +53,9 @@ void Sleepms(unsigned int msec)
start = MPS2_FPGAIO->COUNTER; start = MPS2_FPGAIO->COUNTER;
end = start + (25 * msec * 1000); end = start + (25 * msec * 1000);
if(end >= start) if (end >= start) {
{
while (MPS2_FPGAIO->COUNTER >= start && MPS2_FPGAIO->COUNTER < end); while (MPS2_FPGAIO->COUNTER >= start && MPS2_FPGAIO->COUNTER < end);
} } else {
else
{
while (MPS2_FPGAIO->COUNTER >= start); while (MPS2_FPGAIO->COUNTER >= start);
while (MPS2_FPGAIO->COUNTER < end); while (MPS2_FPGAIO->COUNTER < end);
} }
@ -77,12 +71,9 @@ void Sleepus(unsigned int usec)
start = MPS2_FPGAIO->COUNTER; start = MPS2_FPGAIO->COUNTER;
end = start + (25 * usec); end = start + (25 * usec);
if(end >= start) if (end >= start) {
{
while (MPS2_FPGAIO->COUNTER >= start && MPS2_FPGAIO->COUNTER < end); while (MPS2_FPGAIO->COUNTER >= start && MPS2_FPGAIO->COUNTER < end);
} } else {
else
{
while (MPS2_FPGAIO->COUNTER >= start); while (MPS2_FPGAIO->COUNTER >= start);
while (MPS2_FPGAIO->COUNTER < end); while (MPS2_FPGAIO->COUNTER < end);
} }

14
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/mps2_ethernet_api.c
View File

@ -42,11 +42,11 @@ int smsc9220_check_id(void)
id = smsc9220_read_id(); id = smsc9220_read_id();
// If bottom and top halves of the word are the same // If bottom and top halves of the word are the same
if(((id >> 16) & 0xFFFF) == (id & 0xFFFF)) { if (((id >> 16) & 0xFFFF) == (id & 0xFFFF)) {
error = 1; error = 1;
return error; return error;
} }
switch(((id >> 16) & 0xFFFF)) { switch (((id >> 16) & 0xFFFF)) {
case 0x9220: case 0x9220:
break; break;
@ -81,7 +81,7 @@ int smsc9220_check_macaddress(void)
smsc9220_mac_regread(SMSC9220_MAC_ADDRL, &mac_low); smsc9220_mac_regread(SMSC9220_MAC_ADDRL, &mac_low);
if(mac_high != mac_valid_high || mac_low != mac_valid_low) { if (mac_high != mac_valid_high || mac_low != mac_valid_low) {
error = TRUE; error = TRUE;
return error; return error;
} }
@ -97,7 +97,7 @@ void smsc9220_print_mac_registers()
i = 0; i = 0;
read = 0; read = 0;
for(i = 1; i <= 0xC; i++) { for (i = 1; i <= 0xC; i++) {
smsc9220_mac_regread(i, &read); smsc9220_mac_regread(i, &read);
} }
return; return;
@ -111,7 +111,7 @@ void smsc9220_print_phy_registers()
i = 0; i = 0;
read = 0; read = 0;
for(i = 0; i <= 6; i++) { for (i = 0; i <= 6; i++) {
smsc9220_phy_regread(i, &read); smsc9220_phy_regread(i, &read);
} }
smsc9220_phy_regread(i = 17, &read); smsc9220_phy_regread(i = 17, &read);
@ -133,7 +133,7 @@ void smsc9220_print_phy_registers()
Ethernet Device initialize Ethernet Device initialize
*----------------------------------------------------------------------------*/ *----------------------------------------------------------------------------*/
int ethernet_transmission(unsigned char * pkt, unsigned int length) int ethernet_transmission(unsigned char *pkt, unsigned int length)
{ {
smsc9220_xmit_packet(pkt, length); smsc9220_xmit_packet(pkt, length);
return 0; return 0;
@ -156,7 +156,7 @@ unsigned int ethernet_check_ready(void)
unsigned int ethernet_intf() unsigned int ethernet_intf()
{ {
unsigned int txfifo_inf; unsigned int txfifo_inf;
txfifo_inf = SMSC9220->TX_FIFO_INF; txfifo_inf = SMSC9220->TX_FIFO_INF;

2
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/mps2_ethernet_api.h
View File

@ -28,7 +28,7 @@ extern "C" {
// Connection constants // Connection constants
// send ethernet write buffer, returning the packet size sent // send ethernet write buffer, returning the packet size sent
int ethernet_transmission(unsigned char * pkt, unsigned int length); int ethernet_transmission(unsigned char *pkt, unsigned int length);
// recieve from ethernet buffer, returning packet size, or 0 if no packet // recieve from ethernet buffer, returning packet size, or 0 if no packet
int ethernet_reception(unsigned int *recvbuf, unsigned int *index); int ethernet_reception(unsigned int *recvbuf, unsigned int *index);

315
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/CMSDK_CM0.h
View File

@ -40,56 +40,55 @@
#define CMSDK_CM0_H #define CMSDK_CM0_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* ------------------------- Interrupt Number Definition ------------------------ */ /* ------------------------- Interrupt Number Definition ------------------------ */
typedef enum IRQn typedef enum IRQn {
{ /****** Cortex-M0 Processor Exceptions Numbers ***************************************************/
/****** Cortex-M0 Processor Exceptions Numbers ***************************************************/
/* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M0 device */ /* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M0 device */
NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M0 Non Maskable Interrupt */ NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M0 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
/* ---------------------- CMSDK_CM0 Specific Interrupt Numbers ------------------ */ /* ---------------------- CMSDK_CM0 Specific Interrupt Numbers ------------------ */
UARTRX0_IRQn = 0, /*!< UART 0 RX Interrupt */ UARTRX0_IRQn = 0, /*!< UART 0 RX Interrupt */
UARTTX0_IRQn = 1, /*!< UART 0 TX Interrupt */ UARTTX0_IRQn = 1, /*!< UART 0 TX Interrupt */
UARTRX1_IRQn = 2, /*!< UART 1 RX Interrupt */ UARTRX1_IRQn = 2, /*!< UART 1 RX Interrupt */
UARTTX1_IRQn = 3, /*!< UART 1 TX Interrupt */ UARTTX1_IRQn = 3, /*!< UART 1 TX Interrupt */
UARTRX2_IRQn = 4, /*!< UART 2 RX Interrupt */ UARTRX2_IRQn = 4, /*!< UART 2 RX Interrupt */
UARTTX2_IRQn = 5, /*!< UART 2 TX Interrupt */ UARTTX2_IRQn = 5, /*!< UART 2 TX Interrupt */
PORT0_ALL_IRQn = 6, /*!< Port 0 combined Interrupt */ PORT0_ALL_IRQn = 6, /*!< Port 0 combined Interrupt */
PORT1_ALL_IRQn = 7, /*!< Port 1 combined Interrupt */ PORT1_ALL_IRQn = 7, /*!< Port 1 combined Interrupt */
TIMER0_IRQn = 8, /*!< TIMER 0 Interrupt */ TIMER0_IRQn = 8, /*!< TIMER 0 Interrupt */
TIMER1_IRQn = 9, /*!< TIMER 1 Interrupt */ TIMER1_IRQn = 9, /*!< TIMER 1 Interrupt */
DUALTIMER_IRQn = 10, /*!< Dual Timer Interrupt */ DUALTIMER_IRQn = 10, /*!< Dual Timer Interrupt */
SPI_IRQn = 11, /*!< SPI Interrupt */ SPI_IRQn = 11, /*!< SPI Interrupt */
UARTOVF_IRQn = 12, /*!< UART 0,1,2 Overflow Interrupt */ UARTOVF_IRQn = 12, /*!< UART 0,1,2 Overflow Interrupt */
ETHERNET_IRQn = 13, /*!< Ethernet Interrupt */ ETHERNET_IRQn = 13, /*!< Ethernet Interrupt */
I2S_IRQn = 14, /*!< I2S Interrupt */ I2S_IRQn = 14, /*!< I2S Interrupt */
TSC_IRQn = 15, /*!< Touch Screen Interrupt */ TSC_IRQn = 15, /*!< Touch Screen Interrupt */
PORT2_ALL_IRQn = 16, /*!< Port 2 combined Interrupt */ PORT2_ALL_IRQn = 16, /*!< Port 2 combined Interrupt */
PORT3_ALL_IRQn = 17, /*!< Port 3 combined Interrupt */ PORT3_ALL_IRQn = 17, /*!< Port 3 combined Interrupt */
UARTRX3_IRQn = 18, /*!< UART 3 RX Interrupt */ UARTRX3_IRQn = 18, /*!< UART 3 RX Interrupt */
UARTTX3_IRQn = 19, /*!< UART 3 TX Interrupt */ UARTTX3_IRQn = 19, /*!< UART 3 TX Interrupt */
UARTRX4_IRQn = 20, /*!< UART 4 RX Interrupt */ UARTRX4_IRQn = 20, /*!< UART 4 RX Interrupt */
UARTTX4_IRQn = 21, /*!< UART 4 TX Interrupt */ UARTTX4_IRQn = 21, /*!< UART 4 TX Interrupt */
ADCSPI_IRQn = 22, /*!< SHIELD ADC SPI Interrupt */ ADCSPI_IRQn = 22, /*!< SHIELD ADC SPI Interrupt */
SHIELDSPI_IRQn = 23, /*!< SHIELD SPI Combined Interrupt */ SHIELDSPI_IRQn = 23, /*!< SHIELD SPI Combined Interrupt */
PORT0_0_IRQn = 24, /*!< GPIO Port 0 pin 0 Interrupt */ PORT0_0_IRQn = 24, /*!< GPIO Port 0 pin 0 Interrupt */
PORT0_1_IRQn = 25, /*!< GPIO Port 0 pin 1 Interrupt */ PORT0_1_IRQn = 25, /*!< GPIO Port 0 pin 1 Interrupt */
PORT0_2_IRQn = 26, /*!< GPIO Port 0 pin 2 Interrupt */ PORT0_2_IRQn = 26, /*!< GPIO Port 0 pin 2 Interrupt */
PORT0_3_IRQn = 27, /*!< GPIO Port 0 pin 3 Interrupt */ PORT0_3_IRQn = 27, /*!< GPIO Port 0 pin 3 Interrupt */
PORT0_4_IRQn = 28, /*!< GPIO Port 0 pin 4 Interrupt */ PORT0_4_IRQn = 28, /*!< GPIO Port 0 pin 4 Interrupt */
PORT0_5_IRQn = 29, /*!< GPIO Port 0 pin 5 Interrupt */ PORT0_5_IRQn = 29, /*!< GPIO Port 0 pin 5 Interrupt */
PORT0_6_IRQn = 30, /*!< GPIO Port 0 pin 6 Interrupt */ PORT0_6_IRQn = 30, /*!< GPIO Port 0 pin 6 Interrupt */
PORT0_7_IRQn = 31, /*!< GPIO Port 0 pin 7 Interrupt */ PORT0_7_IRQn = 31, /*!< GPIO Port 0 pin 7 Interrupt */
} IRQn_Type; } IRQn_Type;
@ -113,31 +112,30 @@ typedef enum IRQn
/* ------------------- Start of section using anonymous unions ------------------ */ /* ------------------- Start of section using anonymous unions ------------------ */
#if defined ( __CC_ARM ) #if defined ( __CC_ARM )
#pragma push #pragma push
#pragma anon_unions #pragma anon_unions
#elif defined(__ICCARM__) #elif defined(__ICCARM__)
#pragma language=extended #pragma language=extended
#elif defined(__GNUC__) #elif defined(__GNUC__)
/* anonymous unions are enabled by default */ /* anonymous unions are enabled by default */
#elif defined(__TMS470__) #elif defined(__TMS470__)
/* anonymous unions are enabled by default */ /* anonymous unions are enabled by default */
#elif defined(__TASKING__) #elif defined(__TASKING__)
#pragma warning 586 #pragma warning 586
#else #else
#warning Not supported compiler type #warning Not supported compiler type
#endif #endif
/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
typedef struct typedef struct {
{ __IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */
__IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */ __IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */
__IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */ __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */
__IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */ union {
union { __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */
__I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */ __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */
__O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */
}; };
__IO uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register */ __IO uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register */
} CMSDK_UART_TypeDef; } CMSDK_UART_TypeDef;
@ -196,14 +194,13 @@ typedef struct
/*----------------------------- Timer (TIMER) -------------------------------*/ /*----------------------------- Timer (TIMER) -------------------------------*/
typedef struct typedef struct {
{ __IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */
__IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */ __IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */
__IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */ __IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */
__IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */ union {
union { __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */
__I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */ __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */
__O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */
}; };
} CMSDK_TIMER_TypeDef; } CMSDK_TIMER_TypeDef;
@ -236,26 +233,25 @@ typedef struct
/*------------- Timer (TIM) --------------------------------------------------*/ /*------------- Timer (TIM) --------------------------------------------------*/
typedef struct typedef struct {
{ __IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
__IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */ __I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
__I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */ __IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
__IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */ __O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
__O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */ __I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
__I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */ __I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
__I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */ __IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */
__IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */ uint32_t RESERVED0;
uint32_t RESERVED0; __IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */
__IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */ __I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
__I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */ __IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */
__IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */ __O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
__O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */ __I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
__I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */ __I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
__I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */ __IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */
__IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */ uint32_t RESERVED1[945];
uint32_t RESERVED1[945]; __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Integration Test Control Register */
__IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Integration Test Control Register */ __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Integration Test Output Set Register */
__O uint32_t ITOP; /* Offset: 0xF04 ( /W) Integration Test Output Set Register */
} CMSDK_DUALTIMER_BOTH_TypeDef; } CMSDK_DUALTIMER_BOTH_TypeDef;
#define CMSDK_DUALTIMER1_LOAD_Pos 0 /* CMSDK_DUALTIMER1 LOAD: LOAD Position */ #define CMSDK_DUALTIMER1_LOAD_Pos 0 /* CMSDK_DUALTIMER1 LOAD: LOAD Position */
@ -331,15 +327,14 @@ typedef struct
#define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /* CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */ #define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /* CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */
typedef struct typedef struct {
{ __IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */
__IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */ __I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */
__I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */ __IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */
__IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */ __O uint32_t TimerIntClr; /* Offset: 0x000 (R/W) Timer Interrupt Clear */
__O uint32_t TimerIntClr; /* Offset: 0x000 (R/W) Timer Interrupt Clear */ __I uint32_t TimerRIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */
__I uint32_t TimerRIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */ __I uint32_t TimerMIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */
__I uint32_t TimerMIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */ __IO uint32_t TimerBGLoad; /* Offset: 0x000 (R/W) Background Load Register */
__IO uint32_t TimerBGLoad; /* Offset: 0x000 (R/W) Background Load Register */
} CMSDK_DUALTIMER_SINGLE_TypeDef; } CMSDK_DUALTIMER_SINGLE_TypeDef;
#define CMSDK_DUALTIMER_LOAD_Pos 0 /* CMSDK_DUALTIMER LOAD: LOAD Position */ #define CMSDK_DUALTIMER_LOAD_Pos 0 /* CMSDK_DUALTIMER LOAD: LOAD Position */
@ -380,28 +375,27 @@ typedef struct
/*-------------------- General Purpose Input Output (GPIO) -------------------*/ /*-------------------- General Purpose Input Output (GPIO) -------------------*/
typedef struct typedef struct {
{ __IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */
__IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */ __IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */
__IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */ uint32_t RESERVED0[2];
uint32_t RESERVED0[2]; __IO uint32_t OUTENABLESET; /* Offset: 0x010 (R/W) Output Enable Set Register */
__IO uint32_t OUTENABLESET; /* Offset: 0x010 (R/W) Output Enable Set Register */ __IO uint32_t OUTENABLECLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */
__IO uint32_t OUTENABLECLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */ __IO uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */
__IO uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */ __IO uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */
__IO uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */ __IO uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */
__IO uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */ __IO uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */
__IO uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */ __IO uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */
__IO uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */ __IO uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */
__IO uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */ __IO uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */
__IO uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */ __IO uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */
__IO uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */ union {
union { __I uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */
__I uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */ __O uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */
__O uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */
}; };
uint32_t RESERVED1[241]; uint32_t RESERVED1[241];
__IO uint32_t LB_MASKED[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */ __IO uint32_t LB_MASKED[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */
__IO uint32_t UB_MASKED[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */ __IO uint32_t UB_MASKED[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */
} CMSDK_GPIO_TypeDef; } CMSDK_GPIO_TypeDef;
#define CMSDK_GPIO_DATA_Pos 0 /* CMSDK_GPIO DATA: DATA Position */ #define CMSDK_GPIO_DATA_Pos 0 /* CMSDK_GPIO DATA: DATA Position */
@ -454,13 +448,12 @@ typedef struct
/*------------- System Control (SYSCON) --------------------------------------*/ /*------------- System Control (SYSCON) --------------------------------------*/
typedef struct typedef struct {
{ __IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */
__IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */ __IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */
__IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */ __IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */
__IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */ __IO uint32_t EMICTRL; /* Offset: 0x00C (R/W) EMI Control Register */
__IO uint32_t EMICTRL; /* Offset: 0x00C (R/W) EMI Control Register */ __IO uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */
__IO uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */
} CMSDK_SYSCON_TypeDef; } CMSDK_SYSCON_TypeDef;
#define CMSDK_SYSCON_REMAP_Pos 0 #define CMSDK_SYSCON_REMAP_Pos 0
@ -495,26 +488,25 @@ typedef struct
/*------------- PL230 uDMA (PL230) --------------------------------------*/ /*------------- PL230 uDMA (PL230) --------------------------------------*/
typedef struct typedef struct {
{ __I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */
__I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */ __O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */
__O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */ __IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */
__IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */ __I uint32_t ALT_CTRL_BASE_PTR; /* Offset: 0x00C (R/ ) Channel Alternate Control Data Base Pointer Register */
__I uint32_t ALT_CTRL_BASE_PTR; /* Offset: 0x00C (R/ ) Channel Alternate Control Data Base Pointer Register */ __I uint32_t DMA_WAITONREQ_STATUS; /* Offset: 0x010 (R/ ) Channel Wait On Request Status Register */
__I uint32_t DMA_WAITONREQ_STATUS; /* Offset: 0x010 (R/ ) Channel Wait On Request Status Register */ __O uint32_t CHNL_SW_REQUEST; /* Offset: 0x014 ( /W) Channel Software Request Register */
__O uint32_t CHNL_SW_REQUEST; /* Offset: 0x014 ( /W) Channel Software Request Register */ __IO uint32_t CHNL_USEBURST_SET; /* Offset: 0x018 (R/W) Channel UseBurst Set Register */
__IO uint32_t CHNL_USEBURST_SET; /* Offset: 0x018 (R/W) Channel UseBurst Set Register */ __O uint32_t CHNL_USEBURST_CLR; /* Offset: 0x01C ( /W) Channel UseBurst Clear Register */
__O uint32_t CHNL_USEBURST_CLR; /* Offset: 0x01C ( /W) Channel UseBurst Clear Register */ __IO uint32_t CHNL_REQ_MASK_SET; /* Offset: 0x020 (R/W) Channel Request Mask Set Register */
__IO uint32_t CHNL_REQ_MASK_SET; /* Offset: 0x020 (R/W) Channel Request Mask Set Register */ __O uint32_t CHNL_REQ_MASK_CLR; /* Offset: 0x024 ( /W) Channel Request Mask Clear Register */
__O uint32_t CHNL_REQ_MASK_CLR; /* Offset: 0x024 ( /W) Channel Request Mask Clear Register */ __IO uint32_t CHNL_ENABLE_SET; /* Offset: 0x028 (R/W) Channel Enable Set Register */
__IO uint32_t CHNL_ENABLE_SET; /* Offset: 0x028 (R/W) Channel Enable Set Register */ __O uint32_t CHNL_ENABLE_CLR; /* Offset: 0x02C ( /W) Channel Enable Clear Register */
__O uint32_t CHNL_ENABLE_CLR; /* Offset: 0x02C ( /W) Channel Enable Clear Register */ __IO uint32_t CHNL_PRI_ALT_SET; /* Offset: 0x030 (R/W) Channel Primary-Alterante Set Register */
__IO uint32_t CHNL_PRI_ALT_SET; /* Offset: 0x030 (R/W) Channel Primary-Alterante Set Register */ __O uint32_t CHNL_PRI_ALT_CLR; /* Offset: 0x034 ( /W) Channel Primary-Alterante Clear Register */
__O uint32_t CHNL_PRI_ALT_CLR; /* Offset: 0x034 ( /W) Channel Primary-Alterante Clear Register */ __IO uint32_t CHNL_PRIORITY_SET; /* Offset: 0x038 (R/W) Channel Priority Set Register */
__IO uint32_t CHNL_PRIORITY_SET; /* Offset: 0x038 (R/W) Channel Priority Set Register */ __O uint32_t CHNL_PRIORITY_CLR; /* Offset: 0x03C ( /W) Channel Priority Clear Register */
__O uint32_t CHNL_PRIORITY_CLR; /* Offset: 0x03C ( /W) Channel Priority Clear Register */ uint32_t RESERVED0[3];
uint32_t RESERVED0[3]; __IO uint32_t ERR_CLR; /* Offset: 0x04C Bus Error Clear Register (R/W) */
__IO uint32_t ERR_CLR; /* Offset: 0x04C Bus Error Clear Register (R/W) */
} CMSDK_PL230_TypeDef; } CMSDK_PL230_TypeDef;
@ -591,21 +583,20 @@ typedef struct
/*------------------- Watchdog ----------------------------------------------*/ /*------------------- Watchdog ----------------------------------------------*/
typedef struct typedef struct {
{
__IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */ __IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */
__I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */ __I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */
__IO uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */ __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */
__O uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */ __O uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */
__I uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */ __I uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */
__I uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */ __I uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */
uint32_t RESERVED0[762]; uint32_t RESERVED0[762];
__IO uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */ __IO uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */
uint32_t RESERVED1[191]; uint32_t RESERVED1[191];
__IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */ __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */
__O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */ __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */
}CMSDK_WATCHDOG_TypeDef; } CMSDK_WATCHDOG_TypeDef;
#define CMSDK_Watchdog_LOAD_Pos 0 /* CMSDK_Watchdog LOAD: LOAD Position */ #define CMSDK_Watchdog_LOAD_Pos 0 /* CMSDK_Watchdog LOAD: LOAD Position */
#define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /* CMSDK_Watchdog LOAD: LOAD Mask */ #define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /* CMSDK_Watchdog LOAD: LOAD Mask */
@ -641,17 +632,17 @@ typedef struct
/* -------------------- End of section using anonymous unions ------------------- */ /* -------------------- End of section using anonymous unions ------------------- */
#if defined ( __CC_ARM ) #if defined ( __CC_ARM )
#pragma pop #pragma pop
#elif defined(__ICCARM__) #elif defined(__ICCARM__)
/* leave anonymous unions enabled */ /* leave anonymous unions enabled */
#elif defined(__GNUC__) #elif defined(__GNUC__)
/* anonymous unions are enabled by default */ /* anonymous unions are enabled by default */
#elif defined(__TMS470__) #elif defined(__TMS470__)
/* anonymous unions are enabled by default */ /* anonymous unions are enabled by default */
#elif defined(__TASKING__) #elif defined(__TASKING__)
#pragma warning restore #pragma warning restore
#else #else
#warning Not supported compiler type #warning Not supported compiler type
#endif #endif

12
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/cmsis_nvic.c
View File

@ -36,18 +36,20 @@
#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Location of vectors in RAM #define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Location of vectors in RAM
#define NVIC_FLASH_VECTOR_ADDRESS (0x00000000) // Initial vector position in flash #define NVIC_FLASH_VECTOR_ADDRESS (0x00000000) // Initial vector position in flash
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
// int i; {
// int i;
// Space for dynamic vectors, initialised to allocate in R/W // Space for dynamic vectors, initialised to allocate in R/W
static volatile uint32_t* vectors = (uint32_t*)NVIC_FLASH_VECTOR_ADDRESS; static volatile uint32_t *vectors = (uint32_t *)NVIC_FLASH_VECTOR_ADDRESS;
// Set the vector // Set the vector
vectors[IRQn + 16] = vector; vectors[IRQn + 16] = vector;
} }
uint32_t NVIC_GetVector(IRQn_Type IRQn) { uint32_t NVIC_GetVector(IRQn_Type IRQn)
{
// We can always read vectors at 0x0, as the addresses are remapped // We can always read vectors at 0x0, as the addresses are remapped
uint32_t *vectors = (uint32_t*)NVIC_FLASH_VECTOR_ADDRESS; uint32_t *vectors = (uint32_t *)NVIC_FLASH_VECTOR_ADDRESS;
// Return the vector // Return the vector
return vectors[IRQn + 16]; return vectors[IRQn + 16];

12
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/peripherallink.h
View File

@ -37,17 +37,17 @@
#define __DEVICE_H #define __DEVICE_H
#if defined CMSDK_CM0 #if defined CMSDK_CM0
#include "CMSDK_CM0.h" /* device specific header file */ #include "CMSDK_CM0.h" /* device specific header file */
#elif defined CMSDK_CM0plus #elif defined CMSDK_CM0plus
#include "CMSDK_CM0plus.h" /* device specific header file */ #include "CMSDK_CM0plus.h" /* device specific header file */
#elif defined CMSDK_CM3 #elif defined CMSDK_CM3
#include "CMSDK_CM3.h" /* device specific header file */ #include "CMSDK_CM3.h" /* device specific header file */
#elif defined CMSDK_CM4 #elif defined CMSDK_CM4
#include "CMSDK_CM4.h" /* device specific header file */ #include "CMSDK_CM4.h" /* device specific header file */
#elif defined CMSDK_CM7 #elif defined CMSDK_CM7
#include "CMSDK_CM7.h" /* device specific header file */ #include "CMSDK_CM7.h" /* device specific header file */
#else #else
#warning "no appropriate header file found!" #warning "no appropriate header file found!"
#endif #endif
#endif /* __DEVICE_H */ #endif /* __DEVICE_H */

8
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/system_CMSDK_CM0.c
View File

@ -64,10 +64,10 @@ uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Cloc
* @brief Updates the SystemCoreClock with current core Clock * @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers. * retrieved from cpu registers.
*/ */
void SystemCoreClockUpdate (void) void SystemCoreClockUpdate(void)
{ {
SystemCoreClock = __SYSTEM_CLOCK; SystemCoreClock = __SYSTEM_CLOCK;
} }
@ -80,9 +80,9 @@ void SystemCoreClockUpdate (void)
* @brief Setup the microcontroller system. * @brief Setup the microcontroller system.
* Initialize the System. * Initialize the System.
*/ */
void SystemInit (void) void SystemInit(void)
{ {
SystemCoreClock = __SYSTEM_CLOCK; SystemCoreClock = __SYSTEM_CLOCK;
} }

4
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/system_CMSDK_CM0.h
View File

@ -56,7 +56,7 @@ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) *
* @brief Setup the microcontroller system. * @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable. * Initialize the System and update the SystemCoreClock variable.
*/ */
extern void SystemInit (void); extern void SystemInit(void);
/** /**
* Update SystemCoreClock variable * Update SystemCoreClock variable
@ -67,7 +67,7 @@ extern void SystemInit (void);
* @brief Updates the SystemCoreClock with current core Clock * @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers. * retrieved from cpu registers.
*/ */
extern void SystemCoreClockUpdate (void); extern void SystemCoreClockUpdate(void);
#ifdef __cplusplus #ifdef __cplusplus
} }

315
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/CMSDK_CM0plus.h
View File

@ -40,56 +40,55 @@
#define CMSDK_CM0plus_H #define CMSDK_CM0plus_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* ------------------------- Interrupt Number Definition ------------------------ */ /* ------------------------- Interrupt Number Definition ------------------------ */
typedef enum IRQn typedef enum IRQn {
{ /****** Cortex-M0 Processor Exceptions Numbers ***************************************************/
/****** Cortex-M0 Processor Exceptions Numbers ***************************************************/
/* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M0 device */ /* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M0 device */
NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M0 Non Maskable Interrupt */ NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M0 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
/* ---------------------- CMSDK_CM0 Specific Interrupt Numbers ------------------ */ /* ---------------------- CMSDK_CM0 Specific Interrupt Numbers ------------------ */
UARTRX0_IRQn = 0, /*!< UART 0 RX Interrupt */ UARTRX0_IRQn = 0, /*!< UART 0 RX Interrupt */
UARTTX0_IRQn = 1, /*!< UART 0 TX Interrupt */ UARTTX0_IRQn = 1, /*!< UART 0 TX Interrupt */
UARTRX1_IRQn = 2, /*!< UART 1 RX Interrupt */ UARTRX1_IRQn = 2, /*!< UART 1 RX Interrupt */
UARTTX1_IRQn = 3, /*!< UART 1 TX Interrupt */ UARTTX1_IRQn = 3, /*!< UART 1 TX Interrupt */
UARTRX2_IRQn = 4, /*!< UART 2 RX Interrupt */ UARTRX2_IRQn = 4, /*!< UART 2 RX Interrupt */
UARTTX2_IRQn = 5, /*!< UART 2 TX Interrupt */ UARTTX2_IRQn = 5, /*!< UART 2 TX Interrupt */
PORT0_ALL_IRQn = 6, /*!< Port 0 combined Interrupt */ PORT0_ALL_IRQn = 6, /*!< Port 0 combined Interrupt */
PORT1_ALL_IRQn = 7, /*!< Port 1 combined Interrupt */ PORT1_ALL_IRQn = 7, /*!< Port 1 combined Interrupt */
TIMER0_IRQn = 8, /*!< TIMER 0 Interrupt */ TIMER0_IRQn = 8, /*!< TIMER 0 Interrupt */
TIMER1_IRQn = 9, /*!< TIMER 1 Interrupt */ TIMER1_IRQn = 9, /*!< TIMER 1 Interrupt */
DUALTIMER_IRQn = 10, /*!< Dual Timer Interrupt */ DUALTIMER_IRQn = 10, /*!< Dual Timer Interrupt */
SPI_IRQn = 11, /*!< SPI Interrupt */ SPI_IRQn = 11, /*!< SPI Interrupt */
UARTOVF_IRQn = 12, /*!< UART 0,1,2 Overflow Interrupt */ UARTOVF_IRQn = 12, /*!< UART 0,1,2 Overflow Interrupt */
ETHERNET_IRQn = 13, /*!< Ethernet Interrupt */ ETHERNET_IRQn = 13, /*!< Ethernet Interrupt */
I2S_IRQn = 14, /*!< I2S Interrupt */ I2S_IRQn = 14, /*!< I2S Interrupt */
TSC_IRQn = 15, /*!< Touch Screen Interrupt */ TSC_IRQn = 15, /*!< Touch Screen Interrupt */
PORT2_ALL_IRQn = 16, /*!< Port 2 combined Interrupt */ PORT2_ALL_IRQn = 16, /*!< Port 2 combined Interrupt */
PORT3_ALL_IRQn = 17, /*!< Port 3 combined Interrupt */ PORT3_ALL_IRQn = 17, /*!< Port 3 combined Interrupt */
UARTRX3_IRQn = 18, /*!< UART 3 RX Interrupt */ UARTRX3_IRQn = 18, /*!< UART 3 RX Interrupt */
UARTTX3_IRQn = 19, /*!< UART 3 TX Interrupt */ UARTTX3_IRQn = 19, /*!< UART 3 TX Interrupt */
UARTRX4_IRQn = 20, /*!< UART 4 RX Interrupt */ UARTRX4_IRQn = 20, /*!< UART 4 RX Interrupt */
UARTTX4_IRQn = 21, /*!< UART 4 TX Interrupt */ UARTTX4_IRQn = 21, /*!< UART 4 TX Interrupt */
ADCSPI_IRQn = 22, /*!< SHIELD ADC SPI Interrupt */ ADCSPI_IRQn = 22, /*!< SHIELD ADC SPI Interrupt */
SHIELDSPI_IRQn = 23, /*!< SHIELD SPI Combined Interrupt */ SHIELDSPI_IRQn = 23, /*!< SHIELD SPI Combined Interrupt */
PORT0_0_IRQn = 24, /*!< GPIO Port 0 pin 0 Interrupt */ PORT0_0_IRQn = 24, /*!< GPIO Port 0 pin 0 Interrupt */
PORT0_1_IRQn = 25, /*!< GPIO Port 0 pin 1 Interrupt */ PORT0_1_IRQn = 25, /*!< GPIO Port 0 pin 1 Interrupt */
PORT0_2_IRQn = 26, /*!< GPIO Port 0 pin 2 Interrupt */ PORT0_2_IRQn = 26, /*!< GPIO Port 0 pin 2 Interrupt */
PORT0_3_IRQn = 27, /*!< GPIO Port 0 pin 3 Interrupt */ PORT0_3_IRQn = 27, /*!< GPIO Port 0 pin 3 Interrupt */
PORT0_4_IRQn = 28, /*!< GPIO Port 0 pin 4 Interrupt */ PORT0_4_IRQn = 28, /*!< GPIO Port 0 pin 4 Interrupt */
PORT0_5_IRQn = 29, /*!< GPIO Port 0 pin 5 Interrupt */ PORT0_5_IRQn = 29, /*!< GPIO Port 0 pin 5 Interrupt */
PORT0_6_IRQn = 30, /*!< GPIO Port 0 pin 6 Interrupt */ PORT0_6_IRQn = 30, /*!< GPIO Port 0 pin 6 Interrupt */
PORT0_7_IRQn = 31, /*!< GPIO Port 0 pin 7 Interrupt */ PORT0_7_IRQn = 31, /*!< GPIO Port 0 pin 7 Interrupt */
} IRQn_Type; } IRQn_Type;
@ -114,31 +113,30 @@ typedef enum IRQn
/* ------------------- Start of section using anonymous unions ------------------ */ /* ------------------- Start of section using anonymous unions ------------------ */
#if defined ( __CC_ARM ) #if defined ( __CC_ARM )
#pragma push #pragma push
#pragma anon_unions #pragma anon_unions
#elif defined(__ICCARM__) #elif defined(__ICCARM__)
#pragma language=extended #pragma language=extended
#elif defined(__GNUC__) #elif defined(__GNUC__)
/* anonymous unions are enabled by default */ /* anonymous unions are enabled by default */
#elif defined(__TMS470__) #elif defined(__TMS470__)
/* anonymous unions are enabled by default */ /* anonymous unions are enabled by default */
#elif defined(__TASKING__) #elif defined(__TASKING__)
#pragma warning 586 #pragma warning 586
#else #else
#warning Not supported compiler type #warning Not supported compiler type
#endif #endif
/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
typedef struct typedef struct {
{ __IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */
__IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */ __IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */
__IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */ __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */
__IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */ union {
union { __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */
__I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */ __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */
__O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */
}; };
__IO uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register */ __IO uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register */
} CMSDK_UART_TypeDef; } CMSDK_UART_TypeDef;
@ -197,14 +195,13 @@ typedef struct
/*----------------------------- Timer (TIMER) -------------------------------*/ /*----------------------------- Timer (TIMER) -------------------------------*/
typedef struct typedef struct {
{ __IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */
__IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */ __IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */
__IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */ __IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */
__IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */ union {
union { __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */
__I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */ __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */
__O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */
}; };
} CMSDK_TIMER_TypeDef; } CMSDK_TIMER_TypeDef;
@ -237,26 +234,25 @@ typedef struct
/*------------- Timer (TIM) --------------------------------------------------*/ /*------------- Timer (TIM) --------------------------------------------------*/
typedef struct typedef struct {
{ __IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
__IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */ __I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
__I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */ __IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
__IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */ __O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
__O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */ __I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
__I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */ __I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
__I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */ __IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */
__IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */ uint32_t RESERVED0;
uint32_t RESERVED0; __IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */
__IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */ __I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
__I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */ __IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */
__IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */ __O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
__O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */ __I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
__I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */ __I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
__I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */ __IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */
__IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */ uint32_t RESERVED1[945];
uint32_t RESERVED1[945]; __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Integration Test Control Register */
__IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Integration Test Control Register */ __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Integration Test Output Set Register */
__O uint32_t ITOP; /* Offset: 0xF04 ( /W) Integration Test Output Set Register */
} CMSDK_DUALTIMER_BOTH_TypeDef; } CMSDK_DUALTIMER_BOTH_TypeDef;
#define CMSDK_DUALTIMER1_LOAD_Pos 0 /* CMSDK_DUALTIMER1 LOAD: LOAD Position */ #define CMSDK_DUALTIMER1_LOAD_Pos 0 /* CMSDK_DUALTIMER1 LOAD: LOAD Position */
@ -332,15 +328,14 @@ typedef struct
#define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /* CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */ #define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /* CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */
typedef struct typedef struct {
{ __IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */
__IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */ __I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */
__I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */ __IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */
__IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */ __O uint32_t TimerIntClr; /* Offset: 0x000 (R/W) Timer Interrupt Clear */
__O uint32_t TimerIntClr; /* Offset: 0x000 (R/W) Timer Interrupt Clear */ __I uint32_t TimerRIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */
__I uint32_t TimerRIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */ __I uint32_t TimerMIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */
__I uint32_t TimerMIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */ __IO uint32_t TimerBGLoad; /* Offset: 0x000 (R/W) Background Load Register */
__IO uint32_t TimerBGLoad; /* Offset: 0x000 (R/W) Background Load Register */
} CMSDK_DUALTIMER_SINGLE_TypeDef; } CMSDK_DUALTIMER_SINGLE_TypeDef;
#define CMSDK_DUALTIMER_LOAD_Pos 0 /* CMSDK_DUALTIMER LOAD: LOAD Position */ #define CMSDK_DUALTIMER_LOAD_Pos 0 /* CMSDK_DUALTIMER LOAD: LOAD Position */
@ -381,28 +376,27 @@ typedef struct
/*-------------------- General Purpose Input Output (GPIO) -------------------*/ /*-------------------- General Purpose Input Output (GPIO) -------------------*/
typedef struct typedef struct {
{ __IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */
__IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */ __IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */
__IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */ uint32_t RESERVED0[2];
uint32_t RESERVED0[2]; __IO uint32_t OUTENABLESET; /* Offset: 0x010 (R/W) Output Enable Set Register */
__IO uint32_t OUTENABLESET; /* Offset: 0x010 (R/W) Output Enable Set Register */ __IO uint32_t OUTENABLECLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */
__IO uint32_t OUTENABLECLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */ __IO uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */
__IO uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */ __IO uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */
__IO uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */ __IO uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */
__IO uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */ __IO uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */
__IO uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */ __IO uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */
__IO uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */ __IO uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */
__IO uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */ __IO uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */
__IO uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */ __IO uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */
__IO uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */ union {
union { __I uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */
__I uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */ __O uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */
__O uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */
}; };
uint32_t RESERVED1[241]; uint32_t RESERVED1[241];
__IO uint32_t LB_MASKED[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */ __IO uint32_t LB_MASKED[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */
__IO uint32_t UB_MASKED[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */ __IO uint32_t UB_MASKED[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */
} CMSDK_GPIO_TypeDef; } CMSDK_GPIO_TypeDef;
#define CMSDK_GPIO_DATA_Pos 0 /* CMSDK_GPIO DATA: DATA Position */ #define CMSDK_GPIO_DATA_Pos 0 /* CMSDK_GPIO DATA: DATA Position */
@ -455,13 +449,12 @@ typedef struct
/*------------- System Control (SYSCON) --------------------------------------*/ /*------------- System Control (SYSCON) --------------------------------------*/
typedef struct typedef struct {
{ __IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */
__IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */ __IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */
__IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */ __IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */
__IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */ __IO uint32_t EMICTRL; /* Offset: 0x00C (R/W) EMI Control Register */
__IO uint32_t EMICTRL; /* Offset: 0x00C (R/W) EMI Control Register */ __IO uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */
__IO uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */
} CMSDK_SYSCON_TypeDef; } CMSDK_SYSCON_TypeDef;
#define CMSDK_SYSCON_REMAP_Pos 0 #define CMSDK_SYSCON_REMAP_Pos 0
@ -496,26 +489,25 @@ typedef struct
/*------------- PL230 uDMA (PL230) --------------------------------------*/ /*------------- PL230 uDMA (PL230) --------------------------------------*/
typedef struct typedef struct {
{ __I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */
__I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */ __O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */
__O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */ __IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */
__IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */ __I uint32_t ALT_CTRL_BASE_PTR; /* Offset: 0x00C (R/ ) Channel Alternate Control Data Base Pointer Register */
__I uint32_t ALT_CTRL_BASE_PTR; /* Offset: 0x00C (R/ ) Channel Alternate Control Data Base Pointer Register */ __I uint32_t DMA_WAITONREQ_STATUS; /* Offset: 0x010 (R/ ) Channel Wait On Request Status Register */
__I uint32_t DMA_WAITONREQ_STATUS; /* Offset: 0x010 (R/ ) Channel Wait On Request Status Register */ __O uint32_t CHNL_SW_REQUEST; /* Offset: 0x014 ( /W) Channel Software Request Register */
__O uint32_t CHNL_SW_REQUEST; /* Offset: 0x014 ( /W) Channel Software Request Register */ __IO uint32_t CHNL_USEBURST_SET; /* Offset: 0x018 (R/W) Channel UseBurst Set Register */
__IO uint32_t CHNL_USEBURST_SET; /* Offset: 0x018 (R/W) Channel UseBurst Set Register */ __O uint32_t CHNL_USEBURST_CLR; /* Offset: 0x01C ( /W) Channel UseBurst Clear Register */
__O uint32_t CHNL_USEBURST_CLR; /* Offset: 0x01C ( /W) Channel UseBurst Clear Register */ __IO uint32_t CHNL_REQ_MASK_SET; /* Offset: 0x020 (R/W) Channel Request Mask Set Register */
__IO uint32_t CHNL_REQ_MASK_SET; /* Offset: 0x020 (R/W) Channel Request Mask Set Register */ __O uint32_t CHNL_REQ_MASK_CLR; /* Offset: 0x024 ( /W) Channel Request Mask Clear Register */
__O uint32_t CHNL_REQ_MASK_CLR; /* Offset: 0x024 ( /W) Channel Request Mask Clear Register */ __IO uint32_t CHNL_ENABLE_SET; /* Offset: 0x028 (R/W) Channel Enable Set Register */
__IO uint32_t CHNL_ENABLE_SET; /* Offset: 0x028 (R/W) Channel Enable Set Register */ __O uint32_t CHNL_ENABLE_CLR; /* Offset: 0x02C ( /W) Channel Enable Clear Register */
__O uint32_t CHNL_ENABLE_CLR; /* Offset: 0x02C ( /W) Channel Enable Clear Register */ __IO uint32_t CHNL_PRI_ALT_SET; /* Offset: 0x030 (R/W) Channel Primary-Alterante Set Register */
__IO uint32_t CHNL_PRI_ALT_SET; /* Offset: 0x030 (R/W) Channel Primary-Alterante Set Register */ __O uint32_t CHNL_PRI_ALT_CLR; /* Offset: 0x034 ( /W) Channel Primary-Alterante Clear Register */
__O uint32_t CHNL_PRI_ALT_CLR; /* Offset: 0x034 ( /W) Channel Primary-Alterante Clear Register */ __IO uint32_t CHNL_PRIORITY_SET; /* Offset: 0x038 (R/W) Channel Priority Set Register */
__IO uint32_t CHNL_PRIORITY_SET; /* Offset: 0x038 (R/W) Channel Priority Set Register */ __O uint32_t CHNL_PRIORITY_CLR; /* Offset: 0x03C ( /W) Channel Priority Clear Register */
__O uint32_t CHNL_PRIORITY_CLR; /* Offset: 0x03C ( /W) Channel Priority Clear Register */ uint32_t RESERVED0[3];
uint32_t RESERVED0[3]; __IO uint32_t ERR_CLR; /* Offset: 0x04C Bus Error Clear Register (R/W) */
__IO uint32_t ERR_CLR; /* Offset: 0x04C Bus Error Clear Register (R/W) */
} CMSDK_PL230_TypeDef; } CMSDK_PL230_TypeDef;
@ -592,21 +584,20 @@ typedef struct
/*------------------- Watchdog ----------------------------------------------*/ /*------------------- Watchdog ----------------------------------------------*/
typedef struct typedef struct {
{
__IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */ __IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */
__I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */ __I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */
__IO uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */ __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */
__O uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */ __O uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */
__I uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */ __I uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */
__I uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */ __I uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */
uint32_t RESERVED0[762]; uint32_t RESERVED0[762];
__IO uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */ __IO uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */
uint32_t RESERVED1[191]; uint32_t RESERVED1[191];
__IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */ __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */
__O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */ __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */
}CMSDK_WATCHDOG_TypeDef; } CMSDK_WATCHDOG_TypeDef;
#define CMSDK_Watchdog_LOAD_Pos 0 /* CMSDK_Watchdog LOAD: LOAD Position */ #define CMSDK_Watchdog_LOAD_Pos 0 /* CMSDK_Watchdog LOAD: LOAD Position */
#define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /* CMSDK_Watchdog LOAD: LOAD Mask */ #define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /* CMSDK_Watchdog LOAD: LOAD Mask */
@ -642,17 +633,17 @@ typedef struct
/* -------------------- End of section using anonymous unions ------------------- */ /* -------------------- End of section using anonymous unions ------------------- */
#if defined ( __CC_ARM ) #if defined ( __CC_ARM )
#pragma pop #pragma pop
#elif defined(__ICCARM__) #elif defined(__ICCARM__)
/* leave anonymous unions enabled */ /* leave anonymous unions enabled */
#elif defined(__GNUC__) #elif defined(__GNUC__)
/* anonymous unions are enabled by default */ /* anonymous unions are enabled by default */
#elif defined(__TMS470__) #elif defined(__TMS470__)
/* anonymous unions are enabled by default */ /* anonymous unions are enabled by default */
#elif defined(__TASKING__) #elif defined(__TASKING__)
#pragma warning restore #pragma warning restore
#else #else
#warning Not supported compiler type #warning Not supported compiler type
#endif #endif

560
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/SMM_MPS2.h
View File

@ -46,40 +46,39 @@
/* FPGA System Register declaration */ /* FPGA System Register declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct typedef struct {
{ __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections
__IO uint32_t LED; // Offset: 0x000 (R/W) LED connections // [31:2] : Reserved
// [31:2] : Reserved // [1:0] : LEDs
// [1:0] : LEDs uint32_t RESERVED1[1];
uint32_t RESERVED1[1]; __IO uint32_t BUTTON; // Offset: 0x008 (R/W) Buttons
__IO uint32_t BUTTON; // Offset: 0x008 (R/W) Buttons // [31:2] : Reserved
// [31:2] : Reserved // [1:0] : Buttons
// [1:0] : Buttons uint32_t RESERVED2[1];
uint32_t RESERVED2[1]; __IO uint32_t CLK1HZ; // Offset: 0x010 (R/W) 1Hz up counter
__IO uint32_t CLK1HZ; // Offset: 0x010 (R/W) 1Hz up counter __IO uint32_t CLK100HZ; // Offset: 0x014 (R/W) 100Hz up counter
__IO uint32_t CLK100HZ; // Offset: 0x014 (R/W) 100Hz up counter __IO uint32_t COUNTER; // Offset: 0x018 (R/W) Cycle Up Counter
__IO uint32_t COUNTER; // Offset: 0x018 (R/W) Cycle Up Counter // Increments when 32-bit prescale counter reach zero
// Increments when 32-bit prescale counter reach zero uint32_t RESERVED3[1];
uint32_t RESERVED3[1]; __IO uint32_t PRESCALE; // Offset: 0x020 (R/W) Prescaler
__IO uint32_t PRESCALE; // Offset: 0x020 (R/W) Prescaler // Bit[31:0] : reload value for prescale counter
// Bit[31:0] : reload value for prescale counter __IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter
__IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter // current value of the pre-scaler counter
// current value of the pre-scaler counter // The Cycle Up Counter increment when the prescale down counter reach 0
// The Cycle Up Counter increment when the prescale down counter reach 0 // The pre-scaler counter is reloaded with PRESCALE after reaching 0.
// The pre-scaler counter is reloaded with PRESCALE after reaching 0. uint32_t RESERVED4[9];
uint32_t RESERVED4[9]; __IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */
__IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */ // [31:10] : Reserved
// [31:10] : Reserved // [9] : SHIELD_1_SPI_nCS
// [9] : SHIELD_1_SPI_nCS // [8] : SHIELD_0_SPI_nCS
// [8] : SHIELD_0_SPI_nCS // [7] : ADC_SPI_nCS
// [7] : ADC_SPI_nCS // [6] : CLCD_BL_CTRL
// [6] : CLCD_BL_CTRL // [5] : CLCD_RD
// [5] : CLCD_RD // [4] : CLCD_RS
// [4] : CLCD_RS // [3] : CLCD_RESET
// [3] : CLCD_RESET // [2] : RESERVED
// [2] : RESERVED // [1] : SPI_nSS
// [1] : SPI_nSS // [0] : CLCD_CS
// [0] : CLCD_CS
} MPS2_FPGAIO_TypeDef; } MPS2_FPGAIO_TypeDef;
// MISC register bit definitions // MISC register bit definitions
@ -107,58 +106,57 @@ typedef struct
/* SCC Register declaration */ /* SCC Register declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct // typedef struct { //
{ __IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT
__IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT // [31:1] : Reserved
// [31:1] : Reserved // [0] 1 : REMAP BlockRam to ZBT
// [0] 1 : REMAP BlockRam to ZBT __IO uint32_t LEDS; // Offset: 0x004 (R/W) Controls the MCC user LEDs
__IO uint32_t LEDS; // Offset: 0x004 (R/W) Controls the MCC user LEDs // [31:8] : Reserved
// [31:8] : Reserved // [7:0] : MCC LEDs
// [7:0] : MCC LEDs uint32_t RESERVED0[1];
uint32_t RESERVED0[1]; __I uint32_t SWITCHES; // Offset: 0x00C (R/ ) Denotes the state of the MCC user switches
__I uint32_t SWITCHES; // Offset: 0x00C (R/ ) Denotes the state of the MCC user switches // [31:8] : Reserved
// [31:8] : Reserved // [7:0] : These bits indicate state of the MCC switches
// [7:0] : These bits indicate state of the MCC switches __I uint32_t CFG_REG4; // Offset: 0x010 (R/ ) Denotes the board revision
__I uint32_t CFG_REG4; // Offset: 0x010 (R/ ) Denotes the board revision // [31:4] : Reserved
// [31:4] : Reserved // [3:0] : Used by the MCC to pass PCB revision. 0 = A 1 = B
// [3:0] : Used by the MCC to pass PCB revision. 0 = A 1 = B uint32_t RESERVED1[35];
uint32_t RESERVED1[35]; __IO uint32_t SYS_CFGDATA_RTN; // Offset: 0x0A0 (R/W) User data register
__IO uint32_t SYS_CFGDATA_RTN; // Offset: 0x0A0 (R/W) User data register // [31:0] : Data
// [31:0] : Data __IO uint32_t SYS_CFGDATA_OUT; // Offset: 0x0A4 (R/W) User data register
__IO uint32_t SYS_CFGDATA_OUT; // Offset: 0x0A4 (R/W) User data register // [31:0] : Data
// [31:0] : Data __IO uint32_t SYS_CFGCTRL; // Offset: 0x0A8 (R/W) Control register
__IO uint32_t SYS_CFGCTRL; // Offset: 0x0A8 (R/W) Control register // [31] : Start (generates interrupt on write to this bit)
// [31] : Start (generates interrupt on write to this bit) // [30] : R/W access
// [30] : R/W access // [29:26] : Reserved
// [29:26] : Reserved // [25:20] : Function value
// [25:20] : Function value // [19:12] : Reserved
// [19:12] : Reserved // [11:0] : Device (value of 0/1/2 for supported clocks)
// [11:0] : Device (value of 0/1/2 for supported clocks) __IO uint32_t SYS_CFGSTAT; // Offset: 0x0AC (R/W) Contains status information
__IO uint32_t SYS_CFGSTAT; // Offset: 0x0AC (R/W) Contains status information // [31:2] : Reserved
// [31:2] : Reserved // [1] : Error
// [1] : Error // [0] : Complete
// [0] : Complete __IO uint32_t RESERVED2[20];
__IO uint32_t RESERVED2[20]; __IO uint32_t SCC_DLL; // Offset: 0x100 (R/W) DLL Lock Register
__IO uint32_t SCC_DLL; // Offset: 0x100 (R/W) DLL Lock Register // [31:24] : DLL LOCK MASK[7:0] - Indicate if the DLL locked is masked
// [31:24] : DLL LOCK MASK[7:0] - Indicate if the DLL locked is masked // [23:16] : DLL LOCK MASK[7:0] - Indicate if the DLLs are locked or unlocked
// [23:16] : DLL LOCK MASK[7:0] - Indicate if the DLLs are locked or unlocked // [15:1] : Reserved
// [15:1] : Reserved // [0] : This bit indicates if all enabled DLLs are locked
// [0] : This bit indicates if all enabled DLLs are locked uint32_t RESERVED3[957];
uint32_t RESERVED3[957]; __I uint32_t SCC_AID; // Offset: 0xFF8 (R/ ) SCC AID Register
__I uint32_t SCC_AID; // Offset: 0xFF8 (R/ ) SCC AID Register // [31:24] : FPGA build number
// [31:24] : FPGA build number // [23:20] : V2M-MPS2 target board revision (A = 0, B = 1)
// [23:20] : V2M-MPS2 target board revision (A = 0, B = 1) // [19:11] : Reserved
// [19:11] : Reserved // [10] : if “1” SCC_SW register has been implemented
// [10] : if “1” SCC_SW register has been implemented // [9] : if “1” SCC_LED register has been implemented
// [9] : if “1” SCC_LED register has been implemented // [8] : if “1” DLL lock register has been implemented
// [8] : if “1” DLL lock register has been implemented // [7:0] : number of SCC configuration register
// [7:0] : number of SCC configuration register __I uint32_t SCC_ID; // Offset: 0xFFC (R/ ) Contains information about the FPGA image
__I uint32_t SCC_ID; // Offset: 0xFFC (R/ ) Contains information about the FPGA image // [31:24] : Implementer ID: 0x41 = ARM
// [31:24] : Implementer ID: 0x41 = ARM // [23:20] : Application note IP variant number
// [23:20] : Application note IP variant number // [19:16] : IP Architecture: 0x4 =AHB
// [19:16] : IP Architecture: 0x4 =AHB // [15:4] : Primary part number: 386 = AN386
// [15:4] : Primary part number: 386 = AN386 // [3:0] : Application note IP revision number
// [3:0] : Application note IP revision number
} MPS2_SCC_TypeDef; } MPS2_SCC_TypeDef;
@ -166,60 +164,59 @@ typedef struct //
/* SSP Peripheral declaration */ /* SSP Peripheral declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf typedef struct { // Document DDI0194G_ssp_pl022_r1p3_trm.pdf
{ __IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0
__IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0 // [31:16] : Reserved
// [31:16] : Reserved // [15:8] : Serial clock rate
// [15:8] : Serial clock rate // [7] : SSPCLKOUT phase, applicable to Motorola SPI frame format only
// [7] : SSPCLKOUT phase, applicable to Motorola SPI frame format only // [6] : SSPCLKOUT polarity, applicable to Motorola SPI frame format only
// [6] : SSPCLKOUT polarity, applicable to Motorola SPI frame format only // [5:4] : Frame format
// [5:4] : Frame format // [3:0] : Data Size Select
// [3:0] : Data Size Select __IO uint32_t CR1; // Offset: 0x004 (R/W) Control register 1
__IO uint32_t CR1; // Offset: 0x004 (R/W) Control register 1 // [31:4] : Reserved
// [31:4] : Reserved // [3] : Slave-mode output disable
// [3] : Slave-mode output disable // [2] : Master or slave mode select
// [2] : Master or slave mode select // [1] : Synchronous serial port enable
// [1] : Synchronous serial port enable // [0] : Loop back mode
// [0] : Loop back mode __IO uint32_t DR; // Offset: 0x008 (R/W) Data register
__IO uint32_t DR; // Offset: 0x008 (R/W) Data register // [31:16] : Reserved
// [31:16] : Reserved // [15:0] : Transmit/Receive FIFO
// [15:0] : Transmit/Receive FIFO __I uint32_t SR; // Offset: 0x00C (R/ ) Status register
__I uint32_t SR; // Offset: 0x00C (R/ ) Status register // [31:5] : Reserved
// [31:5] : Reserved // [4] : PrimeCell SSP busy flag
// [4] : PrimeCell SSP busy flag // [3] : Receive FIFO full
// [3] : Receive FIFO full // [2] : Receive FIFO not empty
// [2] : Receive FIFO not empty // [1] : Transmit FIFO not full
// [1] : Transmit FIFO not full // [0] : Transmit FIFO empty
// [0] : Transmit FIFO empty __IO uint32_t CPSR; // Offset: 0x010 (R/W) Clock prescale register
__IO uint32_t CPSR; // Offset: 0x010 (R/W) Clock prescale register // [31:8] : Reserved
// [31:8] : Reserved // [8:0] : Clock prescale divisor
// [8:0] : Clock prescale divisor __IO uint32_t IMSC; // Offset: 0x014 (R/W) Interrupt mask set or clear register
__IO uint32_t IMSC; // Offset: 0x014 (R/W) Interrupt mask set or clear register // [31:4] : Reserved
// [31:4] : Reserved // [3] : Transmit FIFO interrupt mask
// [3] : Transmit FIFO interrupt mask // [2] : Receive FIFO interrupt mask
// [2] : Receive FIFO interrupt mask // [1] : Receive timeout interrupt mask
// [1] : Receive timeout interrupt mask // [0] : Receive overrun interrupt mask
// [0] : Receive overrun interrupt mask __I uint32_t RIS; // Offset: 0x018 (R/ ) Raw interrupt status register
__I uint32_t RIS; // Offset: 0x018 (R/ ) Raw interrupt status register // [31:4] : Reserved
// [31:4] : Reserved // [3] : raw interrupt state, prior to masking, of the SSPTXINTR interrupt
// [3] : raw interrupt state, prior to masking, of the SSPTXINTR interrupt // [2] : raw interrupt state, prior to masking, of the SSPRXINTR interrupt
// [2] : raw interrupt state, prior to masking, of the SSPRXINTR interrupt // [1] : raw interrupt state, prior to masking, of the SSPRTINTR interrupt
// [1] : raw interrupt state, prior to masking, of the SSPRTINTR interrupt // [0] : raw interrupt state, prior to masking, of the SSPRORINTR interrupt
// [0] : raw interrupt state, prior to masking, of the SSPRORINTR interrupt __I uint32_t MIS; // Offset: 0x01C (R/ ) Masked interrupt status register
__I uint32_t MIS; // Offset: 0x01C (R/ ) Masked interrupt status register // [31:4] : Reserved
// [31:4] : Reserved // [3] : transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt
// [3] : transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt // [2] : receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt
// [2] : receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt // [1] : receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt
// [1] : receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt // [0] : receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt
// [0] : receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt __O uint32_t ICR; // Offset: 0x020 ( /W) Interrupt clear register
__O uint32_t ICR; // Offset: 0x020 ( /W) Interrupt clear register // [31:2] : Reserved
// [31:2] : Reserved // [1] : Clears the SSPRTINTR interrupt
// [1] : Clears the SSPRTINTR interrupt // [0] : Clears the SSPRORINTR interrupt
// [0] : Clears the SSPRORINTR interrupt __IO uint32_t DMACR; // Offset: 0x024 (R/W) DMA control register
__IO uint32_t DMACR; // Offset: 0x024 (R/W) DMA control register // [31:2] : Reserved
// [31:2] : Reserved // [1] : Transmit DMA Enable
// [1] : Transmit DMA Enable // [0] : Receive DMA Enable
// [0] : Receive DMA Enable
} MPS2_SSP_TypeDef; } MPS2_SSP_TypeDef;
@ -314,13 +311,12 @@ typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf
/* Audio and Touch Screen (I2C) Peripheral declaration */ /* Audio and Touch Screen (I2C) Peripheral declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct typedef struct {
{ union {
union { __O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W)
__O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W) __I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ )
__I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ ) };
}; __O uint32_t CONTROLC; // Offset: 0x004 CONTROL Clear Register ( /W)
__O uint32_t CONTROLC; // Offset: 0x004 CONTROL Clear Register ( /W)
} MPS2_I2C_TypeDef; } MPS2_I2C_TypeDef;
#define SDA 1 << 1 #define SDA 1 << 1
@ -331,107 +327,106 @@ typedef struct
/* Audio I2S Peripheral declaration */ /* Audio I2S Peripheral declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct typedef struct {
{ /*!< Offset: 0x000 CONTROL Register (R/W) */
/*!< Offset: 0x000 CONTROL Register (R/W) */ __IO uint32_t CONTROL; // <h> CONTROL </h>
__IO uint32_t CONTROL; // <h> CONTROL </h> // <o.0> TX Enable
// <o.0> TX Enable // <0=> TX disabled
// <0=> TX disabled // <1=> TX enabled
// <1=> TX enabled // <o.1> TX IRQ Enable
// <o.1> TX IRQ Enable // <0=> TX IRQ disabled
// <0=> TX IRQ disabled // <1=> TX IRQ enabled
// <1=> TX IRQ enabled // <o.2> RX Enable
// <o.2> RX Enable // <0=> RX disabled
// <0=> RX disabled // <1=> RX enabled
// <1=> RX enabled // <o.3> RX IRQ Enable
// <o.3> RX IRQ Enable // <0=> RX IRQ disabled
// <0=> RX IRQ disabled // <1=> RX IRQ enabled
// <1=> RX IRQ enabled // <o.10..8> TX Buffer Water Level
// <o.10..8> TX Buffer Water Level // <0=> / IRQ triggers when any space available
// <0=> / IRQ triggers when any space available // <1=> / IRQ triggers when more than 1 space available
// <1=> / IRQ triggers when more than 1 space available // <2=> / IRQ triggers when more than 2 space available
// <2=> / IRQ triggers when more than 2 space available // <3=> / IRQ triggers when more than 3 space available
// <3=> / IRQ triggers when more than 3 space available // <4=> Undefined!
// <4=> Undefined! // <5=> Undefined!
// <5=> Undefined! // <6=> Undefined!
// <6=> Undefined! // <7=> Undefined!
// <7=> Undefined! // <o.14..12> RX Buffer Water Level
// <o.14..12> RX Buffer Water Level // <0=> Undefined!
// <0=> Undefined! // <1=> / IRQ triggers when less than 1 space available
// <1=> / IRQ triggers when less than 1 space available // <2=> / IRQ triggers when less than 2 space available
// <2=> / IRQ triggers when less than 2 space available // <3=> / IRQ triggers when less than 3 space available
// <3=> / IRQ triggers when less than 3 space available // <4=> / IRQ triggers when less than 4 space available
// <4=> / IRQ triggers when less than 4 space available // <5=> Undefined!
// <5=> Undefined! // <6=> Undefined!
// <6=> Undefined! // <7=> Undefined!
// <7=> Undefined! // <o.16> FIFO reset
// <o.16> FIFO reset // <0=> Normal operation
// <0=> Normal operation // <1=> FIFO reset
// <1=> FIFO reset // <o.17> Audio Codec reset
// <o.17> Audio Codec reset // <0=> Normal operation
// <0=> Normal operation // <1=> Assert audio Codec reset
// <1=> Assert audio Codec reset /*!< Offset: 0x004 STATUS Register (R/ ) */
/*!< Offset: 0x004 STATUS Register (R/ ) */ __I uint32_t STATUS; // <h> STATUS </h>
__I uint32_t STATUS; // <h> STATUS </h> // <o.0> TX Buffer alert
// <o.0> TX Buffer alert // <0=> TX buffer don't need service yet
// <0=> TX buffer don't need service yet // <1=> TX buffer need service
// <1=> TX buffer need service // <o.1> RX Buffer alert
// <o.1> RX Buffer alert // <0=> RX buffer don't need service yet
// <0=> RX buffer don't need service yet // <1=> RX buffer need service
// <1=> RX buffer need service // <o.2> TX Buffer Empty
// <o.2> TX Buffer Empty // <0=> TX buffer have data
// <0=> TX buffer have data // <1=> TX buffer empty
// <1=> TX buffer empty // <o.3> TX Buffer Full
// <o.3> TX Buffer Full // <0=> TX buffer not full
// <0=> TX buffer not full // <1=> TX buffer full
// <1=> TX buffer full // <o.4> RX Buffer Empty
// <o.4> RX Buffer Empty // <0=> RX buffer have data
// <0=> RX buffer have data // <1=> RX buffer empty
// <1=> RX buffer empty // <o.5> RX Buffer Full
// <o.5> RX Buffer Full // <0=> RX buffer not full
// <0=> RX buffer not full // <1=> RX buffer full
// <1=> RX buffer full union {
union { /*!< Offset: 0x008 Error Status Register (R/ ) */
/*!< Offset: 0x008 Error Status Register (R/ ) */ __I uint32_t ERROR; // <h> ERROR </h>
__I uint32_t ERROR; // <h> ERROR </h> // <o.0> TX error
// <o.0> TX error // <0=> Okay
// <0=> Okay // <1=> TX overrun/underrun
// <1=> TX overrun/underrun // <o.1> RX error
// <o.1> RX error // <0=> Okay
// <0=> Okay // <1=> RX overrun/underrun
// <1=> RX overrun/underrun /*!< Offset: 0x008 Error Clear Register ( /W) */
/*!< Offset: 0x008 Error Clear Register ( /W) */ __O uint32_t ERRORCLR; // <h> ERRORCLR </h>
__O uint32_t ERRORCLR; // <h> ERRORCLR </h> // <o.0> TX error
// <o.0> TX error // <0=> Okay
// <0=> Okay // <1=> Clear TX error
// <1=> Clear TX error // <o.1> RX error
// <o.1> RX error // <0=> Okay
// <0=> Okay // <1=> Clear RX error
// <1=> Clear RX error
}; };
/*!< Offset: 0x00C Divide ratio Register (R/W) */ /*!< Offset: 0x00C Divide ratio Register (R/W) */
__IO uint32_t DIVIDE; // <h> Divide ratio for Left/Right clock </h> __IO uint32_t DIVIDE; // <h> Divide ratio for Left/Right clock </h>
// <o.9..0> TX error (default 0x80) // <o.9..0> TX error (default 0x80)
/*!< Offset: 0x010 Transmit Buffer ( /W) */ /*!< Offset: 0x010 Transmit Buffer ( /W) */
__O uint32_t TXBUF; // <h> Transmit buffer </h> __O uint32_t TXBUF; // <h> Transmit buffer </h>
// <o.15..0> Right channel // <o.15..0> Right channel
// <o.31..16> Left channel // <o.31..16> Left channel
/*!< Offset: 0x014 Receive Buffer (R/ ) */ /*!< Offset: 0x014 Receive Buffer (R/ ) */
__I uint32_t RXBUF; // <h> Receive buffer </h> __I uint32_t RXBUF; // <h> Receive buffer </h>
// <o.15..0> Right channel // <o.15..0> Right channel
// <o.31..16> Left channel // <o.31..16> Left channel
uint32_t RESERVED1[186]; uint32_t RESERVED1[186];
__IO uint32_t ITCR; // <h> Integration Test Control Register </h> __IO uint32_t ITCR; // <h> Integration Test Control Register </h>
// <o.0> ITEN // <o.0> ITEN
// <0=> Normal operation // <0=> Normal operation
// <1=> Integration Test mode enable // <1=> Integration Test mode enable
__O uint32_t ITIP1; // <h> Integration Test Input Register 1</h> __O uint32_t ITIP1; // <h> Integration Test Input Register 1</h>
// <o.0> SDIN // <o.0> SDIN
__O uint32_t ITOP1; // <h> Integration Test Output Register 1</h> __O uint32_t ITOP1; // <h> Integration Test Output Register 1</h>
// <o.0> SDOUT // <o.0> SDOUT
// <o.1> SCLK // <o.1> SCLK
// <o.2> LRCK // <o.2> LRCK
// <o.3> IRQOUT // <o.3> IRQOUT
} MPS2_I2S_TypeDef; } MPS2_I2S_TypeDef;
#define I2S_CONTROL_TXEN_Pos 0 #define I2S_CONTROL_TXEN_Pos 0
@ -486,44 +481,43 @@ typedef struct
/* SMSC9220 Register Definitions */ /* SMSC9220 Register Definitions */
/******************************************************************************/ /******************************************************************************/
typedef struct // SMSC LAN9220 typedef struct { // SMSC LAN9220
{ __I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0)
__I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0) uint32_t RESERVED1[0x7];
uint32_t RESERVED1[0x7]; __O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20)
__O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20) uint32_t RESERVED2[0x7];
uint32_t RESERVED2[0x7];
__I uint32_t RX_STAT_PORT; // Receive FIFO status port (offset 0x40) __I uint32_t RX_STAT_PORT; // Receive FIFO status port (offset 0x40)
__I uint32_t RX_STAT_PEEK; // Receive FIFO status peek (offset 0x44) __I uint32_t RX_STAT_PEEK; // Receive FIFO status peek (offset 0x44)
__I uint32_t TX_STAT_PORT; // Transmit FIFO status port (offset 0x48) __I uint32_t TX_STAT_PORT; // Transmit FIFO status port (offset 0x48)
__I uint32_t TX_STAT_PEEK; // Transmit FIFO status peek (offset 0x4C) __I uint32_t TX_STAT_PEEK; // Transmit FIFO status peek (offset 0x4C)
__I uint32_t ID_REV; // Chip ID and Revision (offset 0x50) __I uint32_t ID_REV; // Chip ID and Revision (offset 0x50)
__IO uint32_t IRQ_CFG; // Main Interrupt Configuration (offset 0x54) __IO uint32_t IRQ_CFG; // Main Interrupt Configuration (offset 0x54)
__IO uint32_t INT_STS; // Interrupt Status (offset 0x58) __IO uint32_t INT_STS; // Interrupt Status (offset 0x58)
__IO uint32_t INT_EN; // Interrupt Enable Register (offset 0x5C) __IO uint32_t INT_EN; // Interrupt Enable Register (offset 0x5C)
uint32_t RESERVED3; // Reserved for future use (offset 0x60) uint32_t RESERVED3; // Reserved for future use (offset 0x60)
__I uint32_t BYTE_TEST; // Read-only byte order testing register 87654321h (offset 0x64) __I uint32_t BYTE_TEST; // Read-only byte order testing register 87654321h (offset 0x64)
__IO uint32_t FIFO_INT; // FIFO Level Interrupts (offset 0x68) __IO uint32_t FIFO_INT; // FIFO Level Interrupts (offset 0x68)
__IO uint32_t RX_CFG; // Receive Configuration (offset 0x6C) __IO uint32_t RX_CFG; // Receive Configuration (offset 0x6C)
__IO uint32_t TX_CFG; // Transmit Configuration (offset 0x70) __IO uint32_t TX_CFG; // Transmit Configuration (offset 0x70)
__IO uint32_t HW_CFG; // Hardware Configuration (offset 0x74) __IO uint32_t HW_CFG; // Hardware Configuration (offset 0x74)
__IO uint32_t RX_DP_CTL; // RX Datapath Control (offset 0x78) __IO uint32_t RX_DP_CTL; // RX Datapath Control (offset 0x78)
__I uint32_t RX_FIFO_INF; // Receive FIFO Information (offset 0x7C) __I uint32_t RX_FIFO_INF; // Receive FIFO Information (offset 0x7C)
__I uint32_t TX_FIFO_INF; // Transmit FIFO Information (offset 0x80) __I uint32_t TX_FIFO_INF; // Transmit FIFO Information (offset 0x80)
__IO uint32_t PMT_CTRL; // Power Management Control (offset 0x84) __IO uint32_t PMT_CTRL; // Power Management Control (offset 0x84)
__IO uint32_t GPIO_CFG; // General Purpose IO Configuration (offset 0x88) __IO uint32_t GPIO_CFG; // General Purpose IO Configuration (offset 0x88)
__IO uint32_t GPT_CFG; // General Purpose Timer Configuration (offset 0x8C) __IO uint32_t GPT_CFG; // General Purpose Timer Configuration (offset 0x8C)
__I uint32_t GPT_CNT; // General Purpose Timer Count (offset 0x90) __I uint32_t GPT_CNT; // General Purpose Timer Count (offset 0x90)
uint32_t RESERVED4; // Reserved for future use (offset 0x94) uint32_t RESERVED4; // Reserved for future use (offset 0x94)
__IO uint32_t ENDIAN; // WORD SWAP Register (offset 0x98) __IO uint32_t ENDIAN; // WORD SWAP Register (offset 0x98)
__I uint32_t FREE_RUN; // Free Run Counter (offset 0x9C) __I uint32_t FREE_RUN; // Free Run Counter (offset 0x9C)
__I uint32_t RX_DROP; // RX Dropped Frames Counter (offset 0xA0) __I uint32_t RX_DROP; // RX Dropped Frames Counter (offset 0xA0)
__IO uint32_t MAC_CSR_CMD; // MAC CSR Synchronizer Command (offset 0xA4) __IO uint32_t MAC_CSR_CMD; // MAC CSR Synchronizer Command (offset 0xA4)
__IO uint32_t MAC_CSR_DATA; // MAC CSR Synchronizer Data (offset 0xA8) __IO uint32_t MAC_CSR_DATA; // MAC CSR Synchronizer Data (offset 0xA8)
__IO uint32_t AFC_CFG; // Automatic Flow Control Configuration (offset 0xAC) __IO uint32_t AFC_CFG; // Automatic Flow Control Configuration (offset 0xAC)
__IO uint32_t E2P_CMD; // EEPROM Command (offset 0xB0) __IO uint32_t E2P_CMD; // EEPROM Command (offset 0xB0)
__IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4) __IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4)
} SMSC9220_TypeDef; } SMSC9220_TypeDef;

12
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/peripherallink.h
View File

@ -37,17 +37,17 @@
#define __DEVICE_H #define __DEVICE_H
#if defined CMSDK_CM0 #if defined CMSDK_CM0
#include "CMSDK_CM0.h" /* device specific header file */ #include "CMSDK_CM0.h" /* device specific header file */
#elif defined CMSDK_CM0plus #elif defined CMSDK_CM0plus
#include "CMSDK_CM0plus.h" /* device specific header file */ #include "CMSDK_CM0plus.h" /* device specific header file */
#elif defined CMSDK_CM3 #elif defined CMSDK_CM3
#include "CMSDK_CM3.h" /* device specific header file */ #include "CMSDK_CM3.h" /* device specific header file */
#elif defined CMSDK_CM4 #elif defined CMSDK_CM4
#include "CMSDK_CM4.h" /* device specific header file */ #include "CMSDK_CM4.h" /* device specific header file */
#elif defined CMSDK_CM7 #elif defined CMSDK_CM7
#include "CMSDK_CM7.h" /* device specific header file */ #include "CMSDK_CM7.h" /* device specific header file */
#else #else
#warning "no appropriate header file found!" #warning "no appropriate header file found!"
#endif #endif
#endif /* __DEVICE_H */ #endif /* __DEVICE_H */

8
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/system_CMSDK_CM0plus.c
View File

@ -64,10 +64,10 @@ uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Cloc
* @brief Updates the SystemCoreClock with current core Clock * @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers. * retrieved from cpu registers.
*/ */
void SystemCoreClockUpdate (void) void SystemCoreClockUpdate(void)
{ {
SystemCoreClock = __SYSTEM_CLOCK; SystemCoreClock = __SYSTEM_CLOCK;
} }
@ -80,9 +80,9 @@ void SystemCoreClockUpdate (void)
* @brief Setup the microcontroller system. * @brief Setup the microcontroller system.
* Initialize the System. * Initialize the System.
*/ */
void SystemInit (void) void SystemInit(void)
{ {
SystemCoreClock = __SYSTEM_CLOCK; SystemCoreClock = __SYSTEM_CLOCK;
} }

4
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/system_CMSDK_CM0plus.h
View File

@ -56,7 +56,7 @@ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) *
* @brief Setup the microcontroller system. * @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable. * Initialize the System and update the SystemCoreClock variable.
*/ */
extern void SystemInit (void); extern void SystemInit(void);
/** /**
* Update SystemCoreClock variable * Update SystemCoreClock variable
@ -67,7 +67,7 @@ extern void SystemInit (void);
* @brief Updates the SystemCoreClock with current core Clock * @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers. * retrieved from cpu registers.
*/ */
extern void SystemCoreClockUpdate (void); extern void SystemCoreClockUpdate(void);
#ifdef __cplusplus #ifdef __cplusplus
} }

321
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/CMSDK_CM3.h
View File

@ -40,58 +40,57 @@
#define CMSDK_CM3_H #define CMSDK_CM3_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* ------------------------- Interrupt Number Definition ------------------------ */ /* ------------------------- Interrupt Number Definition ------------------------ */
typedef enum IRQn typedef enum IRQn {
{ /* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
/* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */ NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ HardFault_IRQn = -13, /* 3 HardFault Interrupt */
HardFault_IRQn = -13, /* 3 HardFault Interrupt */ MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ SVCall_IRQn = -5, /* 11 SV Call Interrupt */
SVCall_IRQn = -5, /* 11 SV Call Interrupt */ DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ SysTick_IRQn = -1, /* 15 System Tick Interrupt */
SysTick_IRQn = -1, /* 15 System Tick Interrupt */
/****** CMSDK Specific Interrupt Numbers *********************************************************/ /****** CMSDK Specific Interrupt Numbers *********************************************************/
UARTRX0_IRQn = 0, /*!< UART 0 RX Interrupt */ UARTRX0_IRQn = 0, /*!< UART 0 RX Interrupt */
UARTTX0_IRQn = 1, /*!< UART 0 TX Interrupt */ UARTTX0_IRQn = 1, /*!< UART 0 TX Interrupt */
UARTRX1_IRQn = 2, /*!< UART 1 RX Interrupt */ UARTRX1_IRQn = 2, /*!< UART 1 RX Interrupt */
UARTTX1_IRQn = 3, /*!< UART 1 TX Interrupt */ UARTTX1_IRQn = 3, /*!< UART 1 TX Interrupt */
UARTRX2_IRQn = 4, /*!< UART 2 RX Interrupt */ UARTRX2_IRQn = 4, /*!< UART 2 RX Interrupt */
UARTTX2_IRQn = 5, /*!< UART 2 TX Interrupt */ UARTTX2_IRQn = 5, /*!< UART 2 TX Interrupt */
PORT0_ALL_IRQn = 6, /*!< Port 0 combined Interrupt */ PORT0_ALL_IRQn = 6, /*!< Port 0 combined Interrupt */
PORT1_ALL_IRQn = 7, /*!< Port 1 combined Interrupt */ PORT1_ALL_IRQn = 7, /*!< Port 1 combined Interrupt */
TIMER0_IRQn = 8, /*!< TIMER 0 Interrupt */ TIMER0_IRQn = 8, /*!< TIMER 0 Interrupt */
TIMER1_IRQn = 9, /*!< TIMER 1 Interrupt */ TIMER1_IRQn = 9, /*!< TIMER 1 Interrupt */
DUALTIMER_IRQn = 10, /*!< Dual Timer Interrupt */ DUALTIMER_IRQn = 10, /*!< Dual Timer Interrupt */
SPI_IRQn = 11, /*!< SPI Interrupt */ SPI_IRQn = 11, /*!< SPI Interrupt */
UARTOVF_IRQn = 12, /*!< UART 0,1,2 Overflow Interrupt */ UARTOVF_IRQn = 12, /*!< UART 0,1,2 Overflow Interrupt */
ETHERNET_IRQn = 13, /*!< Ethernet Interrupt */ ETHERNET_IRQn = 13, /*!< Ethernet Interrupt */
I2S_IRQn = 14, /*!< I2S Interrupt */ I2S_IRQn = 14, /*!< I2S Interrupt */
TSC_IRQn = 15, /*!< Touch Screen Interrupt */ TSC_IRQn = 15, /*!< Touch Screen Interrupt */
PORT2_ALL_IRQn = 16, /*!< Port 2 combined Interrupt */ PORT2_ALL_IRQn = 16, /*!< Port 2 combined Interrupt */
PORT3_ALL_IRQn = 17, /*!< Port 3 combined Interrupt */ PORT3_ALL_IRQn = 17, /*!< Port 3 combined Interrupt */
UARTRX3_IRQn = 18, /*!< UART 3 RX Interrupt */ UARTRX3_IRQn = 18, /*!< UART 3 RX Interrupt */
UARTTX3_IRQn = 19, /*!< UART 3 TX Interrupt */ UARTTX3_IRQn = 19, /*!< UART 3 TX Interrupt */
UARTRX4_IRQn = 20, /*!< UART 4 RX Interrupt */ UARTRX4_IRQn = 20, /*!< UART 4 RX Interrupt */
UARTTX4_IRQn = 21, /*!< UART 4 TX Interrupt */ UARTTX4_IRQn = 21, /*!< UART 4 TX Interrupt */
ADCSPI_IRQn = 22, /*!< SHIELD ADC SPI Interrupt */ ADCSPI_IRQn = 22, /*!< SHIELD ADC SPI Interrupt */
SHIELDSPI_IRQn = 23, /*!< SHIELD SPI Combined Interrupt */ SHIELDSPI_IRQn = 23, /*!< SHIELD SPI Combined Interrupt */
PORT0_0_IRQn = 24, /*!< GPIO Port 0 pin 0 Interrupt */ PORT0_0_IRQn = 24, /*!< GPIO Port 0 pin 0 Interrupt */
PORT0_1_IRQn = 25, /*!< GPIO Port 0 pin 1 Interrupt */ PORT0_1_IRQn = 25, /*!< GPIO Port 0 pin 1 Interrupt */
PORT0_2_IRQn = 26, /*!< GPIO Port 0 pin 2 Interrupt */ PORT0_2_IRQn = 26, /*!< GPIO Port 0 pin 2 Interrupt */
PORT0_3_IRQn = 27, /*!< GPIO Port 0 pin 3 Interrupt */ PORT0_3_IRQn = 27, /*!< GPIO Port 0 pin 3 Interrupt */
PORT0_4_IRQn = 28, /*!< GPIO Port 0 pin 4 Interrupt */ PORT0_4_IRQn = 28, /*!< GPIO Port 0 pin 4 Interrupt */
PORT0_5_IRQn = 29, /*!< GPIO Port 0 pin 5 Interrupt */ PORT0_5_IRQn = 29, /*!< GPIO Port 0 pin 5 Interrupt */
PORT0_6_IRQn = 30, /*!< GPIO Port 0 pin 6 Interrupt */ PORT0_6_IRQn = 30, /*!< GPIO Port 0 pin 6 Interrupt */
PORT0_7_IRQn = 31, /*!< GPIO Port 0 pin 7 Interrupt */ PORT0_7_IRQn = 31, /*!< GPIO Port 0 pin 7 Interrupt */
} IRQn_Type; } IRQn_Type;
@ -115,31 +114,30 @@ typedef enum IRQn
/* ------------------- Start of section using anonymous unions ------------------ */ /* ------------------- Start of section using anonymous unions ------------------ */
#if defined ( __CC_ARM ) #if defined ( __CC_ARM )
#pragma push #pragma push
#pragma anon_unions #pragma anon_unions
#elif defined(__ICCARM__) #elif defined(__ICCARM__)
#pragma language=extended #pragma language=extended
#elif defined(__GNUC__) #elif defined(__GNUC__)
/* anonymous unions are enabled by default */ /* anonymous unions are enabled by default */
#elif defined(__TMS470__) #elif defined(__TMS470__)
/* anonymous unions are enabled by default */ /* anonymous unions are enabled by default */
#elif defined(__TASKING__) #elif defined(__TASKING__)
#pragma warning 586 #pragma warning 586
#else #else
#warning Not supported compiler type #warning Not supported compiler type
#endif #endif
/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
typedef struct typedef struct {
{ __IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */
__IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */ __IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */
__IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */ __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */
__IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */ union {
union { __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */
__I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */ __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */
__O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */
}; };
__IO uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register */ __IO uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register */
} CMSDK_UART_TypeDef; } CMSDK_UART_TypeDef;
@ -198,14 +196,13 @@ typedef struct
/*----------------------------- Timer (TIMER) -------------------------------*/ /*----------------------------- Timer (TIMER) -------------------------------*/
typedef struct typedef struct {
{ __IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */
__IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */ __IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */
__IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */ __IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */
__IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */ union {
union { __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */
__I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */ __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */
__O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */
}; };
} CMSDK_TIMER_TypeDef; } CMSDK_TIMER_TypeDef;
@ -238,26 +235,25 @@ typedef struct
/*------------- Timer (TIM) --------------------------------------------------*/ /*------------- Timer (TIM) --------------------------------------------------*/
typedef struct typedef struct {
{ __IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
__IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */ __I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
__I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */ __IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
__IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */ __O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
__O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */ __I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
__I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */ __I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
__I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */ __IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */
__IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */ uint32_t RESERVED0;
uint32_t RESERVED0; __IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */
__IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */ __I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
__I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */ __IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */
__IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */ __O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
__O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */ __I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
__I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */ __I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
__I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */ __IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */
__IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */ uint32_t RESERVED1[945];
uint32_t RESERVED1[945]; __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Integration Test Control Register */
__IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Integration Test Control Register */ __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Integration Test Output Set Register */
__O uint32_t ITOP; /* Offset: 0xF04 ( /W) Integration Test Output Set Register */
} CMSDK_DUALTIMER_BOTH_TypeDef; } CMSDK_DUALTIMER_BOTH_TypeDef;
#define CMSDK_DUALTIMER1_LOAD_Pos 0 /* CMSDK_DUALTIMER1 LOAD: LOAD Position */ #define CMSDK_DUALTIMER1_LOAD_Pos 0 /* CMSDK_DUALTIMER1 LOAD: LOAD Position */
@ -333,15 +329,14 @@ typedef struct
#define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /* CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */ #define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /* CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */
typedef struct typedef struct {
{ __IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */
__IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */ __I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */
__I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */ __IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */
__IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */ __O uint32_t TimerIntClr; /* Offset: 0x000 (R/W) Timer Interrupt Clear */
__O uint32_t TimerIntClr; /* Offset: 0x000 (R/W) Timer Interrupt Clear */ __I uint32_t TimerRIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */
__I uint32_t TimerRIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */ __I uint32_t TimerMIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */
__I uint32_t TimerMIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */ __IO uint32_t TimerBGLoad; /* Offset: 0x000 (R/W) Background Load Register */
__IO uint32_t TimerBGLoad; /* Offset: 0x000 (R/W) Background Load Register */
} CMSDK_DUALTIMER_SINGLE_TypeDef; } CMSDK_DUALTIMER_SINGLE_TypeDef;
#define CMSDK_DUALTIMER_LOAD_Pos 0 /* CMSDK_DUALTIMER LOAD: LOAD Position */ #define CMSDK_DUALTIMER_LOAD_Pos 0 /* CMSDK_DUALTIMER LOAD: LOAD Position */
@ -382,28 +377,27 @@ typedef struct
/*-------------------- General Purpose Input Output (GPIO) -------------------*/ /*-------------------- General Purpose Input Output (GPIO) -------------------*/
typedef struct typedef struct {
{ __IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */
__IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */ __IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */
__IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */ uint32_t RESERVED0[2];
uint32_t RESERVED0[2]; __IO uint32_t OUTENABLESET; /* Offset: 0x010 (R/W) Output Enable Set Register */
__IO uint32_t OUTENABLESET; /* Offset: 0x010 (R/W) Output Enable Set Register */ __IO uint32_t OUTENABLECLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */
__IO uint32_t OUTENABLECLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */ __IO uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */
__IO uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */ __IO uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */
__IO uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */ __IO uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */
__IO uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */ __IO uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */
__IO uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */ __IO uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */
__IO uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */ __IO uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */
__IO uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */ __IO uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */
__IO uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */ __IO uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */
__IO uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */ union {
union { __I uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */
__I uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */ __O uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */
__O uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */
}; };
uint32_t RESERVED1[241]; uint32_t RESERVED1[241];
__IO uint32_t LB_MASKED[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */ __IO uint32_t LB_MASKED[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */
__IO uint32_t UB_MASKED[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */ __IO uint32_t UB_MASKED[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */
} CMSDK_GPIO_TypeDef; } CMSDK_GPIO_TypeDef;
#define CMSDK_GPIO_DATA_Pos 0 /* CMSDK_GPIO DATA: DATA Position */ #define CMSDK_GPIO_DATA_Pos 0 /* CMSDK_GPIO DATA: DATA Position */
@ -456,13 +450,12 @@ typedef struct
/*------------- System Control (SYSCON) --------------------------------------*/ /*------------- System Control (SYSCON) --------------------------------------*/
typedef struct typedef struct {
{ __IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */
__IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */ __IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */
__IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */ __IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */
__IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */ __IO uint32_t EMICTRL; /* Offset: 0x00C (R/W) EMI Control Register */
__IO uint32_t EMICTRL; /* Offset: 0x00C (R/W) EMI Control Register */ __IO uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */
__IO uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */
} CMSDK_SYSCON_TypeDef; } CMSDK_SYSCON_TypeDef;
#define CMSDK_SYSCON_REMAP_Pos 0 #define CMSDK_SYSCON_REMAP_Pos 0
@ -497,26 +490,25 @@ typedef struct
/*------------- PL230 uDMA (PL230) --------------------------------------*/ /*------------- PL230 uDMA (PL230) --------------------------------------*/
typedef struct typedef struct {
{ __I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */
__I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */ __O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */
__O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */ __IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */
__IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */ __I uint32_t ALT_CTRL_BASE_PTR; /* Offset: 0x00C (R/ ) Channel Alternate Control Data Base Pointer Register */
__I uint32_t ALT_CTRL_BASE_PTR; /* Offset: 0x00C (R/ ) Channel Alternate Control Data Base Pointer Register */ __I uint32_t DMA_WAITONREQ_STATUS; /* Offset: 0x010 (R/ ) Channel Wait On Request Status Register */
__I uint32_t DMA_WAITONREQ_STATUS; /* Offset: 0x010 (R/ ) Channel Wait On Request Status Register */ __O uint32_t CHNL_SW_REQUEST; /* Offset: 0x014 ( /W) Channel Software Request Register */
__O uint32_t CHNL_SW_REQUEST; /* Offset: 0x014 ( /W) Channel Software Request Register */ __IO uint32_t CHNL_USEBURST_SET; /* Offset: 0x018 (R/W) Channel UseBurst Set Register */
__IO uint32_t CHNL_USEBURST_SET; /* Offset: 0x018 (R/W) Channel UseBurst Set Register */ __O uint32_t CHNL_USEBURST_CLR; /* Offset: 0x01C ( /W) Channel UseBurst Clear Register */
__O uint32_t CHNL_USEBURST_CLR; /* Offset: 0x01C ( /W) Channel UseBurst Clear Register */ __IO uint32_t CHNL_REQ_MASK_SET; /* Offset: 0x020 (R/W) Channel Request Mask Set Register */
__IO uint32_t CHNL_REQ_MASK_SET; /* Offset: 0x020 (R/W) Channel Request Mask Set Register */ __O uint32_t CHNL_REQ_MASK_CLR; /* Offset: 0x024 ( /W) Channel Request Mask Clear Register */
__O uint32_t CHNL_REQ_MASK_CLR; /* Offset: 0x024 ( /W) Channel Request Mask Clear Register */ __IO uint32_t CHNL_ENABLE_SET; /* Offset: 0x028 (R/W) Channel Enable Set Register */
__IO uint32_t CHNL_ENABLE_SET; /* Offset: 0x028 (R/W) Channel Enable Set Register */ __O uint32_t CHNL_ENABLE_CLR; /* Offset: 0x02C ( /W) Channel Enable Clear Register */
__O uint32_t CHNL_ENABLE_CLR; /* Offset: 0x02C ( /W) Channel Enable Clear Register */ __IO uint32_t CHNL_PRI_ALT_SET; /* Offset: 0x030 (R/W) Channel Primary-Alterante Set Register */
__IO uint32_t CHNL_PRI_ALT_SET; /* Offset: 0x030 (R/W) Channel Primary-Alterante Set Register */ __O uint32_t CHNL_PRI_ALT_CLR; /* Offset: 0x034 ( /W) Channel Primary-Alterante Clear Register */
__O uint32_t CHNL_PRI_ALT_CLR; /* Offset: 0x034 ( /W) Channel Primary-Alterante Clear Register */ __IO uint32_t CHNL_PRIORITY_SET; /* Offset: 0x038 (R/W) Channel Priority Set Register */
__IO uint32_t CHNL_PRIORITY_SET; /* Offset: 0x038 (R/W) Channel Priority Set Register */ __O uint32_t CHNL_PRIORITY_CLR; /* Offset: 0x03C ( /W) Channel Priority Clear Register */
__O uint32_t CHNL_PRIORITY_CLR; /* Offset: 0x03C ( /W) Channel Priority Clear Register */ uint32_t RESERVED0[3];
uint32_t RESERVED0[3]; __IO uint32_t ERR_CLR; /* Offset: 0x04C Bus Error Clear Register (R/W) */
__IO uint32_t ERR_CLR; /* Offset: 0x04C Bus Error Clear Register (R/W) */
} CMSDK_PL230_TypeDef; } CMSDK_PL230_TypeDef;
@ -593,21 +585,20 @@ typedef struct
/*------------------- Watchdog ----------------------------------------------*/ /*------------------- Watchdog ----------------------------------------------*/
typedef struct typedef struct {
{
__IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */ __IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */
__I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */ __I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */
__IO uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */ __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */
__O uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */ __O uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */
__I uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */ __I uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */
__I uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */ __I uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */
uint32_t RESERVED0[762]; uint32_t RESERVED0[762];
__IO uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */ __IO uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */
uint32_t RESERVED1[191]; uint32_t RESERVED1[191];
__IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */ __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */
__O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */ __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */
}CMSDK_WATCHDOG_TypeDef; } CMSDK_WATCHDOG_TypeDef;
#define CMSDK_Watchdog_LOAD_Pos 0 /* CMSDK_Watchdog LOAD: LOAD Position */ #define CMSDK_Watchdog_LOAD_Pos 0 /* CMSDK_Watchdog LOAD: LOAD Position */
#define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /* CMSDK_Watchdog LOAD: LOAD Mask */ #define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /* CMSDK_Watchdog LOAD: LOAD Mask */
@ -643,17 +634,17 @@ typedef struct
/* -------------------- End of section using anonymous unions ------------------- */ /* -------------------- End of section using anonymous unions ------------------- */
#if defined ( __CC_ARM ) #if defined ( __CC_ARM )
#pragma pop #pragma pop
#elif defined(__ICCARM__) #elif defined(__ICCARM__)
/* leave anonymous unions enabled */ /* leave anonymous unions enabled */
#elif defined(__GNUC__) #elif defined(__GNUC__)
/* anonymous unions are enabled by default */ /* anonymous unions are enabled by default */
#elif defined(__TMS470__) #elif defined(__TMS470__)
/* anonymous unions are enabled by default */ /* anonymous unions are enabled by default */
#elif defined(__TASKING__) #elif defined(__TASKING__)
#pragma warning restore #pragma warning restore
#else #else
#warning Not supported compiler type #warning Not supported compiler type
#endif #endif

560
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/SMM_MPS2.h
View File

@ -46,40 +46,39 @@
/* FPGA System Register declaration */ /* FPGA System Register declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct typedef struct {
{ __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections
__IO uint32_t LED; // Offset: 0x000 (R/W) LED connections // [31:2] : Reserved
// [31:2] : Reserved // [1:0] : LEDs
// [1:0] : LEDs uint32_t RESERVED1[1];
uint32_t RESERVED1[1]; __IO uint32_t BUTTON; // Offset: 0x008 (R/W) Buttons
__IO uint32_t BUTTON; // Offset: 0x008 (R/W) Buttons // [31:2] : Reserved
// [31:2] : Reserved // [1:0] : Buttons
// [1:0] : Buttons uint32_t RESERVED2[1];
uint32_t RESERVED2[1]; __IO uint32_t CLK1HZ; // Offset: 0x010 (R/W) 1Hz up counter
__IO uint32_t CLK1HZ; // Offset: 0x010 (R/W) 1Hz up counter __IO uint32_t CLK100HZ; // Offset: 0x014 (R/W) 100Hz up counter
__IO uint32_t CLK100HZ; // Offset: 0x014 (R/W) 100Hz up counter __IO uint32_t COUNTER; // Offset: 0x018 (R/W) Cycle Up Counter
__IO uint32_t COUNTER; // Offset: 0x018 (R/W) Cycle Up Counter // Increments when 32-bit prescale counter reach zero
// Increments when 32-bit prescale counter reach zero uint32_t RESERVED3[1];
uint32_t RESERVED3[1]; __IO uint32_t PRESCALE; // Offset: 0x020 (R/W) Prescaler
__IO uint32_t PRESCALE; // Offset: 0x020 (R/W) Prescaler // Bit[31:0] : reload value for prescale counter
// Bit[31:0] : reload value for prescale counter __IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter
__IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter // current value of the pre-scaler counter
// current value of the pre-scaler counter // The Cycle Up Counter increment when the prescale down counter reach 0
// The Cycle Up Counter increment when the prescale down counter reach 0 // The pre-scaler counter is reloaded with PRESCALE after reaching 0.
// The pre-scaler counter is reloaded with PRESCALE after reaching 0. uint32_t RESERVED4[9];
uint32_t RESERVED4[9]; __IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */
__IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */ // [31:10] : Reserved
// [31:10] : Reserved // [9] : SHIELD_1_SPI_nCS
// [9] : SHIELD_1_SPI_nCS // [8] : SHIELD_0_SPI_nCS
// [8] : SHIELD_0_SPI_nCS // [7] : ADC_SPI_nCS
// [7] : ADC_SPI_nCS // [6] : CLCD_BL_CTRL
// [6] : CLCD_BL_CTRL // [5] : CLCD_RD
// [5] : CLCD_RD // [4] : CLCD_RS
// [4] : CLCD_RS // [3] : CLCD_RESET
// [3] : CLCD_RESET // [2] : RESERVED
// [2] : RESERVED // [1] : SPI_nSS
// [1] : SPI_nSS // [0] : CLCD_CS
// [0] : CLCD_CS
} MPS2_FPGAIO_TypeDef; } MPS2_FPGAIO_TypeDef;
// MISC register bit definitions // MISC register bit definitions
@ -107,58 +106,57 @@ typedef struct
/* SCC Register declaration */ /* SCC Register declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct // typedef struct { //
{ __IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT
__IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT // [31:1] : Reserved
// [31:1] : Reserved // [0] 1 : REMAP BlockRam to ZBT
// [0] 1 : REMAP BlockRam to ZBT __IO uint32_t LEDS; // Offset: 0x004 (R/W) Controls the MCC user LEDs
__IO uint32_t LEDS; // Offset: 0x004 (R/W) Controls the MCC user LEDs // [31:8] : Reserved
// [31:8] : Reserved // [7:0] : MCC LEDs
// [7:0] : MCC LEDs uint32_t RESERVED0[1];
uint32_t RESERVED0[1]; __I uint32_t SWITCHES; // Offset: 0x00C (R/ ) Denotes the state of the MCC user switches
__I uint32_t SWITCHES; // Offset: 0x00C (R/ ) Denotes the state of the MCC user switches // [31:8] : Reserved
// [31:8] : Reserved // [7:0] : These bits indicate state of the MCC switches
// [7:0] : These bits indicate state of the MCC switches __I uint32_t CFG_REG4; // Offset: 0x010 (R/ ) Denotes the board revision
__I uint32_t CFG_REG4; // Offset: 0x010 (R/ ) Denotes the board revision // [31:4] : Reserved
// [31:4] : Reserved // [3:0] : Used by the MCC to pass PCB revision. 0 = A 1 = B
// [3:0] : Used by the MCC to pass PCB revision. 0 = A 1 = B uint32_t RESERVED1[35];
uint32_t RESERVED1[35]; __IO uint32_t SYS_CFGDATA_RTN; // Offset: 0x0A0 (R/W) User data register
__IO uint32_t SYS_CFGDATA_RTN; // Offset: 0x0A0 (R/W) User data register // [31:0] : Data
// [31:0] : Data __IO uint32_t SYS_CFGDATA_OUT; // Offset: 0x0A4 (R/W) User data register
__IO uint32_t SYS_CFGDATA_OUT; // Offset: 0x0A4 (R/W) User data register // [31:0] : Data
// [31:0] : Data __IO uint32_t SYS_CFGCTRL; // Offset: 0x0A8 (R/W) Control register
__IO uint32_t SYS_CFGCTRL; // Offset: 0x0A8 (R/W) Control register // [31] : Start (generates interrupt on write to this bit)
// [31] : Start (generates interrupt on write to this bit) // [30] : R/W access
// [30] : R/W access // [29:26] : Reserved
// [29:26] : Reserved // [25:20] : Function value
// [25:20] : Function value // [19:12] : Reserved
// [19:12] : Reserved // [11:0] : Device (value of 0/1/2 for supported clocks)
// [11:0] : Device (value of 0/1/2 for supported clocks) __IO uint32_t SYS_CFGSTAT; // Offset: 0x0AC (R/W) Contains status information
__IO uint32_t SYS_CFGSTAT; // Offset: 0x0AC (R/W) Contains status information // [31:2] : Reserved
// [31:2] : Reserved // [1] : Error
// [1] : Error // [0] : Complete
// [0] : Complete __IO uint32_t RESERVED2[20];
__IO uint32_t RESERVED2[20]; __IO uint32_t SCC_DLL; // Offset: 0x100 (R/W) DLL Lock Register
__IO uint32_t SCC_DLL; // Offset: 0x100 (R/W) DLL Lock Register // [31:24] : DLL LOCK MASK[7:0] - Indicate if the DLL locked is masked
// [31:24] : DLL LOCK MASK[7:0] - Indicate if the DLL locked is masked // [23:16] : DLL LOCK MASK[7:0] - Indicate if the DLLs are locked or unlocked
// [23:16] : DLL LOCK MASK[7:0] - Indicate if the DLLs are locked or unlocked // [15:1] : Reserved
// [15:1] : Reserved // [0] : This bit indicates if all enabled DLLs are locked
// [0] : This bit indicates if all enabled DLLs are locked uint32_t RESERVED3[957];
uint32_t RESERVED3[957]; __I uint32_t SCC_AID; // Offset: 0xFF8 (R/ ) SCC AID Register
__I uint32_t SCC_AID; // Offset: 0xFF8 (R/ ) SCC AID Register // [31:24] : FPGA build number
// [31:24] : FPGA build number // [23:20] : V2M-MPS2 target board revision (A = 0, B = 1)
// [23:20] : V2M-MPS2 target board revision (A = 0, B = 1) // [19:11] : Reserved
// [19:11] : Reserved // [10] : if “1” SCC_SW register has been implemented
// [10] : if “1” SCC_SW register has been implemented // [9] : if “1” SCC_LED register has been implemented
// [9] : if “1” SCC_LED register has been implemented // [8] : if “1” DLL lock register has been implemented
// [8] : if “1” DLL lock register has been implemented // [7:0] : number of SCC configuration register
// [7:0] : number of SCC configuration register __I uint32_t SCC_ID; // Offset: 0xFFC (R/ ) Contains information about the FPGA image
__I uint32_t SCC_ID; // Offset: 0xFFC (R/ ) Contains information about the FPGA image // [31:24] : Implementer ID: 0x41 = ARM
// [31:24] : Implementer ID: 0x41 = ARM // [23:20] : Application note IP variant number
// [23:20] : Application note IP variant number // [19:16] : IP Architecture: 0x4 =AHB
// [19:16] : IP Architecture: 0x4 =AHB // [15:4] : Primary part number: 386 = AN386
// [15:4] : Primary part number: 386 = AN386 // [3:0] : Application note IP revision number
// [3:0] : Application note IP revision number
} MPS2_SCC_TypeDef; } MPS2_SCC_TypeDef;
@ -166,60 +164,59 @@ typedef struct //
/* SSP Peripheral declaration */ /* SSP Peripheral declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf typedef struct { // Document DDI0194G_ssp_pl022_r1p3_trm.pdf
{ __IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0
__IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0 // [31:16] : Reserved
// [31:16] : Reserved // [15:8] : Serial clock rate
// [15:8] : Serial clock rate // [7] : SSPCLKOUT phase, applicable to Motorola SPI frame format only
// [7] : SSPCLKOUT phase, applicable to Motorola SPI frame format only // [6] : SSPCLKOUT polarity, applicable to Motorola SPI frame format only
// [6] : SSPCLKOUT polarity, applicable to Motorola SPI frame format only // [5:4] : Frame format
// [5:4] : Frame format // [3:0] : Data Size Select
// [3:0] : Data Size Select __IO uint32_t CR1; // Offset: 0x004 (R/W) Control register 1
__IO uint32_t CR1; // Offset: 0x004 (R/W) Control register 1 // [31:4] : Reserved
// [31:4] : Reserved // [3] : Slave-mode output disable
// [3] : Slave-mode output disable // [2] : Master or slave mode select
// [2] : Master or slave mode select // [1] : Synchronous serial port enable
// [1] : Synchronous serial port enable // [0] : Loop back mode
// [0] : Loop back mode __IO uint32_t DR; // Offset: 0x008 (R/W) Data register
__IO uint32_t DR; // Offset: 0x008 (R/W) Data register // [31:16] : Reserved
// [31:16] : Reserved // [15:0] : Transmit/Receive FIFO
// [15:0] : Transmit/Receive FIFO __I uint32_t SR; // Offset: 0x00C (R/ ) Status register
__I uint32_t SR; // Offset: 0x00C (R/ ) Status register // [31:5] : Reserved
// [31:5] : Reserved // [4] : PrimeCell SSP busy flag
// [4] : PrimeCell SSP busy flag // [3] : Receive FIFO full
// [3] : Receive FIFO full // [2] : Receive FIFO not empty
// [2] : Receive FIFO not empty // [1] : Transmit FIFO not full
// [1] : Transmit FIFO not full // [0] : Transmit FIFO empty
// [0] : Transmit FIFO empty __IO uint32_t CPSR; // Offset: 0x010 (R/W) Clock prescale register
__IO uint32_t CPSR; // Offset: 0x010 (R/W) Clock prescale register // [31:8] : Reserved
// [31:8] : Reserved // [8:0] : Clock prescale divisor
// [8:0] : Clock prescale divisor __IO uint32_t IMSC; // Offset: 0x014 (R/W) Interrupt mask set or clear register
__IO uint32_t IMSC; // Offset: 0x014 (R/W) Interrupt mask set or clear register // [31:4] : Reserved
// [31:4] : Reserved // [3] : Transmit FIFO interrupt mask
// [3] : Transmit FIFO interrupt mask // [2] : Receive FIFO interrupt mask
// [2] : Receive FIFO interrupt mask // [1] : Receive timeout interrupt mask
// [1] : Receive timeout interrupt mask // [0] : Receive overrun interrupt mask
// [0] : Receive overrun interrupt mask __I uint32_t RIS; // Offset: 0x018 (R/ ) Raw interrupt status register
__I uint32_t RIS; // Offset: 0x018 (R/ ) Raw interrupt status register // [31:4] : Reserved
// [31:4] : Reserved // [3] : raw interrupt state, prior to masking, of the SSPTXINTR interrupt
// [3] : raw interrupt state, prior to masking, of the SSPTXINTR interrupt // [2] : raw interrupt state, prior to masking, of the SSPRXINTR interrupt
// [2] : raw interrupt state, prior to masking, of the SSPRXINTR interrupt // [1] : raw interrupt state, prior to masking, of the SSPRTINTR interrupt
// [1] : raw interrupt state, prior to masking, of the SSPRTINTR interrupt // [0] : raw interrupt state, prior to masking, of the SSPRORINTR interrupt
// [0] : raw interrupt state, prior to masking, of the SSPRORINTR interrupt __I uint32_t MIS; // Offset: 0x01C (R/ ) Masked interrupt status register
__I uint32_t MIS; // Offset: 0x01C (R/ ) Masked interrupt status register // [31:4] : Reserved
// [31:4] : Reserved // [3] : transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt
// [3] : transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt // [2] : receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt
// [2] : receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt // [1] : receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt
// [1] : receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt // [0] : receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt
// [0] : receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt __O uint32_t ICR; // Offset: 0x020 ( /W) Interrupt clear register
__O uint32_t ICR; // Offset: 0x020 ( /W) Interrupt clear register // [31:2] : Reserved
// [31:2] : Reserved // [1] : Clears the SSPRTINTR interrupt
// [1] : Clears the SSPRTINTR interrupt // [0] : Clears the SSPRORINTR interrupt
// [0] : Clears the SSPRORINTR interrupt __IO uint32_t DMACR; // Offset: 0x024 (R/W) DMA control register
__IO uint32_t DMACR; // Offset: 0x024 (R/W) DMA control register // [31:2] : Reserved
// [31:2] : Reserved // [1] : Transmit DMA Enable
// [1] : Transmit DMA Enable // [0] : Receive DMA Enable
// [0] : Receive DMA Enable
} MPS2_SSP_TypeDef; } MPS2_SSP_TypeDef;
@ -314,13 +311,12 @@ typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf
/* Audio and Touch Screen (I2C) Peripheral declaration */ /* Audio and Touch Screen (I2C) Peripheral declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct typedef struct {
{ union {
union { __O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W)
__O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W) __I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ )
__I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ ) };
}; __O uint32_t CONTROLC; // Offset: 0x004 CONTROL Clear Register ( /W)
__O uint32_t CONTROLC; // Offset: 0x004 CONTROL Clear Register ( /W)
} MPS2_I2C_TypeDef; } MPS2_I2C_TypeDef;
#define SDA 1 << 1 #define SDA 1 << 1
@ -331,107 +327,106 @@ typedef struct
/* Audio I2S Peripheral declaration */ /* Audio I2S Peripheral declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct typedef struct {
{ /*!< Offset: 0x000 CONTROL Register (R/W) */
/*!< Offset: 0x000 CONTROL Register (R/W) */ __IO uint32_t CONTROL; // <h> CONTROL </h>
__IO uint32_t CONTROL; // <h> CONTROL </h> // <o.0> TX Enable
// <o.0> TX Enable // <0=> TX disabled
// <0=> TX disabled // <1=> TX enabled
// <1=> TX enabled // <o.1> TX IRQ Enable
// <o.1> TX IRQ Enable // <0=> TX IRQ disabled
// <0=> TX IRQ disabled // <1=> TX IRQ enabled
// <1=> TX IRQ enabled // <o.2> RX Enable
// <o.2> RX Enable // <0=> RX disabled
// <0=> RX disabled // <1=> RX enabled
// <1=> RX enabled // <o.3> RX IRQ Enable
// <o.3> RX IRQ Enable // <0=> RX IRQ disabled
// <0=> RX IRQ disabled // <1=> RX IRQ enabled
// <1=> RX IRQ enabled // <o.10..8> TX Buffer Water Level
// <o.10..8> TX Buffer Water Level // <0=> / IRQ triggers when any space available
// <0=> / IRQ triggers when any space available // <1=> / IRQ triggers when more than 1 space available
// <1=> / IRQ triggers when more than 1 space available // <2=> / IRQ triggers when more than 2 space available
// <2=> / IRQ triggers when more than 2 space available // <3=> / IRQ triggers when more than 3 space available
// <3=> / IRQ triggers when more than 3 space available // <4=> Undefined!
// <4=> Undefined! // <5=> Undefined!
// <5=> Undefined! // <6=> Undefined!
// <6=> Undefined! // <7=> Undefined!
// <7=> Undefined! // <o.14..12> RX Buffer Water Level
// <o.14..12> RX Buffer Water Level // <0=> Undefined!
// <0=> Undefined! // <1=> / IRQ triggers when less than 1 space available
// <1=> / IRQ triggers when less than 1 space available // <2=> / IRQ triggers when less than 2 space available
// <2=> / IRQ triggers when less than 2 space available // <3=> / IRQ triggers when less than 3 space available
// <3=> / IRQ triggers when less than 3 space available // <4=> / IRQ triggers when less than 4 space available
// <4=> / IRQ triggers when less than 4 space available // <5=> Undefined!
// <5=> Undefined! // <6=> Undefined!
// <6=> Undefined! // <7=> Undefined!
// <7=> Undefined! // <o.16> FIFO reset
// <o.16> FIFO reset // <0=> Normal operation
// <0=> Normal operation // <1=> FIFO reset
// <1=> FIFO reset // <o.17> Audio Codec reset
// <o.17> Audio Codec reset // <0=> Normal operation
// <0=> Normal operation // <1=> Assert audio Codec reset
// <1=> Assert audio Codec reset /*!< Offset: 0x004 STATUS Register (R/ ) */
/*!< Offset: 0x004 STATUS Register (R/ ) */ __I uint32_t STATUS; // <h> STATUS </h>
__I uint32_t STATUS; // <h> STATUS </h> // <o.0> TX Buffer alert
// <o.0> TX Buffer alert // <0=> TX buffer don't need service yet
// <0=> TX buffer don't need service yet // <1=> TX buffer need service
// <1=> TX buffer need service // <o.1> RX Buffer alert
// <o.1> RX Buffer alert // <0=> RX buffer don't need service yet
// <0=> RX buffer don't need service yet // <1=> RX buffer need service
// <1=> RX buffer need service // <o.2> TX Buffer Empty
// <o.2> TX Buffer Empty // <0=> TX buffer have data
// <0=> TX buffer have data // <1=> TX buffer empty
// <1=> TX buffer empty // <o.3> TX Buffer Full
// <o.3> TX Buffer Full // <0=> TX buffer not full
// <0=> TX buffer not full // <1=> TX buffer full
// <1=> TX buffer full // <o.4> RX Buffer Empty
// <o.4> RX Buffer Empty // <0=> RX buffer have data
// <0=> RX buffer have data // <1=> RX buffer empty
// <1=> RX buffer empty // <o.5> RX Buffer Full
// <o.5> RX Buffer Full // <0=> RX buffer not full
// <0=> RX buffer not full // <1=> RX buffer full
// <1=> RX buffer full union {
union { /*!< Offset: 0x008 Error Status Register (R/ ) */
/*!< Offset: 0x008 Error Status Register (R/ ) */ __I uint32_t ERROR; // <h> ERROR </h>
__I uint32_t ERROR; // <h> ERROR </h> // <o.0> TX error
// <o.0> TX error // <0=> Okay
// <0=> Okay // <1=> TX overrun/underrun
// <1=> TX overrun/underrun // <o.1> RX error
// <o.1> RX error // <0=> Okay
// <0=> Okay // <1=> RX overrun/underrun
// <1=> RX overrun/underrun /*!< Offset: 0x008 Error Clear Register ( /W) */
/*!< Offset: 0x008 Error Clear Register ( /W) */ __O uint32_t ERRORCLR; // <h> ERRORCLR </h>
__O uint32_t ERRORCLR; // <h> ERRORCLR </h> // <o.0> TX error
// <o.0> TX error // <0=> Okay
// <0=> Okay // <1=> Clear TX error
// <1=> Clear TX error // <o.1> RX error
// <o.1> RX error // <0=> Okay
// <0=> Okay // <1=> Clear RX error
// <1=> Clear RX error
}; };
/*!< Offset: 0x00C Divide ratio Register (R/W) */ /*!< Offset: 0x00C Divide ratio Register (R/W) */
__IO uint32_t DIVIDE; // <h> Divide ratio for Left/Right clock </h> __IO uint32_t DIVIDE; // <h> Divide ratio for Left/Right clock </h>
// <o.9..0> TX error (default 0x80) // <o.9..0> TX error (default 0x80)
/*!< Offset: 0x010 Transmit Buffer ( /W) */ /*!< Offset: 0x010 Transmit Buffer ( /W) */
__O uint32_t TXBUF; // <h> Transmit buffer </h> __O uint32_t TXBUF; // <h> Transmit buffer </h>
// <o.15..0> Right channel // <o.15..0> Right channel
// <o.31..16> Left channel // <o.31..16> Left channel
/*!< Offset: 0x014 Receive Buffer (R/ ) */ /*!< Offset: 0x014 Receive Buffer (R/ ) */
__I uint32_t RXBUF; // <h> Receive buffer </h> __I uint32_t RXBUF; // <h> Receive buffer </h>
// <o.15..0> Right channel // <o.15..0> Right channel
// <o.31..16> Left channel // <o.31..16> Left channel
uint32_t RESERVED1[186]; uint32_t RESERVED1[186];
__IO uint32_t ITCR; // <h> Integration Test Control Register </h> __IO uint32_t ITCR; // <h> Integration Test Control Register </h>
// <o.0> ITEN // <o.0> ITEN
// <0=> Normal operation // <0=> Normal operation
// <1=> Integration Test mode enable // <1=> Integration Test mode enable
__O uint32_t ITIP1; // <h> Integration Test Input Register 1</h> __O uint32_t ITIP1; // <h> Integration Test Input Register 1</h>
// <o.0> SDIN // <o.0> SDIN
__O uint32_t ITOP1; // <h> Integration Test Output Register 1</h> __O uint32_t ITOP1; // <h> Integration Test Output Register 1</h>
// <o.0> SDOUT // <o.0> SDOUT
// <o.1> SCLK // <o.1> SCLK
// <o.2> LRCK // <o.2> LRCK
// <o.3> IRQOUT // <o.3> IRQOUT
} MPS2_I2S_TypeDef; } MPS2_I2S_TypeDef;
#define I2S_CONTROL_TXEN_Pos 0 #define I2S_CONTROL_TXEN_Pos 0
@ -486,44 +481,43 @@ typedef struct
/* SMSC9220 Register Definitions */ /* SMSC9220 Register Definitions */
/******************************************************************************/ /******************************************************************************/
typedef struct // SMSC LAN9220 typedef struct { // SMSC LAN9220
{ __I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0)
__I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0) uint32_t RESERVED1[0x7];
uint32_t RESERVED1[0x7]; __O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20)
__O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20) uint32_t RESERVED2[0x7];
uint32_t RESERVED2[0x7];
__I uint32_t RX_STAT_PORT; // Receive FIFO status port (offset 0x40) __I uint32_t RX_STAT_PORT; // Receive FIFO status port (offset 0x40)
__I uint32_t RX_STAT_PEEK; // Receive FIFO status peek (offset 0x44) __I uint32_t RX_STAT_PEEK; // Receive FIFO status peek (offset 0x44)
__I uint32_t TX_STAT_PORT; // Transmit FIFO status port (offset 0x48) __I uint32_t TX_STAT_PORT; // Transmit FIFO status port (offset 0x48)
__I uint32_t TX_STAT_PEEK; // Transmit FIFO status peek (offset 0x4C) __I uint32_t TX_STAT_PEEK; // Transmit FIFO status peek (offset 0x4C)
__I uint32_t ID_REV; // Chip ID and Revision (offset 0x50) __I uint32_t ID_REV; // Chip ID and Revision (offset 0x50)
__IO uint32_t IRQ_CFG; // Main Interrupt Configuration (offset 0x54) __IO uint32_t IRQ_CFG; // Main Interrupt Configuration (offset 0x54)
__IO uint32_t INT_STS; // Interrupt Status (offset 0x58) __IO uint32_t INT_STS; // Interrupt Status (offset 0x58)
__IO uint32_t INT_EN; // Interrupt Enable Register (offset 0x5C) __IO uint32_t INT_EN; // Interrupt Enable Register (offset 0x5C)
uint32_t RESERVED3; // Reserved for future use (offset 0x60) uint32_t RESERVED3; // Reserved for future use (offset 0x60)
__I uint32_t BYTE_TEST; // Read-only byte order testing register 87654321h (offset 0x64) __I uint32_t BYTE_TEST; // Read-only byte order testing register 87654321h (offset 0x64)
__IO uint32_t FIFO_INT; // FIFO Level Interrupts (offset 0x68) __IO uint32_t FIFO_INT; // FIFO Level Interrupts (offset 0x68)
__IO uint32_t RX_CFG; // Receive Configuration (offset 0x6C) __IO uint32_t RX_CFG; // Receive Configuration (offset 0x6C)
__IO uint32_t TX_CFG; // Transmit Configuration (offset 0x70) __IO uint32_t TX_CFG; // Transmit Configuration (offset 0x70)
__IO uint32_t HW_CFG; // Hardware Configuration (offset 0x74) __IO uint32_t HW_CFG; // Hardware Configuration (offset 0x74)
__IO uint32_t RX_DP_CTL; // RX Datapath Control (offset 0x78) __IO uint32_t RX_DP_CTL; // RX Datapath Control (offset 0x78)
__I uint32_t RX_FIFO_INF; // Receive FIFO Information (offset 0x7C) __I uint32_t RX_FIFO_INF; // Receive FIFO Information (offset 0x7C)
__I uint32_t TX_FIFO_INF; // Transmit FIFO Information (offset 0x80) __I uint32_t TX_FIFO_INF; // Transmit FIFO Information (offset 0x80)
__IO uint32_t PMT_CTRL; // Power Management Control (offset 0x84) __IO uint32_t PMT_CTRL; // Power Management Control (offset 0x84)
__IO uint32_t GPIO_CFG; // General Purpose IO Configuration (offset 0x88) __IO uint32_t GPIO_CFG; // General Purpose IO Configuration (offset 0x88)
__IO uint32_t GPT_CFG; // General Purpose Timer Configuration (offset 0x8C) __IO uint32_t GPT_CFG; // General Purpose Timer Configuration (offset 0x8C)
__I uint32_t GPT_CNT; // General Purpose Timer Count (offset 0x90) __I uint32_t GPT_CNT; // General Purpose Timer Count (offset 0x90)
uint32_t RESERVED4; // Reserved for future use (offset 0x94) uint32_t RESERVED4; // Reserved for future use (offset 0x94)
__IO uint32_t ENDIAN; // WORD SWAP Register (offset 0x98) __IO uint32_t ENDIAN; // WORD SWAP Register (offset 0x98)
__I uint32_t FREE_RUN; // Free Run Counter (offset 0x9C) __I uint32_t FREE_RUN; // Free Run Counter (offset 0x9C)
__I uint32_t RX_DROP; // RX Dropped Frames Counter (offset 0xA0) __I uint32_t RX_DROP; // RX Dropped Frames Counter (offset 0xA0)
__IO uint32_t MAC_CSR_CMD; // MAC CSR Synchronizer Command (offset 0xA4) __IO uint32_t MAC_CSR_CMD; // MAC CSR Synchronizer Command (offset 0xA4)
__IO uint32_t MAC_CSR_DATA; // MAC CSR Synchronizer Data (offset 0xA8) __IO uint32_t MAC_CSR_DATA; // MAC CSR Synchronizer Data (offset 0xA8)
__IO uint32_t AFC_CFG; // Automatic Flow Control Configuration (offset 0xAC) __IO uint32_t AFC_CFG; // Automatic Flow Control Configuration (offset 0xAC)
__IO uint32_t E2P_CMD; // EEPROM Command (offset 0xB0) __IO uint32_t E2P_CMD; // EEPROM Command (offset 0xB0)
__IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4) __IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4)
} SMSC9220_TypeDef; } SMSC9220_TypeDef;

12
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/peripherallink.h
View File

@ -37,17 +37,17 @@
#define __DEVICE_H #define __DEVICE_H
#if defined CMSDK_CM0 #if defined CMSDK_CM0
#include "CMSDK_CM0.h" /* device specific header file */ #include "CMSDK_CM0.h" /* device specific header file */
#elif defined CMSDK_CM0plus #elif defined CMSDK_CM0plus
#include "CMSDK_CM0plus.h" /* device specific header file */ #include "CMSDK_CM0plus.h" /* device specific header file */
#elif defined CMSDK_CM3 #elif defined CMSDK_CM3
#include "CMSDK_CM3.h" /* device specific header file */ #include "CMSDK_CM3.h" /* device specific header file */
#elif defined CMSDK_CM4 #elif defined CMSDK_CM4
#include "CMSDK_CM4.h" /* device specific header file */ #include "CMSDK_CM4.h" /* device specific header file */
#elif defined CMSDK_CM7 #elif defined CMSDK_CM7
#include "CMSDK_CM7.h" /* device specific header file */ #include "CMSDK_CM7.h" /* device specific header file */
#else #else
#warning "no appropriate header file found!" #warning "no appropriate header file found!"
#endif #endif
#endif /* __DEVICE_H */ #endif /* __DEVICE_H */

10
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/system_CMSDK_CM3.c
View File

@ -65,10 +65,10 @@ uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Cloc
* @brief Updates the SystemCoreClock with current core Clock * @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers. * retrieved from cpu registers.
*/ */
void SystemCoreClockUpdate (void) void SystemCoreClockUpdate(void)
{ {
SystemCoreClock = __SYSTEM_CLOCK; SystemCoreClock = __SYSTEM_CLOCK;
} }
@ -81,13 +81,13 @@ void SystemCoreClockUpdate (void)
* @brief Setup the microcontroller system. * @brief Setup the microcontroller system.
* Initialize the System. * Initialize the System.
*/ */
void SystemInit (void) void SystemInit(void)
{ {
#ifdef UNALIGNED_SUPPORT_DISABLE #ifdef UNALIGNED_SUPPORT_DISABLE
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
#endif #endif
SystemCoreClock = __SYSTEM_CLOCK; SystemCoreClock = __SYSTEM_CLOCK;
} }

4
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/system_CMSDK_CM3.h
View File

@ -56,7 +56,7 @@ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) *
* @brief Setup the microcontroller system. * @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable. * Initialize the System and update the SystemCoreClock variable.
*/ */
extern void SystemInit (void); extern void SystemInit(void);
/** /**
* Update SystemCoreClock variable * Update SystemCoreClock variable
@ -67,7 +67,7 @@ extern void SystemInit (void);
* @brief Updates the SystemCoreClock with current core Clock * @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers. * retrieved from cpu registers.
*/ */
extern void SystemCoreClockUpdate (void); extern void SystemCoreClockUpdate(void);
#ifdef __cplusplus #ifdef __cplusplus
} }

729
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/CMSDK_CM4.h
View File

@ -40,58 +40,57 @@
#define CMSDK_CM4_H #define CMSDK_CM4_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* ------------------------- Interrupt Number Definition ------------------------ */ /* ------------------------- Interrupt Number Definition ------------------------ */
typedef enum IRQn typedef enum IRQn {
{ /* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
/* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */ NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ HardFault_IRQn = -13, /* 3 HardFault Interrupt */
HardFault_IRQn = -13, /* 3 HardFault Interrupt */ MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ SVCall_IRQn = -5, /* 11 SV Call Interrupt */
SVCall_IRQn = -5, /* 11 SV Call Interrupt */ DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ SysTick_IRQn = -1, /* 15 System Tick Interrupt */
SysTick_IRQn = -1, /* 15 System Tick Interrupt */
/****** CMSDK Specific Interrupt Numbers *********************************************************/ /****** CMSDK Specific Interrupt Numbers *********************************************************/
UARTRX0_IRQn = 0, /*!< UART 0 RX Interrupt */ UARTRX0_IRQn = 0, /*!< UART 0 RX Interrupt */
UARTTX0_IRQn = 1, /*!< UART 0 TX Interrupt */ UARTTX0_IRQn = 1, /*!< UART 0 TX Interrupt */
UARTRX1_IRQn = 2, /*!< UART 1 RX Interrupt */ UARTRX1_IRQn = 2, /*!< UART 1 RX Interrupt */
UARTTX1_IRQn = 3, /*!< UART 1 TX Interrupt */ UARTTX1_IRQn = 3, /*!< UART 1 TX Interrupt */
UARTRX2_IRQn = 4, /*!< UART 2 RX Interrupt */ UARTRX2_IRQn = 4, /*!< UART 2 RX Interrupt */
UARTTX2_IRQn = 5, /*!< UART 2 TX Interrupt */ UARTTX2_IRQn = 5, /*!< UART 2 TX Interrupt */
PORT0_ALL_IRQn = 6, /*!< Port 0 combined Interrupt */ PORT0_ALL_IRQn = 6, /*!< Port 0 combined Interrupt */
PORT1_ALL_IRQn = 7, /*!< Port 1 combined Interrupt */ PORT1_ALL_IRQn = 7, /*!< Port 1 combined Interrupt */
TIMER0_IRQn = 8, /*!< TIMER 0 Interrupt */ TIMER0_IRQn = 8, /*!< TIMER 0 Interrupt */
TIMER1_IRQn = 9, /*!< TIMER 1 Interrupt */ TIMER1_IRQn = 9, /*!< TIMER 1 Interrupt */
DUALTIMER_IRQn = 10, /*!< Dual Timer Interrupt */ DUALTIMER_IRQn = 10, /*!< Dual Timer Interrupt */
SPI_IRQn = 11, /*!< SPI Interrupt */ SPI_IRQn = 11, /*!< SPI Interrupt */
UARTOVF_IRQn = 12, /*!< UART 0,1,2 Overflow Interrupt */ UARTOVF_IRQn = 12, /*!< UART 0,1,2 Overflow Interrupt */
ETHERNET_IRQn = 13, /*!< Ethernet Interrupt */ ETHERNET_IRQn = 13, /*!< Ethernet Interrupt */
I2S_IRQn = 14, /*!< I2S Interrupt */ I2S_IRQn = 14, /*!< I2S Interrupt */
TSC_IRQn = 15, /*!< Touch Screen Interrupt */ TSC_IRQn = 15, /*!< Touch Screen Interrupt */
PORT2_ALL_IRQn = 16, /*!< Port 2 combined Interrupt */ PORT2_ALL_IRQn = 16, /*!< Port 2 combined Interrupt */
PORT3_ALL_IRQn = 17, /*!< Port 3 combined Interrupt */ PORT3_ALL_IRQn = 17, /*!< Port 3 combined Interrupt */
UARTRX3_IRQn = 18, /*!< UART 3 RX Interrupt */ UARTRX3_IRQn = 18, /*!< UART 3 RX Interrupt */
UARTTX3_IRQn = 19, /*!< UART 3 TX Interrupt */ UARTTX3_IRQn = 19, /*!< UART 3 TX Interrupt */
UARTRX4_IRQn = 20, /*!< UART 4 RX Interrupt */ UARTRX4_IRQn = 20, /*!< UART 4 RX Interrupt */
UARTTX4_IRQn = 21, /*!< UART 4 TX Interrupt */ UARTTX4_IRQn = 21, /*!< UART 4 TX Interrupt */
ADCSPI_IRQn = 22, /*!< SHIELD ADC SPI Interrupt */ ADCSPI_IRQn = 22, /*!< SHIELD ADC SPI Interrupt */
SHIELDSPI_IRQn = 23, /*!< SHIELD SPI Combined Interrupt */ SHIELDSPI_IRQn = 23, /*!< SHIELD SPI Combined Interrupt */
PORT0_0_IRQn = 24, /*!< GPIO Port 0 pin 0 Interrupt */ PORT0_0_IRQn = 24, /*!< GPIO Port 0 pin 0 Interrupt */
PORT0_1_IRQn = 25, /*!< GPIO Port 0 pin 1 Interrupt */ PORT0_1_IRQn = 25, /*!< GPIO Port 0 pin 1 Interrupt */
PORT0_2_IRQn = 26, /*!< GPIO Port 0 pin 2 Interrupt */ PORT0_2_IRQn = 26, /*!< GPIO Port 0 pin 2 Interrupt */
PORT0_3_IRQn = 27, /*!< GPIO Port 0 pin 3 Interrupt */ PORT0_3_IRQn = 27, /*!< GPIO Port 0 pin 3 Interrupt */
PORT0_4_IRQn = 28, /*!< GPIO Port 0 pin 4 Interrupt */ PORT0_4_IRQn = 28, /*!< GPIO Port 0 pin 4 Interrupt */
PORT0_5_IRQn = 29, /*!< GPIO Port 0 pin 5 Interrupt */ PORT0_5_IRQn = 29, /*!< GPIO Port 0 pin 5 Interrupt */
PORT0_6_IRQn = 30, /*!< GPIO Port 0 pin 6 Interrupt */ PORT0_6_IRQn = 30, /*!< GPIO Port 0 pin 6 Interrupt */
PORT0_7_IRQn = 31, /*!< GPIO Port 0 pin 7 Interrupt */ PORT0_7_IRQn = 31, /*!< GPIO Port 0 pin 7 Interrupt */
} IRQn_Type; } IRQn_Type;
@ -132,16 +131,15 @@ typedef enum IRQn
memory mapped structure for CMSDK_UART memory mapped structure for CMSDK_UART
@{ @{
*/ */
typedef struct typedef struct {
{ __IO uint32_t DATA; /*!< Offset: 0x000 Data Register (R/W) */
__IO uint32_t DATA; /*!< Offset: 0x000 Data Register (R/W) */ __IO uint32_t STATE; /*!< Offset: 0x004 Status Register (R/W) */
__IO uint32_t STATE; /*!< Offset: 0x004 Status Register (R/W) */ __IO uint32_t CTRL; /*!< Offset: 0x008 Control Register (R/W) */
__IO uint32_t CTRL; /*!< Offset: 0x008 Control Register (R/W) */ union {
union { __I uint32_t INTSTATUS; /*!< Offset: 0x00C Interrupt Status Register (R/ ) */
__I uint32_t INTSTATUS; /*!< Offset: 0x00C Interrupt Status Register (R/ ) */ __O uint32_t INTCLEAR; /*!< Offset: 0x00C Interrupt Clear Register ( /W) */
__O uint32_t INTCLEAR; /*!< Offset: 0x00C Interrupt Clear Register ( /W) */
}; };
__IO uint32_t BAUDDIV; /*!< Offset: 0x010 Baudrate Divider Register (R/W) */ __IO uint32_t BAUDDIV; /*!< Offset: 0x010 Baudrate Divider Register (R/W) */
} CMSDK_UART_TypeDef; } CMSDK_UART_TypeDef;
@ -205,14 +203,13 @@ typedef struct
/** @addtogroup CMSDK_TIMER CMSDK Timer /** @addtogroup CMSDK_TIMER CMSDK Timer
@{ @{
*/ */
typedef struct typedef struct {
{ __IO uint32_t CTRL; /*!< Offset: 0x000 Control Register (R/W) */
__IO uint32_t CTRL; /*!< Offset: 0x000 Control Register (R/W) */ __IO uint32_t VALUE; /*!< Offset: 0x004 Current Value Register (R/W) */
__IO uint32_t VALUE; /*!< Offset: 0x004 Current Value Register (R/W) */ __IO uint32_t RELOAD; /*!< Offset: 0x008 Reload Value Register (R/W) */
__IO uint32_t RELOAD; /*!< Offset: 0x008 Reload Value Register (R/W) */ union {
union { __I uint32_t INTSTATUS; /*!< Offset: 0x00C Interrupt Status Register (R/ ) */
__I uint32_t INTSTATUS; /*!< Offset: 0x00C Interrupt Status Register (R/ ) */ __O uint32_t INTCLEAR; /*!< Offset: 0x00C Interrupt Clear Register ( /W) */
__O uint32_t INTCLEAR; /*!< Offset: 0x00C Interrupt Clear Register ( /W) */
}; };
} CMSDK_TIMER_TypeDef; } CMSDK_TIMER_TypeDef;
@ -253,60 +250,59 @@ typedef struct
@{ @{
*/ */
typedef struct typedef struct {
{ __IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
__IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */ __I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
__I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */ __IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
__IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */ /* <o.7> TimerEn: Timer Enable */
/* <o.7> TimerEn: Timer Enable */ /* <o.6> TimerMode: Timer Mode */
/* <o.6> TimerMode: Timer Mode */ /* <0=> Freerunning-mode */
/* <0=> Freerunning-mode */ /* <1=> Periodic mode */
/* <1=> Periodic mode */ /* <o.5> IntEnable: Interrupt Enable */
/* <o.5> IntEnable: Interrupt Enable */ /* <o.2..3> TimerPre: Timer Prescale */
/* <o.2..3> TimerPre: Timer Prescale */ /* <0=> / 1 */
/* <0=> / 1 */ /* <1=> / 16 */
/* <1=> / 16 */ /* <2=> / 256 */
/* <2=> / 256 */ /* <3=> Undefined! */
/* <3=> Undefined! */ /* <o.1> TimerSize: Timer Size */
/* <o.1> TimerSize: Timer Size */ /* <0=> 16-bit counter */
/* <0=> 16-bit counter */ /* <1=> 32-bit counter */
/* <1=> 32-bit counter */ /* <o.0> OneShot: One-shoot mode */
/* <o.0> OneShot: One-shoot mode */ /* <0=> Wrapping mode */
/* <0=> Wrapping mode */ /* <1=> One-shot mode */
/* <1=> One-shot mode */ /* </h> */
/* </h> */ __O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
__O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */ __I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
__I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */ __I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
__I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */ __IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */
__IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */ uint32_t RESERVED0;
uint32_t RESERVED0; __IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */
__IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */ __I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
__I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */ __IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */
__IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */ /* <o.7> TimerEn: Timer Enable */
/* <o.7> TimerEn: Timer Enable */ /* <o.6> TimerMode: Timer Mode */
/* <o.6> TimerMode: Timer Mode */ /* <0=> Freerunning-mode */
/* <0=> Freerunning-mode */ /* <1=> Periodic mode */
/* <1=> Periodic mode */ /* <o.5> IntEnable: Interrupt Enable */
/* <o.5> IntEnable: Interrupt Enable */ /* <o.2..3> TimerPre: Timer Prescale */
/* <o.2..3> TimerPre: Timer Prescale */ /* <0=> / 1 */
/* <0=> / 1 */ /* <1=> / 16 */
/* <1=> / 16 */ /* <2=> / 256 */
/* <2=> / 256 */ /* <3=> Undefined! */
/* <3=> Undefined! */ /* <o.1> TimerSize: Timer Size */
/* <o.1> TimerSize: Timer Size */ /* <0=> 16-bit counter */
/* <0=> 16-bit counter */ /* <1=> 32-bit counter */
/* <1=> 32-bit counter */ /* <o.0> OneShot: One-shoot mode */
/* <o.0> OneShot: One-shoot mode */ /* <0=> Wrapping mode */
/* <0=> Wrapping mode */ /* <1=> One-shot mode */
/* <1=> One-shot mode */ /* </h> */
/* </h> */ __O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
__O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */ __I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
__I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */ __I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
__I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */ __IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */
__IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */ uint32_t RESERVED1[945];
uint32_t RESERVED1[945]; __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Integration Test Control Register */
__IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Integration Test Control Register */ __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Integration Test Output Set Register */
__O uint32_t ITOP; /* Offset: 0xF04 ( /W) Integration Test Output Set Register */
} CMSDK_DUALTIMER_BOTH_TypeDef; } CMSDK_DUALTIMER_BOTH_TypeDef;
#define CMSDK_DUALTIMER1_LOAD_Pos 0 /*!< CMSDK_DUALTIMER1 LOAD: LOAD Position */ #define CMSDK_DUALTIMER1_LOAD_Pos 0 /*!< CMSDK_DUALTIMER1 LOAD: LOAD Position */
@ -381,32 +377,31 @@ typedef struct
#define CMSDK_DUALTIMER2_BGLOAD_Pos 0 /*!< CMSDK_DUALTIMER2 BGLOAD: Background Load Position */ #define CMSDK_DUALTIMER2_BGLOAD_Pos 0 /*!< CMSDK_DUALTIMER2 BGLOAD: Background Load Position */
#define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /*!< CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */ #define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /*!< CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */
typedef struct typedef struct {
{ __IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */
__IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */ __I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */
__I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */ __IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */
__IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */ /* <o.7> TimerEn: Timer Enable */
/* <o.7> TimerEn: Timer Enable */ /* <o.6> TimerMode: Timer Mode */
/* <o.6> TimerMode: Timer Mode */ /* <0=> Freerunning-mode */
/* <0=> Freerunning-mode */ /* <1=> Periodic mode */
/* <1=> Periodic mode */ /* <o.5> IntEnable: Interrupt Enable */
/* <o.5> IntEnable: Interrupt Enable */ /* <o.2..3> TimerPre: Timer Prescale */
/* <o.2..3> TimerPre: Timer Prescale */ /* <0=> / 1 */
/* <0=> / 1 */ /* <1=> / 16 */
/* <1=> / 16 */ /* <2=> / 256 */
/* <2=> / 256 */ /* <3=> Undefined! */
/* <3=> Undefined! */ /* <o.1> TimerSize: Timer Size */
/* <o.1> TimerSize: Timer Size */ /* <0=> 16-bit counter */
/* <0=> 16-bit counter */ /* <1=> 32-bit counter */
/* <1=> 32-bit counter */ /* <o.0> OneShot: One-shoot mode */
/* <o.0> OneShot: One-shoot mode */ /* <0=> Wrapping mode */
/* <0=> Wrapping mode */ /* <1=> One-shot mode */
/* <1=> One-shot mode */ /* </h> */
/* </h> */ __O uint32_t TimerIntClr; /* Offset: 0x000 (R/W) Timer Interrupt Clear */
__O uint32_t TimerIntClr; /* Offset: 0x000 (R/W) Timer Interrupt Clear */ __I uint32_t TimerRIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */
__I uint32_t TimerRIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */ __I uint32_t TimerMIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */
__I uint32_t TimerMIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */ __IO uint32_t TimerBGLoad; /* Offset: 0x000 (R/W) Background Load Register */
__IO uint32_t TimerBGLoad; /* Offset: 0x000 (R/W) Background Load Register */
} CMSDK_DUALTIMER_SINGLE_TypeDef; } CMSDK_DUALTIMER_SINGLE_TypeDef;
#define CMSDK_DUALTIMER_LOAD_Pos 0 /*!< CMSDK_DUALTIMER LOAD: LOAD Position */ #define CMSDK_DUALTIMER_LOAD_Pos 0 /*!< CMSDK_DUALTIMER LOAD: LOAD Position */
@ -452,28 +447,27 @@ typedef struct
/** @addtogroup CMSDK_GPIO CMSDK GPIO /** @addtogroup CMSDK_GPIO CMSDK GPIO
@{ @{
*/ */
typedef struct typedef struct {
{ __IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */
__IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */ __IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */
__IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */ uint32_t RESERVED0[2];
uint32_t RESERVED0[2]; __IO uint32_t OUTENABLESET; /* Offset: 0x010 (R/W) Output Enable Set Register */
__IO uint32_t OUTENABLESET; /* Offset: 0x010 (R/W) Output Enable Set Register */ __IO uint32_t OUTENABLECLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */
__IO uint32_t OUTENABLECLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */ __IO uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */
__IO uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */ __IO uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */
__IO uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */ __IO uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */
__IO uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */ __IO uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */
__IO uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */ __IO uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */
__IO uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */ __IO uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */
__IO uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */ __IO uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */
__IO uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */ __IO uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */
__IO uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */ union {
union { __I uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */
__I uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */ __O uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */
__O uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */
}; };
uint32_t RESERVED1[241]; uint32_t RESERVED1[241];
__IO uint32_t LB_MASKED[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */ __IO uint32_t LB_MASKED[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */
__IO uint32_t UB_MASKED[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */ __IO uint32_t UB_MASKED[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */
} CMSDK_GPIO_TypeDef; } CMSDK_GPIO_TypeDef;
#define CMSDK_GPIO_DATA_Pos 0 /*!< CMSDK_GPIO DATA: DATA Position */ #define CMSDK_GPIO_DATA_Pos 0 /*!< CMSDK_GPIO DATA: DATA Position */
@ -531,13 +525,12 @@ typedef struct
/** @addtogroup CMSDK_SYSCON CMSDK System Control /** @addtogroup CMSDK_SYSCON CMSDK System Control
@{ @{
*/ */
typedef struct typedef struct {
{ __IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */
__IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */ __IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */
__IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */ __IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */
__IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */ __IO uint32_t EMICTRL; /* Offset: 0x00C (R/W) EMI Control Register */
__IO uint32_t EMICTRL; /* Offset: 0x00C (R/W) EMI Control Register */ __IO uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */
__IO uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */
} CMSDK_SYSCON_TypeDef; } CMSDK_SYSCON_TypeDef;
#define CMSDK_SYSCON_REMAP_Pos 0 #define CMSDK_SYSCON_REMAP_Pos 0
@ -576,26 +569,25 @@ typedef struct
/** @addtogroup CMSDK_PL230 CMSDK uDMA controller /** @addtogroup CMSDK_PL230 CMSDK uDMA controller
@{ @{
*/ */
typedef struct typedef struct {
{ __I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */
__I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */ __O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */
__O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */ __IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */
__IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */ __I uint32_t ALT_CTRL_BASE_PTR; /* Offset: 0x00C (R/ ) Channel Alternate Control Data Base Pointer Register */
__I uint32_t ALT_CTRL_BASE_PTR; /* Offset: 0x00C (R/ ) Channel Alternate Control Data Base Pointer Register */ __I uint32_t DMA_WAITONREQ_STATUS; /* Offset: 0x010 (R/ ) Channel Wait On Request Status Register */
__I uint32_t DMA_WAITONREQ_STATUS; /* Offset: 0x010 (R/ ) Channel Wait On Request Status Register */ __O uint32_t CHNL_SW_REQUEST; /* Offset: 0x014 ( /W) Channel Software Request Register */
__O uint32_t CHNL_SW_REQUEST; /* Offset: 0x014 ( /W) Channel Software Request Register */ __IO uint32_t CHNL_USEBURST_SET; /* Offset: 0x018 (R/W) Channel UseBurst Set Register */
__IO uint32_t CHNL_USEBURST_SET; /* Offset: 0x018 (R/W) Channel UseBurst Set Register */ __O uint32_t CHNL_USEBURST_CLR; /* Offset: 0x01C ( /W) Channel UseBurst Clear Register */
__O uint32_t CHNL_USEBURST_CLR; /* Offset: 0x01C ( /W) Channel UseBurst Clear Register */ __IO uint32_t CHNL_REQ_MASK_SET; /* Offset: 0x020 (R/W) Channel Request Mask Set Register */
__IO uint32_t CHNL_REQ_MASK_SET; /* Offset: 0x020 (R/W) Channel Request Mask Set Register */ __O uint32_t CHNL_REQ_MASK_CLR; /* Offset: 0x024 ( /W) Channel Request Mask Clear Register */
__O uint32_t CHNL_REQ_MASK_CLR; /* Offset: 0x024 ( /W) Channel Request Mask Clear Register */ __IO uint32_t CHNL_ENABLE_SET; /* Offset: 0x028 (R/W) Channel Enable Set Register */
__IO uint32_t CHNL_ENABLE_SET; /* Offset: 0x028 (R/W) Channel Enable Set Register */ __O uint32_t CHNL_ENABLE_CLR; /* Offset: 0x02C ( /W) Channel Enable Clear Register */
__O uint32_t CHNL_ENABLE_CLR; /* Offset: 0x02C ( /W) Channel Enable Clear Register */ __IO uint32_t CHNL_PRI_ALT_SET; /* Offset: 0x030 (R/W) Channel Primary-Alterante Set Register */
__IO uint32_t CHNL_PRI_ALT_SET; /* Offset: 0x030 (R/W) Channel Primary-Alterante Set Register */ __O uint32_t CHNL_PRI_ALT_CLR; /* Offset: 0x034 ( /W) Channel Primary-Alterante Clear Register */
__O uint32_t CHNL_PRI_ALT_CLR; /* Offset: 0x034 ( /W) Channel Primary-Alterante Clear Register */ __IO uint32_t CHNL_PRIORITY_SET; /* Offset: 0x038 (R/W) Channel Priority Set Register */
__IO uint32_t CHNL_PRIORITY_SET; /* Offset: 0x038 (R/W) Channel Priority Set Register */ __O uint32_t CHNL_PRIORITY_CLR; /* Offset: 0x03C ( /W) Channel Priority Clear Register */
__O uint32_t CHNL_PRIORITY_CLR; /* Offset: 0x03C ( /W) Channel Priority Clear Register */ uint32_t RESERVED0[3];
uint32_t RESERVED0[3]; __IO uint32_t ERR_CLR; /* Offset: 0x04C (R/W) Bus Error Clear Register */
__IO uint32_t ERR_CLR; /* Offset: 0x04C (R/W) Bus Error Clear Register */
} CMSDK_PL230_TypeDef; } CMSDK_PL230_TypeDef;
@ -679,155 +671,154 @@ typedef struct
@{ @{
*/ */
typedef struct typedef struct {
{ __IO uint32_t UARTDR; // <h> Data
__IO uint32_t UARTDR; // <h> Data // <o.11> OE: Overrun error <r>
// <o.11> OE: Overrun error <r> // <o.10> BE: Break error <r>
// <o.10> BE: Break error <r> // <o.9> PE: Parity error <r>
// <o.9> PE: Parity error <r> // <o.8> FE: Framing error <r>
// <o.8> FE: Framing error <r> // <o.0..7> DATA: Received or Transmitting data (0..255)
// <o.0..7> DATA: Received or Transmitting data (0..255) // </h>
// </h> union {
union { __I uint32_t UARTRSR; // <h> Receive Status <r>
__I uint32_t UARTRSR; // <h> Receive Status <r> // <o.3> OE: Overrun error <r>
// <o.3> OE: Overrun error <r> // <o.2> BE: Break error <r>
// <o.2> BE: Break error <r> // <o.1> PE: Parity error <r>
// <o.1> PE: Parity error <r> // <o.0> FE: Framing error <r>
// <o.0> FE: Framing error <r> // </h>
// </h> __O uint32_t UARTECR; // <h> Error Clear <w>
__O uint32_t UARTECR; // <h> Error Clear <w> // <o.3> OE: Overrun error <w>
// <o.3> OE: Overrun error <w> // <o.2> BE: Break error <w>
// <o.2> BE: Break error <w> // <o.1> PE: Parity error <w>
// <o.1> PE: Parity error <w> // <o.0> FE: Framing error <w>
// <o.0> FE: Framing error <w> // </h>
// </h> };
}; uint32_t RESERVED0[4];
uint32_t RESERVED0[4]; __IO uint32_t UARTFR; // <h> Flags <r>
__IO uint32_t UARTFR; // <h> Flags <r> // <o.8> RI: Ring indicator <r>
// <o.8> RI: Ring indicator <r> // <o.7> TXFE: Transmit FIFO empty <r>
// <o.7> TXFE: Transmit FIFO empty <r> // <o.6> RXFF: Receive FIFO full <r>
// <o.6> RXFF: Receive FIFO full <r> // <o.5> TXFF: Transmit FIFO full <r>
// <o.5> TXFF: Transmit FIFO full <r> // <o.4> RXFE: Receive FIFO empty <r>
// <o.4> RXFE: Receive FIFO empty <r> // <o.3> BUSY: UART busy <r>
// <o.3> BUSY: UART busy <r> // <o.2> DCD: Data carrier detect <r>
// <o.2> DCD: Data carrier detect <r> // <o.1> DSR: Data set ready <r>
// <o.1> DSR: Data set ready <r> // <o.0> CTS: Clear to send <r>
// <o.0> CTS: Clear to send <r> // </h>
// </h> uint32_t RESERVED1;
uint32_t RESERVED1; __IO uint32_t UARTILPR; // <h> IrDA Low-power Counter
__IO uint32_t UARTILPR; // <h> IrDA Low-power Counter // <o.0..7> ILPDVSR: 8-bit low-power divisor value (0..255)
// <o.0..7> ILPDVSR: 8-bit low-power divisor value (0..255) // </h>
// </h> __IO uint32_t UARTIBRD; // <h> Integer Baud Rate
__IO uint32_t UARTIBRD; // <h> Integer Baud Rate // <o.0..15> BAUD DIVINT: Integer baud rate divisor (0..65535)
// <o.0..15> BAUD DIVINT: Integer baud rate divisor (0..65535) // </h>
// </h> __IO uint32_t UARTFBRD; // <h> Fractional Baud Rate
__IO uint32_t UARTFBRD; // <h> Fractional Baud Rate // <o.0..5> BAUD DIVFRAC: Fractional baud rate divisor (0..63)
// <o.0..5> BAUD DIVFRAC: Fractional baud rate divisor (0..63) // </h>
// </h> __IO uint32_t UARTLCR_H; // <h> Line Control
__IO uint32_t UARTLCR_H; // <h> Line Control // <o.8> SPS: Stick parity select
// <o.8> SPS: Stick parity select // <o.5..6> WLEN: Word length
// <o.5..6> WLEN: Word length // <0=> 5 bits
// <0=> 5 bits // <1=> 6 bits
// <1=> 6 bits // <2=> 7 bits
// <2=> 7 bits // <3=> 8 bits
// <3=> 8 bits // <o.4> FEN: Enable FIFOs
// <o.4> FEN: Enable FIFOs // <o.3> STP2: Two stop bits select
// <o.3> STP2: Two stop bits select // <o.2> EPS: Even parity select
// <o.2> EPS: Even parity select // <o.1> PEN: Parity enable
// <o.1> PEN: Parity enable // <o.0> BRK: Send break
// <o.0> BRK: Send break // </h>
// </h> __IO uint32_t UARTCR; // <h> Control
__IO uint32_t UARTCR; // <h> Control // <o.15> CTSEn: CTS hardware flow control enable
// <o.15> CTSEn: CTS hardware flow control enable // <o.14> RTSEn: RTS hardware flow control enable
// <o.14> RTSEn: RTS hardware flow control enable // <o.13> Out2: Complement of Out2 modem status output
// <o.13> Out2: Complement of Out2 modem status output // <o.12> Out1: Complement of Out1 modem status output
// <o.12> Out1: Complement of Out1 modem status output // <o.11> RTS: Request to send
// <o.11> RTS: Request to send // <o.10> DTR: Data transmit ready
// <o.10> DTR: Data transmit ready // <o.9> RXE: Receive enable
// <o.9> RXE: Receive enable // <o.8> TXE: Transmit enable
// <o.8> TXE: Transmit enable // <o.7> LBE: Loop-back enable
// <o.7> LBE: Loop-back enable // <o.2> SIRLP: IrDA SIR low power mode
// <o.2> SIRLP: IrDA SIR low power mode // <o.1> SIREN: SIR enable
// <o.1> SIREN: SIR enable // <o.0> UARTEN: UART enable
// <o.0> UARTEN: UART enable // </h>
// </h> __IO uint32_t UARTIFLS; // <h> Interrupt FIFO Level Select
__IO uint32_t UARTIFLS; // <h> Interrupt FIFO Level Select // <o.3..5> RXIFLSEL: Receive interrupt FIFO level select
// <o.3..5> RXIFLSEL: Receive interrupt FIFO level select // <0=> >= 1/8 full
// <0=> >= 1/8 full // <1=> >= 1/4 full
// <1=> >= 1/4 full // <2=> >= 1/2 full
// <2=> >= 1/2 full // <3=> >= 3/4 full
// <3=> >= 3/4 full // <4=> >= 7/8 full
// <4=> >= 7/8 full // <5=> reserved
// <5=> reserved // <6=> reserved
// <6=> reserved // <7=> reserved
// <7=> reserved // <o.0..2> TXIFLSEL: Transmit interrupt FIFO level select
// <o.0..2> TXIFLSEL: Transmit interrupt FIFO level select // <0=> <= 1/8 full
// <0=> <= 1/8 full // <1=> <= 1/4 full
// <1=> <= 1/4 full // <2=> <= 1/2 full
// <2=> <= 1/2 full // <3=> <= 3/4 full
// <3=> <= 3/4 full // <4=> <= 7/8 full
// <4=> <= 7/8 full // <5=> reserved
// <5=> reserved // <6=> reserved
// <6=> reserved // <7=> reserved
// <7=> reserved // </h>
// </h> __IO uint32_t UARTIMSC; // <h> Interrupt Mask Set / Clear
__IO uint32_t UARTIMSC; // <h> Interrupt Mask Set / Clear // <o.10> OEIM: Overrun error interrupt mask
// <o.10> OEIM: Overrun error interrupt mask // <o.9> BEIM: Break error interrupt mask
// <o.9> BEIM: Break error interrupt mask // <o.8> PEIM: Parity error interrupt mask
// <o.8> PEIM: Parity error interrupt mask // <o.7> FEIM: Framing error interrupt mask
// <o.7> FEIM: Framing error interrupt mask // <o.6> RTIM: Receive interrupt mask
// <o.6> RTIM: Receive interrupt mask // <o.5> TXIM: Transmit interrupt mask
// <o.5> TXIM: Transmit interrupt mask // <o.4> RXIM: Receive interrupt mask
// <o.4> RXIM: Receive interrupt mask // <o.3> DSRMIM: nUARTDSR modem interrupt mask
// <o.3> DSRMIM: nUARTDSR modem interrupt mask // <o.2> DCDMIM: nUARTDCD modem interrupt mask
// <o.2> DCDMIM: nUARTDCD modem interrupt mask // <o.1> CTSMIM: nUARTCTS modem interrupt mask
// <o.1> CTSMIM: nUARTCTS modem interrupt mask // <o.0> RIMIM: nUARTRI modem interrupt mask
// <o.0> RIMIM: nUARTRI modem interrupt mask // </h>
// </h> __IO uint32_t UARTRIS; // <h> Raw Interrupt Status <r>
__IO uint32_t UARTRIS; // <h> Raw Interrupt Status <r> // <o.10> OERIS: Overrun error interrupt status <r>
// <o.10> OERIS: Overrun error interrupt status <r> // <o.9> BERIS: Break error interrupt status <r>
// <o.9> BERIS: Break error interrupt status <r> // <o.8> PERIS: Parity error interrupt status <r>
// <o.8> PERIS: Parity error interrupt status <r> // <o.7> FERIS: Framing error interrupt status <r>
// <o.7> FERIS: Framing error interrupt status <r> // <o.6> RTRIS: Receive timeout interrupt status <r>
// <o.6> RTRIS: Receive timeout interrupt status <r> // <o.5> TXRIS: Transmit interrupt status <r>
// <o.5> TXRIS: Transmit interrupt status <r> // <o.4> RXRIS: Receive interrupt status <r>
// <o.4> RXRIS: Receive interrupt status <r> // <o.3> DSRRMIS: nUARTDSR modem interrupt status <r>
// <o.3> DSRRMIS: nUARTDSR modem interrupt status <r> // <o.2> DCDRMIS: nUARTDCD modem interrupt status <r>
// <o.2> DCDRMIS: nUARTDCD modem interrupt status <r> // <o.1> CTSRMIS: nUARTCTS modem interrupt status <r>
// <o.1> CTSRMIS: nUARTCTS modem interrupt status <r> // <o.0> RIRMIS: nUARTRI modem interrupt status <r>
// <o.0> RIRMIS: nUARTRI modem interrupt status <r> // </h>
// </h> __IO uint32_t UARTMIS; // <h> Masked Interrupt Status <r>
__IO uint32_t UARTMIS; // <h> Masked Interrupt Status <r> // <o.10> OEMIS: Overrun error masked interrupt status <r>
// <o.10> OEMIS: Overrun error masked interrupt status <r> // <o.9> BEMIS: Break error masked interrupt status <r>
// <o.9> BEMIS: Break error masked interrupt status <r> // <o.8> PEMIS: Parity error masked interrupt status <r>
// <o.8> PEMIS: Parity error masked interrupt status <r> // <o.7> FEMIS: Framing error masked interrupt status <r>
// <o.7> FEMIS: Framing error masked interrupt status <r> // <o.6> RTMIS: Receive timeout masked interrupt status <r>
// <o.6> RTMIS: Receive timeout masked interrupt status <r> // <o.5> TXMIS: Transmit masked interrupt status <r>
// <o.5> TXMIS: Transmit masked interrupt status <r> // <o.4> RXMIS: Receive masked interrupt status <r>
// <o.4> RXMIS: Receive masked interrupt status <r> // <o.3> DSRMMIS: nUARTDSR modem masked interrupt status <r>
// <o.3> DSRMMIS: nUARTDSR modem masked interrupt status <r> // <o.2> DCDMMIS: nUARTDCD modem masked interrupt status <r>
// <o.2> DCDMMIS: nUARTDCD modem masked interrupt status <r> // <o.1> CTSMMIS: nUARTCTS modem masked interrupt status <r>
// <o.1> CTSMMIS: nUARTCTS modem masked interrupt status <r> // <o.0> RIMMIS: nUARTRI modem masked interrupt status <r>
// <o.0> RIMMIS: nUARTRI modem masked interrupt status <r> // </h>
// </h> __O uint32_t UARTICR; // <h> Interrupt Clear <w>
__O uint32_t UARTICR; // <h> Interrupt Clear <w> // <o.10> OEIC: Overrun error interrupt clear <w>
// <o.10> OEIC: Overrun error interrupt clear <w> // <o.9> BEIC: Break error interrupt clear <w>
// <o.9> BEIC: Break error interrupt clear <w> // <o.8> PEIC: Parity error interrupt clear <w>
// <o.8> PEIC: Parity error interrupt clear <w> // <o.7> FEIC: Framing error interrupt clear <w>
// <o.7> FEIC: Framing error interrupt clear <w> // <o.6> RTIC: Receive timeout interrupt clear <w>
// <o.6> RTIC: Receive timeout interrupt clear <w> // <o.5> TXIC: Transmit interrupt clear <w>
// <o.5> TXIC: Transmit interrupt clear <w> // <o.4> RXIC: Receive interrupt clear <w>
// <o.4> RXIC: Receive interrupt clear <w> // <o.3> DSRMIC: nUARTDSR modem interrupt clear <w>
// <o.3> DSRMIC: nUARTDSR modem interrupt clear <w> // <o.2> DCDMIC: nUARTDCD modem interrupt clear <w>
// <o.2> DCDMIC: nUARTDCD modem interrupt clear <w> // <o.1> CTSMIC: nUARTCTS modem interrupt clear <w>
// <o.1> CTSMIC: nUARTCTS modem interrupt clear <w> // <o.0> RIMIC: nUARTRI modem interrupt clear <w>
// <o.0> RIMIC: nUARTRI modem interrupt clear <w> // </h>
// </h> __IO uint32_t UARTDMACR; // <h> DMA Control
__IO uint32_t UARTDMACR; // <h> DMA Control // <o.2> DMAONERR: DMA on error
// <o.2> DMAONERR: DMA on error // <o.1> TXDMAE: Transmit DMA enable
// <o.1> TXDMAE: Transmit DMA enable // <o.0> RXDMAE: Receive DMA enable
// <o.0> RXDMAE: Receive DMA enable // </h>
// </h>
} PL110_UART_TypeDef; } PL110_UART_TypeDef;
#define CMSDK_PL110_DATAOVRRUN_Pos 11 /*!< CMSDK_PL110 DATAOVRRUN: Data Overrun Position */ #define CMSDK_PL110_DATAOVRRUN_Pos 11 /*!< CMSDK_PL110 DATAOVRRUN: Data Overrun Position */
@ -1113,24 +1104,23 @@ typedef struct
/** @addtogroup CMSDK_Watchdog CMSDK Watchdog /** @addtogroup CMSDK_Watchdog CMSDK Watchdog
@{ @{
*/ */
typedef struct typedef struct {
{
__IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */ __IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */
__I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */ __I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */
__IO uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */ __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */
/* <o.1> RESEN: Reset enable */ /* <o.1> RESEN: Reset enable */
/* <o.0> INTEN: Interrupt enable */ /* <o.0> INTEN: Interrupt enable */
/* </h> */ /* </h> */
__O uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */ __O uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */
__I uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */ __I uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */
__I uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */ __I uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */
uint32_t RESERVED0[762]; uint32_t RESERVED0[762];
__IO uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */ __IO uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */
uint32_t RESERVED1[191]; uint32_t RESERVED1[191];
__IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */ __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */
__O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */ __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */
}CMSDK_WATCHDOG_TypeDef; } CMSDK_WATCHDOG_TypeDef;
#define CMSDK_Watchdog_LOAD_Pos 0 /*!< CMSDK_Watchdog LOAD: LOAD Position */ #define CMSDK_Watchdog_LOAD_Pos 0 /*!< CMSDK_Watchdog LOAD: LOAD Position */
#define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /*!< CMSDK_Watchdog LOAD: LOAD Mask */ #define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /*!< CMSDK_Watchdog LOAD: LOAD Mask */
@ -1168,21 +1158,20 @@ typedef struct
/** @addtogroup CMSDK_PL061 CMSDK APB GPIO /** @addtogroup CMSDK_PL061 CMSDK APB GPIO
@{ @{
*/ */
typedef struct typedef struct {
{
__IO uint32_t DATA[256]; __IO uint32_t DATA[256];
__IO uint32_t DIR; __IO uint32_t DIR;
__IO uint32_t INTSENSE; __IO uint32_t INTSENSE;
__IO uint32_t INTBOTHEDGE; __IO uint32_t INTBOTHEDGE;
__IO uint32_t INTEVENT; __IO uint32_t INTEVENT;
__IO uint32_t INTMASK; __IO uint32_t INTMASK;
__O uint32_t RAWINTSTAT; __O uint32_t RAWINTSTAT;
__O uint32_t MASKINTSTAT; __O uint32_t MASKINTSTAT;
__I uint32_t INTCLR; __I uint32_t INTCLR;
__IO uint32_t MODECTRL; __IO uint32_t MODECTRL;
}APBGPIO_TypeDef; } APBGPIO_TypeDef;
#define CMSDK_PL061_DATA_Pos 0 /*!< CMSDK_PL061 DATA: DATA Position */ #define CMSDK_PL061_DATA_Pos 0 /*!< CMSDK_PL061 DATA: DATA Position */
#define CMSDK_PL061_DATA_Msk (0xFFFFFFFFul << CMSDK_PL061_LOAD_Pos) /*!< CMSDK_PL061 DATA: DATA Mask */ #define CMSDK_PL061_DATA_Msk (0xFFFFFFFFul << CMSDK_PL061_LOAD_Pos) /*!< CMSDK_PL061 DATA: DATA Mask */

560
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/SMM_MPS2.h
View File

@ -46,40 +46,39 @@
/* FPGA System Register declaration */ /* FPGA System Register declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct typedef struct {
{ __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections
__IO uint32_t LED; // Offset: 0x000 (R/W) LED connections // [31:2] : Reserved
// [31:2] : Reserved // [1:0] : LEDs
// [1:0] : LEDs uint32_t RESERVED1[1];
uint32_t RESERVED1[1]; __IO uint32_t BUTTON; // Offset: 0x008 (R/W) Buttons
__IO uint32_t BUTTON; // Offset: 0x008 (R/W) Buttons // [31:2] : Reserved
// [31:2] : Reserved // [1:0] : Buttons
// [1:0] : Buttons uint32_t RESERVED2[1];
uint32_t RESERVED2[1]; __IO uint32_t CLK1HZ; // Offset: 0x010 (R/W) 1Hz up counter
__IO uint32_t CLK1HZ; // Offset: 0x010 (R/W) 1Hz up counter __IO uint32_t CLK100HZ; // Offset: 0x014 (R/W) 100Hz up counter
__IO uint32_t CLK100HZ; // Offset: 0x014 (R/W) 100Hz up counter __IO uint32_t COUNTER; // Offset: 0x018 (R/W) Cycle Up Counter
__IO uint32_t COUNTER; // Offset: 0x018 (R/W) Cycle Up Counter // Increments when 32-bit prescale counter reach zero
// Increments when 32-bit prescale counter reach zero uint32_t RESERVED3[1];
uint32_t RESERVED3[1]; __IO uint32_t PRESCALE; // Offset: 0x020 (R/W) Prescaler
__IO uint32_t PRESCALE; // Offset: 0x020 (R/W) Prescaler // Bit[31:0] : reload value for prescale counter
// Bit[31:0] : reload value for prescale counter __IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter
__IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter // current value of the pre-scaler counter
// current value of the pre-scaler counter // The Cycle Up Counter increment when the prescale down counter reach 0
// The Cycle Up Counter increment when the prescale down counter reach 0 // The pre-scaler counter is reloaded with PRESCALE after reaching 0.
// The pre-scaler counter is reloaded with PRESCALE after reaching 0. uint32_t RESERVED4[9];
uint32_t RESERVED4[9]; __IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */
__IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */ // [31:10] : Reserved
// [31:10] : Reserved // [9] : SHIELD_1_SPI_nCS
// [9] : SHIELD_1_SPI_nCS // [8] : SHIELD_0_SPI_nCS
// [8] : SHIELD_0_SPI_nCS // [7] : ADC_SPI_nCS
// [7] : ADC_SPI_nCS // [6] : CLCD_BL_CTRL
// [6] : CLCD_BL_CTRL // [5] : CLCD_RD
// [5] : CLCD_RD // [4] : CLCD_RS
// [4] : CLCD_RS // [3] : CLCD_RESET
// [3] : CLCD_RESET // [2] : RESERVED
// [2] : RESERVED // [1] : SPI_nSS
// [1] : SPI_nSS // [0] : CLCD_CS
// [0] : CLCD_CS
} MPS2_FPGAIO_TypeDef; } MPS2_FPGAIO_TypeDef;
// MISC register bit definitions // MISC register bit definitions
@ -107,58 +106,57 @@ typedef struct
/* SCC Register declaration */ /* SCC Register declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct // typedef struct { //
{ __IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT
__IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT // [31:1] : Reserved
// [31:1] : Reserved // [0] 1 : REMAP BlockRam to ZBT
// [0] 1 : REMAP BlockRam to ZBT __IO uint32_t LEDS; // Offset: 0x004 (R/W) Controls the MCC user LEDs
__IO uint32_t LEDS; // Offset: 0x004 (R/W) Controls the MCC user LEDs // [31:8] : Reserved
// [31:8] : Reserved // [7:0] : MCC LEDs
// [7:0] : MCC LEDs uint32_t RESERVED0[1];
uint32_t RESERVED0[1]; __I uint32_t SWITCHES; // Offset: 0x00C (R/ ) Denotes the state of the MCC user switches
__I uint32_t SWITCHES; // Offset: 0x00C (R/ ) Denotes the state of the MCC user switches // [31:8] : Reserved
// [31:8] : Reserved // [7:0] : These bits indicate state of the MCC switches
// [7:0] : These bits indicate state of the MCC switches __I uint32_t CFG_REG4; // Offset: 0x010 (R/ ) Denotes the board revision
__I uint32_t CFG_REG4; // Offset: 0x010 (R/ ) Denotes the board revision // [31:4] : Reserved
// [31:4] : Reserved // [3:0] : Used by the MCC to pass PCB revision. 0 = A 1 = B
// [3:0] : Used by the MCC to pass PCB revision. 0 = A 1 = B uint32_t RESERVED1[35];
uint32_t RESERVED1[35]; __IO uint32_t SYS_CFGDATA_RTN; // Offset: 0x0A0 (R/W) User data register
__IO uint32_t SYS_CFGDATA_RTN; // Offset: 0x0A0 (R/W) User data register // [31:0] : Data
// [31:0] : Data __IO uint32_t SYS_CFGDATA_OUT; // Offset: 0x0A4 (R/W) User data register
__IO uint32_t SYS_CFGDATA_OUT; // Offset: 0x0A4 (R/W) User data register // [31:0] : Data
// [31:0] : Data __IO uint32_t SYS_CFGCTRL; // Offset: 0x0A8 (R/W) Control register
__IO uint32_t SYS_CFGCTRL; // Offset: 0x0A8 (R/W) Control register // [31] : Start (generates interrupt on write to this bit)
// [31] : Start (generates interrupt on write to this bit) // [30] : R/W access
// [30] : R/W access // [29:26] : Reserved
// [29:26] : Reserved // [25:20] : Function value
// [25:20] : Function value // [19:12] : Reserved
// [19:12] : Reserved // [11:0] : Device (value of 0/1/2 for supported clocks)
// [11:0] : Device (value of 0/1/2 for supported clocks) __IO uint32_t SYS_CFGSTAT; // Offset: 0x0AC (R/W) Contains status information
__IO uint32_t SYS_CFGSTAT; // Offset: 0x0AC (R/W) Contains status information // [31:2] : Reserved
// [31:2] : Reserved // [1] : Error
// [1] : Error // [0] : Complete
// [0] : Complete __IO uint32_t RESERVED2[20];
__IO uint32_t RESERVED2[20]; __IO uint32_t SCC_DLL; // Offset: 0x100 (R/W) DLL Lock Register
__IO uint32_t SCC_DLL; // Offset: 0x100 (R/W) DLL Lock Register // [31:24] : DLL LOCK MASK[7:0] - Indicate if the DLL locked is masked
// [31:24] : DLL LOCK MASK[7:0] - Indicate if the DLL locked is masked // [23:16] : DLL LOCK MASK[7:0] - Indicate if the DLLs are locked or unlocked
// [23:16] : DLL LOCK MASK[7:0] - Indicate if the DLLs are locked or unlocked // [15:1] : Reserved
// [15:1] : Reserved // [0] : This bit indicates if all enabled DLLs are locked
// [0] : This bit indicates if all enabled DLLs are locked uint32_t RESERVED3[957];
uint32_t RESERVED3[957]; __I uint32_t SCC_AID; // Offset: 0xFF8 (R/ ) SCC AID Register
__I uint32_t SCC_AID; // Offset: 0xFF8 (R/ ) SCC AID Register // [31:24] : FPGA build number
// [31:24] : FPGA build number // [23:20] : V2M-MPS2 target board revision (A = 0, B = 1)
// [23:20] : V2M-MPS2 target board revision (A = 0, B = 1) // [19:11] : Reserved
// [19:11] : Reserved // [10] : if “1” SCC_SW register has been implemented
// [10] : if “1” SCC_SW register has been implemented // [9] : if “1” SCC_LED register has been implemented
// [9] : if “1” SCC_LED register has been implemented // [8] : if “1” DLL lock register has been implemented
// [8] : if “1” DLL lock register has been implemented // [7:0] : number of SCC configuration register
// [7:0] : number of SCC configuration register __I uint32_t SCC_ID; // Offset: 0xFFC (R/ ) Contains information about the FPGA image
__I uint32_t SCC_ID; // Offset: 0xFFC (R/ ) Contains information about the FPGA image // [31:24] : Implementer ID: 0x41 = ARM
// [31:24] : Implementer ID: 0x41 = ARM // [23:20] : Application note IP variant number
// [23:20] : Application note IP variant number // [19:16] : IP Architecture: 0x4 =AHB
// [19:16] : IP Architecture: 0x4 =AHB // [15:4] : Primary part number: 386 = AN386
// [15:4] : Primary part number: 386 = AN386 // [3:0] : Application note IP revision number
// [3:0] : Application note IP revision number
} MPS2_SCC_TypeDef; } MPS2_SCC_TypeDef;
@ -166,60 +164,59 @@ typedef struct //
/* SSP Peripheral declaration */ /* SSP Peripheral declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf typedef struct { // Document DDI0194G_ssp_pl022_r1p3_trm.pdf
{ __IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0
__IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0 // [31:16] : Reserved
// [31:16] : Reserved // [15:8] : Serial clock rate
// [15:8] : Serial clock rate // [7] : SSPCLKOUT phase, applicable to Motorola SPI frame format only
// [7] : SSPCLKOUT phase, applicable to Motorola SPI frame format only // [6] : SSPCLKOUT polarity, applicable to Motorola SPI frame format only
// [6] : SSPCLKOUT polarity, applicable to Motorola SPI frame format only // [5:4] : Frame format
// [5:4] : Frame format // [3:0] : Data Size Select
// [3:0] : Data Size Select __IO uint32_t CR1; // Offset: 0x004 (R/W) Control register 1
__IO uint32_t CR1; // Offset: 0x004 (R/W) Control register 1 // [31:4] : Reserved
// [31:4] : Reserved // [3] : Slave-mode output disable
// [3] : Slave-mode output disable // [2] : Master or slave mode select
// [2] : Master or slave mode select // [1] : Synchronous serial port enable
// [1] : Synchronous serial port enable // [0] : Loop back mode
// [0] : Loop back mode __IO uint32_t DR; // Offset: 0x008 (R/W) Data register
__IO uint32_t DR; // Offset: 0x008 (R/W) Data register // [31:16] : Reserved
// [31:16] : Reserved // [15:0] : Transmit/Receive FIFO
// [15:0] : Transmit/Receive FIFO __I uint32_t SR; // Offset: 0x00C (R/ ) Status register
__I uint32_t SR; // Offset: 0x00C (R/ ) Status register // [31:5] : Reserved
// [31:5] : Reserved // [4] : PrimeCell SSP busy flag
// [4] : PrimeCell SSP busy flag // [3] : Receive FIFO full
// [3] : Receive FIFO full // [2] : Receive FIFO not empty
// [2] : Receive FIFO not empty // [1] : Transmit FIFO not full
// [1] : Transmit FIFO not full // [0] : Transmit FIFO empty
// [0] : Transmit FIFO empty __IO uint32_t CPSR; // Offset: 0x010 (R/W) Clock prescale register
__IO uint32_t CPSR; // Offset: 0x010 (R/W) Clock prescale register // [31:8] : Reserved
// [31:8] : Reserved // [8:0] : Clock prescale divisor
// [8:0] : Clock prescale divisor __IO uint32_t IMSC; // Offset: 0x014 (R/W) Interrupt mask set or clear register
__IO uint32_t IMSC; // Offset: 0x014 (R/W) Interrupt mask set or clear register // [31:4] : Reserved
// [31:4] : Reserved // [3] : Transmit FIFO interrupt mask
// [3] : Transmit FIFO interrupt mask // [2] : Receive FIFO interrupt mask
// [2] : Receive FIFO interrupt mask // [1] : Receive timeout interrupt mask
// [1] : Receive timeout interrupt mask // [0] : Receive overrun interrupt mask
// [0] : Receive overrun interrupt mask __I uint32_t RIS; // Offset: 0x018 (R/ ) Raw interrupt status register
__I uint32_t RIS; // Offset: 0x018 (R/ ) Raw interrupt status register // [31:4] : Reserved
// [31:4] : Reserved // [3] : raw interrupt state, prior to masking, of the SSPTXINTR interrupt
// [3] : raw interrupt state, prior to masking, of the SSPTXINTR interrupt // [2] : raw interrupt state, prior to masking, of the SSPRXINTR interrupt
// [2] : raw interrupt state, prior to masking, of the SSPRXINTR interrupt // [1] : raw interrupt state, prior to masking, of the SSPRTINTR interrupt
// [1] : raw interrupt state, prior to masking, of the SSPRTINTR interrupt // [0] : raw interrupt state, prior to masking, of the SSPRORINTR interrupt
// [0] : raw interrupt state, prior to masking, of the SSPRORINTR interrupt __I uint32_t MIS; // Offset: 0x01C (R/ ) Masked interrupt status register
__I uint32_t MIS; // Offset: 0x01C (R/ ) Masked interrupt status register // [31:4] : Reserved
// [31:4] : Reserved // [3] : transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt
// [3] : transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt // [2] : receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt
// [2] : receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt // [1] : receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt
// [1] : receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt // [0] : receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt
// [0] : receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt __O uint32_t ICR; // Offset: 0x020 ( /W) Interrupt clear register
__O uint32_t ICR; // Offset: 0x020 ( /W) Interrupt clear register // [31:2] : Reserved
// [31:2] : Reserved // [1] : Clears the SSPRTINTR interrupt
// [1] : Clears the SSPRTINTR interrupt // [0] : Clears the SSPRORINTR interrupt
// [0] : Clears the SSPRORINTR interrupt __IO uint32_t DMACR; // Offset: 0x024 (R/W) DMA control register
__IO uint32_t DMACR; // Offset: 0x024 (R/W) DMA control register // [31:2] : Reserved
// [31:2] : Reserved // [1] : Transmit DMA Enable
// [1] : Transmit DMA Enable // [0] : Receive DMA Enable
// [0] : Receive DMA Enable
} MPS2_SSP_TypeDef; } MPS2_SSP_TypeDef;
@ -314,13 +311,12 @@ typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf
/* Audio and Touch Screen (I2C) Peripheral declaration */ /* Audio and Touch Screen (I2C) Peripheral declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct typedef struct {
{ union {
union { __O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W)
__O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W) __I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ )
__I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ ) };
}; __O uint32_t CONTROLC; // Offset: 0x004 CONTROL Clear Register ( /W)
__O uint32_t CONTROLC; // Offset: 0x004 CONTROL Clear Register ( /W)
} MPS2_I2C_TypeDef; } MPS2_I2C_TypeDef;
#define SDA 1 << 1 #define SDA 1 << 1
@ -331,107 +327,106 @@ typedef struct
/* Audio I2S Peripheral declaration */ /* Audio I2S Peripheral declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct typedef struct {
{ /*!< Offset: 0x000 CONTROL Register (R/W) */
/*!< Offset: 0x000 CONTROL Register (R/W) */ __IO uint32_t CONTROL; // <h> CONTROL </h>
__IO uint32_t CONTROL; // <h> CONTROL </h> // <o.0> TX Enable
// <o.0> TX Enable // <0=> TX disabled
// <0=> TX disabled // <1=> TX enabled
// <1=> TX enabled // <o.1> TX IRQ Enable
// <o.1> TX IRQ Enable // <0=> TX IRQ disabled
// <0=> TX IRQ disabled // <1=> TX IRQ enabled
// <1=> TX IRQ enabled // <o.2> RX Enable
// <o.2> RX Enable // <0=> RX disabled
// <0=> RX disabled // <1=> RX enabled
// <1=> RX enabled // <o.3> RX IRQ Enable
// <o.3> RX IRQ Enable // <0=> RX IRQ disabled
// <0=> RX IRQ disabled // <1=> RX IRQ enabled
// <1=> RX IRQ enabled // <o.10..8> TX Buffer Water Level
// <o.10..8> TX Buffer Water Level // <0=> / IRQ triggers when any space available
// <0=> / IRQ triggers when any space available // <1=> / IRQ triggers when more than 1 space available
// <1=> / IRQ triggers when more than 1 space available // <2=> / IRQ triggers when more than 2 space available
// <2=> / IRQ triggers when more than 2 space available // <3=> / IRQ triggers when more than 3 space available
// <3=> / IRQ triggers when more than 3 space available // <4=> Undefined!
// <4=> Undefined! // <5=> Undefined!
// <5=> Undefined! // <6=> Undefined!
// <6=> Undefined! // <7=> Undefined!
// <7=> Undefined! // <o.14..12> RX Buffer Water Level
// <o.14..12> RX Buffer Water Level // <0=> Undefined!
// <0=> Undefined! // <1=> / IRQ triggers when less than 1 space available
// <1=> / IRQ triggers when less than 1 space available // <2=> / IRQ triggers when less than 2 space available
// <2=> / IRQ triggers when less than 2 space available // <3=> / IRQ triggers when less than 3 space available
// <3=> / IRQ triggers when less than 3 space available // <4=> / IRQ triggers when less than 4 space available
// <4=> / IRQ triggers when less than 4 space available // <5=> Undefined!
// <5=> Undefined! // <6=> Undefined!
// <6=> Undefined! // <7=> Undefined!
// <7=> Undefined! // <o.16> FIFO reset
// <o.16> FIFO reset // <0=> Normal operation
// <0=> Normal operation // <1=> FIFO reset
// <1=> FIFO reset // <o.17> Audio Codec reset
// <o.17> Audio Codec reset // <0=> Normal operation
// <0=> Normal operation // <1=> Assert audio Codec reset
// <1=> Assert audio Codec reset /*!< Offset: 0x004 STATUS Register (R/ ) */
/*!< Offset: 0x004 STATUS Register (R/ ) */ __I uint32_t STATUS; // <h> STATUS </h>
__I uint32_t STATUS; // <h> STATUS </h> // <o.0> TX Buffer alert
// <o.0> TX Buffer alert // <0=> TX buffer don't need service yet
// <0=> TX buffer don't need service yet // <1=> TX buffer need service
// <1=> TX buffer need service // <o.1> RX Buffer alert
// <o.1> RX Buffer alert // <0=> RX buffer don't need service yet
// <0=> RX buffer don't need service yet // <1=> RX buffer need service
// <1=> RX buffer need service // <o.2> TX Buffer Empty
// <o.2> TX Buffer Empty // <0=> TX buffer have data
// <0=> TX buffer have data // <1=> TX buffer empty
// <1=> TX buffer empty // <o.3> TX Buffer Full
// <o.3> TX Buffer Full // <0=> TX buffer not full
// <0=> TX buffer not full // <1=> TX buffer full
// <1=> TX buffer full // <o.4> RX Buffer Empty
// <o.4> RX Buffer Empty // <0=> RX buffer have data
// <0=> RX buffer have data // <1=> RX buffer empty
// <1=> RX buffer empty // <o.5> RX Buffer Full
// <o.5> RX Buffer Full // <0=> RX buffer not full
// <0=> RX buffer not full // <1=> RX buffer full
// <1=> RX buffer full union {
union { /*!< Offset: 0x008 Error Status Register (R/ ) */
/*!< Offset: 0x008 Error Status Register (R/ ) */ __I uint32_t ERROR; // <h> ERROR </h>
__I uint32_t ERROR; // <h> ERROR </h> // <o.0> TX error
// <o.0> TX error // <0=> Okay
// <0=> Okay // <1=> TX overrun/underrun
// <1=> TX overrun/underrun // <o.1> RX error
// <o.1> RX error // <0=> Okay
// <0=> Okay // <1=> RX overrun/underrun
// <1=> RX overrun/underrun /*!< Offset: 0x008 Error Clear Register ( /W) */
/*!< Offset: 0x008 Error Clear Register ( /W) */ __O uint32_t ERRORCLR; // <h> ERRORCLR </h>
__O uint32_t ERRORCLR; // <h> ERRORCLR </h> // <o.0> TX error
// <o.0> TX error // <0=> Okay
// <0=> Okay // <1=> Clear TX error
// <1=> Clear TX error // <o.1> RX error
// <o.1> RX error // <0=> Okay
// <0=> Okay // <1=> Clear RX error
// <1=> Clear RX error
}; };
/*!< Offset: 0x00C Divide ratio Register (R/W) */ /*!< Offset: 0x00C Divide ratio Register (R/W) */
__IO uint32_t DIVIDE; // <h> Divide ratio for Left/Right clock </h> __IO uint32_t DIVIDE; // <h> Divide ratio for Left/Right clock </h>
// <o.9..0> TX error (default 0x80) // <o.9..0> TX error (default 0x80)
/*!< Offset: 0x010 Transmit Buffer ( /W) */ /*!< Offset: 0x010 Transmit Buffer ( /W) */
__O uint32_t TXBUF; // <h> Transmit buffer </h> __O uint32_t TXBUF; // <h> Transmit buffer </h>
// <o.15..0> Right channel // <o.15..0> Right channel
// <o.31..16> Left channel // <o.31..16> Left channel
/*!< Offset: 0x014 Receive Buffer (R/ ) */ /*!< Offset: 0x014 Receive Buffer (R/ ) */
__I uint32_t RXBUF; // <h> Receive buffer </h> __I uint32_t RXBUF; // <h> Receive buffer </h>
// <o.15..0> Right channel // <o.15..0> Right channel
// <o.31..16> Left channel // <o.31..16> Left channel
uint32_t RESERVED1[186]; uint32_t RESERVED1[186];
__IO uint32_t ITCR; // <h> Integration Test Control Register </h> __IO uint32_t ITCR; // <h> Integration Test Control Register </h>
// <o.0> ITEN // <o.0> ITEN
// <0=> Normal operation // <0=> Normal operation
// <1=> Integration Test mode enable // <1=> Integration Test mode enable
__O uint32_t ITIP1; // <h> Integration Test Input Register 1</h> __O uint32_t ITIP1; // <h> Integration Test Input Register 1</h>
// <o.0> SDIN // <o.0> SDIN
__O uint32_t ITOP1; // <h> Integration Test Output Register 1</h> __O uint32_t ITOP1; // <h> Integration Test Output Register 1</h>
// <o.0> SDOUT // <o.0> SDOUT
// <o.1> SCLK // <o.1> SCLK
// <o.2> LRCK // <o.2> LRCK
// <o.3> IRQOUT // <o.3> IRQOUT
} MPS2_I2S_TypeDef; } MPS2_I2S_TypeDef;
#define I2S_CONTROL_TXEN_Pos 0 #define I2S_CONTROL_TXEN_Pos 0
@ -486,44 +481,43 @@ typedef struct
/* SMSC9220 Register Definitions */ /* SMSC9220 Register Definitions */
/******************************************************************************/ /******************************************************************************/
typedef struct // SMSC LAN9220 typedef struct { // SMSC LAN9220
{ __I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0)
__I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0) uint32_t RESERVED1[0x7];
uint32_t RESERVED1[0x7]; __O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20)
__O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20) uint32_t RESERVED2[0x7];
uint32_t RESERVED2[0x7];
__I uint32_t RX_STAT_PORT; // Receive FIFO status port (offset 0x40) __I uint32_t RX_STAT_PORT; // Receive FIFO status port (offset 0x40)
__I uint32_t RX_STAT_PEEK; // Receive FIFO status peek (offset 0x44) __I uint32_t RX_STAT_PEEK; // Receive FIFO status peek (offset 0x44)
__I uint32_t TX_STAT_PORT; // Transmit FIFO status port (offset 0x48) __I uint32_t TX_STAT_PORT; // Transmit FIFO status port (offset 0x48)
__I uint32_t TX_STAT_PEEK; // Transmit FIFO status peek (offset 0x4C) __I uint32_t TX_STAT_PEEK; // Transmit FIFO status peek (offset 0x4C)
__I uint32_t ID_REV; // Chip ID and Revision (offset 0x50) __I uint32_t ID_REV; // Chip ID and Revision (offset 0x50)
__IO uint32_t IRQ_CFG; // Main Interrupt Configuration (offset 0x54) __IO uint32_t IRQ_CFG; // Main Interrupt Configuration (offset 0x54)
__IO uint32_t INT_STS; // Interrupt Status (offset 0x58) __IO uint32_t INT_STS; // Interrupt Status (offset 0x58)
__IO uint32_t INT_EN; // Interrupt Enable Register (offset 0x5C) __IO uint32_t INT_EN; // Interrupt Enable Register (offset 0x5C)
uint32_t RESERVED3; // Reserved for future use (offset 0x60) uint32_t RESERVED3; // Reserved for future use (offset 0x60)
__I uint32_t BYTE_TEST; // Read-only byte order testing register 87654321h (offset 0x64) __I uint32_t BYTE_TEST; // Read-only byte order testing register 87654321h (offset 0x64)
__IO uint32_t FIFO_INT; // FIFO Level Interrupts (offset 0x68) __IO uint32_t FIFO_INT; // FIFO Level Interrupts (offset 0x68)
__IO uint32_t RX_CFG; // Receive Configuration (offset 0x6C) __IO uint32_t RX_CFG; // Receive Configuration (offset 0x6C)
__IO uint32_t TX_CFG; // Transmit Configuration (offset 0x70) __IO uint32_t TX_CFG; // Transmit Configuration (offset 0x70)
__IO uint32_t HW_CFG; // Hardware Configuration (offset 0x74) __IO uint32_t HW_CFG; // Hardware Configuration (offset 0x74)
__IO uint32_t RX_DP_CTL; // RX Datapath Control (offset 0x78) __IO uint32_t RX_DP_CTL; // RX Datapath Control (offset 0x78)
__I uint32_t RX_FIFO_INF; // Receive FIFO Information (offset 0x7C) __I uint32_t RX_FIFO_INF; // Receive FIFO Information (offset 0x7C)
__I uint32_t TX_FIFO_INF; // Transmit FIFO Information (offset 0x80) __I uint32_t TX_FIFO_INF; // Transmit FIFO Information (offset 0x80)
__IO uint32_t PMT_CTRL; // Power Management Control (offset 0x84) __IO uint32_t PMT_CTRL; // Power Management Control (offset 0x84)
__IO uint32_t GPIO_CFG; // General Purpose IO Configuration (offset 0x88) __IO uint32_t GPIO_CFG; // General Purpose IO Configuration (offset 0x88)
__IO uint32_t GPT_CFG; // General Purpose Timer Configuration (offset 0x8C) __IO uint32_t GPT_CFG; // General Purpose Timer Configuration (offset 0x8C)
__I uint32_t GPT_CNT; // General Purpose Timer Count (offset 0x90) __I uint32_t GPT_CNT; // General Purpose Timer Count (offset 0x90)
uint32_t RESERVED4; // Reserved for future use (offset 0x94) uint32_t RESERVED4; // Reserved for future use (offset 0x94)
__IO uint32_t ENDIAN; // WORD SWAP Register (offset 0x98) __IO uint32_t ENDIAN; // WORD SWAP Register (offset 0x98)
__I uint32_t FREE_RUN; // Free Run Counter (offset 0x9C) __I uint32_t FREE_RUN; // Free Run Counter (offset 0x9C)
__I uint32_t RX_DROP; // RX Dropped Frames Counter (offset 0xA0) __I uint32_t RX_DROP; // RX Dropped Frames Counter (offset 0xA0)
__IO uint32_t MAC_CSR_CMD; // MAC CSR Synchronizer Command (offset 0xA4) __IO uint32_t MAC_CSR_CMD; // MAC CSR Synchronizer Command (offset 0xA4)
__IO uint32_t MAC_CSR_DATA; // MAC CSR Synchronizer Data (offset 0xA8) __IO uint32_t MAC_CSR_DATA; // MAC CSR Synchronizer Data (offset 0xA8)
__IO uint32_t AFC_CFG; // Automatic Flow Control Configuration (offset 0xAC) __IO uint32_t AFC_CFG; // Automatic Flow Control Configuration (offset 0xAC)
__IO uint32_t E2P_CMD; // EEPROM Command (offset 0xB0) __IO uint32_t E2P_CMD; // EEPROM Command (offset 0xB0)
__IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4) __IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4)
} SMSC9220_TypeDef; } SMSC9220_TypeDef;

12
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/peripherallink.h
View File

@ -37,17 +37,17 @@
#define __DEVICE_H #define __DEVICE_H
#if defined CMSDK_CM0 #if defined CMSDK_CM0
#include "CMSDK_CM0.h" /* device specific header file */ #include "CMSDK_CM0.h" /* device specific header file */
#elif defined CMSDK_CM0plus #elif defined CMSDK_CM0plus
#include "CMSDK_CM0plus.h" /* device specific header file */ #include "CMSDK_CM0plus.h" /* device specific header file */
#elif defined CMSDK_CM3 #elif defined CMSDK_CM3
#include "CMSDK_CM3.h" /* device specific header file */ #include "CMSDK_CM3.h" /* device specific header file */
#elif defined CMSDK_CM4 #elif defined CMSDK_CM4
#include "CMSDK_CM4.h" /* device specific header file */ #include "CMSDK_CM4.h" /* device specific header file */
#elif defined CMSDK_CM7 #elif defined CMSDK_CM7
#include "CMSDK_CM7.h" /* device specific header file */ #include "CMSDK_CM7.h" /* device specific header file */
#else #else
#warning "no appropriate header file found!" #warning "no appropriate header file found!"
#endif #endif
#endif /* __DEVICE_H */ #endif /* __DEVICE_H */

22
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/system_CMSDK_CM4.c
View File

@ -64,10 +64,10 @@ uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Cloc
* @brief Updates the SystemCoreClock with current core Clock * @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers. * retrieved from cpu registers.
*/ */
void SystemCoreClockUpdate (void) void SystemCoreClockUpdate(void)
{ {
SystemCoreClock = __SYSTEM_CLOCK; SystemCoreClock = __SYSTEM_CLOCK;
} }
@ -80,17 +80,17 @@ void SystemCoreClockUpdate (void)
* @brief Setup the microcontroller system. * @brief Setup the microcontroller system.
* Initialize the System. * Initialize the System.
*/ */
void SystemInit (void) void SystemInit(void)
{ {
#if (__FPU_USED == 1) #if (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ SCB->CPACR |= ((3UL << 10 * 2) | /* set CP10 Full Access */
(3UL << 11*2) ); /* set CP11 Full Access */ (3UL << 11 * 2)); /* set CP11 Full Access */
#endif
#ifdef UNALIGNED_SUPPORT_DISABLE
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
#endif #endif
SystemCoreClock = __SYSTEM_CLOCK; #ifdef UNALIGNED_SUPPORT_DISABLE
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
#endif
SystemCoreClock = __SYSTEM_CLOCK;
} }

4
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/system_CMSDK_CM4.h
View File

@ -56,7 +56,7 @@ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) *
* @brief Setup the microcontroller system. * @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable. * Initialize the System and update the SystemCoreClock variable.
*/ */
extern void SystemInit (void); extern void SystemInit(void);
/** /**
* Update SystemCoreClock variable * Update SystemCoreClock variable
@ -67,7 +67,7 @@ extern void SystemInit (void);
* @brief Updates the SystemCoreClock with current core Clock * @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers. * retrieved from cpu registers.
*/ */
extern void SystemCoreClockUpdate (void); extern void SystemCoreClockUpdate(void);
#ifdef __cplusplus #ifdef __cplusplus
} }

327
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/CMSDK_CM7.h
View File

@ -46,52 +46,51 @@ extern "C" {
/* ------------------------- Interrupt Number Definition ------------------------ */ /* ------------------------- Interrupt Number Definition ------------------------ */
typedef enum IRQn typedef enum IRQn {
{ /* ------------------- Cortex-M7 Processor Exceptions Numbers ------------------- */
/* ------------------- Cortex-M7 Processor Exceptions Numbers ------------------- */ NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ HardFault_IRQn = -13, /* 3 HardFault Interrupt */
HardFault_IRQn = -13, /* 3 HardFault Interrupt */ MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ SVCall_IRQn = -5, /* 11 SV Call Interrupt */
SVCall_IRQn = -5, /* 11 SV Call Interrupt */ DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ SysTick_IRQn = -1, /* 15 System Tick Interrupt */
SysTick_IRQn = -1, /* 15 System Tick Interrupt */
/* ---------------------- CMSDK_CM7 Specific Interrupt Numbers -------------- */ /* ---------------------- CMSDK_CM7 Specific Interrupt Numbers -------------- */
UARTRX0_IRQn = 0, /* UART 0 RX Interrupt */ UARTRX0_IRQn = 0, /* UART 0 RX Interrupt */
UARTTX0_IRQn = 1, /* UART 0 TX Interrupt */ UARTTX0_IRQn = 1, /* UART 0 TX Interrupt */
UARTRX1_IRQn = 2, /* UART 1 RX Interrupt */ UARTRX1_IRQn = 2, /* UART 1 RX Interrupt */
UARTTX1_IRQn = 3, /* UART 1 TX Interrupt */ UARTTX1_IRQn = 3, /* UART 1 TX Interrupt */
UARTRX2_IRQn = 4, /* UART 2 RX Interrupt */ UARTRX2_IRQn = 4, /* UART 2 RX Interrupt */
UARTTX2_IRQn = 5, /* UART 2 TX Interrupt */ UARTTX2_IRQn = 5, /* UART 2 TX Interrupt */
PORT0_ALL_IRQn = 6, /* Port 1 combined Interrupt */ PORT0_ALL_IRQn = 6, /* Port 1 combined Interrupt */
PORT1_ALL_IRQn = 7, /* Port 1 combined Interrupt */ PORT1_ALL_IRQn = 7, /* Port 1 combined Interrupt */
TIMER0_IRQn = 8, /* TIMER 0 Interrupt */ TIMER0_IRQn = 8, /* TIMER 0 Interrupt */
TIMER1_IRQn = 9, /* TIMER 1 Interrupt */ TIMER1_IRQn = 9, /* TIMER 1 Interrupt */
DUALTIMER_IRQn = 10, /* Dual Timer Interrupt */ DUALTIMER_IRQn = 10, /* Dual Timer Interrupt */
SPI_IRQn = 11, /* SPI Interrupt */ SPI_IRQn = 11, /* SPI Interrupt */
UARTOVF_IRQn = 12, /* UART 0,1,2 Overflow Interrupt */ UARTOVF_IRQn = 12, /* UART 0,1,2 Overflow Interrupt */
ETHERNET_IRQn = 13, /* Ethernet Interrupt */ ETHERNET_IRQn = 13, /* Ethernet Interrupt */
I2S_IRQn = 14, /* I2S Interrupt */ I2S_IRQn = 14, /* I2S Interrupt */
TSC_IRQn = 15, /* Touch Screen Interrupt */ TSC_IRQn = 15, /* Touch Screen Interrupt */
PORT2_ALL_IRQn = 16, /*< Port 2 combined Interrupt */ PORT2_ALL_IRQn = 16, /*< Port 2 combined Interrupt */
PORT3_ALL_IRQn = 17, /*< Port 3 combined Interrupt */ PORT3_ALL_IRQn = 17, /*< Port 3 combined Interrupt */
UARTRX3_IRQn = 18, /*< UART 3 RX Interrupt */ UARTRX3_IRQn = 18, /*< UART 3 RX Interrupt */
UARTTX3_IRQn = 19, /*< UART 3 TX Interrupt */ UARTTX3_IRQn = 19, /*< UART 3 TX Interrupt */
UARTRX4_IRQn = 20, /*< UART 4 RX Interrupt */ UARTRX4_IRQn = 20, /*< UART 4 RX Interrupt */
UARTTX4_IRQn = 21, /*< UART 4 TX Interrupt */ UARTTX4_IRQn = 21, /*< UART 4 TX Interrupt */
ADCSPI_IRQn = 22, /*< SHIELD ADC SPI Interrupt */ ADCSPI_IRQn = 22, /*< SHIELD ADC SPI Interrupt */
SHIELDSPI_IRQn = 23, /*< SHIELD SPI Combined Interrupt */ SHIELDSPI_IRQn = 23, /*< SHIELD SPI Combined Interrupt */
PORT0_0_IRQn = 24, /*< GPIO Port 0 pin 0 Interrupt */ PORT0_0_IRQn = 24, /*< GPIO Port 0 pin 0 Interrupt */
PORT0_1_IRQn = 25, /*< GPIO Port 0 pin 1 Interrupt */ PORT0_1_IRQn = 25, /*< GPIO Port 0 pin 1 Interrupt */
PORT0_2_IRQn = 26, /*< GPIO Port 0 pin 2 Interrupt */ PORT0_2_IRQn = 26, /*< GPIO Port 0 pin 2 Interrupt */
PORT0_3_IRQn = 27, /*< GPIO Port 0 pin 3 Interrupt */ PORT0_3_IRQn = 27, /*< GPIO Port 0 pin 3 Interrupt */
PORT0_4_IRQn = 28, /*< GPIO Port 0 pin 4 Interrupt */ PORT0_4_IRQn = 28, /*< GPIO Port 0 pin 4 Interrupt */
PORT0_5_IRQn = 29, /*< GPIO Port 0 pin 5 Interrupt */ PORT0_5_IRQn = 29, /*< GPIO Port 0 pin 5 Interrupt */
PORT0_6_IRQn = 30, /*< GPIO Port 0 pin 6 Interrupt */ PORT0_6_IRQn = 30, /*< GPIO Port 0 pin 6 Interrupt */
PORT0_7_IRQn = 31, /*< GPIO Port 0 pin 7 Interrupt */ PORT0_7_IRQn = 31, /*< GPIO Port 0 pin 7 Interrupt */
} IRQn_Type; } IRQn_Type;
@ -119,33 +118,32 @@ typedef enum IRQn
/* ------------------- Start of section using anonymous unions ------------------ */ /* ------------------- Start of section using anonymous unions ------------------ */
#if defined (__CC_ARM) #if defined (__CC_ARM)
#pragma push #pragma push
#pragma anon_unions #pragma anon_unions
#elif defined (__ICCARM__) #elif defined (__ICCARM__)
#pragma language=extended #pragma language=extended
#elif defined (__GNUC__) #elif defined (__GNUC__)
/* anonymous unions are enabled by default */ /* anonymous unions are enabled by default */
#elif defined (__TMS470__) #elif defined (__TMS470__)
/* anonymous unions are enabled by default */ /* anonymous unions are enabled by default */
#elif defined (__TASKING__) #elif defined (__TASKING__)
#pragma warning 586 #pragma warning 586
#elif defined (__CSMC__) #elif defined (__CSMC__)
/* anonymous unions are enabled by default */ /* anonymous unions are enabled by default */
#else #else
#warning Not supported compiler type #warning Not supported compiler type
#endif #endif
/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
typedef struct typedef struct {
{ __IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */
__IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */ __IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */
__IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */ __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */
__IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */ union {
union { __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */
__I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */ __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */
__O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */
}; };
__IO uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register */ __IO uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register */
} CMSDK_UART_TypeDef; } CMSDK_UART_TypeDef;
@ -204,14 +202,13 @@ typedef struct
/*----------------------------- Timer (TIMER) -------------------------------*/ /*----------------------------- Timer (TIMER) -------------------------------*/
typedef struct typedef struct {
{ __IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */
__IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */ __IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */
__IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */ __IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */
__IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */ union {
union { __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */
__I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */ __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */
__O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */
}; };
} CMSDK_TIMER_TypeDef; } CMSDK_TIMER_TypeDef;
@ -244,26 +241,25 @@ typedef struct
/*------------- Timer (TIM) --------------------------------------------------*/ /*------------- Timer (TIM) --------------------------------------------------*/
typedef struct typedef struct {
{ __IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
__IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */ __I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
__I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */ __IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
__IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */ __O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
__O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */ __I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
__I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */ __I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
__I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */ __IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */
__IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */ uint32_t RESERVED0;
uint32_t RESERVED0; __IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */
__IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */ __I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
__I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */ __IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */
__IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */ __O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
__O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */ __I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
__I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */ __I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
__I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */ __IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */
__IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */ uint32_t RESERVED1[945];
uint32_t RESERVED1[945]; __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Integration Test Control Register */
__IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Integration Test Control Register */ __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Integration Test Output Set Register */
__O uint32_t ITOP; /* Offset: 0xF04 ( /W) Integration Test Output Set Register */
} CMSDK_DUALTIMER_BOTH_TypeDef; } CMSDK_DUALTIMER_BOTH_TypeDef;
#define CMSDK_DUALTIMER1_LOAD_Pos 0 /* CMSDK_DUALTIMER1 LOAD: LOAD Position */ #define CMSDK_DUALTIMER1_LOAD_Pos 0 /* CMSDK_DUALTIMER1 LOAD: LOAD Position */
@ -339,15 +335,14 @@ typedef struct
#define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /* CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */ #define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /* CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */
typedef struct typedef struct {
{ __IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */
__IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */ __I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */
__I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */ __IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */
__IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */ __O uint32_t TimerIntClr; /* Offset: 0x000 (R/W) Timer Interrupt Clear */
__O uint32_t TimerIntClr; /* Offset: 0x000 (R/W) Timer Interrupt Clear */ __I uint32_t TimerRIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */
__I uint32_t TimerRIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */ __I uint32_t TimerMIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */
__I uint32_t TimerMIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */ __IO uint32_t TimerBGLoad; /* Offset: 0x000 (R/W) Background Load Register */
__IO uint32_t TimerBGLoad; /* Offset: 0x000 (R/W) Background Load Register */
} CMSDK_DUALTIMER_SINGLE_TypeDef; } CMSDK_DUALTIMER_SINGLE_TypeDef;
#define CMSDK_DUALTIMER_LOAD_Pos 0 /* CMSDK_DUALTIMER LOAD: LOAD Position */ #define CMSDK_DUALTIMER_LOAD_Pos 0 /* CMSDK_DUALTIMER LOAD: LOAD Position */
@ -388,28 +383,27 @@ typedef struct
/*-------------------- General Purpose Input Output (GPIO) -------------------*/ /*-------------------- General Purpose Input Output (GPIO) -------------------*/
typedef struct typedef struct {
{ __IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */
__IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */ __IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */
__IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */ uint32_t RESERVED0[2];
uint32_t RESERVED0[2]; __IO uint32_t OUTENABLESET; /* Offset: 0x010 (R/W) Output Enable Set Register */
__IO uint32_t OUTENABLESET; /* Offset: 0x010 (R/W) Output Enable Set Register */ __IO uint32_t OUTENABLECLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */
__IO uint32_t OUTENABLECLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */ __IO uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */
__IO uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */ __IO uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */
__IO uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */ __IO uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */
__IO uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */ __IO uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */
__IO uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */ __IO uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */
__IO uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */ __IO uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */
__IO uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */ __IO uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */
__IO uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */ __IO uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */
__IO uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */ union {
union { __I uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */
__I uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */ __O uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */
__O uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */
}; };
uint32_t RESERVED1[241]; uint32_t RESERVED1[241];
__IO uint32_t LB_MASKED[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */ __IO uint32_t LB_MASKED[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */
__IO uint32_t UB_MASKED[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */ __IO uint32_t UB_MASKED[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */
} CMSDK_GPIO_TypeDef; } CMSDK_GPIO_TypeDef;
#define CMSDK_GPIO_DATA_Pos 0 /* CMSDK_GPIO DATA: DATA Position */ #define CMSDK_GPIO_DATA_Pos 0 /* CMSDK_GPIO DATA: DATA Position */
@ -462,13 +456,12 @@ typedef struct
/*------------- System Control (SYSCON) --------------------------------------*/ /*------------- System Control (SYSCON) --------------------------------------*/
typedef struct typedef struct {
{ __IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */
__IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */ __IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */
__IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */ __IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */
__IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */ __IO uint32_t EMICTRL; /* Offset: 0x00C (R/W) EMI Control Register */
__IO uint32_t EMICTRL; /* Offset: 0x00C (R/W) EMI Control Register */ __IO uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */
__IO uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */
} CMSDK_SYSCON_TypeDef; } CMSDK_SYSCON_TypeDef;
#define CMSDK_SYSCON_REMAP_Pos 0 #define CMSDK_SYSCON_REMAP_Pos 0
@ -503,26 +496,25 @@ typedef struct
/*------------- PL230 uDMA (PL230) --------------------------------------*/ /*------------- PL230 uDMA (PL230) --------------------------------------*/
typedef struct typedef struct {
{ __I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */
__I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */ __O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */
__O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */ __IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */
__IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */ __I uint32_t ALT_CTRL_BASE_PTR; /* Offset: 0x00C (R/ ) Channel Alternate Control Data Base Pointer Register */
__I uint32_t ALT_CTRL_BASE_PTR; /* Offset: 0x00C (R/ ) Channel Alternate Control Data Base Pointer Register */ __I uint32_t DMA_WAITONREQ_STATUS; /* Offset: 0x010 (R/ ) Channel Wait On Request Status Register */
__I uint32_t DMA_WAITONREQ_STATUS; /* Offset: 0x010 (R/ ) Channel Wait On Request Status Register */ __O uint32_t CHNL_SW_REQUEST; /* Offset: 0x014 ( /W) Channel Software Request Register */
__O uint32_t CHNL_SW_REQUEST; /* Offset: 0x014 ( /W) Channel Software Request Register */ __IO uint32_t CHNL_USEBURST_SET; /* Offset: 0x018 (R/W) Channel UseBurst Set Register */
__IO uint32_t CHNL_USEBURST_SET; /* Offset: 0x018 (R/W) Channel UseBurst Set Register */ __O uint32_t CHNL_USEBURST_CLR; /* Offset: 0x01C ( /W) Channel UseBurst Clear Register */
__O uint32_t CHNL_USEBURST_CLR; /* Offset: 0x01C ( /W) Channel UseBurst Clear Register */ __IO uint32_t CHNL_REQ_MASK_SET; /* Offset: 0x020 (R/W) Channel Request Mask Set Register */
__IO uint32_t CHNL_REQ_MASK_SET; /* Offset: 0x020 (R/W) Channel Request Mask Set Register */ __O uint32_t CHNL_REQ_MASK_CLR; /* Offset: 0x024 ( /W) Channel Request Mask Clear Register */
__O uint32_t CHNL_REQ_MASK_CLR; /* Offset: 0x024 ( /W) Channel Request Mask Clear Register */ __IO uint32_t CHNL_ENABLE_SET; /* Offset: 0x028 (R/W) Channel Enable Set Register */
__IO uint32_t CHNL_ENABLE_SET; /* Offset: 0x028 (R/W) Channel Enable Set Register */ __O uint32_t CHNL_ENABLE_CLR; /* Offset: 0x02C ( /W) Channel Enable Clear Register */
__O uint32_t CHNL_ENABLE_CLR; /* Offset: 0x02C ( /W) Channel Enable Clear Register */ __IO uint32_t CHNL_PRI_ALT_SET; /* Offset: 0x030 (R/W) Channel Primary-Alterante Set Register */
__IO uint32_t CHNL_PRI_ALT_SET; /* Offset: 0x030 (R/W) Channel Primary-Alterante Set Register */ __O uint32_t CHNL_PRI_ALT_CLR; /* Offset: 0x034 ( /W) Channel Primary-Alterante Clear Register */
__O uint32_t CHNL_PRI_ALT_CLR; /* Offset: 0x034 ( /W) Channel Primary-Alterante Clear Register */ __IO uint32_t CHNL_PRIORITY_SET; /* Offset: 0x038 (R/W) Channel Priority Set Register */
__IO uint32_t CHNL_PRIORITY_SET; /* Offset: 0x038 (R/W) Channel Priority Set Register */ __O uint32_t CHNL_PRIORITY_CLR; /* Offset: 0x03C ( /W) Channel Priority Clear Register */
__O uint32_t CHNL_PRIORITY_CLR; /* Offset: 0x03C ( /W) Channel Priority Clear Register */ uint32_t RESERVED0[3];
uint32_t RESERVED0[3]; __IO uint32_t ERR_CLR; /* Offset: 0x04C Bus Error Clear Register (R/W) */
__IO uint32_t ERR_CLR; /* Offset: 0x04C Bus Error Clear Register (R/W) */
} CMSDK_PL230_TypeDef; } CMSDK_PL230_TypeDef;
@ -599,21 +591,20 @@ typedef struct
/*------------------- Watchdog ----------------------------------------------*/ /*------------------- Watchdog ----------------------------------------------*/
typedef struct typedef struct {
{
__IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */ __IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */
__I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */ __I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */
__IO uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */ __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */
__O uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */ __O uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */
__I uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */ __I uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */
__I uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */ __I uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */
uint32_t RESERVED0[762]; uint32_t RESERVED0[762];
__IO uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */ __IO uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */
uint32_t RESERVED1[191]; uint32_t RESERVED1[191];
__IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */ __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */
__O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */ __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */
}CMSDK_WATCHDOG_TypeDef; } CMSDK_WATCHDOG_TypeDef;
#define CMSDK_Watchdog_LOAD_Pos 0 /* CMSDK_Watchdog LOAD: LOAD Position */ #define CMSDK_Watchdog_LOAD_Pos 0 /* CMSDK_Watchdog LOAD: LOAD Position */
#define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /* CMSDK_Watchdog LOAD: LOAD Mask */ #define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /* CMSDK_Watchdog LOAD: LOAD Mask */
@ -649,19 +640,19 @@ typedef struct
/* -------------------- End of section using anonymous unions ------------------- */ /* -------------------- End of section using anonymous unions ------------------- */
#if defined (__CC_ARM) #if defined (__CC_ARM)
#pragma pop #pragma pop
#elif defined (__ICCARM__) #elif defined (__ICCARM__)
/* leave anonymous unions enabled */ /* leave anonymous unions enabled */
#elif defined (__GNUC__) #elif defined (__GNUC__)
/* anonymous unions are enabled by default */ /* anonymous unions are enabled by default */
#elif defined (__TMS470__) #elif defined (__TMS470__)
/* anonymous unions are enabled by default */ /* anonymous unions are enabled by default */
#elif defined (__TASKING__) #elif defined (__TASKING__)
#pragma warning restore #pragma warning restore
#elif defined (__CSMC__) #elif defined (__CSMC__)
/* anonymous unions are enabled by default */ /* anonymous unions are enabled by default */
#else #else
#warning Not supported compiler type #warning Not supported compiler type
#endif #endif

560
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/SMM_MPS2.h
View File

@ -46,40 +46,39 @@
/* FPGA System Register declaration */ /* FPGA System Register declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct typedef struct {
{ __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections
__IO uint32_t LED; // Offset: 0x000 (R/W) LED connections // [31:2] : Reserved
// [31:2] : Reserved // [1:0] : LEDs
// [1:0] : LEDs uint32_t RESERVED1[1];
uint32_t RESERVED1[1]; __IO uint32_t BUTTON; // Offset: 0x008 (R/W) Buttons
__IO uint32_t BUTTON; // Offset: 0x008 (R/W) Buttons // [31:2] : Reserved
// [31:2] : Reserved // [1:0] : Buttons
// [1:0] : Buttons uint32_t RESERVED2[1];
uint32_t RESERVED2[1]; __IO uint32_t CLK1HZ; // Offset: 0x010 (R/W) 1Hz up counter
__IO uint32_t CLK1HZ; // Offset: 0x010 (R/W) 1Hz up counter __IO uint32_t CLK100HZ; // Offset: 0x014 (R/W) 100Hz up counter
__IO uint32_t CLK100HZ; // Offset: 0x014 (R/W) 100Hz up counter __IO uint32_t COUNTER; // Offset: 0x018 (R/W) Cycle Up Counter
__IO uint32_t COUNTER; // Offset: 0x018 (R/W) Cycle Up Counter // Increments when 32-bit prescale counter reach zero
// Increments when 32-bit prescale counter reach zero uint32_t RESERVED3[1];
uint32_t RESERVED3[1]; __IO uint32_t PRESCALE; // Offset: 0x020 (R/W) Prescaler
__IO uint32_t PRESCALE; // Offset: 0x020 (R/W) Prescaler // Bit[31:0] : reload value for prescale counter
// Bit[31:0] : reload value for prescale counter __IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter
__IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter // current value of the pre-scaler counter
// current value of the pre-scaler counter // The Cycle Up Counter increment when the prescale down counter reach 0
// The Cycle Up Counter increment when the prescale down counter reach 0 // The pre-scaler counter is reloaded with PRESCALE after reaching 0.
// The pre-scaler counter is reloaded with PRESCALE after reaching 0. uint32_t RESERVED4[9];
uint32_t RESERVED4[9]; __IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */
__IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */ // [31:10] : Reserved
// [31:10] : Reserved // [9] : SHIELD_1_SPI_nCS
// [9] : SHIELD_1_SPI_nCS // [8] : SHIELD_0_SPI_nCS
// [8] : SHIELD_0_SPI_nCS // [7] : ADC_SPI_nCS
// [7] : ADC_SPI_nCS // [6] : CLCD_BL_CTRL
// [6] : CLCD_BL_CTRL // [5] : CLCD_RD
// [5] : CLCD_RD // [4] : CLCD_RS
// [4] : CLCD_RS // [3] : CLCD_RESET
// [3] : CLCD_RESET // [2] : RESERVED
// [2] : RESERVED // [1] : SPI_nSS
// [1] : SPI_nSS // [0] : CLCD_CS
// [0] : CLCD_CS
} MPS2_FPGAIO_TypeDef; } MPS2_FPGAIO_TypeDef;
// MISC register bit definitions // MISC register bit definitions
@ -107,58 +106,57 @@ typedef struct
/* SCC Register declaration */ /* SCC Register declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct // typedef struct { //
{ __IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT
__IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT // [31:1] : Reserved
// [31:1] : Reserved // [0] 1 : REMAP BlockRam to ZBT
// [0] 1 : REMAP BlockRam to ZBT __IO uint32_t LEDS; // Offset: 0x004 (R/W) Controls the MCC user LEDs
__IO uint32_t LEDS; // Offset: 0x004 (R/W) Controls the MCC user LEDs // [31:8] : Reserved
// [31:8] : Reserved // [7:0] : MCC LEDs
// [7:0] : MCC LEDs uint32_t RESERVED0[1];
uint32_t RESERVED0[1]; __I uint32_t SWITCHES; // Offset: 0x00C (R/ ) Denotes the state of the MCC user switches
__I uint32_t SWITCHES; // Offset: 0x00C (R/ ) Denotes the state of the MCC user switches // [31:8] : Reserved
// [31:8] : Reserved // [7:0] : These bits indicate state of the MCC switches
// [7:0] : These bits indicate state of the MCC switches __I uint32_t CFG_REG4; // Offset: 0x010 (R/ ) Denotes the board revision
__I uint32_t CFG_REG4; // Offset: 0x010 (R/ ) Denotes the board revision // [31:4] : Reserved
// [31:4] : Reserved // [3:0] : Used by the MCC to pass PCB revision. 0 = A 1 = B
// [3:0] : Used by the MCC to pass PCB revision. 0 = A 1 = B uint32_t RESERVED1[35];
uint32_t RESERVED1[35]; __IO uint32_t SYS_CFGDATA_RTN; // Offset: 0x0A0 (R/W) User data register
__IO uint32_t SYS_CFGDATA_RTN; // Offset: 0x0A0 (R/W) User data register // [31:0] : Data
// [31:0] : Data __IO uint32_t SYS_CFGDATA_OUT; // Offset: 0x0A4 (R/W) User data register
__IO uint32_t SYS_CFGDATA_OUT; // Offset: 0x0A4 (R/W) User data register // [31:0] : Data
// [31:0] : Data __IO uint32_t SYS_CFGCTRL; // Offset: 0x0A8 (R/W) Control register
__IO uint32_t SYS_CFGCTRL; // Offset: 0x0A8 (R/W) Control register // [31] : Start (generates interrupt on write to this bit)
// [31] : Start (generates interrupt on write to this bit) // [30] : R/W access
// [30] : R/W access // [29:26] : Reserved
// [29:26] : Reserved // [25:20] : Function value
// [25:20] : Function value // [19:12] : Reserved
// [19:12] : Reserved // [11:0] : Device (value of 0/1/2 for supported clocks)
// [11:0] : Device (value of 0/1/2 for supported clocks) __IO uint32_t SYS_CFGSTAT; // Offset: 0x0AC (R/W) Contains status information
__IO uint32_t SYS_CFGSTAT; // Offset: 0x0AC (R/W) Contains status information // [31:2] : Reserved
// [31:2] : Reserved // [1] : Error
// [1] : Error // [0] : Complete
// [0] : Complete __IO uint32_t RESERVED2[20];
__IO uint32_t RESERVED2[20]; __IO uint32_t SCC_DLL; // Offset: 0x100 (R/W) DLL Lock Register
__IO uint32_t SCC_DLL; // Offset: 0x100 (R/W) DLL Lock Register // [31:24] : DLL LOCK MASK[7:0] - Indicate if the DLL locked is masked
// [31:24] : DLL LOCK MASK[7:0] - Indicate if the DLL locked is masked // [23:16] : DLL LOCK MASK[7:0] - Indicate if the DLLs are locked or unlocked
// [23:16] : DLL LOCK MASK[7:0] - Indicate if the DLLs are locked or unlocked // [15:1] : Reserved
// [15:1] : Reserved // [0] : This bit indicates if all enabled DLLs are locked
// [0] : This bit indicates if all enabled DLLs are locked uint32_t RESERVED3[957];
uint32_t RESERVED3[957]; __I uint32_t SCC_AID; // Offset: 0xFF8 (R/ ) SCC AID Register
__I uint32_t SCC_AID; // Offset: 0xFF8 (R/ ) SCC AID Register // [31:24] : FPGA build number
// [31:24] : FPGA build number // [23:20] : V2M-MPS2 target board revision (A = 0, B = 1)
// [23:20] : V2M-MPS2 target board revision (A = 0, B = 1) // [19:11] : Reserved
// [19:11] : Reserved // [10] : if “1” SCC_SW register has been implemented
// [10] : if “1” SCC_SW register has been implemented // [9] : if “1” SCC_LED register has been implemented
// [9] : if “1” SCC_LED register has been implemented // [8] : if “1” DLL lock register has been implemented
// [8] : if “1” DLL lock register has been implemented // [7:0] : number of SCC configuration register
// [7:0] : number of SCC configuration register __I uint32_t SCC_ID; // Offset: 0xFFC (R/ ) Contains information about the FPGA image
__I uint32_t SCC_ID; // Offset: 0xFFC (R/ ) Contains information about the FPGA image // [31:24] : Implementer ID: 0x41 = ARM
// [31:24] : Implementer ID: 0x41 = ARM // [23:20] : Application note IP variant number
// [23:20] : Application note IP variant number // [19:16] : IP Architecture: 0x4 =AHB
// [19:16] : IP Architecture: 0x4 =AHB // [15:4] : Primary part number: 386 = AN386
// [15:4] : Primary part number: 386 = AN386 // [3:0] : Application note IP revision number
// [3:0] : Application note IP revision number
} MPS2_SCC_TypeDef; } MPS2_SCC_TypeDef;
@ -166,60 +164,59 @@ typedef struct //
/* SSP Peripheral declaration */ /* SSP Peripheral declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf typedef struct { // Document DDI0194G_ssp_pl022_r1p3_trm.pdf
{ __IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0
__IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0 // [31:16] : Reserved
// [31:16] : Reserved // [15:8] : Serial clock rate
// [15:8] : Serial clock rate // [7] : SSPCLKOUT phase, applicable to Motorola SPI frame format only
// [7] : SSPCLKOUT phase, applicable to Motorola SPI frame format only // [6] : SSPCLKOUT polarity, applicable to Motorola SPI frame format only
// [6] : SSPCLKOUT polarity, applicable to Motorola SPI frame format only // [5:4] : Frame format
// [5:4] : Frame format // [3:0] : Data Size Select
// [3:0] : Data Size Select __IO uint32_t CR1; // Offset: 0x004 (R/W) Control register 1
__IO uint32_t CR1; // Offset: 0x004 (R/W) Control register 1 // [31:4] : Reserved
// [31:4] : Reserved // [3] : Slave-mode output disable
// [3] : Slave-mode output disable // [2] : Master or slave mode select
// [2] : Master or slave mode select // [1] : Synchronous serial port enable
// [1] : Synchronous serial port enable // [0] : Loop back mode
// [0] : Loop back mode __IO uint32_t DR; // Offset: 0x008 (R/W) Data register
__IO uint32_t DR; // Offset: 0x008 (R/W) Data register // [31:16] : Reserved
// [31:16] : Reserved // [15:0] : Transmit/Receive FIFO
// [15:0] : Transmit/Receive FIFO __I uint32_t SR; // Offset: 0x00C (R/ ) Status register
__I uint32_t SR; // Offset: 0x00C (R/ ) Status register // [31:5] : Reserved
// [31:5] : Reserved // [4] : PrimeCell SSP busy flag
// [4] : PrimeCell SSP busy flag // [3] : Receive FIFO full
// [3] : Receive FIFO full // [2] : Receive FIFO not empty
// [2] : Receive FIFO not empty // [1] : Transmit FIFO not full
// [1] : Transmit FIFO not full // [0] : Transmit FIFO empty
// [0] : Transmit FIFO empty __IO uint32_t CPSR; // Offset: 0x010 (R/W) Clock prescale register
__IO uint32_t CPSR; // Offset: 0x010 (R/W) Clock prescale register // [31:8] : Reserved
// [31:8] : Reserved // [8:0] : Clock prescale divisor
// [8:0] : Clock prescale divisor __IO uint32_t IMSC; // Offset: 0x014 (R/W) Interrupt mask set or clear register
__IO uint32_t IMSC; // Offset: 0x014 (R/W) Interrupt mask set or clear register // [31:4] : Reserved
// [31:4] : Reserved // [3] : Transmit FIFO interrupt mask
// [3] : Transmit FIFO interrupt mask // [2] : Receive FIFO interrupt mask
// [2] : Receive FIFO interrupt mask // [1] : Receive timeout interrupt mask
// [1] : Receive timeout interrupt mask // [0] : Receive overrun interrupt mask
// [0] : Receive overrun interrupt mask __I uint32_t RIS; // Offset: 0x018 (R/ ) Raw interrupt status register
__I uint32_t RIS; // Offset: 0x018 (R/ ) Raw interrupt status register // [31:4] : Reserved
// [31:4] : Reserved // [3] : raw interrupt state, prior to masking, of the SSPTXINTR interrupt
// [3] : raw interrupt state, prior to masking, of the SSPTXINTR interrupt // [2] : raw interrupt state, prior to masking, of the SSPRXINTR interrupt
// [2] : raw interrupt state, prior to masking, of the SSPRXINTR interrupt // [1] : raw interrupt state, prior to masking, of the SSPRTINTR interrupt
// [1] : raw interrupt state, prior to masking, of the SSPRTINTR interrupt // [0] : raw interrupt state, prior to masking, of the SSPRORINTR interrupt
// [0] : raw interrupt state, prior to masking, of the SSPRORINTR interrupt __I uint32_t MIS; // Offset: 0x01C (R/ ) Masked interrupt status register
__I uint32_t MIS; // Offset: 0x01C (R/ ) Masked interrupt status register // [31:4] : Reserved
// [31:4] : Reserved // [3] : transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt
// [3] : transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt // [2] : receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt
// [2] : receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt // [1] : receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt
// [1] : receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt // [0] : receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt
// [0] : receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt __O uint32_t ICR; // Offset: 0x020 ( /W) Interrupt clear register
__O uint32_t ICR; // Offset: 0x020 ( /W) Interrupt clear register // [31:2] : Reserved
// [31:2] : Reserved // [1] : Clears the SSPRTINTR interrupt
// [1] : Clears the SSPRTINTR interrupt // [0] : Clears the SSPRORINTR interrupt
// [0] : Clears the SSPRORINTR interrupt __IO uint32_t DMACR; // Offset: 0x024 (R/W) DMA control register
__IO uint32_t DMACR; // Offset: 0x024 (R/W) DMA control register // [31:2] : Reserved
// [31:2] : Reserved // [1] : Transmit DMA Enable
// [1] : Transmit DMA Enable // [0] : Receive DMA Enable
// [0] : Receive DMA Enable
} MPS2_SSP_TypeDef; } MPS2_SSP_TypeDef;
@ -314,13 +311,12 @@ typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf
/* Audio and Touch Screen (I2C) Peripheral declaration */ /* Audio and Touch Screen (I2C) Peripheral declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct typedef struct {
{ union {
union { __O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W)
__O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W) __I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ )
__I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ ) };
}; __O uint32_t CONTROLC; // Offset: 0x004 CONTROL Clear Register ( /W)
__O uint32_t CONTROLC; // Offset: 0x004 CONTROL Clear Register ( /W)
} MPS2_I2C_TypeDef; } MPS2_I2C_TypeDef;
#define SDA 1 << 1 #define SDA 1 << 1
@ -331,107 +327,106 @@ typedef struct
/* Audio I2S Peripheral declaration */ /* Audio I2S Peripheral declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct typedef struct {
{ /*!< Offset: 0x000 CONTROL Register (R/W) */
/*!< Offset: 0x000 CONTROL Register (R/W) */ __IO uint32_t CONTROL; // <h> CONTROL </h>
__IO uint32_t CONTROL; // <h> CONTROL </h> // <o.0> TX Enable
// <o.0> TX Enable // <0=> TX disabled
// <0=> TX disabled // <1=> TX enabled
// <1=> TX enabled // <o.1> TX IRQ Enable
// <o.1> TX IRQ Enable // <0=> TX IRQ disabled
// <0=> TX IRQ disabled // <1=> TX IRQ enabled
// <1=> TX IRQ enabled // <o.2> RX Enable
// <o.2> RX Enable // <0=> RX disabled
// <0=> RX disabled // <1=> RX enabled
// <1=> RX enabled // <o.3> RX IRQ Enable
// <o.3> RX IRQ Enable // <0=> RX IRQ disabled
// <0=> RX IRQ disabled // <1=> RX IRQ enabled
// <1=> RX IRQ enabled // <o.10..8> TX Buffer Water Level
// <o.10..8> TX Buffer Water Level // <0=> / IRQ triggers when any space available
// <0=> / IRQ triggers when any space available // <1=> / IRQ triggers when more than 1 space available
// <1=> / IRQ triggers when more than 1 space available // <2=> / IRQ triggers when more than 2 space available
// <2=> / IRQ triggers when more than 2 space available // <3=> / IRQ triggers when more than 3 space available
// <3=> / IRQ triggers when more than 3 space available // <4=> Undefined!
// <4=> Undefined! // <5=> Undefined!
// <5=> Undefined! // <6=> Undefined!
// <6=> Undefined! // <7=> Undefined!
// <7=> Undefined! // <o.14..12> RX Buffer Water Level
// <o.14..12> RX Buffer Water Level // <0=> Undefined!
// <0=> Undefined! // <1=> / IRQ triggers when less than 1 space available
// <1=> / IRQ triggers when less than 1 space available // <2=> / IRQ triggers when less than 2 space available
// <2=> / IRQ triggers when less than 2 space available // <3=> / IRQ triggers when less than 3 space available
// <3=> / IRQ triggers when less than 3 space available // <4=> / IRQ triggers when less than 4 space available
// <4=> / IRQ triggers when less than 4 space available // <5=> Undefined!
// <5=> Undefined! // <6=> Undefined!
// <6=> Undefined! // <7=> Undefined!
// <7=> Undefined! // <o.16> FIFO reset
// <o.16> FIFO reset // <0=> Normal operation
// <0=> Normal operation // <1=> FIFO reset
// <1=> FIFO reset // <o.17> Audio Codec reset
// <o.17> Audio Codec reset // <0=> Normal operation
// <0=> Normal operation // <1=> Assert audio Codec reset
// <1=> Assert audio Codec reset /*!< Offset: 0x004 STATUS Register (R/ ) */
/*!< Offset: 0x004 STATUS Register (R/ ) */ __I uint32_t STATUS; // <h> STATUS </h>
__I uint32_t STATUS; // <h> STATUS </h> // <o.0> TX Buffer alert
// <o.0> TX Buffer alert // <0=> TX buffer don't need service yet
// <0=> TX buffer don't need service yet // <1=> TX buffer need service
// <1=> TX buffer need service // <o.1> RX Buffer alert
// <o.1> RX Buffer alert // <0=> RX buffer don't need service yet
// <0=> RX buffer don't need service yet // <1=> RX buffer need service
// <1=> RX buffer need service // <o.2> TX Buffer Empty
// <o.2> TX Buffer Empty // <0=> TX buffer have data
// <0=> TX buffer have data // <1=> TX buffer empty
// <1=> TX buffer empty // <o.3> TX Buffer Full
// <o.3> TX Buffer Full // <0=> TX buffer not full
// <0=> TX buffer not full // <1=> TX buffer full
// <1=> TX buffer full // <o.4> RX Buffer Empty
// <o.4> RX Buffer Empty // <0=> RX buffer have data
// <0=> RX buffer have data // <1=> RX buffer empty
// <1=> RX buffer empty // <o.5> RX Buffer Full
// <o.5> RX Buffer Full // <0=> RX buffer not full
// <0=> RX buffer not full // <1=> RX buffer full
// <1=> RX buffer full union {
union { /*!< Offset: 0x008 Error Status Register (R/ ) */
/*!< Offset: 0x008 Error Status Register (R/ ) */ __I uint32_t ERROR; // <h> ERROR </h>
__I uint32_t ERROR; // <h> ERROR </h> // <o.0> TX error
// <o.0> TX error // <0=> Okay
// <0=> Okay // <1=> TX overrun/underrun
// <1=> TX overrun/underrun // <o.1> RX error
// <o.1> RX error // <0=> Okay
// <0=> Okay // <1=> RX overrun/underrun
// <1=> RX overrun/underrun /*!< Offset: 0x008 Error Clear Register ( /W) */
/*!< Offset: 0x008 Error Clear Register ( /W) */ __O uint32_t ERRORCLR; // <h> ERRORCLR </h>
__O uint32_t ERRORCLR; // <h> ERRORCLR </h> // <o.0> TX error
// <o.0> TX error // <0=> Okay
// <0=> Okay // <1=> Clear TX error
// <1=> Clear TX error // <o.1> RX error
// <o.1> RX error // <0=> Okay
// <0=> Okay // <1=> Clear RX error
// <1=> Clear RX error
}; };
/*!< Offset: 0x00C Divide ratio Register (R/W) */ /*!< Offset: 0x00C Divide ratio Register (R/W) */
__IO uint32_t DIVIDE; // <h> Divide ratio for Left/Right clock </h> __IO uint32_t DIVIDE; // <h> Divide ratio for Left/Right clock </h>
// <o.9..0> TX error (default 0x80) // <o.9..0> TX error (default 0x80)
/*!< Offset: 0x010 Transmit Buffer ( /W) */ /*!< Offset: 0x010 Transmit Buffer ( /W) */
__O uint32_t TXBUF; // <h> Transmit buffer </h> __O uint32_t TXBUF; // <h> Transmit buffer </h>
// <o.15..0> Right channel // <o.15..0> Right channel
// <o.31..16> Left channel // <o.31..16> Left channel
/*!< Offset: 0x014 Receive Buffer (R/ ) */ /*!< Offset: 0x014 Receive Buffer (R/ ) */
__I uint32_t RXBUF; // <h> Receive buffer </h> __I uint32_t RXBUF; // <h> Receive buffer </h>
// <o.15..0> Right channel // <o.15..0> Right channel
// <o.31..16> Left channel // <o.31..16> Left channel
uint32_t RESERVED1[186]; uint32_t RESERVED1[186];
__IO uint32_t ITCR; // <h> Integration Test Control Register </h> __IO uint32_t ITCR; // <h> Integration Test Control Register </h>
// <o.0> ITEN // <o.0> ITEN
// <0=> Normal operation // <0=> Normal operation
// <1=> Integration Test mode enable // <1=> Integration Test mode enable
__O uint32_t ITIP1; // <h> Integration Test Input Register 1</h> __O uint32_t ITIP1; // <h> Integration Test Input Register 1</h>
// <o.0> SDIN // <o.0> SDIN
__O uint32_t ITOP1; // <h> Integration Test Output Register 1</h> __O uint32_t ITOP1; // <h> Integration Test Output Register 1</h>
// <o.0> SDOUT // <o.0> SDOUT
// <o.1> SCLK // <o.1> SCLK
// <o.2> LRCK // <o.2> LRCK
// <o.3> IRQOUT // <o.3> IRQOUT
} MPS2_I2S_TypeDef; } MPS2_I2S_TypeDef;
#define I2S_CONTROL_TXEN_Pos 0 #define I2S_CONTROL_TXEN_Pos 0
@ -486,44 +481,43 @@ typedef struct
/* SMSC9220 Register Definitions */ /* SMSC9220 Register Definitions */
/******************************************************************************/ /******************************************************************************/
typedef struct // SMSC LAN9220 typedef struct { // SMSC LAN9220
{ __I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0)
__I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0) uint32_t RESERVED1[0x7];
uint32_t RESERVED1[0x7]; __O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20)
__O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20) uint32_t RESERVED2[0x7];
uint32_t RESERVED2[0x7];
__I uint32_t RX_STAT_PORT; // Receive FIFO status port (offset 0x40) __I uint32_t RX_STAT_PORT; // Receive FIFO status port (offset 0x40)
__I uint32_t RX_STAT_PEEK; // Receive FIFO status peek (offset 0x44) __I uint32_t RX_STAT_PEEK; // Receive FIFO status peek (offset 0x44)
__I uint32_t TX_STAT_PORT; // Transmit FIFO status port (offset 0x48) __I uint32_t TX_STAT_PORT; // Transmit FIFO status port (offset 0x48)
__I uint32_t TX_STAT_PEEK; // Transmit FIFO status peek (offset 0x4C) __I uint32_t TX_STAT_PEEK; // Transmit FIFO status peek (offset 0x4C)
__I uint32_t ID_REV; // Chip ID and Revision (offset 0x50) __I uint32_t ID_REV; // Chip ID and Revision (offset 0x50)
__IO uint32_t IRQ_CFG; // Main Interrupt Configuration (offset 0x54) __IO uint32_t IRQ_CFG; // Main Interrupt Configuration (offset 0x54)
__IO uint32_t INT_STS; // Interrupt Status (offset 0x58) __IO uint32_t INT_STS; // Interrupt Status (offset 0x58)
__IO uint32_t INT_EN; // Interrupt Enable Register (offset 0x5C) __IO uint32_t INT_EN; // Interrupt Enable Register (offset 0x5C)
uint32_t RESERVED3; // Reserved for future use (offset 0x60) uint32_t RESERVED3; // Reserved for future use (offset 0x60)
__I uint32_t BYTE_TEST; // Read-only byte order testing register 87654321h (offset 0x64) __I uint32_t BYTE_TEST; // Read-only byte order testing register 87654321h (offset 0x64)
__IO uint32_t FIFO_INT; // FIFO Level Interrupts (offset 0x68) __IO uint32_t FIFO_INT; // FIFO Level Interrupts (offset 0x68)
__IO uint32_t RX_CFG; // Receive Configuration (offset 0x6C) __IO uint32_t RX_CFG; // Receive Configuration (offset 0x6C)
__IO uint32_t TX_CFG; // Transmit Configuration (offset 0x70) __IO uint32_t TX_CFG; // Transmit Configuration (offset 0x70)
__IO uint32_t HW_CFG; // Hardware Configuration (offset 0x74) __IO uint32_t HW_CFG; // Hardware Configuration (offset 0x74)
__IO uint32_t RX_DP_CTL; // RX Datapath Control (offset 0x78) __IO uint32_t RX_DP_CTL; // RX Datapath Control (offset 0x78)
__I uint32_t RX_FIFO_INF; // Receive FIFO Information (offset 0x7C) __I uint32_t RX_FIFO_INF; // Receive FIFO Information (offset 0x7C)
__I uint32_t TX_FIFO_INF; // Transmit FIFO Information (offset 0x80) __I uint32_t TX_FIFO_INF; // Transmit FIFO Information (offset 0x80)
__IO uint32_t PMT_CTRL; // Power Management Control (offset 0x84) __IO uint32_t PMT_CTRL; // Power Management Control (offset 0x84)
__IO uint32_t GPIO_CFG; // General Purpose IO Configuration (offset 0x88) __IO uint32_t GPIO_CFG; // General Purpose IO Configuration (offset 0x88)
__IO uint32_t GPT_CFG; // General Purpose Timer Configuration (offset 0x8C) __IO uint32_t GPT_CFG; // General Purpose Timer Configuration (offset 0x8C)
__I uint32_t GPT_CNT; // General Purpose Timer Count (offset 0x90) __I uint32_t GPT_CNT; // General Purpose Timer Count (offset 0x90)
uint32_t RESERVED4; // Reserved for future use (offset 0x94) uint32_t RESERVED4; // Reserved for future use (offset 0x94)
__IO uint32_t ENDIAN; // WORD SWAP Register (offset 0x98) __IO uint32_t ENDIAN; // WORD SWAP Register (offset 0x98)
__I uint32_t FREE_RUN; // Free Run Counter (offset 0x9C) __I uint32_t FREE_RUN; // Free Run Counter (offset 0x9C)
__I uint32_t RX_DROP; // RX Dropped Frames Counter (offset 0xA0) __I uint32_t RX_DROP; // RX Dropped Frames Counter (offset 0xA0)
__IO uint32_t MAC_CSR_CMD; // MAC CSR Synchronizer Command (offset 0xA4) __IO uint32_t MAC_CSR_CMD; // MAC CSR Synchronizer Command (offset 0xA4)
__IO uint32_t MAC_CSR_DATA; // MAC CSR Synchronizer Data (offset 0xA8) __IO uint32_t MAC_CSR_DATA; // MAC CSR Synchronizer Data (offset 0xA8)
__IO uint32_t AFC_CFG; // Automatic Flow Control Configuration (offset 0xAC) __IO uint32_t AFC_CFG; // Automatic Flow Control Configuration (offset 0xAC)
__IO uint32_t E2P_CMD; // EEPROM Command (offset 0xB0) __IO uint32_t E2P_CMD; // EEPROM Command (offset 0xB0)
__IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4) __IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4)
} SMSC9220_TypeDef; } SMSC9220_TypeDef;

12
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/peripherallink.h
View File

@ -37,17 +37,17 @@
#define __DEVICE_H #define __DEVICE_H
#if defined CMSDK_CM0 #if defined CMSDK_CM0
#include "CMSDK_CM0.h" /* device specific header file */ #include "CMSDK_CM0.h" /* device specific header file */
#elif defined CMSDK_CM0plus #elif defined CMSDK_CM0plus
#include "CMSDK_CM0plus.h" /* device specific header file */ #include "CMSDK_CM0plus.h" /* device specific header file */
#elif defined CMSDK_CM3 #elif defined CMSDK_CM3
#include "CMSDK_CM3.h" /* device specific header file */ #include "CMSDK_CM3.h" /* device specific header file */
#elif defined CMSDK_CM4 #elif defined CMSDK_CM4
#include "CMSDK_CM4.h" /* device specific header file */ #include "CMSDK_CM4.h" /* device specific header file */
#elif defined CMSDK_CM7 #elif defined CMSDK_CM7
#include "CMSDK_CM7.h" /* device specific header file */ #include "CMSDK_CM7.h" /* device specific header file */
#else #else
#warning "no appropriate header file found!" #warning "no appropriate header file found!"
#endif #endif
#endif /* __DEVICE_H */ #endif /* __DEVICE_H */

30
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/system_CMSDK_CM7.c
View File

@ -37,13 +37,13 @@
#if defined (CMSDK_CM7) #if defined (CMSDK_CM7)
#include "CMSDK_CM7.h" #include "CMSDK_CM7.h"
#elif defined (CMSDK_CM7_SP) #elif defined (CMSDK_CM7_SP)
#include "CMSDK_CM7_SP.h" #include "CMSDK_CM7_SP.h"
#elif defined (CMSDK_CM7_DP) #elif defined (CMSDK_CM7_DP)
#include "CMSDK_CM7_DP.h" #include "CMSDK_CM7_DP.h"
#else #else
#error device not specified! #error device not specified!
#endif #endif
/*---------------------------------------------------------------------------- /*----------------------------------------------------------------------------
@ -72,10 +72,10 @@ uint32_t SystemCoreClock = __SYSTEM_CLOCK;/* System Core Clock Frequency */
* @brief Updates the SystemCoreClock with current core Clock * @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers. * retrieved from cpu registers.
*/ */
void SystemCoreClockUpdate (void) void SystemCoreClockUpdate(void)
{ {
SystemCoreClock = __SYSTEM_CLOCK; SystemCoreClock = __SYSTEM_CLOCK;
} }
@ -88,17 +88,17 @@ void SystemCoreClockUpdate (void)
* @brief Setup the microcontroller system. * @brief Setup the microcontroller system.
* Initialize the System. * Initialize the System.
*/ */
void SystemInit (void) void SystemInit(void)
{ {
#if (__FPU_USED == 1) #if (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ SCB->CPACR |= ((3UL << 10 * 2) | /* set CP10 Full Access */
(3UL << 11*2) ); /* set CP11 Full Access */ (3UL << 11 * 2)); /* set CP11 Full Access */
#endif
#ifdef UNALIGNED_SUPPORT_DISABLE
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
#endif #endif
SystemCoreClock = __SYSTEM_CLOCK; #ifdef UNALIGNED_SUPPORT_DISABLE
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
#endif
SystemCoreClock = __SYSTEM_CLOCK;
} }

4
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/system_CMSDK_CM7.h
View File

@ -56,7 +56,7 @@ extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */
* @brief Setup the microcontroller system. * @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable. * Initialize the System and update the SystemCoreClock variable.
*/ */
extern void SystemInit (void); extern void SystemInit(void);
/** /**
* Update SystemCoreClock variable * Update SystemCoreClock variable
@ -67,7 +67,7 @@ extern void SystemInit (void);
* @brief Updates the SystemCoreClock with current core Clock * @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers. * retrieved from cpu registers.
*/ */
extern void SystemCoreClockUpdate (void); extern void SystemCoreClockUpdate(void);
#ifdef __cplusplus #ifdef __cplusplus
} }

70
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/analogin_api.c
View File

@ -38,73 +38,77 @@ static const PinMap PinMap_ADC[] = {
}; };
static const PinMap PinMap_SPI_SCLK[] = { static const PinMap PinMap_SPI_SCLK[] = {
{ADC_SCLK , SPI_3, 0}, {ADC_SCLK, SPI_3, 0},
{NC , NC , 0} {NC, NC, 0}
}; };
static const PinMap PinMap_SPI_MOSI[] = { static const PinMap PinMap_SPI_MOSI[] = {
{ADC_MOSI, SPI_3, 0}, {ADC_MOSI, SPI_3, 0},
{NC , NC , 0} {NC, NC, 0}
}; };
static const PinMap PinMap_SPI_MISO[] = { static const PinMap PinMap_SPI_MISO[] = {
{ADC_MISO, SPI_3, 0}, {ADC_MISO, SPI_3, 0},
{NC , NC , 0} {NC, NC, 0}
}; };
static const PinMap PinMap_SPI_SSEL[] = { static const PinMap PinMap_SPI_SSEL[] = {
{ADC_SSEL, SPI_3, 0}, {ADC_SSEL, SPI_3, 0},
{NC , NC , 0} {NC, NC, 0}
}; };
#define ADC_RANGE ADC_12BIT_RANGE #define ADC_RANGE ADC_12BIT_RANGE
int analog_spi_inited = 0; int analog_spi_inited = 0;
void analogin_init(analogin_t *obj, PinName pin) { void analogin_init(analogin_t *obj, PinName pin)
{
obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
MBED_ASSERT(obj->adc != (ADCName)NC); MBED_ASSERT(obj->adc != (ADCName)NC);
obj->pin = pin; obj->pin = pin;
obj->pin_number = pin-600; obj->pin_number = pin - 600;
obj->address = (0x0000 | (pin-600)); obj->address = (0x0000 | (pin - 600));
SPIName adc_mosi = (SPIName)pinmap_peripheral(ADC_MOSI, PinMap_SPI_MOSI); SPIName adc_mosi = (SPIName)pinmap_peripheral(ADC_MOSI, PinMap_SPI_MOSI);
SPIName adc_miso = (SPIName)pinmap_peripheral(ADC_MISO, PinMap_SPI_MISO); SPIName adc_miso = (SPIName)pinmap_peripheral(ADC_MISO, PinMap_SPI_MISO);
SPIName adc_sclk = (SPIName)pinmap_peripheral(ADC_SCLK, PinMap_SPI_SCLK); SPIName adc_sclk = (SPIName)pinmap_peripheral(ADC_SCLK, PinMap_SPI_SCLK);
SPIName adc_ssel = (SPIName)pinmap_peripheral(ADC_SSEL, PinMap_SPI_SSEL); SPIName adc_ssel = (SPIName)pinmap_peripheral(ADC_SSEL, PinMap_SPI_SSEL);
SPIName adc_data = (SPIName)pinmap_merge(adc_mosi, adc_miso); SPIName adc_data = (SPIName)pinmap_merge(adc_mosi, adc_miso);
SPIName adc_cntl = (SPIName)pinmap_merge(adc_sclk, adc_ssel); SPIName adc_cntl = (SPIName)pinmap_merge(adc_sclk, adc_ssel);
obj->adc_spi = (MPS2_SSP_TypeDef*)pinmap_merge(adc_data, adc_cntl); obj->adc_spi = (MPS2_SSP_TypeDef *)pinmap_merge(adc_data, adc_cntl);
if(analog_spi_inited == 0){ if (analog_spi_inited == 0) {
obj->adc_spi->CR1 = 0; obj->adc_spi->CR1 = 0;
obj->adc_spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_16; obj->adc_spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_16;
obj->adc_spi->CPSR = SSP_CPSR_DFLT; obj->adc_spi->CPSR = SSP_CPSR_DFLT;
obj->adc_spi->IMSC = 0x8; obj->adc_spi->IMSC = 0x8;
obj->adc_spi->DMACR = 0; obj->adc_spi->DMACR = 0;
obj->adc_spi->CR1 = SSP_CR1_SSE_Msk; obj->adc_spi->CR1 = SSP_CR1_SSE_Msk;
obj->adc_spi->ICR = 0x3; obj->adc_spi->ICR = 0x3;
analog_spi_inited = 1; analog_spi_inited = 1;
} }
pinmap_pinout(ADC_MOSI, PinMap_SPI_MOSI); pinmap_pinout(ADC_MOSI, PinMap_SPI_MOSI);
pinmap_pinout(ADC_MISO, PinMap_SPI_MISO); pinmap_pinout(ADC_MISO, PinMap_SPI_MISO);
pinmap_pinout(ADC_SCLK, PinMap_SPI_SCLK); pinmap_pinout(ADC_SCLK, PinMap_SPI_SCLK);
pinmap_pinout(ADC_SSEL, PinMap_SPI_SSEL); pinmap_pinout(ADC_SSEL, PinMap_SPI_SSEL);
pinmap_pinout(pin, PinMap_ADC); pinmap_pinout(pin, PinMap_ADC);
} }
static inline uint32_t adc_read(analogin_t *obj) { static inline uint32_t adc_read(analogin_t *obj)
{
return 0; return 0;
} }
float analogin_read(analogin_t *obj) { float analogin_read(analogin_t *obj)
{
uint32_t value = adc_read(obj); uint32_t value = adc_read(obj);
return 0; return 0;
} }
uint16_t analogin_read_u16(analogin_t *obj) { uint16_t analogin_read_u16(analogin_t *obj)
{
return 0; return 0;
} }

2
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/device.h
View File

@ -17,7 +17,7 @@
// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. // The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
// Check the 'features' section of the target description in 'targets.json' for more details. // Check the 'features' section of the target description in 'targets.json' for more details.
#ifndef MBED_DEVICE_H #ifndef MBED_DEVICE_H
#define MBED_DEVICE_H #define MBED_DEVICE_H

26
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/ethernet_api.c
View File

@ -38,14 +38,14 @@
*----------------------------------------------------------------------------*/ *----------------------------------------------------------------------------*/
int ethernet_init() int ethernet_init()
{ {
int error; int error;
error = 0; error = 0;
if(smsc9220_check_id()) { if (smsc9220_check_id()) {
error = TRUE; error = TRUE;
} }
if(smsc9220_soft_reset()) { if (smsc9220_soft_reset()) {
error = TRUE; error = TRUE;
} }
@ -55,7 +55,7 @@ int ethernet_init()
// threshold to defaults specified. // threshold to defaults specified.
SMSC9220->AFC_CFG = 0x006E3740; SMSC9220->AFC_CFG = 0x006E3740;
if(smsc9220_wait_eeprom()) { if (smsc9220_wait_eeprom()) {
error = TRUE; error = TRUE;
} }
@ -66,11 +66,11 @@ int ethernet_init()
/* Configure MAC addresses here if needed. */ /* Configure MAC addresses here if needed. */
if(smsc9220_check_phy()) { if (smsc9220_check_phy()) {
error = TRUE; error = TRUE;
} }
if(smsc9220_reset_phy()) { if (smsc9220_reset_phy()) {
error = TRUE; error = TRUE;
return error; return error;
} }
@ -81,7 +81,7 @@ int ethernet_init()
unsigned short phyreset; unsigned short phyreset;
phyreset = 0; phyreset = 0;
smsc9220_phy_regread(SMSC9220_PHY_BCONTROL, &phyreset); smsc9220_phy_regread(SMSC9220_PHY_BCONTROL, &phyreset);
if(phyreset & (1 << 15)) { if (phyreset & (1 << 15)) {
error = TRUE; error = TRUE;
return error; return error;
} }
@ -93,7 +93,7 @@ int ethernet_init()
/* Begin to establish link */ /* Begin to establish link */
smsc9220_establish_link(); // bit [12] of BCONTROL seems self-clearing. smsc9220_establish_link(); // bit [12] of BCONTROL seems self-clearing.
// Although it's not so in the manual. // Although it's not so in the manual.
/* Interrupt threshold */ /* Interrupt threshold */
SMSC9220->FIFO_INT = 0xFF000000; SMSC9220->FIFO_INT = 0xFF000000;
@ -118,17 +118,18 @@ int ethernet_init()
/*---------------------------------------------------------------------------- /*----------------------------------------------------------------------------
Ethernet Device Uninitialize Ethernet Device Uninitialize
*----------------------------------------------------------------------------*/ *----------------------------------------------------------------------------*/
void ethernet_free() { void ethernet_free()
{
} }
int ethernet_write(const char *data, int size) int ethernet_write(const char *data, int size)
{ {
return 0; return 0;
} }
int ethernet_send() int ethernet_send()
{ {
return 0; return 0;
} }
int ethernet_receive() int ethernet_receive()
@ -148,7 +149,8 @@ int ethernet_read(char *data, int dlen)
return 0; return 0;
} }
void ethernet_address(char *mac) { void ethernet_address(char *mac)
{
mbed_mac_address(mac); mbed_mac_address(mac);
} }

133
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/gpio_api.c
View File

@ -17,121 +17,132 @@
#include "pinmap.h" #include "pinmap.h"
// function to enable the GPIO pin // function to enable the GPIO pin
uint32_t gpio_set(PinName pin) { uint32_t gpio_set(PinName pin)
{
return (1); return (1);
} }
//function to initialise the gpio pin //function to initialise the gpio pin
// this links the board control bits for each pin // this links the board control bits for each pin
// with the object created for the pin // with the object created for the pin
void gpio_init(gpio_t *obj, PinName pin) { void gpio_init(gpio_t *obj, PinName pin)
if(pin == NC){ return;} {
else { if (pin == NC) {
return;
} else {
int pin_value = 0; int pin_value = 0;
obj->pin = pin; obj->pin = pin;
if(pin <=15){ if (pin <= 15) {
pin_value = pin; pin_value = pin;
}else if (pin >= 16 && pin <= 31){ } else if (pin >= 16 && pin <= 31) {
pin_value = pin-16; pin_value = pin - 16;
}else if (pin >= 32 && pin <= 47){ } else if (pin >= 32 && pin <= 47) {
pin_value = pin-32; pin_value = pin - 32;
}else if (pin >= 48 && pin <= 51){ } else if (pin >= 48 && pin <= 51) {
pin_value = pin-48; pin_value = pin - 48;
}else if (pin == 100 || pin == 101){ } else if (pin == 100 || pin == 101) {
pin_value = pin-100; pin_value = pin - 100;
}else if (pin == 110 || pin == 111){ } else if (pin == 110 || pin == 111) {
pin_value = pin-110; pin_value = pin - 110;
}else if (pin >= 200 && pin <= 207){ } else if (pin >= 200 && pin <= 207) {
pin_value = pin-200; pin_value = pin - 200;
}else if (pin >= 210 && pin <= 217){ } else if (pin >= 210 && pin <= 217) {
pin_value = pin-210; pin_value = pin - 210;
}else if (pin == 303){ } else if (pin == 303) {
pin_value = pin-302; pin_value = pin - 302;
}else if (pin == 307){ } else if (pin == 307) {
pin_value = pin-307; pin_value = pin - 307;
}else if (pin == 308){ } else if (pin == 308) {
pin_value = pin-305; pin_value = pin - 305;
}else if (pin == 309){ } else if (pin == 309) {
pin_value = pin-305; pin_value = pin - 305;
}else if (pin == 310){ } else if (pin == 310) {
pin_value = pin-305; pin_value = pin - 305;
}else if (pin == 311){ } else if (pin == 311) {
pin_value = pin-305; pin_value = pin - 305;
}else if (pin == 323){ } else if (pin == 323) {
pin_value = pin-315; pin_value = pin - 315;
}else if (pin == 334){ } else if (pin == 334) {
pin_value = pin-325; pin_value = pin - 325;
}else if (pin == 653){ } else if (pin == 653) {
pin_value = pin-646; pin_value = pin - 646;
} }
obj->mask = 0x1 << pin_value; obj->mask = 0x1 << pin_value;
obj->pin_number = pin; obj->pin_number = pin;
if(pin <=15) { if (pin <= 15) {
obj->reg_data = &CMSDK_GPIO0->DATAOUT ; obj->reg_data = &CMSDK_GPIO0->DATAOUT ;
obj->reg_in = &CMSDK_GPIO0->DATA ; obj->reg_in = &CMSDK_GPIO0->DATA ;
obj->reg_dir = &CMSDK_GPIO0->OUTENABLESET ; obj->reg_dir = &CMSDK_GPIO0->OUTENABLESET ;
obj->reg_dirclr = &CMSDK_GPIO0->OUTENABLECLR ; obj->reg_dirclr = &CMSDK_GPIO0->OUTENABLECLR ;
} else if (pin >= 16 && pin <= 31){ } else if (pin >= 16 && pin <= 31) {
obj->reg_data = &CMSDK_GPIO1->DATAOUT ; obj->reg_data = &CMSDK_GPIO1->DATAOUT ;
obj->reg_in = &CMSDK_GPIO1->DATA ; obj->reg_in = &CMSDK_GPIO1->DATA ;
obj->reg_dir = &CMSDK_GPIO1->OUTENABLESET ; obj->reg_dir = &CMSDK_GPIO1->OUTENABLESET ;
obj->reg_dirclr = &CMSDK_GPIO1->OUTENABLECLR ; obj->reg_dirclr = &CMSDK_GPIO1->OUTENABLECLR ;
} else if (pin >= 32 && pin <= 47){ } else if (pin >= 32 && pin <= 47) {
obj->reg_data = &CMSDK_GPIO2->DATAOUT; obj->reg_data = &CMSDK_GPIO2->DATAOUT;
obj->reg_in = &CMSDK_GPIO2->DATA; obj->reg_in = &CMSDK_GPIO2->DATA;
obj->reg_dir = &CMSDK_GPIO2->OUTENABLESET ; obj->reg_dir = &CMSDK_GPIO2->OUTENABLESET ;
obj->reg_dirclr = &CMSDK_GPIO2->OUTENABLECLR ; obj->reg_dirclr = &CMSDK_GPIO2->OUTENABLECLR ;
} else if (pin >= 48 && pin <= 51){ } else if (pin >= 48 && pin <= 51) {
obj->reg_data = &CMSDK_GPIO3->DATAOUT; obj->reg_data = &CMSDK_GPIO3->DATAOUT;
obj->reg_in = &CMSDK_GPIO3->DATA; obj->reg_in = &CMSDK_GPIO3->DATA;
obj->reg_dir = &CMSDK_GPIO3->OUTENABLESET ; obj->reg_dir = &CMSDK_GPIO3->OUTENABLESET ;
obj->reg_dirclr = &CMSDK_GPIO3->OUTENABLECLR ; obj->reg_dirclr = &CMSDK_GPIO3->OUTENABLECLR ;
} else if (pin == 100 || pin == 101){ } else if (pin == 100 || pin == 101) {
obj->reg_data = &MPS2_FPGAIO->LED; //user leds obj->reg_data = &MPS2_FPGAIO->LED; //user leds
obj->reg_in = &MPS2_FPGAIO->LED; obj->reg_in = &MPS2_FPGAIO->LED;
} else if (pin == 110 || pin == 111){ } else if (pin == 110 || pin == 111) {
obj->reg_data = &MPS2_FPGAIO->BUTTON; //user switches obj->reg_data = &MPS2_FPGAIO->BUTTON; //user switches
obj->reg_in = &MPS2_FPGAIO->BUTTON; //user switches obj->reg_in = &MPS2_FPGAIO->BUTTON; //user switches
}else if (pin >= 200 && pin <= 207){ } else if (pin >= 200 && pin <= 207) {
obj->reg_data = &MPS2_SCC->LEDS; //mcc leds obj->reg_data = &MPS2_SCC->LEDS; //mcc leds
obj->reg_in = &MPS2_SCC->LEDS; //mcc leds obj->reg_in = &MPS2_SCC->LEDS; //mcc leds
}else if (pin >= 210 && pin <= 217){ } else if (pin >= 210 && pin <= 217) {
obj->reg_in = &MPS2_SCC->SWITCHES; //mcc switches obj->reg_in = &MPS2_SCC->SWITCHES; //mcc switches
}else if (pin == 303 || pin == 307){ } else if (pin == 303 || pin == 307) {
obj->reg_data = &MPS2_FPGAIO->MISC; //spi chip select = 303, clcd chip select = 307 obj->reg_data = &MPS2_FPGAIO->MISC; //spi chip select = 303, clcd chip select = 307
}else if (pin == 308 || pin == 309 || pin == 310 || pin == 311){ } else if (pin == 308 || pin == 309 || pin == 310 || pin == 311) {
obj->reg_data = &MPS2_FPGAIO->MISC; //clcd control bits obj->reg_data = &MPS2_FPGAIO->MISC; //clcd control bits
}else if (pin == 323 || pin == 334 || pin == 653){ //spi 3 chip select = 323, spi 4 chip select = 334, adc chip select = 653 } else if (pin == 323 || pin == 334 || pin == 653) { //spi 3 chip select = 323, spi 4 chip select = 334, adc chip select = 653
obj->reg_data = &MPS2_FPGAIO->MISC; //spi cs bits obj->reg_data = &MPS2_FPGAIO->MISC; //spi cs bits
} }
if (pin == 323){ if (pin == 323) {
CMSDK_GPIO0->ALTFUNCSET |= 0x1000; CMSDK_GPIO0->ALTFUNCSET |= 0x1000;
}else if (pin == 334){ } else if (pin == 334) {
CMSDK_GPIO2->ALTFUNCSET |= 0x0040; CMSDK_GPIO2->ALTFUNCSET |= 0x0040;
}else if (pin == 653){ } else if (pin == 653) {
CMSDK_GPIO1->ALTFUNCSET |= 0x0001; CMSDK_GPIO1->ALTFUNCSET |= 0x0001;
} }
} }
} }
void gpio_mode(gpio_t *obj, PinMode mode) { void gpio_mode(gpio_t *obj, PinMode mode)
pin_mode(obj->pin, mode); {
pin_mode(obj->pin, mode);
} }
void gpio_dir(gpio_t *obj, PinDirection direction) { void gpio_dir(gpio_t *obj, PinDirection direction)
if(obj->pin >= 0 && obj->pin <= 51) {
{ if (obj->pin >= 0 && obj->pin <= 51) {
switch (direction) { switch (direction) {
case PIN_INPUT : *obj->reg_dirclr = obj->mask; break; case PIN_INPUT :
case PIN_OUTPUT: *obj->reg_dir |= obj->mask; break; *obj->reg_dirclr = obj->mask;
break;
case PIN_OUTPUT:
*obj->reg_dir |= obj->mask;
break;
} }
} else {return;} } else {
return;
}
} }
int gpio_is_connected(const gpio_t *obj){ int gpio_is_connected(const gpio_t *obj)
if(obj->pin != (PinName)NC){ {
if (obj->pin != (PinName)NC) {
return 1; return 1;
} else { } else {
return 0; return 0;

473
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/gpio_irq_api.c
View File

@ -26,140 +26,307 @@
static uint32_t channel_ids[CHANNEL_NUM] = {0}; static uint32_t channel_ids[CHANNEL_NUM] = {0};
static gpio_irq_handler irq_handler; static gpio_irq_handler irq_handler;
static inline void handle_interrupt_in(uint32_t channel) { static inline void handle_interrupt_in(uint32_t channel)
uint32_t ch_bit = (1 << channel); {
// Return immediately if: uint32_t ch_bit = (1 << channel);
// * The interrupt was already served // Return immediately if:
// * There is no user handler // * The interrupt was already served
// * It is a level interrupt, not an edge interrupt // * There is no user handler
if (ch_bit <16){ // * It is a level interrupt, not an edge interrupt
if ( ((CMSDK_GPIO_0->INTSTATUS) == 0) || (channel_ids[channel] == 0) || ((CMSDK_GPIO_0->INTTYPESET) == 0) ) return; if (ch_bit < 16) {
if (((CMSDK_GPIO_0->INTSTATUS) == 0) || (channel_ids[channel] == 0) || ((CMSDK_GPIO_0->INTTYPESET) == 0)) {
return;
}
if ((CMSDK_GPIO_0->INTTYPESET & ch_bit) && (CMSDK_GPIO_0->INTPOLSET & ch_bit)) { if ((CMSDK_GPIO_0->INTTYPESET & ch_bit) && (CMSDK_GPIO_0->INTPOLSET & ch_bit)) {
irq_handler(channel_ids[channel], IRQ_RISE); irq_handler(channel_ids[channel], IRQ_RISE);
CMSDK_GPIO_0->INTPOLSET = ch_bit; CMSDK_GPIO_0->INTPOLSET = ch_bit;
} }
if ((CMSDK_GPIO_0->INTTYPESET & ch_bit) && ~(CMSDK_GPIO_0->INTPOLSET & ch_bit)) { if ((CMSDK_GPIO_0->INTTYPESET & ch_bit) && ~(CMSDK_GPIO_0->INTPOLSET & ch_bit)) {
irq_handler(channel_ids[channel], IRQ_FALL); irq_handler(channel_ids[channel], IRQ_FALL);
} }
CMSDK_GPIO_0->INTCLEAR = ch_bit; CMSDK_GPIO_0->INTCLEAR = ch_bit;
} }
if (ch_bit>=16) { if (ch_bit >= 16) {
if ( ((CMSDK_GPIO_1->INTSTATUS) == 0) || (channel_ids[channel] == 0) || ((CMSDK_GPIO_1->INTTYPESET) == 0) ) return; if (((CMSDK_GPIO_1->INTSTATUS) == 0) || (channel_ids[channel] == 0) || ((CMSDK_GPIO_1->INTTYPESET) == 0)) {
return;
}
if ((CMSDK_GPIO_1->INTTYPESET & ch_bit) && (CMSDK_GPIO_1->INTPOLSET & ch_bit)) { if ((CMSDK_GPIO_1->INTTYPESET & ch_bit) && (CMSDK_GPIO_1->INTPOLSET & ch_bit)) {
irq_handler(channel_ids[channel], IRQ_RISE); irq_handler(channel_ids[channel], IRQ_RISE);
CMSDK_GPIO_1->INTPOLSET = ch_bit; CMSDK_GPIO_1->INTPOLSET = ch_bit;
} }
if ((CMSDK_GPIO_1->INTTYPESET & ch_bit) && ~(CMSDK_GPIO_1->INTPOLSET & ch_bit)) { if ((CMSDK_GPIO_1->INTTYPESET & ch_bit) && ~(CMSDK_GPIO_1->INTPOLSET & ch_bit)) {
irq_handler(channel_ids[channel], IRQ_FALL); irq_handler(channel_ids[channel], IRQ_FALL);
} }
CMSDK_GPIO_1->INTCLEAR = ch_bit; CMSDK_GPIO_1->INTCLEAR = ch_bit;
} }
} }
void gpio0_irq0(void) {handle_interrupt_in(0);} void gpio0_irq0(void)
void gpio0_irq1(void) {handle_interrupt_in(1);} {
void gpio0_irq2(void) {handle_interrupt_in(2);} handle_interrupt_in(0);
void gpio0_irq3(void) {handle_interrupt_in(3);} }
void gpio0_irq4(void) {handle_interrupt_in(4);} void gpio0_irq1(void)
void gpio0_irq5(void) {handle_interrupt_in(5);} {
void gpio0_irq6(void) {handle_interrupt_in(6);} handle_interrupt_in(1);
void gpio0_irq7(void) {handle_interrupt_in(7);} }
void gpio0_irq8(void) {handle_interrupt_in(8);} void gpio0_irq2(void)
void gpio0_irq9(void) {handle_interrupt_in(9);} {
void gpio0_irq10(void) {handle_interrupt_in(10);} handle_interrupt_in(2);
void gpio0_irq11(void) {handle_interrupt_in(11);} }
void gpio0_irq12(void) {handle_interrupt_in(12);} void gpio0_irq3(void)
void gpio0_irq13(void) {handle_interrupt_in(13);} {
void gpio0_irq14(void) {handle_interrupt_in(14);} handle_interrupt_in(3);
void gpio0_irq15(void) {handle_interrupt_in(15);} }
void gpio1_irq0(void) {handle_interrupt_in(16);} void gpio0_irq4(void)
void gpio1_irq1(void) {handle_interrupt_in(17);} {
void gpio1_irq2(void) {handle_interrupt_in(18);} handle_interrupt_in(4);
void gpio1_irq3(void) {handle_interrupt_in(19);} }
void gpio1_irq4(void) {handle_interrupt_in(20);} void gpio0_irq5(void)
void gpio1_irq5(void) {handle_interrupt_in(21);} {
void gpio1_irq6(void) {handle_interrupt_in(22);} handle_interrupt_in(5);
void gpio1_irq7(void) {handle_interrupt_in(23);} }
void gpio1_irq8(void) {handle_interrupt_in(24);} void gpio0_irq6(void)
void gpio1_irq9(void) {handle_interrupt_in(25);} {
void gpio1_irq10(void) {handle_interrupt_in(26);} handle_interrupt_in(6);
void gpio1_irq11(void) {handle_interrupt_in(27);} }
void gpio1_irq12(void) {handle_interrupt_in(28);} void gpio0_irq7(void)
void gpio1_irq13(void) {handle_interrupt_in(29);} {
void gpio1_irq14(void) {handle_interrupt_in(30);} handle_interrupt_in(7);
void gpio1_irq15(void) {handle_interrupt_in(31);} }
void gpio0_irq8(void)
{
handle_interrupt_in(8);
}
void gpio0_irq9(void)
{
handle_interrupt_in(9);
}
void gpio0_irq10(void)
{
handle_interrupt_in(10);
}
void gpio0_irq11(void)
{
handle_interrupt_in(11);
}
void gpio0_irq12(void)
{
handle_interrupt_in(12);
}
void gpio0_irq13(void)
{
handle_interrupt_in(13);
}
void gpio0_irq14(void)
{
handle_interrupt_in(14);
}
void gpio0_irq15(void)
{
handle_interrupt_in(15);
}
void gpio1_irq0(void)
{
handle_interrupt_in(16);
}
void gpio1_irq1(void)
{
handle_interrupt_in(17);
}
void gpio1_irq2(void)
{
handle_interrupt_in(18);
}
void gpio1_irq3(void)
{
handle_interrupt_in(19);
}
void gpio1_irq4(void)
{
handle_interrupt_in(20);
}
void gpio1_irq5(void)
{
handle_interrupt_in(21);
}
void gpio1_irq6(void)
{
handle_interrupt_in(22);
}
void gpio1_irq7(void)
{
handle_interrupt_in(23);
}
void gpio1_irq8(void)
{
handle_interrupt_in(24);
}
void gpio1_irq9(void)
{
handle_interrupt_in(25);
}
void gpio1_irq10(void)
{
handle_interrupt_in(26);
}
void gpio1_irq11(void)
{
handle_interrupt_in(27);
}
void gpio1_irq12(void)
{
handle_interrupt_in(28);
}
void gpio1_irq13(void)
{
handle_interrupt_in(29);
}
void gpio1_irq14(void)
{
handle_interrupt_in(30);
}
void gpio1_irq15(void)
{
handle_interrupt_in(31);
}
int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) { int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
if (pin == NC) {return -1;} {
else { if (pin == NC) {
return -1;
} else {
irq_handler = handler; irq_handler = handler;
int found_free_channel = 0; int found_free_channel = 0;
int i = 0; int i = 0;
for (i=0; i<CHANNEL_NUM; i++) { for (i = 0; i < CHANNEL_NUM; i++) {
if (channel_ids[i] == 0) { if (channel_ids[i] == 0) {
channel_ids[i] = id; channel_ids[i] = id;
obj->ch = i; obj->ch = i;
found_free_channel = 1; found_free_channel = 1;
break; break;
} }
}
if (!found_free_channel) {
return -1;
} }
if (!found_free_channel) return -1;
/* To select a pin for any of the eight pin interrupts, write the pin number /* To select a pin for any of the eight pin interrupts, write the pin number
* as 0 to 23 for pins PIO0_0 to PIO0_23 and 24 to 55. * as 0 to 23 for pins PIO0_0 to PIO0_23 and 24 to 55.
* @see: mbed_capi/PinNames.h * @see: mbed_capi/PinNames.h
*/ */
if (pin <16) if (pin < 16) {
{ CMSDK_GPIO_0->INTENSET |= (0x1 << pin);
CMSDK_GPIO_0->INTENSET |= (0x1 << pin);
} }
if (pin >= 16) if (pin >= 16) {
{ CMSDK_GPIO_1->INTENSET |= (0x1 << pin);
CMSDK_GPIO_1->INTENSET |= (0x1 << pin);
} }
void (*channels_irq)(void) = NULL; void (*channels_irq)(void) = NULL;
switch (obj->ch) { switch (obj->ch) {
case 0: channels_irq = &gpio0_irq0; break; case 0:
case 1: channels_irq = &gpio0_irq1; break; channels_irq = &gpio0_irq0;
case 2: channels_irq = &gpio0_irq2; break; break;
case 3: channels_irq = &gpio0_irq3; break; case 1:
case 4: channels_irq = &gpio0_irq4; break; channels_irq = &gpio0_irq1;
case 5: channels_irq = &gpio0_irq5; break; break;
case 6: channels_irq = &gpio0_irq6; break; case 2:
case 7: channels_irq = &gpio0_irq7; break; channels_irq = &gpio0_irq2;
case 8: channels_irq = &gpio0_irq8; break; break;
case 9: channels_irq = &gpio0_irq9; break; case 3:
case 10: channels_irq = &gpio0_irq10; break; channels_irq = &gpio0_irq3;
case 11: channels_irq = &gpio0_irq11; break; break;
case 12: channels_irq = &gpio0_irq12; break; case 4:
case 13: channels_irq = &gpio0_irq13; break; channels_irq = &gpio0_irq4;
case 14: channels_irq = &gpio0_irq14; break; break;
case 15: channels_irq = &gpio0_irq15; break; case 5:
case 16: channels_irq = &gpio1_irq0; break; channels_irq = &gpio0_irq5;
case 17: channels_irq = &gpio1_irq1; break; break;
case 18: channels_irq = &gpio1_irq2; break; case 6:
case 19: channels_irq = &gpio1_irq3; break; channels_irq = &gpio0_irq6;
case 20: channels_irq = &gpio1_irq4; break; break;
case 21: channels_irq = &gpio1_irq5; break; case 7:
case 22: channels_irq = &gpio1_irq6; break; channels_irq = &gpio0_irq7;
case 23: channels_irq = &gpio1_irq7; break; break;
case 24: channels_irq = &gpio1_irq8; break; case 8:
case 25: channels_irq = &gpio1_irq9; break; channels_irq = &gpio0_irq8;
case 26: channels_irq = &gpio1_irq10; break; break;
case 27: channels_irq = &gpio1_irq11; break; case 9:
case 28: channels_irq = &gpio1_irq12; break; channels_irq = &gpio0_irq9;
case 29: channels_irq = &gpio1_irq13; break; break;
case 30: channels_irq = &gpio1_irq14; break; case 10:
case 31: channels_irq = &gpio1_irq15; break; channels_irq = &gpio0_irq10;
break;
case 11:
channels_irq = &gpio0_irq11;
break;
case 12:
channels_irq = &gpio0_irq12;
break;
case 13:
channels_irq = &gpio0_irq13;
break;
case 14:
channels_irq = &gpio0_irq14;
break;
case 15:
channels_irq = &gpio0_irq15;
break;
case 16:
channels_irq = &gpio1_irq0;
break;
case 17:
channels_irq = &gpio1_irq1;
break;
case 18:
channels_irq = &gpio1_irq2;
break;
case 19:
channels_irq = &gpio1_irq3;
break;
case 20:
channels_irq = &gpio1_irq4;
break;
case 21:
channels_irq = &gpio1_irq5;
break;
case 22:
channels_irq = &gpio1_irq6;
break;
case 23:
channels_irq = &gpio1_irq7;
break;
case 24:
channels_irq = &gpio1_irq8;
break;
case 25:
channels_irq = &gpio1_irq9;
break;
case 26:
channels_irq = &gpio1_irq10;
break;
case 27:
channels_irq = &gpio1_irq11;
break;
case 28:
channels_irq = &gpio1_irq12;
break;
case 29:
channels_irq = &gpio1_irq13;
break;
case 30:
channels_irq = &gpio1_irq14;
break;
case 31:
channels_irq = &gpio1_irq15;
break;
} }
NVIC_SetVector((IRQn_Type)(PININT_IRQ + obj->ch), (uint32_t)channels_irq); NVIC_SetVector((IRQn_Type)(PININT_IRQ + obj->ch), (uint32_t)channels_irq);
@ -169,73 +336,71 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32
} }
} }
void gpio_irq_free(gpio_irq_t *obj) { void gpio_irq_free(gpio_irq_t *obj)
{
} }
void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) { void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
unsigned int ch_bit = (1 << obj->ch); {
unsigned int ch_bit = (1 << obj->ch);
// Clear interrupt // Clear interrupt
if (obj->ch <16) if (obj->ch < 16) {
{ if (!(CMSDK_GPIO_0->INTTYPESET & ch_bit)) {
if (!(CMSDK_GPIO_0->INTTYPESET & ch_bit)) CMSDK_GPIO_0->INTCLEAR = ch_bit;
{
CMSDK_GPIO_0->INTCLEAR = ch_bit;
}
} }
if (obj->ch >= 16) }
{ if (obj->ch >= 16) {
if (!(CMSDK_GPIO_1->INTTYPESET & ch_bit)) if (!(CMSDK_GPIO_1->INTTYPESET & ch_bit)) {
{ CMSDK_GPIO_1->INTCLEAR = ch_bit;
CMSDK_GPIO_1->INTCLEAR = ch_bit;
}
} }
}
// Edge trigger // Edge trigger
if (obj->ch <16) if (obj->ch < 16) {
{ CMSDK_GPIO_0->INTTYPESET &= ch_bit;
CMSDK_GPIO_0->INTTYPESET &= ch_bit; if (event == IRQ_RISE) {
if (event == IRQ_RISE) { CMSDK_GPIO_0->INTPOLSET |= ch_bit;
CMSDK_GPIO_0->INTPOLSET |= ch_bit; if (enable) {
if (enable) { CMSDK_GPIO_0->INTENSET |= ch_bit;
CMSDK_GPIO_0->INTENSET |= ch_bit; } else {
} else { CMSDK_GPIO_0->INTENCLR |= ch_bit;
CMSDK_GPIO_0->INTENCLR |= ch_bit; }
} } else {
} else { CMSDK_GPIO_0->INTPOLCLR |= ch_bit;
CMSDK_GPIO_0->INTPOLCLR |= ch_bit; if (enable) {
if (enable) { CMSDK_GPIO_0->INTENSET |= ch_bit;
CMSDK_GPIO_0->INTENSET |= ch_bit; } else {
} else { CMSDK_GPIO_0->INTENCLR |= ch_bit;
CMSDK_GPIO_0->INTENCLR |= ch_bit; }
}
}
} }
if (obj->ch >= 16) }
{ if (obj->ch >= 16) {
CMSDK_GPIO_1->INTTYPESET &= ch_bit; CMSDK_GPIO_1->INTTYPESET &= ch_bit;
if (event == IRQ_RISE) { if (event == IRQ_RISE) {
CMSDK_GPIO_1->INTPOLSET |= ch_bit; CMSDK_GPIO_1->INTPOLSET |= ch_bit;
if (enable) { if (enable) {
CMSDK_GPIO_1->INTENSET |= ch_bit; CMSDK_GPIO_1->INTENSET |= ch_bit;
} else { } else {
CMSDK_GPIO_1->INTENCLR |= ch_bit; CMSDK_GPIO_1->INTENCLR |= ch_bit;
} }
} else { } else {
CMSDK_GPIO_1->INTPOLCLR |= ch_bit; CMSDK_GPIO_1->INTPOLCLR |= ch_bit;
if (enable) { if (enable) {
CMSDK_GPIO_1->INTENSET |= ch_bit; CMSDK_GPIO_1->INTENSET |= ch_bit;
} else { } else {
CMSDK_GPIO_1->INTENCLR |= ch_bit; CMSDK_GPIO_1->INTENCLR |= ch_bit;
} }
}
} }
}
} }
void gpio_irq_enable(gpio_irq_t *obj) { void gpio_irq_enable(gpio_irq_t *obj)
NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch)); {
NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
} }
void gpio_irq_disable(gpio_irq_t *obj) { void gpio_irq_disable(gpio_irq_t *obj)
NVIC_DisableIRQ((IRQn_Type)(PININT_IRQ + obj->ch)); {
NVIC_DisableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
} }

20
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/gpio_object.h
View File

@ -28,23 +28,25 @@ extern "C" {
typedef struct { typedef struct {
PinName pin; PinName pin;
uint32_t mask; uint32_t mask;
uint32_t pin_number; uint32_t pin_number;
__IO uint32_t *reg_dir; __IO uint32_t *reg_dir;
__IO uint32_t *reg_dirclr; __IO uint32_t *reg_dirclr;
__IO uint32_t *reg_data; __IO uint32_t *reg_data;
__I uint32_t *reg_in; __I uint32_t *reg_in;
} gpio_t; } gpio_t;
static inline void gpio_write(gpio_t *obj, int value) { static inline void gpio_write(gpio_t *obj, int value)
if (value){ {
*obj->reg_data |= (obj->mask); if (value) {
} else { *obj->reg_data |= (obj->mask);
*obj->reg_data &= ~(obj->mask); } else {
} *obj->reg_data &= ~(obj->mask);
}
} }
static inline int gpio_read(gpio_t *obj) { static inline int gpio_read(gpio_t *obj)
{
return ((*obj->reg_in & obj->mask) ? 1 : 0); return ((*obj->reg_in & obj->mask) ? 1 : 0);
} }

226
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/i2c_api.c
View File

@ -56,7 +56,7 @@ static const PinMap PinMap_I2C_SDA[] = {
{AUD_SDA, I2C_1, 0}, {AUD_SDA, I2C_1, 0},
{SHIELD_0_SDA, I2C_2, 0}, {SHIELD_0_SDA, I2C_2, 0},
{SHIELD_1_SDA, I2C_3, 0}, {SHIELD_1_SDA, I2C_3, 0},
{NC , NC , 0} {NC, NC, 0}
}; };
static const PinMap PinMap_I2C_SCL[] = { static const PinMap PinMap_I2C_SCL[] = {
@ -64,7 +64,7 @@ static const PinMap PinMap_I2C_SCL[] = {
{AUD_SCL, I2C_1, 0}, {AUD_SCL, I2C_1, 0},
{SHIELD_0_SCL, I2C_2, 0}, {SHIELD_0_SCL, I2C_2, 0},
{SHIELD_1_SCL, I2C_3, 0}, {SHIELD_1_SCL, I2C_3, 0},
{NC , NC, 0} {NC, NC, 0}
}; };
static inline void i2c_send_byte(i2c_t *obj, unsigned char c) static inline void i2c_send_byte(i2c_t *obj, unsigned char c)
@ -75,12 +75,12 @@ static inline void i2c_send_byte(i2c_t *obj, unsigned char c)
obj->i2c->CONTROLC = SCL; obj->i2c->CONTROLC = SCL;
i2c_delay(TSC_TSU); i2c_delay(TSC_TSU);
for (loop = 0; loop < 8; loop++) for (loop = 0; loop < 8; loop++) {
{ if (c & (1 << (7 - loop))) {
if (c & (1 << (7 - loop)))
obj->i2c->CONTROLS = SDA; obj->i2c->CONTROLS = SDA;
else } else {
obj->i2c->CONTROLC = SDA; obj->i2c->CONTROLC = SDA;
}
i2c_delay(TSC_TSU); i2c_delay(TSC_TSU);
obj->i2c->CONTROLS = SCL; obj->i2c->CONTROLS = SCL;
@ -91,16 +91,17 @@ static inline void i2c_send_byte(i2c_t *obj, unsigned char c)
obj->i2c->CONTROLS = SDA; obj->i2c->CONTROLS = SDA;
i2c_delay(TSC_TSU); i2c_delay(TSC_TSU);
break; break;
case I2C_1: case I2C_1:
for (loop = 0; loop < 8; loop++) { for (loop = 0; loop < 8; loop++) {
i2c_delay(AAIC_TSU); i2c_delay(AAIC_TSU);
obj->i2c->CONTROLC = SCL; obj->i2c->CONTROLC = SCL;
i2c_delay(AAIC_TSU); i2c_delay(AAIC_TSU);
if (c & (1 << (7 - loop))) if (c & (1 << (7 - loop))) {
obj->i2c->CONTROLS = SDA; obj->i2c->CONTROLS = SDA;
else } else {
obj->i2c->CONTROLC = SDA; obj->i2c->CONTROLC = SDA;
}
i2c_delay(AAIC_TSU); i2c_delay(AAIC_TSU);
obj->i2c->CONTROLS = SCL; obj->i2c->CONTROLS = SCL;
@ -111,18 +112,18 @@ static inline void i2c_send_byte(i2c_t *obj, unsigned char c)
i2c_delay(AAIC_TSU); i2c_delay(AAIC_TSU);
obj->i2c->CONTROLS = SDA; obj->i2c->CONTROLS = SDA;
i2c_delay(AAIC_TSU); i2c_delay(AAIC_TSU);
break; break;
case I2C_2: case I2C_2:
case I2C_3: case I2C_3:
obj->i2c->CONTROLC = SCL; obj->i2c->CONTROLC = SCL;
i2c_delay(SHIELD_TSU); i2c_delay(SHIELD_TSU);
for (loop = 0; loop < 8; loop++) for (loop = 0; loop < 8; loop++) {
{ if (c & (1 << (7 - loop))) {
if (c & (1 << (7 - loop)))
obj->i2c->CONTROLS = SDA; obj->i2c->CONTROLS = SDA;
else } else {
obj->i2c->CONTROLC = SDA; obj->i2c->CONTROLC = SDA;
}
i2c_delay(SHIELD_TSU); i2c_delay(SHIELD_TSU);
obj->i2c->CONTROLS = SCL; obj->i2c->CONTROLS = SCL;
@ -133,7 +134,7 @@ static inline void i2c_send_byte(i2c_t *obj, unsigned char c)
obj->i2c->CONTROLS = SDA; obj->i2c->CONTROLS = SDA;
i2c_delay(SHIELD_TSU); i2c_delay(SHIELD_TSU);
break; break;
} }
} }
@ -147,12 +148,12 @@ static inline unsigned char i2c_receive_byte(i2c_t *obj)
data_receive_byte = 0; data_receive_byte = 0;
for (loop = 0; loop < 8; loop++) for (loop = 0; loop < 8; loop++) {
{
obj->i2c->CONTROLS = SCL; obj->i2c->CONTROLS = SCL;
i2c_delay(TSC_TSU); i2c_delay(TSC_TSU);
if ((obj->i2c->CONTROL & SDA)) if ((obj->i2c->CONTROL & SDA)) {
data_receive_byte += (1 << (7 - loop)); data_receive_byte += (1 << (7 - loop));
}
obj->i2c->CONTROLC = SCL; obj->i2c->CONTROLC = SCL;
i2c_delay(TSC_TSU); i2c_delay(TSC_TSU);
@ -160,7 +161,7 @@ static inline unsigned char i2c_receive_byte(i2c_t *obj)
obj->i2c->CONTROLC = SDA; obj->i2c->CONTROLC = SDA;
i2c_delay(TSC_TSU); i2c_delay(TSC_TSU);
break; break;
case I2C_1: case I2C_1:
obj->i2c->CONTROLS = SDA; obj->i2c->CONTROLS = SDA;
data_receive_byte = 0; data_receive_byte = 0;
@ -171,8 +172,9 @@ static inline unsigned char i2c_receive_byte(i2c_t *obj)
i2c_delay(AAIC_TSU); i2c_delay(AAIC_TSU);
obj->i2c->CONTROLS = SCL | SDA; obj->i2c->CONTROLS = SCL | SDA;
i2c_delay(AAIC_TSU); i2c_delay(AAIC_TSU);
if ((obj->i2c->CONTROL & SDA)) if ((obj->i2c->CONTROL & SDA)) {
data_receive_byte += (1 << (7 - loop)); data_receive_byte += (1 << (7 - loop));
}
i2c_delay(AAIC_TSU); i2c_delay(AAIC_TSU);
obj->i2c->CONTROLC = SCL; obj->i2c->CONTROLC = SCL;
@ -181,7 +183,7 @@ static inline unsigned char i2c_receive_byte(i2c_t *obj)
i2c_delay(AAIC_TSU); i2c_delay(AAIC_TSU);
obj->i2c->CONTROLC = SDA; obj->i2c->CONTROLC = SDA;
i2c_delay(AAIC_TSU); i2c_delay(AAIC_TSU);
break; break;
case I2C_2: case I2C_2:
case I2C_3: case I2C_3:
obj->i2c->CONTROLS = SDA; obj->i2c->CONTROLS = SDA;
@ -189,12 +191,12 @@ static inline unsigned char i2c_receive_byte(i2c_t *obj)
data_receive_byte = 0; data_receive_byte = 0;
for (loop = 0; loop < 8; loop++) for (loop = 0; loop < 8; loop++) {
{
obj->i2c->CONTROLS = SCL; obj->i2c->CONTROLS = SCL;
i2c_delay(SHIELD_TSU); i2c_delay(SHIELD_TSU);
if ((obj->i2c->CONTROL & SDA)) if ((obj->i2c->CONTROL & SDA)) {
data_receive_byte += (1 << (7 - loop)); data_receive_byte += (1 << (7 - loop));
}
obj->i2c->CONTROLC = SCL; obj->i2c->CONTROLC = SCL;
i2c_delay(SHIELD_TSU); i2c_delay(SHIELD_TSU);
@ -202,7 +204,7 @@ static inline unsigned char i2c_receive_byte(i2c_t *obj)
obj->i2c->CONTROLC = SDA; obj->i2c->CONTROLC = SDA;
i2c_delay(SHIELD_TSU); i2c_delay(SHIELD_TSU);
break; break;
} }
return data_receive_byte; return data_receive_byte;
} }
@ -212,10 +214,18 @@ static inline int i2c_receive_ack(i2c_t *obj)
int nack; int nack;
int delay_value; int delay_value;
switch ((int)obj->i2c) { switch ((int)obj->i2c) {
case I2C_0: delay_value = TSC_TSU; break; case I2C_0:
case I2C_1: delay_value = AAIC_TSU; break; delay_value = TSC_TSU;
case I2C_2: delay_value = SHIELD_TSU; break; break;
case I2C_3: delay_value = SHIELD_TSU; break; case I2C_1:
delay_value = AAIC_TSU;
break;
case I2C_2:
delay_value = SHIELD_TSU;
break;
case I2C_3:
delay_value = SHIELD_TSU;
break;
} }
i2c_delay(delay_value); i2c_delay(delay_value);
@ -231,8 +241,9 @@ static inline int i2c_receive_ack(i2c_t *obj)
i2c_delay(delay_value); i2c_delay(delay_value);
obj->i2c->CONTROLS = SDA; obj->i2c->CONTROLS = SDA;
i2c_delay(delay_value); i2c_delay(delay_value);
if(nack==0) if (nack == 0) {
return 1; return 1;
}
return 0; return 0;
} }
@ -242,10 +253,18 @@ static inline void i2c_send_nack(i2c_t *obj)
{ {
int delay_value; int delay_value;
switch ((int)obj->i2c) { switch ((int)obj->i2c) {
case I2C_0: delay_value = TSC_TSU; break; case I2C_0:
case I2C_1: delay_value = AAIC_TSU; break; delay_value = TSC_TSU;
case I2C_2: delay_value = SHIELD_TSU; break; break;
case I2C_3: delay_value = SHIELD_TSU; break; case I2C_1:
delay_value = AAIC_TSU;
break;
case I2C_2:
delay_value = SHIELD_TSU;
break;
case I2C_3:
delay_value = SHIELD_TSU;
break;
} }
i2c_delay(delay_value); i2c_delay(delay_value);
@ -266,10 +285,18 @@ static inline void i2c_send_ack(i2c_t *obj)
{ {
int delay_value; int delay_value;
switch ((int)obj->i2c) { switch ((int)obj->i2c) {
case I2C_0: delay_value = TSC_TSU; break; case I2C_0:
case I2C_1: delay_value = AAIC_TSU; break; delay_value = TSC_TSU;
case I2C_2: delay_value = SHIELD_TSU; break; break;
case I2C_3: delay_value = SHIELD_TSU; break; case I2C_1:
delay_value = AAIC_TSU;
break;
case I2C_2:
delay_value = SHIELD_TSU;
break;
case I2C_3:
delay_value = SHIELD_TSU;
break;
} }
i2c_delay(delay_value); i2c_delay(delay_value);
@ -297,9 +324,13 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl)
pinmap_pinout(scl, PinMap_I2C_SCL); pinmap_pinout(scl, PinMap_I2C_SCL);
switch ((int)obj->i2c) { switch ((int)obj->i2c) {
case I2C_2: CMSDK_GPIO0->ALTFUNCSET |= 0x8020; break; case I2C_2:
case I2C_3: CMSDK_GPIO1->ALTFUNCSET |= 0x8000; CMSDK_GPIO0->ALTFUNCSET |= 0x8020;
CMSDK_GPIO2->ALTFUNCSET |= 0x0200; break; break;
case I2C_3:
CMSDK_GPIO1->ALTFUNCSET |= 0x8000;
CMSDK_GPIO2->ALTFUNCSET |= 0x0200;
break;
} }
@ -309,10 +340,18 @@ int i2c_start(i2c_t *obj)
{ {
int delay_value; int delay_value;
switch ((int)obj->i2c) { switch ((int)obj->i2c) {
case I2C_0: delay_value = TSC_TSU; break; case I2C_0:
case I2C_1: delay_value = AAIC_TSU; break; delay_value = TSC_TSU;
case I2C_2: delay_value = SHIELD_TSU; break; break;
case I2C_3: delay_value = SHIELD_TSU; break; case I2C_1:
delay_value = AAIC_TSU;
break;
case I2C_2:
delay_value = SHIELD_TSU;
break;
case I2C_3:
delay_value = SHIELD_TSU;
break;
} }
i2c_delay(delay_value); i2c_delay(delay_value);
@ -328,10 +367,18 @@ int i2c_start_tsc(i2c_t *obj)
{ {
int delay_value; int delay_value;
switch ((int)obj->i2c) { switch ((int)obj->i2c) {
case I2C_0: delay_value = TSC_TSU; break; case I2C_0:
case I2C_1: delay_value = AAIC_TSU; break; delay_value = TSC_TSU;
case I2C_2: delay_value = SHIELD_TSU; break; break;
case I2C_3: delay_value = SHIELD_TSU; break; case I2C_1:
delay_value = AAIC_TSU;
break;
case I2C_2:
delay_value = SHIELD_TSU;
break;
case I2C_3:
delay_value = SHIELD_TSU;
break;
} }
i2c_delay(delay_value); i2c_delay(delay_value);
@ -347,10 +394,18 @@ int i2c_stop(i2c_t *obj)
{ {
int delay_value; int delay_value;
switch ((int)obj->i2c) { switch ((int)obj->i2c) {
case I2C_0: delay_value = TSC_TSU; break; case I2C_0:
case I2C_1: delay_value = AAIC_TSU; break; delay_value = TSC_TSU;
case I2C_2: delay_value = SHIELD_TSU; break; break;
case I2C_3: delay_value = SHIELD_TSU; break; case I2C_1:
delay_value = AAIC_TSU;
break;
case I2C_2:
delay_value = SHIELD_TSU;
break;
case I2C_3:
delay_value = SHIELD_TSU;
break;
} }
// Actual stop bit // Actual stop bit
i2c_delay(delay_value); i2c_delay(delay_value);
@ -366,14 +421,15 @@ int i2c_stop(i2c_t *obj)
void i2c_frequency(i2c_t *obj, int hz) { void i2c_frequency(i2c_t *obj, int hz)
{
} }
int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
{ {
unsigned int loop, rxdata; unsigned int loop, rxdata;
int sadr, ack, bytes_read; int sadr, ack, bytes_read;
rxdata=0; rxdata = 0;
switch ((int)obj->i2c) { switch ((int)obj->i2c) {
case I2C_0: case I2C_0:
sadr = TSC_I2C_ADDR; sadr = TSC_I2C_ADDR;
@ -385,7 +441,7 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
case I2C_3: case I2C_3:
sadr = address; //LM75_I2C_ADDR; or MMA7660_I2C_ADDR; sadr = address; //LM75_I2C_ADDR; or MMA7660_I2C_ADDR;
break; break;
} }
bytes_read = 0; bytes_read = 0;
// Start bit // Start bit
i2c_start(obj); i2c_start(obj);
@ -393,7 +449,7 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
switch ((int)obj->i2c) { switch ((int)obj->i2c) {
case I2C_0: case I2C_0:
// Set serial and register address // Set serial and register address
i2c_send_byte(obj,sadr); i2c_send_byte(obj, sadr);
ack += i2c_receive_ack(obj); ack += i2c_receive_ack(obj);
i2c_send_byte(obj, address); i2c_send_byte(obj, address);
ack += i2c_receive_ack(obj); ack += i2c_receive_ack(obj);
@ -405,17 +461,15 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
i2c_start_tsc(obj); i2c_start_tsc(obj);
// Read from I2C address // Read from I2C address
i2c_send_byte(obj,sadr | 1); i2c_send_byte(obj, sadr | 1);
ack += i2c_receive_ack(obj); ack += i2c_receive_ack(obj);
rxdata = (i2c_receive_byte(obj) & 0xFF); rxdata = (i2c_receive_byte(obj) & 0xFF);
data[((length-1)-bytes_read)] = (char)rxdata; data[((length - 1) - bytes_read)] = (char)rxdata;
bytes_read++; bytes_read++;
// Read multiple bytes // Read multiple bytes
if ((length > 1) && (length < 5)) if ((length > 1) && (length < 5)) {
{ for (loop = 1; loop <= (length - 1); loop++) {
for (loop = 1; loop <= (length - 1); loop++)
{
// Send ACK // Send ACK
i2c_send_ack(obj); i2c_send_ack(obj);
@ -423,7 +477,7 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
//rxdata = ((rxdata << 8) & 0xFFFFFF00); //rxdata = ((rxdata << 8) & 0xFFFFFF00);
//rxdata |= (i2c_receive_byte(obj) & 0xFF); //rxdata |= (i2c_receive_byte(obj) & 0xFF);
rxdata = i2c_receive_byte(obj); rxdata = i2c_receive_byte(obj);
data[(length-1)-bytes_read] = (char)rxdata; data[(length - 1) - bytes_read] = (char)rxdata;
bytes_read++; bytes_read++;
} }
@ -431,7 +485,7 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
break; break;
case I2C_1: case I2C_1:
// Set serial and register address // Set serial and register address
i2c_send_byte(obj,sadr); i2c_send_byte(obj, sadr);
ack += i2c_receive_ack(obj); ack += i2c_receive_ack(obj);
i2c_send_byte(obj, address); i2c_send_byte(obj, address);
ack += i2c_receive_ack(obj); ack += i2c_receive_ack(obj);
@ -441,21 +495,19 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
// Start bit // Start bit
i2c_start_tsc(obj); i2c_start_tsc(obj);
// Fall through to read data // Fall through to read data
case I2C_2: case I2C_2:
case I2C_3: case I2C_3:
// Read from preset register address pointer // Read from preset register address pointer
i2c_send_byte(obj,sadr | 1); i2c_send_byte(obj, sadr | 1);
ack += i2c_receive_ack(obj); ack += i2c_receive_ack(obj);
rxdata = i2c_receive_byte(obj); rxdata = i2c_receive_byte(obj);
data[bytes_read] = (char)rxdata; data[bytes_read] = (char)rxdata;
bytes_read++; bytes_read++;
// Read multiple bytes // Read multiple bytes
if ((length > 1) && (length < 5)) if ((length > 1) && (length < 5)) {
{ for (loop = 1; loop <= (length - 1); loop++) {
for (loop = 1; loop <= (length - 1); loop++)
{
// Send ACK // Send ACK
i2c_send_ack(obj); i2c_send_ack(obj);
@ -477,13 +529,12 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
{ {
int ack=0; int ack = 0;
int sadr; int sadr;
char * ptr; char *ptr;
char addr; char addr;
ptr = (char*)data; ptr = (char *)data;
switch ((int)obj->i2c) switch ((int)obj->i2c) {
{
case I2C_0: case I2C_0:
sadr = TSC_I2C_ADDR; sadr = TSC_I2C_ADDR;
addr = address; addr = address;
@ -497,37 +548,42 @@ int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
sadr = address; //LM75_I2C_ADDR or MMA7660_I2C_ADDR; sadr = address; //LM75_I2C_ADDR or MMA7660_I2C_ADDR;
addr = *ptr++; addr = *ptr++;
break; break;
} }
// printf("adr = %x, reg = %x\n",sadr, address); // printf("adr = %x, reg = %x\n",sadr, address);
i2c_start(obj); i2c_start(obj);
// Set serial and register address // Set serial and register address
i2c_send_byte(obj,sadr); i2c_send_byte(obj, sadr);
ack += i2c_receive_ack(obj); ack += i2c_receive_ack(obj);
i2c_send_byte(obj, addr); i2c_send_byte(obj, addr);
ack += i2c_receive_ack(obj); ack += i2c_receive_ack(obj);
for(int i = 1; i<length; i++) for (int i = 1; i < length; i++) {
{
i2c_send_byte(obj, *ptr++); i2c_send_byte(obj, *ptr++);
ack += i2c_receive_ack(obj); ack += i2c_receive_ack(obj);
} }
i2c_stop(obj); i2c_stop(obj);
if(ack==3) { return 1; } if (ack == 3) {
else{ return 0; } return 1;
} else {
return 0;
}
} }
void i2c_reset(i2c_t *obj) { void i2c_reset(i2c_t *obj)
{
i2c_stop(obj); i2c_stop(obj);
} }
int i2c_byte_read(i2c_t *obj, int last) { int i2c_byte_read(i2c_t *obj, int last)
{
return 0; return 0;
} }
int i2c_byte_write(i2c_t *obj, int data) { int i2c_byte_write(i2c_t *obj, int data)
{
return 0; return 0;
} }

8
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/objects.h
View File

@ -31,7 +31,7 @@ struct gpio_irq_s {
struct port_s { struct port_s {
__IO uint32_t *reg_dir; __IO uint32_t *reg_dir;
__IO uint32_t *reg_dirclr; __IO uint32_t *reg_dirclr;
__IO uint32_t *reg_out; __IO uint32_t *reg_out;
__IO uint32_t *reg_in; __IO uint32_t *reg_in;
PortName port; PortName port;
@ -53,7 +53,7 @@ struct tsc_s {
struct audio_s { struct audio_s {
MPS2_I2S_TypeDef *audio_I2S; MPS2_I2S_TypeDef *audio_I2S;
MPS2_I2C_TypeDef *audio_I2C; MPS2_I2C_TypeDef *audio_I2C;
}; };
@ -67,9 +67,9 @@ struct clcd_s {
struct analogin_s { struct analogin_s {
ADCName adc; ADCName adc;
MPS2_SSP_TypeDef *adc_spi; MPS2_SSP_TypeDef *adc_spi;
PinName pin; PinName pin;
uint32_t pin_number; uint32_t pin_number;
__IO uint32_t address; __IO uint32_t address;
}; };

10
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/pinmap.c
View File

@ -18,11 +18,13 @@
#include "mbed_error.h" #include "mbed_error.h"
void pin_function(PinName pin, int function) { void pin_function(PinName pin, int function)
MBED_ASSERT(pin != (PinName)NC); {
MBED_ASSERT(pin != (PinName)NC);
} }
void pin_mode(PinName pin, PinMode mode) { void pin_mode(PinName pin, PinMode mode)
MBED_ASSERT(pin != (PinName)NC); {
MBED_ASSERT(pin != (PinName)NC);
} }

34
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/port_api.c
View File

@ -17,11 +17,13 @@
#include "pinmap.h" #include "pinmap.h"
#include "gpio_api.h" #include "gpio_api.h"
PinName port_pin(PortName port, int pin_n) { PinName port_pin(PortName port, int pin_n)
{
return (PinName)((port << PORT_SHIFT) | pin_n); return (PinName)((port << PORT_SHIFT) | pin_n);
} }
void port_init(port_t *obj, PortName port, int mask, PinDirection dir) { void port_init(port_t *obj, PortName port, int mask, PinDirection dir)
{
obj->port = port; obj->port = port;
obj->mask = mask; obj->mask = mask;
@ -33,8 +35,8 @@ void port_init(port_t *obj, PortName port, int mask, PinDirection dir) {
uint32_t i; uint32_t i;
// The function is set per pin: reuse gpio logic // The function is set per pin: reuse gpio logic
for (i=0; i<16; i++) { for (i = 0; i < 16; i++) {
if (obj->mask & (1<<i)) { if (obj->mask & (1 << i)) {
gpio_set(port_pin(obj->port, i)); gpio_set(port_pin(obj->port, i));
} }
} }
@ -42,27 +44,35 @@ void port_init(port_t *obj, PortName port, int mask, PinDirection dir) {
port_dir(obj, dir); port_dir(obj, dir);
} }
void port_mode(port_t *obj, PinMode mode) { void port_mode(port_t *obj, PinMode mode)
{
uint32_t i; uint32_t i;
// The mode is set per pin: reuse pinmap logic // The mode is set per pin: reuse pinmap logic
for (i=0; i<32; i++) { for (i = 0; i < 32; i++) {
if (obj->mask & (1<<i)) { if (obj->mask & (1 << i)) {
pin_mode(port_pin(obj->port, i), mode); pin_mode(port_pin(obj->port, i), mode);
} }
} }
} }
void port_dir(port_t *obj, PinDirection dir) { void port_dir(port_t *obj, PinDirection dir)
{
switch (dir) { switch (dir) {
case PIN_INPUT : *obj->reg_dir &= ~obj->mask; break; case PIN_INPUT :
case PIN_OUTPUT: *obj->reg_dir |= obj->mask; break; *obj->reg_dir &= ~obj->mask;
break;
case PIN_OUTPUT:
*obj->reg_dir |= obj->mask;
break;
} }
} }
void port_write(port_t *obj, int value) { void port_write(port_t *obj, int value)
{
*obj->reg_in = value; *obj->reg_in = value;
} }
int port_read(port_t *obj) { int port_read(port_t *obj)
{
return (*obj->reg_in); return (*obj->reg_in);
} }

345
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/serial_api.c
View File

@ -30,19 +30,19 @@
******************************************************************************/ ******************************************************************************/
static const PinMap PinMap_UART_TX[] = { static const PinMap PinMap_UART_TX[] = {
{USBTX , UART_0, 0}, {USBTX, UART_0, 0},
{XB_TX , UART_1, 0}, {XB_TX, UART_1, 0},
{SH0_TX , UART_2, 0}, {SH0_TX, UART_2, 0},
{SH1_TX , UART_3, 0}, {SH1_TX, UART_3, 0},
{NC , NC , 0} {NC, NC, 0}
}; };
static const PinMap PinMap_UART_RX[] = { static const PinMap PinMap_UART_RX[] = {
{USBRX , UART_0, 0}, {USBRX, UART_0, 0},
{XB_RX , UART_1, 0}, {XB_RX, UART_1, 0},
{SH0_RX , UART_2, 0}, {SH0_RX, UART_2, 0},
{SH1_RX , UART_3, 0}, {SH1_RX, UART_3, 0},
{NC , NC , 0} {NC, NC, 0}
}; };
#define UART_NUM 4 #define UART_NUM 4
@ -60,7 +60,8 @@ struct serial_global_data_s {
static struct serial_global_data_s uart_data[UART_NUM]; static struct serial_global_data_s uart_data[UART_NUM];
void serial_init(serial_t *obj, PinName tx, PinName rx) { void serial_init(serial_t *obj, PinName tx, PinName rx)
{
int is_stdio_uart = 0; int is_stdio_uart = 0;
// determine the UART to use // determine the UART to use
@ -73,87 +74,82 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) {
obj->uart = (CMSDK_UART_TypeDef *)uart; obj->uart = (CMSDK_UART_TypeDef *)uart;
//set baud rate and enable Uart in normarl mode (RX and TX enabled) //set baud rate and enable Uart in normarl mode (RX and TX enabled)
switch (uart) switch (uart) {
{ case UART_0: {
case UART_0: CMSDK_UART0->CTRL = 0x00; // Disable UART when changing configuration
{ if ((int)uart_tx != NC) {
CMSDK_UART0->CTRL = 0x00; // Disable UART when changing configuration CMSDK_UART0->CTRL |= 0x01; // TX enable
if((int)uart_tx != NC) } else {
{ CMSDK_UART0->CTRL &= 0xFFFE; // TX disable
CMSDK_UART0->CTRL |= 0x01; // TX enable }
} else {
CMSDK_UART0->CTRL &= 0xFFFE; // TX disable
}
if((int)uart_rx != NC) if ((int)uart_rx != NC) {
{ CMSDK_UART0->CTRL |= 0x02; // RX enable
CMSDK_UART0->CTRL |= 0x02; // RX enable } else {
} else { CMSDK_UART0->CTRL &= 0xFFFD; // RX disable
CMSDK_UART0->CTRL &= 0xFFFD; // RX disable }
}
} }
break; break;
case UART_1: //XBEE SOCKET UART case UART_1: { //XBEE SOCKET UART
{ CMSDK_UART1->CTRL = 0x00; // Disable UART when changing configuration
CMSDK_UART1->CTRL = 0x00; // Disable UART when changing configuration if ((int)tx != NC) {
if((int)tx != NC) CMSDK_UART1->CTRL = 0x1; // TX enable
{ CMSDK_GPIO1->ALTFUNCSET |= 0x0100;
CMSDK_UART1->CTRL = 0x1; // TX enable }
CMSDK_GPIO1->ALTFUNCSET |= 0x0100; if ((int)rx != NC) {
} CMSDK_UART1->CTRL |= 0x2; // RX enable
if((int)rx != NC) CMSDK_GPIO1->ALTFUNCSET |= 0x0080;
{ }
CMSDK_UART1->CTRL |= 0x2; // RX enable }
CMSDK_GPIO1->ALTFUNCSET |= 0x0080; break;
} case UART_2: { //Sheild0 UART
} CMSDK_UART3->CTRL = 0x00; // Disable UART when changing configuration
break; if ((int)tx != NC) {
case UART_2: //Sheild0 UART CMSDK_UART3->CTRL = 0x1; // TX enable
{ CMSDK_GPIO0->ALTFUNCSET |= 0x0010;
CMSDK_UART3->CTRL = 0x00; // Disable UART when changing configuration }
if((int)tx != NC) if ((int)rx != NC) {
{ CMSDK_UART3->CTRL |= 0x2; // RX enable
CMSDK_UART3->CTRL = 0x1; // TX enable CMSDK_GPIO0->ALTFUNCSET |= 0x0001;
CMSDK_GPIO0->ALTFUNCSET |= 0x0010; }
} }
if((int)rx != NC) break;
{ case UART_3: { //Sheild1 UART
CMSDK_UART3->CTRL |= 0x2; // RX enable CMSDK_UART4->CTRL = 0x00; // Disable UART when changing configuration
CMSDK_GPIO0->ALTFUNCSET |= 0x0001; if ((int)tx != NC) {
} CMSDK_UART4->CTRL = 0x1; // TX enable
} CMSDK_GPIO1->ALTFUNCSET |= 0x4000;
break; }
case UART_3: //Sheild1 UART if ((int)rx != NC) {
{ CMSDK_UART4->CTRL |= 0x2; // RX enable
CMSDK_UART4->CTRL = 0x00; // Disable UART when changing configuration CMSDK_GPIO1->ALTFUNCSET |= 0x0400;
if((int)tx != NC) }
{ }
CMSDK_UART4->CTRL = 0x1; // TX enable break;
CMSDK_GPIO1->ALTFUNCSET |= 0x4000;
}
if((int)rx != NC)
{
CMSDK_UART4->CTRL |= 0x2; // RX enable
CMSDK_GPIO1->ALTFUNCSET |= 0x0400;
}
}
break;
} }
// set default baud rate and format // set default baud rate and format
serial_baud (obj, 9600); serial_baud(obj, 9600);
// pinout the chosen uart // pinout the chosen uart
pinmap_pinout(tx, PinMap_UART_TX); pinmap_pinout(tx, PinMap_UART_TX);
pinmap_pinout(rx, PinMap_UART_RX); pinmap_pinout(rx, PinMap_UART_RX);
switch (uart) { switch (uart) {
case UART_0: obj->index = 0; break; case UART_0:
case UART_1: obj->index = 1; break; obj->index = 0;
case UART_2: obj->index = 2; break; break;
case UART_3: obj->index = 3; break; case UART_1:
obj->index = 1;
break;
case UART_2:
obj->index = 2;
break;
case UART_3:
obj->index = 3;
break;
} }
uart_data[obj->index].sw_rts.pin = NC; uart_data[obj->index].sw_rts.pin = NC;
uart_data[obj->index].sw_cts.pin = NC; uart_data[obj->index].sw_cts.pin = NC;
@ -167,203 +163,222 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) {
} }
} }
void serial_free(serial_t *obj) { void serial_free(serial_t *obj)
uart_data[obj->index].serial_irq_id = 0; {
uart_data[obj->index].serial_irq_id = 0;
} }
// serial_baud // serial_baud
// set the baud rate, taking in to account the current SystemFrequency // set the baud rate, taking in to account the current SystemFrequency
void serial_baud(serial_t *obj, int baudrate) { void serial_baud(serial_t *obj, int baudrate)
{
// The MPS2 has a simple divider to control the baud rate. The formula is: // The MPS2 has a simple divider to control the baud rate. The formula is:
// //
// Baudrate = PCLK / BAUDDIV // Baudrate = PCLK / BAUDDIV
// //
// PCLK = 25 Mhz // PCLK = 25 Mhz
// so for a desired baud rate of 9600 // so for a desired baud rate of 9600
// 25000000 / 9600 = 2604 // 25000000 / 9600 = 2604
// //
//check to see if minimum baud value entered //check to see if minimum baud value entered
int baudrate_div = 0; int baudrate_div = 0;
baudrate_div = SystemCoreClock / baudrate; baudrate_div = SystemCoreClock / baudrate;
if(baudrate >= 16){ if (baudrate >= 16) {
switch ((int)obj->uart) { switch ((int)obj->uart) {
case UART_0: CMSDK_UART0->BAUDDIV = baudrate_div; break; case UART_0:
case UART_1: CMSDK_UART1->BAUDDIV = baudrate_div; break; CMSDK_UART0->BAUDDIV = baudrate_div;
case UART_2: CMSDK_UART3->BAUDDIV = baudrate_div; break; break;
case UART_3: CMSDK_UART4->BAUDDIV = baudrate_div; break; case UART_1:
default: error("serial_baud"); break; CMSDK_UART1->BAUDDIV = baudrate_div;
} break;
case UART_2:
CMSDK_UART3->BAUDDIV = baudrate_div;
break;
case UART_3:
CMSDK_UART4->BAUDDIV = baudrate_div;
break;
default:
error("serial_baud");
break;
}
} else { } else {
error("serial_baud"); error("serial_baud");
} }
} }
void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) { void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
{
} }
/****************************************************************************** /******************************************************************************
* INTERRUPTS HANDLING * INTERRUPTS HANDLING
******************************************************************************/ ******************************************************************************/
static inline void uart_irq(uint32_t intstatus, uint32_t index, CMSDK_UART_TypeDef *puart) { static inline void uart_irq(uint32_t intstatus, uint32_t index, CMSDK_UART_TypeDef *puart)
{
SerialIrq irq_type; SerialIrq irq_type;
switch (intstatus) switch (intstatus) {
{ case 1: {
case 1: irq_type = TxIrq;
{ }
irq_type = TxIrq; break;
}
break;
case 2: case 2: {
{ irq_type = RxIrq;
irq_type = RxIrq; }
} break;
break;
default: return; default:
return;
} /* End of Switch */ } /* End of Switch */
if ((RxIrq == irq_type) && (NC != uart_data[index].sw_rts.pin)) if ((RxIrq == irq_type) && (NC != uart_data[index].sw_rts.pin)) {
{
gpio_write(&uart_data[index].sw_rts, 1); gpio_write(&uart_data[index].sw_rts, 1);
// Disable interrupt if it wasn't enabled by other part of the application // Disable interrupt if it wasn't enabled by other part of the application
if (!uart_data[index].rx_irq_set_api) if (!uart_data[index].rx_irq_set_api) {
{
/* Disable Rx interrupt */ /* Disable Rx interrupt */
puart->CTRL &= ~(CMSDK_UART_CTRL_RXIRQEN_Msk); puart->CTRL &= ~(CMSDK_UART_CTRL_RXIRQEN_Msk);
} }
} }
if (uart_data[index].serial_irq_id != 0) if (uart_data[index].serial_irq_id != 0) {
{ if ((irq_type != RxIrq) || (uart_data[index].rx_irq_set_api)) {
if ((irq_type != RxIrq) || (uart_data[index].rx_irq_set_api))
{
irq_handler(uart_data[index].serial_irq_id, irq_type); irq_handler(uart_data[index].serial_irq_id, irq_type);
} }
} }
if( irq_type == TxIrq ) if (irq_type == TxIrq) {
{
/* Clear the TX interrupt Flag */ /* Clear the TX interrupt Flag */
puart->INTCLEAR |= 0x01; puart->INTCLEAR |= 0x01;
} } else {
else
{
/* Clear the Rx interupt Flag */ /* Clear the Rx interupt Flag */
puart->INTCLEAR |= 0x02; puart->INTCLEAR |= 0x02;
} }
} }
void uart0_irq() {uart_irq(CMSDK_UART0->INTSTATUS & 0x3, 0, (CMSDK_UART_TypeDef*)CMSDK_UART0);} void uart0_irq()
void uart1_irq() {uart_irq(CMSDK_UART1->INTSTATUS & 0x3, 1, (CMSDK_UART_TypeDef*)CMSDK_UART1);} {
void uart2_irq() {uart_irq(CMSDK_UART3->INTSTATUS & 0x3, 2, (CMSDK_UART_TypeDef*)CMSDK_UART3);} uart_irq(CMSDK_UART0->INTSTATUS & 0x3, 0, (CMSDK_UART_TypeDef *)CMSDK_UART0);
void uart3_irq() {uart_irq(CMSDK_UART4->INTSTATUS & 0x3, 3, (CMSDK_UART_TypeDef*)CMSDK_UART4);} }
void uart1_irq()
{
uart_irq(CMSDK_UART1->INTSTATUS & 0x3, 1, (CMSDK_UART_TypeDef *)CMSDK_UART1);
}
void uart2_irq()
{
uart_irq(CMSDK_UART3->INTSTATUS & 0x3, 2, (CMSDK_UART_TypeDef *)CMSDK_UART3);
}
void uart3_irq()
{
uart_irq(CMSDK_UART4->INTSTATUS & 0x3, 3, (CMSDK_UART_TypeDef *)CMSDK_UART4);
}
void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
{
irq_handler = handler; irq_handler = handler;
uart_data[obj->index].serial_irq_id = id; uart_data[obj->index].serial_irq_id = id;
} }
static void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enable) { static void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enable)
{
/* Declare a variable of type IRQn, initialise to 0 */ /* Declare a variable of type IRQn, initialise to 0 */
IRQn_Type irq_n = (IRQn_Type)0; IRQn_Type irq_n = (IRQn_Type)0;
uint32_t vector = 0; uint32_t vector = 0;
switch ((int)obj->uart) switch ((int)obj->uart) {
{ case UART_0: {
case UART_0: irq_n = ((irq == TxIrq) ? UARTTX0_IRQn : UARTRX0_IRQn);
{
irq_n = (( irq == TxIrq ) ? UARTTX0_IRQn : UARTRX0_IRQn);
vector = (uint32_t)&uart0_irq; vector = (uint32_t)&uart0_irq;
} }
break; break;
case UART_1: case UART_1: {
{ irq_n = ((irq == TxIrq) ? UARTTX1_IRQn : UARTRX1_IRQn);
irq_n = (( irq == TxIrq ) ? UARTTX1_IRQn : UARTRX1_IRQn);
vector = (uint32_t)&uart1_irq; vector = (uint32_t)&uart1_irq;
} }
break; break;
case UART_2: case UART_2: {
{ irq_n = ((irq == TxIrq) ? UARTTX3_IRQn : UARTRX3_IRQn);
irq_n = (( irq == TxIrq ) ? UARTTX3_IRQn : UARTRX3_IRQn);
vector = (uint32_t)&uart2_irq; vector = (uint32_t)&uart2_irq;
} }
break; break;
case UART_3: case UART_3: {
{ irq_n = ((irq == TxIrq) ? UARTTX4_IRQn : UARTRX4_IRQn);
irq_n = (( irq == TxIrq ) ? UARTTX4_IRQn : UARTRX4_IRQn); vector = (uint32_t)&uart3_irq;
vector = (uint32_t)&uart3_irq;
} }
break; break;
} }
if (enable) if (enable) {
{ if (irq == TxIrq) {
if( irq == TxIrq )
{
/* Transmit IRQ, set appripriate enable */ /* Transmit IRQ, set appripriate enable */
/* set TX interrupt enable in CTRL REG */ /* set TX interrupt enable in CTRL REG */
obj->uart->CTRL |= CMSDK_UART_CTRL_TXIRQEN_Msk; obj->uart->CTRL |= CMSDK_UART_CTRL_TXIRQEN_Msk;
} } else {
else
{
/* set Rx interrupt on in CTRL REG */ /* set Rx interrupt on in CTRL REG */
obj->uart->CTRL |= CMSDK_UART_CTRL_RXIRQEN_Msk; obj->uart->CTRL |= CMSDK_UART_CTRL_RXIRQEN_Msk;
} }
NVIC_SetVector(irq_n, vector); NVIC_SetVector(irq_n, vector);
NVIC_EnableIRQ(irq_n); NVIC_EnableIRQ(irq_n);
} } else {
else /* Disable IRQ */
{ /* Disable IRQ */
obj->uart->CTRL &= ~(1 << (irq + 2)); obj->uart->CTRL &= ~(1 << (irq + 2));
NVIC_DisableIRQ(irq_n); NVIC_DisableIRQ(irq_n);
} }
} }
void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
{
serial_irq_set_internal(obj, irq, enable); serial_irq_set_internal(obj, irq, enable);
} }
/****************************************************************************** /******************************************************************************
* READ/WRITE * READ/WRITE
******************************************************************************/ ******************************************************************************/
int serial_getc(serial_t *obj) { int serial_getc(serial_t *obj)
{
while (serial_readable(obj) == 0); while (serial_readable(obj) == 0);
int data = obj->uart->DATA; int data = obj->uart->DATA;
return data; return data;
} }
void serial_putc(serial_t *obj, int c) { void serial_putc(serial_t *obj, int c)
{
while (serial_writable(obj) == 0); while (serial_writable(obj) == 0);
obj->uart->DATA = c; obj->uart->DATA = c;
} }
int serial_readable(serial_t *obj) { int serial_readable(serial_t *obj)
{
return obj->uart->STATE & 0x2; return obj->uart->STATE & 0x2;
} }
int serial_writable(serial_t *obj) { int serial_writable(serial_t *obj)
{
return !(obj->uart->STATE & 0x1); return !(obj->uart->STATE & 0x1);
} }
void serial_clear(serial_t *obj) { void serial_clear(serial_t *obj)
{
obj->uart->DATA = 0x00; obj->uart->DATA = 0x00;
} }
void serial_pinout_tx(PinName tx) { void serial_pinout_tx(PinName tx)
{
pinmap_pinout(tx, PinMap_UART_TX); pinmap_pinout(tx, PinMap_UART_TX);
} }
void serial_break_set(serial_t *obj) { void serial_break_set(serial_t *obj)
{
} }
void serial_break_clear(serial_t *obj) { void serial_break_clear(serial_t *obj)
{
} }
void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) { void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow)
{
} }

150
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/spi_api.c
View File

@ -23,12 +23,12 @@
#include "mbed_wait_api.h" #include "mbed_wait_api.h"
static const PinMap PinMap_SPI_SCLK[] = { static const PinMap PinMap_SPI_SCLK[] = {
{SCLK_SPI , SPI_0, 0}, {SCLK_SPI, SPI_0, 0},
{CLCD_SCLK , SPI_1, 0}, {CLCD_SCLK, SPI_1, 0},
{ADC_SCLK , SPI_2, 0}, {ADC_SCLK, SPI_2, 0},
{SHIELD_0_SPI_SCK , SPI_3, 0}, {SHIELD_0_SPI_SCK, SPI_3, 0},
{SHIELD_1_SPI_SCK , SPI_4, 0}, {SHIELD_1_SPI_SCK, SPI_4, 0},
{NC , NC , 0} {NC, NC, 0}
}; };
static const PinMap PinMap_SPI_MOSI[] = { static const PinMap PinMap_SPI_MOSI[] = {
@ -37,7 +37,7 @@ static const PinMap PinMap_SPI_MOSI[] = {
{ADC_MOSI, SPI_2, 0}, {ADC_MOSI, SPI_2, 0},
{SHIELD_0_SPI_MOSI, SPI_3, 0}, {SHIELD_0_SPI_MOSI, SPI_3, 0},
{SHIELD_1_SPI_MOSI, SPI_4, 0}, {SHIELD_1_SPI_MOSI, SPI_4, 0},
{NC , NC , 0} {NC, NC, 0}
}; };
static const PinMap PinMap_SPI_MISO[] = { static const PinMap PinMap_SPI_MISO[] = {
@ -46,7 +46,7 @@ static const PinMap PinMap_SPI_MISO[] = {
{ADC_MISO, SPI_2, 0}, {ADC_MISO, SPI_2, 0},
{SHIELD_0_SPI_MISO, SPI_3, 0}, {SHIELD_0_SPI_MISO, SPI_3, 0},
{SHIELD_1_SPI_MISO, SPI_4, 0}, {SHIELD_1_SPI_MISO, SPI_4, 0},
{NC , NC , 0} {NC, NC, 0}
}; };
static const PinMap PinMap_SPI_SSEL[] = { static const PinMap PinMap_SPI_SSEL[] = {
@ -55,30 +55,31 @@ static const PinMap PinMap_SPI_SSEL[] = {
{ADC_SSEL, SPI_2, 0}, {ADC_SSEL, SPI_2, 0},
{SHIELD_0_SPI_nCS, SPI_3, 0}, {SHIELD_0_SPI_nCS, SPI_3, 0},
{SHIELD_1_SPI_nCS, SPI_4, 0}, {SHIELD_1_SPI_nCS, SPI_4, 0},
{NC , NC , 0} {NC, NC, 0}
}; };
static inline int ssp_disable(spi_t *obj); static inline int ssp_disable(spi_t *obj);
static inline int ssp_enable(spi_t *obj); static inline int ssp_enable(spi_t *obj);
void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) { void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
{
int altfunction[4]; int altfunction[4];
// determine the SPI to use // determine the SPI to use
SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso); SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel); SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
obj->spi = (MPS2_SSP_TypeDef*)pinmap_merge(spi_data, spi_cntl); obj->spi = (MPS2_SSP_TypeDef *)pinmap_merge(spi_data, spi_cntl);
if ((int)obj->spi == NC) { if ((int)obj->spi == NC) {
error("SPI pinout mapping failed"); error("SPI pinout mapping failed");
} }
// enable power and clocking // enable power and clocking
switch ((int)obj->spi) { switch ((int)obj->spi) {
case (int)SPI_0: case (int)SPI_0:
obj->spi->CR1 = 0; obj->spi->CR1 = 0;
obj->spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8; obj->spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8;
obj->spi->CPSR = SSP_CPSR_DFLT; obj->spi->CPSR = SSP_CPSR_DFLT;
@ -87,23 +88,23 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel
obj->spi->CR1 = SSP_CR1_SSE_Msk; obj->spi->CR1 = SSP_CR1_SSE_Msk;
obj->spi->ICR = 0x3; obj->spi->ICR = 0x3;
break; break;
case (int)SPI_1: case (int)SPI_1:
/* Configure SSP used for LCD */ /* Configure SSP used for LCD */
obj->spi->CR1 = 0; /* Synchronous serial port disable */ obj->spi->CR1 = 0; /* Synchronous serial port disable */
obj->spi->DMACR = 0; /* Disable FIFO DMA */ obj->spi->DMACR = 0; /* Disable FIFO DMA */
obj->spi->IMSC = 0; /* Mask all FIFO/IRQ interrupts */ obj->spi->IMSC = 0; /* Mask all FIFO/IRQ interrupts */
obj->spi->ICR = ((1ul << 0) | /* Clear SSPRORINTR interrupt */ obj->spi->ICR = ((1ul << 0) | /* Clear SSPRORINTR interrupt */
(1ul << 1) ); /* Clear SSPRTINTR interrupt */ (1ul << 1)); /* Clear SSPRTINTR interrupt */
obj->spi->CR0 = ((7ul << 0) | /* 8 bit data size */ obj->spi->CR0 = ((7ul << 0) | /* 8 bit data size */
(0ul << 4) | /* Motorola frame format */ (0ul << 4) | /* Motorola frame format */
(0ul << 6) | /* CPOL = 0 */ (0ul << 6) | /* CPOL = 0 */
(0ul << 7) | /* CPHA = 0 */ (0ul << 7) | /* CPHA = 0 */
(1ul << 8) ); /* Set serial clock rate */ (1ul << 8)); /* Set serial clock rate */
obj->spi->CPSR = (2ul << 0); /* set SSP clk to 6MHz (6.6MHz max) */ obj->spi->CPSR = (2ul << 0); /* set SSP clk to 6MHz (6.6MHz max) */
obj->spi->CR1 = ((1ul << 1) | /* Synchronous serial port enable */ obj->spi->CR1 = ((1ul << 1) | /* Synchronous serial port enable */
(0ul << 2) ); /* Device configured as master */ (0ul << 2)); /* Device configured as master */
break; break;
case (int)SPI_2: case (int)SPI_2:
obj->spi->CR1 = 0; obj->spi->CR1 = 0;
obj->spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8; obj->spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8;
obj->spi->CPSR = SSP_CPSR_DFLT; obj->spi->CPSR = SSP_CPSR_DFLT;
@ -112,7 +113,7 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel
obj->spi->CR1 = SSP_CR1_SSE_Msk; obj->spi->CR1 = SSP_CR1_SSE_Msk;
obj->spi->ICR = 0x3; obj->spi->ICR = 0x3;
break; break;
case (int)SPI_3: case (int)SPI_3:
obj->spi->CR1 = 0; obj->spi->CR1 = 0;
obj->spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8; obj->spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8;
obj->spi->CPSR = SSP_CPSR_DFLT; obj->spi->CPSR = SSP_CPSR_DFLT;
@ -121,7 +122,7 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel
obj->spi->CR1 = SSP_CR1_SSE_Msk; obj->spi->CR1 = SSP_CR1_SSE_Msk;
obj->spi->ICR = 0x3; obj->spi->ICR = 0x3;
break; break;
case (int)SPI_4: case (int)SPI_4:
obj->spi->CR1 = 0; obj->spi->CR1 = 0;
obj->spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8; obj->spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8;
obj->spi->CPSR = SSP_CPSR_DFLT; obj->spi->CPSR = SSP_CPSR_DFLT;
@ -132,23 +133,39 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel
break; break;
} }
if(mosi != NC){ altfunction[0] = 1;}else{ altfunction[0] = 0;} if (mosi != NC) {
if(miso != NC){ altfunction[1] = 1;}else{ altfunction[1] = 0;} altfunction[0] = 1;
if(sclk != NC){ altfunction[2] = 1;}else{ altfunction[2] = 0;} } else {
if(ssel != NC){ altfunction[3] = 1;}else{ altfunction[3] = 0;} altfunction[0] = 0;
}
if (miso != NC) {
altfunction[1] = 1;
} else {
altfunction[1] = 0;
}
if (sclk != NC) {
altfunction[2] = 1;
} else {
altfunction[2] = 0;
}
if (ssel != NC) {
altfunction[3] = 1;
} else {
altfunction[3] = 0;
}
// enable alt function // enable alt function
switch ((int)obj->spi) { switch ((int)obj->spi) {
case (int)SPI_2: case (int)SPI_2:
CMSDK_GPIO1->ALTFUNCSET |= (altfunction[2]<<3 | altfunction[0]<<2 | altfunction[1]<<1 | altfunction[3]); CMSDK_GPIO1->ALTFUNCSET |= (altfunction[2] << 3 | altfunction[0] << 2 | altfunction[1] << 1 | altfunction[3]);
break; break;
case (int)SPI_3: case (int)SPI_3:
CMSDK_GPIO0->ALTFUNCSET |= (altfunction[1]<<14 | altfunction[0]<<13 | altfunction[3]<<12 | altfunction[2]<<11); CMSDK_GPIO0->ALTFUNCSET |= (altfunction[1] << 14 | altfunction[0] << 13 | altfunction[3] << 12 | altfunction[2] << 11);
break; break;
case (int)SPI_4: case (int)SPI_4:
CMSDK_GPIO2->ALTFUNCSET |= (altfunction[2]<<12 | altfunction[1]<<8 | altfunction[0]<<7 | altfunction[3]<<6); CMSDK_GPIO2->ALTFUNCSET |= (altfunction[2] << 12 | altfunction[1] << 8 | altfunction[0] << 7 | altfunction[3] << 6);
break; break;
} }
// set default format and frequency // set default format and frequency
if (ssel == NC) { if (ssel == NC) {
@ -172,7 +189,8 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel
void spi_free(spi_t *obj) {} void spi_free(spi_t *obj) {}
void spi_format(spi_t *obj, int bits, int mode, int slave) { void spi_format(spi_t *obj, int bits, int mode, int slave)
{
ssp_disable(obj); ssp_disable(obj);
if (!(bits >= 4 && bits <= 16) || !(mode >= 0 && mode <= 3)) { if (!(bits >= 4 && bits <= 16) || !(mode >= 0 && mode <= 3)) {
error("SPI format error"); error("SPI format error");
@ -190,27 +208,28 @@ void spi_format(spi_t *obj, int bits, int mode, int slave) {
uint32_t tmp = obj->spi->CR0; uint32_t tmp = obj->spi->CR0;
tmp &= ~(0xFFFF); tmp &= ~(0xFFFF);
tmp |= DSS << 0 tmp |= DSS << 0
| FRF << 4 | FRF << 4
| SPO << 6 | SPO << 6
| SPH << 7; | SPH << 7;
obj->spi->CR0 = tmp; obj->spi->CR0 = tmp;
tmp = obj->spi->CR1; tmp = obj->spi->CR1;
tmp &= ~(0xD); tmp &= ~(0xD);
tmp |= 0 << 0 // LBM - loop back mode - off tmp |= 0 << 0 // LBM - loop back mode - off
| ((slave) ? 1 : 0) << 2 // MS - master slave mode, 1 = slave | ((slave) ? 1 : 0) << 2 // MS - master slave mode, 1 = slave
| 0 << 3; // SOD - slave output disable - na | 0 << 3; // SOD - slave output disable - na
obj->spi->CR1 = tmp; obj->spi->CR1 = tmp;
ssp_enable(obj); ssp_enable(obj);
} }
void spi_frequency(spi_t *obj, int hz) { void spi_frequency(spi_t *obj, int hz)
{
ssp_disable(obj); ssp_disable(obj);
uint32_t PCLK = SystemCoreClock; uint32_t PCLK = SystemCoreClock;
int prescaler; int prescaler;
for (prescaler = 2; prescaler <= 254; prescaler += 2) { for (prescaler = 2; prescaler <= 254; prescaler += 2) {
int prescale_hz = PCLK / prescaler; int prescale_hz = PCLK / prescaler;
@ -233,43 +252,52 @@ void spi_frequency(spi_t *obj, int hz) {
error("Couldn't setup requested SPI frequency"); error("Couldn't setup requested SPI frequency");
} }
static inline int ssp_disable(spi_t *obj) { static inline int ssp_disable(spi_t *obj)
{
return obj->spi->CR1 &= ~(1 << 1); return obj->spi->CR1 &= ~(1 << 1);
} }
static inline int ssp_enable(spi_t *obj) { static inline int ssp_enable(spi_t *obj)
{
return obj->spi->CR1 |= SSP_CR1_SSE_Msk; return obj->spi->CR1 |= SSP_CR1_SSE_Msk;
} }
static inline int ssp_readable(spi_t *obj) { static inline int ssp_readable(spi_t *obj)
{
return obj->spi->SR & (1 << 2); return obj->spi->SR & (1 << 2);
} }
static inline int ssp_writeable(spi_t *obj) { static inline int ssp_writeable(spi_t *obj)
{
return obj->spi->SR & SSP_SR_BSY_Msk; return obj->spi->SR & SSP_SR_BSY_Msk;
} }
static inline void ssp_write(spi_t *obj, int value) { static inline void ssp_write(spi_t *obj, int value)
{
obj->spi->DR = value; obj->spi->DR = value;
while (ssp_writeable(obj)); while (ssp_writeable(obj));
} }
static inline int ssp_read(spi_t *obj) { static inline int ssp_read(spi_t *obj)
{
int read_DR = obj->spi->DR; int read_DR = obj->spi->DR;
return read_DR; return read_DR;
} }
static inline int ssp_busy(spi_t *obj) { static inline int ssp_busy(spi_t *obj)
{
return (obj->spi->SR & (1 << 4)) ? (1) : (0); return (obj->spi->SR & (1 << 4)) ? (1) : (0);
} }
int spi_master_write(spi_t *obj, int value) { int spi_master_write(spi_t *obj, int value)
{
ssp_write(obj, value); ssp_write(obj, value);
while (obj->spi->SR & SSP_SR_BSY_Msk); /* Wait for send to finish */ while (obj->spi->SR & SSP_SR_BSY_Msk); /* Wait for send to finish */
return (ssp_read(obj)); return (ssp_read(obj));
} }
int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
char *rx_buffer, int rx_length, char write_fill) { char *rx_buffer, int rx_length, char write_fill)
{
int total = (tx_length > rx_length) ? tx_length : rx_length; int total = (tx_length > rx_length) ? tx_length : rx_length;
for (int i = 0; i < total; i++) { for (int i = 0; i < total; i++) {
@ -283,19 +311,23 @@ int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
return total; return total;
} }
int spi_slave_receive(spi_t *obj) { int spi_slave_receive(spi_t *obj)
{
return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0); return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0);
} }
int spi_slave_read(spi_t *obj) { int spi_slave_read(spi_t *obj)
{
return obj->spi->DR; return obj->spi->DR;
} }
void spi_slave_write(spi_t *obj, int value) { void spi_slave_write(spi_t *obj, int value)
{
while (ssp_writeable(obj) == 0) ; while (ssp_writeable(obj) == 0) ;
obj->spi->DR = value; obj->spi->DR = value;
} }
int spi_busy(spi_t *obj) { int spi_busy(spi_t *obj)
{
return ssp_busy(obj); return ssp_busy(obj);
} }

10
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/spi_def.h
View File

@ -107,11 +107,11 @@
#define EERDSR_BP1 0x0008 // Block protect 1 #define EERDSR_BP1 0x0008 // Block protect 1
#define EERDSR_WPEN 0x0080 // Write protect enable #define EERDSR_WPEN 0x0080 // Write protect enable
/* ---------------------------------------------------------------- /* ----------------------------------------------------------------
* *
* Color LCD Support * Color LCD Support
* ================= * =================
*/ */
// Color LCD Controller Internal Register addresses // Color LCD Controller Internal Register addresses
#define LSSPCS_BASE (0x4002804C) // LSSP chip select register #define LSSPCS_BASE (0x4002804C) // LSSP chip select register

35
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/us_ticker.c
View File

@ -23,8 +23,11 @@
int us_ticker_inited = 0; int us_ticker_inited = 0;
void us_ticker_init(void) { void us_ticker_init(void)
if (us_ticker_inited) return; {
if (us_ticker_inited) {
return;
}
us_ticker_inited = 1; us_ticker_inited = 1;
US_TICKER_TIMER1->TimerControl = 0x0; // disable timer US_TICKER_TIMER1->TimerControl = 0x0; // disable timer
@ -42,23 +45,27 @@ void us_ticker_init(void) {
NVIC_EnableIRQ(US_TICKER_TIMER_IRQn); NVIC_EnableIRQ(US_TICKER_TIMER_IRQn);
} }
uint32_t us_ticker_read() { uint32_t us_ticker_read()
uint32_t return_value = 0; {
if (!us_ticker_inited) uint32_t return_value = 0;
if (!us_ticker_inited) {
us_ticker_init(); us_ticker_init();
return_value = ((~US_TICKER_TIMER2->TimerValue)/25); }
return_value = ((~US_TICKER_TIMER2->TimerValue) / 25);
return return_value; return return_value;
} }
void us_ticker_set_interrupt(timestamp_t timestamp) { void us_ticker_set_interrupt(timestamp_t timestamp)
if (!us_ticker_inited) {
if (!us_ticker_inited) {
us_ticker_init(); us_ticker_init();
}
uint32_t delta = timestamp - us_ticker_read(); uint32_t delta = timestamp - us_ticker_read();
// enable interrupt // enable interrupt
US_TICKER_TIMER1->TimerControl = 0x0; // disable timer US_TICKER_TIMER1->TimerControl = 0x0; // disable timer
US_TICKER_TIMER1->TimerControl = 0x62; // enable interrupt and set to 32 bit counter and set to periodic mode US_TICKER_TIMER1->TimerControl = 0x62; // enable interrupt and set to 32 bit counter and set to periodic mode
US_TICKER_TIMER1->TimerLoad = (delta)*25; //initialise the timer value US_TICKER_TIMER1->TimerLoad = (delta) * 25; //initialise the timer value
US_TICKER_TIMER1->TimerControl |= 0x80; //enable timer US_TICKER_TIMER1->TimerControl |= 0x80; //enable timer
} }
@ -68,14 +75,16 @@ void us_ticker_fire_interrupt(void)
} }
void us_ticker_disable_interrupt(void) { void us_ticker_disable_interrupt(void)
{
US_TICKER_TIMER1->TimerControl &= 0xDF; US_TICKER_TIMER1->TimerControl &= 0xDF;
US_TICKER_TIMER2->TimerControl &= 0xDF; US_TICKER_TIMER2->TimerControl &= 0xDF;
} }
void us_ticker_clear_interrupt(void) { void us_ticker_clear_interrupt(void)
{
US_TICKER_TIMER1->TimerIntClr = 0x1; US_TICKER_TIMER1->TimerIntClr = 0x1;
US_TICKER_TIMER2->TimerIntClr = 0x1; US_TICKER_TIMER2->TimerIntClr = 0x1;