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reformat coding styles based on coding guidelines

pull/6862/head
Qinghao Shi 2018-05-18 15:52:55 +01:00
parent 953a735129
commit aab82a78b3
48 changed files with 3675 additions and 3440 deletions
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77
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/ETH_MPS2.c
View File

@ -47,7 +47,7 @@ unsigned int smsc9220_mac_regread(unsigned char regoffset, unsigned int *data)
error = 0; error = 0;
val = SMSC9220->MAC_CSR_CMD; val = SMSC9220->MAC_CSR_CMD;
if(!(val & ((unsigned int)1 << 31))) { // Make sure there's no pending operation if (!(val & ((unsigned int)1 << 31))) { // Make sure there's no pending operation
maccmd = 0; maccmd = 0;
maccmd |= regoffset; maccmd |= regoffset;
maccmd |= ((unsigned int)1 << 30); // Indicates read maccmd |= ((unsigned int)1 << 30); // Indicates read
@ -59,13 +59,13 @@ unsigned int smsc9220_mac_regread(unsigned char regoffset, unsigned int *data)
val = SMSC9220->BYTE_TEST; // A no-op read. val = SMSC9220->BYTE_TEST; // A no-op read.
wait_ms(1); wait_ms(1);
timedout--; timedout--;
} while(timedout && (SMSC9220->MAC_CSR_CMD & ((unsigned int)1 << 31))); } while (timedout && (SMSC9220->MAC_CSR_CMD & ((unsigned int)1 << 31)));
if(!timedout) { if (!timedout) {
error = 1; error = 1;
} } else {
else
*data = SMSC9220->MAC_CSR_DATA; *data = SMSC9220->MAC_CSR_DATA;
}
} else { } else {
*data = 0; *data = 0;
} }
@ -80,7 +80,7 @@ unsigned int smsc9220_mac_regwrite(unsigned char regoffset, unsigned int data)
error = 0; error = 0;
read = SMSC9220->MAC_CSR_CMD; read = SMSC9220->MAC_CSR_CMD;
if(!(read & ((unsigned int)1 << 31))) { // Make sure there's no pending operation if (!(read & ((unsigned int)1 << 31))) { // Make sure there's no pending operation
SMSC9220->MAC_CSR_DATA = data; // Store data. SMSC9220->MAC_CSR_DATA = data; // Store data.
maccmd = 0; maccmd = 0;
maccmd |= regoffset; maccmd |= regoffset;
@ -93,9 +93,9 @@ unsigned int smsc9220_mac_regwrite(unsigned char regoffset, unsigned int data)
read = SMSC9220->BYTE_TEST; // A no-op read. read = SMSC9220->BYTE_TEST; // A no-op read.
wait_ms(1); wait_ms(1);
timedout--; timedout--;
} while(timedout && (SMSC9220->MAC_CSR_CMD & ((unsigned int)1 << 31))); } while (timedout && (SMSC9220->MAC_CSR_CMD & ((unsigned int)1 << 31)));
if(!timedout) { if (!timedout) {
error = 1; error = 1;
} }
} else { } else {
@ -106,14 +106,15 @@ unsigned int smsc9220_mac_regwrite(unsigned char regoffset, unsigned int data)
unsigned int smsc9220_phy_regread(unsigned char regoffset, unsigned short *data) unsigned int smsc9220_phy_regread(unsigned char regoffset, unsigned short *data)
{ {
unsigned int val, phycmd; int error; unsigned int val, phycmd;
int error;
int timedout; int timedout;
error = 0; error = 0;
smsc9220_mac_regread(SMSC9220_MAC_MII_ACC, &val); smsc9220_mac_regread(SMSC9220_MAC_MII_ACC, &val);
if(!(val & 1)) { // Not busy if (!(val & 1)) { // Not busy
phycmd = 0; phycmd = 0;
phycmd |= (1 << 11); // 1 to [15:11] phycmd |= (1 << 11); // 1 to [15:11]
phycmd |= ((regoffset & 0x1F) << 6); // Put regoffset to [10:6] phycmd |= ((regoffset & 0x1F) << 6); // Put regoffset to [10:6]
@ -127,14 +128,14 @@ unsigned int smsc9220_phy_regread(unsigned char regoffset, unsigned short *data)
do { do {
wait_ms(1); wait_ms(1);
timedout--; timedout--;
smsc9220_mac_regread(SMSC9220_MAC_MII_ACC,&val); smsc9220_mac_regread(SMSC9220_MAC_MII_ACC, &val);
} while(timedout && (val & ((unsigned int)1 << 0))); } while (timedout && (val & ((unsigned int)1 << 0)));
if(!timedout) { if (!timedout) {
error = 1; error = 1;
} } else {
else
smsc9220_mac_regread(SMSC9220_MAC_MII_DATA, (unsigned int *)data); smsc9220_mac_regread(SMSC9220_MAC_MII_DATA, (unsigned int *)data);
}
} else { } else {
*data = 0; *data = 0;
@ -144,14 +145,15 @@ unsigned int smsc9220_phy_regread(unsigned char regoffset, unsigned short *data)
unsigned int smsc9220_phy_regwrite(unsigned char regoffset, unsigned short data) unsigned int smsc9220_phy_regwrite(unsigned char regoffset, unsigned short data)
{ {
unsigned int val, phycmd; int error; unsigned int val, phycmd;
int error;
int timedout; int timedout;
error = 0; error = 0;
smsc9220_mac_regread(SMSC9220_MAC_MII_ACC, &val); smsc9220_mac_regread(SMSC9220_MAC_MII_ACC, &val);
if(!(val & 1)) { // Not busy if (!(val & 1)) { // Not busy
smsc9220_mac_regwrite(SMSC9220_MAC_MII_DATA, (data & 0xFFFF)); // Load the data smsc9220_mac_regwrite(SMSC9220_MAC_MII_DATA, (data & 0xFFFF)); // Load the data
phycmd = 0; phycmd = 0;
phycmd |= (1 << 11); // 1 to [15:11] phycmd |= (1 << 11); // 1 to [15:11]
@ -168,9 +170,9 @@ unsigned int smsc9220_phy_regwrite(unsigned char regoffset, unsigned short data)
wait_ms(1); wait_ms(1);
timedout--; timedout--;
smsc9220_mac_regread(SMSC9220_MAC_MII_ACC, &phycmd); smsc9220_mac_regread(SMSC9220_MAC_MII_ACC, &phycmd);
} while(timedout && (phycmd & (1 << 0))); } while (timedout && (phycmd & (1 << 0)));
if(!timedout) { if (!timedout) {
error = 1; error = 1;
} }
@ -198,10 +200,11 @@ unsigned int smsc9220_soft_reset(void)
do { do {
wait_ms(1); wait_ms(1);
timedout--; timedout--;
} while(timedout && (SMSC9220->HW_CFG & 1)); } while (timedout && (SMSC9220->HW_CFG & 1));
if(!timedout) if (!timedout) {
return 1; return 1;
}
return 0; return 0;
} }
@ -209,8 +212,9 @@ unsigned int smsc9220_soft_reset(void)
void smsc9220_set_txfifo(unsigned int val) void smsc9220_set_txfifo(unsigned int val)
{ {
// 2kb minimum, 14kb maximum // 2kb minimum, 14kb maximum
if(val < 2 || val > 14) if (val < 2 || val > 14) {
return; return;
}
SMSC9220->HW_CFG = val << 16; SMSC9220->HW_CFG = val << 16;
} }
@ -226,10 +230,11 @@ unsigned int smsc9220_wait_eeprom(void)
wait_ms(1); wait_ms(1);
timedout--; timedout--;
} while(timedout && (SMSC9220->E2P_CMD & ((unsigned int) 1 << 31))); } while (timedout && (SMSC9220->E2P_CMD & ((unsigned int) 1 << 31)));
if(!timedout) if (!timedout) {
return 1; return 1;
}
return 0; return 0;
} }
@ -246,8 +251,8 @@ unsigned int smsc9220_check_phy(void)
{ {
unsigned short phyid1, phyid2; unsigned short phyid1, phyid2;
smsc9220_phy_regread(SMSC9220_PHY_ID1,&phyid1); smsc9220_phy_regread(SMSC9220_PHY_ID1, &phyid1);
smsc9220_phy_regread(SMSC9220_PHY_ID2,&phyid2); smsc9220_phy_regread(SMSC9220_PHY_ID2, &phyid2);
return ((phyid1 == 0xFFFF && phyid2 == 0xFFFF) || return ((phyid1 == 0xFFFF && phyid2 == 0xFFFF) ||
(phyid1 == 0x0 && phyid2 == 0x0)); (phyid1 == 0x0 && phyid2 == 0x0));
} }
@ -258,13 +263,13 @@ unsigned int smsc9220_reset_phy(void)
int error; int error;
error = 0; error = 0;
if(smsc9220_phy_regread(SMSC9220_PHY_BCONTROL, &read)) { if (smsc9220_phy_regread(SMSC9220_PHY_BCONTROL, &read)) {
error = 1; error = 1;
return error; return error;
} }
read |= (1 << 15); read |= (1 << 15);
if(smsc9220_phy_regwrite(SMSC9220_PHY_BCONTROL, read)) { if (smsc9220_phy_regwrite(SMSC9220_PHY_BCONTROL, read)) {
error = 1; error = 1;
return error; return error;
} }
@ -370,11 +375,11 @@ unsigned int smsc9220_recv_packet(unsigned int *recvbuf, unsigned int *index)
rxfifo_inf = SMSC9220->RX_FIFO_INF; rxfifo_inf = SMSC9220->RX_FIFO_INF;
if(rxfifo_inf & 0xFFFF) { // If there's data if (rxfifo_inf & 0xFFFF) { // If there's data
rxfifo_stat = SMSC9220->RX_STAT_PORT; rxfifo_stat = SMSC9220->RX_STAT_PORT;
if(rxfifo_stat != 0) { // Fetch status of this packet if (rxfifo_stat != 0) { // Fetch status of this packet
pktsize = ((rxfifo_stat >> 16) & 0x3FFF); pktsize = ((rxfifo_stat >> 16) & 0x3FFF);
if(rxfifo_stat & (1 << 15)) { if (rxfifo_stat & (1 << 15)) {
printf("Error occured during receiving of packets on the bus.\n"); printf("Error occured during receiving of packets on the bus.\n");
return 1; return 1;
} else { } else {
@ -384,7 +389,7 @@ unsigned int smsc9220_recv_packet(unsigned int *recvbuf, unsigned int *index)
*/ */
dwords_to_read = (pktsize + 3) >> 2; dwords_to_read = (pktsize + 3) >> 2;
// PIO copy of data received: // PIO copy of data received:
while(dwords_to_read > 0) { while (dwords_to_read > 0) {
recvbuf[*index] = SMSC9220->RX_DATA_PORT; recvbuf[*index] = SMSC9220->RX_DATA_PORT;
(*index)++; (*index)++;
dwords_to_read--; dwords_to_read--;
@ -407,7 +412,7 @@ unsigned int smsc9220_recv_packet(unsigned int *recvbuf, unsigned int *index)
// Does the actual transfer of data to FIFO, note it does no // Does the actual transfer of data to FIFO, note it does no
// fifo availability checking. This should be done by caller. // fifo availability checking. This should be done by caller.
// Assumes the whole frame is transferred at once as a single segment // Assumes the whole frame is transferred at once as a single segment
void smsc9220_xmit_packet(unsigned char * pkt, unsigned int length) void smsc9220_xmit_packet(unsigned char *pkt, unsigned int length)
{ {
unsigned int txcmd_a, txcmd_b; unsigned int txcmd_a, txcmd_b;
unsigned int dwords_to_write; unsigned int dwords_to_write;
@ -432,7 +437,7 @@ void smsc9220_xmit_packet(unsigned char * pkt, unsigned int length)
dwritten = dwords_to_write = (length + 3) >> 2; dwritten = dwords_to_write = (length + 3) >> 2;
// PIO Copy to FIFO. Could replace this with DMA. // PIO Copy to FIFO. Could replace this with DMA.
while(dwords_to_write > 0) { while (dwords_to_write > 0) {
SMSC9220->TX_DATA_PORT = *pktptr; SMSC9220->TX_DATA_PORT = *pktptr;
pktptr++; pktptr++;
dwords_to_write--; dwords_to_write--;
@ -442,8 +447,8 @@ void smsc9220_xmit_packet(unsigned char * pkt, unsigned int length)
xmit_stat2 = SMSC9220->TX_STAT_PORT; xmit_stat2 = SMSC9220->TX_STAT_PORT;
xmit_inf = SMSC9220->TX_FIFO_INF; xmit_inf = SMSC9220->TX_FIFO_INF;
if(xmit_stat2 != 0 ) { if (xmit_stat2 != 0) {
for(i = 0; i < 6; i++) { for (i = 0; i < 6; i++) {
xmit_stat2 = SMSC9220->TX_STAT_PORT; xmit_stat2 = SMSC9220->TX_STAT_PORT;
} }
} }

2
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/ETH_MPS2.h
View File

@ -60,6 +60,6 @@ void smsc9220_set_soft_int(void);
void smsc9220_clear_soft_int(void); void smsc9220_clear_soft_int(void);
unsigned int smsc9220_recv_packet(unsigned int *recvbuf, unsigned int *index); unsigned int smsc9220_recv_packet(unsigned int *recvbuf, unsigned int *index);
void smsc9220_xmit_packet(unsigned char * pkt, unsigned int length); void smsc9220_xmit_packet(unsigned char *pkt, unsigned int length);
#endif #endif

21
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/fpga.c
View File

@ -34,12 +34,9 @@ void i2c_delay(unsigned int tick)
start = MPS2_FPGAIO->COUNTER; start = MPS2_FPGAIO->COUNTER;
end = start + (tick); end = start + (tick);
if(end >= start) if (end >= start) {
{
while (MPS2_FPGAIO->COUNTER >= start && MPS2_FPGAIO->COUNTER < end); while (MPS2_FPGAIO->COUNTER >= start && MPS2_FPGAIO->COUNTER < end);
} } else {
else
{
while (MPS2_FPGAIO->COUNTER >= start); while (MPS2_FPGAIO->COUNTER >= start);
while (MPS2_FPGAIO->COUNTER < end); while (MPS2_FPGAIO->COUNTER < end);
} }
@ -56,12 +53,9 @@ void Sleepms(unsigned int msec)
start = MPS2_FPGAIO->COUNTER; start = MPS2_FPGAIO->COUNTER;
end = start + (25 * msec * 1000); end = start + (25 * msec * 1000);
if(end >= start) if (end >= start) {
{
while (MPS2_FPGAIO->COUNTER >= start && MPS2_FPGAIO->COUNTER < end); while (MPS2_FPGAIO->COUNTER >= start && MPS2_FPGAIO->COUNTER < end);
} } else {
else
{
while (MPS2_FPGAIO->COUNTER >= start); while (MPS2_FPGAIO->COUNTER >= start);
while (MPS2_FPGAIO->COUNTER < end); while (MPS2_FPGAIO->COUNTER < end);
} }
@ -77,12 +71,9 @@ void Sleepus(unsigned int usec)
start = MPS2_FPGAIO->COUNTER; start = MPS2_FPGAIO->COUNTER;
end = start + (25 * usec); end = start + (25 * usec);
if(end >= start) if (end >= start) {
{
while (MPS2_FPGAIO->COUNTER >= start && MPS2_FPGAIO->COUNTER < end); while (MPS2_FPGAIO->COUNTER >= start && MPS2_FPGAIO->COUNTER < end);
} } else {
else
{
while (MPS2_FPGAIO->COUNTER >= start); while (MPS2_FPGAIO->COUNTER >= start);
while (MPS2_FPGAIO->COUNTER < end); while (MPS2_FPGAIO->COUNTER < end);
} }

12
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/mps2_ethernet_api.c
View File

@ -42,11 +42,11 @@ int smsc9220_check_id(void)
id = smsc9220_read_id(); id = smsc9220_read_id();
// If bottom and top halves of the word are the same // If bottom and top halves of the word are the same
if(((id >> 16) & 0xFFFF) == (id & 0xFFFF)) { if (((id >> 16) & 0xFFFF) == (id & 0xFFFF)) {
error = 1; error = 1;
return error; return error;
} }
switch(((id >> 16) & 0xFFFF)) { switch (((id >> 16) & 0xFFFF)) {
case 0x9220: case 0x9220:
break; break;
@ -81,7 +81,7 @@ int smsc9220_check_macaddress(void)
smsc9220_mac_regread(SMSC9220_MAC_ADDRL, &mac_low); smsc9220_mac_regread(SMSC9220_MAC_ADDRL, &mac_low);
if(mac_high != mac_valid_high || mac_low != mac_valid_low) { if (mac_high != mac_valid_high || mac_low != mac_valid_low) {
error = TRUE; error = TRUE;
return error; return error;
} }
@ -97,7 +97,7 @@ void smsc9220_print_mac_registers()
i = 0; i = 0;
read = 0; read = 0;
for(i = 1; i <= 0xC; i++) { for (i = 1; i <= 0xC; i++) {
smsc9220_mac_regread(i, &read); smsc9220_mac_regread(i, &read);
} }
return; return;
@ -111,7 +111,7 @@ void smsc9220_print_phy_registers()
i = 0; i = 0;
read = 0; read = 0;
for(i = 0; i <= 6; i++) { for (i = 0; i <= 6; i++) {
smsc9220_phy_regread(i, &read); smsc9220_phy_regread(i, &read);
} }
smsc9220_phy_regread(i = 17, &read); smsc9220_phy_regread(i = 17, &read);
@ -133,7 +133,7 @@ void smsc9220_print_phy_registers()
Ethernet Device initialize Ethernet Device initialize
*----------------------------------------------------------------------------*/ *----------------------------------------------------------------------------*/
int ethernet_transmission(unsigned char * pkt, unsigned int length) int ethernet_transmission(unsigned char *pkt, unsigned int length)
{ {
smsc9220_xmit_packet(pkt, length); smsc9220_xmit_packet(pkt, length);
return 0; return 0;

2
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/mps2_ethernet_api.h
View File

@ -28,7 +28,7 @@ extern "C" {
// Connection constants // Connection constants
// send ethernet write buffer, returning the packet size sent // send ethernet write buffer, returning the packet size sent
int ethernet_transmission(unsigned char * pkt, unsigned int length); int ethernet_transmission(unsigned char *pkt, unsigned int length);
// recieve from ethernet buffer, returning packet size, or 0 if no packet // recieve from ethernet buffer, returning packet size, or 0 if no packet
int ethernet_reception(unsigned int *recvbuf, unsigned int *index); int ethernet_reception(unsigned int *recvbuf, unsigned int *index);

59
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/CMSDK_CM0.h
View File

@ -40,24 +40,23 @@
#define CMSDK_CM0_H #define CMSDK_CM0_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* ------------------------- Interrupt Number Definition ------------------------ */ /* ------------------------- Interrupt Number Definition ------------------------ */
typedef enum IRQn typedef enum IRQn {
{ /****** Cortex-M0 Processor Exceptions Numbers ***************************************************/
/****** Cortex-M0 Processor Exceptions Numbers ***************************************************/
/* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M0 device */ /* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M0 device */
NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M0 Non Maskable Interrupt */ NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M0 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
/* ---------------------- CMSDK_CM0 Specific Interrupt Numbers ------------------ */ /* ---------------------- CMSDK_CM0 Specific Interrupt Numbers ------------------ */
UARTRX0_IRQn = 0, /*!< UART 0 RX Interrupt */ UARTRX0_IRQn = 0, /*!< UART 0 RX Interrupt */
UARTTX0_IRQn = 1, /*!< UART 0 TX Interrupt */ UARTTX0_IRQn = 1, /*!< UART 0 TX Interrupt */
UARTRX1_IRQn = 2, /*!< UART 1 RX Interrupt */ UARTRX1_IRQn = 2, /*!< UART 1 RX Interrupt */
@ -113,23 +112,22 @@ typedef enum IRQn
/* ------------------- Start of section using anonymous unions ------------------ */ /* ------------------- Start of section using anonymous unions ------------------ */
#if defined ( __CC_ARM ) #if defined ( __CC_ARM )
#pragma push #pragma push
#pragma anon_unions #pragma anon_unions
#elif defined(__ICCARM__) #elif defined(__ICCARM__)
#pragma language=extended #pragma language=extended
#elif defined(__GNUC__) #elif defined(__GNUC__)
/* anonymous unions are enabled by default */ /* anonymous unions are enabled by default */
#elif defined(__TMS470__) #elif defined(__TMS470__)
/* anonymous unions are enabled by default */ /* anonymous unions are enabled by default */
#elif defined(__TASKING__) #elif defined(__TASKING__)
#pragma warning 586 #pragma warning 586
#else #else
#warning Not supported compiler type #warning Not supported compiler type
#endif #endif
/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
typedef struct typedef struct {
{
__IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */ __IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */
__IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */ __IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */
__IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */ __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */
@ -196,8 +194,7 @@ typedef struct
/*----------------------------- Timer (TIMER) -------------------------------*/ /*----------------------------- Timer (TIMER) -------------------------------*/
typedef struct typedef struct {
{
__IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */ __IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */
__IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */ __IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */
__IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */ __IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */
@ -236,8 +233,7 @@ typedef struct
/*------------- Timer (TIM) --------------------------------------------------*/ /*------------- Timer (TIM) --------------------------------------------------*/
typedef struct typedef struct {
{
__IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */ __IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
__I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */ __I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
__IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */ __IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
@ -331,8 +327,7 @@ typedef struct
#define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /* CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */ #define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /* CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */
typedef struct typedef struct {
{
__IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */ __IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */
__I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */ __I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */
__IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */ __IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */
@ -380,8 +375,7 @@ typedef struct
/*-------------------- General Purpose Input Output (GPIO) -------------------*/ /*-------------------- General Purpose Input Output (GPIO) -------------------*/
typedef struct typedef struct {
{
__IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */ __IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */
__IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */ __IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */
uint32_t RESERVED0[2]; uint32_t RESERVED0[2];
@ -454,8 +448,7 @@ typedef struct
/*------------- System Control (SYSCON) --------------------------------------*/ /*------------- System Control (SYSCON) --------------------------------------*/
typedef struct typedef struct {
{
__IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */ __IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */
__IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */ __IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */
__IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */ __IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */
@ -495,8 +488,7 @@ typedef struct
/*------------- PL230 uDMA (PL230) --------------------------------------*/ /*------------- PL230 uDMA (PL230) --------------------------------------*/
typedef struct typedef struct {
{
__I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */ __I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */
__O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */ __O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */
__IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */ __IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */
@ -591,8 +583,7 @@ typedef struct
/*------------------- Watchdog ----------------------------------------------*/ /*------------------- Watchdog ----------------------------------------------*/
typedef struct typedef struct {
{
__IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */ __IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */
__I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */ __I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */
@ -605,7 +596,7 @@ typedef struct
uint32_t RESERVED1[191]; uint32_t RESERVED1[191];
__IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */ __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */
__O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */ __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */
}CMSDK_WATCHDOG_TypeDef; } CMSDK_WATCHDOG_TypeDef;
#define CMSDK_Watchdog_LOAD_Pos 0 /* CMSDK_Watchdog LOAD: LOAD Position */ #define CMSDK_Watchdog_LOAD_Pos 0 /* CMSDK_Watchdog LOAD: LOAD Position */
#define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /* CMSDK_Watchdog LOAD: LOAD Mask */ #define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /* CMSDK_Watchdog LOAD: LOAD Mask */
@ -641,17 +632,17 @@ typedef struct
/* -------------------- End of section using anonymous unions ------------------- */ /* -------------------- End of section using anonymous unions ------------------- */
#if defined ( __CC_ARM ) #if defined ( __CC_ARM )
#pragma pop #pragma pop
#elif defined(__ICCARM__) #elif defined(__ICCARM__)
/* leave anonymous unions enabled */ /* leave anonymous unions enabled */
#elif defined(__GNUC__) #elif defined(__GNUC__)
/* anonymous unions are enabled by default */ /* anonymous unions are enabled by default */
#elif defined(__TMS470__) #elif defined(__TMS470__)
/* anonymous unions are enabled by default */ /* anonymous unions are enabled by default */
#elif defined(__TASKING__) #elif defined(__TASKING__)
#pragma warning restore #pragma warning restore
#else #else
#warning Not supported compiler type #warning Not supported compiler type
#endif #endif

10
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/cmsis_nvic.c
View File

@ -36,18 +36,20 @@
#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Location of vectors in RAM #define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Location of vectors in RAM
#define NVIC_FLASH_VECTOR_ADDRESS (0x00000000) // Initial vector position in flash #define NVIC_FLASH_VECTOR_ADDRESS (0x00000000) // Initial vector position in flash
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
// int i; // int i;
// Space for dynamic vectors, initialised to allocate in R/W // Space for dynamic vectors, initialised to allocate in R/W
static volatile uint32_t* vectors = (uint32_t*)NVIC_FLASH_VECTOR_ADDRESS; static volatile uint32_t *vectors = (uint32_t *)NVIC_FLASH_VECTOR_ADDRESS;
// Set the vector // Set the vector
vectors[IRQn + 16] = vector; vectors[IRQn + 16] = vector;
} }
uint32_t NVIC_GetVector(IRQn_Type IRQn) { uint32_t NVIC_GetVector(IRQn_Type IRQn)
{
// We can always read vectors at 0x0, as the addresses are remapped // We can always read vectors at 0x0, as the addresses are remapped
uint32_t *vectors = (uint32_t*)NVIC_FLASH_VECTOR_ADDRESS; uint32_t *vectors = (uint32_t *)NVIC_FLASH_VECTOR_ADDRESS;
// Return the vector // Return the vector
return vectors[IRQn + 16]; return vectors[IRQn + 16];

12
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/peripherallink.h
View File

@ -37,17 +37,17 @@
#define __DEVICE_H #define __DEVICE_H
#if defined CMSDK_CM0 #if defined CMSDK_CM0
#include "CMSDK_CM0.h" /* device specific header file */ #include "CMSDK_CM0.h" /* device specific header file */
#elif defined CMSDK_CM0plus #elif defined CMSDK_CM0plus
#include "CMSDK_CM0plus.h" /* device specific header file */ #include "CMSDK_CM0plus.h" /* device specific header file */
#elif defined CMSDK_CM3 #elif defined CMSDK_CM3
#include "CMSDK_CM3.h" /* device specific header file */ #include "CMSDK_CM3.h" /* device specific header file */
#elif defined CMSDK_CM4 #elif defined CMSDK_CM4
#include "CMSDK_CM4.h" /* device specific header file */ #include "CMSDK_CM4.h" /* device specific header file */
#elif defined CMSDK_CM7 #elif defined CMSDK_CM7
#include "CMSDK_CM7.h" /* device specific header file */ #include "CMSDK_CM7.h" /* device specific header file */
#else #else
#warning "no appropriate header file found!" #warning "no appropriate header file found!"
#endif #endif
#endif /* __DEVICE_H */ #endif /* __DEVICE_H */

4
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/system_CMSDK_CM0.c
View File

@ -64,7 +64,7 @@ uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Cloc
* @brief Updates the SystemCoreClock with current core Clock * @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers. * retrieved from cpu registers.
*/ */
void SystemCoreClockUpdate (void) void SystemCoreClockUpdate(void)
{ {
SystemCoreClock = __SYSTEM_CLOCK; SystemCoreClock = __SYSTEM_CLOCK;
@ -80,7 +80,7 @@ void SystemCoreClockUpdate (void)
* @brief Setup the microcontroller system. * @brief Setup the microcontroller system.
* Initialize the System. * Initialize the System.
*/ */
void SystemInit (void) void SystemInit(void)
{ {
SystemCoreClock = __SYSTEM_CLOCK; SystemCoreClock = __SYSTEM_CLOCK;

4
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/system_CMSDK_CM0.h
View File

@ -56,7 +56,7 @@ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) *
* @brief Setup the microcontroller system. * @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable. * Initialize the System and update the SystemCoreClock variable.
*/ */
extern void SystemInit (void); extern void SystemInit(void);
/** /**
* Update SystemCoreClock variable * Update SystemCoreClock variable
@ -67,7 +67,7 @@ extern void SystemInit (void);
* @brief Updates the SystemCoreClock with current core Clock * @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers. * retrieved from cpu registers.
*/ */
extern void SystemCoreClockUpdate (void); extern void SystemCoreClockUpdate(void);
#ifdef __cplusplus #ifdef __cplusplus
} }

59
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/CMSDK_CM0plus.h
View File

@ -40,24 +40,23 @@
#define CMSDK_CM0plus_H #define CMSDK_CM0plus_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* ------------------------- Interrupt Number Definition ------------------------ */ /* ------------------------- Interrupt Number Definition ------------------------ */
typedef enum IRQn typedef enum IRQn {
{ /****** Cortex-M0 Processor Exceptions Numbers ***************************************************/
/****** Cortex-M0 Processor Exceptions Numbers ***************************************************/
/* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M0 device */ /* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M0 device */
NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M0 Non Maskable Interrupt */ NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M0 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
/* ---------------------- CMSDK_CM0 Specific Interrupt Numbers ------------------ */ /* ---------------------- CMSDK_CM0 Specific Interrupt Numbers ------------------ */
UARTRX0_IRQn = 0, /*!< UART 0 RX Interrupt */ UARTRX0_IRQn = 0, /*!< UART 0 RX Interrupt */
UARTTX0_IRQn = 1, /*!< UART 0 TX Interrupt */ UARTTX0_IRQn = 1, /*!< UART 0 TX Interrupt */
UARTRX1_IRQn = 2, /*!< UART 1 RX Interrupt */ UARTRX1_IRQn = 2, /*!< UART 1 RX Interrupt */
@ -114,23 +113,22 @@ typedef enum IRQn
/* ------------------- Start of section using anonymous unions ------------------ */ /* ------------------- Start of section using anonymous unions ------------------ */
#if defined ( __CC_ARM ) #if defined ( __CC_ARM )
#pragma push #pragma push
#pragma anon_unions #pragma anon_unions
#elif defined(__ICCARM__) #elif defined(__ICCARM__)
#pragma language=extended #pragma language=extended
#elif defined(__GNUC__) #elif defined(__GNUC__)
/* anonymous unions are enabled by default */ /* anonymous unions are enabled by default */
#elif defined(__TMS470__) #elif defined(__TMS470__)
/* anonymous unions are enabled by default */ /* anonymous unions are enabled by default */
#elif defined(__TASKING__) #elif defined(__TASKING__)
#pragma warning 586 #pragma warning 586
#else #else
#warning Not supported compiler type #warning Not supported compiler type
#endif #endif
/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
typedef struct typedef struct {
{
__IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */ __IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */
__IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */ __IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */
__IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */ __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */
@ -197,8 +195,7 @@ typedef struct
/*----------------------------- Timer (TIMER) -------------------------------*/ /*----------------------------- Timer (TIMER) -------------------------------*/
typedef struct typedef struct {
{
__IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */ __IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */
__IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */ __IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */
__IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */ __IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */
@ -237,8 +234,7 @@ typedef struct
/*------------- Timer (TIM) --------------------------------------------------*/ /*------------- Timer (TIM) --------------------------------------------------*/
typedef struct typedef struct {
{
__IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */ __IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
__I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */ __I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
__IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */ __IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
@ -332,8 +328,7 @@ typedef struct
#define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /* CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */ #define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /* CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */
typedef struct typedef struct {
{
__IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */ __IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */
__I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */ __I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */
__IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */ __IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */
@ -381,8 +376,7 @@ typedef struct
/*-------------------- General Purpose Input Output (GPIO) -------------------*/ /*-------------------- General Purpose Input Output (GPIO) -------------------*/
typedef struct typedef struct {
{
__IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */ __IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */
__IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */ __IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */
uint32_t RESERVED0[2]; uint32_t RESERVED0[2];
@ -455,8 +449,7 @@ typedef struct
/*------------- System Control (SYSCON) --------------------------------------*/ /*------------- System Control (SYSCON) --------------------------------------*/
typedef struct typedef struct {
{
__IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */ __IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */
__IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */ __IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */
__IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */ __IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */
@ -496,8 +489,7 @@ typedef struct
/*------------- PL230 uDMA (PL230) --------------------------------------*/ /*------------- PL230 uDMA (PL230) --------------------------------------*/
typedef struct typedef struct {
{
__I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */ __I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */
__O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */ __O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */
__IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */ __IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */
@ -592,8 +584,7 @@ typedef struct
/*------------------- Watchdog ----------------------------------------------*/ /*------------------- Watchdog ----------------------------------------------*/
typedef struct typedef struct {
{
__IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */ __IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */
__I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */ __I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */
@ -606,7 +597,7 @@ typedef struct
uint32_t RESERVED1[191]; uint32_t RESERVED1[191];
__IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */ __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */
__O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */ __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */
}CMSDK_WATCHDOG_TypeDef; } CMSDK_WATCHDOG_TypeDef;
#define CMSDK_Watchdog_LOAD_Pos 0 /* CMSDK_Watchdog LOAD: LOAD Position */ #define CMSDK_Watchdog_LOAD_Pos 0 /* CMSDK_Watchdog LOAD: LOAD Position */
#define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /* CMSDK_Watchdog LOAD: LOAD Mask */ #define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /* CMSDK_Watchdog LOAD: LOAD Mask */
@ -642,17 +633,17 @@ typedef struct
/* -------------------- End of section using anonymous unions ------------------- */ /* -------------------- End of section using anonymous unions ------------------- */
#if defined ( __CC_ARM ) #if defined ( __CC_ARM )
#pragma pop #pragma pop
#elif defined(__ICCARM__) #elif defined(__ICCARM__)
/* leave anonymous unions enabled */ /* leave anonymous unions enabled */
#elif defined(__GNUC__) #elif defined(__GNUC__)
/* anonymous unions are enabled by default */ /* anonymous unions are enabled by default */
#elif defined(__TMS470__) #elif defined(__TMS470__)
/* anonymous unions are enabled by default */ /* anonymous unions are enabled by default */
#elif defined(__TASKING__) #elif defined(__TASKING__)
#pragma warning restore #pragma warning restore
#else #else
#warning Not supported compiler type #warning Not supported compiler type
#endif #endif

78
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/SMM_MPS2.h
View File

@ -46,8 +46,7 @@
/* FPGA System Register declaration */ /* FPGA System Register declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct typedef struct {
{
__IO uint32_t LED; // Offset: 0x000 (R/W) LED connections __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections
// [31:2] : Reserved // [31:2] : Reserved
// [1:0] : LEDs // [1:0] : LEDs
@ -107,8 +106,7 @@ typedef struct
/* SCC Register declaration */ /* SCC Register declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct // typedef struct { //
{
__IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT __IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT
// [31:1] : Reserved // [31:1] : Reserved
// [0] 1 : REMAP BlockRam to ZBT // [0] 1 : REMAP BlockRam to ZBT
@ -166,8 +164,7 @@ typedef struct //
/* SSP Peripheral declaration */ /* SSP Peripheral declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf typedef struct { // Document DDI0194G_ssp_pl022_r1p3_trm.pdf
{
__IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0 __IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0
// [31:16] : Reserved // [31:16] : Reserved
// [15:8] : Serial clock rate // [15:8] : Serial clock rate
@ -314,8 +311,7 @@ typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf
/* Audio and Touch Screen (I2C) Peripheral declaration */ /* Audio and Touch Screen (I2C) Peripheral declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct typedef struct {
{
union { union {
__O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W) __O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W)
__I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ ) __I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ )
@ -331,8 +327,7 @@ typedef struct
/* Audio I2S Peripheral declaration */ /* Audio I2S Peripheral declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct typedef struct {
{
/*!< Offset: 0x000 CONTROL Register (R/W) */ /*!< Offset: 0x000 CONTROL Register (R/W) */
__IO uint32_t CONTROL; // <h> CONTROL </h> __IO uint32_t CONTROL; // <h> CONTROL </h>
// <o.0> TX Enable // <o.0> TX Enable
@ -486,44 +481,43 @@ typedef struct
/* SMSC9220 Register Definitions */ /* SMSC9220 Register Definitions */
/******************************************************************************/ /******************************************************************************/
typedef struct // SMSC LAN9220 typedef struct { // SMSC LAN9220
{ __I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0)
__I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0)
uint32_t RESERVED1[0x7]; uint32_t RESERVED1[0x7];
__O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20) __O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20)
uint32_t RESERVED2[0x7]; uint32_t RESERVED2[0x7];
__I uint32_t RX_STAT_PORT; // Receive FIFO status port (offset 0x40) __I uint32_t RX_STAT_PORT; // Receive FIFO status port (offset 0x40)
__I uint32_t RX_STAT_PEEK; // Receive FIFO status peek (offset 0x44) __I uint32_t RX_STAT_PEEK; // Receive FIFO status peek (offset 0x44)
__I uint32_t TX_STAT_PORT; // Transmit FIFO status port (offset 0x48) __I uint32_t TX_STAT_PORT; // Transmit FIFO status port (offset 0x48)
__I uint32_t TX_STAT_PEEK; // Transmit FIFO status peek (offset 0x4C) __I uint32_t TX_STAT_PEEK; // Transmit FIFO status peek (offset 0x4C)
__I uint32_t ID_REV; // Chip ID and Revision (offset 0x50) __I uint32_t ID_REV; // Chip ID and Revision (offset 0x50)
__IO uint32_t IRQ_CFG; // Main Interrupt Configuration (offset 0x54) __IO uint32_t IRQ_CFG; // Main Interrupt Configuration (offset 0x54)
__IO uint32_t INT_STS; // Interrupt Status (offset 0x58) __IO uint32_t INT_STS; // Interrupt Status (offset 0x58)
__IO uint32_t INT_EN; // Interrupt Enable Register (offset 0x5C) __IO uint32_t INT_EN; // Interrupt Enable Register (offset 0x5C)
uint32_t RESERVED3; // Reserved for future use (offset 0x60) uint32_t RESERVED3; // Reserved for future use (offset 0x60)
__I uint32_t BYTE_TEST; // Read-only byte order testing register 87654321h (offset 0x64) __I uint32_t BYTE_TEST; // Read-only byte order testing register 87654321h (offset 0x64)
__IO uint32_t FIFO_INT; // FIFO Level Interrupts (offset 0x68) __IO uint32_t FIFO_INT; // FIFO Level Interrupts (offset 0x68)
__IO uint32_t RX_CFG; // Receive Configuration (offset 0x6C) __IO uint32_t RX_CFG; // Receive Configuration (offset 0x6C)
__IO uint32_t TX_CFG; // Transmit Configuration (offset 0x70) __IO uint32_t TX_CFG; // Transmit Configuration (offset 0x70)
__IO uint32_t HW_CFG; // Hardware Configuration (offset 0x74) __IO uint32_t HW_CFG; // Hardware Configuration (offset 0x74)
__IO uint32_t RX_DP_CTL; // RX Datapath Control (offset 0x78) __IO uint32_t RX_DP_CTL; // RX Datapath Control (offset 0x78)
__I uint32_t RX_FIFO_INF; // Receive FIFO Information (offset 0x7C) __I uint32_t RX_FIFO_INF; // Receive FIFO Information (offset 0x7C)
__I uint32_t TX_FIFO_INF; // Transmit FIFO Information (offset 0x80) __I uint32_t TX_FIFO_INF; // Transmit FIFO Information (offset 0x80)
__IO uint32_t PMT_CTRL; // Power Management Control (offset 0x84) __IO uint32_t PMT_CTRL; // Power Management Control (offset 0x84)
__IO uint32_t GPIO_CFG; // General Purpose IO Configuration (offset 0x88) __IO uint32_t GPIO_CFG; // General Purpose IO Configuration (offset 0x88)
__IO uint32_t GPT_CFG; // General Purpose Timer Configuration (offset 0x8C) __IO uint32_t GPT_CFG; // General Purpose Timer Configuration (offset 0x8C)
__I uint32_t GPT_CNT; // General Purpose Timer Count (offset 0x90) __I uint32_t GPT_CNT; // General Purpose Timer Count (offset 0x90)
uint32_t RESERVED4; // Reserved for future use (offset 0x94) uint32_t RESERVED4; // Reserved for future use (offset 0x94)
__IO uint32_t ENDIAN; // WORD SWAP Register (offset 0x98) __IO uint32_t ENDIAN; // WORD SWAP Register (offset 0x98)
__I uint32_t FREE_RUN; // Free Run Counter (offset 0x9C) __I uint32_t FREE_RUN; // Free Run Counter (offset 0x9C)
__I uint32_t RX_DROP; // RX Dropped Frames Counter (offset 0xA0) __I uint32_t RX_DROP; // RX Dropped Frames Counter (offset 0xA0)
__IO uint32_t MAC_CSR_CMD; // MAC CSR Synchronizer Command (offset 0xA4) __IO uint32_t MAC_CSR_CMD; // MAC CSR Synchronizer Command (offset 0xA4)
__IO uint32_t MAC_CSR_DATA; // MAC CSR Synchronizer Data (offset 0xA8) __IO uint32_t MAC_CSR_DATA; // MAC CSR Synchronizer Data (offset 0xA8)
__IO uint32_t AFC_CFG; // Automatic Flow Control Configuration (offset 0xAC) __IO uint32_t AFC_CFG; // Automatic Flow Control Configuration (offset 0xAC)
__IO uint32_t E2P_CMD; // EEPROM Command (offset 0xB0) __IO uint32_t E2P_CMD; // EEPROM Command (offset 0xB0)
__IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4) __IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4)
} SMSC9220_TypeDef; } SMSC9220_TypeDef;

12
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/peripherallink.h
View File

@ -37,17 +37,17 @@
#define __DEVICE_H #define __DEVICE_H
#if defined CMSDK_CM0 #if defined CMSDK_CM0
#include "CMSDK_CM0.h" /* device specific header file */ #include "CMSDK_CM0.h" /* device specific header file */
#elif defined CMSDK_CM0plus #elif defined CMSDK_CM0plus
#include "CMSDK_CM0plus.h" /* device specific header file */ #include "CMSDK_CM0plus.h" /* device specific header file */
#elif defined CMSDK_CM3 #elif defined CMSDK_CM3
#include "CMSDK_CM3.h" /* device specific header file */ #include "CMSDK_CM3.h" /* device specific header file */
#elif defined CMSDK_CM4 #elif defined CMSDK_CM4
#include "CMSDK_CM4.h" /* device specific header file */ #include "CMSDK_CM4.h" /* device specific header file */
#elif defined CMSDK_CM7 #elif defined CMSDK_CM7
#include "CMSDK_CM7.h" /* device specific header file */ #include "CMSDK_CM7.h" /* device specific header file */
#else #else
#warning "no appropriate header file found!" #warning "no appropriate header file found!"
#endif #endif
#endif /* __DEVICE_H */ #endif /* __DEVICE_H */

4
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/system_CMSDK_CM0plus.c
View File

@ -64,7 +64,7 @@ uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Cloc
* @brief Updates the SystemCoreClock with current core Clock * @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers. * retrieved from cpu registers.
*/ */
void SystemCoreClockUpdate (void) void SystemCoreClockUpdate(void)
{ {
SystemCoreClock = __SYSTEM_CLOCK; SystemCoreClock = __SYSTEM_CLOCK;
@ -80,7 +80,7 @@ void SystemCoreClockUpdate (void)
* @brief Setup the microcontroller system. * @brief Setup the microcontroller system.
* Initialize the System. * Initialize the System.
*/ */
void SystemInit (void) void SystemInit(void)
{ {
SystemCoreClock = __SYSTEM_CLOCK; SystemCoreClock = __SYSTEM_CLOCK;

4
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/system_CMSDK_CM0plus.h
View File

@ -56,7 +56,7 @@ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) *
* @brief Setup the microcontroller system. * @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable. * Initialize the System and update the SystemCoreClock variable.
*/ */
extern void SystemInit (void); extern void SystemInit(void);
/** /**
* Update SystemCoreClock variable * Update SystemCoreClock variable
@ -67,7 +67,7 @@ extern void SystemInit (void);
* @brief Updates the SystemCoreClock with current core Clock * @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers. * retrieved from cpu registers.
*/ */
extern void SystemCoreClockUpdate (void); extern void SystemCoreClockUpdate(void);
#ifdef __cplusplus #ifdef __cplusplus
} }

57
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/CMSDK_CM3.h
View File

@ -40,15 +40,14 @@
#define CMSDK_CM3_H #define CMSDK_CM3_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* ------------------------- Interrupt Number Definition ------------------------ */ /* ------------------------- Interrupt Number Definition ------------------------ */
typedef enum IRQn typedef enum IRQn {
{ /* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
/* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /* 3 HardFault Interrupt */ HardFault_IRQn = -13, /* 3 HardFault Interrupt */
MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
@ -59,7 +58,7 @@ typedef enum IRQn
PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
SysTick_IRQn = -1, /* 15 System Tick Interrupt */ SysTick_IRQn = -1, /* 15 System Tick Interrupt */
/****** CMSDK Specific Interrupt Numbers *********************************************************/ /****** CMSDK Specific Interrupt Numbers *********************************************************/
UARTRX0_IRQn = 0, /*!< UART 0 RX Interrupt */ UARTRX0_IRQn = 0, /*!< UART 0 RX Interrupt */
UARTTX0_IRQn = 1, /*!< UART 0 TX Interrupt */ UARTTX0_IRQn = 1, /*!< UART 0 TX Interrupt */
UARTRX1_IRQn = 2, /*!< UART 1 RX Interrupt */ UARTRX1_IRQn = 2, /*!< UART 1 RX Interrupt */
@ -115,23 +114,22 @@ typedef enum IRQn
/* ------------------- Start of section using anonymous unions ------------------ */ /* ------------------- Start of section using anonymous unions ------------------ */
#if defined ( __CC_ARM ) #if defined ( __CC_ARM )
#pragma push #pragma push
#pragma anon_unions #pragma anon_unions
#elif defined(__ICCARM__) #elif defined(__ICCARM__)
#pragma language=extended #pragma language=extended
#elif defined(__GNUC__) #elif defined(__GNUC__)
/* anonymous unions are enabled by default */ /* anonymous unions are enabled by default */
#elif defined(__TMS470__) #elif defined(__TMS470__)
/* anonymous unions are enabled by default */ /* anonymous unions are enabled by default */
#elif defined(__TASKING__) #elif defined(__TASKING__)
#pragma warning 586 #pragma warning 586
#else #else
#warning Not supported compiler type #warning Not supported compiler type
#endif #endif
/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
typedef struct typedef struct {
{
__IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */ __IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */
__IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */ __IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */
__IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */ __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */
@ -198,8 +196,7 @@ typedef struct
/*----------------------------- Timer (TIMER) -------------------------------*/ /*----------------------------- Timer (TIMER) -------------------------------*/
typedef struct typedef struct {
{
__IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */ __IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */
__IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */ __IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */
__IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */ __IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */
@ -238,8 +235,7 @@ typedef struct
/*------------- Timer (TIM) --------------------------------------------------*/ /*------------- Timer (TIM) --------------------------------------------------*/
typedef struct typedef struct {
{
__IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */ __IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
__I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */ __I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
__IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */ __IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
@ -333,8 +329,7 @@ typedef struct
#define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /* CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */ #define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /* CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */
typedef struct typedef struct {
{
__IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */ __IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */
__I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */ __I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */
__IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */ __IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */
@ -382,8 +377,7 @@ typedef struct
/*-------------------- General Purpose Input Output (GPIO) -------------------*/ /*-------------------- General Purpose Input Output (GPIO) -------------------*/
typedef struct typedef struct {
{
__IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */ __IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */
__IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */ __IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */
uint32_t RESERVED0[2]; uint32_t RESERVED0[2];
@ -456,8 +450,7 @@ typedef struct
/*------------- System Control (SYSCON) --------------------------------------*/ /*------------- System Control (SYSCON) --------------------------------------*/
typedef struct typedef struct {
{
__IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */ __IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */
__IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */ __IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */
__IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */ __IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */
@ -497,8 +490,7 @@ typedef struct
/*------------- PL230 uDMA (PL230) --------------------------------------*/ /*------------- PL230 uDMA (PL230) --------------------------------------*/
typedef struct typedef struct {
{
__I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */ __I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */
__O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */ __O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */
__IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */ __IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */
@ -593,8 +585,7 @@ typedef struct
/*------------------- Watchdog ----------------------------------------------*/ /*------------------- Watchdog ----------------------------------------------*/
typedef struct typedef struct {
{
__IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */ __IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */
__I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */ __I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */
@ -607,7 +598,7 @@ typedef struct
uint32_t RESERVED1[191]; uint32_t RESERVED1[191];
__IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */ __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */
__O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */ __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */
}CMSDK_WATCHDOG_TypeDef; } CMSDK_WATCHDOG_TypeDef;
#define CMSDK_Watchdog_LOAD_Pos 0 /* CMSDK_Watchdog LOAD: LOAD Position */ #define CMSDK_Watchdog_LOAD_Pos 0 /* CMSDK_Watchdog LOAD: LOAD Position */
#define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /* CMSDK_Watchdog LOAD: LOAD Mask */ #define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /* CMSDK_Watchdog LOAD: LOAD Mask */
@ -643,17 +634,17 @@ typedef struct
/* -------------------- End of section using anonymous unions ------------------- */ /* -------------------- End of section using anonymous unions ------------------- */
#if defined ( __CC_ARM ) #if defined ( __CC_ARM )
#pragma pop #pragma pop
#elif defined(__ICCARM__) #elif defined(__ICCARM__)
/* leave anonymous unions enabled */ /* leave anonymous unions enabled */
#elif defined(__GNUC__) #elif defined(__GNUC__)
/* anonymous unions are enabled by default */ /* anonymous unions are enabled by default */
#elif defined(__TMS470__) #elif defined(__TMS470__)
/* anonymous unions are enabled by default */ /* anonymous unions are enabled by default */
#elif defined(__TASKING__) #elif defined(__TASKING__)
#pragma warning restore #pragma warning restore
#else #else
#warning Not supported compiler type #warning Not supported compiler type
#endif #endif

78
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/SMM_MPS2.h
View File

@ -46,8 +46,7 @@
/* FPGA System Register declaration */ /* FPGA System Register declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct typedef struct {
{
__IO uint32_t LED; // Offset: 0x000 (R/W) LED connections __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections
// [31:2] : Reserved // [31:2] : Reserved
// [1:0] : LEDs // [1:0] : LEDs
@ -107,8 +106,7 @@ typedef struct
/* SCC Register declaration */ /* SCC Register declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct // typedef struct { //
{
__IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT __IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT
// [31:1] : Reserved // [31:1] : Reserved
// [0] 1 : REMAP BlockRam to ZBT // [0] 1 : REMAP BlockRam to ZBT
@ -166,8 +164,7 @@ typedef struct //
/* SSP Peripheral declaration */ /* SSP Peripheral declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf typedef struct { // Document DDI0194G_ssp_pl022_r1p3_trm.pdf
{
__IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0 __IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0
// [31:16] : Reserved // [31:16] : Reserved
// [15:8] : Serial clock rate // [15:8] : Serial clock rate
@ -314,8 +311,7 @@ typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf
/* Audio and Touch Screen (I2C) Peripheral declaration */ /* Audio and Touch Screen (I2C) Peripheral declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct typedef struct {
{
union { union {
__O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W) __O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W)
__I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ ) __I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ )
@ -331,8 +327,7 @@ typedef struct
/* Audio I2S Peripheral declaration */ /* Audio I2S Peripheral declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct typedef struct {
{
/*!< Offset: 0x000 CONTROL Register (R/W) */ /*!< Offset: 0x000 CONTROL Register (R/W) */
__IO uint32_t CONTROL; // <h> CONTROL </h> __IO uint32_t CONTROL; // <h> CONTROL </h>
// <o.0> TX Enable // <o.0> TX Enable
@ -486,44 +481,43 @@ typedef struct
/* SMSC9220 Register Definitions */ /* SMSC9220 Register Definitions */
/******************************************************************************/ /******************************************************************************/
typedef struct // SMSC LAN9220 typedef struct { // SMSC LAN9220
{ __I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0)
__I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0)
uint32_t RESERVED1[0x7]; uint32_t RESERVED1[0x7];
__O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20) __O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20)
uint32_t RESERVED2[0x7]; uint32_t RESERVED2[0x7];
__I uint32_t RX_STAT_PORT; // Receive FIFO status port (offset 0x40) __I uint32_t RX_STAT_PORT; // Receive FIFO status port (offset 0x40)
__I uint32_t RX_STAT_PEEK; // Receive FIFO status peek (offset 0x44) __I uint32_t RX_STAT_PEEK; // Receive FIFO status peek (offset 0x44)
__I uint32_t TX_STAT_PORT; // Transmit FIFO status port (offset 0x48) __I uint32_t TX_STAT_PORT; // Transmit FIFO status port (offset 0x48)
__I uint32_t TX_STAT_PEEK; // Transmit FIFO status peek (offset 0x4C) __I uint32_t TX_STAT_PEEK; // Transmit FIFO status peek (offset 0x4C)
__I uint32_t ID_REV; // Chip ID and Revision (offset 0x50) __I uint32_t ID_REV; // Chip ID and Revision (offset 0x50)
__IO uint32_t IRQ_CFG; // Main Interrupt Configuration (offset 0x54) __IO uint32_t IRQ_CFG; // Main Interrupt Configuration (offset 0x54)
__IO uint32_t INT_STS; // Interrupt Status (offset 0x58) __IO uint32_t INT_STS; // Interrupt Status (offset 0x58)
__IO uint32_t INT_EN; // Interrupt Enable Register (offset 0x5C) __IO uint32_t INT_EN; // Interrupt Enable Register (offset 0x5C)
uint32_t RESERVED3; // Reserved for future use (offset 0x60) uint32_t RESERVED3; // Reserved for future use (offset 0x60)
__I uint32_t BYTE_TEST; // Read-only byte order testing register 87654321h (offset 0x64) __I uint32_t BYTE_TEST; // Read-only byte order testing register 87654321h (offset 0x64)
__IO uint32_t FIFO_INT; // FIFO Level Interrupts (offset 0x68) __IO uint32_t FIFO_INT; // FIFO Level Interrupts (offset 0x68)
__IO uint32_t RX_CFG; // Receive Configuration (offset 0x6C) __IO uint32_t RX_CFG; // Receive Configuration (offset 0x6C)
__IO uint32_t TX_CFG; // Transmit Configuration (offset 0x70) __IO uint32_t TX_CFG; // Transmit Configuration (offset 0x70)
__IO uint32_t HW_CFG; // Hardware Configuration (offset 0x74) __IO uint32_t HW_CFG; // Hardware Configuration (offset 0x74)
__IO uint32_t RX_DP_CTL; // RX Datapath Control (offset 0x78) __IO uint32_t RX_DP_CTL; // RX Datapath Control (offset 0x78)
__I uint32_t RX_FIFO_INF; // Receive FIFO Information (offset 0x7C) __I uint32_t RX_FIFO_INF; // Receive FIFO Information (offset 0x7C)
__I uint32_t TX_FIFO_INF; // Transmit FIFO Information (offset 0x80) __I uint32_t TX_FIFO_INF; // Transmit FIFO Information (offset 0x80)
__IO uint32_t PMT_CTRL; // Power Management Control (offset 0x84) __IO uint32_t PMT_CTRL; // Power Management Control (offset 0x84)
__IO uint32_t GPIO_CFG; // General Purpose IO Configuration (offset 0x88) __IO uint32_t GPIO_CFG; // General Purpose IO Configuration (offset 0x88)
__IO uint32_t GPT_CFG; // General Purpose Timer Configuration (offset 0x8C) __IO uint32_t GPT_CFG; // General Purpose Timer Configuration (offset 0x8C)
__I uint32_t GPT_CNT; // General Purpose Timer Count (offset 0x90) __I uint32_t GPT_CNT; // General Purpose Timer Count (offset 0x90)
uint32_t RESERVED4; // Reserved for future use (offset 0x94) uint32_t RESERVED4; // Reserved for future use (offset 0x94)
__IO uint32_t ENDIAN; // WORD SWAP Register (offset 0x98) __IO uint32_t ENDIAN; // WORD SWAP Register (offset 0x98)
__I uint32_t FREE_RUN; // Free Run Counter (offset 0x9C) __I uint32_t FREE_RUN; // Free Run Counter (offset 0x9C)
__I uint32_t RX_DROP; // RX Dropped Frames Counter (offset 0xA0) __I uint32_t RX_DROP; // RX Dropped Frames Counter (offset 0xA0)
__IO uint32_t MAC_CSR_CMD; // MAC CSR Synchronizer Command (offset 0xA4) __IO uint32_t MAC_CSR_CMD; // MAC CSR Synchronizer Command (offset 0xA4)
__IO uint32_t MAC_CSR_DATA; // MAC CSR Synchronizer Data (offset 0xA8) __IO uint32_t MAC_CSR_DATA; // MAC CSR Synchronizer Data (offset 0xA8)
__IO uint32_t AFC_CFG; // Automatic Flow Control Configuration (offset 0xAC) __IO uint32_t AFC_CFG; // Automatic Flow Control Configuration (offset 0xAC)
__IO uint32_t E2P_CMD; // EEPROM Command (offset 0xB0) __IO uint32_t E2P_CMD; // EEPROM Command (offset 0xB0)
__IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4) __IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4)
} SMSC9220_TypeDef; } SMSC9220_TypeDef;

12
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/peripherallink.h
View File

@ -37,17 +37,17 @@
#define __DEVICE_H #define __DEVICE_H
#if defined CMSDK_CM0 #if defined CMSDK_CM0
#include "CMSDK_CM0.h" /* device specific header file */ #include "CMSDK_CM0.h" /* device specific header file */
#elif defined CMSDK_CM0plus #elif defined CMSDK_CM0plus
#include "CMSDK_CM0plus.h" /* device specific header file */ #include "CMSDK_CM0plus.h" /* device specific header file */
#elif defined CMSDK_CM3 #elif defined CMSDK_CM3
#include "CMSDK_CM3.h" /* device specific header file */ #include "CMSDK_CM3.h" /* device specific header file */
#elif defined CMSDK_CM4 #elif defined CMSDK_CM4
#include "CMSDK_CM4.h" /* device specific header file */ #include "CMSDK_CM4.h" /* device specific header file */
#elif defined CMSDK_CM7 #elif defined CMSDK_CM7
#include "CMSDK_CM7.h" /* device specific header file */ #include "CMSDK_CM7.h" /* device specific header file */
#else #else
#warning "no appropriate header file found!" #warning "no appropriate header file found!"
#endif #endif
#endif /* __DEVICE_H */ #endif /* __DEVICE_H */

4
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/system_CMSDK_CM3.c
View File

@ -65,7 +65,7 @@ uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Cloc
* @brief Updates the SystemCoreClock with current core Clock * @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers. * retrieved from cpu registers.
*/ */
void SystemCoreClockUpdate (void) void SystemCoreClockUpdate(void)
{ {
SystemCoreClock = __SYSTEM_CLOCK; SystemCoreClock = __SYSTEM_CLOCK;
@ -81,7 +81,7 @@ void SystemCoreClockUpdate (void)
* @brief Setup the microcontroller system. * @brief Setup the microcontroller system.
* Initialize the System. * Initialize the System.
*/ */
void SystemInit (void) void SystemInit(void)
{ {
#ifdef UNALIGNED_SUPPORT_DISABLE #ifdef UNALIGNED_SUPPORT_DISABLE

4
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/system_CMSDK_CM3.h
View File

@ -56,7 +56,7 @@ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) *
* @brief Setup the microcontroller system. * @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable. * Initialize the System and update the SystemCoreClock variable.
*/ */
extern void SystemInit (void); extern void SystemInit(void);
/** /**
* Update SystemCoreClock variable * Update SystemCoreClock variable
@ -67,7 +67,7 @@ extern void SystemInit (void);
* @brief Updates the SystemCoreClock with current core Clock * @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers. * retrieved from cpu registers.
*/ */
extern void SystemCoreClockUpdate (void); extern void SystemCoreClockUpdate(void);
#ifdef __cplusplus #ifdef __cplusplus
} }

63
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/CMSDK_CM4.h
View File

@ -40,15 +40,14 @@
#define CMSDK_CM4_H #define CMSDK_CM4_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* ------------------------- Interrupt Number Definition ------------------------ */ /* ------------------------- Interrupt Number Definition ------------------------ */
typedef enum IRQn typedef enum IRQn {
{ /* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
/* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /* 3 HardFault Interrupt */ HardFault_IRQn = -13, /* 3 HardFault Interrupt */
MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
@ -59,7 +58,7 @@ typedef enum IRQn
PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
SysTick_IRQn = -1, /* 15 System Tick Interrupt */ SysTick_IRQn = -1, /* 15 System Tick Interrupt */
/****** CMSDK Specific Interrupt Numbers *********************************************************/ /****** CMSDK Specific Interrupt Numbers *********************************************************/
UARTRX0_IRQn = 0, /*!< UART 0 RX Interrupt */ UARTRX0_IRQn = 0, /*!< UART 0 RX Interrupt */
UARTTX0_IRQn = 1, /*!< UART 0 TX Interrupt */ UARTTX0_IRQn = 1, /*!< UART 0 TX Interrupt */
UARTRX1_IRQn = 2, /*!< UART 1 RX Interrupt */ UARTRX1_IRQn = 2, /*!< UART 1 RX Interrupt */
@ -132,8 +131,7 @@ typedef enum IRQn
memory mapped structure for CMSDK_UART memory mapped structure for CMSDK_UART
@{ @{
*/ */
typedef struct typedef struct {
{
__IO uint32_t DATA; /*!< Offset: 0x000 Data Register (R/W) */ __IO uint32_t DATA; /*!< Offset: 0x000 Data Register (R/W) */
__IO uint32_t STATE; /*!< Offset: 0x004 Status Register (R/W) */ __IO uint32_t STATE; /*!< Offset: 0x004 Status Register (R/W) */
__IO uint32_t CTRL; /*!< Offset: 0x008 Control Register (R/W) */ __IO uint32_t CTRL; /*!< Offset: 0x008 Control Register (R/W) */
@ -205,8 +203,7 @@ typedef struct
/** @addtogroup CMSDK_TIMER CMSDK Timer /** @addtogroup CMSDK_TIMER CMSDK Timer
@{ @{
*/ */
typedef struct typedef struct {
{
__IO uint32_t CTRL; /*!< Offset: 0x000 Control Register (R/W) */ __IO uint32_t CTRL; /*!< Offset: 0x000 Control Register (R/W) */
__IO uint32_t VALUE; /*!< Offset: 0x004 Current Value Register (R/W) */ __IO uint32_t VALUE; /*!< Offset: 0x004 Current Value Register (R/W) */
__IO uint32_t RELOAD; /*!< Offset: 0x008 Reload Value Register (R/W) */ __IO uint32_t RELOAD; /*!< Offset: 0x008 Reload Value Register (R/W) */
@ -253,8 +250,7 @@ typedef struct
@{ @{
*/ */
typedef struct typedef struct {
{
__IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */ __IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
__I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */ __I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
__IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */ __IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
@ -381,8 +377,7 @@ typedef struct
#define CMSDK_DUALTIMER2_BGLOAD_Pos 0 /*!< CMSDK_DUALTIMER2 BGLOAD: Background Load Position */ #define CMSDK_DUALTIMER2_BGLOAD_Pos 0 /*!< CMSDK_DUALTIMER2 BGLOAD: Background Load Position */
#define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /*!< CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */ #define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /*!< CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */
typedef struct typedef struct {
{
__IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */ __IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */
__I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */ __I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */
__IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */ __IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */
@ -452,8 +447,7 @@ typedef struct
/** @addtogroup CMSDK_GPIO CMSDK GPIO /** @addtogroup CMSDK_GPIO CMSDK GPIO
@{ @{
*/ */
typedef struct typedef struct {
{
__IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */ __IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */
__IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */ __IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */
uint32_t RESERVED0[2]; uint32_t RESERVED0[2];
@ -531,8 +525,7 @@ typedef struct
/** @addtogroup CMSDK_SYSCON CMSDK System Control /** @addtogroup CMSDK_SYSCON CMSDK System Control
@{ @{
*/ */
typedef struct typedef struct {
{
__IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */ __IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */
__IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */ __IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */
__IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */ __IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */
@ -576,8 +569,7 @@ typedef struct
/** @addtogroup CMSDK_PL230 CMSDK uDMA controller /** @addtogroup CMSDK_PL230 CMSDK uDMA controller
@{ @{
*/ */
typedef struct typedef struct {
{
__I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */ __I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */
__O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */ __O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */
__IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */ __IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */
@ -679,8 +671,7 @@ typedef struct
@{ @{
*/ */
typedef struct typedef struct {
{
__IO uint32_t UARTDR; // <h> Data __IO uint32_t UARTDR; // <h> Data
// <o.11> OE: Overrun error <r> // <o.11> OE: Overrun error <r>
// <o.10> BE: Break error <r> // <o.10> BE: Break error <r>
@ -1113,8 +1104,7 @@ typedef struct
/** @addtogroup CMSDK_Watchdog CMSDK Watchdog /** @addtogroup CMSDK_Watchdog CMSDK Watchdog
@{ @{
*/ */
typedef struct typedef struct {
{
__IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */ __IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */
__I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */ __I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */
@ -1130,7 +1120,7 @@ typedef struct
uint32_t RESERVED1[191]; uint32_t RESERVED1[191];
__IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */ __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */
__O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */ __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */
}CMSDK_WATCHDOG_TypeDef; } CMSDK_WATCHDOG_TypeDef;
#define CMSDK_Watchdog_LOAD_Pos 0 /*!< CMSDK_Watchdog LOAD: LOAD Position */ #define CMSDK_Watchdog_LOAD_Pos 0 /*!< CMSDK_Watchdog LOAD: LOAD Position */
#define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /*!< CMSDK_Watchdog LOAD: LOAD Mask */ #define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /*!< CMSDK_Watchdog LOAD: LOAD Mask */
@ -1168,21 +1158,20 @@ typedef struct
/** @addtogroup CMSDK_PL061 CMSDK APB GPIO /** @addtogroup CMSDK_PL061 CMSDK APB GPIO
@{ @{
*/ */
typedef struct typedef struct {
{
__IO uint32_t DATA[256]; __IO uint32_t DATA[256];
__IO uint32_t DIR; __IO uint32_t DIR;
__IO uint32_t INTSENSE; __IO uint32_t INTSENSE;
__IO uint32_t INTBOTHEDGE; __IO uint32_t INTBOTHEDGE;
__IO uint32_t INTEVENT; __IO uint32_t INTEVENT;
__IO uint32_t INTMASK; __IO uint32_t INTMASK;
__O uint32_t RAWINTSTAT; __O uint32_t RAWINTSTAT;
__O uint32_t MASKINTSTAT; __O uint32_t MASKINTSTAT;
__I uint32_t INTCLR; __I uint32_t INTCLR;
__IO uint32_t MODECTRL; __IO uint32_t MODECTRL;
}APBGPIO_TypeDef; } APBGPIO_TypeDef;
#define CMSDK_PL061_DATA_Pos 0 /*!< CMSDK_PL061 DATA: DATA Position */ #define CMSDK_PL061_DATA_Pos 0 /*!< CMSDK_PL061 DATA: DATA Position */
#define CMSDK_PL061_DATA_Msk (0xFFFFFFFFul << CMSDK_PL061_LOAD_Pos) /*!< CMSDK_PL061 DATA: DATA Mask */ #define CMSDK_PL061_DATA_Msk (0xFFFFFFFFul << CMSDK_PL061_LOAD_Pos) /*!< CMSDK_PL061 DATA: DATA Mask */

78
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/SMM_MPS2.h
View File

@ -46,8 +46,7 @@
/* FPGA System Register declaration */ /* FPGA System Register declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct typedef struct {
{
__IO uint32_t LED; // Offset: 0x000 (R/W) LED connections __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections
// [31:2] : Reserved // [31:2] : Reserved
// [1:0] : LEDs // [1:0] : LEDs
@ -107,8 +106,7 @@ typedef struct
/* SCC Register declaration */ /* SCC Register declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct // typedef struct { //
{
__IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT __IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT
// [31:1] : Reserved // [31:1] : Reserved
// [0] 1 : REMAP BlockRam to ZBT // [0] 1 : REMAP BlockRam to ZBT
@ -166,8 +164,7 @@ typedef struct //
/* SSP Peripheral declaration */ /* SSP Peripheral declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf typedef struct { // Document DDI0194G_ssp_pl022_r1p3_trm.pdf
{
__IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0 __IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0
// [31:16] : Reserved // [31:16] : Reserved
// [15:8] : Serial clock rate // [15:8] : Serial clock rate
@ -314,8 +311,7 @@ typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf
/* Audio and Touch Screen (I2C) Peripheral declaration */ /* Audio and Touch Screen (I2C) Peripheral declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct typedef struct {
{
union { union {
__O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W) __O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W)
__I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ ) __I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ )
@ -331,8 +327,7 @@ typedef struct
/* Audio I2S Peripheral declaration */ /* Audio I2S Peripheral declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct typedef struct {
{
/*!< Offset: 0x000 CONTROL Register (R/W) */ /*!< Offset: 0x000 CONTROL Register (R/W) */
__IO uint32_t CONTROL; // <h> CONTROL </h> __IO uint32_t CONTROL; // <h> CONTROL </h>
// <o.0> TX Enable // <o.0> TX Enable
@ -486,44 +481,43 @@ typedef struct
/* SMSC9220 Register Definitions */ /* SMSC9220 Register Definitions */
/******************************************************************************/ /******************************************************************************/
typedef struct // SMSC LAN9220 typedef struct { // SMSC LAN9220
{ __I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0)
__I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0)
uint32_t RESERVED1[0x7]; uint32_t RESERVED1[0x7];
__O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20) __O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20)
uint32_t RESERVED2[0x7]; uint32_t RESERVED2[0x7];
__I uint32_t RX_STAT_PORT; // Receive FIFO status port (offset 0x40) __I uint32_t RX_STAT_PORT; // Receive FIFO status port (offset 0x40)
__I uint32_t RX_STAT_PEEK; // Receive FIFO status peek (offset 0x44) __I uint32_t RX_STAT_PEEK; // Receive FIFO status peek (offset 0x44)
__I uint32_t TX_STAT_PORT; // Transmit FIFO status port (offset 0x48) __I uint32_t TX_STAT_PORT; // Transmit FIFO status port (offset 0x48)
__I uint32_t TX_STAT_PEEK; // Transmit FIFO status peek (offset 0x4C) __I uint32_t TX_STAT_PEEK; // Transmit FIFO status peek (offset 0x4C)
__I uint32_t ID_REV; // Chip ID and Revision (offset 0x50) __I uint32_t ID_REV; // Chip ID and Revision (offset 0x50)
__IO uint32_t IRQ_CFG; // Main Interrupt Configuration (offset 0x54) __IO uint32_t IRQ_CFG; // Main Interrupt Configuration (offset 0x54)
__IO uint32_t INT_STS; // Interrupt Status (offset 0x58) __IO uint32_t INT_STS; // Interrupt Status (offset 0x58)
__IO uint32_t INT_EN; // Interrupt Enable Register (offset 0x5C) __IO uint32_t INT_EN; // Interrupt Enable Register (offset 0x5C)
uint32_t RESERVED3; // Reserved for future use (offset 0x60) uint32_t RESERVED3; // Reserved for future use (offset 0x60)
__I uint32_t BYTE_TEST; // Read-only byte order testing register 87654321h (offset 0x64) __I uint32_t BYTE_TEST; // Read-only byte order testing register 87654321h (offset 0x64)
__IO uint32_t FIFO_INT; // FIFO Level Interrupts (offset 0x68) __IO uint32_t FIFO_INT; // FIFO Level Interrupts (offset 0x68)
__IO uint32_t RX_CFG; // Receive Configuration (offset 0x6C) __IO uint32_t RX_CFG; // Receive Configuration (offset 0x6C)
__IO uint32_t TX_CFG; // Transmit Configuration (offset 0x70) __IO uint32_t TX_CFG; // Transmit Configuration (offset 0x70)
__IO uint32_t HW_CFG; // Hardware Configuration (offset 0x74) __IO uint32_t HW_CFG; // Hardware Configuration (offset 0x74)
__IO uint32_t RX_DP_CTL; // RX Datapath Control (offset 0x78) __IO uint32_t RX_DP_CTL; // RX Datapath Control (offset 0x78)
__I uint32_t RX_FIFO_INF; // Receive FIFO Information (offset 0x7C) __I uint32_t RX_FIFO_INF; // Receive FIFO Information (offset 0x7C)
__I uint32_t TX_FIFO_INF; // Transmit FIFO Information (offset 0x80) __I uint32_t TX_FIFO_INF; // Transmit FIFO Information (offset 0x80)
__IO uint32_t PMT_CTRL; // Power Management Control (offset 0x84) __IO uint32_t PMT_CTRL; // Power Management Control (offset 0x84)
__IO uint32_t GPIO_CFG; // General Purpose IO Configuration (offset 0x88) __IO uint32_t GPIO_CFG; // General Purpose IO Configuration (offset 0x88)
__IO uint32_t GPT_CFG; // General Purpose Timer Configuration (offset 0x8C) __IO uint32_t GPT_CFG; // General Purpose Timer Configuration (offset 0x8C)
__I uint32_t GPT_CNT; // General Purpose Timer Count (offset 0x90) __I uint32_t GPT_CNT; // General Purpose Timer Count (offset 0x90)
uint32_t RESERVED4; // Reserved for future use (offset 0x94) uint32_t RESERVED4; // Reserved for future use (offset 0x94)
__IO uint32_t ENDIAN; // WORD SWAP Register (offset 0x98) __IO uint32_t ENDIAN; // WORD SWAP Register (offset 0x98)
__I uint32_t FREE_RUN; // Free Run Counter (offset 0x9C) __I uint32_t FREE_RUN; // Free Run Counter (offset 0x9C)
__I uint32_t RX_DROP; // RX Dropped Frames Counter (offset 0xA0) __I uint32_t RX_DROP; // RX Dropped Frames Counter (offset 0xA0)
__IO uint32_t MAC_CSR_CMD; // MAC CSR Synchronizer Command (offset 0xA4) __IO uint32_t MAC_CSR_CMD; // MAC CSR Synchronizer Command (offset 0xA4)
__IO uint32_t MAC_CSR_DATA; // MAC CSR Synchronizer Data (offset 0xA8) __IO uint32_t MAC_CSR_DATA; // MAC CSR Synchronizer Data (offset 0xA8)
__IO uint32_t AFC_CFG; // Automatic Flow Control Configuration (offset 0xAC) __IO uint32_t AFC_CFG; // Automatic Flow Control Configuration (offset 0xAC)
__IO uint32_t E2P_CMD; // EEPROM Command (offset 0xB0) __IO uint32_t E2P_CMD; // EEPROM Command (offset 0xB0)
__IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4) __IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4)
} SMSC9220_TypeDef; } SMSC9220_TypeDef;

12
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/peripherallink.h
View File

@ -37,17 +37,17 @@
#define __DEVICE_H #define __DEVICE_H
#if defined CMSDK_CM0 #if defined CMSDK_CM0
#include "CMSDK_CM0.h" /* device specific header file */ #include "CMSDK_CM0.h" /* device specific header file */
#elif defined CMSDK_CM0plus #elif defined CMSDK_CM0plus
#include "CMSDK_CM0plus.h" /* device specific header file */ #include "CMSDK_CM0plus.h" /* device specific header file */
#elif defined CMSDK_CM3 #elif defined CMSDK_CM3
#include "CMSDK_CM3.h" /* device specific header file */ #include "CMSDK_CM3.h" /* device specific header file */
#elif defined CMSDK_CM4 #elif defined CMSDK_CM4
#include "CMSDK_CM4.h" /* device specific header file */ #include "CMSDK_CM4.h" /* device specific header file */
#elif defined CMSDK_CM7 #elif defined CMSDK_CM7
#include "CMSDK_CM7.h" /* device specific header file */ #include "CMSDK_CM7.h" /* device specific header file */
#else #else
#warning "no appropriate header file found!" #warning "no appropriate header file found!"
#endif #endif
#endif /* __DEVICE_H */ #endif /* __DEVICE_H */

12
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/system_CMSDK_CM4.c
View File

@ -64,7 +64,7 @@ uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Cloc
* @brief Updates the SystemCoreClock with current core Clock * @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers. * retrieved from cpu registers.
*/ */
void SystemCoreClockUpdate (void) void SystemCoreClockUpdate(void)
{ {
SystemCoreClock = __SYSTEM_CLOCK; SystemCoreClock = __SYSTEM_CLOCK;
@ -80,12 +80,12 @@ void SystemCoreClockUpdate (void)
* @brief Setup the microcontroller system. * @brief Setup the microcontroller system.
* Initialize the System. * Initialize the System.
*/ */
void SystemInit (void) void SystemInit(void)
{ {
#if (__FPU_USED == 1) #if (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ SCB->CPACR |= ((3UL << 10 * 2) | /* set CP10 Full Access */
(3UL << 11*2) ); /* set CP11 Full Access */ (3UL << 11 * 2)); /* set CP11 Full Access */
#endif #endif
#ifdef UNALIGNED_SUPPORT_DISABLE #ifdef UNALIGNED_SUPPORT_DISABLE
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;

4
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/system_CMSDK_CM4.h
View File

@ -56,7 +56,7 @@ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) *
* @brief Setup the microcontroller system. * @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable. * Initialize the System and update the SystemCoreClock variable.
*/ */
extern void SystemInit (void); extern void SystemInit(void);
/** /**
* Update SystemCoreClock variable * Update SystemCoreClock variable
@ -67,7 +67,7 @@ extern void SystemInit (void);
* @brief Updates the SystemCoreClock with current core Clock * @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers. * retrieved from cpu registers.
*/ */
extern void SystemCoreClockUpdate (void); extern void SystemCoreClockUpdate(void);
#ifdef __cplusplus #ifdef __cplusplus
} }

63
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/CMSDK_CM7.h
View File

@ -46,9 +46,8 @@ extern "C" {
/* ------------------------- Interrupt Number Definition ------------------------ */ /* ------------------------- Interrupt Number Definition ------------------------ */
typedef enum IRQn typedef enum IRQn {
{ /* ------------------- Cortex-M7 Processor Exceptions Numbers ------------------- */
/* ------------------- Cortex-M7 Processor Exceptions Numbers ------------------- */
NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /* 3 HardFault Interrupt */ HardFault_IRQn = -13, /* 3 HardFault Interrupt */
MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
@ -59,7 +58,7 @@ typedef enum IRQn
PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
SysTick_IRQn = -1, /* 15 System Tick Interrupt */ SysTick_IRQn = -1, /* 15 System Tick Interrupt */
/* ---------------------- CMSDK_CM7 Specific Interrupt Numbers -------------- */ /* ---------------------- CMSDK_CM7 Specific Interrupt Numbers -------------- */
UARTRX0_IRQn = 0, /* UART 0 RX Interrupt */ UARTRX0_IRQn = 0, /* UART 0 RX Interrupt */
UARTTX0_IRQn = 1, /* UART 0 TX Interrupt */ UARTTX0_IRQn = 1, /* UART 0 TX Interrupt */
UARTRX1_IRQn = 2, /* UART 1 RX Interrupt */ UARTRX1_IRQn = 2, /* UART 1 RX Interrupt */
@ -119,25 +118,24 @@ typedef enum IRQn
/* ------------------- Start of section using anonymous unions ------------------ */ /* ------------------- Start of section using anonymous unions ------------------ */
#if defined (__CC_ARM) #if defined (__CC_ARM)
#pragma push #pragma push
#pragma anon_unions #pragma anon_unions
#elif defined (__ICCARM__) #elif defined (__ICCARM__)
#pragma language=extended #pragma language=extended
#elif defined (__GNUC__) #elif defined (__GNUC__)
/* anonymous unions are enabled by default */ /* anonymous unions are enabled by default */
#elif defined (__TMS470__) #elif defined (__TMS470__)
/* anonymous unions are enabled by default */ /* anonymous unions are enabled by default */
#elif defined (__TASKING__) #elif defined (__TASKING__)
#pragma warning 586 #pragma warning 586
#elif defined (__CSMC__) #elif defined (__CSMC__)
/* anonymous unions are enabled by default */ /* anonymous unions are enabled by default */
#else #else
#warning Not supported compiler type #warning Not supported compiler type
#endif #endif
/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
typedef struct typedef struct {
{
__IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */ __IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */
__IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */ __IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */
__IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */ __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */
@ -204,8 +202,7 @@ typedef struct
/*----------------------------- Timer (TIMER) -------------------------------*/ /*----------------------------- Timer (TIMER) -------------------------------*/
typedef struct typedef struct {
{
__IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */ __IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */
__IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */ __IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */
__IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */ __IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */
@ -244,8 +241,7 @@ typedef struct
/*------------- Timer (TIM) --------------------------------------------------*/ /*------------- Timer (TIM) --------------------------------------------------*/
typedef struct typedef struct {
{
__IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */ __IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
__I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */ __I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
__IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */ __IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
@ -339,8 +335,7 @@ typedef struct
#define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /* CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */ #define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /* CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */
typedef struct typedef struct {
{
__IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */ __IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */
__I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */ __I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */
__IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */ __IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */
@ -388,8 +383,7 @@ typedef struct
/*-------------------- General Purpose Input Output (GPIO) -------------------*/ /*-------------------- General Purpose Input Output (GPIO) -------------------*/
typedef struct typedef struct {
{
__IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */ __IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */
__IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */ __IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */
uint32_t RESERVED0[2]; uint32_t RESERVED0[2];
@ -462,8 +456,7 @@ typedef struct
/*------------- System Control (SYSCON) --------------------------------------*/ /*------------- System Control (SYSCON) --------------------------------------*/
typedef struct typedef struct {
{
__IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */ __IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */
__IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */ __IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */
__IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */ __IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */
@ -503,8 +496,7 @@ typedef struct
/*------------- PL230 uDMA (PL230) --------------------------------------*/ /*------------- PL230 uDMA (PL230) --------------------------------------*/
typedef struct typedef struct {
{
__I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */ __I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */
__O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */ __O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */
__IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */ __IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */
@ -599,8 +591,7 @@ typedef struct
/*------------------- Watchdog ----------------------------------------------*/ /*------------------- Watchdog ----------------------------------------------*/
typedef struct typedef struct {
{
__IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */ __IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */
__I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */ __I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */
@ -613,7 +604,7 @@ typedef struct
uint32_t RESERVED1[191]; uint32_t RESERVED1[191];
__IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */ __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */
__O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */ __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */
}CMSDK_WATCHDOG_TypeDef; } CMSDK_WATCHDOG_TypeDef;
#define CMSDK_Watchdog_LOAD_Pos 0 /* CMSDK_Watchdog LOAD: LOAD Position */ #define CMSDK_Watchdog_LOAD_Pos 0 /* CMSDK_Watchdog LOAD: LOAD Position */
#define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /* CMSDK_Watchdog LOAD: LOAD Mask */ #define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /* CMSDK_Watchdog LOAD: LOAD Mask */
@ -649,19 +640,19 @@ typedef struct
/* -------------------- End of section using anonymous unions ------------------- */ /* -------------------- End of section using anonymous unions ------------------- */
#if defined (__CC_ARM) #if defined (__CC_ARM)
#pragma pop #pragma pop
#elif defined (__ICCARM__) #elif defined (__ICCARM__)
/* leave anonymous unions enabled */ /* leave anonymous unions enabled */
#elif defined (__GNUC__) #elif defined (__GNUC__)
/* anonymous unions are enabled by default */ /* anonymous unions are enabled by default */
#elif defined (__TMS470__) #elif defined (__TMS470__)
/* anonymous unions are enabled by default */ /* anonymous unions are enabled by default */
#elif defined (__TASKING__) #elif defined (__TASKING__)
#pragma warning restore #pragma warning restore
#elif defined (__CSMC__) #elif defined (__CSMC__)
/* anonymous unions are enabled by default */ /* anonymous unions are enabled by default */
#else #else
#warning Not supported compiler type #warning Not supported compiler type
#endif #endif

78
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/SMM_MPS2.h
View File

@ -46,8 +46,7 @@
/* FPGA System Register declaration */ /* FPGA System Register declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct typedef struct {
{
__IO uint32_t LED; // Offset: 0x000 (R/W) LED connections __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections
// [31:2] : Reserved // [31:2] : Reserved
// [1:0] : LEDs // [1:0] : LEDs
@ -107,8 +106,7 @@ typedef struct
/* SCC Register declaration */ /* SCC Register declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct // typedef struct { //
{
__IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT __IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT
// [31:1] : Reserved // [31:1] : Reserved
// [0] 1 : REMAP BlockRam to ZBT // [0] 1 : REMAP BlockRam to ZBT
@ -166,8 +164,7 @@ typedef struct //
/* SSP Peripheral declaration */ /* SSP Peripheral declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf typedef struct { // Document DDI0194G_ssp_pl022_r1p3_trm.pdf
{
__IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0 __IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0
// [31:16] : Reserved // [31:16] : Reserved
// [15:8] : Serial clock rate // [15:8] : Serial clock rate
@ -314,8 +311,7 @@ typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf
/* Audio and Touch Screen (I2C) Peripheral declaration */ /* Audio and Touch Screen (I2C) Peripheral declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct typedef struct {
{
union { union {
__O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W) __O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W)
__I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ ) __I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ )
@ -331,8 +327,7 @@ typedef struct
/* Audio I2S Peripheral declaration */ /* Audio I2S Peripheral declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct typedef struct {
{
/*!< Offset: 0x000 CONTROL Register (R/W) */ /*!< Offset: 0x000 CONTROL Register (R/W) */
__IO uint32_t CONTROL; // <h> CONTROL </h> __IO uint32_t CONTROL; // <h> CONTROL </h>
// <o.0> TX Enable // <o.0> TX Enable
@ -486,44 +481,43 @@ typedef struct
/* SMSC9220 Register Definitions */ /* SMSC9220 Register Definitions */
/******************************************************************************/ /******************************************************************************/
typedef struct // SMSC LAN9220 typedef struct { // SMSC LAN9220
{ __I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0)
__I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0)
uint32_t RESERVED1[0x7]; uint32_t RESERVED1[0x7];
__O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20) __O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20)
uint32_t RESERVED2[0x7]; uint32_t RESERVED2[0x7];
__I uint32_t RX_STAT_PORT; // Receive FIFO status port (offset 0x40) __I uint32_t RX_STAT_PORT; // Receive FIFO status port (offset 0x40)
__I uint32_t RX_STAT_PEEK; // Receive FIFO status peek (offset 0x44) __I uint32_t RX_STAT_PEEK; // Receive FIFO status peek (offset 0x44)
__I uint32_t TX_STAT_PORT; // Transmit FIFO status port (offset 0x48) __I uint32_t TX_STAT_PORT; // Transmit FIFO status port (offset 0x48)
__I uint32_t TX_STAT_PEEK; // Transmit FIFO status peek (offset 0x4C) __I uint32_t TX_STAT_PEEK; // Transmit FIFO status peek (offset 0x4C)
__I uint32_t ID_REV; // Chip ID and Revision (offset 0x50) __I uint32_t ID_REV; // Chip ID and Revision (offset 0x50)
__IO uint32_t IRQ_CFG; // Main Interrupt Configuration (offset 0x54) __IO uint32_t IRQ_CFG; // Main Interrupt Configuration (offset 0x54)
__IO uint32_t INT_STS; // Interrupt Status (offset 0x58) __IO uint32_t INT_STS; // Interrupt Status (offset 0x58)
__IO uint32_t INT_EN; // Interrupt Enable Register (offset 0x5C) __IO uint32_t INT_EN; // Interrupt Enable Register (offset 0x5C)
uint32_t RESERVED3; // Reserved for future use (offset 0x60) uint32_t RESERVED3; // Reserved for future use (offset 0x60)
__I uint32_t BYTE_TEST; // Read-only byte order testing register 87654321h (offset 0x64) __I uint32_t BYTE_TEST; // Read-only byte order testing register 87654321h (offset 0x64)
__IO uint32_t FIFO_INT; // FIFO Level Interrupts (offset 0x68) __IO uint32_t FIFO_INT; // FIFO Level Interrupts (offset 0x68)
__IO uint32_t RX_CFG; // Receive Configuration (offset 0x6C) __IO uint32_t RX_CFG; // Receive Configuration (offset 0x6C)
__IO uint32_t TX_CFG; // Transmit Configuration (offset 0x70) __IO uint32_t TX_CFG; // Transmit Configuration (offset 0x70)
__IO uint32_t HW_CFG; // Hardware Configuration (offset 0x74) __IO uint32_t HW_CFG; // Hardware Configuration (offset 0x74)
__IO uint32_t RX_DP_CTL; // RX Datapath Control (offset 0x78) __IO uint32_t RX_DP_CTL; // RX Datapath Control (offset 0x78)
__I uint32_t RX_FIFO_INF; // Receive FIFO Information (offset 0x7C) __I uint32_t RX_FIFO_INF; // Receive FIFO Information (offset 0x7C)
__I uint32_t TX_FIFO_INF; // Transmit FIFO Information (offset 0x80) __I uint32_t TX_FIFO_INF; // Transmit FIFO Information (offset 0x80)
__IO uint32_t PMT_CTRL; // Power Management Control (offset 0x84) __IO uint32_t PMT_CTRL; // Power Management Control (offset 0x84)
__IO uint32_t GPIO_CFG; // General Purpose IO Configuration (offset 0x88) __IO uint32_t GPIO_CFG; // General Purpose IO Configuration (offset 0x88)
__IO uint32_t GPT_CFG; // General Purpose Timer Configuration (offset 0x8C) __IO uint32_t GPT_CFG; // General Purpose Timer Configuration (offset 0x8C)
__I uint32_t GPT_CNT; // General Purpose Timer Count (offset 0x90) __I uint32_t GPT_CNT; // General Purpose Timer Count (offset 0x90)
uint32_t RESERVED4; // Reserved for future use (offset 0x94) uint32_t RESERVED4; // Reserved for future use (offset 0x94)
__IO uint32_t ENDIAN; // WORD SWAP Register (offset 0x98) __IO uint32_t ENDIAN; // WORD SWAP Register (offset 0x98)
__I uint32_t FREE_RUN; // Free Run Counter (offset 0x9C) __I uint32_t FREE_RUN; // Free Run Counter (offset 0x9C)
__I uint32_t RX_DROP; // RX Dropped Frames Counter (offset 0xA0) __I uint32_t RX_DROP; // RX Dropped Frames Counter (offset 0xA0)
__IO uint32_t MAC_CSR_CMD; // MAC CSR Synchronizer Command (offset 0xA4) __IO uint32_t MAC_CSR_CMD; // MAC CSR Synchronizer Command (offset 0xA4)
__IO uint32_t MAC_CSR_DATA; // MAC CSR Synchronizer Data (offset 0xA8) __IO uint32_t MAC_CSR_DATA; // MAC CSR Synchronizer Data (offset 0xA8)
__IO uint32_t AFC_CFG; // Automatic Flow Control Configuration (offset 0xAC) __IO uint32_t AFC_CFG; // Automatic Flow Control Configuration (offset 0xAC)
__IO uint32_t E2P_CMD; // EEPROM Command (offset 0xB0) __IO uint32_t E2P_CMD; // EEPROM Command (offset 0xB0)
__IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4) __IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4)
} SMSC9220_TypeDef; } SMSC9220_TypeDef;

12
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/peripherallink.h
View File

@ -37,17 +37,17 @@
#define __DEVICE_H #define __DEVICE_H
#if defined CMSDK_CM0 #if defined CMSDK_CM0
#include "CMSDK_CM0.h" /* device specific header file */ #include "CMSDK_CM0.h" /* device specific header file */
#elif defined CMSDK_CM0plus #elif defined CMSDK_CM0plus
#include "CMSDK_CM0plus.h" /* device specific header file */ #include "CMSDK_CM0plus.h" /* device specific header file */
#elif defined CMSDK_CM3 #elif defined CMSDK_CM3
#include "CMSDK_CM3.h" /* device specific header file */ #include "CMSDK_CM3.h" /* device specific header file */
#elif defined CMSDK_CM4 #elif defined CMSDK_CM4
#include "CMSDK_CM4.h" /* device specific header file */ #include "CMSDK_CM4.h" /* device specific header file */
#elif defined CMSDK_CM7 #elif defined CMSDK_CM7
#include "CMSDK_CM7.h" /* device specific header file */ #include "CMSDK_CM7.h" /* device specific header file */
#else #else
#warning "no appropriate header file found!" #warning "no appropriate header file found!"
#endif #endif
#endif /* __DEVICE_H */ #endif /* __DEVICE_H */

20
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/system_CMSDK_CM7.c
View File

@ -37,13 +37,13 @@
#if defined (CMSDK_CM7) #if defined (CMSDK_CM7)
#include "CMSDK_CM7.h" #include "CMSDK_CM7.h"
#elif defined (CMSDK_CM7_SP) #elif defined (CMSDK_CM7_SP)
#include "CMSDK_CM7_SP.h" #include "CMSDK_CM7_SP.h"
#elif defined (CMSDK_CM7_DP) #elif defined (CMSDK_CM7_DP)
#include "CMSDK_CM7_DP.h" #include "CMSDK_CM7_DP.h"
#else #else
#error device not specified! #error device not specified!
#endif #endif
/*---------------------------------------------------------------------------- /*----------------------------------------------------------------------------
@ -72,7 +72,7 @@ uint32_t SystemCoreClock = __SYSTEM_CLOCK;/* System Core Clock Frequency */
* @brief Updates the SystemCoreClock with current core Clock * @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers. * retrieved from cpu registers.
*/ */
void SystemCoreClockUpdate (void) void SystemCoreClockUpdate(void)
{ {
SystemCoreClock = __SYSTEM_CLOCK; SystemCoreClock = __SYSTEM_CLOCK;
@ -88,12 +88,12 @@ void SystemCoreClockUpdate (void)
* @brief Setup the microcontroller system. * @brief Setup the microcontroller system.
* Initialize the System. * Initialize the System.
*/ */
void SystemInit (void) void SystemInit(void)
{ {
#if (__FPU_USED == 1) #if (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ SCB->CPACR |= ((3UL << 10 * 2) | /* set CP10 Full Access */
(3UL << 11*2) ); /* set CP11 Full Access */ (3UL << 11 * 2)); /* set CP11 Full Access */
#endif #endif
#ifdef UNALIGNED_SUPPORT_DISABLE #ifdef UNALIGNED_SUPPORT_DISABLE
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;

4
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/system_CMSDK_CM7.h
View File

@ -56,7 +56,7 @@ extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */
* @brief Setup the microcontroller system. * @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable. * Initialize the System and update the SystemCoreClock variable.
*/ */
extern void SystemInit (void); extern void SystemInit(void);
/** /**
* Update SystemCoreClock variable * Update SystemCoreClock variable
@ -67,7 +67,7 @@ extern void SystemInit (void);
* @brief Updates the SystemCoreClock with current core Clock * @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers. * retrieved from cpu registers.
*/ */
extern void SystemCoreClockUpdate (void); extern void SystemCoreClockUpdate(void);
#ifdef __cplusplus #ifdef __cplusplus
} }

30
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/analogin_api.c
View File

@ -38,35 +38,36 @@ static const PinMap PinMap_ADC[] = {
}; };
static const PinMap PinMap_SPI_SCLK[] = { static const PinMap PinMap_SPI_SCLK[] = {
{ADC_SCLK , SPI_3, 0}, {ADC_SCLK, SPI_3, 0},
{NC , NC , 0} {NC, NC, 0}
}; };
static const PinMap PinMap_SPI_MOSI[] = { static const PinMap PinMap_SPI_MOSI[] = {
{ADC_MOSI, SPI_3, 0}, {ADC_MOSI, SPI_3, 0},
{NC , NC , 0} {NC, NC, 0}
}; };
static const PinMap PinMap_SPI_MISO[] = { static const PinMap PinMap_SPI_MISO[] = {
{ADC_MISO, SPI_3, 0}, {ADC_MISO, SPI_3, 0},
{NC , NC , 0} {NC, NC, 0}
}; };
static const PinMap PinMap_SPI_SSEL[] = { static const PinMap PinMap_SPI_SSEL[] = {
{ADC_SSEL, SPI_3, 0}, {ADC_SSEL, SPI_3, 0},
{NC , NC , 0} {NC, NC, 0}
}; };
#define ADC_RANGE ADC_12BIT_RANGE #define ADC_RANGE ADC_12BIT_RANGE
int analog_spi_inited = 0; int analog_spi_inited = 0;
void analogin_init(analogin_t *obj, PinName pin) { void analogin_init(analogin_t *obj, PinName pin)
{
obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
MBED_ASSERT(obj->adc != (ADCName)NC); MBED_ASSERT(obj->adc != (ADCName)NC);
obj->pin = pin; obj->pin = pin;
obj->pin_number = pin-600; obj->pin_number = pin - 600;
obj->address = (0x0000 | (pin-600)); obj->address = (0x0000 | (pin - 600));
SPIName adc_mosi = (SPIName)pinmap_peripheral(ADC_MOSI, PinMap_SPI_MOSI); SPIName adc_mosi = (SPIName)pinmap_peripheral(ADC_MOSI, PinMap_SPI_MOSI);
SPIName adc_miso = (SPIName)pinmap_peripheral(ADC_MISO, PinMap_SPI_MISO); SPIName adc_miso = (SPIName)pinmap_peripheral(ADC_MISO, PinMap_SPI_MISO);
@ -74,9 +75,9 @@ void analogin_init(analogin_t *obj, PinName pin) {
SPIName adc_ssel = (SPIName)pinmap_peripheral(ADC_SSEL, PinMap_SPI_SSEL); SPIName adc_ssel = (SPIName)pinmap_peripheral(ADC_SSEL, PinMap_SPI_SSEL);
SPIName adc_data = (SPIName)pinmap_merge(adc_mosi, adc_miso); SPIName adc_data = (SPIName)pinmap_merge(adc_mosi, adc_miso);
SPIName adc_cntl = (SPIName)pinmap_merge(adc_sclk, adc_ssel); SPIName adc_cntl = (SPIName)pinmap_merge(adc_sclk, adc_ssel);
obj->adc_spi = (MPS2_SSP_TypeDef*)pinmap_merge(adc_data, adc_cntl); obj->adc_spi = (MPS2_SSP_TypeDef *)pinmap_merge(adc_data, adc_cntl);
if(analog_spi_inited == 0){ if (analog_spi_inited == 0) {
obj->adc_spi->CR1 = 0; obj->adc_spi->CR1 = 0;
obj->adc_spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_16; obj->adc_spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_16;
obj->adc_spi->CPSR = SSP_CPSR_DFLT; obj->adc_spi->CPSR = SSP_CPSR_DFLT;
@ -94,17 +95,20 @@ void analogin_init(analogin_t *obj, PinName pin) {
pinmap_pinout(pin, PinMap_ADC); pinmap_pinout(pin, PinMap_ADC);
} }
static inline uint32_t adc_read(analogin_t *obj) { static inline uint32_t adc_read(analogin_t *obj)
{
return 0; return 0;
} }
float analogin_read(analogin_t *obj) { float analogin_read(analogin_t *obj)
{
uint32_t value = adc_read(obj); uint32_t value = adc_read(obj);
return 0; return 0;
} }
uint16_t analogin_read_u16(analogin_t *obj) { uint16_t analogin_read_u16(analogin_t *obj)
{
return 0; return 0;
} }

2
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/device.h
View File

@ -17,7 +17,7 @@
// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. // The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
// Check the 'features' section of the target description in 'targets.json' for more details. // Check the 'features' section of the target description in 'targets.json' for more details.
#ifndef MBED_DEVICE_H #ifndef MBED_DEVICE_H
#define MBED_DEVICE_H #define MBED_DEVICE_H

18
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/ethernet_api.c
View File

@ -41,11 +41,11 @@ int ethernet_init()
int error; int error;
error = 0; error = 0;
if(smsc9220_check_id()) { if (smsc9220_check_id()) {
error = TRUE; error = TRUE;
} }
if(smsc9220_soft_reset()) { if (smsc9220_soft_reset()) {
error = TRUE; error = TRUE;
} }
@ -55,7 +55,7 @@ int ethernet_init()
// threshold to defaults specified. // threshold to defaults specified.
SMSC9220->AFC_CFG = 0x006E3740; SMSC9220->AFC_CFG = 0x006E3740;
if(smsc9220_wait_eeprom()) { if (smsc9220_wait_eeprom()) {
error = TRUE; error = TRUE;
} }
@ -66,11 +66,11 @@ int ethernet_init()
/* Configure MAC addresses here if needed. */ /* Configure MAC addresses here if needed. */
if(smsc9220_check_phy()) { if (smsc9220_check_phy()) {
error = TRUE; error = TRUE;
} }
if(smsc9220_reset_phy()) { if (smsc9220_reset_phy()) {
error = TRUE; error = TRUE;
return error; return error;
} }
@ -81,7 +81,7 @@ int ethernet_init()
unsigned short phyreset; unsigned short phyreset;
phyreset = 0; phyreset = 0;
smsc9220_phy_regread(SMSC9220_PHY_BCONTROL, &phyreset); smsc9220_phy_regread(SMSC9220_PHY_BCONTROL, &phyreset);
if(phyreset & (1 << 15)) { if (phyreset & (1 << 15)) {
error = TRUE; error = TRUE;
return error; return error;
} }
@ -118,7 +118,8 @@ int ethernet_init()
/*---------------------------------------------------------------------------- /*----------------------------------------------------------------------------
Ethernet Device Uninitialize Ethernet Device Uninitialize
*----------------------------------------------------------------------------*/ *----------------------------------------------------------------------------*/
void ethernet_free() { void ethernet_free()
{
} }
int ethernet_write(const char *data, int size) int ethernet_write(const char *data, int size)
@ -148,7 +149,8 @@ int ethernet_read(char *data, int dlen)
return 0; return 0;
} }
void ethernet_address(char *mac) { void ethernet_address(char *mac)
{
mbed_mac_address(mac); mbed_mac_address(mac);
} }

131
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/gpio_api.c
View File

@ -17,121 +17,132 @@
#include "pinmap.h" #include "pinmap.h"
// function to enable the GPIO pin // function to enable the GPIO pin
uint32_t gpio_set(PinName pin) { uint32_t gpio_set(PinName pin)
{
return (1); return (1);
} }
//function to initialise the gpio pin //function to initialise the gpio pin
// this links the board control bits for each pin // this links the board control bits for each pin
// with the object created for the pin // with the object created for the pin
void gpio_init(gpio_t *obj, PinName pin) { void gpio_init(gpio_t *obj, PinName pin)
if(pin == NC){ return;} {
else { if (pin == NC) {
return;
} else {
int pin_value = 0; int pin_value = 0;
obj->pin = pin; obj->pin = pin;
if(pin <=15){ if (pin <= 15) {
pin_value = pin; pin_value = pin;
}else if (pin >= 16 && pin <= 31){ } else if (pin >= 16 && pin <= 31) {
pin_value = pin-16; pin_value = pin - 16;
}else if (pin >= 32 && pin <= 47){ } else if (pin >= 32 && pin <= 47) {
pin_value = pin-32; pin_value = pin - 32;
}else if (pin >= 48 && pin <= 51){ } else if (pin >= 48 && pin <= 51) {
pin_value = pin-48; pin_value = pin - 48;
}else if (pin == 100 || pin == 101){ } else if (pin == 100 || pin == 101) {
pin_value = pin-100; pin_value = pin - 100;
}else if (pin == 110 || pin == 111){ } else if (pin == 110 || pin == 111) {
pin_value = pin-110; pin_value = pin - 110;
}else if (pin >= 200 && pin <= 207){ } else if (pin >= 200 && pin <= 207) {
pin_value = pin-200; pin_value = pin - 200;
}else if (pin >= 210 && pin <= 217){ } else if (pin >= 210 && pin <= 217) {
pin_value = pin-210; pin_value = pin - 210;
}else if (pin == 303){ } else if (pin == 303) {
pin_value = pin-302; pin_value = pin - 302;
}else if (pin == 307){ } else if (pin == 307) {
pin_value = pin-307; pin_value = pin - 307;
}else if (pin == 308){ } else if (pin == 308) {
pin_value = pin-305; pin_value = pin - 305;
}else if (pin == 309){ } else if (pin == 309) {
pin_value = pin-305; pin_value = pin - 305;
}else if (pin == 310){ } else if (pin == 310) {
pin_value = pin-305; pin_value = pin - 305;
}else if (pin == 311){ } else if (pin == 311) {
pin_value = pin-305; pin_value = pin - 305;
}else if (pin == 323){ } else if (pin == 323) {
pin_value = pin-315; pin_value = pin - 315;
}else if (pin == 334){ } else if (pin == 334) {
pin_value = pin-325; pin_value = pin - 325;
}else if (pin == 653){ } else if (pin == 653) {
pin_value = pin-646; pin_value = pin - 646;
} }
obj->mask = 0x1 << pin_value; obj->mask = 0x1 << pin_value;
obj->pin_number = pin; obj->pin_number = pin;
if(pin <=15) { if (pin <= 15) {
obj->reg_data = &CMSDK_GPIO0->DATAOUT ; obj->reg_data = &CMSDK_GPIO0->DATAOUT ;
obj->reg_in = &CMSDK_GPIO0->DATA ; obj->reg_in = &CMSDK_GPIO0->DATA ;
obj->reg_dir = &CMSDK_GPIO0->OUTENABLESET ; obj->reg_dir = &CMSDK_GPIO0->OUTENABLESET ;
obj->reg_dirclr = &CMSDK_GPIO0->OUTENABLECLR ; obj->reg_dirclr = &CMSDK_GPIO0->OUTENABLECLR ;
} else if (pin >= 16 && pin <= 31){ } else if (pin >= 16 && pin <= 31) {
obj->reg_data = &CMSDK_GPIO1->DATAOUT ; obj->reg_data = &CMSDK_GPIO1->DATAOUT ;
obj->reg_in = &CMSDK_GPIO1->DATA ; obj->reg_in = &CMSDK_GPIO1->DATA ;
obj->reg_dir = &CMSDK_GPIO1->OUTENABLESET ; obj->reg_dir = &CMSDK_GPIO1->OUTENABLESET ;
obj->reg_dirclr = &CMSDK_GPIO1->OUTENABLECLR ; obj->reg_dirclr = &CMSDK_GPIO1->OUTENABLECLR ;
} else if (pin >= 32 && pin <= 47){ } else if (pin >= 32 && pin <= 47) {
obj->reg_data = &CMSDK_GPIO2->DATAOUT; obj->reg_data = &CMSDK_GPIO2->DATAOUT;
obj->reg_in = &CMSDK_GPIO2->DATA; obj->reg_in = &CMSDK_GPIO2->DATA;
obj->reg_dir = &CMSDK_GPIO2->OUTENABLESET ; obj->reg_dir = &CMSDK_GPIO2->OUTENABLESET ;
obj->reg_dirclr = &CMSDK_GPIO2->OUTENABLECLR ; obj->reg_dirclr = &CMSDK_GPIO2->OUTENABLECLR ;
} else if (pin >= 48 && pin <= 51){ } else if (pin >= 48 && pin <= 51) {
obj->reg_data = &CMSDK_GPIO3->DATAOUT; obj->reg_data = &CMSDK_GPIO3->DATAOUT;
obj->reg_in = &CMSDK_GPIO3->DATA; obj->reg_in = &CMSDK_GPIO3->DATA;
obj->reg_dir = &CMSDK_GPIO3->OUTENABLESET ; obj->reg_dir = &CMSDK_GPIO3->OUTENABLESET ;
obj->reg_dirclr = &CMSDK_GPIO3->OUTENABLECLR ; obj->reg_dirclr = &CMSDK_GPIO3->OUTENABLECLR ;
} else if (pin == 100 || pin == 101){ } else if (pin == 100 || pin == 101) {
obj->reg_data = &MPS2_FPGAIO->LED; //user leds obj->reg_data = &MPS2_FPGAIO->LED; //user leds
obj->reg_in = &MPS2_FPGAIO->LED; obj->reg_in = &MPS2_FPGAIO->LED;
} else if (pin == 110 || pin == 111){ } else if (pin == 110 || pin == 111) {
obj->reg_data = &MPS2_FPGAIO->BUTTON; //user switches obj->reg_data = &MPS2_FPGAIO->BUTTON; //user switches
obj->reg_in = &MPS2_FPGAIO->BUTTON; //user switches obj->reg_in = &MPS2_FPGAIO->BUTTON; //user switches
}else if (pin >= 200 && pin <= 207){ } else if (pin >= 200 && pin <= 207) {
obj->reg_data = &MPS2_SCC->LEDS; //mcc leds obj->reg_data = &MPS2_SCC->LEDS; //mcc leds
obj->reg_in = &MPS2_SCC->LEDS; //mcc leds obj->reg_in = &MPS2_SCC->LEDS; //mcc leds
}else if (pin >= 210 && pin <= 217){ } else if (pin >= 210 && pin <= 217) {
obj->reg_in = &MPS2_SCC->SWITCHES; //mcc switches obj->reg_in = &MPS2_SCC->SWITCHES; //mcc switches
}else if (pin == 303 || pin == 307){ } else if (pin == 303 || pin == 307) {
obj->reg_data = &MPS2_FPGAIO->MISC; //spi chip select = 303, clcd chip select = 307 obj->reg_data = &MPS2_FPGAIO->MISC; //spi chip select = 303, clcd chip select = 307
}else if (pin == 308 || pin == 309 || pin == 310 || pin == 311){ } else if (pin == 308 || pin == 309 || pin == 310 || pin == 311) {
obj->reg_data = &MPS2_FPGAIO->MISC; //clcd control bits obj->reg_data = &MPS2_FPGAIO->MISC; //clcd control bits
}else if (pin == 323 || pin == 334 || pin == 653){ //spi 3 chip select = 323, spi 4 chip select = 334, adc chip select = 653 } else if (pin == 323 || pin == 334 || pin == 653) { //spi 3 chip select = 323, spi 4 chip select = 334, adc chip select = 653
obj->reg_data = &MPS2_FPGAIO->MISC; //spi cs bits obj->reg_data = &MPS2_FPGAIO->MISC; //spi cs bits
} }
if (pin == 323){ if (pin == 323) {
CMSDK_GPIO0->ALTFUNCSET |= 0x1000; CMSDK_GPIO0->ALTFUNCSET |= 0x1000;
}else if (pin == 334){ } else if (pin == 334) {
CMSDK_GPIO2->ALTFUNCSET |= 0x0040; CMSDK_GPIO2->ALTFUNCSET |= 0x0040;
}else if (pin == 653){ } else if (pin == 653) {
CMSDK_GPIO1->ALTFUNCSET |= 0x0001; CMSDK_GPIO1->ALTFUNCSET |= 0x0001;
} }
} }
} }
void gpio_mode(gpio_t *obj, PinMode mode) { void gpio_mode(gpio_t *obj, PinMode mode)
{
pin_mode(obj->pin, mode); pin_mode(obj->pin, mode);
} }
void gpio_dir(gpio_t *obj, PinDirection direction) { void gpio_dir(gpio_t *obj, PinDirection direction)
if(obj->pin >= 0 && obj->pin <= 51) {
{ if (obj->pin >= 0 && obj->pin <= 51) {
switch (direction) { switch (direction) {
case PIN_INPUT : *obj->reg_dirclr = obj->mask; break; case PIN_INPUT :
case PIN_OUTPUT: *obj->reg_dir |= obj->mask; break; *obj->reg_dirclr = obj->mask;
break;
case PIN_OUTPUT:
*obj->reg_dir |= obj->mask;
break;
}
} else {
return;
} }
} else {return;}
} }
int gpio_is_connected(const gpio_t *obj){ int gpio_is_connected(const gpio_t *obj)
if(obj->pin != (PinName)NC){ {
if (obj->pin != (PinName)NC) {
return 1; return 1;
} else { } else {
return 0; return 0;

353
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/gpio_irq_api.c
View File

@ -26,14 +26,17 @@
static uint32_t channel_ids[CHANNEL_NUM] = {0}; static uint32_t channel_ids[CHANNEL_NUM] = {0};
static gpio_irq_handler irq_handler; static gpio_irq_handler irq_handler;
static inline void handle_interrupt_in(uint32_t channel) { static inline void handle_interrupt_in(uint32_t channel)
{
uint32_t ch_bit = (1 << channel); uint32_t ch_bit = (1 << channel);
// Return immediately if: // Return immediately if:
// * The interrupt was already served // * The interrupt was already served
// * There is no user handler // * There is no user handler
// * It is a level interrupt, not an edge interrupt // * It is a level interrupt, not an edge interrupt
if (ch_bit <16){ if (ch_bit < 16) {
if ( ((CMSDK_GPIO_0->INTSTATUS) == 0) || (channel_ids[channel] == 0) || ((CMSDK_GPIO_0->INTTYPESET) == 0) ) return; if (((CMSDK_GPIO_0->INTSTATUS) == 0) || (channel_ids[channel] == 0) || ((CMSDK_GPIO_0->INTTYPESET) == 0)) {
return;
}
if ((CMSDK_GPIO_0->INTTYPESET & ch_bit) && (CMSDK_GPIO_0->INTPOLSET & ch_bit)) { if ((CMSDK_GPIO_0->INTTYPESET & ch_bit) && (CMSDK_GPIO_0->INTPOLSET & ch_bit)) {
irq_handler(channel_ids[channel], IRQ_RISE); irq_handler(channel_ids[channel], IRQ_RISE);
@ -45,8 +48,10 @@ static inline void handle_interrupt_in(uint32_t channel) {
CMSDK_GPIO_0->INTCLEAR = ch_bit; CMSDK_GPIO_0->INTCLEAR = ch_bit;
} }
if (ch_bit>=16) { if (ch_bit >= 16) {
if ( ((CMSDK_GPIO_1->INTSTATUS) == 0) || (channel_ids[channel] == 0) || ((CMSDK_GPIO_1->INTTYPESET) == 0) ) return; if (((CMSDK_GPIO_1->INTSTATUS) == 0) || (channel_ids[channel] == 0) || ((CMSDK_GPIO_1->INTTYPESET) == 0)) {
return;
}
if ((CMSDK_GPIO_1->INTTYPESET & ch_bit) && (CMSDK_GPIO_1->INTPOLSET & ch_bit)) { if ((CMSDK_GPIO_1->INTTYPESET & ch_bit) && (CMSDK_GPIO_1->INTPOLSET & ch_bit)) {
irq_handler(channel_ids[channel], IRQ_RISE); irq_handler(channel_ids[channel], IRQ_RISE);
@ -59,49 +64,147 @@ static inline void handle_interrupt_in(uint32_t channel) {
} }
} }
void gpio0_irq0(void) {handle_interrupt_in(0);} void gpio0_irq0(void)
void gpio0_irq1(void) {handle_interrupt_in(1);} {
void gpio0_irq2(void) {handle_interrupt_in(2);} handle_interrupt_in(0);
void gpio0_irq3(void) {handle_interrupt_in(3);} }
void gpio0_irq4(void) {handle_interrupt_in(4);} void gpio0_irq1(void)
void gpio0_irq5(void) {handle_interrupt_in(5);} {
void gpio0_irq6(void) {handle_interrupt_in(6);} handle_interrupt_in(1);
void gpio0_irq7(void) {handle_interrupt_in(7);} }
void gpio0_irq8(void) {handle_interrupt_in(8);} void gpio0_irq2(void)
void gpio0_irq9(void) {handle_interrupt_in(9);} {
void gpio0_irq10(void) {handle_interrupt_in(10);} handle_interrupt_in(2);
void gpio0_irq11(void) {handle_interrupt_in(11);} }
void gpio0_irq12(void) {handle_interrupt_in(12);} void gpio0_irq3(void)
void gpio0_irq13(void) {handle_interrupt_in(13);} {
void gpio0_irq14(void) {handle_interrupt_in(14);} handle_interrupt_in(3);
void gpio0_irq15(void) {handle_interrupt_in(15);} }
void gpio1_irq0(void) {handle_interrupt_in(16);} void gpio0_irq4(void)
void gpio1_irq1(void) {handle_interrupt_in(17);} {
void gpio1_irq2(void) {handle_interrupt_in(18);} handle_interrupt_in(4);
void gpio1_irq3(void) {handle_interrupt_in(19);} }
void gpio1_irq4(void) {handle_interrupt_in(20);} void gpio0_irq5(void)
void gpio1_irq5(void) {handle_interrupt_in(21);} {
void gpio1_irq6(void) {handle_interrupt_in(22);} handle_interrupt_in(5);
void gpio1_irq7(void) {handle_interrupt_in(23);} }
void gpio1_irq8(void) {handle_interrupt_in(24);} void gpio0_irq6(void)
void gpio1_irq9(void) {handle_interrupt_in(25);} {
void gpio1_irq10(void) {handle_interrupt_in(26);} handle_interrupt_in(6);
void gpio1_irq11(void) {handle_interrupt_in(27);} }
void gpio1_irq12(void) {handle_interrupt_in(28);} void gpio0_irq7(void)
void gpio1_irq13(void) {handle_interrupt_in(29);} {
void gpio1_irq14(void) {handle_interrupt_in(30);} handle_interrupt_in(7);
void gpio1_irq15(void) {handle_interrupt_in(31);} }
void gpio0_irq8(void)
{
handle_interrupt_in(8);
}
void gpio0_irq9(void)
{
handle_interrupt_in(9);
}
void gpio0_irq10(void)
{
handle_interrupt_in(10);
}
void gpio0_irq11(void)
{
handle_interrupt_in(11);
}
void gpio0_irq12(void)
{
handle_interrupt_in(12);
}
void gpio0_irq13(void)
{
handle_interrupt_in(13);
}
void gpio0_irq14(void)
{
handle_interrupt_in(14);
}
void gpio0_irq15(void)
{
handle_interrupt_in(15);
}
void gpio1_irq0(void)
{
handle_interrupt_in(16);
}
void gpio1_irq1(void)
{
handle_interrupt_in(17);
}
void gpio1_irq2(void)
{
handle_interrupt_in(18);
}
void gpio1_irq3(void)
{
handle_interrupt_in(19);
}
void gpio1_irq4(void)
{
handle_interrupt_in(20);
}
void gpio1_irq5(void)
{
handle_interrupt_in(21);
}
void gpio1_irq6(void)
{
handle_interrupt_in(22);
}
void gpio1_irq7(void)
{
handle_interrupt_in(23);
}
void gpio1_irq8(void)
{
handle_interrupt_in(24);
}
void gpio1_irq9(void)
{
handle_interrupt_in(25);
}
void gpio1_irq10(void)
{
handle_interrupt_in(26);
}
void gpio1_irq11(void)
{
handle_interrupt_in(27);
}
void gpio1_irq12(void)
{
handle_interrupt_in(28);
}
void gpio1_irq13(void)
{
handle_interrupt_in(29);
}
void gpio1_irq14(void)
{
handle_interrupt_in(30);
}
void gpio1_irq15(void)
{
handle_interrupt_in(31);
}
int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) { int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
if (pin == NC) {return -1;} {
else { if (pin == NC) {
return -1;
} else {
irq_handler = handler; irq_handler = handler;
int found_free_channel = 0; int found_free_channel = 0;
int i = 0; int i = 0;
for (i=0; i<CHANNEL_NUM; i++) { for (i = 0; i < CHANNEL_NUM; i++) {
if (channel_ids[i] == 0) { if (channel_ids[i] == 0) {
channel_ids[i] = id; channel_ids[i] = id;
obj->ch = i; obj->ch = i;
@ -109,57 +212,121 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32
break; break;
} }
} }
if (!found_free_channel) return -1; if (!found_free_channel) {
return -1;
}
/* To select a pin for any of the eight pin interrupts, write the pin number /* To select a pin for any of the eight pin interrupts, write the pin number
* as 0 to 23 for pins PIO0_0 to PIO0_23 and 24 to 55. * as 0 to 23 for pins PIO0_0 to PIO0_23 and 24 to 55.
* @see: mbed_capi/PinNames.h * @see: mbed_capi/PinNames.h
*/ */
if (pin <16) if (pin < 16) {
{
CMSDK_GPIO_0->INTENSET |= (0x1 << pin); CMSDK_GPIO_0->INTENSET |= (0x1 << pin);
} }
if (pin >= 16) if (pin >= 16) {
{
CMSDK_GPIO_1->INTENSET |= (0x1 << pin); CMSDK_GPIO_1->INTENSET |= (0x1 << pin);
} }
void (*channels_irq)(void) = NULL; void (*channels_irq)(void) = NULL;
switch (obj->ch) { switch (obj->ch) {
case 0: channels_irq = &gpio0_irq0; break; case 0:
case 1: channels_irq = &gpio0_irq1; break; channels_irq = &gpio0_irq0;
case 2: channels_irq = &gpio0_irq2; break; break;
case 3: channels_irq = &gpio0_irq3; break; case 1:
case 4: channels_irq = &gpio0_irq4; break; channels_irq = &gpio0_irq1;
case 5: channels_irq = &gpio0_irq5; break; break;
case 6: channels_irq = &gpio0_irq6; break; case 2:
case 7: channels_irq = &gpio0_irq7; break; channels_irq = &gpio0_irq2;
case 8: channels_irq = &gpio0_irq8; break; break;
case 9: channels_irq = &gpio0_irq9; break; case 3:
case 10: channels_irq = &gpio0_irq10; break; channels_irq = &gpio0_irq3;
case 11: channels_irq = &gpio0_irq11; break; break;
case 12: channels_irq = &gpio0_irq12; break; case 4:
case 13: channels_irq = &gpio0_irq13; break; channels_irq = &gpio0_irq4;
case 14: channels_irq = &gpio0_irq14; break; break;
case 15: channels_irq = &gpio0_irq15; break; case 5:
case 16: channels_irq = &gpio1_irq0; break; channels_irq = &gpio0_irq5;
case 17: channels_irq = &gpio1_irq1; break; break;
case 18: channels_irq = &gpio1_irq2; break; case 6:
case 19: channels_irq = &gpio1_irq3; break; channels_irq = &gpio0_irq6;
case 20: channels_irq = &gpio1_irq4; break; break;
case 21: channels_irq = &gpio1_irq5; break; case 7:
case 22: channels_irq = &gpio1_irq6; break; channels_irq = &gpio0_irq7;
case 23: channels_irq = &gpio1_irq7; break; break;
case 24: channels_irq = &gpio1_irq8; break; case 8:
case 25: channels_irq = &gpio1_irq9; break; channels_irq = &gpio0_irq8;
case 26: channels_irq = &gpio1_irq10; break; break;
case 27: channels_irq = &gpio1_irq11; break; case 9:
case 28: channels_irq = &gpio1_irq12; break; channels_irq = &gpio0_irq9;
case 29: channels_irq = &gpio1_irq13; break; break;
case 30: channels_irq = &gpio1_irq14; break; case 10:
case 31: channels_irq = &gpio1_irq15; break; channels_irq = &gpio0_irq10;
break;
case 11:
channels_irq = &gpio0_irq11;
break;
case 12:
channels_irq = &gpio0_irq12;
break;
case 13:
channels_irq = &gpio0_irq13;
break;
case 14:
channels_irq = &gpio0_irq14;
break;
case 15:
channels_irq = &gpio0_irq15;
break;
case 16:
channels_irq = &gpio1_irq0;
break;
case 17:
channels_irq = &gpio1_irq1;
break;
case 18:
channels_irq = &gpio1_irq2;
break;
case 19:
channels_irq = &gpio1_irq3;
break;
case 20:
channels_irq = &gpio1_irq4;
break;
case 21:
channels_irq = &gpio1_irq5;
break;
case 22:
channels_irq = &gpio1_irq6;
break;
case 23:
channels_irq = &gpio1_irq7;
break;
case 24:
channels_irq = &gpio1_irq8;
break;
case 25:
channels_irq = &gpio1_irq9;
break;
case 26:
channels_irq = &gpio1_irq10;
break;
case 27:
channels_irq = &gpio1_irq11;
break;
case 28:
channels_irq = &gpio1_irq12;
break;
case 29:
channels_irq = &gpio1_irq13;
break;
case 30:
channels_irq = &gpio1_irq14;
break;
case 31:
channels_irq = &gpio1_irq15;
break;
} }
NVIC_SetVector((IRQn_Type)(PININT_IRQ + obj->ch), (uint32_t)channels_irq); NVIC_SetVector((IRQn_Type)(PININT_IRQ + obj->ch), (uint32_t)channels_irq);
@ -169,31 +336,28 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32
} }
} }
void gpio_irq_free(gpio_irq_t *obj) { void gpio_irq_free(gpio_irq_t *obj)
{
} }
void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) { void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
{
unsigned int ch_bit = (1 << obj->ch); unsigned int ch_bit = (1 << obj->ch);
// Clear interrupt // Clear interrupt
if (obj->ch <16) if (obj->ch < 16) {
{ if (!(CMSDK_GPIO_0->INTTYPESET & ch_bit)) {
if (!(CMSDK_GPIO_0->INTTYPESET & ch_bit))
{
CMSDK_GPIO_0->INTCLEAR = ch_bit; CMSDK_GPIO_0->INTCLEAR = ch_bit;
} }
} }
if (obj->ch >= 16) if (obj->ch >= 16) {
{ if (!(CMSDK_GPIO_1->INTTYPESET & ch_bit)) {
if (!(CMSDK_GPIO_1->INTTYPESET & ch_bit))
{
CMSDK_GPIO_1->INTCLEAR = ch_bit; CMSDK_GPIO_1->INTCLEAR = ch_bit;
} }
} }
// Edge trigger // Edge trigger
if (obj->ch <16) if (obj->ch < 16) {
{
CMSDK_GPIO_0->INTTYPESET &= ch_bit; CMSDK_GPIO_0->INTTYPESET &= ch_bit;
if (event == IRQ_RISE) { if (event == IRQ_RISE) {
CMSDK_GPIO_0->INTPOLSET |= ch_bit; CMSDK_GPIO_0->INTPOLSET |= ch_bit;
@ -211,8 +375,7 @@ void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
} }
} }
} }
if (obj->ch >= 16) if (obj->ch >= 16) {
{
CMSDK_GPIO_1->INTTYPESET &= ch_bit; CMSDK_GPIO_1->INTTYPESET &= ch_bit;
if (event == IRQ_RISE) { if (event == IRQ_RISE) {
CMSDK_GPIO_1->INTPOLSET |= ch_bit; CMSDK_GPIO_1->INTPOLSET |= ch_bit;
@ -232,10 +395,12 @@ void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
} }
} }
void gpio_irq_enable(gpio_irq_t *obj) { void gpio_irq_enable(gpio_irq_t *obj)
{
NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch)); NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
} }
void gpio_irq_disable(gpio_irq_t *obj) { void gpio_irq_disable(gpio_irq_t *obj)
{
NVIC_DisableIRQ((IRQn_Type)(PININT_IRQ + obj->ch)); NVIC_DisableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
} }

8
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/gpio_object.h
View File

@ -36,15 +36,17 @@ typedef struct {
__I uint32_t *reg_in; __I uint32_t *reg_in;
} gpio_t; } gpio_t;
static inline void gpio_write(gpio_t *obj, int value) { static inline void gpio_write(gpio_t *obj, int value)
if (value){ {
if (value) {
*obj->reg_data |= (obj->mask); *obj->reg_data |= (obj->mask);
} else { } else {
*obj->reg_data &= ~(obj->mask); *obj->reg_data &= ~(obj->mask);
} }
} }
static inline int gpio_read(gpio_t *obj) { static inline int gpio_read(gpio_t *obj)
{
return ((*obj->reg_in & obj->mask) ? 1 : 0); return ((*obj->reg_in & obj->mask) ? 1 : 0);
} }

208
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/i2c_api.c
View File

@ -56,7 +56,7 @@ static const PinMap PinMap_I2C_SDA[] = {
{AUD_SDA, I2C_1, 0}, {AUD_SDA, I2C_1, 0},
{SHIELD_0_SDA, I2C_2, 0}, {SHIELD_0_SDA, I2C_2, 0},
{SHIELD_1_SDA, I2C_3, 0}, {SHIELD_1_SDA, I2C_3, 0},
{NC , NC , 0} {NC, NC, 0}
}; };
static const PinMap PinMap_I2C_SCL[] = { static const PinMap PinMap_I2C_SCL[] = {
@ -64,7 +64,7 @@ static const PinMap PinMap_I2C_SCL[] = {
{AUD_SCL, I2C_1, 0}, {AUD_SCL, I2C_1, 0},
{SHIELD_0_SCL, I2C_2, 0}, {SHIELD_0_SCL, I2C_2, 0},
{SHIELD_1_SCL, I2C_3, 0}, {SHIELD_1_SCL, I2C_3, 0},
{NC , NC, 0} {NC, NC, 0}
}; };
static inline void i2c_send_byte(i2c_t *obj, unsigned char c) static inline void i2c_send_byte(i2c_t *obj, unsigned char c)
@ -75,12 +75,12 @@ static inline void i2c_send_byte(i2c_t *obj, unsigned char c)
obj->i2c->CONTROLC = SCL; obj->i2c->CONTROLC = SCL;
i2c_delay(TSC_TSU); i2c_delay(TSC_TSU);
for (loop = 0; loop < 8; loop++) for (loop = 0; loop < 8; loop++) {
{ if (c & (1 << (7 - loop))) {
if (c & (1 << (7 - loop)))
obj->i2c->CONTROLS = SDA; obj->i2c->CONTROLS = SDA;
else } else {
obj->i2c->CONTROLC = SDA; obj->i2c->CONTROLC = SDA;
}
i2c_delay(TSC_TSU); i2c_delay(TSC_TSU);
obj->i2c->CONTROLS = SCL; obj->i2c->CONTROLS = SCL;
@ -97,10 +97,11 @@ static inline void i2c_send_byte(i2c_t *obj, unsigned char c)
i2c_delay(AAIC_TSU); i2c_delay(AAIC_TSU);
obj->i2c->CONTROLC = SCL; obj->i2c->CONTROLC = SCL;
i2c_delay(AAIC_TSU); i2c_delay(AAIC_TSU);
if (c & (1 << (7 - loop))) if (c & (1 << (7 - loop))) {
obj->i2c->CONTROLS = SDA; obj->i2c->CONTROLS = SDA;
else } else {
obj->i2c->CONTROLC = SDA; obj->i2c->CONTROLC = SDA;
}
i2c_delay(AAIC_TSU); i2c_delay(AAIC_TSU);
obj->i2c->CONTROLS = SCL; obj->i2c->CONTROLS = SCL;
@ -117,12 +118,12 @@ static inline void i2c_send_byte(i2c_t *obj, unsigned char c)
obj->i2c->CONTROLC = SCL; obj->i2c->CONTROLC = SCL;
i2c_delay(SHIELD_TSU); i2c_delay(SHIELD_TSU);
for (loop = 0; loop < 8; loop++) for (loop = 0; loop < 8; loop++) {
{ if (c & (1 << (7 - loop))) {
if (c & (1 << (7 - loop)))
obj->i2c->CONTROLS = SDA; obj->i2c->CONTROLS = SDA;
else } else {
obj->i2c->CONTROLC = SDA; obj->i2c->CONTROLC = SDA;
}
i2c_delay(SHIELD_TSU); i2c_delay(SHIELD_TSU);
obj->i2c->CONTROLS = SCL; obj->i2c->CONTROLS = SCL;
@ -147,12 +148,12 @@ static inline unsigned char i2c_receive_byte(i2c_t *obj)
data_receive_byte = 0; data_receive_byte = 0;
for (loop = 0; loop < 8; loop++) for (loop = 0; loop < 8; loop++) {
{
obj->i2c->CONTROLS = SCL; obj->i2c->CONTROLS = SCL;
i2c_delay(TSC_TSU); i2c_delay(TSC_TSU);
if ((obj->i2c->CONTROL & SDA)) if ((obj->i2c->CONTROL & SDA)) {
data_receive_byte += (1 << (7 - loop)); data_receive_byte += (1 << (7 - loop));
}
obj->i2c->CONTROLC = SCL; obj->i2c->CONTROLC = SCL;
i2c_delay(TSC_TSU); i2c_delay(TSC_TSU);
@ -171,8 +172,9 @@ static inline unsigned char i2c_receive_byte(i2c_t *obj)
i2c_delay(AAIC_TSU); i2c_delay(AAIC_TSU);
obj->i2c->CONTROLS = SCL | SDA; obj->i2c->CONTROLS = SCL | SDA;
i2c_delay(AAIC_TSU); i2c_delay(AAIC_TSU);
if ((obj->i2c->CONTROL & SDA)) if ((obj->i2c->CONTROL & SDA)) {
data_receive_byte += (1 << (7 - loop)); data_receive_byte += (1 << (7 - loop));
}
i2c_delay(AAIC_TSU); i2c_delay(AAIC_TSU);
obj->i2c->CONTROLC = SCL; obj->i2c->CONTROLC = SCL;
@ -189,12 +191,12 @@ static inline unsigned char i2c_receive_byte(i2c_t *obj)
data_receive_byte = 0; data_receive_byte = 0;
for (loop = 0; loop < 8; loop++) for (loop = 0; loop < 8; loop++) {
{
obj->i2c->CONTROLS = SCL; obj->i2c->CONTROLS = SCL;
i2c_delay(SHIELD_TSU); i2c_delay(SHIELD_TSU);
if ((obj->i2c->CONTROL & SDA)) if ((obj->i2c->CONTROL & SDA)) {
data_receive_byte += (1 << (7 - loop)); data_receive_byte += (1 << (7 - loop));
}
obj->i2c->CONTROLC = SCL; obj->i2c->CONTROLC = SCL;
i2c_delay(SHIELD_TSU); i2c_delay(SHIELD_TSU);
@ -212,10 +214,18 @@ static inline int i2c_receive_ack(i2c_t *obj)
int nack; int nack;
int delay_value; int delay_value;
switch ((int)obj->i2c) { switch ((int)obj->i2c) {
case I2C_0: delay_value = TSC_TSU; break; case I2C_0:
case I2C_1: delay_value = AAIC_TSU; break; delay_value = TSC_TSU;
case I2C_2: delay_value = SHIELD_TSU; break; break;
case I2C_3: delay_value = SHIELD_TSU; break; case I2C_1:
delay_value = AAIC_TSU;
break;
case I2C_2:
delay_value = SHIELD_TSU;
break;
case I2C_3:
delay_value = SHIELD_TSU;
break;
} }
i2c_delay(delay_value); i2c_delay(delay_value);
@ -231,8 +241,9 @@ static inline int i2c_receive_ack(i2c_t *obj)
i2c_delay(delay_value); i2c_delay(delay_value);
obj->i2c->CONTROLS = SDA; obj->i2c->CONTROLS = SDA;
i2c_delay(delay_value); i2c_delay(delay_value);
if(nack==0) if (nack == 0) {
return 1; return 1;
}
return 0; return 0;
} }
@ -242,10 +253,18 @@ static inline void i2c_send_nack(i2c_t *obj)
{ {
int delay_value; int delay_value;
switch ((int)obj->i2c) { switch ((int)obj->i2c) {
case I2C_0: delay_value = TSC_TSU; break; case I2C_0:
case I2C_1: delay_value = AAIC_TSU; break; delay_value = TSC_TSU;
case I2C_2: delay_value = SHIELD_TSU; break; break;
case I2C_3: delay_value = SHIELD_TSU; break; case I2C_1:
delay_value = AAIC_TSU;
break;
case I2C_2:
delay_value = SHIELD_TSU;
break;
case I2C_3:
delay_value = SHIELD_TSU;
break;
} }
i2c_delay(delay_value); i2c_delay(delay_value);
@ -266,10 +285,18 @@ static inline void i2c_send_ack(i2c_t *obj)
{ {
int delay_value; int delay_value;
switch ((int)obj->i2c) { switch ((int)obj->i2c) {
case I2C_0: delay_value = TSC_TSU; break; case I2C_0:
case I2C_1: delay_value = AAIC_TSU; break; delay_value = TSC_TSU;
case I2C_2: delay_value = SHIELD_TSU; break; break;
case I2C_3: delay_value = SHIELD_TSU; break; case I2C_1:
delay_value = AAIC_TSU;
break;
case I2C_2:
delay_value = SHIELD_TSU;
break;
case I2C_3:
delay_value = SHIELD_TSU;
break;
} }
i2c_delay(delay_value); i2c_delay(delay_value);
@ -297,9 +324,13 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl)
pinmap_pinout(scl, PinMap_I2C_SCL); pinmap_pinout(scl, PinMap_I2C_SCL);
switch ((int)obj->i2c) { switch ((int)obj->i2c) {
case I2C_2: CMSDK_GPIO0->ALTFUNCSET |= 0x8020; break; case I2C_2:
case I2C_3: CMSDK_GPIO1->ALTFUNCSET |= 0x8000; CMSDK_GPIO0->ALTFUNCSET |= 0x8020;
CMSDK_GPIO2->ALTFUNCSET |= 0x0200; break; break;
case I2C_3:
CMSDK_GPIO1->ALTFUNCSET |= 0x8000;
CMSDK_GPIO2->ALTFUNCSET |= 0x0200;
break;
} }
@ -309,10 +340,18 @@ int i2c_start(i2c_t *obj)
{ {
int delay_value; int delay_value;
switch ((int)obj->i2c) { switch ((int)obj->i2c) {
case I2C_0: delay_value = TSC_TSU; break; case I2C_0:
case I2C_1: delay_value = AAIC_TSU; break; delay_value = TSC_TSU;
case I2C_2: delay_value = SHIELD_TSU; break; break;
case I2C_3: delay_value = SHIELD_TSU; break; case I2C_1:
delay_value = AAIC_TSU;
break;
case I2C_2:
delay_value = SHIELD_TSU;
break;
case I2C_3:
delay_value = SHIELD_TSU;
break;
} }
i2c_delay(delay_value); i2c_delay(delay_value);
@ -328,10 +367,18 @@ int i2c_start_tsc(i2c_t *obj)
{ {
int delay_value; int delay_value;
switch ((int)obj->i2c) { switch ((int)obj->i2c) {
case I2C_0: delay_value = TSC_TSU; break; case I2C_0:
case I2C_1: delay_value = AAIC_TSU; break; delay_value = TSC_TSU;
case I2C_2: delay_value = SHIELD_TSU; break; break;
case I2C_3: delay_value = SHIELD_TSU; break; case I2C_1:
delay_value = AAIC_TSU;
break;
case I2C_2:
delay_value = SHIELD_TSU;
break;
case I2C_3:
delay_value = SHIELD_TSU;
break;
} }
i2c_delay(delay_value); i2c_delay(delay_value);
@ -347,10 +394,18 @@ int i2c_stop(i2c_t *obj)
{ {
int delay_value; int delay_value;
switch ((int)obj->i2c) { switch ((int)obj->i2c) {
case I2C_0: delay_value = TSC_TSU; break; case I2C_0:
case I2C_1: delay_value = AAIC_TSU; break; delay_value = TSC_TSU;
case I2C_2: delay_value = SHIELD_TSU; break; break;
case I2C_3: delay_value = SHIELD_TSU; break; case I2C_1:
delay_value = AAIC_TSU;
break;
case I2C_2:
delay_value = SHIELD_TSU;
break;
case I2C_3:
delay_value = SHIELD_TSU;
break;
} }
// Actual stop bit // Actual stop bit
i2c_delay(delay_value); i2c_delay(delay_value);
@ -366,14 +421,15 @@ int i2c_stop(i2c_t *obj)
void i2c_frequency(i2c_t *obj, int hz) { void i2c_frequency(i2c_t *obj, int hz)
{
} }
int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
{ {
unsigned int loop, rxdata; unsigned int loop, rxdata;
int sadr, ack, bytes_read; int sadr, ack, bytes_read;
rxdata=0; rxdata = 0;
switch ((int)obj->i2c) { switch ((int)obj->i2c) {
case I2C_0: case I2C_0:
sadr = TSC_I2C_ADDR; sadr = TSC_I2C_ADDR;
@ -393,7 +449,7 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
switch ((int)obj->i2c) { switch ((int)obj->i2c) {
case I2C_0: case I2C_0:
// Set serial and register address // Set serial and register address
i2c_send_byte(obj,sadr); i2c_send_byte(obj, sadr);
ack += i2c_receive_ack(obj); ack += i2c_receive_ack(obj);
i2c_send_byte(obj, address); i2c_send_byte(obj, address);
ack += i2c_receive_ack(obj); ack += i2c_receive_ack(obj);
@ -405,17 +461,15 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
i2c_start_tsc(obj); i2c_start_tsc(obj);
// Read from I2C address // Read from I2C address
i2c_send_byte(obj,sadr | 1); i2c_send_byte(obj, sadr | 1);
ack += i2c_receive_ack(obj); ack += i2c_receive_ack(obj);
rxdata = (i2c_receive_byte(obj) & 0xFF); rxdata = (i2c_receive_byte(obj) & 0xFF);
data[((length-1)-bytes_read)] = (char)rxdata; data[((length - 1) - bytes_read)] = (char)rxdata;
bytes_read++; bytes_read++;
// Read multiple bytes // Read multiple bytes
if ((length > 1) && (length < 5)) if ((length > 1) && (length < 5)) {
{ for (loop = 1; loop <= (length - 1); loop++) {
for (loop = 1; loop <= (length - 1); loop++)
{
// Send ACK // Send ACK
i2c_send_ack(obj); i2c_send_ack(obj);
@ -423,7 +477,7 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
//rxdata = ((rxdata << 8) & 0xFFFFFF00); //rxdata = ((rxdata << 8) & 0xFFFFFF00);
//rxdata |= (i2c_receive_byte(obj) & 0xFF); //rxdata |= (i2c_receive_byte(obj) & 0xFF);
rxdata = i2c_receive_byte(obj); rxdata = i2c_receive_byte(obj);
data[(length-1)-bytes_read] = (char)rxdata; data[(length - 1) - bytes_read] = (char)rxdata;
bytes_read++; bytes_read++;
} }
@ -431,7 +485,7 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
break; break;
case I2C_1: case I2C_1:
// Set serial and register address // Set serial and register address
i2c_send_byte(obj,sadr); i2c_send_byte(obj, sadr);
ack += i2c_receive_ack(obj); ack += i2c_receive_ack(obj);
i2c_send_byte(obj, address); i2c_send_byte(obj, address);
ack += i2c_receive_ack(obj); ack += i2c_receive_ack(obj);
@ -445,17 +499,15 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
case I2C_2: case I2C_2:
case I2C_3: case I2C_3:
// Read from preset register address pointer // Read from preset register address pointer
i2c_send_byte(obj,sadr | 1); i2c_send_byte(obj, sadr | 1);
ack += i2c_receive_ack(obj); ack += i2c_receive_ack(obj);
rxdata = i2c_receive_byte(obj); rxdata = i2c_receive_byte(obj);
data[bytes_read] = (char)rxdata; data[bytes_read] = (char)rxdata;
bytes_read++; bytes_read++;
// Read multiple bytes // Read multiple bytes
if ((length > 1) && (length < 5)) if ((length > 1) && (length < 5)) {
{ for (loop = 1; loop <= (length - 1); loop++) {
for (loop = 1; loop <= (length - 1); loop++)
{
// Send ACK // Send ACK
i2c_send_ack(obj); i2c_send_ack(obj);
@ -477,13 +529,12 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
{ {
int ack=0; int ack = 0;
int sadr; int sadr;
char * ptr; char *ptr;
char addr; char addr;
ptr = (char*)data; ptr = (char *)data;
switch ((int)obj->i2c) switch ((int)obj->i2c) {
{
case I2C_0: case I2C_0:
sadr = TSC_I2C_ADDR; sadr = TSC_I2C_ADDR;
addr = address; addr = address;
@ -503,31 +554,36 @@ int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
i2c_start(obj); i2c_start(obj);
// Set serial and register address // Set serial and register address
i2c_send_byte(obj,sadr); i2c_send_byte(obj, sadr);
ack += i2c_receive_ack(obj); ack += i2c_receive_ack(obj);
i2c_send_byte(obj, addr); i2c_send_byte(obj, addr);
ack += i2c_receive_ack(obj); ack += i2c_receive_ack(obj);
for(int i = 1; i<length; i++) for (int i = 1; i < length; i++) {
{
i2c_send_byte(obj, *ptr++); i2c_send_byte(obj, *ptr++);
ack += i2c_receive_ack(obj); ack += i2c_receive_ack(obj);
} }
i2c_stop(obj); i2c_stop(obj);
if(ack==3) { return 1; } if (ack == 3) {
else{ return 0; } return 1;
} else {
return 0;
}
} }
void i2c_reset(i2c_t *obj) { void i2c_reset(i2c_t *obj)
{
i2c_stop(obj); i2c_stop(obj);
} }
int i2c_byte_read(i2c_t *obj, int last) { int i2c_byte_read(i2c_t *obj, int last)
{
return 0; return 0;
} }
int i2c_byte_write(i2c_t *obj, int data) { int i2c_byte_write(i2c_t *obj, int data)
{
return 0; return 0;
} }

6
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/pinmap.c
View File

@ -18,11 +18,13 @@
#include "mbed_error.h" #include "mbed_error.h"
void pin_function(PinName pin, int function) { void pin_function(PinName pin, int function)
{
MBED_ASSERT(pin != (PinName)NC); MBED_ASSERT(pin != (PinName)NC);
} }
void pin_mode(PinName pin, PinMode mode) { void pin_mode(PinName pin, PinMode mode)
{
MBED_ASSERT(pin != (PinName)NC); MBED_ASSERT(pin != (PinName)NC);
} }

34
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/port_api.c
View File

@ -17,11 +17,13 @@
#include "pinmap.h" #include "pinmap.h"
#include "gpio_api.h" #include "gpio_api.h"
PinName port_pin(PortName port, int pin_n) { PinName port_pin(PortName port, int pin_n)
{
return (PinName)((port << PORT_SHIFT) | pin_n); return (PinName)((port << PORT_SHIFT) | pin_n);
} }
void port_init(port_t *obj, PortName port, int mask, PinDirection dir) { void port_init(port_t *obj, PortName port, int mask, PinDirection dir)
{
obj->port = port; obj->port = port;
obj->mask = mask; obj->mask = mask;
@ -33,8 +35,8 @@ void port_init(port_t *obj, PortName port, int mask, PinDirection dir) {
uint32_t i; uint32_t i;
// The function is set per pin: reuse gpio logic // The function is set per pin: reuse gpio logic
for (i=0; i<16; i++) { for (i = 0; i < 16; i++) {
if (obj->mask & (1<<i)) { if (obj->mask & (1 << i)) {
gpio_set(port_pin(obj->port, i)); gpio_set(port_pin(obj->port, i));
} }
} }
@ -42,27 +44,35 @@ void port_init(port_t *obj, PortName port, int mask, PinDirection dir) {
port_dir(obj, dir); port_dir(obj, dir);
} }
void port_mode(port_t *obj, PinMode mode) { void port_mode(port_t *obj, PinMode mode)
{
uint32_t i; uint32_t i;
// The mode is set per pin: reuse pinmap logic // The mode is set per pin: reuse pinmap logic
for (i=0; i<32; i++) { for (i = 0; i < 32; i++) {
if (obj->mask & (1<<i)) { if (obj->mask & (1 << i)) {
pin_mode(port_pin(obj->port, i), mode); pin_mode(port_pin(obj->port, i), mode);
} }
} }
} }
void port_dir(port_t *obj, PinDirection dir) { void port_dir(port_t *obj, PinDirection dir)
{
switch (dir) { switch (dir) {
case PIN_INPUT : *obj->reg_dir &= ~obj->mask; break; case PIN_INPUT :
case PIN_OUTPUT: *obj->reg_dir |= obj->mask; break; *obj->reg_dir &= ~obj->mask;
break;
case PIN_OUTPUT:
*obj->reg_dir |= obj->mask;
break;
} }
} }
void port_write(port_t *obj, int value) { void port_write(port_t *obj, int value)
{
*obj->reg_in = value; *obj->reg_in = value;
} }
int port_read(port_t *obj) { int port_read(port_t *obj)
{
return (*obj->reg_in); return (*obj->reg_in);
} }

239
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/serial_api.c
View File

@ -30,19 +30,19 @@
******************************************************************************/ ******************************************************************************/
static const PinMap PinMap_UART_TX[] = { static const PinMap PinMap_UART_TX[] = {
{USBTX , UART_0, 0}, {USBTX, UART_0, 0},
{XB_TX , UART_1, 0}, {XB_TX, UART_1, 0},
{SH0_TX , UART_2, 0}, {SH0_TX, UART_2, 0},
{SH1_TX , UART_3, 0}, {SH1_TX, UART_3, 0},
{NC , NC , 0} {NC, NC, 0}
}; };
static const PinMap PinMap_UART_RX[] = { static const PinMap PinMap_UART_RX[] = {
{USBRX , UART_0, 0}, {USBRX, UART_0, 0},
{XB_RX , UART_1, 0}, {XB_RX, UART_1, 0},
{SH0_RX , UART_2, 0}, {SH0_RX, UART_2, 0},
{SH1_RX , UART_3, 0}, {SH1_RX, UART_3, 0},
{NC , NC , 0} {NC, NC, 0}
}; };
#define UART_NUM 4 #define UART_NUM 4
@ -60,7 +60,8 @@ struct serial_global_data_s {
static struct serial_global_data_s uart_data[UART_NUM]; static struct serial_global_data_s uart_data[UART_NUM];
void serial_init(serial_t *obj, PinName tx, PinName rx) { void serial_init(serial_t *obj, PinName tx, PinName rx)
{
int is_stdio_uart = 0; int is_stdio_uart = 0;
// determine the UART to use // determine the UART to use
@ -73,21 +74,17 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) {
obj->uart = (CMSDK_UART_TypeDef *)uart; obj->uart = (CMSDK_UART_TypeDef *)uart;
//set baud rate and enable Uart in normarl mode (RX and TX enabled) //set baud rate and enable Uart in normarl mode (RX and TX enabled)
switch (uart) switch (uart) {
{ case UART_0: {
case UART_0:
{
CMSDK_UART0->CTRL = 0x00; // Disable UART when changing configuration CMSDK_UART0->CTRL = 0x00; // Disable UART when changing configuration
if((int)uart_tx != NC) if ((int)uart_tx != NC) {
{
CMSDK_UART0->CTRL |= 0x01; // TX enable CMSDK_UART0->CTRL |= 0x01; // TX enable
} else { } else {
CMSDK_UART0->CTRL &= 0xFFFE; // TX disable CMSDK_UART0->CTRL &= 0xFFFE; // TX disable
} }
if((int)uart_rx != NC) if ((int)uart_rx != NC) {
{
CMSDK_UART0->CTRL |= 0x02; // RX enable CMSDK_UART0->CTRL |= 0x02; // RX enable
} else { } else {
CMSDK_UART0->CTRL &= 0xFFFD; // RX disable CMSDK_UART0->CTRL &= 0xFFFD; // RX disable
@ -95,46 +92,37 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) {
} }
break; break;
case UART_1: //XBEE SOCKET UART case UART_1: { //XBEE SOCKET UART
{
CMSDK_UART1->CTRL = 0x00; // Disable UART when changing configuration CMSDK_UART1->CTRL = 0x00; // Disable UART when changing configuration
if((int)tx != NC) if ((int)tx != NC) {
{
CMSDK_UART1->CTRL = 0x1; // TX enable CMSDK_UART1->CTRL = 0x1; // TX enable
CMSDK_GPIO1->ALTFUNCSET |= 0x0100; CMSDK_GPIO1->ALTFUNCSET |= 0x0100;
} }
if((int)rx != NC) if ((int)rx != NC) {
{
CMSDK_UART1->CTRL |= 0x2; // RX enable CMSDK_UART1->CTRL |= 0x2; // RX enable
CMSDK_GPIO1->ALTFUNCSET |= 0x0080; CMSDK_GPIO1->ALTFUNCSET |= 0x0080;
} }
} }
break; break;
case UART_2: //Sheild0 UART case UART_2: { //Sheild0 UART
{
CMSDK_UART3->CTRL = 0x00; // Disable UART when changing configuration CMSDK_UART3->CTRL = 0x00; // Disable UART when changing configuration
if((int)tx != NC) if ((int)tx != NC) {
{
CMSDK_UART3->CTRL = 0x1; // TX enable CMSDK_UART3->CTRL = 0x1; // TX enable
CMSDK_GPIO0->ALTFUNCSET |= 0x0010; CMSDK_GPIO0->ALTFUNCSET |= 0x0010;
} }
if((int)rx != NC) if ((int)rx != NC) {
{
CMSDK_UART3->CTRL |= 0x2; // RX enable CMSDK_UART3->CTRL |= 0x2; // RX enable
CMSDK_GPIO0->ALTFUNCSET |= 0x0001; CMSDK_GPIO0->ALTFUNCSET |= 0x0001;
} }
} }
break; break;
case UART_3: //Sheild1 UART case UART_3: { //Sheild1 UART
{
CMSDK_UART4->CTRL = 0x00; // Disable UART when changing configuration CMSDK_UART4->CTRL = 0x00; // Disable UART when changing configuration
if((int)tx != NC) if ((int)tx != NC) {
{
CMSDK_UART4->CTRL = 0x1; // TX enable CMSDK_UART4->CTRL = 0x1; // TX enable
CMSDK_GPIO1->ALTFUNCSET |= 0x4000; CMSDK_GPIO1->ALTFUNCSET |= 0x4000;
} }
if((int)rx != NC) if ((int)rx != NC) {
{
CMSDK_UART4->CTRL |= 0x2; // RX enable CMSDK_UART4->CTRL |= 0x2; // RX enable
CMSDK_GPIO1->ALTFUNCSET |= 0x0400; CMSDK_GPIO1->ALTFUNCSET |= 0x0400;
} }
@ -143,17 +131,25 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) {
} }
// set default baud rate and format // set default baud rate and format
serial_baud (obj, 9600); serial_baud(obj, 9600);
// pinout the chosen uart // pinout the chosen uart
pinmap_pinout(tx, PinMap_UART_TX); pinmap_pinout(tx, PinMap_UART_TX);
pinmap_pinout(rx, PinMap_UART_RX); pinmap_pinout(rx, PinMap_UART_RX);
switch (uart) { switch (uart) {
case UART_0: obj->index = 0; break; case UART_0:
case UART_1: obj->index = 1; break; obj->index = 0;
case UART_2: obj->index = 2; break; break;
case UART_3: obj->index = 3; break; case UART_1:
obj->index = 1;
break;
case UART_2:
obj->index = 2;
break;
case UART_3:
obj->index = 3;
break;
} }
uart_data[obj->index].sw_rts.pin = NC; uart_data[obj->index].sw_rts.pin = NC;
uart_data[obj->index].sw_cts.pin = NC; uart_data[obj->index].sw_cts.pin = NC;
@ -167,13 +163,15 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) {
} }
} }
void serial_free(serial_t *obj) { void serial_free(serial_t *obj)
{
uart_data[obj->index].serial_irq_id = 0; uart_data[obj->index].serial_irq_id = 0;
} }
// serial_baud // serial_baud
// set the baud rate, taking in to account the current SystemFrequency // set the baud rate, taking in to account the current SystemFrequency
void serial_baud(serial_t *obj, int baudrate) { void serial_baud(serial_t *obj, int baudrate)
{
// The MPS2 has a simple divider to control the baud rate. The formula is: // The MPS2 has a simple divider to control the baud rate. The formula is:
// //
// Baudrate = PCLK / BAUDDIV // Baudrate = PCLK / BAUDDIV
@ -185,13 +183,23 @@ void serial_baud(serial_t *obj, int baudrate) {
//check to see if minimum baud value entered //check to see if minimum baud value entered
int baudrate_div = 0; int baudrate_div = 0;
baudrate_div = SystemCoreClock / baudrate; baudrate_div = SystemCoreClock / baudrate;
if(baudrate >= 16){ if (baudrate >= 16) {
switch ((int)obj->uart) { switch ((int)obj->uart) {
case UART_0: CMSDK_UART0->BAUDDIV = baudrate_div; break; case UART_0:
case UART_1: CMSDK_UART1->BAUDDIV = baudrate_div; break; CMSDK_UART0->BAUDDIV = baudrate_div;
case UART_2: CMSDK_UART3->BAUDDIV = baudrate_div; break; break;
case UART_3: CMSDK_UART4->BAUDDIV = baudrate_div; break; case UART_1:
default: error("serial_baud"); break; CMSDK_UART1->BAUDDIV = baudrate_div;
break;
case UART_2:
CMSDK_UART3->BAUDDIV = baudrate_div;
break;
case UART_3:
CMSDK_UART4->BAUDDIV = baudrate_div;
break;
default:
error("serial_baud");
break;
} }
} else { } else {
error("serial_baud"); error("serial_baud");
@ -199,125 +207,122 @@ void serial_baud(serial_t *obj, int baudrate) {
} }
void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) { void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
{
} }
/****************************************************************************** /******************************************************************************
* INTERRUPTS HANDLING * INTERRUPTS HANDLING
******************************************************************************/ ******************************************************************************/
static inline void uart_irq(uint32_t intstatus, uint32_t index, CMSDK_UART_TypeDef *puart) { static inline void uart_irq(uint32_t intstatus, uint32_t index, CMSDK_UART_TypeDef *puart)
{
SerialIrq irq_type; SerialIrq irq_type;
switch (intstatus) switch (intstatus) {
{ case 1: {
case 1:
{
irq_type = TxIrq; irq_type = TxIrq;
} }
break; break;
case 2: case 2: {
{
irq_type = RxIrq; irq_type = RxIrq;
} }
break; break;
default: return; default:
return;
} /* End of Switch */ } /* End of Switch */
if ((RxIrq == irq_type) && (NC != uart_data[index].sw_rts.pin)) if ((RxIrq == irq_type) && (NC != uart_data[index].sw_rts.pin)) {
{
gpio_write(&uart_data[index].sw_rts, 1); gpio_write(&uart_data[index].sw_rts, 1);
// Disable interrupt if it wasn't enabled by other part of the application // Disable interrupt if it wasn't enabled by other part of the application
if (!uart_data[index].rx_irq_set_api) if (!uart_data[index].rx_irq_set_api) {
{
/* Disable Rx interrupt */ /* Disable Rx interrupt */
puart->CTRL &= ~(CMSDK_UART_CTRL_RXIRQEN_Msk); puart->CTRL &= ~(CMSDK_UART_CTRL_RXIRQEN_Msk);
} }
} }
if (uart_data[index].serial_irq_id != 0) if (uart_data[index].serial_irq_id != 0) {
{ if ((irq_type != RxIrq) || (uart_data[index].rx_irq_set_api)) {
if ((irq_type != RxIrq) || (uart_data[index].rx_irq_set_api))
{
irq_handler(uart_data[index].serial_irq_id, irq_type); irq_handler(uart_data[index].serial_irq_id, irq_type);
} }
} }
if( irq_type == TxIrq ) if (irq_type == TxIrq) {
{
/* Clear the TX interrupt Flag */ /* Clear the TX interrupt Flag */
puart->INTCLEAR |= 0x01; puart->INTCLEAR |= 0x01;
} } else {
else
{
/* Clear the Rx interupt Flag */ /* Clear the Rx interupt Flag */
puart->INTCLEAR |= 0x02; puart->INTCLEAR |= 0x02;
} }
} }
void uart0_irq() {uart_irq(CMSDK_UART0->INTSTATUS & 0x3, 0, (CMSDK_UART_TypeDef*)CMSDK_UART0);} void uart0_irq()
void uart1_irq() {uart_irq(CMSDK_UART1->INTSTATUS & 0x3, 1, (CMSDK_UART_TypeDef*)CMSDK_UART1);} {
void uart2_irq() {uart_irq(CMSDK_UART3->INTSTATUS & 0x3, 2, (CMSDK_UART_TypeDef*)CMSDK_UART3);} uart_irq(CMSDK_UART0->INTSTATUS & 0x3, 0, (CMSDK_UART_TypeDef *)CMSDK_UART0);
void uart3_irq() {uart_irq(CMSDK_UART4->INTSTATUS & 0x3, 3, (CMSDK_UART_TypeDef*)CMSDK_UART4);} }
void uart1_irq()
{
uart_irq(CMSDK_UART1->INTSTATUS & 0x3, 1, (CMSDK_UART_TypeDef *)CMSDK_UART1);
}
void uart2_irq()
{
uart_irq(CMSDK_UART3->INTSTATUS & 0x3, 2, (CMSDK_UART_TypeDef *)CMSDK_UART3);
}
void uart3_irq()
{
uart_irq(CMSDK_UART4->INTSTATUS & 0x3, 3, (CMSDK_UART_TypeDef *)CMSDK_UART4);
}
void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
{
irq_handler = handler; irq_handler = handler;
uart_data[obj->index].serial_irq_id = id; uart_data[obj->index].serial_irq_id = id;
} }
static void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enable) { static void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enable)
{
/* Declare a variable of type IRQn, initialise to 0 */ /* Declare a variable of type IRQn, initialise to 0 */
IRQn_Type irq_n = (IRQn_Type)0; IRQn_Type irq_n = (IRQn_Type)0;
uint32_t vector = 0; uint32_t vector = 0;
switch ((int)obj->uart) switch ((int)obj->uart) {
{ case UART_0: {
case UART_0: irq_n = ((irq == TxIrq) ? UARTTX0_IRQn : UARTRX0_IRQn);
{
irq_n = (( irq == TxIrq ) ? UARTTX0_IRQn : UARTRX0_IRQn);
vector = (uint32_t)&uart0_irq; vector = (uint32_t)&uart0_irq;
} }
break; break;
case UART_1: case UART_1: {
{ irq_n = ((irq == TxIrq) ? UARTTX1_IRQn : UARTRX1_IRQn);
irq_n = (( irq == TxIrq ) ? UARTTX1_IRQn : UARTRX1_IRQn);
vector = (uint32_t)&uart1_irq; vector = (uint32_t)&uart1_irq;
} }
break; break;
case UART_2: case UART_2: {
{ irq_n = ((irq == TxIrq) ? UARTTX3_IRQn : UARTRX3_IRQn);
irq_n = (( irq == TxIrq ) ? UARTTX3_IRQn : UARTRX3_IRQn);
vector = (uint32_t)&uart2_irq; vector = (uint32_t)&uart2_irq;
} }
break; break;
case UART_3: case UART_3: {
{ irq_n = ((irq == TxIrq) ? UARTTX4_IRQn : UARTRX4_IRQn);
irq_n = (( irq == TxIrq ) ? UARTTX4_IRQn : UARTRX4_IRQn);
vector = (uint32_t)&uart3_irq; vector = (uint32_t)&uart3_irq;
} }
break; break;
} }
if (enable) if (enable) {
{ if (irq == TxIrq) {
if( irq == TxIrq )
{
/* Transmit IRQ, set appripriate enable */ /* Transmit IRQ, set appripriate enable */
/* set TX interrupt enable in CTRL REG */ /* set TX interrupt enable in CTRL REG */
obj->uart->CTRL |= CMSDK_UART_CTRL_TXIRQEN_Msk; obj->uart->CTRL |= CMSDK_UART_CTRL_TXIRQEN_Msk;
} } else {
else
{
/* set Rx interrupt on in CTRL REG */ /* set Rx interrupt on in CTRL REG */
obj->uart->CTRL |= CMSDK_UART_CTRL_RXIRQEN_Msk; obj->uart->CTRL |= CMSDK_UART_CTRL_RXIRQEN_Msk;
} }
NVIC_SetVector(irq_n, vector); NVIC_SetVector(irq_n, vector);
NVIC_EnableIRQ(irq_n); NVIC_EnableIRQ(irq_n);
} } else {
else /* Disable IRQ */
{ /* Disable IRQ */
obj->uart->CTRL &= ~(1 << (irq + 2)); obj->uart->CTRL &= ~(1 << (irq + 2));
@ -325,45 +330,55 @@ static void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enabl
} }
} }
void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
{
serial_irq_set_internal(obj, irq, enable); serial_irq_set_internal(obj, irq, enable);
} }
/****************************************************************************** /******************************************************************************
* READ/WRITE * READ/WRITE
******************************************************************************/ ******************************************************************************/
int serial_getc(serial_t *obj) { int serial_getc(serial_t *obj)
{
while (serial_readable(obj) == 0); while (serial_readable(obj) == 0);
int data = obj->uart->DATA; int data = obj->uart->DATA;
return data; return data;
} }
void serial_putc(serial_t *obj, int c) { void serial_putc(serial_t *obj, int c)
{
while (serial_writable(obj) == 0); while (serial_writable(obj) == 0);
obj->uart->DATA = c; obj->uart->DATA = c;
} }
int serial_readable(serial_t *obj) { int serial_readable(serial_t *obj)
{
return obj->uart->STATE & 0x2; return obj->uart->STATE & 0x2;
} }
int serial_writable(serial_t *obj) { int serial_writable(serial_t *obj)
{
return !(obj->uart->STATE & 0x1); return !(obj->uart->STATE & 0x1);
} }
void serial_clear(serial_t *obj) { void serial_clear(serial_t *obj)
{
obj->uart->DATA = 0x00; obj->uart->DATA = 0x00;
} }
void serial_pinout_tx(PinName tx) { void serial_pinout_tx(PinName tx)
{
pinmap_pinout(tx, PinMap_UART_TX); pinmap_pinout(tx, PinMap_UART_TX);
} }
void serial_break_set(serial_t *obj) { void serial_break_set(serial_t *obj)
{
} }
void serial_break_clear(serial_t *obj) { void serial_break_clear(serial_t *obj)
{
} }
void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) { void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow)
{
} }

104
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/spi_api.c
View File

@ -23,12 +23,12 @@
#include "mbed_wait_api.h" #include "mbed_wait_api.h"
static const PinMap PinMap_SPI_SCLK[] = { static const PinMap PinMap_SPI_SCLK[] = {
{SCLK_SPI , SPI_0, 0}, {SCLK_SPI, SPI_0, 0},
{CLCD_SCLK , SPI_1, 0}, {CLCD_SCLK, SPI_1, 0},
{ADC_SCLK , SPI_2, 0}, {ADC_SCLK, SPI_2, 0},
{SHIELD_0_SPI_SCK , SPI_3, 0}, {SHIELD_0_SPI_SCK, SPI_3, 0},
{SHIELD_1_SPI_SCK , SPI_4, 0}, {SHIELD_1_SPI_SCK, SPI_4, 0},
{NC , NC , 0} {NC, NC, 0}
}; };
static const PinMap PinMap_SPI_MOSI[] = { static const PinMap PinMap_SPI_MOSI[] = {
@ -37,7 +37,7 @@ static const PinMap PinMap_SPI_MOSI[] = {
{ADC_MOSI, SPI_2, 0}, {ADC_MOSI, SPI_2, 0},
{SHIELD_0_SPI_MOSI, SPI_3, 0}, {SHIELD_0_SPI_MOSI, SPI_3, 0},
{SHIELD_1_SPI_MOSI, SPI_4, 0}, {SHIELD_1_SPI_MOSI, SPI_4, 0},
{NC , NC , 0} {NC, NC, 0}
}; };
static const PinMap PinMap_SPI_MISO[] = { static const PinMap PinMap_SPI_MISO[] = {
@ -46,7 +46,7 @@ static const PinMap PinMap_SPI_MISO[] = {
{ADC_MISO, SPI_2, 0}, {ADC_MISO, SPI_2, 0},
{SHIELD_0_SPI_MISO, SPI_3, 0}, {SHIELD_0_SPI_MISO, SPI_3, 0},
{SHIELD_1_SPI_MISO, SPI_4, 0}, {SHIELD_1_SPI_MISO, SPI_4, 0},
{NC , NC , 0} {NC, NC, 0}
}; };
static const PinMap PinMap_SPI_SSEL[] = { static const PinMap PinMap_SPI_SSEL[] = {
@ -55,13 +55,14 @@ static const PinMap PinMap_SPI_SSEL[] = {
{ADC_SSEL, SPI_2, 0}, {ADC_SSEL, SPI_2, 0},
{SHIELD_0_SPI_nCS, SPI_3, 0}, {SHIELD_0_SPI_nCS, SPI_3, 0},
{SHIELD_1_SPI_nCS, SPI_4, 0}, {SHIELD_1_SPI_nCS, SPI_4, 0},
{NC , NC , 0} {NC, NC, 0}
}; };
static inline int ssp_disable(spi_t *obj); static inline int ssp_disable(spi_t *obj);
static inline int ssp_enable(spi_t *obj); static inline int ssp_enable(spi_t *obj);
void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) { void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
{
int altfunction[4]; int altfunction[4];
// determine the SPI to use // determine the SPI to use
@ -71,7 +72,7 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel
SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso); SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel); SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
obj->spi = (MPS2_SSP_TypeDef*)pinmap_merge(spi_data, spi_cntl); obj->spi = (MPS2_SSP_TypeDef *)pinmap_merge(spi_data, spi_cntl);
if ((int)obj->spi == NC) { if ((int)obj->spi == NC) {
error("SPI pinout mapping failed"); error("SPI pinout mapping failed");
} }
@ -93,15 +94,15 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel
obj->spi->DMACR = 0; /* Disable FIFO DMA */ obj->spi->DMACR = 0; /* Disable FIFO DMA */
obj->spi->IMSC = 0; /* Mask all FIFO/IRQ interrupts */ obj->spi->IMSC = 0; /* Mask all FIFO/IRQ interrupts */
obj->spi->ICR = ((1ul << 0) | /* Clear SSPRORINTR interrupt */ obj->spi->ICR = ((1ul << 0) | /* Clear SSPRORINTR interrupt */
(1ul << 1) ); /* Clear SSPRTINTR interrupt */ (1ul << 1)); /* Clear SSPRTINTR interrupt */
obj->spi->CR0 = ((7ul << 0) | /* 8 bit data size */ obj->spi->CR0 = ((7ul << 0) | /* 8 bit data size */
(0ul << 4) | /* Motorola frame format */ (0ul << 4) | /* Motorola frame format */
(0ul << 6) | /* CPOL = 0 */ (0ul << 6) | /* CPOL = 0 */
(0ul << 7) | /* CPHA = 0 */ (0ul << 7) | /* CPHA = 0 */
(1ul << 8) ); /* Set serial clock rate */ (1ul << 8)); /* Set serial clock rate */
obj->spi->CPSR = (2ul << 0); /* set SSP clk to 6MHz (6.6MHz max) */ obj->spi->CPSR = (2ul << 0); /* set SSP clk to 6MHz (6.6MHz max) */
obj->spi->CR1 = ((1ul << 1) | /* Synchronous serial port enable */ obj->spi->CR1 = ((1ul << 1) | /* Synchronous serial port enable */
(0ul << 2) ); /* Device configured as master */ (0ul << 2)); /* Device configured as master */
break; break;
case (int)SPI_2: case (int)SPI_2:
obj->spi->CR1 = 0; obj->spi->CR1 = 0;
@ -132,21 +133,37 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel
break; break;
} }
if(mosi != NC){ altfunction[0] = 1;}else{ altfunction[0] = 0;} if (mosi != NC) {
if(miso != NC){ altfunction[1] = 1;}else{ altfunction[1] = 0;} altfunction[0] = 1;
if(sclk != NC){ altfunction[2] = 1;}else{ altfunction[2] = 0;} } else {
if(ssel != NC){ altfunction[3] = 1;}else{ altfunction[3] = 0;} altfunction[0] = 0;
}
if (miso != NC) {
altfunction[1] = 1;
} else {
altfunction[1] = 0;
}
if (sclk != NC) {
altfunction[2] = 1;
} else {
altfunction[2] = 0;
}
if (ssel != NC) {
altfunction[3] = 1;
} else {
altfunction[3] = 0;
}
// enable alt function // enable alt function
switch ((int)obj->spi) { switch ((int)obj->spi) {
case (int)SPI_2: case (int)SPI_2:
CMSDK_GPIO1->ALTFUNCSET |= (altfunction[2]<<3 | altfunction[0]<<2 | altfunction[1]<<1 | altfunction[3]); CMSDK_GPIO1->ALTFUNCSET |= (altfunction[2] << 3 | altfunction[0] << 2 | altfunction[1] << 1 | altfunction[3]);
break; break;
case (int)SPI_3: case (int)SPI_3:
CMSDK_GPIO0->ALTFUNCSET |= (altfunction[1]<<14 | altfunction[0]<<13 | altfunction[3]<<12 | altfunction[2]<<11); CMSDK_GPIO0->ALTFUNCSET |= (altfunction[1] << 14 | altfunction[0] << 13 | altfunction[3] << 12 | altfunction[2] << 11);
break; break;
case (int)SPI_4: case (int)SPI_4:
CMSDK_GPIO2->ALTFUNCSET |= (altfunction[2]<<12 | altfunction[1]<<8 | altfunction[0]<<7 | altfunction[3]<<6); CMSDK_GPIO2->ALTFUNCSET |= (altfunction[2] << 12 | altfunction[1] << 8 | altfunction[0] << 7 | altfunction[3] << 6);
break; break;
} }
@ -172,7 +189,8 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel
void spi_free(spi_t *obj) {} void spi_free(spi_t *obj) {}
void spi_format(spi_t *obj, int bits, int mode, int slave) { void spi_format(spi_t *obj, int bits, int mode, int slave)
{
ssp_disable(obj); ssp_disable(obj);
if (!(bits >= 4 && bits <= 16) || !(mode >= 0 && mode <= 3)) { if (!(bits >= 4 && bits <= 16) || !(mode >= 0 && mode <= 3)) {
error("SPI format error"); error("SPI format error");
@ -205,7 +223,8 @@ void spi_format(spi_t *obj, int bits, int mode, int slave) {
ssp_enable(obj); ssp_enable(obj);
} }
void spi_frequency(spi_t *obj, int hz) { void spi_frequency(spi_t *obj, int hz)
{
ssp_disable(obj); ssp_disable(obj);
uint32_t PCLK = SystemCoreClock; uint32_t PCLK = SystemCoreClock;
@ -233,43 +252,52 @@ void spi_frequency(spi_t *obj, int hz) {
error("Couldn't setup requested SPI frequency"); error("Couldn't setup requested SPI frequency");
} }
static inline int ssp_disable(spi_t *obj) { static inline int ssp_disable(spi_t *obj)
{
return obj->spi->CR1 &= ~(1 << 1); return obj->spi->CR1 &= ~(1 << 1);
} }
static inline int ssp_enable(spi_t *obj) { static inline int ssp_enable(spi_t *obj)
{
return obj->spi->CR1 |= SSP_CR1_SSE_Msk; return obj->spi->CR1 |= SSP_CR1_SSE_Msk;
} }
static inline int ssp_readable(spi_t *obj) { static inline int ssp_readable(spi_t *obj)
{
return obj->spi->SR & (1 << 2); return obj->spi->SR & (1 << 2);
} }
static inline int ssp_writeable(spi_t *obj) { static inline int ssp_writeable(spi_t *obj)
{
return obj->spi->SR & SSP_SR_BSY_Msk; return obj->spi->SR & SSP_SR_BSY_Msk;
} }
static inline void ssp_write(spi_t *obj, int value) { static inline void ssp_write(spi_t *obj, int value)
{
obj->spi->DR = value; obj->spi->DR = value;
while (ssp_writeable(obj)); while (ssp_writeable(obj));
} }
static inline int ssp_read(spi_t *obj) { static inline int ssp_read(spi_t *obj)
{
int read_DR = obj->spi->DR; int read_DR = obj->spi->DR;
return read_DR; return read_DR;
} }
static inline int ssp_busy(spi_t *obj) { static inline int ssp_busy(spi_t *obj)
{
return (obj->spi->SR & (1 << 4)) ? (1) : (0); return (obj->spi->SR & (1 << 4)) ? (1) : (0);
} }
int spi_master_write(spi_t *obj, int value) { int spi_master_write(spi_t *obj, int value)
{
ssp_write(obj, value); ssp_write(obj, value);
while (obj->spi->SR & SSP_SR_BSY_Msk); /* Wait for send to finish */ while (obj->spi->SR & SSP_SR_BSY_Msk); /* Wait for send to finish */
return (ssp_read(obj)); return (ssp_read(obj));
} }
int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
char *rx_buffer, int rx_length, char write_fill) { char *rx_buffer, int rx_length, char write_fill)
{
int total = (tx_length > rx_length) ? tx_length : rx_length; int total = (tx_length > rx_length) ? tx_length : rx_length;
for (int i = 0; i < total; i++) { for (int i = 0; i < total; i++) {
@ -283,19 +311,23 @@ int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
return total; return total;
} }
int spi_slave_receive(spi_t *obj) { int spi_slave_receive(spi_t *obj)
{
return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0); return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0);
} }
int spi_slave_read(spi_t *obj) { int spi_slave_read(spi_t *obj)
{
return obj->spi->DR; return obj->spi->DR;
} }
void spi_slave_write(spi_t *obj, int value) { void spi_slave_write(spi_t *obj, int value)
{
while (ssp_writeable(obj) == 0) ; while (ssp_writeable(obj) == 0) ;
obj->spi->DR = value; obj->spi->DR = value;
} }
int spi_busy(spi_t *obj) { int spi_busy(spi_t *obj)
{
return ssp_busy(obj); return ssp_busy(obj);
} }

10
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/spi_def.h
View File

@ -107,11 +107,11 @@
#define EERDSR_BP1 0x0008 // Block protect 1 #define EERDSR_BP1 0x0008 // Block protect 1
#define EERDSR_WPEN 0x0080 // Write protect enable #define EERDSR_WPEN 0x0080 // Write protect enable
/* ---------------------------------------------------------------- /* ----------------------------------------------------------------
* *
* Color LCD Support * Color LCD Support
* ================= * =================
*/ */
// Color LCD Controller Internal Register addresses // Color LCD Controller Internal Register addresses
#define LSSPCS_BASE (0x4002804C) // LSSP chip select register #define LSSPCS_BASE (0x4002804C) // LSSP chip select register

31
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/us_ticker.c
View File

@ -23,8 +23,11 @@
int us_ticker_inited = 0; int us_ticker_inited = 0;
void us_ticker_init(void) { void us_ticker_init(void)
if (us_ticker_inited) return; {
if (us_ticker_inited) {
return;
}
us_ticker_inited = 1; us_ticker_inited = 1;
US_TICKER_TIMER1->TimerControl = 0x0; // disable timer US_TICKER_TIMER1->TimerControl = 0x0; // disable timer
@ -42,23 +45,27 @@ void us_ticker_init(void) {
NVIC_EnableIRQ(US_TICKER_TIMER_IRQn); NVIC_EnableIRQ(US_TICKER_TIMER_IRQn);
} }
uint32_t us_ticker_read() { uint32_t us_ticker_read()
uint32_t return_value = 0; {
if (!us_ticker_inited) uint32_t return_value = 0;
if (!us_ticker_inited) {
us_ticker_init(); us_ticker_init();
return_value = ((~US_TICKER_TIMER2->TimerValue)/25); }
return_value = ((~US_TICKER_TIMER2->TimerValue) / 25);
return return_value; return return_value;
} }
void us_ticker_set_interrupt(timestamp_t timestamp) { void us_ticker_set_interrupt(timestamp_t timestamp)
if (!us_ticker_inited) {
if (!us_ticker_inited) {
us_ticker_init(); us_ticker_init();
}
uint32_t delta = timestamp - us_ticker_read(); uint32_t delta = timestamp - us_ticker_read();
// enable interrupt // enable interrupt
US_TICKER_TIMER1->TimerControl = 0x0; // disable timer US_TICKER_TIMER1->TimerControl = 0x0; // disable timer
US_TICKER_TIMER1->TimerControl = 0x62; // enable interrupt and set to 32 bit counter and set to periodic mode US_TICKER_TIMER1->TimerControl = 0x62; // enable interrupt and set to 32 bit counter and set to periodic mode
US_TICKER_TIMER1->TimerLoad = (delta)*25; //initialise the timer value US_TICKER_TIMER1->TimerLoad = (delta) * 25; //initialise the timer value
US_TICKER_TIMER1->TimerControl |= 0x80; //enable timer US_TICKER_TIMER1->TimerControl |= 0x80; //enable timer
} }
@ -68,14 +75,16 @@ void us_ticker_fire_interrupt(void)
} }
void us_ticker_disable_interrupt(void) { void us_ticker_disable_interrupt(void)
{
US_TICKER_TIMER1->TimerControl &= 0xDF; US_TICKER_TIMER1->TimerControl &= 0xDF;
US_TICKER_TIMER2->TimerControl &= 0xDF; US_TICKER_TIMER2->TimerControl &= 0xDF;
} }
void us_ticker_clear_interrupt(void) { void us_ticker_clear_interrupt(void)
{
US_TICKER_TIMER1->TimerIntClr = 0x1; US_TICKER_TIMER1->TimerIntClr = 0x1;
US_TICKER_TIMER2->TimerIntClr = 0x1; US_TICKER_TIMER2->TimerIntClr = 0x1;