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reformat coding styles based on coding guidelines

pull/6862/head
Qinghao Shi 2018-05-18 15:52:55 +01:00
parent 953a735129
commit aab82a78b3
48 changed files with 3675 additions and 3440 deletions
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23
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/ETH_MPS2.c
View File

@ -63,9 +63,9 @@ unsigned int smsc9220_mac_regread(unsigned char regoffset, unsigned int *data)
if (!timedout) { if (!timedout) {
error = 1; error = 1;
} } else {
else
*data = SMSC9220->MAC_CSR_DATA; *data = SMSC9220->MAC_CSR_DATA;
}
} else { } else {
*data = 0; *data = 0;
} }
@ -106,7 +106,8 @@ unsigned int smsc9220_mac_regwrite(unsigned char regoffset, unsigned int data)
unsigned int smsc9220_phy_regread(unsigned char regoffset, unsigned short *data) unsigned int smsc9220_phy_regread(unsigned char regoffset, unsigned short *data)
{ {
unsigned int val, phycmd; int error; unsigned int val, phycmd;
int error;
int timedout; int timedout;
error = 0; error = 0;
@ -132,9 +133,9 @@ unsigned int smsc9220_phy_regread(unsigned char regoffset, unsigned short *data)
if (!timedout) { if (!timedout) {
error = 1; error = 1;
} } else {
else
smsc9220_mac_regread(SMSC9220_MAC_MII_DATA, (unsigned int *)data); smsc9220_mac_regread(SMSC9220_MAC_MII_DATA, (unsigned int *)data);
}
} else { } else {
*data = 0; *data = 0;
@ -144,7 +145,8 @@ unsigned int smsc9220_phy_regread(unsigned char regoffset, unsigned short *data)
unsigned int smsc9220_phy_regwrite(unsigned char regoffset, unsigned short data) unsigned int smsc9220_phy_regwrite(unsigned char regoffset, unsigned short data)
{ {
unsigned int val, phycmd; int error; unsigned int val, phycmd;
int error;
int timedout; int timedout;
error = 0; error = 0;
@ -200,8 +202,9 @@ unsigned int smsc9220_soft_reset(void)
timedout--; timedout--;
} while (timedout && (SMSC9220->HW_CFG & 1)); } while (timedout && (SMSC9220->HW_CFG & 1));
if(!timedout) if (!timedout) {
return 1; return 1;
}
return 0; return 0;
} }
@ -209,8 +212,9 @@ unsigned int smsc9220_soft_reset(void)
void smsc9220_set_txfifo(unsigned int val) void smsc9220_set_txfifo(unsigned int val)
{ {
// 2kb minimum, 14kb maximum // 2kb minimum, 14kb maximum
if(val < 2 || val > 14) if (val < 2 || val > 14) {
return; return;
}
SMSC9220->HW_CFG = val << 16; SMSC9220->HW_CFG = val << 16;
} }
@ -228,8 +232,9 @@ unsigned int smsc9220_wait_eeprom(void)
} while (timedout && (SMSC9220->E2P_CMD & ((unsigned int) 1 << 31))); } while (timedout && (SMSC9220->E2P_CMD & ((unsigned int) 1 << 31)));
if(!timedout) if (!timedout) {
return 1; return 1;
}
return 0; return 0;
} }

21
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/fpga.c
View File

@ -34,12 +34,9 @@ void i2c_delay(unsigned int tick)
start = MPS2_FPGAIO->COUNTER; start = MPS2_FPGAIO->COUNTER;
end = start + (tick); end = start + (tick);
if(end >= start) if (end >= start) {
{
while (MPS2_FPGAIO->COUNTER >= start && MPS2_FPGAIO->COUNTER < end); while (MPS2_FPGAIO->COUNTER >= start && MPS2_FPGAIO->COUNTER < end);
} } else {
else
{
while (MPS2_FPGAIO->COUNTER >= start); while (MPS2_FPGAIO->COUNTER >= start);
while (MPS2_FPGAIO->COUNTER < end); while (MPS2_FPGAIO->COUNTER < end);
} }
@ -56,12 +53,9 @@ void Sleepms(unsigned int msec)
start = MPS2_FPGAIO->COUNTER; start = MPS2_FPGAIO->COUNTER;
end = start + (25 * msec * 1000); end = start + (25 * msec * 1000);
if(end >= start) if (end >= start) {
{
while (MPS2_FPGAIO->COUNTER >= start && MPS2_FPGAIO->COUNTER < end); while (MPS2_FPGAIO->COUNTER >= start && MPS2_FPGAIO->COUNTER < end);
} } else {
else
{
while (MPS2_FPGAIO->COUNTER >= start); while (MPS2_FPGAIO->COUNTER >= start);
while (MPS2_FPGAIO->COUNTER < end); while (MPS2_FPGAIO->COUNTER < end);
} }
@ -77,12 +71,9 @@ void Sleepus(unsigned int usec)
start = MPS2_FPGAIO->COUNTER; start = MPS2_FPGAIO->COUNTER;
end = start + (25 * usec); end = start + (25 * usec);
if(end >= start) if (end >= start) {
{
while (MPS2_FPGAIO->COUNTER >= start && MPS2_FPGAIO->COUNTER < end); while (MPS2_FPGAIO->COUNTER >= start && MPS2_FPGAIO->COUNTER < end);
} } else {
else
{
while (MPS2_FPGAIO->COUNTER >= start); while (MPS2_FPGAIO->COUNTER >= start);
while (MPS2_FPGAIO->COUNTER < end); while (MPS2_FPGAIO->COUNTER < end);
} }

27
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/CMSDK_CM0.h
View File

@ -46,8 +46,7 @@
/* ------------------------- Interrupt Number Definition ------------------------ */ /* ------------------------- Interrupt Number Definition ------------------------ */
typedef enum IRQn typedef enum IRQn {
{
/****** Cortex-M0 Processor Exceptions Numbers ***************************************************/ /****** Cortex-M0 Processor Exceptions Numbers ***************************************************/
/* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M0 device */ /* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M0 device */
@ -128,8 +127,7 @@ typedef enum IRQn
#endif #endif
/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
typedef struct typedef struct {
{
__IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */ __IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */
__IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */ __IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */
__IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */ __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */
@ -196,8 +194,7 @@ typedef struct
/*----------------------------- Timer (TIMER) -------------------------------*/ /*----------------------------- Timer (TIMER) -------------------------------*/
typedef struct typedef struct {
{
__IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */ __IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */
__IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */ __IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */
__IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */ __IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */
@ -236,8 +233,7 @@ typedef struct
/*------------- Timer (TIM) --------------------------------------------------*/ /*------------- Timer (TIM) --------------------------------------------------*/
typedef struct typedef struct {
{
__IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */ __IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
__I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */ __I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
__IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */ __IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
@ -331,8 +327,7 @@ typedef struct
#define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /* CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */ #define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /* CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */
typedef struct typedef struct {
{
__IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */ __IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */
__I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */ __I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */
__IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */ __IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */
@ -380,8 +375,7 @@ typedef struct
/*-------------------- General Purpose Input Output (GPIO) -------------------*/ /*-------------------- General Purpose Input Output (GPIO) -------------------*/
typedef struct typedef struct {
{
__IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */ __IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */
__IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */ __IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */
uint32_t RESERVED0[2]; uint32_t RESERVED0[2];
@ -454,8 +448,7 @@ typedef struct
/*------------- System Control (SYSCON) --------------------------------------*/ /*------------- System Control (SYSCON) --------------------------------------*/
typedef struct typedef struct {
{
__IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */ __IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */
__IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */ __IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */
__IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */ __IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */
@ -495,8 +488,7 @@ typedef struct
/*------------- PL230 uDMA (PL230) --------------------------------------*/ /*------------- PL230 uDMA (PL230) --------------------------------------*/
typedef struct typedef struct {
{
__I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */ __I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */
__O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */ __O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */
__IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */ __IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */
@ -591,8 +583,7 @@ typedef struct
/*------------------- Watchdog ----------------------------------------------*/ /*------------------- Watchdog ----------------------------------------------*/
typedef struct typedef struct {
{
__IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */ __IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */
__I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */ __I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */

6
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/cmsis_nvic.c
View File

@ -36,7 +36,8 @@
#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Location of vectors in RAM #define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Location of vectors in RAM
#define NVIC_FLASH_VECTOR_ADDRESS (0x00000000) // Initial vector position in flash #define NVIC_FLASH_VECTOR_ADDRESS (0x00000000) // Initial vector position in flash
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
// int i; // int i;
// Space for dynamic vectors, initialised to allocate in R/W // Space for dynamic vectors, initialised to allocate in R/W
static volatile uint32_t *vectors = (uint32_t *)NVIC_FLASH_VECTOR_ADDRESS; static volatile uint32_t *vectors = (uint32_t *)NVIC_FLASH_VECTOR_ADDRESS;
@ -45,7 +46,8 @@ void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
vectors[IRQn + 16] = vector; vectors[IRQn + 16] = vector;
} }
uint32_t NVIC_GetVector(IRQn_Type IRQn) { uint32_t NVIC_GetVector(IRQn_Type IRQn)
{
// We can always read vectors at 0x0, as the addresses are remapped // We can always read vectors at 0x0, as the addresses are remapped
uint32_t *vectors = (uint32_t *)NVIC_FLASH_VECTOR_ADDRESS; uint32_t *vectors = (uint32_t *)NVIC_FLASH_VECTOR_ADDRESS;

27
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/CMSDK_CM0plus.h
View File

@ -46,8 +46,7 @@
/* ------------------------- Interrupt Number Definition ------------------------ */ /* ------------------------- Interrupt Number Definition ------------------------ */
typedef enum IRQn typedef enum IRQn {
{
/****** Cortex-M0 Processor Exceptions Numbers ***************************************************/ /****** Cortex-M0 Processor Exceptions Numbers ***************************************************/
/* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M0 device */ /* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M0 device */
@ -129,8 +128,7 @@ typedef enum IRQn
#endif #endif
/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
typedef struct typedef struct {
{
__IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */ __IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */
__IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */ __IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */
__IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */ __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */
@ -197,8 +195,7 @@ typedef struct
/*----------------------------- Timer (TIMER) -------------------------------*/ /*----------------------------- Timer (TIMER) -------------------------------*/
typedef struct typedef struct {
{
__IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */ __IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */
__IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */ __IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */
__IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */ __IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */
@ -237,8 +234,7 @@ typedef struct
/*------------- Timer (TIM) --------------------------------------------------*/ /*------------- Timer (TIM) --------------------------------------------------*/
typedef struct typedef struct {
{
__IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */ __IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
__I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */ __I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
__IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */ __IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
@ -332,8 +328,7 @@ typedef struct
#define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /* CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */ #define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /* CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */
typedef struct typedef struct {
{
__IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */ __IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */
__I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */ __I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */
__IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */ __IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */
@ -381,8 +376,7 @@ typedef struct
/*-------------------- General Purpose Input Output (GPIO) -------------------*/ /*-------------------- General Purpose Input Output (GPIO) -------------------*/
typedef struct typedef struct {
{
__IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */ __IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */
__IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */ __IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */
uint32_t RESERVED0[2]; uint32_t RESERVED0[2];
@ -455,8 +449,7 @@ typedef struct
/*------------- System Control (SYSCON) --------------------------------------*/ /*------------- System Control (SYSCON) --------------------------------------*/
typedef struct typedef struct {
{
__IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */ __IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */
__IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */ __IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */
__IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */ __IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */
@ -496,8 +489,7 @@ typedef struct
/*------------- PL230 uDMA (PL230) --------------------------------------*/ /*------------- PL230 uDMA (PL230) --------------------------------------*/
typedef struct typedef struct {
{
__I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */ __I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */
__O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */ __O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */
__IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */ __IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */
@ -592,8 +584,7 @@ typedef struct
/*------------------- Watchdog ----------------------------------------------*/ /*------------------- Watchdog ----------------------------------------------*/
typedef struct typedef struct {
{
__IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */ __IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */
__I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */ __I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */

18
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/SMM_MPS2.h
View File

@ -46,8 +46,7 @@
/* FPGA System Register declaration */ /* FPGA System Register declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct typedef struct {
{
__IO uint32_t LED; // Offset: 0x000 (R/W) LED connections __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections
// [31:2] : Reserved // [31:2] : Reserved
// [1:0] : LEDs // [1:0] : LEDs
@ -107,8 +106,7 @@ typedef struct
/* SCC Register declaration */ /* SCC Register declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct // typedef struct { //
{
__IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT __IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT
// [31:1] : Reserved // [31:1] : Reserved
// [0] 1 : REMAP BlockRam to ZBT // [0] 1 : REMAP BlockRam to ZBT
@ -166,8 +164,7 @@ typedef struct //
/* SSP Peripheral declaration */ /* SSP Peripheral declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf typedef struct { // Document DDI0194G_ssp_pl022_r1p3_trm.pdf
{
__IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0 __IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0
// [31:16] : Reserved // [31:16] : Reserved
// [15:8] : Serial clock rate // [15:8] : Serial clock rate
@ -314,8 +311,7 @@ typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf
/* Audio and Touch Screen (I2C) Peripheral declaration */ /* Audio and Touch Screen (I2C) Peripheral declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct typedef struct {
{
union { union {
__O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W) __O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W)
__I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ ) __I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ )
@ -331,8 +327,7 @@ typedef struct
/* Audio I2S Peripheral declaration */ /* Audio I2S Peripheral declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct typedef struct {
{
/*!< Offset: 0x000 CONTROL Register (R/W) */ /*!< Offset: 0x000 CONTROL Register (R/W) */
__IO uint32_t CONTROL; // <h> CONTROL </h> __IO uint32_t CONTROL; // <h> CONTROL </h>
// <o.0> TX Enable // <o.0> TX Enable
@ -486,8 +481,7 @@ typedef struct
/* SMSC9220 Register Definitions */ /* SMSC9220 Register Definitions */
/******************************************************************************/ /******************************************************************************/
typedef struct // SMSC LAN9220 typedef struct { // SMSC LAN9220
{
__I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0) __I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0)
uint32_t RESERVED1[0x7]; uint32_t RESERVED1[0x7];
__O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20) __O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20)

27
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/CMSDK_CM3.h
View File

@ -46,8 +46,7 @@
/* ------------------------- Interrupt Number Definition ------------------------ */ /* ------------------------- Interrupt Number Definition ------------------------ */
typedef enum IRQn typedef enum IRQn {
{
/* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */ /* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /* 3 HardFault Interrupt */ HardFault_IRQn = -13, /* 3 HardFault Interrupt */
@ -130,8 +129,7 @@ typedef enum IRQn
#endif #endif
/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
typedef struct typedef struct {
{
__IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */ __IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */
__IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */ __IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */
__IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */ __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */
@ -198,8 +196,7 @@ typedef struct
/*----------------------------- Timer (TIMER) -------------------------------*/ /*----------------------------- Timer (TIMER) -------------------------------*/
typedef struct typedef struct {
{
__IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */ __IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */
__IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */ __IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */
__IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */ __IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */
@ -238,8 +235,7 @@ typedef struct
/*------------- Timer (TIM) --------------------------------------------------*/ /*------------- Timer (TIM) --------------------------------------------------*/
typedef struct typedef struct {
{
__IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */ __IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
__I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */ __I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
__IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */ __IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
@ -333,8 +329,7 @@ typedef struct
#define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /* CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */ #define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /* CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */
typedef struct typedef struct {
{
__IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */ __IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */
__I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */ __I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */
__IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */ __IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */
@ -382,8 +377,7 @@ typedef struct
/*-------------------- General Purpose Input Output (GPIO) -------------------*/ /*-------------------- General Purpose Input Output (GPIO) -------------------*/
typedef struct typedef struct {
{
__IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */ __IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */
__IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */ __IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */
uint32_t RESERVED0[2]; uint32_t RESERVED0[2];
@ -456,8 +450,7 @@ typedef struct
/*------------- System Control (SYSCON) --------------------------------------*/ /*------------- System Control (SYSCON) --------------------------------------*/
typedef struct typedef struct {
{
__IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */ __IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */
__IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */ __IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */
__IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */ __IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */
@ -497,8 +490,7 @@ typedef struct
/*------------- PL230 uDMA (PL230) --------------------------------------*/ /*------------- PL230 uDMA (PL230) --------------------------------------*/
typedef struct typedef struct {
{
__I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */ __I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */
__O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */ __O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */
__IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */ __IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */
@ -593,8 +585,7 @@ typedef struct
/*------------------- Watchdog ----------------------------------------------*/ /*------------------- Watchdog ----------------------------------------------*/
typedef struct typedef struct {
{
__IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */ __IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */
__I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */ __I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */

18
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/SMM_MPS2.h
View File

@ -46,8 +46,7 @@
/* FPGA System Register declaration */ /* FPGA System Register declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct typedef struct {
{
__IO uint32_t LED; // Offset: 0x000 (R/W) LED connections __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections
// [31:2] : Reserved // [31:2] : Reserved
// [1:0] : LEDs // [1:0] : LEDs
@ -107,8 +106,7 @@ typedef struct
/* SCC Register declaration */ /* SCC Register declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct // typedef struct { //
{
__IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT __IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT
// [31:1] : Reserved // [31:1] : Reserved
// [0] 1 : REMAP BlockRam to ZBT // [0] 1 : REMAP BlockRam to ZBT
@ -166,8 +164,7 @@ typedef struct //
/* SSP Peripheral declaration */ /* SSP Peripheral declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf typedef struct { // Document DDI0194G_ssp_pl022_r1p3_trm.pdf
{
__IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0 __IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0
// [31:16] : Reserved // [31:16] : Reserved
// [15:8] : Serial clock rate // [15:8] : Serial clock rate
@ -314,8 +311,7 @@ typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf
/* Audio and Touch Screen (I2C) Peripheral declaration */ /* Audio and Touch Screen (I2C) Peripheral declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct typedef struct {
{
union { union {
__O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W) __O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W)
__I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ ) __I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ )
@ -331,8 +327,7 @@ typedef struct
/* Audio I2S Peripheral declaration */ /* Audio I2S Peripheral declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct typedef struct {
{
/*!< Offset: 0x000 CONTROL Register (R/W) */ /*!< Offset: 0x000 CONTROL Register (R/W) */
__IO uint32_t CONTROL; // <h> CONTROL </h> __IO uint32_t CONTROL; // <h> CONTROL </h>
// <o.0> TX Enable // <o.0> TX Enable
@ -486,8 +481,7 @@ typedef struct
/* SMSC9220 Register Definitions */ /* SMSC9220 Register Definitions */
/******************************************************************************/ /******************************************************************************/
typedef struct // SMSC LAN9220 typedef struct { // SMSC LAN9220
{
__I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0) __I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0)
uint32_t RESERVED1[0x7]; uint32_t RESERVED1[0x7];
__O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20) __O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20)

33
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/CMSDK_CM4.h
View File

@ -46,8 +46,7 @@
/* ------------------------- Interrupt Number Definition ------------------------ */ /* ------------------------- Interrupt Number Definition ------------------------ */
typedef enum IRQn typedef enum IRQn {
{
/* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */ /* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /* 3 HardFault Interrupt */ HardFault_IRQn = -13, /* 3 HardFault Interrupt */
@ -132,8 +131,7 @@ typedef enum IRQn
memory mapped structure for CMSDK_UART memory mapped structure for CMSDK_UART
@{ @{
*/ */
typedef struct typedef struct {
{
__IO uint32_t DATA; /*!< Offset: 0x000 Data Register (R/W) */ __IO uint32_t DATA; /*!< Offset: 0x000 Data Register (R/W) */
__IO uint32_t STATE; /*!< Offset: 0x004 Status Register (R/W) */ __IO uint32_t STATE; /*!< Offset: 0x004 Status Register (R/W) */
__IO uint32_t CTRL; /*!< Offset: 0x008 Control Register (R/W) */ __IO uint32_t CTRL; /*!< Offset: 0x008 Control Register (R/W) */
@ -205,8 +203,7 @@ typedef struct
/** @addtogroup CMSDK_TIMER CMSDK Timer /** @addtogroup CMSDK_TIMER CMSDK Timer
@{ @{
*/ */
typedef struct typedef struct {
{
__IO uint32_t CTRL; /*!< Offset: 0x000 Control Register (R/W) */ __IO uint32_t CTRL; /*!< Offset: 0x000 Control Register (R/W) */
__IO uint32_t VALUE; /*!< Offset: 0x004 Current Value Register (R/W) */ __IO uint32_t VALUE; /*!< Offset: 0x004 Current Value Register (R/W) */
__IO uint32_t RELOAD; /*!< Offset: 0x008 Reload Value Register (R/W) */ __IO uint32_t RELOAD; /*!< Offset: 0x008 Reload Value Register (R/W) */
@ -253,8 +250,7 @@ typedef struct
@{ @{
*/ */
typedef struct typedef struct {
{
__IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */ __IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
__I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */ __I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
__IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */ __IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
@ -381,8 +377,7 @@ typedef struct
#define CMSDK_DUALTIMER2_BGLOAD_Pos 0 /*!< CMSDK_DUALTIMER2 BGLOAD: Background Load Position */ #define CMSDK_DUALTIMER2_BGLOAD_Pos 0 /*!< CMSDK_DUALTIMER2 BGLOAD: Background Load Position */
#define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /*!< CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */ #define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /*!< CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */
typedef struct typedef struct {
{
__IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */ __IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */
__I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */ __I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */
__IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */ __IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */
@ -452,8 +447,7 @@ typedef struct
/** @addtogroup CMSDK_GPIO CMSDK GPIO /** @addtogroup CMSDK_GPIO CMSDK GPIO
@{ @{
*/ */
typedef struct typedef struct {
{
__IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */ __IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */
__IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */ __IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */
uint32_t RESERVED0[2]; uint32_t RESERVED0[2];
@ -531,8 +525,7 @@ typedef struct
/** @addtogroup CMSDK_SYSCON CMSDK System Control /** @addtogroup CMSDK_SYSCON CMSDK System Control
@{ @{
*/ */
typedef struct typedef struct {
{
__IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */ __IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */
__IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */ __IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */
__IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */ __IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */
@ -576,8 +569,7 @@ typedef struct
/** @addtogroup CMSDK_PL230 CMSDK uDMA controller /** @addtogroup CMSDK_PL230 CMSDK uDMA controller
@{ @{
*/ */
typedef struct typedef struct {
{
__I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */ __I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */
__O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */ __O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */
__IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */ __IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */
@ -679,8 +671,7 @@ typedef struct
@{ @{
*/ */
typedef struct typedef struct {
{
__IO uint32_t UARTDR; // <h> Data __IO uint32_t UARTDR; // <h> Data
// <o.11> OE: Overrun error <r> // <o.11> OE: Overrun error <r>
// <o.10> BE: Break error <r> // <o.10> BE: Break error <r>
@ -1113,8 +1104,7 @@ typedef struct
/** @addtogroup CMSDK_Watchdog CMSDK Watchdog /** @addtogroup CMSDK_Watchdog CMSDK Watchdog
@{ @{
*/ */
typedef struct typedef struct {
{
__IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */ __IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */
__I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */ __I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */
@ -1168,8 +1158,7 @@ typedef struct
/** @addtogroup CMSDK_PL061 CMSDK APB GPIO /** @addtogroup CMSDK_PL061 CMSDK APB GPIO
@{ @{
*/ */
typedef struct typedef struct {
{
__IO uint32_t DATA[256]; __IO uint32_t DATA[256];
__IO uint32_t DIR; __IO uint32_t DIR;

18
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/SMM_MPS2.h
View File

@ -46,8 +46,7 @@
/* FPGA System Register declaration */ /* FPGA System Register declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct typedef struct {
{
__IO uint32_t LED; // Offset: 0x000 (R/W) LED connections __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections
// [31:2] : Reserved // [31:2] : Reserved
// [1:0] : LEDs // [1:0] : LEDs
@ -107,8 +106,7 @@ typedef struct
/* SCC Register declaration */ /* SCC Register declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct // typedef struct { //
{
__IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT __IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT
// [31:1] : Reserved // [31:1] : Reserved
// [0] 1 : REMAP BlockRam to ZBT // [0] 1 : REMAP BlockRam to ZBT
@ -166,8 +164,7 @@ typedef struct //
/* SSP Peripheral declaration */ /* SSP Peripheral declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf typedef struct { // Document DDI0194G_ssp_pl022_r1p3_trm.pdf
{
__IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0 __IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0
// [31:16] : Reserved // [31:16] : Reserved
// [15:8] : Serial clock rate // [15:8] : Serial clock rate
@ -314,8 +311,7 @@ typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf
/* Audio and Touch Screen (I2C) Peripheral declaration */ /* Audio and Touch Screen (I2C) Peripheral declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct typedef struct {
{
union { union {
__O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W) __O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W)
__I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ ) __I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ )
@ -331,8 +327,7 @@ typedef struct
/* Audio I2S Peripheral declaration */ /* Audio I2S Peripheral declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct typedef struct {
{
/*!< Offset: 0x000 CONTROL Register (R/W) */ /*!< Offset: 0x000 CONTROL Register (R/W) */
__IO uint32_t CONTROL; // <h> CONTROL </h> __IO uint32_t CONTROL; // <h> CONTROL </h>
// <o.0> TX Enable // <o.0> TX Enable
@ -486,8 +481,7 @@ typedef struct
/* SMSC9220 Register Definitions */ /* SMSC9220 Register Definitions */
/******************************************************************************/ /******************************************************************************/
typedef struct // SMSC LAN9220 typedef struct { // SMSC LAN9220
{
__I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0) __I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0)
uint32_t RESERVED1[0x7]; uint32_t RESERVED1[0x7];
__O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20) __O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20)

27
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/CMSDK_CM7.h
View File

@ -46,8 +46,7 @@ extern "C" {
/* ------------------------- Interrupt Number Definition ------------------------ */ /* ------------------------- Interrupt Number Definition ------------------------ */
typedef enum IRQn typedef enum IRQn {
{
/* ------------------- Cortex-M7 Processor Exceptions Numbers ------------------- */ /* ------------------- Cortex-M7 Processor Exceptions Numbers ------------------- */
NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /* 3 HardFault Interrupt */ HardFault_IRQn = -13, /* 3 HardFault Interrupt */
@ -136,8 +135,7 @@ typedef enum IRQn
#endif #endif
/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
typedef struct typedef struct {
{
__IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */ __IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */
__IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */ __IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */
__IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */ __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */
@ -204,8 +202,7 @@ typedef struct
/*----------------------------- Timer (TIMER) -------------------------------*/ /*----------------------------- Timer (TIMER) -------------------------------*/
typedef struct typedef struct {
{
__IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */ __IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */
__IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */ __IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */
__IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */ __IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */
@ -244,8 +241,7 @@ typedef struct
/*------------- Timer (TIM) --------------------------------------------------*/ /*------------- Timer (TIM) --------------------------------------------------*/
typedef struct typedef struct {
{
__IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */ __IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
__I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */ __I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
__IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */ __IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
@ -339,8 +335,7 @@ typedef struct
#define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /* CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */ #define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /* CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */
typedef struct typedef struct {
{
__IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */ __IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */
__I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */ __I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */
__IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */ __IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */
@ -388,8 +383,7 @@ typedef struct
/*-------------------- General Purpose Input Output (GPIO) -------------------*/ /*-------------------- General Purpose Input Output (GPIO) -------------------*/
typedef struct typedef struct {
{
__IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */ __IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */
__IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */ __IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */
uint32_t RESERVED0[2]; uint32_t RESERVED0[2];
@ -462,8 +456,7 @@ typedef struct
/*------------- System Control (SYSCON) --------------------------------------*/ /*------------- System Control (SYSCON) --------------------------------------*/
typedef struct typedef struct {
{
__IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */ __IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */
__IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */ __IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */
__IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */ __IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */
@ -503,8 +496,7 @@ typedef struct
/*------------- PL230 uDMA (PL230) --------------------------------------*/ /*------------- PL230 uDMA (PL230) --------------------------------------*/
typedef struct typedef struct {
{
__I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */ __I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */
__O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */ __O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */
__IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */ __IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */
@ -599,8 +591,7 @@ typedef struct
/*------------------- Watchdog ----------------------------------------------*/ /*------------------- Watchdog ----------------------------------------------*/
typedef struct typedef struct {
{
__IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */ __IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */
__I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */ __I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */

18
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/SMM_MPS2.h
View File

@ -46,8 +46,7 @@
/* FPGA System Register declaration */ /* FPGA System Register declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct typedef struct {
{
__IO uint32_t LED; // Offset: 0x000 (R/W) LED connections __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections
// [31:2] : Reserved // [31:2] : Reserved
// [1:0] : LEDs // [1:0] : LEDs
@ -107,8 +106,7 @@ typedef struct
/* SCC Register declaration */ /* SCC Register declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct // typedef struct { //
{
__IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT __IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT
// [31:1] : Reserved // [31:1] : Reserved
// [0] 1 : REMAP BlockRam to ZBT // [0] 1 : REMAP BlockRam to ZBT
@ -166,8 +164,7 @@ typedef struct //
/* SSP Peripheral declaration */ /* SSP Peripheral declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf typedef struct { // Document DDI0194G_ssp_pl022_r1p3_trm.pdf
{
__IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0 __IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0
// [31:16] : Reserved // [31:16] : Reserved
// [15:8] : Serial clock rate // [15:8] : Serial clock rate
@ -314,8 +311,7 @@ typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf
/* Audio and Touch Screen (I2C) Peripheral declaration */ /* Audio and Touch Screen (I2C) Peripheral declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct typedef struct {
{
union { union {
__O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W) __O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W)
__I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ ) __I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ )
@ -331,8 +327,7 @@ typedef struct
/* Audio I2S Peripheral declaration */ /* Audio I2S Peripheral declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct typedef struct {
{
/*!< Offset: 0x000 CONTROL Register (R/W) */ /*!< Offset: 0x000 CONTROL Register (R/W) */
__IO uint32_t CONTROL; // <h> CONTROL </h> __IO uint32_t CONTROL; // <h> CONTROL </h>
// <o.0> TX Enable // <o.0> TX Enable
@ -486,8 +481,7 @@ typedef struct
/* SMSC9220 Register Definitions */ /* SMSC9220 Register Definitions */
/******************************************************************************/ /******************************************************************************/
typedef struct // SMSC LAN9220 typedef struct { // SMSC LAN9220
{
__I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0) __I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0)
uint32_t RESERVED1[0x7]; uint32_t RESERVED1[0x7];
__O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20) __O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20)

12
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/analogin_api.c
View File

@ -60,7 +60,8 @@ static const PinMap PinMap_SPI_SSEL[] = {
#define ADC_RANGE ADC_12BIT_RANGE #define ADC_RANGE ADC_12BIT_RANGE
int analog_spi_inited = 0; int analog_spi_inited = 0;
void analogin_init(analogin_t *obj, PinName pin) { void analogin_init(analogin_t *obj, PinName pin)
{
obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
MBED_ASSERT(obj->adc != (ADCName)NC); MBED_ASSERT(obj->adc != (ADCName)NC);
@ -94,17 +95,20 @@ void analogin_init(analogin_t *obj, PinName pin) {
pinmap_pinout(pin, PinMap_ADC); pinmap_pinout(pin, PinMap_ADC);
} }
static inline uint32_t adc_read(analogin_t *obj) { static inline uint32_t adc_read(analogin_t *obj)
{
return 0; return 0;
} }
float analogin_read(analogin_t *obj) { float analogin_read(analogin_t *obj)
{
uint32_t value = adc_read(obj); uint32_t value = adc_read(obj);
return 0; return 0;
} }
uint16_t analogin_read_u16(analogin_t *obj) { uint16_t analogin_read_u16(analogin_t *obj)
{
return 0; return 0;
} }

6
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/ethernet_api.c
View File

@ -118,7 +118,8 @@ int ethernet_init()
/*---------------------------------------------------------------------------- /*----------------------------------------------------------------------------
Ethernet Device Uninitialize Ethernet Device Uninitialize
*----------------------------------------------------------------------------*/ *----------------------------------------------------------------------------*/
void ethernet_free() { void ethernet_free()
{
} }
int ethernet_write(const char *data, int size) int ethernet_write(const char *data, int size)
@ -148,7 +149,8 @@ int ethernet_read(char *data, int dlen)
return 0; return 0;
} }
void ethernet_address(char *mac) { void ethernet_address(char *mac)
{
mbed_mac_address(mac); mbed_mac_address(mac);
} }

33
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/gpio_api.c
View File

@ -17,16 +17,19 @@
#include "pinmap.h" #include "pinmap.h"
// function to enable the GPIO pin // function to enable the GPIO pin
uint32_t gpio_set(PinName pin) { uint32_t gpio_set(PinName pin)
{
return (1); return (1);
} }
//function to initialise the gpio pin //function to initialise the gpio pin
// this links the board control bits for each pin // this links the board control bits for each pin
// with the object created for the pin // with the object created for the pin
void gpio_init(gpio_t *obj, PinName pin) { void gpio_init(gpio_t *obj, PinName pin)
if(pin == NC){ return;} {
else { if (pin == NC) {
return;
} else {
int pin_value = 0; int pin_value = 0;
obj->pin = pin; obj->pin = pin;
if (pin <= 15) { if (pin <= 15) {
@ -116,21 +119,29 @@ void gpio_init(gpio_t *obj, PinName pin) {
} }
} }
void gpio_mode(gpio_t *obj, PinMode mode) { void gpio_mode(gpio_t *obj, PinMode mode)
{
pin_mode(obj->pin, mode); pin_mode(obj->pin, mode);
} }
void gpio_dir(gpio_t *obj, PinDirection direction) { void gpio_dir(gpio_t *obj, PinDirection direction)
if(obj->pin >= 0 && obj->pin <= 51)
{ {
if (obj->pin >= 0 && obj->pin <= 51) {
switch (direction) { switch (direction) {
case PIN_INPUT : *obj->reg_dirclr = obj->mask; break; case PIN_INPUT :
case PIN_OUTPUT: *obj->reg_dir |= obj->mask; break; *obj->reg_dirclr = obj->mask;
break;
case PIN_OUTPUT:
*obj->reg_dir |= obj->mask;
break;
}
} else {
return;
} }
} else {return;}
} }
int gpio_is_connected(const gpio_t *obj){ int gpio_is_connected(const gpio_t *obj)
{
if (obj->pin != (PinName)NC) { if (obj->pin != (PinName)NC) {
return 1; return 1;
} else { } else {

347
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/gpio_irq_api.c
View File

@ -26,14 +26,17 @@
static uint32_t channel_ids[CHANNEL_NUM] = {0}; static uint32_t channel_ids[CHANNEL_NUM] = {0};
static gpio_irq_handler irq_handler; static gpio_irq_handler irq_handler;
static inline void handle_interrupt_in(uint32_t channel) { static inline void handle_interrupt_in(uint32_t channel)
{
uint32_t ch_bit = (1 << channel); uint32_t ch_bit = (1 << channel);
// Return immediately if: // Return immediately if:
// * The interrupt was already served // * The interrupt was already served
// * There is no user handler // * There is no user handler
// * It is a level interrupt, not an edge interrupt // * It is a level interrupt, not an edge interrupt
if (ch_bit < 16) { if (ch_bit < 16) {
if ( ((CMSDK_GPIO_0->INTSTATUS) == 0) || (channel_ids[channel] == 0) || ((CMSDK_GPIO_0->INTTYPESET) == 0) ) return; if (((CMSDK_GPIO_0->INTSTATUS) == 0) || (channel_ids[channel] == 0) || ((CMSDK_GPIO_0->INTTYPESET) == 0)) {
return;
}
if ((CMSDK_GPIO_0->INTTYPESET & ch_bit) && (CMSDK_GPIO_0->INTPOLSET & ch_bit)) { if ((CMSDK_GPIO_0->INTTYPESET & ch_bit) && (CMSDK_GPIO_0->INTPOLSET & ch_bit)) {
irq_handler(channel_ids[channel], IRQ_RISE); irq_handler(channel_ids[channel], IRQ_RISE);
@ -46,7 +49,9 @@ static inline void handle_interrupt_in(uint32_t channel) {
} }
if (ch_bit >= 16) { if (ch_bit >= 16) {
if ( ((CMSDK_GPIO_1->INTSTATUS) == 0) || (channel_ids[channel] == 0) || ((CMSDK_GPIO_1->INTTYPESET) == 0) ) return; if (((CMSDK_GPIO_1->INTSTATUS) == 0) || (channel_ids[channel] == 0) || ((CMSDK_GPIO_1->INTTYPESET) == 0)) {
return;
}
if ((CMSDK_GPIO_1->INTTYPESET & ch_bit) && (CMSDK_GPIO_1->INTPOLSET & ch_bit)) { if ((CMSDK_GPIO_1->INTTYPESET & ch_bit) && (CMSDK_GPIO_1->INTPOLSET & ch_bit)) {
irq_handler(channel_ids[channel], IRQ_RISE); irq_handler(channel_ids[channel], IRQ_RISE);
@ -59,43 +64,141 @@ static inline void handle_interrupt_in(uint32_t channel) {
} }
} }
void gpio0_irq0(void) {handle_interrupt_in(0);} void gpio0_irq0(void)
void gpio0_irq1(void) {handle_interrupt_in(1);} {
void gpio0_irq2(void) {handle_interrupt_in(2);} handle_interrupt_in(0);
void gpio0_irq3(void) {handle_interrupt_in(3);} }
void gpio0_irq4(void) {handle_interrupt_in(4);} void gpio0_irq1(void)
void gpio0_irq5(void) {handle_interrupt_in(5);} {
void gpio0_irq6(void) {handle_interrupt_in(6);} handle_interrupt_in(1);
void gpio0_irq7(void) {handle_interrupt_in(7);} }
void gpio0_irq8(void) {handle_interrupt_in(8);} void gpio0_irq2(void)
void gpio0_irq9(void) {handle_interrupt_in(9);} {
void gpio0_irq10(void) {handle_interrupt_in(10);} handle_interrupt_in(2);
void gpio0_irq11(void) {handle_interrupt_in(11);} }
void gpio0_irq12(void) {handle_interrupt_in(12);} void gpio0_irq3(void)
void gpio0_irq13(void) {handle_interrupt_in(13);} {
void gpio0_irq14(void) {handle_interrupt_in(14);} handle_interrupt_in(3);
void gpio0_irq15(void) {handle_interrupt_in(15);} }
void gpio1_irq0(void) {handle_interrupt_in(16);} void gpio0_irq4(void)
void gpio1_irq1(void) {handle_interrupt_in(17);} {
void gpio1_irq2(void) {handle_interrupt_in(18);} handle_interrupt_in(4);
void gpio1_irq3(void) {handle_interrupt_in(19);} }
void gpio1_irq4(void) {handle_interrupt_in(20);} void gpio0_irq5(void)
void gpio1_irq5(void) {handle_interrupt_in(21);} {
void gpio1_irq6(void) {handle_interrupt_in(22);} handle_interrupt_in(5);
void gpio1_irq7(void) {handle_interrupt_in(23);} }
void gpio1_irq8(void) {handle_interrupt_in(24);} void gpio0_irq6(void)
void gpio1_irq9(void) {handle_interrupt_in(25);} {
void gpio1_irq10(void) {handle_interrupt_in(26);} handle_interrupt_in(6);
void gpio1_irq11(void) {handle_interrupt_in(27);} }
void gpio1_irq12(void) {handle_interrupt_in(28);} void gpio0_irq7(void)
void gpio1_irq13(void) {handle_interrupt_in(29);} {
void gpio1_irq14(void) {handle_interrupt_in(30);} handle_interrupt_in(7);
void gpio1_irq15(void) {handle_interrupt_in(31);} }
void gpio0_irq8(void)
{
handle_interrupt_in(8);
}
void gpio0_irq9(void)
{
handle_interrupt_in(9);
}
void gpio0_irq10(void)
{
handle_interrupt_in(10);
}
void gpio0_irq11(void)
{
handle_interrupt_in(11);
}
void gpio0_irq12(void)
{
handle_interrupt_in(12);
}
void gpio0_irq13(void)
{
handle_interrupt_in(13);
}
void gpio0_irq14(void)
{
handle_interrupt_in(14);
}
void gpio0_irq15(void)
{
handle_interrupt_in(15);
}
void gpio1_irq0(void)
{
handle_interrupt_in(16);
}
void gpio1_irq1(void)
{
handle_interrupt_in(17);
}
void gpio1_irq2(void)
{
handle_interrupt_in(18);
}
void gpio1_irq3(void)
{
handle_interrupt_in(19);
}
void gpio1_irq4(void)
{
handle_interrupt_in(20);
}
void gpio1_irq5(void)
{
handle_interrupt_in(21);
}
void gpio1_irq6(void)
{
handle_interrupt_in(22);
}
void gpio1_irq7(void)
{
handle_interrupt_in(23);
}
void gpio1_irq8(void)
{
handle_interrupt_in(24);
}
void gpio1_irq9(void)
{
handle_interrupt_in(25);
}
void gpio1_irq10(void)
{
handle_interrupt_in(26);
}
void gpio1_irq11(void)
{
handle_interrupt_in(27);
}
void gpio1_irq12(void)
{
handle_interrupt_in(28);
}
void gpio1_irq13(void)
{
handle_interrupt_in(29);
}
void gpio1_irq14(void)
{
handle_interrupt_in(30);
}
void gpio1_irq15(void)
{
handle_interrupt_in(31);
}
int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) { int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
if (pin == NC) {return -1;} {
else { if (pin == NC) {
return -1;
} else {
irq_handler = handler; irq_handler = handler;
@ -109,57 +212,121 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32
break; break;
} }
} }
if (!found_free_channel) return -1; if (!found_free_channel) {
return -1;
}
/* To select a pin for any of the eight pin interrupts, write the pin number /* To select a pin for any of the eight pin interrupts, write the pin number
* as 0 to 23 for pins PIO0_0 to PIO0_23 and 24 to 55. * as 0 to 23 for pins PIO0_0 to PIO0_23 and 24 to 55.
* @see: mbed_capi/PinNames.h * @see: mbed_capi/PinNames.h
*/ */
if (pin <16) if (pin < 16) {
{
CMSDK_GPIO_0->INTENSET |= (0x1 << pin); CMSDK_GPIO_0->INTENSET |= (0x1 << pin);
} }
if (pin >= 16) if (pin >= 16) {
{
CMSDK_GPIO_1->INTENSET |= (0x1 << pin); CMSDK_GPIO_1->INTENSET |= (0x1 << pin);
} }
void (*channels_irq)(void) = NULL; void (*channels_irq)(void) = NULL;
switch (obj->ch) { switch (obj->ch) {
case 0: channels_irq = &gpio0_irq0; break; case 0:
case 1: channels_irq = &gpio0_irq1; break; channels_irq = &gpio0_irq0;
case 2: channels_irq = &gpio0_irq2; break; break;
case 3: channels_irq = &gpio0_irq3; break; case 1:
case 4: channels_irq = &gpio0_irq4; break; channels_irq = &gpio0_irq1;
case 5: channels_irq = &gpio0_irq5; break; break;
case 6: channels_irq = &gpio0_irq6; break; case 2:
case 7: channels_irq = &gpio0_irq7; break; channels_irq = &gpio0_irq2;
case 8: channels_irq = &gpio0_irq8; break; break;
case 9: channels_irq = &gpio0_irq9; break; case 3:
case 10: channels_irq = &gpio0_irq10; break; channels_irq = &gpio0_irq3;
case 11: channels_irq = &gpio0_irq11; break; break;
case 12: channels_irq = &gpio0_irq12; break; case 4:
case 13: channels_irq = &gpio0_irq13; break; channels_irq = &gpio0_irq4;
case 14: channels_irq = &gpio0_irq14; break; break;
case 15: channels_irq = &gpio0_irq15; break; case 5:
case 16: channels_irq = &gpio1_irq0; break; channels_irq = &gpio0_irq5;
case 17: channels_irq = &gpio1_irq1; break; break;
case 18: channels_irq = &gpio1_irq2; break; case 6:
case 19: channels_irq = &gpio1_irq3; break; channels_irq = &gpio0_irq6;
case 20: channels_irq = &gpio1_irq4; break; break;
case 21: channels_irq = &gpio1_irq5; break; case 7:
case 22: channels_irq = &gpio1_irq6; break; channels_irq = &gpio0_irq7;
case 23: channels_irq = &gpio1_irq7; break; break;
case 24: channels_irq = &gpio1_irq8; break; case 8:
case 25: channels_irq = &gpio1_irq9; break; channels_irq = &gpio0_irq8;
case 26: channels_irq = &gpio1_irq10; break; break;
case 27: channels_irq = &gpio1_irq11; break; case 9:
case 28: channels_irq = &gpio1_irq12; break; channels_irq = &gpio0_irq9;
case 29: channels_irq = &gpio1_irq13; break; break;
case 30: channels_irq = &gpio1_irq14; break; case 10:
case 31: channels_irq = &gpio1_irq15; break; channels_irq = &gpio0_irq10;
break;
case 11:
channels_irq = &gpio0_irq11;
break;
case 12:
channels_irq = &gpio0_irq12;
break;
case 13:
channels_irq = &gpio0_irq13;
break;
case 14:
channels_irq = &gpio0_irq14;
break;
case 15:
channels_irq = &gpio0_irq15;
break;
case 16:
channels_irq = &gpio1_irq0;
break;
case 17:
channels_irq = &gpio1_irq1;
break;
case 18:
channels_irq = &gpio1_irq2;
break;
case 19:
channels_irq = &gpio1_irq3;
break;
case 20:
channels_irq = &gpio1_irq4;
break;
case 21:
channels_irq = &gpio1_irq5;
break;
case 22:
channels_irq = &gpio1_irq6;
break;
case 23:
channels_irq = &gpio1_irq7;
break;
case 24:
channels_irq = &gpio1_irq8;
break;
case 25:
channels_irq = &gpio1_irq9;
break;
case 26:
channels_irq = &gpio1_irq10;
break;
case 27:
channels_irq = &gpio1_irq11;
break;
case 28:
channels_irq = &gpio1_irq12;
break;
case 29:
channels_irq = &gpio1_irq13;
break;
case 30:
channels_irq = &gpio1_irq14;
break;
case 31:
channels_irq = &gpio1_irq15;
break;
} }
NVIC_SetVector((IRQn_Type)(PININT_IRQ + obj->ch), (uint32_t)channels_irq); NVIC_SetVector((IRQn_Type)(PININT_IRQ + obj->ch), (uint32_t)channels_irq);
@ -169,31 +336,28 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32
} }
} }
void gpio_irq_free(gpio_irq_t *obj) { void gpio_irq_free(gpio_irq_t *obj)
{
} }
void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) { void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
{
unsigned int ch_bit = (1 << obj->ch); unsigned int ch_bit = (1 << obj->ch);
// Clear interrupt // Clear interrupt
if (obj->ch <16) if (obj->ch < 16) {
{ if (!(CMSDK_GPIO_0->INTTYPESET & ch_bit)) {
if (!(CMSDK_GPIO_0->INTTYPESET & ch_bit))
{
CMSDK_GPIO_0->INTCLEAR = ch_bit; CMSDK_GPIO_0->INTCLEAR = ch_bit;
} }
} }
if (obj->ch >= 16) if (obj->ch >= 16) {
{ if (!(CMSDK_GPIO_1->INTTYPESET & ch_bit)) {
if (!(CMSDK_GPIO_1->INTTYPESET & ch_bit))
{
CMSDK_GPIO_1->INTCLEAR = ch_bit; CMSDK_GPIO_1->INTCLEAR = ch_bit;
} }
} }
// Edge trigger // Edge trigger
if (obj->ch <16) if (obj->ch < 16) {
{
CMSDK_GPIO_0->INTTYPESET &= ch_bit; CMSDK_GPIO_0->INTTYPESET &= ch_bit;
if (event == IRQ_RISE) { if (event == IRQ_RISE) {
CMSDK_GPIO_0->INTPOLSET |= ch_bit; CMSDK_GPIO_0->INTPOLSET |= ch_bit;
@ -211,8 +375,7 @@ void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
} }
} }
} }
if (obj->ch >= 16) if (obj->ch >= 16) {
{
CMSDK_GPIO_1->INTTYPESET &= ch_bit; CMSDK_GPIO_1->INTTYPESET &= ch_bit;
if (event == IRQ_RISE) { if (event == IRQ_RISE) {
CMSDK_GPIO_1->INTPOLSET |= ch_bit; CMSDK_GPIO_1->INTPOLSET |= ch_bit;
@ -232,10 +395,12 @@ void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
} }
} }
void gpio_irq_enable(gpio_irq_t *obj) { void gpio_irq_enable(gpio_irq_t *obj)
{
NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch)); NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
} }
void gpio_irq_disable(gpio_irq_t *obj) { void gpio_irq_disable(gpio_irq_t *obj)
{
NVIC_DisableIRQ((IRQn_Type)(PININT_IRQ + obj->ch)); NVIC_DisableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
} }

6
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/gpio_object.h
View File

@ -36,7 +36,8 @@ typedef struct {
__I uint32_t *reg_in; __I uint32_t *reg_in;
} gpio_t; } gpio_t;
static inline void gpio_write(gpio_t *obj, int value) { static inline void gpio_write(gpio_t *obj, int value)
{
if (value) { if (value) {
*obj->reg_data |= (obj->mask); *obj->reg_data |= (obj->mask);
} else { } else {
@ -44,7 +45,8 @@ static inline void gpio_write(gpio_t *obj, int value) {
} }
} }
static inline int gpio_read(gpio_t *obj) { static inline int gpio_read(gpio_t *obj)
{
return ((*obj->reg_in & obj->mask) ? 1 : 0); return ((*obj->reg_in & obj->mask) ? 1 : 0);
} }

182
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/i2c_api.c
View File

@ -75,12 +75,12 @@ static inline void i2c_send_byte(i2c_t *obj, unsigned char c)
obj->i2c->CONTROLC = SCL; obj->i2c->CONTROLC = SCL;
i2c_delay(TSC_TSU); i2c_delay(TSC_TSU);
for (loop = 0; loop < 8; loop++) for (loop = 0; loop < 8; loop++) {
{ if (c & (1 << (7 - loop))) {
if (c & (1 << (7 - loop)))
obj->i2c->CONTROLS = SDA; obj->i2c->CONTROLS = SDA;
else } else {
obj->i2c->CONTROLC = SDA; obj->i2c->CONTROLC = SDA;
}
i2c_delay(TSC_TSU); i2c_delay(TSC_TSU);
obj->i2c->CONTROLS = SCL; obj->i2c->CONTROLS = SCL;
@ -97,10 +97,11 @@ static inline void i2c_send_byte(i2c_t *obj, unsigned char c)
i2c_delay(AAIC_TSU); i2c_delay(AAIC_TSU);
obj->i2c->CONTROLC = SCL; obj->i2c->CONTROLC = SCL;
i2c_delay(AAIC_TSU); i2c_delay(AAIC_TSU);
if (c & (1 << (7 - loop))) if (c & (1 << (7 - loop))) {
obj->i2c->CONTROLS = SDA; obj->i2c->CONTROLS = SDA;
else } else {
obj->i2c->CONTROLC = SDA; obj->i2c->CONTROLC = SDA;
}
i2c_delay(AAIC_TSU); i2c_delay(AAIC_TSU);
obj->i2c->CONTROLS = SCL; obj->i2c->CONTROLS = SCL;
@ -117,12 +118,12 @@ static inline void i2c_send_byte(i2c_t *obj, unsigned char c)
obj->i2c->CONTROLC = SCL; obj->i2c->CONTROLC = SCL;
i2c_delay(SHIELD_TSU); i2c_delay(SHIELD_TSU);
for (loop = 0; loop < 8; loop++) for (loop = 0; loop < 8; loop++) {
{ if (c & (1 << (7 - loop))) {
if (c & (1 << (7 - loop)))
obj->i2c->CONTROLS = SDA; obj->i2c->CONTROLS = SDA;
else } else {
obj->i2c->CONTROLC = SDA; obj->i2c->CONTROLC = SDA;
}
i2c_delay(SHIELD_TSU); i2c_delay(SHIELD_TSU);
obj->i2c->CONTROLS = SCL; obj->i2c->CONTROLS = SCL;
@ -147,12 +148,12 @@ static inline unsigned char i2c_receive_byte(i2c_t *obj)
data_receive_byte = 0; data_receive_byte = 0;
for (loop = 0; loop < 8; loop++) for (loop = 0; loop < 8; loop++) {
{
obj->i2c->CONTROLS = SCL; obj->i2c->CONTROLS = SCL;
i2c_delay(TSC_TSU); i2c_delay(TSC_TSU);
if ((obj->i2c->CONTROL & SDA)) if ((obj->i2c->CONTROL & SDA)) {
data_receive_byte += (1 << (7 - loop)); data_receive_byte += (1 << (7 - loop));
}
obj->i2c->CONTROLC = SCL; obj->i2c->CONTROLC = SCL;
i2c_delay(TSC_TSU); i2c_delay(TSC_TSU);
@ -171,8 +172,9 @@ static inline unsigned char i2c_receive_byte(i2c_t *obj)
i2c_delay(AAIC_TSU); i2c_delay(AAIC_TSU);
obj->i2c->CONTROLS = SCL | SDA; obj->i2c->CONTROLS = SCL | SDA;
i2c_delay(AAIC_TSU); i2c_delay(AAIC_TSU);
if ((obj->i2c->CONTROL & SDA)) if ((obj->i2c->CONTROL & SDA)) {
data_receive_byte += (1 << (7 - loop)); data_receive_byte += (1 << (7 - loop));
}
i2c_delay(AAIC_TSU); i2c_delay(AAIC_TSU);
obj->i2c->CONTROLC = SCL; obj->i2c->CONTROLC = SCL;
@ -189,12 +191,12 @@ static inline unsigned char i2c_receive_byte(i2c_t *obj)
data_receive_byte = 0; data_receive_byte = 0;
for (loop = 0; loop < 8; loop++) for (loop = 0; loop < 8; loop++) {
{
obj->i2c->CONTROLS = SCL; obj->i2c->CONTROLS = SCL;
i2c_delay(SHIELD_TSU); i2c_delay(SHIELD_TSU);
if ((obj->i2c->CONTROL & SDA)) if ((obj->i2c->CONTROL & SDA)) {
data_receive_byte += (1 << (7 - loop)); data_receive_byte += (1 << (7 - loop));
}
obj->i2c->CONTROLC = SCL; obj->i2c->CONTROLC = SCL;
i2c_delay(SHIELD_TSU); i2c_delay(SHIELD_TSU);
@ -212,10 +214,18 @@ static inline int i2c_receive_ack(i2c_t *obj)
int nack; int nack;
int delay_value; int delay_value;
switch ((int)obj->i2c) { switch ((int)obj->i2c) {
case I2C_0: delay_value = TSC_TSU; break; case I2C_0:
case I2C_1: delay_value = AAIC_TSU; break; delay_value = TSC_TSU;
case I2C_2: delay_value = SHIELD_TSU; break; break;
case I2C_3: delay_value = SHIELD_TSU; break; case I2C_1:
delay_value = AAIC_TSU;
break;
case I2C_2:
delay_value = SHIELD_TSU;
break;
case I2C_3:
delay_value = SHIELD_TSU;
break;
} }
i2c_delay(delay_value); i2c_delay(delay_value);
@ -231,8 +241,9 @@ static inline int i2c_receive_ack(i2c_t *obj)
i2c_delay(delay_value); i2c_delay(delay_value);
obj->i2c->CONTROLS = SDA; obj->i2c->CONTROLS = SDA;
i2c_delay(delay_value); i2c_delay(delay_value);
if(nack==0) if (nack == 0) {
return 1; return 1;
}
return 0; return 0;
} }
@ -242,10 +253,18 @@ static inline void i2c_send_nack(i2c_t *obj)
{ {
int delay_value; int delay_value;
switch ((int)obj->i2c) { switch ((int)obj->i2c) {
case I2C_0: delay_value = TSC_TSU; break; case I2C_0:
case I2C_1: delay_value = AAIC_TSU; break; delay_value = TSC_TSU;
case I2C_2: delay_value = SHIELD_TSU; break; break;
case I2C_3: delay_value = SHIELD_TSU; break; case I2C_1:
delay_value = AAIC_TSU;
break;
case I2C_2:
delay_value = SHIELD_TSU;
break;
case I2C_3:
delay_value = SHIELD_TSU;
break;
} }
i2c_delay(delay_value); i2c_delay(delay_value);
@ -266,10 +285,18 @@ static inline void i2c_send_ack(i2c_t *obj)
{ {
int delay_value; int delay_value;
switch ((int)obj->i2c) { switch ((int)obj->i2c) {
case I2C_0: delay_value = TSC_TSU; break; case I2C_0:
case I2C_1: delay_value = AAIC_TSU; break; delay_value = TSC_TSU;
case I2C_2: delay_value = SHIELD_TSU; break; break;
case I2C_3: delay_value = SHIELD_TSU; break; case I2C_1:
delay_value = AAIC_TSU;
break;
case I2C_2:
delay_value = SHIELD_TSU;
break;
case I2C_3:
delay_value = SHIELD_TSU;
break;
} }
i2c_delay(delay_value); i2c_delay(delay_value);
@ -297,9 +324,13 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl)
pinmap_pinout(scl, PinMap_I2C_SCL); pinmap_pinout(scl, PinMap_I2C_SCL);
switch ((int)obj->i2c) { switch ((int)obj->i2c) {
case I2C_2: CMSDK_GPIO0->ALTFUNCSET |= 0x8020; break; case I2C_2:
case I2C_3: CMSDK_GPIO1->ALTFUNCSET |= 0x8000; CMSDK_GPIO0->ALTFUNCSET |= 0x8020;
CMSDK_GPIO2->ALTFUNCSET |= 0x0200; break; break;
case I2C_3:
CMSDK_GPIO1->ALTFUNCSET |= 0x8000;
CMSDK_GPIO2->ALTFUNCSET |= 0x0200;
break;
} }
@ -309,10 +340,18 @@ int i2c_start(i2c_t *obj)
{ {
int delay_value; int delay_value;
switch ((int)obj->i2c) { switch ((int)obj->i2c) {
case I2C_0: delay_value = TSC_TSU; break; case I2C_0:
case I2C_1: delay_value = AAIC_TSU; break; delay_value = TSC_TSU;
case I2C_2: delay_value = SHIELD_TSU; break; break;
case I2C_3: delay_value = SHIELD_TSU; break; case I2C_1:
delay_value = AAIC_TSU;
break;
case I2C_2:
delay_value = SHIELD_TSU;
break;
case I2C_3:
delay_value = SHIELD_TSU;
break;
} }
i2c_delay(delay_value); i2c_delay(delay_value);
@ -328,10 +367,18 @@ int i2c_start_tsc(i2c_t *obj)
{ {
int delay_value; int delay_value;
switch ((int)obj->i2c) { switch ((int)obj->i2c) {
case I2C_0: delay_value = TSC_TSU; break; case I2C_0:
case I2C_1: delay_value = AAIC_TSU; break; delay_value = TSC_TSU;
case I2C_2: delay_value = SHIELD_TSU; break; break;
case I2C_3: delay_value = SHIELD_TSU; break; case I2C_1:
delay_value = AAIC_TSU;
break;
case I2C_2:
delay_value = SHIELD_TSU;
break;
case I2C_3:
delay_value = SHIELD_TSU;
break;
} }
i2c_delay(delay_value); i2c_delay(delay_value);
@ -347,10 +394,18 @@ int i2c_stop(i2c_t *obj)
{ {
int delay_value; int delay_value;
switch ((int)obj->i2c) { switch ((int)obj->i2c) {
case I2C_0: delay_value = TSC_TSU; break; case I2C_0:
case I2C_1: delay_value = AAIC_TSU; break; delay_value = TSC_TSU;
case I2C_2: delay_value = SHIELD_TSU; break; break;
case I2C_3: delay_value = SHIELD_TSU; break; case I2C_1:
delay_value = AAIC_TSU;
break;
case I2C_2:
delay_value = SHIELD_TSU;
break;
case I2C_3:
delay_value = SHIELD_TSU;
break;
} }
// Actual stop bit // Actual stop bit
i2c_delay(delay_value); i2c_delay(delay_value);
@ -366,7 +421,8 @@ int i2c_stop(i2c_t *obj)
void i2c_frequency(i2c_t *obj, int hz) { void i2c_frequency(i2c_t *obj, int hz)
{
} }
int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
@ -412,10 +468,8 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
data[((length - 1) - bytes_read)] = (char)rxdata; data[((length - 1) - bytes_read)] = (char)rxdata;
bytes_read++; bytes_read++;
// Read multiple bytes // Read multiple bytes
if ((length > 1) && (length < 5)) if ((length > 1) && (length < 5)) {
{ for (loop = 1; loop <= (length - 1); loop++) {
for (loop = 1; loop <= (length - 1); loop++)
{
// Send ACK // Send ACK
i2c_send_ack(obj); i2c_send_ack(obj);
@ -452,10 +506,8 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
data[bytes_read] = (char)rxdata; data[bytes_read] = (char)rxdata;
bytes_read++; bytes_read++;
// Read multiple bytes // Read multiple bytes
if ((length > 1) && (length < 5)) if ((length > 1) && (length < 5)) {
{ for (loop = 1; loop <= (length - 1); loop++) {
for (loop = 1; loop <= (length - 1); loop++)
{
// Send ACK // Send ACK
i2c_send_ack(obj); i2c_send_ack(obj);
@ -482,8 +534,7 @@ int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
char *ptr; char *ptr;
char addr; char addr;
ptr = (char *)data; ptr = (char *)data;
switch ((int)obj->i2c) switch ((int)obj->i2c) {
{
case I2C_0: case I2C_0:
sadr = TSC_I2C_ADDR; sadr = TSC_I2C_ADDR;
addr = address; addr = address;
@ -508,26 +559,31 @@ int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
i2c_send_byte(obj, addr); i2c_send_byte(obj, addr);
ack += i2c_receive_ack(obj); ack += i2c_receive_ack(obj);
for(int i = 1; i<length; i++) for (int i = 1; i < length; i++) {
{
i2c_send_byte(obj, *ptr++); i2c_send_byte(obj, *ptr++);
ack += i2c_receive_ack(obj); ack += i2c_receive_ack(obj);
} }
i2c_stop(obj); i2c_stop(obj);
if(ack==3) { return 1; } if (ack == 3) {
else{ return 0; } return 1;
} else {
return 0;
}
} }
void i2c_reset(i2c_t *obj) { void i2c_reset(i2c_t *obj)
{
i2c_stop(obj); i2c_stop(obj);
} }
int i2c_byte_read(i2c_t *obj, int last) { int i2c_byte_read(i2c_t *obj, int last)
{
return 0; return 0;
} }
int i2c_byte_write(i2c_t *obj, int data) { int i2c_byte_write(i2c_t *obj, int data)
{
return 0; return 0;
} }

6
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/pinmap.c
View File

@ -18,11 +18,13 @@
#include "mbed_error.h" #include "mbed_error.h"
void pin_function(PinName pin, int function) { void pin_function(PinName pin, int function)
{
MBED_ASSERT(pin != (PinName)NC); MBED_ASSERT(pin != (PinName)NC);
} }
void pin_mode(PinName pin, PinMode mode) { void pin_mode(PinName pin, PinMode mode)
{
MBED_ASSERT(pin != (PinName)NC); MBED_ASSERT(pin != (PinName)NC);
} }

26
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/port_api.c
View File

@ -17,11 +17,13 @@
#include "pinmap.h" #include "pinmap.h"
#include "gpio_api.h" #include "gpio_api.h"
PinName port_pin(PortName port, int pin_n) { PinName port_pin(PortName port, int pin_n)
{
return (PinName)((port << PORT_SHIFT) | pin_n); return (PinName)((port << PORT_SHIFT) | pin_n);
} }
void port_init(port_t *obj, PortName port, int mask, PinDirection dir) { void port_init(port_t *obj, PortName port, int mask, PinDirection dir)
{
obj->port = port; obj->port = port;
obj->mask = mask; obj->mask = mask;
@ -42,7 +44,8 @@ void port_init(port_t *obj, PortName port, int mask, PinDirection dir) {
port_dir(obj, dir); port_dir(obj, dir);
} }
void port_mode(port_t *obj, PinMode mode) { void port_mode(port_t *obj, PinMode mode)
{
uint32_t i; uint32_t i;
// The mode is set per pin: reuse pinmap logic // The mode is set per pin: reuse pinmap logic
for (i = 0; i < 32; i++) { for (i = 0; i < 32; i++) {
@ -52,17 +55,24 @@ void port_mode(port_t *obj, PinMode mode) {
} }
} }
void port_dir(port_t *obj, PinDirection dir) { void port_dir(port_t *obj, PinDirection dir)
{
switch (dir) { switch (dir) {
case PIN_INPUT : *obj->reg_dir &= ~obj->mask; break; case PIN_INPUT :
case PIN_OUTPUT: *obj->reg_dir |= obj->mask; break; *obj->reg_dir &= ~obj->mask;
break;
case PIN_OUTPUT:
*obj->reg_dir |= obj->mask;
break;
} }
} }
void port_write(port_t *obj, int value) { void port_write(port_t *obj, int value)
{
*obj->reg_in = value; *obj->reg_in = value;
} }
int port_read(port_t *obj) { int port_read(port_t *obj)
{
return (*obj->reg_in); return (*obj->reg_in);
} }

207
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/serial_api.c
View File

@ -60,7 +60,8 @@ struct serial_global_data_s {
static struct serial_global_data_s uart_data[UART_NUM]; static struct serial_global_data_s uart_data[UART_NUM];
void serial_init(serial_t *obj, PinName tx, PinName rx) { void serial_init(serial_t *obj, PinName tx, PinName rx)
{
int is_stdio_uart = 0; int is_stdio_uart = 0;
// determine the UART to use // determine the UART to use
@ -73,21 +74,17 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) {
obj->uart = (CMSDK_UART_TypeDef *)uart; obj->uart = (CMSDK_UART_TypeDef *)uart;
//set baud rate and enable Uart in normarl mode (RX and TX enabled) //set baud rate and enable Uart in normarl mode (RX and TX enabled)
switch (uart) switch (uart) {
{ case UART_0: {
case UART_0:
{
CMSDK_UART0->CTRL = 0x00; // Disable UART when changing configuration CMSDK_UART0->CTRL = 0x00; // Disable UART when changing configuration
if((int)uart_tx != NC) if ((int)uart_tx != NC) {
{
CMSDK_UART0->CTRL |= 0x01; // TX enable CMSDK_UART0->CTRL |= 0x01; // TX enable
} else { } else {
CMSDK_UART0->CTRL &= 0xFFFE; // TX disable CMSDK_UART0->CTRL &= 0xFFFE; // TX disable
} }
if((int)uart_rx != NC) if ((int)uart_rx != NC) {
{
CMSDK_UART0->CTRL |= 0x02; // RX enable CMSDK_UART0->CTRL |= 0x02; // RX enable
} else { } else {
CMSDK_UART0->CTRL &= 0xFFFD; // RX disable CMSDK_UART0->CTRL &= 0xFFFD; // RX disable
@ -95,46 +92,37 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) {
} }
break; break;
case UART_1: //XBEE SOCKET UART case UART_1: { //XBEE SOCKET UART
{
CMSDK_UART1->CTRL = 0x00; // Disable UART when changing configuration CMSDK_UART1->CTRL = 0x00; // Disable UART when changing configuration
if((int)tx != NC) if ((int)tx != NC) {
{
CMSDK_UART1->CTRL = 0x1; // TX enable CMSDK_UART1->CTRL = 0x1; // TX enable
CMSDK_GPIO1->ALTFUNCSET |= 0x0100; CMSDK_GPIO1->ALTFUNCSET |= 0x0100;
} }
if((int)rx != NC) if ((int)rx != NC) {
{
CMSDK_UART1->CTRL |= 0x2; // RX enable CMSDK_UART1->CTRL |= 0x2; // RX enable
CMSDK_GPIO1->ALTFUNCSET |= 0x0080; CMSDK_GPIO1->ALTFUNCSET |= 0x0080;
} }
} }
break; break;
case UART_2: //Sheild0 UART case UART_2: { //Sheild0 UART
{
CMSDK_UART3->CTRL = 0x00; // Disable UART when changing configuration CMSDK_UART3->CTRL = 0x00; // Disable UART when changing configuration
if((int)tx != NC) if ((int)tx != NC) {
{
CMSDK_UART3->CTRL = 0x1; // TX enable CMSDK_UART3->CTRL = 0x1; // TX enable
CMSDK_GPIO0->ALTFUNCSET |= 0x0010; CMSDK_GPIO0->ALTFUNCSET |= 0x0010;
} }
if((int)rx != NC) if ((int)rx != NC) {
{
CMSDK_UART3->CTRL |= 0x2; // RX enable CMSDK_UART3->CTRL |= 0x2; // RX enable
CMSDK_GPIO0->ALTFUNCSET |= 0x0001; CMSDK_GPIO0->ALTFUNCSET |= 0x0001;
} }
} }
break; break;
case UART_3: //Sheild1 UART case UART_3: { //Sheild1 UART
{
CMSDK_UART4->CTRL = 0x00; // Disable UART when changing configuration CMSDK_UART4->CTRL = 0x00; // Disable UART when changing configuration
if((int)tx != NC) if ((int)tx != NC) {
{
CMSDK_UART4->CTRL = 0x1; // TX enable CMSDK_UART4->CTRL = 0x1; // TX enable
CMSDK_GPIO1->ALTFUNCSET |= 0x4000; CMSDK_GPIO1->ALTFUNCSET |= 0x4000;
} }
if((int)rx != NC) if ((int)rx != NC) {
{
CMSDK_UART4->CTRL |= 0x2; // RX enable CMSDK_UART4->CTRL |= 0x2; // RX enable
CMSDK_GPIO1->ALTFUNCSET |= 0x0400; CMSDK_GPIO1->ALTFUNCSET |= 0x0400;
} }
@ -150,10 +138,18 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) {
pinmap_pinout(rx, PinMap_UART_RX); pinmap_pinout(rx, PinMap_UART_RX);
switch (uart) { switch (uart) {
case UART_0: obj->index = 0; break; case UART_0:
case UART_1: obj->index = 1; break; obj->index = 0;
case UART_2: obj->index = 2; break; break;
case UART_3: obj->index = 3; break; case UART_1:
obj->index = 1;
break;
case UART_2:
obj->index = 2;
break;
case UART_3:
obj->index = 3;
break;
} }
uart_data[obj->index].sw_rts.pin = NC; uart_data[obj->index].sw_rts.pin = NC;
uart_data[obj->index].sw_cts.pin = NC; uart_data[obj->index].sw_cts.pin = NC;
@ -167,13 +163,15 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) {
} }
} }
void serial_free(serial_t *obj) { void serial_free(serial_t *obj)
{
uart_data[obj->index].serial_irq_id = 0; uart_data[obj->index].serial_irq_id = 0;
} }
// serial_baud // serial_baud
// set the baud rate, taking in to account the current SystemFrequency // set the baud rate, taking in to account the current SystemFrequency
void serial_baud(serial_t *obj, int baudrate) { void serial_baud(serial_t *obj, int baudrate)
{
// The MPS2 has a simple divider to control the baud rate. The formula is: // The MPS2 has a simple divider to control the baud rate. The formula is:
// //
// Baudrate = PCLK / BAUDDIV // Baudrate = PCLK / BAUDDIV
@ -187,11 +185,21 @@ void serial_baud(serial_t *obj, int baudrate) {
baudrate_div = SystemCoreClock / baudrate; baudrate_div = SystemCoreClock / baudrate;
if (baudrate >= 16) { if (baudrate >= 16) {
switch ((int)obj->uart) { switch ((int)obj->uart) {
case UART_0: CMSDK_UART0->BAUDDIV = baudrate_div; break; case UART_0:
case UART_1: CMSDK_UART1->BAUDDIV = baudrate_div; break; CMSDK_UART0->BAUDDIV = baudrate_div;
case UART_2: CMSDK_UART3->BAUDDIV = baudrate_div; break; break;
case UART_3: CMSDK_UART4->BAUDDIV = baudrate_div; break; case UART_1:
default: error("serial_baud"); break; CMSDK_UART1->BAUDDIV = baudrate_div;
break;
case UART_2:
CMSDK_UART3->BAUDDIV = baudrate_div;
break;
case UART_3:
CMSDK_UART4->BAUDDIV = baudrate_div;
break;
default:
error("serial_baud");
break;
} }
} else { } else {
error("serial_baud"); error("serial_baud");
@ -199,125 +207,122 @@ void serial_baud(serial_t *obj, int baudrate) {
} }
void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) { void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
{
} }
/****************************************************************************** /******************************************************************************
* INTERRUPTS HANDLING * INTERRUPTS HANDLING
******************************************************************************/ ******************************************************************************/
static inline void uart_irq(uint32_t intstatus, uint32_t index, CMSDK_UART_TypeDef *puart) { static inline void uart_irq(uint32_t intstatus, uint32_t index, CMSDK_UART_TypeDef *puart)
{
SerialIrq irq_type; SerialIrq irq_type;
switch (intstatus) switch (intstatus) {
{ case 1: {
case 1:
{
irq_type = TxIrq; irq_type = TxIrq;
} }
break; break;
case 2: case 2: {
{
irq_type = RxIrq; irq_type = RxIrq;
} }
break; break;
default: return; default:
return;
} /* End of Switch */ } /* End of Switch */
if ((RxIrq == irq_type) && (NC != uart_data[index].sw_rts.pin)) if ((RxIrq == irq_type) && (NC != uart_data[index].sw_rts.pin)) {
{
gpio_write(&uart_data[index].sw_rts, 1); gpio_write(&uart_data[index].sw_rts, 1);
// Disable interrupt if it wasn't enabled by other part of the application // Disable interrupt if it wasn't enabled by other part of the application
if (!uart_data[index].rx_irq_set_api) if (!uart_data[index].rx_irq_set_api) {
{
/* Disable Rx interrupt */ /* Disable Rx interrupt */
puart->CTRL &= ~(CMSDK_UART_CTRL_RXIRQEN_Msk); puart->CTRL &= ~(CMSDK_UART_CTRL_RXIRQEN_Msk);
} }
} }
if (uart_data[index].serial_irq_id != 0) if (uart_data[index].serial_irq_id != 0) {
{ if ((irq_type != RxIrq) || (uart_data[index].rx_irq_set_api)) {
if ((irq_type != RxIrq) || (uart_data[index].rx_irq_set_api))
{
irq_handler(uart_data[index].serial_irq_id, irq_type); irq_handler(uart_data[index].serial_irq_id, irq_type);
} }
} }
if( irq_type == TxIrq ) if (irq_type == TxIrq) {
{
/* Clear the TX interrupt Flag */ /* Clear the TX interrupt Flag */
puart->INTCLEAR |= 0x01; puart->INTCLEAR |= 0x01;
} } else {
else
{
/* Clear the Rx interupt Flag */ /* Clear the Rx interupt Flag */
puart->INTCLEAR |= 0x02; puart->INTCLEAR |= 0x02;
} }
} }
void uart0_irq() {uart_irq(CMSDK_UART0->INTSTATUS & 0x3, 0, (CMSDK_UART_TypeDef*)CMSDK_UART0);} void uart0_irq()
void uart1_irq() {uart_irq(CMSDK_UART1->INTSTATUS & 0x3, 1, (CMSDK_UART_TypeDef*)CMSDK_UART1);} {
void uart2_irq() {uart_irq(CMSDK_UART3->INTSTATUS & 0x3, 2, (CMSDK_UART_TypeDef*)CMSDK_UART3);} uart_irq(CMSDK_UART0->INTSTATUS & 0x3, 0, (CMSDK_UART_TypeDef *)CMSDK_UART0);
void uart3_irq() {uart_irq(CMSDK_UART4->INTSTATUS & 0x3, 3, (CMSDK_UART_TypeDef*)CMSDK_UART4);} }
void uart1_irq()
{
uart_irq(CMSDK_UART1->INTSTATUS & 0x3, 1, (CMSDK_UART_TypeDef *)CMSDK_UART1);
}
void uart2_irq()
{
uart_irq(CMSDK_UART3->INTSTATUS & 0x3, 2, (CMSDK_UART_TypeDef *)CMSDK_UART3);
}
void uart3_irq()
{
uart_irq(CMSDK_UART4->INTSTATUS & 0x3, 3, (CMSDK_UART_TypeDef *)CMSDK_UART4);
}
void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
{
irq_handler = handler; irq_handler = handler;
uart_data[obj->index].serial_irq_id = id; uart_data[obj->index].serial_irq_id = id;
} }
static void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enable) { static void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enable)
{
/* Declare a variable of type IRQn, initialise to 0 */ /* Declare a variable of type IRQn, initialise to 0 */
IRQn_Type irq_n = (IRQn_Type)0; IRQn_Type irq_n = (IRQn_Type)0;
uint32_t vector = 0; uint32_t vector = 0;
switch ((int)obj->uart) switch ((int)obj->uart) {
{ case UART_0: {
case UART_0:
{
irq_n = ((irq == TxIrq) ? UARTTX0_IRQn : UARTRX0_IRQn); irq_n = ((irq == TxIrq) ? UARTTX0_IRQn : UARTRX0_IRQn);
vector = (uint32_t)&uart0_irq; vector = (uint32_t)&uart0_irq;
} }
break; break;
case UART_1: case UART_1: {
{
irq_n = ((irq == TxIrq) ? UARTTX1_IRQn : UARTRX1_IRQn); irq_n = ((irq == TxIrq) ? UARTTX1_IRQn : UARTRX1_IRQn);
vector = (uint32_t)&uart1_irq; vector = (uint32_t)&uart1_irq;
} }
break; break;
case UART_2: case UART_2: {
{
irq_n = ((irq == TxIrq) ? UARTTX3_IRQn : UARTRX3_IRQn); irq_n = ((irq == TxIrq) ? UARTTX3_IRQn : UARTRX3_IRQn);
vector = (uint32_t)&uart2_irq; vector = (uint32_t)&uart2_irq;
} }
break; break;
case UART_3: case UART_3: {
{
irq_n = ((irq == TxIrq) ? UARTTX4_IRQn : UARTRX4_IRQn); irq_n = ((irq == TxIrq) ? UARTTX4_IRQn : UARTRX4_IRQn);
vector = (uint32_t)&uart3_irq; vector = (uint32_t)&uart3_irq;
} }
break; break;
} }
if (enable) if (enable) {
{ if (irq == TxIrq) {
if( irq == TxIrq )
{
/* Transmit IRQ, set appripriate enable */ /* Transmit IRQ, set appripriate enable */
/* set TX interrupt enable in CTRL REG */ /* set TX interrupt enable in CTRL REG */
obj->uart->CTRL |= CMSDK_UART_CTRL_TXIRQEN_Msk; obj->uart->CTRL |= CMSDK_UART_CTRL_TXIRQEN_Msk;
} } else {
else
{
/* set Rx interrupt on in CTRL REG */ /* set Rx interrupt on in CTRL REG */
obj->uart->CTRL |= CMSDK_UART_CTRL_RXIRQEN_Msk; obj->uart->CTRL |= CMSDK_UART_CTRL_RXIRQEN_Msk;
} }
NVIC_SetVector(irq_n, vector); NVIC_SetVector(irq_n, vector);
NVIC_EnableIRQ(irq_n); NVIC_EnableIRQ(irq_n);
} } else {
else /* Disable IRQ */
{ /* Disable IRQ */
obj->uart->CTRL &= ~(1 << (irq + 2)); obj->uart->CTRL &= ~(1 << (irq + 2));
@ -325,45 +330,55 @@ static void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enabl
} }
} }
void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
{
serial_irq_set_internal(obj, irq, enable); serial_irq_set_internal(obj, irq, enable);
} }
/****************************************************************************** /******************************************************************************
* READ/WRITE * READ/WRITE
******************************************************************************/ ******************************************************************************/
int serial_getc(serial_t *obj) { int serial_getc(serial_t *obj)
{
while (serial_readable(obj) == 0); while (serial_readable(obj) == 0);
int data = obj->uart->DATA; int data = obj->uart->DATA;
return data; return data;
} }
void serial_putc(serial_t *obj, int c) { void serial_putc(serial_t *obj, int c)
{
while (serial_writable(obj) == 0); while (serial_writable(obj) == 0);
obj->uart->DATA = c; obj->uart->DATA = c;
} }
int serial_readable(serial_t *obj) { int serial_readable(serial_t *obj)
{
return obj->uart->STATE & 0x2; return obj->uart->STATE & 0x2;
} }
int serial_writable(serial_t *obj) { int serial_writable(serial_t *obj)
{
return !(obj->uart->STATE & 0x1); return !(obj->uart->STATE & 0x1);
} }
void serial_clear(serial_t *obj) { void serial_clear(serial_t *obj)
{
obj->uart->DATA = 0x00; obj->uart->DATA = 0x00;
} }
void serial_pinout_tx(PinName tx) { void serial_pinout_tx(PinName tx)
{
pinmap_pinout(tx, PinMap_UART_TX); pinmap_pinout(tx, PinMap_UART_TX);
} }
void serial_break_set(serial_t *obj) { void serial_break_set(serial_t *obj)
{
} }
void serial_break_clear(serial_t *obj) { void serial_break_clear(serial_t *obj)
{
} }
void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) { void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow)
{
} }

72
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/spi_api.c
View File

@ -61,7 +61,8 @@ static const PinMap PinMap_SPI_SSEL[] = {
static inline int ssp_disable(spi_t *obj); static inline int ssp_disable(spi_t *obj);
static inline int ssp_enable(spi_t *obj); static inline int ssp_enable(spi_t *obj);
void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) { void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
{
int altfunction[4]; int altfunction[4];
// determine the SPI to use // determine the SPI to use
@ -132,10 +133,26 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel
break; break;
} }
if(mosi != NC){ altfunction[0] = 1;}else{ altfunction[0] = 0;} if (mosi != NC) {
if(miso != NC){ altfunction[1] = 1;}else{ altfunction[1] = 0;} altfunction[0] = 1;
if(sclk != NC){ altfunction[2] = 1;}else{ altfunction[2] = 0;} } else {
if(ssel != NC){ altfunction[3] = 1;}else{ altfunction[3] = 0;} altfunction[0] = 0;
}
if (miso != NC) {
altfunction[1] = 1;
} else {
altfunction[1] = 0;
}
if (sclk != NC) {
altfunction[2] = 1;
} else {
altfunction[2] = 0;
}
if (ssel != NC) {
altfunction[3] = 1;
} else {
altfunction[3] = 0;
}
// enable alt function // enable alt function
switch ((int)obj->spi) { switch ((int)obj->spi) {
@ -172,7 +189,8 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel
void spi_free(spi_t *obj) {} void spi_free(spi_t *obj) {}
void spi_format(spi_t *obj, int bits, int mode, int slave) { void spi_format(spi_t *obj, int bits, int mode, int slave)
{
ssp_disable(obj); ssp_disable(obj);
if (!(bits >= 4 && bits <= 16) || !(mode >= 0 && mode <= 3)) { if (!(bits >= 4 && bits <= 16) || !(mode >= 0 && mode <= 3)) {
error("SPI format error"); error("SPI format error");
@ -205,7 +223,8 @@ void spi_format(spi_t *obj, int bits, int mode, int slave) {
ssp_enable(obj); ssp_enable(obj);
} }
void spi_frequency(spi_t *obj, int hz) { void spi_frequency(spi_t *obj, int hz)
{
ssp_disable(obj); ssp_disable(obj);
uint32_t PCLK = SystemCoreClock; uint32_t PCLK = SystemCoreClock;
@ -233,43 +252,52 @@ void spi_frequency(spi_t *obj, int hz) {
error("Couldn't setup requested SPI frequency"); error("Couldn't setup requested SPI frequency");
} }
static inline int ssp_disable(spi_t *obj) { static inline int ssp_disable(spi_t *obj)
{
return obj->spi->CR1 &= ~(1 << 1); return obj->spi->CR1 &= ~(1 << 1);
} }
static inline int ssp_enable(spi_t *obj) { static inline int ssp_enable(spi_t *obj)
{
return obj->spi->CR1 |= SSP_CR1_SSE_Msk; return obj->spi->CR1 |= SSP_CR1_SSE_Msk;
} }
static inline int ssp_readable(spi_t *obj) { static inline int ssp_readable(spi_t *obj)
{
return obj->spi->SR & (1 << 2); return obj->spi->SR & (1 << 2);
} }
static inline int ssp_writeable(spi_t *obj) { static inline int ssp_writeable(spi_t *obj)
{
return obj->spi->SR & SSP_SR_BSY_Msk; return obj->spi->SR & SSP_SR_BSY_Msk;
} }
static inline void ssp_write(spi_t *obj, int value) { static inline void ssp_write(spi_t *obj, int value)
{
obj->spi->DR = value; obj->spi->DR = value;
while (ssp_writeable(obj)); while (ssp_writeable(obj));
} }
static inline int ssp_read(spi_t *obj) { static inline int ssp_read(spi_t *obj)
{
int read_DR = obj->spi->DR; int read_DR = obj->spi->DR;
return read_DR; return read_DR;
} }
static inline int ssp_busy(spi_t *obj) { static inline int ssp_busy(spi_t *obj)
{
return (obj->spi->SR & (1 << 4)) ? (1) : (0); return (obj->spi->SR & (1 << 4)) ? (1) : (0);
} }
int spi_master_write(spi_t *obj, int value) { int spi_master_write(spi_t *obj, int value)
{
ssp_write(obj, value); ssp_write(obj, value);
while (obj->spi->SR & SSP_SR_BSY_Msk); /* Wait for send to finish */ while (obj->spi->SR & SSP_SR_BSY_Msk); /* Wait for send to finish */
return (ssp_read(obj)); return (ssp_read(obj));
} }
int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
char *rx_buffer, int rx_length, char write_fill) { char *rx_buffer, int rx_length, char write_fill)
{
int total = (tx_length > rx_length) ? tx_length : rx_length; int total = (tx_length > rx_length) ? tx_length : rx_length;
for (int i = 0; i < total; i++) { for (int i = 0; i < total; i++) {
@ -283,19 +311,23 @@ int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
return total; return total;
} }
int spi_slave_receive(spi_t *obj) { int spi_slave_receive(spi_t *obj)
{
return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0); return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0);
} }
int spi_slave_read(spi_t *obj) { int spi_slave_read(spi_t *obj)
{
return obj->spi->DR; return obj->spi->DR;
} }
void spi_slave_write(spi_t *obj, int value) { void spi_slave_write(spi_t *obj, int value)
{
while (ssp_writeable(obj) == 0) ; while (ssp_writeable(obj) == 0) ;
obj->spi->DR = value; obj->spi->DR = value;
} }
int spi_busy(spi_t *obj) { int spi_busy(spi_t *obj)
{
return ssp_busy(obj); return ssp_busy(obj);
} }

25
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/us_ticker.c
View File

@ -23,8 +23,11 @@
int us_ticker_inited = 0; int us_ticker_inited = 0;
void us_ticker_init(void) { void us_ticker_init(void)
if (us_ticker_inited) return; {
if (us_ticker_inited) {
return;
}
us_ticker_inited = 1; us_ticker_inited = 1;
US_TICKER_TIMER1->TimerControl = 0x0; // disable timer US_TICKER_TIMER1->TimerControl = 0x0; // disable timer
@ -42,17 +45,21 @@ void us_ticker_init(void) {
NVIC_EnableIRQ(US_TICKER_TIMER_IRQn); NVIC_EnableIRQ(US_TICKER_TIMER_IRQn);
} }
uint32_t us_ticker_read() { uint32_t us_ticker_read()
{
uint32_t return_value = 0; uint32_t return_value = 0;
if (!us_ticker_inited) if (!us_ticker_inited) {
us_ticker_init(); us_ticker_init();
}
return_value = ((~US_TICKER_TIMER2->TimerValue) / 25); return_value = ((~US_TICKER_TIMER2->TimerValue) / 25);
return return_value; return return_value;
} }
void us_ticker_set_interrupt(timestamp_t timestamp) { void us_ticker_set_interrupt(timestamp_t timestamp)
if (!us_ticker_inited) {
if (!us_ticker_inited) {
us_ticker_init(); us_ticker_init();
}
uint32_t delta = timestamp - us_ticker_read(); uint32_t delta = timestamp - us_ticker_read();
// enable interrupt // enable interrupt
@ -68,14 +75,16 @@ void us_ticker_fire_interrupt(void)
} }
void us_ticker_disable_interrupt(void) { void us_ticker_disable_interrupt(void)
{
US_TICKER_TIMER1->TimerControl &= 0xDF; US_TICKER_TIMER1->TimerControl &= 0xDF;
US_TICKER_TIMER2->TimerControl &= 0xDF; US_TICKER_TIMER2->TimerControl &= 0xDF;
} }
void us_ticker_clear_interrupt(void) { void us_ticker_clear_interrupt(void)
{
US_TICKER_TIMER1->TimerIntClr = 0x1; US_TICKER_TIMER1->TimerIntClr = 0x1;
US_TICKER_TIMER2->TimerIntClr = 0x1; US_TICKER_TIMER2->TimerIntClr = 0x1;