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[M487] Revise CAN & AES to fulfill real-chip

pull/4608/head
cyliangtw 2017-06-15 17:56:54 +08:00 committed by ccli8
parent 8f67774fd9
commit aa47503435
3 changed files with 24 additions and 27 deletions
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34
features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c
View File

@ -38,7 +38,6 @@
#include "mbed_toolchain.h"
#include "mbed_assert.h"
//static int aes_init_done = 0;
#define mbedtls_trace(...) //printf(__VA_ARGS__)
@ -83,15 +82,21 @@ static void swapInitVector(unsigned char iv[16])
}
}
//volatile void CRYPTO_IRQHandler()
//{
// if (AES_GET_INT_FLAG()) {
// g_AES_done = 1;
// AES_CLR_INT_FLAG();
// }
//}
/* IRQHandler: To share CRYPTO_IRQHandler() with TRNG & other crypto IPs
For ex:
volatile void CRYPTO_IRQHandler()
{
...
if (AES_GET_INT_FLAG()) {
g_AES_done = 1;
AES_CLR_INT_FLAG();
}
...
}
*/
// AES available channel 0~3
/* AES available channel 0~3 */
static unsigned char channel_flag[4]={0x00,0x00,0x00,0x00}; // 0: idle, 1: busy
static int channel_alloc()
{
@ -118,8 +123,6 @@ void mbedtls_aes_init( mbedtls_aes_context *ctx )
{
int i =-1;
// sw_mbedtls_aes_init(ctx);
// return;
mbedtls_trace("=== %s \r\n", __FUNCTION__);
memset( ctx, 0, sizeof( mbedtls_aes_context ) );
@ -128,7 +131,6 @@ void mbedtls_aes_init( mbedtls_aes_context *ctx )
while( (i = channel_alloc()) < 0 )
{
mbed_assert_internal("No available AES channel", __FILE__, __LINE__);
//osDelay(300);
}
ctx->channel = i;
ctx->iv = au32MyAESIV;
@ -152,14 +154,6 @@ void mbedtls_aes_free( mbedtls_aes_context *ctx )
if( ctx == NULL )
return;
/* Unlock protected registers */
// SYS_UnlockReg();
// CLK_DisableModuleClock(CRPT_MODULE);
/* Lock protected registers */
// SYS_LockReg();
// NVIC_DisableIRQ(CRPT_IRQn);
// AES_DISABLE_INT();
channel_free(ctx->channel);
mbedtls_zeroize( ctx, sizeof( mbedtls_aes_context ) );
}

11
targets/TARGET_NUVOTON/TARGET_M480/can_api.c
View File

@ -48,9 +48,8 @@ extern void CAN_EnterTestMode(CAN_T *tCAN, uint8_t u8TestMask);
{NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL}
};
void can_init(can_t *obj, PinName rd, PinName td)
{
void can_init_freq(can_t *obj, PinName rd, PinName td, int hz)
{
uint32_t can_td = (CANName)pinmap_peripheral(td, PinMap_CAN_TD);
uint32_t can_rd = (CANName)pinmap_peripheral(rd, PinMap_CAN_RD);
obj->can = (CANName)pinmap_merge(can_td, can_rd);
@ -83,11 +82,15 @@ extern void CAN_EnterTestMode(CAN_T *tCAN, uint8_t u8TestMask);
PA2 = 0x00;
PA3 = 0x00;
#endif
CAN_Open((CAN_T *)NU_MODBASE(obj->can), 500000, CAN_NORMAL_MODE);
CAN_Open((CAN_T *)NU_MODBASE(obj->can), hz, CAN_NORMAL_MODE);
can_filter(obj, 0, 0, CANStandard, 0);
}
void can_init(can_t *obj, PinName rd, PinName td)
{
can_init_freq(obj, rd, td, 500000);
}
void can_free(can_t *obj)
{

2
targets/targets.json
View File

@ -3265,7 +3265,7 @@
"supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
"inherits": ["Target"],
"macros_add": ["MBEDTLS_CONFIG_HW_SUPPORT"],
"device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "STDIO_MESSAGES", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "TRNG", "FLASH"],
"device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "STDIO_MESSAGES", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "TRNG", "FLASH", "CAN"],
"features": ["LWIP"],
"release_versions": ["5"],
"device_name": "M487JIDAE",