diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c4588azi_h675.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c4588azi_h675.h index cd5846b4f4..f8940c6917 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c4588azi_h675.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c4588azi_h675.h @@ -5,7 +5,7 @@ * CY8C4588AZI-H675 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -471,18 +471,6 @@ typedef enum { #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -// #define CY_IP_MXS40PASS 1u -// #define CY_IP_MXS40PASS_INSTANCES 1u -// #define CY_IP_MXS40PASS_VERSION 2u -// #define CY_IP_MXS40PASS_SAR 1u -// #define CY_IP_MXS40PASS_SAR_INSTANCES 2u -// #define CY_IP_MXS40PASS_SAR_VERSION 2u -// #define CY_IP_MXS40PASS_CTDAC 1u -// #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u -// #define CY_IP_MXS40PASS_CTDAC_VERSION 2u -// #define CY_IP_MXS40PASS_CTB 1u -// #define CY_IP_MXS40PASS_CTB_INSTANCES 1u -// #define CY_IP_MXS40PASS_CTB_VERSION 2u #define CY_IP_MXPERI 1u #define CY_IP_MXPERI_INSTANCES 1u #define CY_IP_MXPERI_VERSION 2u @@ -504,9 +492,6 @@ typedef enum { #define CY_IP_MXS40SRSS_MCWDT 1u #define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u #define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -// #define CY_IP_MXTCPWM 1u -// #define CY_IP_MXTCPWM_INSTANCES 1u -// #define CY_IP_MXTCPWM_VERSION 2u #include "psoc6_04_config.h" #include "gpio_psoc6_04_64_tqfp.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c4588azi_h676.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c4588azi_h676.h index fad466291f..4841dfd3c4 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c4588azi_h676.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c4588azi_h676.h @@ -5,7 +5,7 @@ * CY8C4588AZI-H676 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -471,18 +471,6 @@ typedef enum { #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -// #define CY_IP_MXS40PASS 1u -// #define CY_IP_MXS40PASS_INSTANCES 1u -// #define CY_IP_MXS40PASS_VERSION 2u -// #define CY_IP_MXS40PASS_SAR 1u -// #define CY_IP_MXS40PASS_SAR_INSTANCES 2u -// #define CY_IP_MXS40PASS_SAR_VERSION 2u -// #define CY_IP_MXS40PASS_CTDAC 1u -// #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u -// #define CY_IP_MXS40PASS_CTDAC_VERSION 2u -// #define CY_IP_MXS40PASS_CTB 1u -// #define CY_IP_MXS40PASS_CTB_INSTANCES 1u -// #define CY_IP_MXS40PASS_CTB_VERSION 2u #define CY_IP_MXPERI 1u #define CY_IP_MXPERI_INSTANCES 1u #define CY_IP_MXPERI_VERSION 2u @@ -504,9 +492,6 @@ typedef enum { #define CY_IP_MXS40SRSS_MCWDT 1u #define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u #define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -// #define CY_IP_MXTCPWM 1u -// #define CY_IP_MXTCPWM_INSTANCES 1u -// #define CY_IP_MXTCPWM_VERSION 2u #include "psoc6_04_config.h" #include "gpio_psoc6_04_80_tqfp.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c4588azi_h685.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c4588azi_h685.h index bdbda38645..d029c664c6 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c4588azi_h685.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c4588azi_h685.h @@ -5,7 +5,7 @@ * CY8C4588AZI-H685 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -471,18 +471,6 @@ typedef enum { #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -// #define CY_IP_MXS40PASS 1u -// #define CY_IP_MXS40PASS_INSTANCES 1u -// #define CY_IP_MXS40PASS_VERSION 2u -// #define CY_IP_MXS40PASS_SAR 1u -// #define CY_IP_MXS40PASS_SAR_INSTANCES 2u -// #define CY_IP_MXS40PASS_SAR_VERSION 2u -// #define CY_IP_MXS40PASS_CTDAC 1u -// #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u -// #define CY_IP_MXS40PASS_CTDAC_VERSION 2u -// #define CY_IP_MXS40PASS_CTB 1u -// #define CY_IP_MXS40PASS_CTB_INSTANCES 1u -// #define CY_IP_MXS40PASS_CTB_VERSION 2u #define CY_IP_MXPERI 1u #define CY_IP_MXPERI_INSTANCES 1u #define CY_IP_MXPERI_VERSION 2u @@ -504,9 +492,6 @@ typedef enum { #define CY_IP_MXS40SRSS_MCWDT 1u #define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u #define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -// #define CY_IP_MXTCPWM 1u -// #define CY_IP_MXTCPWM_INSTANCES 1u -// #define CY_IP_MXTCPWM_VERSION 2u #include "psoc6_04_config.h" #include "gpio_psoc6_04_64_tqfp.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c4588azi_h686.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c4588azi_h686.h index 6e1a752be9..a9e030aeda 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c4588azi_h686.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c4588azi_h686.h @@ -5,7 +5,7 @@ * CY8C4588AZI-H686 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -471,18 +471,6 @@ typedef enum { #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -// #define CY_IP_MXS40PASS 1u -// #define CY_IP_MXS40PASS_INSTANCES 1u -// #define CY_IP_MXS40PASS_VERSION 2u -// #define CY_IP_MXS40PASS_SAR 1u -// #define CY_IP_MXS40PASS_SAR_INSTANCES 2u -// #define CY_IP_MXS40PASS_SAR_VERSION 2u -// #define CY_IP_MXS40PASS_CTDAC 1u -// #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u -// #define CY_IP_MXS40PASS_CTDAC_VERSION 2u -// #define CY_IP_MXS40PASS_CTB 1u -// #define CY_IP_MXS40PASS_CTB_INSTANCES 1u -// #define CY_IP_MXS40PASS_CTB_VERSION 2u #define CY_IP_MXPERI 1u #define CY_IP_MXPERI_INSTANCES 1u #define CY_IP_MXPERI_VERSION 2u @@ -504,9 +492,6 @@ typedef enum { #define CY_IP_MXS40SRSS_MCWDT 1u #define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u #define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -// #define CY_IP_MXTCPWM 1u -// #define CY_IP_MXTCPWM_INSTANCES 1u -// #define CY_IP_MXTCPWM_VERSION 2u #include "psoc6_04_config.h" #include "gpio_psoc6_04_80_tqfp.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6016bzi_f04.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6016bzi_f04.h index ed17949ce1..30c137b9b1 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6016bzi_f04.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6016bzi_f04.h @@ -5,7 +5,7 @@ * CY8C6016BZI-F04 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -246,42 +246,27 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -294,21 +279,36 @@ typedef enum { #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u #define CY_IP_MXS40PASS_CTDAC_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_124_bga.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6036bzi_f04.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6036bzi_f04.h index f7b11c404c..080d4312ea 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6036bzi_f04.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6036bzi_f04.h @@ -5,7 +5,7 @@ * CY8C6036BZI-F04 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -246,42 +246,27 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -294,21 +279,36 @@ typedef enum { #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u #define CY_IP_MXS40PASS_CTDAC_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_124_bga.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6116bzi_f54.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6116bzi_f54.h index cad576cf83..b668986672 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6116bzi_f54.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6116bzi_f54.h @@ -5,7 +5,7 @@ * CY8C6116BZI-F54 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -246,33 +246,9 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -282,9 +258,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -300,24 +285,39 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_124_bga.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6117bzi_f34.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6117bzi_f34.h index 92cb24f450..9dfb2c587c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6117bzi_f34.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6117bzi_f34.h @@ -5,7 +5,7 @@ * CY8C6117BZI-F34 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -246,42 +246,27 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -297,24 +282,39 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_124_bga.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6117fdi_f02.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6117fdi_f02.h index f615622fb9..52d470f531 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6117fdi_f02.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6117fdi_f02.h @@ -5,7 +5,7 @@ * CY8C6117FDI-F02 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -246,42 +246,27 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -294,21 +279,36 @@ typedef enum { #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u #define CY_IP_MXS40PASS_CTDAC_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_80_wlcsp.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6117wi_f34.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6117wi_f34.h index f8f7699277..29f84cf61e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6117wi_f34.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6117wi_f34.h @@ -5,7 +5,7 @@ * CY8C6117WI-F34 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -246,42 +246,27 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -297,24 +282,39 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_124_bga.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6136bzi_f14.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6136bzi_f14.h index 79a290e22d..83b74cba7e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6136bzi_f14.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6136bzi_f14.h @@ -5,7 +5,7 @@ * CY8C6136BZI-F14 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -246,42 +246,27 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -294,21 +279,36 @@ typedef enum { #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u #define CY_IP_MXS40PASS_CTDAC_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_124_bga.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6136bzi_f34.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6136bzi_f34.h index 6df5fbb5d4..740a126213 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6136bzi_f34.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6136bzi_f34.h @@ -5,7 +5,7 @@ * CY8C6136BZI-F34 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -246,42 +246,27 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -297,24 +282,39 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_124_bga.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6136fdi_f42.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6136fdi_f42.h index f741e6429f..700f72e079 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6136fdi_f42.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6136fdi_f42.h @@ -5,7 +5,7 @@ * CY8C6136FDI-F42 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -246,33 +246,9 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -282,9 +258,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -297,21 +282,36 @@ typedef enum { #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u #define CY_IP_MXS40PASS_CTDAC_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_80_wlcsp.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6136fti_f42.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6136fti_f42.h index bc0e936923..6018cb0b34 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6136fti_f42.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6136fti_f42.h @@ -5,7 +5,7 @@ * CY8C6136FTI-F42 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -246,33 +246,9 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -282,9 +258,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -297,21 +282,36 @@ typedef enum { #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u #define CY_IP_MXS40PASS_CTDAC_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_80_wlcsp.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137bzi_f14.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137bzi_f14.h index b3914e7747..6493e472b3 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137bzi_f14.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137bzi_f14.h @@ -5,7 +5,7 @@ * CY8C6137BZI-F14 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -246,42 +246,27 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -294,21 +279,36 @@ typedef enum { #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u #define CY_IP_MXS40PASS_CTDAC_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_124_bga.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137bzi_f34.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137bzi_f34.h index 5c5ebf28a2..68b3a21370 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137bzi_f34.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137bzi_f34.h @@ -5,7 +5,7 @@ * CY8C6137BZI-F34 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -246,42 +246,27 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -297,24 +282,39 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_124_bga.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137bzi_f54.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137bzi_f54.h index 1a1252d2ff..d0da1c19ec 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137bzi_f54.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137bzi_f54.h @@ -5,7 +5,7 @@ * CY8C6137BZI-F54 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -246,33 +246,9 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -282,9 +258,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -300,24 +285,39 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_124_bga.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137fdi_f02.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137fdi_f02.h index 2390c26065..be6928993b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137fdi_f02.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137fdi_f02.h @@ -5,7 +5,7 @@ * CY8C6137FDI-F02 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -246,42 +246,27 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -294,21 +279,36 @@ typedef enum { #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u #define CY_IP_MXS40PASS_CTDAC_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_80_wlcsp.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137wi_f54.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137wi_f54.h index ec019e7947..8438299d9d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137wi_f54.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137wi_f54.h @@ -5,7 +5,7 @@ * CY8C6137WI-F54 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -246,33 +246,9 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -282,9 +258,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -300,24 +285,39 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_124_bga.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144azi_s4f12.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144azi_s4f12.h new file mode 100644 index 0000000000..28e9c5d10f --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144azi_s4f12.h @@ -0,0 +1,968 @@ +/***************************************************************************//** +* \file cy8c6144azi_s4f12.h +* +* \brief +* CY8C6144AZI-S4F12 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6144AZI_S4F12_H_ +#define _CY8C6144AZI_S4F12_H_ + +/** +* \addtogroup group_device CY8C6144AZI-S4F12 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6144AZI-S4F12 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */ + pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */ + pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */ + pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */ + pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */ + scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #2 */ + scb_4_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_256_IRQn = 131, /*!< 131 [Active] TCPWM #0, Counter #256 */ + tcpwm_0_interrupts_257_IRQn = 132, /*!< 132 [Active] TCPWM #0, Counter #257 */ + tcpwm_0_interrupts_258_IRQn = 133, /*!< 133 [Active] TCPWM #0, Counter #258 */ + tcpwm_0_interrupts_259_IRQn = 134, /*!< 134 [Active] TCPWM #0, Counter #259 */ + tcpwm_0_interrupts_260_IRQn = 135, /*!< 135 [Active] TCPWM #0, Counter #260 */ + tcpwm_0_interrupts_261_IRQn = 136, /*!< 136 [Active] TCPWM #0, Counter #261 */ + tcpwm_0_interrupts_262_IRQn = 137, /*!< 137 [Active] TCPWM #0, Counter #262 */ + tcpwm_0_interrupts_263_IRQn = 138, /*!< 138 [Active] TCPWM #0, Counter #263 */ + pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + cpuss_interrupts_dw0_29_IRQn = 174, /*!< 174 [Active] CPUSS DataWire #0, Channel #29 */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00020000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00040000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00000000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 6u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u + +#include "psoc6_04_config.h" +#include "gpio_psoc6_04_64_tqfp.h" + +#define CY_DEVICE_PSOC6A256K +#define CY_SILICON_ID 0xEAD2110EUL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_GR11 ((PERI_TR_GR_Type*) &PERI->TR_GR[11]) /* 0x4000AC00 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ +#define PERI_TR_1TO1_GR8 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[8]) /* 0x4000E000 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT0_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT1_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT2_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT3_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT0_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT1_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT2_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT3_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT4_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT5_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT6_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT7_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW0_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[29]) /* 0x40288740 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM0_GRP0 ((TCPWM_GRP_Type*) &TCPWM0->GRP[0]) /* 0x40380000 */ +#define TCPWM0_GRP1 ((TCPWM_GRP_Type*) &TCPWM0->GRP[1]) /* 0x40388000 */ +#define TCPWM0_GRP0_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[0]) /* 0x40380000 */ +#define TCPWM0_GRP0_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[1]) /* 0x40380080 */ +#define TCPWM0_GRP0_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[2]) /* 0x40380100 */ +#define TCPWM0_GRP0_CNT3 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[3]) /* 0x40380180 */ +#define TCPWM0_GRP1_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[0]) /* 0x40388000 */ +#define TCPWM0_GRP1_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[1]) /* 0x40388080 */ +#define TCPWM0_GRP1_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[2]) /* 0x40388100 */ +#define TCPWM0_GRP1_CNT3 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[3]) /* 0x40388180 */ +#define TCPWM0_GRP1_CNT4 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[4]) /* 0x40388200 */ +#define TCPWM0_GRP1_CNT5 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[5]) /* 0x40388280 */ +#define TCPWM0_GRP1_CNT6 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[6]) /* 0x40388300 */ +#define TCPWM0_GRP1_CNT7 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[7]) /* 0x40388380 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* CTBM +*******************************************************************************/ + +#define CTBM0_BASE 0x40900000UL +#define CTBM0 ((CTBM_Type*) CTBM0_BASE) /* 0x40900000 */ + +/******************************************************************************* +* CTDAC +*******************************************************************************/ + +#define CTDAC0_BASE 0x40940000UL +#define CTDAC0 ((CTDAC_Type*) CTDAC0_BASE) /* 0x40940000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR0_BASE 0x409B0000UL +#define SAR0 ((SAR_Type*) SAR0_BASE) /* 0x409B0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_TIMER ((PASS_TIMER_Type*) &PASS->TIMER) /* 0x409F0100 */ +#define PASS_LPOSC ((PASS_LPOSC_Type*) &PASS->LPOSC) /* 0x409F0200 */ +#define PASS_FIFO0 ((PASS_FIFO_Type*) &PASS->FIFO[0]) /* 0x409F0300 */ +#define PASS_FIFO1 ((PASS_FIFO_Type*) &PASS->FIFO[1]) /* 0x409F0400 */ +#define PASS_AREFV2 ((PASS_AREFV2_Type*) &PASS->AREFV2) /* 0x409F0E00 */ + +/** \} CY8C6144AZI-S4F12 */ + +#endif /* _CY8C6144AZI_S4F12_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144azi_s4f62.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144azi_s4f62.h new file mode 100644 index 0000000000..753a7435d5 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144azi_s4f62.h @@ -0,0 +1,968 @@ +/***************************************************************************//** +* \file cy8c6144azi_s4f62.h +* +* \brief +* CY8C6144AZI-S4F62 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6144AZI_S4F62_H_ +#define _CY8C6144AZI_S4F62_H_ + +/** +* \addtogroup group_device CY8C6144AZI-S4F62 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6144AZI-S4F62 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */ + pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */ + pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */ + pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */ + pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */ + scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #2 */ + scb_4_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_256_IRQn = 131, /*!< 131 [Active] TCPWM #0, Counter #256 */ + tcpwm_0_interrupts_257_IRQn = 132, /*!< 132 [Active] TCPWM #0, Counter #257 */ + tcpwm_0_interrupts_258_IRQn = 133, /*!< 133 [Active] TCPWM #0, Counter #258 */ + tcpwm_0_interrupts_259_IRQn = 134, /*!< 134 [Active] TCPWM #0, Counter #259 */ + tcpwm_0_interrupts_260_IRQn = 135, /*!< 135 [Active] TCPWM #0, Counter #260 */ + tcpwm_0_interrupts_261_IRQn = 136, /*!< 136 [Active] TCPWM #0, Counter #261 */ + tcpwm_0_interrupts_262_IRQn = 137, /*!< 137 [Active] TCPWM #0, Counter #262 */ + tcpwm_0_interrupts_263_IRQn = 138, /*!< 138 [Active] TCPWM #0, Counter #263 */ + pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + cpuss_interrupts_dw0_29_IRQn = 174, /*!< 174 [Active] CPUSS DataWire #0, Channel #29 */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00020000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00040000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00000000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 6u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u + +#include "psoc6_04_config.h" +#include "gpio_psoc6_04_64_tqfp.h" + +#define CY_DEVICE_PSOC6A256K +#define CY_SILICON_ID 0xEAD0110EUL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_GR11 ((PERI_TR_GR_Type*) &PERI->TR_GR[11]) /* 0x4000AC00 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ +#define PERI_TR_1TO1_GR8 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[8]) /* 0x4000E000 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT0_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT1_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT2_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT3_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT0_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT1_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT2_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT3_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT4_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT5_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT6_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT7_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW0_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[29]) /* 0x40288740 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM0_GRP0 ((TCPWM_GRP_Type*) &TCPWM0->GRP[0]) /* 0x40380000 */ +#define TCPWM0_GRP1 ((TCPWM_GRP_Type*) &TCPWM0->GRP[1]) /* 0x40388000 */ +#define TCPWM0_GRP0_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[0]) /* 0x40380000 */ +#define TCPWM0_GRP0_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[1]) /* 0x40380080 */ +#define TCPWM0_GRP0_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[2]) /* 0x40380100 */ +#define TCPWM0_GRP0_CNT3 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[3]) /* 0x40380180 */ +#define TCPWM0_GRP1_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[0]) /* 0x40388000 */ +#define TCPWM0_GRP1_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[1]) /* 0x40388080 */ +#define TCPWM0_GRP1_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[2]) /* 0x40388100 */ +#define TCPWM0_GRP1_CNT3 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[3]) /* 0x40388180 */ +#define TCPWM0_GRP1_CNT4 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[4]) /* 0x40388200 */ +#define TCPWM0_GRP1_CNT5 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[5]) /* 0x40388280 */ +#define TCPWM0_GRP1_CNT6 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[6]) /* 0x40388300 */ +#define TCPWM0_GRP1_CNT7 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[7]) /* 0x40388380 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* CTBM +*******************************************************************************/ + +#define CTBM0_BASE 0x40900000UL +#define CTBM0 ((CTBM_Type*) CTBM0_BASE) /* 0x40900000 */ + +/******************************************************************************* +* CTDAC +*******************************************************************************/ + +#define CTDAC0_BASE 0x40940000UL +#define CTDAC0 ((CTDAC_Type*) CTDAC0_BASE) /* 0x40940000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR0_BASE 0x409B0000UL +#define SAR0 ((SAR_Type*) SAR0_BASE) /* 0x409B0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_TIMER ((PASS_TIMER_Type*) &PASS->TIMER) /* 0x409F0100 */ +#define PASS_LPOSC ((PASS_LPOSC_Type*) &PASS->LPOSC) /* 0x409F0200 */ +#define PASS_FIFO0 ((PASS_FIFO_Type*) &PASS->FIFO[0]) /* 0x409F0300 */ +#define PASS_FIFO1 ((PASS_FIFO_Type*) &PASS->FIFO[1]) /* 0x409F0400 */ +#define PASS_AREFV2 ((PASS_AREFV2_Type*) &PASS->AREFV2) /* 0x409F0E00 */ + +/** \} CY8C6144AZI-S4F62 */ + +#endif /* _CY8C6144AZI_S4F62_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144azi_s4f82.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144azi_s4f82.h new file mode 100644 index 0000000000..af9b146ac2 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144azi_s4f82.h @@ -0,0 +1,980 @@ +/***************************************************************************//** +* \file cy8c6144azi_s4f82.h +* +* \brief +* CY8C6144AZI-S4F82 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6144AZI_S4F82_H_ +#define _CY8C6144AZI_S4F82_H_ + +/** +* \addtogroup group_device CY8C6144AZI-S4F82 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6144AZI-S4F82 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */ + pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */ + pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */ + pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */ + pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */ + scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #2 */ + scb_4_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_256_IRQn = 131, /*!< 131 [Active] TCPWM #0, Counter #256 */ + tcpwm_0_interrupts_257_IRQn = 132, /*!< 132 [Active] TCPWM #0, Counter #257 */ + tcpwm_0_interrupts_258_IRQn = 133, /*!< 133 [Active] TCPWM #0, Counter #258 */ + tcpwm_0_interrupts_259_IRQn = 134, /*!< 134 [Active] TCPWM #0, Counter #259 */ + tcpwm_0_interrupts_260_IRQn = 135, /*!< 135 [Active] TCPWM #0, Counter #260 */ + tcpwm_0_interrupts_261_IRQn = 136, /*!< 136 [Active] TCPWM #0, Counter #261 */ + tcpwm_0_interrupts_262_IRQn = 137, /*!< 137 [Active] TCPWM #0, Counter #262 */ + tcpwm_0_interrupts_263_IRQn = 138, /*!< 138 [Active] TCPWM #0, Counter #263 */ + pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + cpuss_interrupts_dw0_29_IRQn = 174, /*!< 174 [Active] CPUSS DataWire #0, Channel #29 */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00020000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00040000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00000000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 6u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u + +#include "psoc6_04_config.h" +#include "gpio_psoc6_04_64_tqfp.h" + +#define CY_DEVICE_PSOC6A256K +#define CY_SILICON_ID 0xEACD110EUL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_GR11 ((PERI_TR_GR_Type*) &PERI->TR_GR[11]) /* 0x4000AC00 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ +#define PERI_TR_1TO1_GR8 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[8]) /* 0x4000E000 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT0_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT1_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT2_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT3_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT0_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT1_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT2_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT3_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT4_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT5_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT6_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT7_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40100000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40100000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW0_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[29]) /* 0x40288740 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM0_GRP0 ((TCPWM_GRP_Type*) &TCPWM0->GRP[0]) /* 0x40380000 */ +#define TCPWM0_GRP1 ((TCPWM_GRP_Type*) &TCPWM0->GRP[1]) /* 0x40388000 */ +#define TCPWM0_GRP0_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[0]) /* 0x40380000 */ +#define TCPWM0_GRP0_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[1]) /* 0x40380080 */ +#define TCPWM0_GRP0_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[2]) /* 0x40380100 */ +#define TCPWM0_GRP0_CNT3 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[3]) /* 0x40380180 */ +#define TCPWM0_GRP1_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[0]) /* 0x40388000 */ +#define TCPWM0_GRP1_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[1]) /* 0x40388080 */ +#define TCPWM0_GRP1_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[2]) /* 0x40388100 */ +#define TCPWM0_GRP1_CNT3 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[3]) /* 0x40388180 */ +#define TCPWM0_GRP1_CNT4 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[4]) /* 0x40388200 */ +#define TCPWM0_GRP1_CNT5 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[5]) /* 0x40388280 */ +#define TCPWM0_GRP1_CNT6 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[6]) /* 0x40388300 */ +#define TCPWM0_GRP1_CNT7 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[7]) /* 0x40388380 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* CTBM +*******************************************************************************/ + +#define CTBM0_BASE 0x40900000UL +#define CTBM0 ((CTBM_Type*) CTBM0_BASE) /* 0x40900000 */ + +/******************************************************************************* +* CTDAC +*******************************************************************************/ + +#define CTDAC0_BASE 0x40940000UL +#define CTDAC0 ((CTDAC_Type*) CTDAC0_BASE) /* 0x40940000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR0_BASE 0x409B0000UL +#define SAR1_BASE 0x409C0000UL +#define SAR0 ((SAR_Type*) SAR0_BASE) /* 0x409B0000 */ +#define SAR1 ((SAR_Type*) SAR1_BASE) /* 0x409C0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_TIMER ((PASS_TIMER_Type*) &PASS->TIMER) /* 0x409F0100 */ +#define PASS_LPOSC ((PASS_LPOSC_Type*) &PASS->LPOSC) /* 0x409F0200 */ +#define PASS_FIFO0 ((PASS_FIFO_Type*) &PASS->FIFO[0]) /* 0x409F0300 */ +#define PASS_FIFO1 ((PASS_FIFO_Type*) &PASS->FIFO[1]) /* 0x409F0400 */ +#define PASS_AREFV2 ((PASS_AREFV2_Type*) &PASS->AREFV2) /* 0x409F0E00 */ + +/** \} CY8C6144AZI-S4F82 */ + +#endif /* _CY8C6144AZI_S4F82_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144azi_s4f83.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144azi_s4f83.h new file mode 100644 index 0000000000..18c8aeb1d1 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144azi_s4f83.h @@ -0,0 +1,980 @@ +/***************************************************************************//** +* \file cy8c6144azi_s4f83.h +* +* \brief +* CY8C6144AZI-S4F83 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6144AZI_S4F83_H_ +#define _CY8C6144AZI_S4F83_H_ + +/** +* \addtogroup group_device CY8C6144AZI-S4F83 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6144AZI-S4F83 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */ + pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */ + pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */ + pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */ + pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */ + scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #2 */ + scb_4_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_256_IRQn = 131, /*!< 131 [Active] TCPWM #0, Counter #256 */ + tcpwm_0_interrupts_257_IRQn = 132, /*!< 132 [Active] TCPWM #0, Counter #257 */ + tcpwm_0_interrupts_258_IRQn = 133, /*!< 133 [Active] TCPWM #0, Counter #258 */ + tcpwm_0_interrupts_259_IRQn = 134, /*!< 134 [Active] TCPWM #0, Counter #259 */ + tcpwm_0_interrupts_260_IRQn = 135, /*!< 135 [Active] TCPWM #0, Counter #260 */ + tcpwm_0_interrupts_261_IRQn = 136, /*!< 136 [Active] TCPWM #0, Counter #261 */ + tcpwm_0_interrupts_262_IRQn = 137, /*!< 137 [Active] TCPWM #0, Counter #262 */ + tcpwm_0_interrupts_263_IRQn = 138, /*!< 138 [Active] TCPWM #0, Counter #263 */ + pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + cpuss_interrupts_dw0_29_IRQn = 174, /*!< 174 [Active] CPUSS DataWire #0, Channel #29 */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00020000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00040000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00000000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 6u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u + +#include "psoc6_04_config.h" +#include "gpio_psoc6_04_80_tqfp.h" + +#define CY_DEVICE_PSOC6A256K +#define CY_SILICON_ID 0xEACF110EUL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_GR11 ((PERI_TR_GR_Type*) &PERI->TR_GR[11]) /* 0x4000AC00 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ +#define PERI_TR_1TO1_GR8 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[8]) /* 0x4000E000 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT0_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT1_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT2_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT3_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT0_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT1_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT2_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT3_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT4_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT5_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT6_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT7_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40100000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40100000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW0_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[29]) /* 0x40288740 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM0_GRP0 ((TCPWM_GRP_Type*) &TCPWM0->GRP[0]) /* 0x40380000 */ +#define TCPWM0_GRP1 ((TCPWM_GRP_Type*) &TCPWM0->GRP[1]) /* 0x40388000 */ +#define TCPWM0_GRP0_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[0]) /* 0x40380000 */ +#define TCPWM0_GRP0_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[1]) /* 0x40380080 */ +#define TCPWM0_GRP0_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[2]) /* 0x40380100 */ +#define TCPWM0_GRP0_CNT3 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[3]) /* 0x40380180 */ +#define TCPWM0_GRP1_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[0]) /* 0x40388000 */ +#define TCPWM0_GRP1_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[1]) /* 0x40388080 */ +#define TCPWM0_GRP1_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[2]) /* 0x40388100 */ +#define TCPWM0_GRP1_CNT3 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[3]) /* 0x40388180 */ +#define TCPWM0_GRP1_CNT4 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[4]) /* 0x40388200 */ +#define TCPWM0_GRP1_CNT5 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[5]) /* 0x40388280 */ +#define TCPWM0_GRP1_CNT6 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[6]) /* 0x40388300 */ +#define TCPWM0_GRP1_CNT7 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[7]) /* 0x40388380 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* CTBM +*******************************************************************************/ + +#define CTBM0_BASE 0x40900000UL +#define CTBM0 ((CTBM_Type*) CTBM0_BASE) /* 0x40900000 */ + +/******************************************************************************* +* CTDAC +*******************************************************************************/ + +#define CTDAC0_BASE 0x40940000UL +#define CTDAC0 ((CTDAC_Type*) CTDAC0_BASE) /* 0x40940000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR0_BASE 0x409B0000UL +#define SAR1_BASE 0x409C0000UL +#define SAR0 ((SAR_Type*) SAR0_BASE) /* 0x409B0000 */ +#define SAR1 ((SAR_Type*) SAR1_BASE) /* 0x409C0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_TIMER ((PASS_TIMER_Type*) &PASS->TIMER) /* 0x409F0100 */ +#define PASS_LPOSC ((PASS_LPOSC_Type*) &PASS->LPOSC) /* 0x409F0200 */ +#define PASS_FIFO0 ((PASS_FIFO_Type*) &PASS->FIFO[0]) /* 0x409F0300 */ +#define PASS_FIFO1 ((PASS_FIFO_Type*) &PASS->FIFO[1]) /* 0x409F0400 */ +#define PASS_AREFV2 ((PASS_AREFV2_Type*) &PASS->AREFV2) /* 0x409F0E00 */ + +/** \} CY8C6144AZI-S4F83 */ + +#endif /* _CY8C6144AZI_S4F83_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144azi_s4f92.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144azi_s4f92.h new file mode 100644 index 0000000000..d140945ba0 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144azi_s4f92.h @@ -0,0 +1,980 @@ +/***************************************************************************//** +* \file cy8c6144azi_s4f92.h +* +* \brief +* CY8C6144AZI-S4F92 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6144AZI_S4F92_H_ +#define _CY8C6144AZI_S4F92_H_ + +/** +* \addtogroup group_device CY8C6144AZI-S4F92 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6144AZI-S4F92 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */ + pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */ + pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */ + pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */ + pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */ + scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #2 */ + scb_4_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_256_IRQn = 131, /*!< 131 [Active] TCPWM #0, Counter #256 */ + tcpwm_0_interrupts_257_IRQn = 132, /*!< 132 [Active] TCPWM #0, Counter #257 */ + tcpwm_0_interrupts_258_IRQn = 133, /*!< 133 [Active] TCPWM #0, Counter #258 */ + tcpwm_0_interrupts_259_IRQn = 134, /*!< 134 [Active] TCPWM #0, Counter #259 */ + tcpwm_0_interrupts_260_IRQn = 135, /*!< 135 [Active] TCPWM #0, Counter #260 */ + tcpwm_0_interrupts_261_IRQn = 136, /*!< 136 [Active] TCPWM #0, Counter #261 */ + tcpwm_0_interrupts_262_IRQn = 137, /*!< 137 [Active] TCPWM #0, Counter #262 */ + tcpwm_0_interrupts_263_IRQn = 138, /*!< 138 [Active] TCPWM #0, Counter #263 */ + pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + cpuss_interrupts_dw0_29_IRQn = 174, /*!< 174 [Active] CPUSS DataWire #0, Channel #29 */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00020000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00040000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00000000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 6u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u + +#include "psoc6_04_config.h" +#include "gpio_psoc6_04_64_tqfp.h" + +#define CY_DEVICE_PSOC6A256K +#define CY_SILICON_ID 0xEACA110EUL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_GR11 ((PERI_TR_GR_Type*) &PERI->TR_GR[11]) /* 0x4000AC00 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ +#define PERI_TR_1TO1_GR8 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[8]) /* 0x4000E000 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT0_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT1_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT2_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT3_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT0_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT1_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT2_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT3_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT4_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT5_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT6_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT7_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40100000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40100000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW0_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[29]) /* 0x40288740 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM0_GRP0 ((TCPWM_GRP_Type*) &TCPWM0->GRP[0]) /* 0x40380000 */ +#define TCPWM0_GRP1 ((TCPWM_GRP_Type*) &TCPWM0->GRP[1]) /* 0x40388000 */ +#define TCPWM0_GRP0_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[0]) /* 0x40380000 */ +#define TCPWM0_GRP0_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[1]) /* 0x40380080 */ +#define TCPWM0_GRP0_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[2]) /* 0x40380100 */ +#define TCPWM0_GRP0_CNT3 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[3]) /* 0x40380180 */ +#define TCPWM0_GRP1_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[0]) /* 0x40388000 */ +#define TCPWM0_GRP1_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[1]) /* 0x40388080 */ +#define TCPWM0_GRP1_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[2]) /* 0x40388100 */ +#define TCPWM0_GRP1_CNT3 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[3]) /* 0x40388180 */ +#define TCPWM0_GRP1_CNT4 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[4]) /* 0x40388200 */ +#define TCPWM0_GRP1_CNT5 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[5]) /* 0x40388280 */ +#define TCPWM0_GRP1_CNT6 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[6]) /* 0x40388300 */ +#define TCPWM0_GRP1_CNT7 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[7]) /* 0x40388380 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* CTBM +*******************************************************************************/ + +#define CTBM0_BASE 0x40900000UL +#define CTBM0 ((CTBM_Type*) CTBM0_BASE) /* 0x40900000 */ + +/******************************************************************************* +* CTDAC +*******************************************************************************/ + +#define CTDAC0_BASE 0x40940000UL +#define CTDAC0 ((CTDAC_Type*) CTDAC0_BASE) /* 0x40940000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR0_BASE 0x409B0000UL +#define SAR1_BASE 0x409C0000UL +#define SAR0 ((SAR_Type*) SAR0_BASE) /* 0x409B0000 */ +#define SAR1 ((SAR_Type*) SAR1_BASE) /* 0x409C0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_TIMER ((PASS_TIMER_Type*) &PASS->TIMER) /* 0x409F0100 */ +#define PASS_LPOSC ((PASS_LPOSC_Type*) &PASS->LPOSC) /* 0x409F0200 */ +#define PASS_FIFO0 ((PASS_FIFO_Type*) &PASS->FIFO[0]) /* 0x409F0300 */ +#define PASS_FIFO1 ((PASS_FIFO_Type*) &PASS->FIFO[1]) /* 0x409F0400 */ +#define PASS_AREFV2 ((PASS_AREFV2_Type*) &PASS->AREFV2) /* 0x409F0E00 */ + +/** \} CY8C6144AZI-S4F92 */ + +#endif /* _CY8C6144AZI_S4F92_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144azi_s4f93.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144azi_s4f93.h new file mode 100644 index 0000000000..54d3551a8c --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144azi_s4f93.h @@ -0,0 +1,980 @@ +/***************************************************************************//** +* \file cy8c6144azi_s4f93.h +* +* \brief +* CY8C6144AZI-S4F93 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6144AZI_S4F93_H_ +#define _CY8C6144AZI_S4F93_H_ + +/** +* \addtogroup group_device CY8C6144AZI-S4F93 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6144AZI-S4F93 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */ + pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */ + pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */ + pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */ + pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */ + scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #2 */ + scb_4_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_256_IRQn = 131, /*!< 131 [Active] TCPWM #0, Counter #256 */ + tcpwm_0_interrupts_257_IRQn = 132, /*!< 132 [Active] TCPWM #0, Counter #257 */ + tcpwm_0_interrupts_258_IRQn = 133, /*!< 133 [Active] TCPWM #0, Counter #258 */ + tcpwm_0_interrupts_259_IRQn = 134, /*!< 134 [Active] TCPWM #0, Counter #259 */ + tcpwm_0_interrupts_260_IRQn = 135, /*!< 135 [Active] TCPWM #0, Counter #260 */ + tcpwm_0_interrupts_261_IRQn = 136, /*!< 136 [Active] TCPWM #0, Counter #261 */ + tcpwm_0_interrupts_262_IRQn = 137, /*!< 137 [Active] TCPWM #0, Counter #262 */ + tcpwm_0_interrupts_263_IRQn = 138, /*!< 138 [Active] TCPWM #0, Counter #263 */ + pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + cpuss_interrupts_dw0_29_IRQn = 174, /*!< 174 [Active] CPUSS DataWire #0, Channel #29 */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00020000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00040000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00000000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 6u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u + +#include "psoc6_04_config.h" +#include "gpio_psoc6_04_80_tqfp.h" + +#define CY_DEVICE_PSOC6A256K +#define CY_SILICON_ID 0xEACC110EUL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_GR11 ((PERI_TR_GR_Type*) &PERI->TR_GR[11]) /* 0x4000AC00 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ +#define PERI_TR_1TO1_GR8 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[8]) /* 0x4000E000 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT0_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT1_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT2_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT3_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT0_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT1_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT2_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT3_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT4_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT5_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT6_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT7_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40100000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40100000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW0_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[29]) /* 0x40288740 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM0_GRP0 ((TCPWM_GRP_Type*) &TCPWM0->GRP[0]) /* 0x40380000 */ +#define TCPWM0_GRP1 ((TCPWM_GRP_Type*) &TCPWM0->GRP[1]) /* 0x40388000 */ +#define TCPWM0_GRP0_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[0]) /* 0x40380000 */ +#define TCPWM0_GRP0_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[1]) /* 0x40380080 */ +#define TCPWM0_GRP0_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[2]) /* 0x40380100 */ +#define TCPWM0_GRP0_CNT3 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[3]) /* 0x40380180 */ +#define TCPWM0_GRP1_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[0]) /* 0x40388000 */ +#define TCPWM0_GRP1_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[1]) /* 0x40388080 */ +#define TCPWM0_GRP1_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[2]) /* 0x40388100 */ +#define TCPWM0_GRP1_CNT3 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[3]) /* 0x40388180 */ +#define TCPWM0_GRP1_CNT4 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[4]) /* 0x40388200 */ +#define TCPWM0_GRP1_CNT5 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[5]) /* 0x40388280 */ +#define TCPWM0_GRP1_CNT6 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[6]) /* 0x40388300 */ +#define TCPWM0_GRP1_CNT7 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[7]) /* 0x40388380 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* CTBM +*******************************************************************************/ + +#define CTBM0_BASE 0x40900000UL +#define CTBM0 ((CTBM_Type*) CTBM0_BASE) /* 0x40900000 */ + +/******************************************************************************* +* CTDAC +*******************************************************************************/ + +#define CTDAC0_BASE 0x40940000UL +#define CTDAC0 ((CTDAC_Type*) CTDAC0_BASE) /* 0x40940000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR0_BASE 0x409B0000UL +#define SAR1_BASE 0x409C0000UL +#define SAR0 ((SAR_Type*) SAR0_BASE) /* 0x409B0000 */ +#define SAR1 ((SAR_Type*) SAR1_BASE) /* 0x409C0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_TIMER ((PASS_TIMER_Type*) &PASS->TIMER) /* 0x409F0100 */ +#define PASS_LPOSC ((PASS_LPOSC_Type*) &PASS->LPOSC) /* 0x409F0200 */ +#define PASS_FIFO0 ((PASS_FIFO_Type*) &PASS->FIFO[0]) /* 0x409F0300 */ +#define PASS_FIFO1 ((PASS_FIFO_Type*) &PASS->FIFO[1]) /* 0x409F0400 */ +#define PASS_AREFV2 ((PASS_AREFV2_Type*) &PASS->AREFV2) /* 0x409F0E00 */ + +/** \} CY8C6144AZI-S4F93 */ + +#endif /* _CY8C6144AZI_S4F93_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144lqi_s4f12.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144lqi_s4f12.h new file mode 100644 index 0000000000..bf9e69cc64 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144lqi_s4f12.h @@ -0,0 +1,981 @@ +/***************************************************************************//** +* \file cy8c6144lqi_s4f12.h +* +* \brief +* CY8C6144LQI-S4F12 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6144LQI_S4F12_H_ +#define _CY8C6144LQI_S4F12_H_ + +/** +* \addtogroup group_device CY8C6144LQI-S4F12 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6144LQI-S4F12 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */ + pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */ + pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */ + pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */ + pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */ + scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #2 */ + scb_4_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_256_IRQn = 131, /*!< 131 [Active] TCPWM #0, Counter #256 */ + tcpwm_0_interrupts_257_IRQn = 132, /*!< 132 [Active] TCPWM #0, Counter #257 */ + tcpwm_0_interrupts_258_IRQn = 133, /*!< 133 [Active] TCPWM #0, Counter #258 */ + tcpwm_0_interrupts_259_IRQn = 134, /*!< 134 [Active] TCPWM #0, Counter #259 */ + tcpwm_0_interrupts_260_IRQn = 135, /*!< 135 [Active] TCPWM #0, Counter #260 */ + tcpwm_0_interrupts_261_IRQn = 136, /*!< 136 [Active] TCPWM #0, Counter #261 */ + tcpwm_0_interrupts_262_IRQn = 137, /*!< 137 [Active] TCPWM #0, Counter #262 */ + tcpwm_0_interrupts_263_IRQn = 138, /*!< 138 [Active] TCPWM #0, Counter #263 */ + pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + cpuss_interrupts_dw0_29_IRQn = 174, /*!< 174 [Active] CPUSS DataWire #0, Channel #29 */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00020000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00040000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00000000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 6u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u + +#include "psoc6_04_config.h" +#include "gpio_psoc6_04_68_qfn.h" + +#define CY_DEVICE_PSOC6A256K +#define CY_SILICON_ID 0xEAD3110EUL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_GR11 ((PERI_TR_GR_Type*) &PERI->TR_GR[11]) /* 0x4000AC00 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ +#define PERI_TR_1TO1_GR8 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[8]) /* 0x4000E000 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT0_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT1_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT2_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT3_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT0_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT1_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT2_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT3_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT4_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT5_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT6_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT7_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW0_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[29]) /* 0x40288740 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM0_GRP0 ((TCPWM_GRP_Type*) &TCPWM0->GRP[0]) /* 0x40380000 */ +#define TCPWM0_GRP1 ((TCPWM_GRP_Type*) &TCPWM0->GRP[1]) /* 0x40388000 */ +#define TCPWM0_GRP0_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[0]) /* 0x40380000 */ +#define TCPWM0_GRP0_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[1]) /* 0x40380080 */ +#define TCPWM0_GRP0_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[2]) /* 0x40380100 */ +#define TCPWM0_GRP0_CNT3 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[3]) /* 0x40380180 */ +#define TCPWM0_GRP1_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[0]) /* 0x40388000 */ +#define TCPWM0_GRP1_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[1]) /* 0x40388080 */ +#define TCPWM0_GRP1_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[2]) /* 0x40388100 */ +#define TCPWM0_GRP1_CNT3 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[3]) /* 0x40388180 */ +#define TCPWM0_GRP1_CNT4 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[4]) /* 0x40388200 */ +#define TCPWM0_GRP1_CNT5 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[5]) /* 0x40388280 */ +#define TCPWM0_GRP1_CNT6 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[6]) /* 0x40388300 */ +#define TCPWM0_GRP1_CNT7 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[7]) /* 0x40388380 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* CTBM +*******************************************************************************/ + +#define CTBM0_BASE 0x40900000UL +#define CTBM0 ((CTBM_Type*) CTBM0_BASE) /* 0x40900000 */ + +/******************************************************************************* +* CTDAC +*******************************************************************************/ + +#define CTDAC0_BASE 0x40940000UL +#define CTDAC0 ((CTDAC_Type*) CTDAC0_BASE) /* 0x40940000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR0_BASE 0x409B0000UL +#define SAR0 ((SAR_Type*) SAR0_BASE) /* 0x409B0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_TIMER ((PASS_TIMER_Type*) &PASS->TIMER) /* 0x409F0100 */ +#define PASS_LPOSC ((PASS_LPOSC_Type*) &PASS->LPOSC) /* 0x409F0200 */ +#define PASS_FIFO0 ((PASS_FIFO_Type*) &PASS->FIFO[0]) /* 0x409F0300 */ +#define PASS_FIFO1 ((PASS_FIFO_Type*) &PASS->FIFO[1]) /* 0x409F0400 */ +#define PASS_AREFV2 ((PASS_AREFV2_Type*) &PASS->AREFV2) /* 0x409F0E00 */ + +/** \} CY8C6144LQI-S4F12 */ + +#endif /* _CY8C6144LQI_S4F12_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144lqi_s4f62.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144lqi_s4f62.h new file mode 100644 index 0000000000..d2a6a3c812 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144lqi_s4f62.h @@ -0,0 +1,981 @@ +/***************************************************************************//** +* \file cy8c6144lqi_s4f62.h +* +* \brief +* CY8C6144LQI-S4F62 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6144LQI_S4F62_H_ +#define _CY8C6144LQI_S4F62_H_ + +/** +* \addtogroup group_device CY8C6144LQI-S4F62 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6144LQI-S4F62 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */ + pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */ + pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */ + pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */ + pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */ + scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #2 */ + scb_4_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_256_IRQn = 131, /*!< 131 [Active] TCPWM #0, Counter #256 */ + tcpwm_0_interrupts_257_IRQn = 132, /*!< 132 [Active] TCPWM #0, Counter #257 */ + tcpwm_0_interrupts_258_IRQn = 133, /*!< 133 [Active] TCPWM #0, Counter #258 */ + tcpwm_0_interrupts_259_IRQn = 134, /*!< 134 [Active] TCPWM #0, Counter #259 */ + tcpwm_0_interrupts_260_IRQn = 135, /*!< 135 [Active] TCPWM #0, Counter #260 */ + tcpwm_0_interrupts_261_IRQn = 136, /*!< 136 [Active] TCPWM #0, Counter #261 */ + tcpwm_0_interrupts_262_IRQn = 137, /*!< 137 [Active] TCPWM #0, Counter #262 */ + tcpwm_0_interrupts_263_IRQn = 138, /*!< 138 [Active] TCPWM #0, Counter #263 */ + pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + cpuss_interrupts_dw0_29_IRQn = 174, /*!< 174 [Active] CPUSS DataWire #0, Channel #29 */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00020000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00040000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00000000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 6u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u + +#include "psoc6_04_config.h" +#include "gpio_psoc6_04_68_qfn.h" + +#define CY_DEVICE_PSOC6A256K +#define CY_SILICON_ID 0xEAD1110EUL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_GR11 ((PERI_TR_GR_Type*) &PERI->TR_GR[11]) /* 0x4000AC00 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ +#define PERI_TR_1TO1_GR8 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[8]) /* 0x4000E000 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT0_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT1_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT2_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT3_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT0_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT1_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT2_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT3_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT4_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT5_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT6_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT7_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW0_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[29]) /* 0x40288740 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM0_GRP0 ((TCPWM_GRP_Type*) &TCPWM0->GRP[0]) /* 0x40380000 */ +#define TCPWM0_GRP1 ((TCPWM_GRP_Type*) &TCPWM0->GRP[1]) /* 0x40388000 */ +#define TCPWM0_GRP0_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[0]) /* 0x40380000 */ +#define TCPWM0_GRP0_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[1]) /* 0x40380080 */ +#define TCPWM0_GRP0_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[2]) /* 0x40380100 */ +#define TCPWM0_GRP0_CNT3 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[3]) /* 0x40380180 */ +#define TCPWM0_GRP1_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[0]) /* 0x40388000 */ +#define TCPWM0_GRP1_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[1]) /* 0x40388080 */ +#define TCPWM0_GRP1_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[2]) /* 0x40388100 */ +#define TCPWM0_GRP1_CNT3 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[3]) /* 0x40388180 */ +#define TCPWM0_GRP1_CNT4 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[4]) /* 0x40388200 */ +#define TCPWM0_GRP1_CNT5 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[5]) /* 0x40388280 */ +#define TCPWM0_GRP1_CNT6 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[6]) /* 0x40388300 */ +#define TCPWM0_GRP1_CNT7 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[7]) /* 0x40388380 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* CTBM +*******************************************************************************/ + +#define CTBM0_BASE 0x40900000UL +#define CTBM0 ((CTBM_Type*) CTBM0_BASE) /* 0x40900000 */ + +/******************************************************************************* +* CTDAC +*******************************************************************************/ + +#define CTDAC0_BASE 0x40940000UL +#define CTDAC0 ((CTDAC_Type*) CTDAC0_BASE) /* 0x40940000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR0_BASE 0x409B0000UL +#define SAR0 ((SAR_Type*) SAR0_BASE) /* 0x409B0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_TIMER ((PASS_TIMER_Type*) &PASS->TIMER) /* 0x409F0100 */ +#define PASS_LPOSC ((PASS_LPOSC_Type*) &PASS->LPOSC) /* 0x409F0200 */ +#define PASS_FIFO0 ((PASS_FIFO_Type*) &PASS->FIFO[0]) /* 0x409F0300 */ +#define PASS_FIFO1 ((PASS_FIFO_Type*) &PASS->FIFO[1]) /* 0x409F0400 */ +#define PASS_AREFV2 ((PASS_AREFV2_Type*) &PASS->AREFV2) /* 0x409F0E00 */ + +/** \} CY8C6144LQI-S4F62 */ + +#endif /* _CY8C6144LQI_S4F62_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144lqi_s4f82.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144lqi_s4f82.h new file mode 100644 index 0000000000..86c856b2b4 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144lqi_s4f82.h @@ -0,0 +1,993 @@ +/***************************************************************************//** +* \file cy8c6144lqi_s4f82.h +* +* \brief +* CY8C6144LQI-S4F82 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6144LQI_S4F82_H_ +#define _CY8C6144LQI_S4F82_H_ + +/** +* \addtogroup group_device CY8C6144LQI-S4F82 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6144LQI-S4F82 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */ + pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */ + pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */ + pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */ + pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */ + scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #2 */ + scb_4_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_256_IRQn = 131, /*!< 131 [Active] TCPWM #0, Counter #256 */ + tcpwm_0_interrupts_257_IRQn = 132, /*!< 132 [Active] TCPWM #0, Counter #257 */ + tcpwm_0_interrupts_258_IRQn = 133, /*!< 133 [Active] TCPWM #0, Counter #258 */ + tcpwm_0_interrupts_259_IRQn = 134, /*!< 134 [Active] TCPWM #0, Counter #259 */ + tcpwm_0_interrupts_260_IRQn = 135, /*!< 135 [Active] TCPWM #0, Counter #260 */ + tcpwm_0_interrupts_261_IRQn = 136, /*!< 136 [Active] TCPWM #0, Counter #261 */ + tcpwm_0_interrupts_262_IRQn = 137, /*!< 137 [Active] TCPWM #0, Counter #262 */ + tcpwm_0_interrupts_263_IRQn = 138, /*!< 138 [Active] TCPWM #0, Counter #263 */ + pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + cpuss_interrupts_dw0_29_IRQn = 174, /*!< 174 [Active] CPUSS DataWire #0, Channel #29 */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00020000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00040000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00000000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 6u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u + +#include "psoc6_04_config.h" +#include "gpio_psoc6_04_68_qfn.h" + +#define CY_DEVICE_PSOC6A256K +#define CY_SILICON_ID 0xEACE110EUL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_GR11 ((PERI_TR_GR_Type*) &PERI->TR_GR[11]) /* 0x4000AC00 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ +#define PERI_TR_1TO1_GR8 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[8]) /* 0x4000E000 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT0_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT1_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT2_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT3_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT0_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT1_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT2_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT3_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT4_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT5_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT6_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT7_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40100000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40100000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW0_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[29]) /* 0x40288740 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM0_GRP0 ((TCPWM_GRP_Type*) &TCPWM0->GRP[0]) /* 0x40380000 */ +#define TCPWM0_GRP1 ((TCPWM_GRP_Type*) &TCPWM0->GRP[1]) /* 0x40388000 */ +#define TCPWM0_GRP0_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[0]) /* 0x40380000 */ +#define TCPWM0_GRP0_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[1]) /* 0x40380080 */ +#define TCPWM0_GRP0_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[2]) /* 0x40380100 */ +#define TCPWM0_GRP0_CNT3 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[3]) /* 0x40380180 */ +#define TCPWM0_GRP1_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[0]) /* 0x40388000 */ +#define TCPWM0_GRP1_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[1]) /* 0x40388080 */ +#define TCPWM0_GRP1_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[2]) /* 0x40388100 */ +#define TCPWM0_GRP1_CNT3 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[3]) /* 0x40388180 */ +#define TCPWM0_GRP1_CNT4 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[4]) /* 0x40388200 */ +#define TCPWM0_GRP1_CNT5 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[5]) /* 0x40388280 */ +#define TCPWM0_GRP1_CNT6 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[6]) /* 0x40388300 */ +#define TCPWM0_GRP1_CNT7 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[7]) /* 0x40388380 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* CTBM +*******************************************************************************/ + +#define CTBM0_BASE 0x40900000UL +#define CTBM0 ((CTBM_Type*) CTBM0_BASE) /* 0x40900000 */ + +/******************************************************************************* +* CTDAC +*******************************************************************************/ + +#define CTDAC0_BASE 0x40940000UL +#define CTDAC0 ((CTDAC_Type*) CTDAC0_BASE) /* 0x40940000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR0_BASE 0x409B0000UL +#define SAR1_BASE 0x409C0000UL +#define SAR0 ((SAR_Type*) SAR0_BASE) /* 0x409B0000 */ +#define SAR1 ((SAR_Type*) SAR1_BASE) /* 0x409C0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_TIMER ((PASS_TIMER_Type*) &PASS->TIMER) /* 0x409F0100 */ +#define PASS_LPOSC ((PASS_LPOSC_Type*) &PASS->LPOSC) /* 0x409F0200 */ +#define PASS_FIFO0 ((PASS_FIFO_Type*) &PASS->FIFO[0]) /* 0x409F0300 */ +#define PASS_FIFO1 ((PASS_FIFO_Type*) &PASS->FIFO[1]) /* 0x409F0400 */ +#define PASS_AREFV2 ((PASS_AREFV2_Type*) &PASS->AREFV2) /* 0x409F0E00 */ + +/** \} CY8C6144LQI-S4F82 */ + +#endif /* _CY8C6144LQI_S4F82_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144lqi_s4f92.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144lqi_s4f92.h new file mode 100644 index 0000000000..c6f9a35c82 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144lqi_s4f92.h @@ -0,0 +1,993 @@ +/***************************************************************************//** +* \file cy8c6144lqi_s4f92.h +* +* \brief +* CY8C6144LQI-S4F92 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6144LQI_S4F92_H_ +#define _CY8C6144LQI_S4F92_H_ + +/** +* \addtogroup group_device CY8C6144LQI-S4F92 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6144LQI-S4F92 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */ + pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */ + pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */ + pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */ + pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */ + scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #2 */ + scb_4_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_256_IRQn = 131, /*!< 131 [Active] TCPWM #0, Counter #256 */ + tcpwm_0_interrupts_257_IRQn = 132, /*!< 132 [Active] TCPWM #0, Counter #257 */ + tcpwm_0_interrupts_258_IRQn = 133, /*!< 133 [Active] TCPWM #0, Counter #258 */ + tcpwm_0_interrupts_259_IRQn = 134, /*!< 134 [Active] TCPWM #0, Counter #259 */ + tcpwm_0_interrupts_260_IRQn = 135, /*!< 135 [Active] TCPWM #0, Counter #260 */ + tcpwm_0_interrupts_261_IRQn = 136, /*!< 136 [Active] TCPWM #0, Counter #261 */ + tcpwm_0_interrupts_262_IRQn = 137, /*!< 137 [Active] TCPWM #0, Counter #262 */ + tcpwm_0_interrupts_263_IRQn = 138, /*!< 138 [Active] TCPWM #0, Counter #263 */ + pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + cpuss_interrupts_dw0_29_IRQn = 174, /*!< 174 [Active] CPUSS DataWire #0, Channel #29 */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00020000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00040000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00000000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 6u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u + +#include "psoc6_04_config.h" +#include "gpio_psoc6_04_68_qfn.h" + +#define CY_DEVICE_PSOC6A256K +#define CY_SILICON_ID 0xEACB110EUL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_GR11 ((PERI_TR_GR_Type*) &PERI->TR_GR[11]) /* 0x4000AC00 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ +#define PERI_TR_1TO1_GR8 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[8]) /* 0x4000E000 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT0_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT1_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT2_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT3_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT0_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT1_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT2_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT3_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT4_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT5_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT6_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT7_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40100000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40100000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW0_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[29]) /* 0x40288740 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM0_GRP0 ((TCPWM_GRP_Type*) &TCPWM0->GRP[0]) /* 0x40380000 */ +#define TCPWM0_GRP1 ((TCPWM_GRP_Type*) &TCPWM0->GRP[1]) /* 0x40388000 */ +#define TCPWM0_GRP0_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[0]) /* 0x40380000 */ +#define TCPWM0_GRP0_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[1]) /* 0x40380080 */ +#define TCPWM0_GRP0_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[2]) /* 0x40380100 */ +#define TCPWM0_GRP0_CNT3 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[3]) /* 0x40380180 */ +#define TCPWM0_GRP1_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[0]) /* 0x40388000 */ +#define TCPWM0_GRP1_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[1]) /* 0x40388080 */ +#define TCPWM0_GRP1_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[2]) /* 0x40388100 */ +#define TCPWM0_GRP1_CNT3 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[3]) /* 0x40388180 */ +#define TCPWM0_GRP1_CNT4 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[4]) /* 0x40388200 */ +#define TCPWM0_GRP1_CNT5 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[5]) /* 0x40388280 */ +#define TCPWM0_GRP1_CNT6 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[6]) /* 0x40388300 */ +#define TCPWM0_GRP1_CNT7 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[7]) /* 0x40388380 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* CTBM +*******************************************************************************/ + +#define CTBM0_BASE 0x40900000UL +#define CTBM0 ((CTBM_Type*) CTBM0_BASE) /* 0x40900000 */ + +/******************************************************************************* +* CTDAC +*******************************************************************************/ + +#define CTDAC0_BASE 0x40940000UL +#define CTDAC0 ((CTDAC_Type*) CTDAC0_BASE) /* 0x40940000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR0_BASE 0x409B0000UL +#define SAR1_BASE 0x409C0000UL +#define SAR0 ((SAR_Type*) SAR0_BASE) /* 0x409B0000 */ +#define SAR1 ((SAR_Type*) SAR1_BASE) /* 0x409C0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_TIMER ((PASS_TIMER_Type*) &PASS->TIMER) /* 0x409F0100 */ +#define PASS_LPOSC ((PASS_LPOSC_Type*) &PASS->LPOSC) /* 0x409F0200 */ +#define PASS_FIFO0 ((PASS_FIFO_Type*) &PASS->FIFO[0]) /* 0x409F0300 */ +#define PASS_FIFO1 ((PASS_FIFO_Type*) &PASS->FIFO[1]) /* 0x409F0400 */ +#define PASS_AREFV2 ((PASS_AREFV2_Type*) &PASS->AREFV2) /* 0x409F0E00 */ + +/** \} CY8C6144LQI-S4F92 */ + +#endif /* _CY8C6144LQI_S4F92_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145azi_s3f02.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145azi_s3f02.h new file mode 100644 index 0000000000..7d4466a393 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145azi_s3f02.h @@ -0,0 +1,983 @@ +/***************************************************************************//** +* \file cy8c6145azi_s3f02.h +* +* \brief +* CY8C6145AZI-S3F02 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6145AZI_S3F02_H_ +#define _CY8C6145AZI_S3F02_H_ + +/** +* \addtogroup group_device CY8C6145AZI-S3F02 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6145AZI-S3F02 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00040000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00080000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u + +#include "psoc6_03_config.h" +#include "gpio_psoc6_03_100_tqfp.h" + +#define CY_DEVICE_PSOC6A512K +#define CY_SILICON_ID 0xE71A1105UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/** \} CY8C6145AZI-S3F02 */ + +#endif /* _CY8C6145AZI_S3F02_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145azi_s3f12.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145azi_s3f12.h new file mode 100644 index 0000000000..91a95c3b1d --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145azi_s3f12.h @@ -0,0 +1,983 @@ +/***************************************************************************//** +* \file cy8c6145azi_s3f12.h +* +* \brief +* CY8C6145AZI-S3F12 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6145AZI_S3F12_H_ +#define _CY8C6145AZI_S3F12_H_ + +/** +* \addtogroup group_device CY8C6145AZI-S3F12 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6145AZI-S3F12 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00040000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00080000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u + +#include "psoc6_03_config.h" +#include "gpio_psoc6_03_100_tqfp.h" + +#define CY_DEVICE_PSOC6A512K +#define CY_SILICON_ID 0xE7171105UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/** \} CY8C6145AZI-S3F12 */ + +#endif /* _CY8C6145AZI_S3F12_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245w_s3d72.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145azi_s3f42.h similarity index 83% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245w_s3d72.h rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145azi_s3f42.h index 8a273c2722..de940011a7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245w_s3d72.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145azi_s3f42.h @@ -1,11 +1,11 @@ /***************************************************************************//** -* \file cy8c6245w_s3d72.h +* \file cy8c6145azi_s3f42.h * * \brief -* CY8C6245W-S3D72 device header +* CY8C6145AZI-S3F42 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -25,11 +25,11 @@ * limitations under the License. *******************************************************************************/ -#ifndef _CY8C6245W_S3D72_H_ -#define _CY8C6245W_S3D72_H_ +#ifndef _CY8C6145AZI_S3F42_H_ +#define _CY8C6145AZI_S3F42_H_ /** -* \addtogroup group_device CY8C6245W-S3D72 +* \addtogroup group_device CY8C6145AZI-S3F42 * \{ */ @@ -43,37 +43,6 @@ *******************************************************************************/ typedef enum { -#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ - (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ - (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ - (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) - /* ARM Cortex-M0+ Core Interrupt Numbers */ - Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ - NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ - HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ - SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ - PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ - SysTick_IRQn = -1, /*!< -1 System Tick Timer */ - /* CY8C6245W-S3D72 User Interrupt Numbers */ - NvicMux0_IRQn = 0, /*!< 0 [DeepSleep] CPU User Interrupt #0 */ - NvicMux1_IRQn = 1, /*!< 1 [DeepSleep] CPU User Interrupt #1 */ - NvicMux2_IRQn = 2, /*!< 2 [DeepSleep] CPU User Interrupt #2 */ - NvicMux3_IRQn = 3, /*!< 3 [DeepSleep] CPU User Interrupt #3 */ - NvicMux4_IRQn = 4, /*!< 4 [DeepSleep] CPU User Interrupt #4 */ - NvicMux5_IRQn = 5, /*!< 5 [DeepSleep] CPU User Interrupt #5 */ - NvicMux6_IRQn = 6, /*!< 6 [DeepSleep] CPU User Interrupt #6 */ - NvicMux7_IRQn = 7, /*!< 7 [DeepSleep] CPU User Interrupt #7 */ - /* CY8C6245W-S3D72 Internal SW Interrupt Numbers */ - Internal0_IRQn = 8, /*!< 8 [Active] Internal SW Interrupt #0 */ - Internal1_IRQn = 9, /*!< 9 [Active] Internal SW Interrupt #1 */ - Internal2_IRQn = 10, /*!< 10 [Active] Internal SW Interrupt #2 */ - Internal3_IRQn = 11, /*!< 11 [Active] Internal SW Interrupt #3 */ - Internal4_IRQn = 12, /*!< 12 [Active] Internal SW Interrupt #4 */ - Internal5_IRQn = 13, /*!< 13 [Active] Internal SW Interrupt #5 */ - Internal6_IRQn = 14, /*!< 14 [Active] Internal SW Interrupt #6 */ - Internal7_IRQn = 15, /*!< 15 [Active] Internal SW Interrupt #7 */ - unconnected_IRQn =1023 /*!< 1023 Unconnected */ -#else /* ARM Cortex-M4 Core Interrupt Numbers */ Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ @@ -85,7 +54,7 @@ typedef enum { DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ SysTick_IRQn = -1, /*!< -1 System Tick Timer */ - /* CY8C6245W-S3D72 Peripheral Interrupt Numbers */ + /* CY8C6145AZI-S3F42 Peripheral Interrupt Numbers */ ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ @@ -223,182 +192,14 @@ typedef enum { cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ - unconnected_IRQn =1023 /*!< 1023 Unconnected */ -#endif + unconnected_IRQn = 240 /*!< 240 Unconnected */ } IRQn_Type; -#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ - (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ - (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ - (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) - -/* CY8C6245W-S3D72 interrupts that can be routed to the CM0+ NVIC */ -typedef enum { - ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ - ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ - ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ - ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ - ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ - ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ - ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ - ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ - ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ - ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ - ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ - ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ - ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ - ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ - lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ - scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ - srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ - srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ - srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ - srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ - cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ - cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ - cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ - cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ - cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ - cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ - cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ - cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ - cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ - cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ - cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ - cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ - cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ - cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ - cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ - cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ - scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ - scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ - scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ - scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ - scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ - scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ - csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ - cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ - cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ - cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ - cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ - cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ - cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ - cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ - cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ - cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ - cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ - cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ - cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ - cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ - cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ - cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ - cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ - cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ - cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ - cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ - cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ - cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ - cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ - cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ - cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ - cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ - cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ - cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ - cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ - cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ - cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ - cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ - cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ - cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ - cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ - cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ - cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ - cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ - cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ - cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ - cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ - cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ - cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ - cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ - cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ - cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ - cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ - cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ - cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ - cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ - cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ - cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ - cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ - cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ - cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ - cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ - cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ - cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ - cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ - cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ - cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ - cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ - cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ - cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ - cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ - cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ - cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ - cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ - cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ - cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ - tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ - tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ - tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ - tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ - tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ - tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ - tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ - tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ - tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ - tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ - tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ - tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ - pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ - smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ - usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ - usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ - usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ - sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ - sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ - canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ - canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ - canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ - cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ - cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ - cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ - disconnected_IRQn =1023 /*!< 1023 Disconnected */ -} cy_en_intr_t; - -#endif - /******************************************************************************* * Processor and Core Peripheral Section *******************************************************************************/ -#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ - (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ - (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ - (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) - -/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */ -#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ -#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ - -/** \} Configuration_of_CMSIS */ - -#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ - -#else - /* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ #define __CM4_REV 0x0001U /*!< CM4 Core Revision */ #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ @@ -406,7 +207,7 @@ typedef enum { #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ #define __MPU_PRESENT 1 /*!< MPU present or not */ #define __FPU_PRESENT 1 /*!< FPU present or not */ -#define __CM0P_PRESENT 1 /*!< CM0P present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ #define __DTCM_PRESENT 0 /*!< DTCM present or not */ #define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ #define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ @@ -415,7 +216,6 @@ typedef enum { #include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ -#endif /* Memory Blocks */ #define CY_ROM_BASE 0x00000000UL @@ -438,33 +238,9 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 2u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 7u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -477,39 +253,63 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 1u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXTTCANFD 1u -#define CY_IP_MXTTCANFD_INSTANCES 1u -#define CY_IP_MXTTCANFD_VERSION 1u -#define CY_IP_MXLPCOMP 1u -#define CY_IP_MXLPCOMP_INSTANCES 1u -#define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u #define CY_IP_MXS40IOSS 1u #define CY_IP_MXS40IOSS_INSTANCES 1u #define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_03_config.h" #include "gpio_psoc6_03_100_tqfp.h" #define CY_DEVICE_PSOC6A512K -#define CY_SILICON_ID 0xE70E1105UL +#define CY_SILICON_ID 0xE7141105UL #define CY_HF_CLK_MAX_FREQ 150000000UL #define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL @@ -1185,9 +985,9 @@ typedef enum { #define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ #define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ -/** \} CY8C6245W-S3D72 */ +/** \} CY8C6145AZI-S3F42 */ -#endif /* _CY8C6245W_S3D72_H_ */ +#endif /* _CY8C6145AZI_S3F42_H_ */ /* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145azi_s3f62.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145azi_s3f62.h new file mode 100644 index 0000000000..4fbace6c09 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145azi_s3f62.h @@ -0,0 +1,983 @@ +/***************************************************************************//** +* \file cy8c6145azi_s3f62.h +* +* \brief +* CY8C6145AZI-S3F62 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6145AZI_S3F62_H_ +#define _CY8C6145AZI_S3F62_H_ + +/** +* \addtogroup group_device CY8C6145AZI-S3F62 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6145AZI-S3F62 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00040000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00080000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u + +#include "psoc6_03_config.h" +#include "gpio_psoc6_03_100_tqfp.h" + +#define CY_DEVICE_PSOC6A512K +#define CY_SILICON_ID 0xE7121105UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/** \} CY8C6145AZI-S3F62 */ + +#endif /* _CY8C6145AZI_S3F62_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145azi_s3f72.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145azi_s3f72.h new file mode 100644 index 0000000000..7a16cf8aad --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145azi_s3f72.h @@ -0,0 +1,993 @@ +/***************************************************************************//** +* \file cy8c6145azi_s3f72.h +* +* \brief +* CY8C6145AZI-S3F72 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6145AZI_S3F72_H_ +#define _CY8C6145AZI_S3F72_H_ + +/** +* \addtogroup group_device CY8C6145AZI-S3F72 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6145AZI-S3F72 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00040000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00080000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u + +#include "psoc6_03_config.h" +#include "gpio_psoc6_03_100_tqfp.h" + +#define CY_DEVICE_PSOC6A512K +#define CY_SILICON_ID 0xE70F1105UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40100000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40100000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/** \} CY8C6145AZI-S3F72 */ + +#endif /* _CY8C6145AZI_S3F72_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145fni_s3f11.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145fni_s3f11.h new file mode 100644 index 0000000000..bc3400320e --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145fni_s3f11.h @@ -0,0 +1,970 @@ +/***************************************************************************//** +* \file cy8c6145fni_s3f11.h +* +* \brief +* CY8C6145FNI-S3F11 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6145FNI_S3F11_H_ +#define _CY8C6145FNI_S3F11_H_ + +/** +* \addtogroup group_device CY8C6145FNI-S3F11 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6145FNI-S3F11 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00040000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00080000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u + +#include "psoc6_03_config.h" +#include "gpio_psoc6_03_49_wlcsp.h" + +#define CY_DEVICE_PSOC6A512K +#define CY_SILICON_ID 0xE7191105UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/** \} CY8C6145FNI-S3F11 */ + +#endif /* _CY8C6145FNI_S3F11_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145fni_s3f41.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145fni_s3f41.h new file mode 100644 index 0000000000..89284841ce --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145fni_s3f41.h @@ -0,0 +1,980 @@ +/***************************************************************************//** +* \file cy8c6145fni_s3f41.h +* +* \brief +* CY8C6145FNI-S3F41 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6145FNI_S3F41_H_ +#define _CY8C6145FNI_S3F41_H_ + +/** +* \addtogroup group_device CY8C6145FNI-S3F41 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6145FNI-S3F41 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00040000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00080000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u + +#include "psoc6_03_config.h" +#include "gpio_psoc6_03_49_wlcsp.h" + +#define CY_DEVICE_PSOC6A512K +#define CY_SILICON_ID 0xE7161105UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40100000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40100000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/** \} CY8C6145FNI-S3F41 */ + +#endif /* _CY8C6145FNI_S3F41_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145fni_s3f71.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145fni_s3f71.h new file mode 100644 index 0000000000..0193cbc358 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145fni_s3f71.h @@ -0,0 +1,980 @@ +/***************************************************************************//** +* \file cy8c6145fni_s3f71.h +* +* \brief +* CY8C6145FNI-S3F71 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6145FNI_S3F71_H_ +#define _CY8C6145FNI_S3F71_H_ + +/** +* \addtogroup group_device CY8C6145FNI-S3F71 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6145FNI-S3F71 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00040000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00080000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u + +#include "psoc6_03_config.h" +#include "gpio_psoc6_03_49_wlcsp.h" + +#define CY_DEVICE_PSOC6A512K +#define CY_SILICON_ID 0xE7111105UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40100000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40100000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/** \} CY8C6145FNI-S3F71 */ + +#endif /* _CY8C6145FNI_S3F71_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145lqi_s3f02.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145lqi_s3f02.h new file mode 100644 index 0000000000..70e31314d9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145lqi_s3f02.h @@ -0,0 +1,983 @@ +/***************************************************************************//** +* \file cy8c6145lqi_s3f02.h +* +* \brief +* CY8C6145LQI-S3F02 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6145LQI_S3F02_H_ +#define _CY8C6145LQI_S3F02_H_ + +/** +* \addtogroup group_device CY8C6145LQI-S3F02 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6145LQI-S3F02 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00040000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00080000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u + +#include "psoc6_03_config.h" +#include "gpio_psoc6_03_68_qfn.h" + +#define CY_DEVICE_PSOC6A512K +#define CY_SILICON_ID 0xE71B1105UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/** \} CY8C6145LQI-S3F02 */ + +#endif /* _CY8C6145LQI_S3F02_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145lqi_s3f12.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145lqi_s3f12.h new file mode 100644 index 0000000000..551b9fbb77 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145lqi_s3f12.h @@ -0,0 +1,983 @@ +/***************************************************************************//** +* \file cy8c6145lqi_s3f12.h +* +* \brief +* CY8C6145LQI-S3F12 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6145LQI_S3F12_H_ +#define _CY8C6145LQI_S3F12_H_ + +/** +* \addtogroup group_device CY8C6145LQI-S3F12 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6145LQI-S3F12 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00040000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00080000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u + +#include "psoc6_03_config.h" +#include "gpio_psoc6_03_68_qfn.h" + +#define CY_DEVICE_PSOC6A512K +#define CY_SILICON_ID 0xE7181105UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/** \} CY8C6145LQI-S3F12 */ + +#endif /* _CY8C6145LQI_S3F12_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145lqi_s3f42.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145lqi_s3f42.h new file mode 100644 index 0000000000..e43d30cdac --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145lqi_s3f42.h @@ -0,0 +1,993 @@ +/***************************************************************************//** +* \file cy8c6145lqi_s3f42.h +* +* \brief +* CY8C6145LQI-S3F42 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6145LQI_S3F42_H_ +#define _CY8C6145LQI_S3F42_H_ + +/** +* \addtogroup group_device CY8C6145LQI-S3F42 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6145LQI-S3F42 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00040000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00080000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u + +#include "psoc6_03_config.h" +#include "gpio_psoc6_03_68_qfn.h" + +#define CY_DEVICE_PSOC6A512K +#define CY_SILICON_ID 0xE7151105UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40100000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40100000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/** \} CY8C6145LQI-S3F42 */ + +#endif /* _CY8C6145LQI_S3F42_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145lqi_s3f62.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145lqi_s3f62.h new file mode 100644 index 0000000000..e34256c12f --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145lqi_s3f62.h @@ -0,0 +1,983 @@ +/***************************************************************************//** +* \file cy8c6145lqi_s3f62.h +* +* \brief +* CY8C6145LQI-S3F62 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6145LQI_S3F62_H_ +#define _CY8C6145LQI_S3F62_H_ + +/** +* \addtogroup group_device CY8C6145LQI-S3F62 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6145LQI-S3F62 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00040000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00080000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u + +#include "psoc6_03_config.h" +#include "gpio_psoc6_03_68_qfn.h" + +#define CY_DEVICE_PSOC6A512K +#define CY_SILICON_ID 0xE7131105UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/** \} CY8C6145LQI-S3F62 */ + +#endif /* _CY8C6145LQI_S3F62_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145lqi_s3f72.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145lqi_s3f72.h new file mode 100644 index 0000000000..987416dde1 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145lqi_s3f72.h @@ -0,0 +1,993 @@ +/***************************************************************************//** +* \file cy8c6145lqi_s3f72.h +* +* \brief +* CY8C6145LQI-S3F72 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6145LQI_S3F72_H_ +#define _CY8C6145LQI_S3F72_H_ + +/** +* \addtogroup group_device CY8C6145LQI-S3F72 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6145LQI-S3F72 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00040000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00080000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u + +#include "psoc6_03_config.h" +#include "gpio_psoc6_03_68_qfn.h" + +#define CY_DEVICE_PSOC6A512K +#define CY_SILICON_ID 0xE7101105UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40100000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40100000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/** \} CY8C6145LQI-S3F72 */ + +#endif /* _CY8C6145LQI_S3F72_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6148azi_s2f44.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6148azi_s2f44.h new file mode 100644 index 0000000000..5987877e67 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6148azi_s2f44.h @@ -0,0 +1,1098 @@ +/***************************************************************************//** +* \file cy8c6148azi_s2f44.h +* +* \brief +* CY8C6148AZI-S2F44 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6148AZI_S2F44_H_ +#define _CY8C6148AZI_S2F44_H_ + +/** +* \addtogroup group_device CY8C6148AZI-S2F44 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6148AZI-S2F44 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00080000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00100000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXPROFILE 1u +#define CY_IP_MXPROFILE_INSTANCES 1u +#define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u + +#include "psoc6_02_config.h" +#include "gpio_psoc6_02_128_tqfp.h" + +#define CY_DEVICE_PSOC6A2M +#define CY_SILICON_ID 0xE4621202UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40004140 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR10_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU6_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_DMAC_CH3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_PROFILE ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_SDHC1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB8 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB9 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB10 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB11 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB12 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ +#define PERI_MS_PPU_FX_PDM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[226]) /* 0x40014080 */ +#define PERI_MS_PPU_FX_I2S0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[227]) /* 0x400140C0 */ +#define PERI_MS_PPU_FX_I2S1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[228]) /* 0x40014100 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40100000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40100000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU6_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[0]) /* 0x40235A00 */ +#define PROT_MPU6_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[1]) /* 0x40235A20 */ +#define PROT_MPU6_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[2]) /* 0x40235A40 */ +#define PROT_MPU6_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[3]) /* 0x40235A60 */ +#define PROT_MPU6_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[4]) /* 0x40235A80 */ +#define PROT_MPU6_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[5]) /* 0x40235AA0 */ +#define PROT_MPU6_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[6]) /* 0x40235AC0 */ +#define PROT_MPU6_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[7]) /* 0x40235AE0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ +#define DMAC_CH2 ((DMAC_CH_Type*) &DMAC->CH[2]) /* 0x402A1200 */ +#define DMAC_CH3 ((DMAC_CH_Type*) &DMAC->CH[3]) /* 0x402A1300 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* PROFILE +*******************************************************************************/ + +#define PROFILE_BASE 0x402D0000UL +#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */ +#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */ +#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */ +#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */ +#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */ +#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */ +#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */ +#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */ +#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */ +#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */ +#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */ +#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ +#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */ +#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */ +#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */ +#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */ +#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */ +#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */ +#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */ +#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */ +#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */ +#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */ +#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */ +#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */ +#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */ +#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */ +#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */ +#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ +#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC1_BASE 0x40470000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC1 ((SDHC_Type*) SDHC1_BASE) /* 0x40470000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC1_WRAP ((SDHC_WRAP_Type*) &SDHC1->WRAP) /* 0x40470000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ +#define SDHC1_CORE ((SDHC_CORE_Type*) &SDHC1->CORE) /* 0x40471000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB7_BASE 0x40670000UL +#define SCB8_BASE 0x40680000UL +#define SCB9_BASE 0x40690000UL +#define SCB10_BASE 0x406A0000UL +#define SCB11_BASE 0x406B0000UL +#define SCB12_BASE 0x406C0000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ +#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40670000 */ +#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40680000 */ +#define SCB9 ((CySCB_Type*) SCB9_BASE) /* 0x40690000 */ +#define SCB10 ((CySCB_Type*) SCB10_BASE) /* 0x406A0000 */ +#define SCB11 ((CySCB_Type*) SCB11_BASE) /* 0x406B0000 */ +#define SCB12 ((CySCB_Type*) SCB12_BASE) /* 0x406C0000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/******************************************************************************* +* PDM +*******************************************************************************/ + +#define PDM0_BASE 0x40A00000UL +#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x40A00000 */ + +/******************************************************************************* +* I2S +*******************************************************************************/ + +#define I2S0_BASE 0x40A10000UL +#define I2S1_BASE 0x40A11000UL +#define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x40A10000 */ +#define I2S1 ((I2S_Type*) I2S1_BASE) /* 0x40A11000 */ + +/** \} CY8C6148AZI-S2F44 */ + +#endif /* _CY8C6148AZI_S2F44_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6148bzi_s2f44.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6148bzi_s2f44.h new file mode 100644 index 0000000000..1389299a52 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6148bzi_s2f44.h @@ -0,0 +1,1098 @@ +/***************************************************************************//** +* \file cy8c6148bzi_s2f44.h +* +* \brief +* CY8C6148BZI-S2F44 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6148BZI_S2F44_H_ +#define _CY8C6148BZI_S2F44_H_ + +/** +* \addtogroup group_device CY8C6148BZI-S2F44 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6148BZI-S2F44 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00080000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00100000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXPROFILE 1u +#define CY_IP_MXPROFILE_INSTANCES 1u +#define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u + +#include "psoc6_02_config.h" +#include "gpio_psoc6_02_124_bga.h" + +#define CY_DEVICE_PSOC6A2M +#define CY_SILICON_ID 0xE4611202UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40004140 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR10_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU6_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_DMAC_CH3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_PROFILE ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_SDHC1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB8 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB9 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB10 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB11 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB12 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ +#define PERI_MS_PPU_FX_PDM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[226]) /* 0x40014080 */ +#define PERI_MS_PPU_FX_I2S0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[227]) /* 0x400140C0 */ +#define PERI_MS_PPU_FX_I2S1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[228]) /* 0x40014100 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40100000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40100000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU6_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[0]) /* 0x40235A00 */ +#define PROT_MPU6_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[1]) /* 0x40235A20 */ +#define PROT_MPU6_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[2]) /* 0x40235A40 */ +#define PROT_MPU6_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[3]) /* 0x40235A60 */ +#define PROT_MPU6_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[4]) /* 0x40235A80 */ +#define PROT_MPU6_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[5]) /* 0x40235AA0 */ +#define PROT_MPU6_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[6]) /* 0x40235AC0 */ +#define PROT_MPU6_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[7]) /* 0x40235AE0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ +#define DMAC_CH2 ((DMAC_CH_Type*) &DMAC->CH[2]) /* 0x402A1200 */ +#define DMAC_CH3 ((DMAC_CH_Type*) &DMAC->CH[3]) /* 0x402A1300 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* PROFILE +*******************************************************************************/ + +#define PROFILE_BASE 0x402D0000UL +#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */ +#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */ +#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */ +#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */ +#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */ +#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */ +#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */ +#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */ +#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */ +#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */ +#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */ +#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ +#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */ +#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */ +#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */ +#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */ +#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */ +#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */ +#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */ +#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */ +#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */ +#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */ +#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */ +#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */ +#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */ +#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */ +#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */ +#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ +#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC1_BASE 0x40470000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC1 ((SDHC_Type*) SDHC1_BASE) /* 0x40470000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC1_WRAP ((SDHC_WRAP_Type*) &SDHC1->WRAP) /* 0x40470000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ +#define SDHC1_CORE ((SDHC_CORE_Type*) &SDHC1->CORE) /* 0x40471000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB7_BASE 0x40670000UL +#define SCB8_BASE 0x40680000UL +#define SCB9_BASE 0x40690000UL +#define SCB10_BASE 0x406A0000UL +#define SCB11_BASE 0x406B0000UL +#define SCB12_BASE 0x406C0000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ +#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40670000 */ +#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40680000 */ +#define SCB9 ((CySCB_Type*) SCB9_BASE) /* 0x40690000 */ +#define SCB10 ((CySCB_Type*) SCB10_BASE) /* 0x406A0000 */ +#define SCB11 ((CySCB_Type*) SCB11_BASE) /* 0x406B0000 */ +#define SCB12 ((CySCB_Type*) SCB12_BASE) /* 0x406C0000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/******************************************************************************* +* PDM +*******************************************************************************/ + +#define PDM0_BASE 0x40A00000UL +#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x40A00000 */ + +/******************************************************************************* +* I2S +*******************************************************************************/ + +#define I2S0_BASE 0x40A10000UL +#define I2S1_BASE 0x40A11000UL +#define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x40A10000 */ +#define I2S1 ((I2S_Type*) I2S1_BASE) /* 0x40A11000 */ + +/** \} CY8C6148BZI-S2F44 */ + +#endif /* _CY8C6148BZI_S2F44_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6148fni_s2f43.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6148fni_s2f43.h new file mode 100644 index 0000000000..a52da93fc9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6148fni_s2f43.h @@ -0,0 +1,1098 @@ +/***************************************************************************//** +* \file cy8c6148fni_s2f43.h +* +* \brief +* CY8C6148FNI-S2F43 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6148FNI_S2F43_H_ +#define _CY8C6148FNI_S2F43_H_ + +/** +* \addtogroup group_device CY8C6148FNI-S2F43 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6148FNI-S2F43 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00080000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00100000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXPROFILE 1u +#define CY_IP_MXPROFILE_INSTANCES 1u +#define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u + +#include "psoc6_02_config.h" +#include "gpio_psoc6_02_100_wlcsp.h" + +#define CY_DEVICE_PSOC6A2M +#define CY_SILICON_ID 0xE4631202UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40004140 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR10_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU6_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_DMAC_CH3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_PROFILE ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_SDHC1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB8 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB9 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB10 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB11 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB12 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ +#define PERI_MS_PPU_FX_PDM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[226]) /* 0x40014080 */ +#define PERI_MS_PPU_FX_I2S0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[227]) /* 0x400140C0 */ +#define PERI_MS_PPU_FX_I2S1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[228]) /* 0x40014100 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40100000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40100000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU6_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[0]) /* 0x40235A00 */ +#define PROT_MPU6_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[1]) /* 0x40235A20 */ +#define PROT_MPU6_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[2]) /* 0x40235A40 */ +#define PROT_MPU6_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[3]) /* 0x40235A60 */ +#define PROT_MPU6_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[4]) /* 0x40235A80 */ +#define PROT_MPU6_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[5]) /* 0x40235AA0 */ +#define PROT_MPU6_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[6]) /* 0x40235AC0 */ +#define PROT_MPU6_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[7]) /* 0x40235AE0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ +#define DMAC_CH2 ((DMAC_CH_Type*) &DMAC->CH[2]) /* 0x402A1200 */ +#define DMAC_CH3 ((DMAC_CH_Type*) &DMAC->CH[3]) /* 0x402A1300 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* PROFILE +*******************************************************************************/ + +#define PROFILE_BASE 0x402D0000UL +#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */ +#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */ +#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */ +#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */ +#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */ +#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */ +#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */ +#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */ +#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */ +#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */ +#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */ +#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ +#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */ +#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */ +#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */ +#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */ +#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */ +#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */ +#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */ +#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */ +#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */ +#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */ +#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */ +#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */ +#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */ +#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */ +#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */ +#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ +#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC1_BASE 0x40470000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC1 ((SDHC_Type*) SDHC1_BASE) /* 0x40470000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC1_WRAP ((SDHC_WRAP_Type*) &SDHC1->WRAP) /* 0x40470000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ +#define SDHC1_CORE ((SDHC_CORE_Type*) &SDHC1->CORE) /* 0x40471000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB7_BASE 0x40670000UL +#define SCB8_BASE 0x40680000UL +#define SCB9_BASE 0x40690000UL +#define SCB10_BASE 0x406A0000UL +#define SCB11_BASE 0x406B0000UL +#define SCB12_BASE 0x406C0000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ +#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40670000 */ +#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40680000 */ +#define SCB9 ((CySCB_Type*) SCB9_BASE) /* 0x40690000 */ +#define SCB10 ((CySCB_Type*) SCB10_BASE) /* 0x406A0000 */ +#define SCB11 ((CySCB_Type*) SCB11_BASE) /* 0x406B0000 */ +#define SCB12 ((CySCB_Type*) SCB12_BASE) /* 0x406C0000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/******************************************************************************* +* PDM +*******************************************************************************/ + +#define PDM0_BASE 0x40A00000UL +#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x40A00000 */ + +/******************************************************************************* +* I2S +*******************************************************************************/ + +#define I2S0_BASE 0x40A10000UL +#define I2S1_BASE 0x40A11000UL +#define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x40A10000 */ +#define I2S1 ((I2S_Type*) I2S1_BASE) /* 0x40A11000 */ + +/** \} CY8C6148FNI-S2F43 */ + +#endif /* _CY8C6148FNI_S2F43_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c614aazi_s2f04.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c614aazi_s2f04.h new file mode 100644 index 0000000000..37bdca82bd --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c614aazi_s2f04.h @@ -0,0 +1,1088 @@ +/***************************************************************************//** +* \file cy8c614aazi_s2f04.h +* +* \brief +* CY8C614AAZI-S2F04 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C614AAZI_S2F04_H_ +#define _CY8C614AAZI_S2F04_H_ + +/** +* \addtogroup group_device CY8C614AAZI-S2F04 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C614AAZI-S2F04 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00100000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00200000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXPROFILE 1u +#define CY_IP_MXPROFILE_INSTANCES 1u +#define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u + +#include "psoc6_02_config.h" +#include "gpio_psoc6_02_128_tqfp.h" + +#define CY_DEVICE_PSOC6A2M +#define CY_SILICON_ID 0xE45B1202UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40004140 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR10_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU6_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_DMAC_CH3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_PROFILE ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_SDHC1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB8 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB9 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB10 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB11 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB12 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ +#define PERI_MS_PPU_FX_PDM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[226]) /* 0x40014080 */ +#define PERI_MS_PPU_FX_I2S0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[227]) /* 0x400140C0 */ +#define PERI_MS_PPU_FX_I2S1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[228]) /* 0x40014100 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU6_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[0]) /* 0x40235A00 */ +#define PROT_MPU6_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[1]) /* 0x40235A20 */ +#define PROT_MPU6_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[2]) /* 0x40235A40 */ +#define PROT_MPU6_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[3]) /* 0x40235A60 */ +#define PROT_MPU6_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[4]) /* 0x40235A80 */ +#define PROT_MPU6_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[5]) /* 0x40235AA0 */ +#define PROT_MPU6_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[6]) /* 0x40235AC0 */ +#define PROT_MPU6_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[7]) /* 0x40235AE0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ +#define DMAC_CH2 ((DMAC_CH_Type*) &DMAC->CH[2]) /* 0x402A1200 */ +#define DMAC_CH3 ((DMAC_CH_Type*) &DMAC->CH[3]) /* 0x402A1300 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* PROFILE +*******************************************************************************/ + +#define PROFILE_BASE 0x402D0000UL +#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */ +#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */ +#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */ +#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */ +#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */ +#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */ +#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */ +#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */ +#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */ +#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */ +#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */ +#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ +#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */ +#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */ +#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */ +#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */ +#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */ +#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */ +#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */ +#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */ +#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */ +#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */ +#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */ +#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */ +#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */ +#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */ +#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */ +#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ +#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC1_BASE 0x40470000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC1 ((SDHC_Type*) SDHC1_BASE) /* 0x40470000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC1_WRAP ((SDHC_WRAP_Type*) &SDHC1->WRAP) /* 0x40470000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ +#define SDHC1_CORE ((SDHC_CORE_Type*) &SDHC1->CORE) /* 0x40471000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB7_BASE 0x40670000UL +#define SCB8_BASE 0x40680000UL +#define SCB9_BASE 0x40690000UL +#define SCB10_BASE 0x406A0000UL +#define SCB11_BASE 0x406B0000UL +#define SCB12_BASE 0x406C0000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ +#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40670000 */ +#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40680000 */ +#define SCB9 ((CySCB_Type*) SCB9_BASE) /* 0x40690000 */ +#define SCB10 ((CySCB_Type*) SCB10_BASE) /* 0x406A0000 */ +#define SCB11 ((CySCB_Type*) SCB11_BASE) /* 0x406B0000 */ +#define SCB12 ((CySCB_Type*) SCB12_BASE) /* 0x406C0000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/******************************************************************************* +* PDM +*******************************************************************************/ + +#define PDM0_BASE 0x40A00000UL +#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x40A00000 */ + +/******************************************************************************* +* I2S +*******************************************************************************/ + +#define I2S0_BASE 0x40A10000UL +#define I2S1_BASE 0x40A11000UL +#define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x40A10000 */ +#define I2S1 ((I2S_Type*) I2S1_BASE) /* 0x40A11000 */ + +/** \} CY8C614AAZI-S2F04 */ + +#endif /* _CY8C614AAZI_S2F04_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c614aazi_s2f14.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c614aazi_s2f14.h new file mode 100644 index 0000000000..47ad77bb21 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c614aazi_s2f14.h @@ -0,0 +1,1088 @@ +/***************************************************************************//** +* \file cy8c614aazi_s2f14.h +* +* \brief +* CY8C614AAZI-S2F14 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C614AAZI_S2F14_H_ +#define _CY8C614AAZI_S2F14_H_ + +/** +* \addtogroup group_device CY8C614AAZI-S2F14 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C614AAZI-S2F14 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00100000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00200000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXPROFILE 1u +#define CY_IP_MXPROFILE_INSTANCES 1u +#define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u + +#include "psoc6_02_config.h" +#include "gpio_psoc6_02_128_tqfp.h" + +#define CY_DEVICE_PSOC6A2M +#define CY_SILICON_ID 0xE45D1202UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40004140 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR10_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU6_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_DMAC_CH3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_PROFILE ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_SDHC1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB8 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB9 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB10 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB11 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB12 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ +#define PERI_MS_PPU_FX_PDM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[226]) /* 0x40014080 */ +#define PERI_MS_PPU_FX_I2S0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[227]) /* 0x400140C0 */ +#define PERI_MS_PPU_FX_I2S1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[228]) /* 0x40014100 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU6_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[0]) /* 0x40235A00 */ +#define PROT_MPU6_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[1]) /* 0x40235A20 */ +#define PROT_MPU6_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[2]) /* 0x40235A40 */ +#define PROT_MPU6_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[3]) /* 0x40235A60 */ +#define PROT_MPU6_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[4]) /* 0x40235A80 */ +#define PROT_MPU6_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[5]) /* 0x40235AA0 */ +#define PROT_MPU6_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[6]) /* 0x40235AC0 */ +#define PROT_MPU6_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[7]) /* 0x40235AE0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ +#define DMAC_CH2 ((DMAC_CH_Type*) &DMAC->CH[2]) /* 0x402A1200 */ +#define DMAC_CH3 ((DMAC_CH_Type*) &DMAC->CH[3]) /* 0x402A1300 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* PROFILE +*******************************************************************************/ + +#define PROFILE_BASE 0x402D0000UL +#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */ +#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */ +#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */ +#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */ +#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */ +#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */ +#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */ +#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */ +#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */ +#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */ +#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */ +#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ +#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */ +#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */ +#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */ +#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */ +#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */ +#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */ +#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */ +#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */ +#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */ +#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */ +#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */ +#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */ +#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */ +#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */ +#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */ +#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ +#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC1_BASE 0x40470000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC1 ((SDHC_Type*) SDHC1_BASE) /* 0x40470000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC1_WRAP ((SDHC_WRAP_Type*) &SDHC1->WRAP) /* 0x40470000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ +#define SDHC1_CORE ((SDHC_CORE_Type*) &SDHC1->CORE) /* 0x40471000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB7_BASE 0x40670000UL +#define SCB8_BASE 0x40680000UL +#define SCB9_BASE 0x40690000UL +#define SCB10_BASE 0x406A0000UL +#define SCB11_BASE 0x406B0000UL +#define SCB12_BASE 0x406C0000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ +#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40670000 */ +#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40680000 */ +#define SCB9 ((CySCB_Type*) SCB9_BASE) /* 0x40690000 */ +#define SCB10 ((CySCB_Type*) SCB10_BASE) /* 0x406A0000 */ +#define SCB11 ((CySCB_Type*) SCB11_BASE) /* 0x406B0000 */ +#define SCB12 ((CySCB_Type*) SCB12_BASE) /* 0x406C0000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/******************************************************************************* +* PDM +*******************************************************************************/ + +#define PDM0_BASE 0x40A00000UL +#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x40A00000 */ + +/******************************************************************************* +* I2S +*******************************************************************************/ + +#define I2S0_BASE 0x40A10000UL +#define I2S1_BASE 0x40A11000UL +#define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x40A10000 */ +#define I2S1 ((I2S_Type*) I2S1_BASE) /* 0x40A11000 */ + +/** \} CY8C614AAZI-S2F14 */ + +#endif /* _CY8C614AAZI_S2F14_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c614aazi_s2f44.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c614aazi_s2f44.h new file mode 100644 index 0000000000..bb1464403c --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c614aazi_s2f44.h @@ -0,0 +1,1098 @@ +/***************************************************************************//** +* \file cy8c614aazi_s2f44.h +* +* \brief +* CY8C614AAZI-S2F44 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C614AAZI_S2F44_H_ +#define _CY8C614AAZI_S2F44_H_ + +/** +* \addtogroup group_device CY8C614AAZI-S2F44 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C614AAZI-S2F44 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00100000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00200000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXPROFILE 1u +#define CY_IP_MXPROFILE_INSTANCES 1u +#define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u + +#include "psoc6_02_config.h" +#include "gpio_psoc6_02_128_tqfp.h" + +#define CY_DEVICE_PSOC6A2M +#define CY_SILICON_ID 0xE45F1202UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40004140 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR10_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU6_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_DMAC_CH3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_PROFILE ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_SDHC1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB8 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB9 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB10 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB11 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB12 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ +#define PERI_MS_PPU_FX_PDM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[226]) /* 0x40014080 */ +#define PERI_MS_PPU_FX_I2S0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[227]) /* 0x400140C0 */ +#define PERI_MS_PPU_FX_I2S1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[228]) /* 0x40014100 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40100000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40100000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU6_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[0]) /* 0x40235A00 */ +#define PROT_MPU6_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[1]) /* 0x40235A20 */ +#define PROT_MPU6_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[2]) /* 0x40235A40 */ +#define PROT_MPU6_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[3]) /* 0x40235A60 */ +#define PROT_MPU6_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[4]) /* 0x40235A80 */ +#define PROT_MPU6_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[5]) /* 0x40235AA0 */ +#define PROT_MPU6_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[6]) /* 0x40235AC0 */ +#define PROT_MPU6_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[7]) /* 0x40235AE0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ +#define DMAC_CH2 ((DMAC_CH_Type*) &DMAC->CH[2]) /* 0x402A1200 */ +#define DMAC_CH3 ((DMAC_CH_Type*) &DMAC->CH[3]) /* 0x402A1300 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* PROFILE +*******************************************************************************/ + +#define PROFILE_BASE 0x402D0000UL +#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */ +#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */ +#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */ +#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */ +#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */ +#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */ +#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */ +#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */ +#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */ +#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */ +#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */ +#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ +#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */ +#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */ +#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */ +#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */ +#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */ +#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */ +#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */ +#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */ +#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */ +#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */ +#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */ +#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */ +#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */ +#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */ +#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */ +#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ +#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC1_BASE 0x40470000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC1 ((SDHC_Type*) SDHC1_BASE) /* 0x40470000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC1_WRAP ((SDHC_WRAP_Type*) &SDHC1->WRAP) /* 0x40470000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ +#define SDHC1_CORE ((SDHC_CORE_Type*) &SDHC1->CORE) /* 0x40471000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB7_BASE 0x40670000UL +#define SCB8_BASE 0x40680000UL +#define SCB9_BASE 0x40690000UL +#define SCB10_BASE 0x406A0000UL +#define SCB11_BASE 0x406B0000UL +#define SCB12_BASE 0x406C0000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ +#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40670000 */ +#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40680000 */ +#define SCB9 ((CySCB_Type*) SCB9_BASE) /* 0x40690000 */ +#define SCB10 ((CySCB_Type*) SCB10_BASE) /* 0x406A0000 */ +#define SCB11 ((CySCB_Type*) SCB11_BASE) /* 0x406B0000 */ +#define SCB12 ((CySCB_Type*) SCB12_BASE) /* 0x406C0000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/******************************************************************************* +* PDM +*******************************************************************************/ + +#define PDM0_BASE 0x40A00000UL +#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x40A00000 */ + +/******************************************************************************* +* I2S +*******************************************************************************/ + +#define I2S0_BASE 0x40A10000UL +#define I2S1_BASE 0x40A11000UL +#define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x40A10000 */ +#define I2S1 ((I2S_Type*) I2S1_BASE) /* 0x40A11000 */ + +/** \} CY8C614AAZI-S2F44 */ + +#endif /* _CY8C614AAZI_S2F44_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c614abzi_s2f04.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c614abzi_s2f04.h new file mode 100644 index 0000000000..7cc7d8c923 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c614abzi_s2f04.h @@ -0,0 +1,1088 @@ +/***************************************************************************//** +* \file cy8c614abzi_s2f04.h +* +* \brief +* CY8C614ABZI-S2F04 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C614ABZI_S2F04_H_ +#define _CY8C614ABZI_S2F04_H_ + +/** +* \addtogroup group_device CY8C614ABZI-S2F04 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C614ABZI-S2F04 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00100000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00200000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXPROFILE 1u +#define CY_IP_MXPROFILE_INSTANCES 1u +#define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u + +#include "psoc6_02_config.h" +#include "gpio_psoc6_02_124_bga.h" + +#define CY_DEVICE_PSOC6A2M +#define CY_SILICON_ID 0xE45A1202UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40004140 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR10_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU6_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_DMAC_CH3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_PROFILE ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_SDHC1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB8 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB9 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB10 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB11 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB12 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ +#define PERI_MS_PPU_FX_PDM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[226]) /* 0x40014080 */ +#define PERI_MS_PPU_FX_I2S0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[227]) /* 0x400140C0 */ +#define PERI_MS_PPU_FX_I2S1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[228]) /* 0x40014100 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU6_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[0]) /* 0x40235A00 */ +#define PROT_MPU6_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[1]) /* 0x40235A20 */ +#define PROT_MPU6_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[2]) /* 0x40235A40 */ +#define PROT_MPU6_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[3]) /* 0x40235A60 */ +#define PROT_MPU6_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[4]) /* 0x40235A80 */ +#define PROT_MPU6_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[5]) /* 0x40235AA0 */ +#define PROT_MPU6_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[6]) /* 0x40235AC0 */ +#define PROT_MPU6_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[7]) /* 0x40235AE0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ +#define DMAC_CH2 ((DMAC_CH_Type*) &DMAC->CH[2]) /* 0x402A1200 */ +#define DMAC_CH3 ((DMAC_CH_Type*) &DMAC->CH[3]) /* 0x402A1300 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* PROFILE +*******************************************************************************/ + +#define PROFILE_BASE 0x402D0000UL +#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */ +#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */ +#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */ +#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */ +#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */ +#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */ +#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */ +#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */ +#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */ +#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */ +#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */ +#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ +#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */ +#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */ +#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */ +#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */ +#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */ +#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */ +#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */ +#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */ +#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */ +#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */ +#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */ +#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */ +#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */ +#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */ +#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */ +#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ +#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC1_BASE 0x40470000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC1 ((SDHC_Type*) SDHC1_BASE) /* 0x40470000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC1_WRAP ((SDHC_WRAP_Type*) &SDHC1->WRAP) /* 0x40470000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ +#define SDHC1_CORE ((SDHC_CORE_Type*) &SDHC1->CORE) /* 0x40471000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB7_BASE 0x40670000UL +#define SCB8_BASE 0x40680000UL +#define SCB9_BASE 0x40690000UL +#define SCB10_BASE 0x406A0000UL +#define SCB11_BASE 0x406B0000UL +#define SCB12_BASE 0x406C0000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ +#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40670000 */ +#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40680000 */ +#define SCB9 ((CySCB_Type*) SCB9_BASE) /* 0x40690000 */ +#define SCB10 ((CySCB_Type*) SCB10_BASE) /* 0x406A0000 */ +#define SCB11 ((CySCB_Type*) SCB11_BASE) /* 0x406B0000 */ +#define SCB12 ((CySCB_Type*) SCB12_BASE) /* 0x406C0000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/******************************************************************************* +* PDM +*******************************************************************************/ + +#define PDM0_BASE 0x40A00000UL +#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x40A00000 */ + +/******************************************************************************* +* I2S +*******************************************************************************/ + +#define I2S0_BASE 0x40A10000UL +#define I2S1_BASE 0x40A11000UL +#define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x40A10000 */ +#define I2S1 ((I2S_Type*) I2S1_BASE) /* 0x40A11000 */ + +/** \} CY8C614ABZI-S2F04 */ + +#endif /* _CY8C614ABZI_S2F04_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c614abzi_s2f44.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c614abzi_s2f44.h new file mode 100644 index 0000000000..bd1d63e991 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c614abzi_s2f44.h @@ -0,0 +1,1098 @@ +/***************************************************************************//** +* \file cy8c614abzi_s2f44.h +* +* \brief +* CY8C614ABZI-S2F44 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C614ABZI_S2F44_H_ +#define _CY8C614ABZI_S2F44_H_ + +/** +* \addtogroup group_device CY8C614ABZI-S2F44 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C614ABZI-S2F44 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00100000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00200000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXPROFILE 1u +#define CY_IP_MXPROFILE_INSTANCES 1u +#define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u + +#include "psoc6_02_config.h" +#include "gpio_psoc6_02_124_bga.h" + +#define CY_DEVICE_PSOC6A2M +#define CY_SILICON_ID 0xE45E1202UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40004140 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR10_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU6_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_DMAC_CH3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_PROFILE ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_SDHC1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB8 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB9 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB10 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB11 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB12 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ +#define PERI_MS_PPU_FX_PDM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[226]) /* 0x40014080 */ +#define PERI_MS_PPU_FX_I2S0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[227]) /* 0x400140C0 */ +#define PERI_MS_PPU_FX_I2S1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[228]) /* 0x40014100 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40100000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40100000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU6_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[0]) /* 0x40235A00 */ +#define PROT_MPU6_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[1]) /* 0x40235A20 */ +#define PROT_MPU6_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[2]) /* 0x40235A40 */ +#define PROT_MPU6_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[3]) /* 0x40235A60 */ +#define PROT_MPU6_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[4]) /* 0x40235A80 */ +#define PROT_MPU6_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[5]) /* 0x40235AA0 */ +#define PROT_MPU6_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[6]) /* 0x40235AC0 */ +#define PROT_MPU6_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[7]) /* 0x40235AE0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ +#define DMAC_CH2 ((DMAC_CH_Type*) &DMAC->CH[2]) /* 0x402A1200 */ +#define DMAC_CH3 ((DMAC_CH_Type*) &DMAC->CH[3]) /* 0x402A1300 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* PROFILE +*******************************************************************************/ + +#define PROFILE_BASE 0x402D0000UL +#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */ +#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */ +#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */ +#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */ +#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */ +#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */ +#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */ +#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */ +#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */ +#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */ +#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */ +#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ +#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */ +#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */ +#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */ +#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */ +#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */ +#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */ +#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */ +#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */ +#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */ +#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */ +#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */ +#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */ +#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */ +#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */ +#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */ +#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ +#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC1_BASE 0x40470000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC1 ((SDHC_Type*) SDHC1_BASE) /* 0x40470000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC1_WRAP ((SDHC_WRAP_Type*) &SDHC1->WRAP) /* 0x40470000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ +#define SDHC1_CORE ((SDHC_CORE_Type*) &SDHC1->CORE) /* 0x40471000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB7_BASE 0x40670000UL +#define SCB8_BASE 0x40680000UL +#define SCB9_BASE 0x40690000UL +#define SCB10_BASE 0x406A0000UL +#define SCB11_BASE 0x406B0000UL +#define SCB12_BASE 0x406C0000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ +#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40670000 */ +#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40680000 */ +#define SCB9 ((CySCB_Type*) SCB9_BASE) /* 0x40690000 */ +#define SCB10 ((CySCB_Type*) SCB10_BASE) /* 0x406A0000 */ +#define SCB11 ((CySCB_Type*) SCB11_BASE) /* 0x406B0000 */ +#define SCB12 ((CySCB_Type*) SCB12_BASE) /* 0x406C0000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/******************************************************************************* +* PDM +*******************************************************************************/ + +#define PDM0_BASE 0x40A00000UL +#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x40A00000 */ + +/******************************************************************************* +* I2S +*******************************************************************************/ + +#define I2S0_BASE 0x40A10000UL +#define I2S1_BASE 0x40A11000UL +#define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x40A10000 */ +#define I2S1 ((I2S_Type*) I2S1_BASE) /* 0x40A11000 */ + +/** \} CY8C614ABZI-S2F44 */ + +#endif /* _CY8C614ABZI_S2F44_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c614afni_s2f03.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c614afni_s2f03.h new file mode 100644 index 0000000000..5cf7c0a1cf --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c614afni_s2f03.h @@ -0,0 +1,1088 @@ +/***************************************************************************//** +* \file cy8c614afni_s2f03.h +* +* \brief +* CY8C614AFNI-S2F03 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C614AFNI_S2F03_H_ +#define _CY8C614AFNI_S2F03_H_ + +/** +* \addtogroup group_device CY8C614AFNI-S2F03 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C614AFNI-S2F03 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00100000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00200000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXPROFILE 1u +#define CY_IP_MXPROFILE_INSTANCES 1u +#define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u + +#include "psoc6_02_config.h" +#include "gpio_psoc6_02_100_wlcsp.h" + +#define CY_DEVICE_PSOC6A2M +#define CY_SILICON_ID 0xE45C1202UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40004140 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR10_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU6_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_DMAC_CH3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_PROFILE ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_SDHC1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB8 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB9 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB10 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB11 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB12 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ +#define PERI_MS_PPU_FX_PDM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[226]) /* 0x40014080 */ +#define PERI_MS_PPU_FX_I2S0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[227]) /* 0x400140C0 */ +#define PERI_MS_PPU_FX_I2S1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[228]) /* 0x40014100 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU6_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[0]) /* 0x40235A00 */ +#define PROT_MPU6_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[1]) /* 0x40235A20 */ +#define PROT_MPU6_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[2]) /* 0x40235A40 */ +#define PROT_MPU6_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[3]) /* 0x40235A60 */ +#define PROT_MPU6_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[4]) /* 0x40235A80 */ +#define PROT_MPU6_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[5]) /* 0x40235AA0 */ +#define PROT_MPU6_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[6]) /* 0x40235AC0 */ +#define PROT_MPU6_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[7]) /* 0x40235AE0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ +#define DMAC_CH2 ((DMAC_CH_Type*) &DMAC->CH[2]) /* 0x402A1200 */ +#define DMAC_CH3 ((DMAC_CH_Type*) &DMAC->CH[3]) /* 0x402A1300 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* PROFILE +*******************************************************************************/ + +#define PROFILE_BASE 0x402D0000UL +#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */ +#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */ +#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */ +#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */ +#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */ +#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */ +#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */ +#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */ +#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */ +#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */ +#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */ +#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ +#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */ +#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */ +#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */ +#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */ +#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */ +#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */ +#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */ +#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */ +#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */ +#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */ +#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */ +#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */ +#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */ +#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */ +#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */ +#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ +#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC1_BASE 0x40470000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC1 ((SDHC_Type*) SDHC1_BASE) /* 0x40470000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC1_WRAP ((SDHC_WRAP_Type*) &SDHC1->WRAP) /* 0x40470000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ +#define SDHC1_CORE ((SDHC_CORE_Type*) &SDHC1->CORE) /* 0x40471000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB7_BASE 0x40670000UL +#define SCB8_BASE 0x40680000UL +#define SCB9_BASE 0x40690000UL +#define SCB10_BASE 0x406A0000UL +#define SCB11_BASE 0x406B0000UL +#define SCB12_BASE 0x406C0000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ +#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40670000 */ +#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40680000 */ +#define SCB9 ((CySCB_Type*) SCB9_BASE) /* 0x40690000 */ +#define SCB10 ((CySCB_Type*) SCB10_BASE) /* 0x406A0000 */ +#define SCB11 ((CySCB_Type*) SCB11_BASE) /* 0x406B0000 */ +#define SCB12 ((CySCB_Type*) SCB12_BASE) /* 0x406C0000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/******************************************************************************* +* PDM +*******************************************************************************/ + +#define PDM0_BASE 0x40A00000UL +#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x40A00000 */ + +/******************************************************************************* +* I2S +*******************************************************************************/ + +#define I2S0_BASE 0x40A10000UL +#define I2S1_BASE 0x40A11000UL +#define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x40A10000 */ +#define I2S1 ((I2S_Type*) I2S1_BASE) /* 0x40A11000 */ + +/** \} CY8C614AFNI-S2F03 */ + +#endif /* _CY8C614AFNI_S2F03_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c614afni_s2f43.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c614afni_s2f43.h new file mode 100644 index 0000000000..ef4adad9f0 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c614afni_s2f43.h @@ -0,0 +1,1098 @@ +/***************************************************************************//** +* \file cy8c614afni_s2f43.h +* +* \brief +* CY8C614AFNI-S2F43 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C614AFNI_S2F43_H_ +#define _CY8C614AFNI_S2F43_H_ + +/** +* \addtogroup group_device CY8C614AFNI-S2F43 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C614AFNI-S2F43 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00100000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00200000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXPROFILE 1u +#define CY_IP_MXPROFILE_INSTANCES 1u +#define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u + +#include "psoc6_02_config.h" +#include "gpio_psoc6_02_100_wlcsp.h" + +#define CY_DEVICE_PSOC6A2M +#define CY_SILICON_ID 0xE4601202UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40004140 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR10_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU6_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_DMAC_CH3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_PROFILE ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_SDHC1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB8 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB9 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB10 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB11 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB12 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ +#define PERI_MS_PPU_FX_PDM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[226]) /* 0x40014080 */ +#define PERI_MS_PPU_FX_I2S0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[227]) /* 0x400140C0 */ +#define PERI_MS_PPU_FX_I2S1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[228]) /* 0x40014100 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40100000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40100000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU6_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[0]) /* 0x40235A00 */ +#define PROT_MPU6_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[1]) /* 0x40235A20 */ +#define PROT_MPU6_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[2]) /* 0x40235A40 */ +#define PROT_MPU6_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[3]) /* 0x40235A60 */ +#define PROT_MPU6_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[4]) /* 0x40235A80 */ +#define PROT_MPU6_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[5]) /* 0x40235AA0 */ +#define PROT_MPU6_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[6]) /* 0x40235AC0 */ +#define PROT_MPU6_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[7]) /* 0x40235AE0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ +#define DMAC_CH2 ((DMAC_CH_Type*) &DMAC->CH[2]) /* 0x402A1200 */ +#define DMAC_CH3 ((DMAC_CH_Type*) &DMAC->CH[3]) /* 0x402A1300 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* PROFILE +*******************************************************************************/ + +#define PROFILE_BASE 0x402D0000UL +#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */ +#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */ +#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */ +#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */ +#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */ +#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */ +#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */ +#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */ +#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */ +#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */ +#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */ +#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ +#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */ +#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */ +#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */ +#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */ +#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */ +#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */ +#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */ +#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */ +#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */ +#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */ +#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */ +#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */ +#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */ +#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */ +#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */ +#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ +#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC1_BASE 0x40470000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC1 ((SDHC_Type*) SDHC1_BASE) /* 0x40470000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC1_WRAP ((SDHC_WRAP_Type*) &SDHC1->WRAP) /* 0x40470000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ +#define SDHC1_CORE ((SDHC_CORE_Type*) &SDHC1->CORE) /* 0x40471000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB7_BASE 0x40670000UL +#define SCB8_BASE 0x40680000UL +#define SCB9_BASE 0x40690000UL +#define SCB10_BASE 0x406A0000UL +#define SCB11_BASE 0x406B0000UL +#define SCB12_BASE 0x406C0000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ +#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40670000 */ +#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40680000 */ +#define SCB9 ((CySCB_Type*) SCB9_BASE) /* 0x40690000 */ +#define SCB10 ((CySCB_Type*) SCB10_BASE) /* 0x406A0000 */ +#define SCB11 ((CySCB_Type*) SCB11_BASE) /* 0x406B0000 */ +#define SCB12 ((CySCB_Type*) SCB12_BASE) /* 0x406C0000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/******************************************************************************* +* PDM +*******************************************************************************/ + +#define PDM0_BASE 0x40A00000UL +#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x40A00000 */ + +/******************************************************************************* +* I2S +*******************************************************************************/ + +#define I2S0_BASE 0x40A10000UL +#define I2S1_BASE 0x40A11000UL +#define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x40A10000 */ +#define I2S1 ((I2S_Type*) I2S1_BASE) /* 0x40A11000 */ + +/** \} CY8C614AFNI-S2F43 */ + +#endif /* _CY8C614AFNI_S2F43_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244azi_s4d12.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244azi_s4d12.h index e2d4f40920..63a7c2c370 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244azi_s4d12.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244azi_s4d12.h @@ -5,7 +5,7 @@ * CY8C6244AZI-S4D12 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -471,15 +471,6 @@ typedef enum { #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -// #define CY_IP_MXS40PASS 1u -// #define CY_IP_MXS40PASS_INSTANCES 1u -// #define CY_IP_MXS40PASS_VERSION 2u -// #define CY_IP_MXS40PASS_SAR 1u -// #define CY_IP_MXS40PASS_SAR_INSTANCES 2u -// #define CY_IP_MXS40PASS_SAR_VERSION 2u -// #define CY_IP_MXS40PASS_CTDAC 1u -// #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u -// #define CY_IP_MXS40PASS_CTDAC_VERSION 2u #define CY_IP_MXPERI 1u #define CY_IP_MXPERI_INSTANCES 1u #define CY_IP_MXPERI_VERSION 2u @@ -501,9 +492,6 @@ typedef enum { #define CY_IP_MXS40SRSS_MCWDT 1u #define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u #define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -// #define CY_IP_MXTCPWM 1u -// #define CY_IP_MXTCPWM_INSTANCES 1u -// #define CY_IP_MXTCPWM_VERSION 2u #include "psoc6_04_config.h" #include "gpio_psoc6_04_64_tqfp.h" @@ -1161,9 +1149,7 @@ typedef enum { *******************************************************************************/ #define SAR0_BASE 0x409B0000UL -#define SAR1_BASE 0x409C0000UL #define SAR0 ((SAR_Type*) SAR0_BASE) /* 0x409B0000 */ -#define SAR1 ((SAR_Type*) SAR1_BASE) /* 0x409C0000 */ /******************************************************************************* * PASS diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244azi_s4d62.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244azi_s4d62.h index 150bca0ab3..149fab3153 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244azi_s4d62.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244azi_s4d62.h @@ -5,7 +5,7 @@ * CY8C6244AZI-S4D62 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -471,15 +471,6 @@ typedef enum { #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -// #define CY_IP_MXS40PASS 1u -// #define CY_IP_MXS40PASS_INSTANCES 1u -// #define CY_IP_MXS40PASS_VERSION 2u -// #define CY_IP_MXS40PASS_SAR 1u -// #define CY_IP_MXS40PASS_SAR_INSTANCES 2u -// #define CY_IP_MXS40PASS_SAR_VERSION 2u -// #define CY_IP_MXS40PASS_CTDAC 1u -// #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u -// #define CY_IP_MXS40PASS_CTDAC_VERSION 2u #define CY_IP_MXPERI 1u #define CY_IP_MXPERI_INSTANCES 1u #define CY_IP_MXPERI_VERSION 2u @@ -501,9 +492,6 @@ typedef enum { #define CY_IP_MXS40SRSS_MCWDT 1u #define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u #define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -// #define CY_IP_MXTCPWM 1u -// #define CY_IP_MXTCPWM_INSTANCES 1u -// #define CY_IP_MXTCPWM_VERSION 2u #include "psoc6_04_config.h" #include "gpio_psoc6_04_64_tqfp.h" @@ -1161,9 +1149,7 @@ typedef enum { *******************************************************************************/ #define SAR0_BASE 0x409B0000UL -#define SAR1_BASE 0x409C0000UL #define SAR0 ((SAR_Type*) SAR0_BASE) /* 0x409B0000 */ -#define SAR1 ((SAR_Type*) SAR1_BASE) /* 0x409C0000 */ /******************************************************************************* * PASS diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244azi_s4d82.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244azi_s4d82.h index feaa976a66..743b96e694 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244azi_s4d82.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244azi_s4d82.h @@ -5,7 +5,7 @@ * CY8C6244AZI-S4D82 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -474,18 +474,6 @@ typedef enum { #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -// #define CY_IP_MXS40PASS 1u -// #define CY_IP_MXS40PASS_INSTANCES 1u -// #define CY_IP_MXS40PASS_VERSION 2u -// #define CY_IP_MXS40PASS_SAR 1u -// #define CY_IP_MXS40PASS_SAR_INSTANCES 2u -// #define CY_IP_MXS40PASS_SAR_VERSION 2u -// #define CY_IP_MXS40PASS_CTDAC 1u -// #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u -// #define CY_IP_MXS40PASS_CTDAC_VERSION 2u -// #define CY_IP_MXS40PASS_CTB 1u -// #define CY_IP_MXS40PASS_CTB_INSTANCES 1u -// #define CY_IP_MXS40PASS_CTB_VERSION 2u #define CY_IP_MXPERI 1u #define CY_IP_MXPERI_INSTANCES 1u #define CY_IP_MXPERI_VERSION 2u @@ -507,9 +495,6 @@ typedef enum { #define CY_IP_MXS40SRSS_MCWDT 1u #define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u #define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -// #define CY_IP_MXTCPWM 1u -// #define CY_IP_MXTCPWM_INSTANCES 1u -// #define CY_IP_MXTCPWM_VERSION 2u #include "psoc6_04_config.h" #include "gpio_psoc6_04_64_tqfp.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244azi_s4d83.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244azi_s4d83.h index ce35891099..a372cb5995 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244azi_s4d83.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244azi_s4d83.h @@ -5,7 +5,7 @@ * CY8C6244AZI-S4D83 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -474,18 +474,6 @@ typedef enum { #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -// #define CY_IP_MXS40PASS 1u -// #define CY_IP_MXS40PASS_INSTANCES 1u -// #define CY_IP_MXS40PASS_VERSION 2u -// #define CY_IP_MXS40PASS_SAR 1u -// #define CY_IP_MXS40PASS_SAR_INSTANCES 2u -// #define CY_IP_MXS40PASS_SAR_VERSION 2u -// #define CY_IP_MXS40PASS_CTDAC 1u -// #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u -// #define CY_IP_MXS40PASS_CTDAC_VERSION 2u -// #define CY_IP_MXS40PASS_CTB 1u -// #define CY_IP_MXS40PASS_CTB_INSTANCES 1u -// #define CY_IP_MXS40PASS_CTB_VERSION 2u #define CY_IP_MXPERI 1u #define CY_IP_MXPERI_INSTANCES 1u #define CY_IP_MXPERI_VERSION 2u @@ -507,9 +495,6 @@ typedef enum { #define CY_IP_MXS40SRSS_MCWDT 1u #define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u #define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -// #define CY_IP_MXTCPWM 1u -// #define CY_IP_MXTCPWM_INSTANCES 1u -// #define CY_IP_MXTCPWM_VERSION 2u #include "psoc6_04_config.h" #include "gpio_psoc6_04_80_tqfp.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244azi_s4d92.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244azi_s4d92.h index 75214bc653..5d7a245c0a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244azi_s4d92.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244azi_s4d92.h @@ -5,7 +5,7 @@ * CY8C6244AZI-S4D92 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -474,18 +474,6 @@ typedef enum { #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -// #define CY_IP_MXS40PASS 1u -// #define CY_IP_MXS40PASS_INSTANCES 1u -// #define CY_IP_MXS40PASS_VERSION 2u -// #define CY_IP_MXS40PASS_SAR 1u -// #define CY_IP_MXS40PASS_SAR_INSTANCES 2u -// #define CY_IP_MXS40PASS_SAR_VERSION 2u -// #define CY_IP_MXS40PASS_CTDAC 1u -// #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u -// #define CY_IP_MXS40PASS_CTDAC_VERSION 2u -// #define CY_IP_MXS40PASS_CTB 1u -// #define CY_IP_MXS40PASS_CTB_INSTANCES 1u -// #define CY_IP_MXS40PASS_CTB_VERSION 2u #define CY_IP_MXPERI 1u #define CY_IP_MXPERI_INSTANCES 1u #define CY_IP_MXPERI_VERSION 2u @@ -507,9 +495,6 @@ typedef enum { #define CY_IP_MXS40SRSS_MCWDT 1u #define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u #define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -// #define CY_IP_MXTCPWM 1u -// #define CY_IP_MXTCPWM_INSTANCES 1u -// #define CY_IP_MXTCPWM_VERSION 2u #include "psoc6_04_config.h" #include "gpio_psoc6_04_64_tqfp.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244azi_s4d93.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244azi_s4d93.h index c838988290..2d2b98bf78 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244azi_s4d93.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244azi_s4d93.h @@ -5,7 +5,7 @@ * CY8C6244AZI-S4D93 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -474,18 +474,6 @@ typedef enum { #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -// #define CY_IP_MXS40PASS 1u -// #define CY_IP_MXS40PASS_INSTANCES 1u -// #define CY_IP_MXS40PASS_VERSION 2u -// #define CY_IP_MXS40PASS_SAR 1u -// #define CY_IP_MXS40PASS_SAR_INSTANCES 2u -// #define CY_IP_MXS40PASS_SAR_VERSION 2u -// #define CY_IP_MXS40PASS_CTDAC 1u -// #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u -// #define CY_IP_MXS40PASS_CTDAC_VERSION 2u -// #define CY_IP_MXS40PASS_CTB 1u -// #define CY_IP_MXS40PASS_CTB_INSTANCES 1u -// #define CY_IP_MXS40PASS_CTB_VERSION 2u #define CY_IP_MXPERI 1u #define CY_IP_MXPERI_INSTANCES 1u #define CY_IP_MXPERI_VERSION 2u @@ -507,9 +495,6 @@ typedef enum { #define CY_IP_MXS40SRSS_MCWDT 1u #define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u #define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -// #define CY_IP_MXTCPWM 1u -// #define CY_IP_MXTCPWM_INSTANCES 1u -// #define CY_IP_MXTCPWM_VERSION 2u #include "psoc6_04_config.h" #include "gpio_psoc6_04_80_tqfp.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244lqi_s4d12.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244lqi_s4d12.h index e2fefcf36c..81d71e8884 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244lqi_s4d12.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244lqi_s4d12.h @@ -5,7 +5,7 @@ * CY8C6244LQI-S4D12 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -471,15 +471,6 @@ typedef enum { #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -// #define CY_IP_MXS40PASS 1u -// #define CY_IP_MXS40PASS_INSTANCES 1u -// #define CY_IP_MXS40PASS_VERSION 2u -// #define CY_IP_MXS40PASS_SAR 1u -// #define CY_IP_MXS40PASS_SAR_INSTANCES 2u -// #define CY_IP_MXS40PASS_SAR_VERSION 2u -// #define CY_IP_MXS40PASS_CTDAC 1u -// #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u -// #define CY_IP_MXS40PASS_CTDAC_VERSION 2u #define CY_IP_MXPERI 1u #define CY_IP_MXPERI_INSTANCES 1u #define CY_IP_MXPERI_VERSION 2u @@ -501,9 +492,6 @@ typedef enum { #define CY_IP_MXS40SRSS_MCWDT 1u #define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u #define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -// #define CY_IP_MXTCPWM 1u -// #define CY_IP_MXTCPWM_INSTANCES 1u -// #define CY_IP_MXTCPWM_VERSION 2u #define CY_IP_MXUSBFS 1u #define CY_IP_MXUSBFS_INSTANCES 1u #define CY_IP_MXUSBFS_VERSION 1u @@ -1174,9 +1162,7 @@ typedef enum { *******************************************************************************/ #define SAR0_BASE 0x409B0000UL -#define SAR1_BASE 0x409C0000UL #define SAR0 ((SAR_Type*) SAR0_BASE) /* 0x409B0000 */ -#define SAR1 ((SAR_Type*) SAR1_BASE) /* 0x409C0000 */ /******************************************************************************* * PASS diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244lqi_s4d62.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244lqi_s4d62.h index 97e6a2632a..a1c0208380 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244lqi_s4d62.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244lqi_s4d62.h @@ -5,7 +5,7 @@ * CY8C6244LQI-S4D62 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -471,15 +471,6 @@ typedef enum { #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -// #define CY_IP_MXS40PASS 1u -// #define CY_IP_MXS40PASS_INSTANCES 1u -// #define CY_IP_MXS40PASS_VERSION 2u -// #define CY_IP_MXS40PASS_SAR 1u -// #define CY_IP_MXS40PASS_SAR_INSTANCES 2u -// #define CY_IP_MXS40PASS_SAR_VERSION 2u -// #define CY_IP_MXS40PASS_CTDAC 1u -// #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u -// #define CY_IP_MXS40PASS_CTDAC_VERSION 2u #define CY_IP_MXPERI 1u #define CY_IP_MXPERI_INSTANCES 1u #define CY_IP_MXPERI_VERSION 2u @@ -501,9 +492,6 @@ typedef enum { #define CY_IP_MXS40SRSS_MCWDT 1u #define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u #define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -// #define CY_IP_MXTCPWM 1u -// #define CY_IP_MXTCPWM_INSTANCES 1u -// #define CY_IP_MXTCPWM_VERSION 2u #define CY_IP_MXUSBFS 1u #define CY_IP_MXUSBFS_INSTANCES 1u #define CY_IP_MXUSBFS_VERSION 1u @@ -1174,9 +1162,7 @@ typedef enum { *******************************************************************************/ #define SAR0_BASE 0x409B0000UL -#define SAR1_BASE 0x409C0000UL #define SAR0 ((SAR_Type*) SAR0_BASE) /* 0x409B0000 */ -#define SAR1 ((SAR_Type*) SAR1_BASE) /* 0x409C0000 */ /******************************************************************************* * PASS diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244lqi_s4d82.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244lqi_s4d82.h index 882780af87..756238ac72 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244lqi_s4d82.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244lqi_s4d82.h @@ -5,7 +5,7 @@ * CY8C6244LQI-S4D82 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -474,18 +474,6 @@ typedef enum { #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -// #define CY_IP_MXS40PASS 1u -// #define CY_IP_MXS40PASS_INSTANCES 1u -// #define CY_IP_MXS40PASS_VERSION 2u -// #define CY_IP_MXS40PASS_SAR 1u -// #define CY_IP_MXS40PASS_SAR_INSTANCES 2u -// #define CY_IP_MXS40PASS_SAR_VERSION 2u -// #define CY_IP_MXS40PASS_CTDAC 1u -// #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u -// #define CY_IP_MXS40PASS_CTDAC_VERSION 2u -// #define CY_IP_MXS40PASS_CTB 1u -// #define CY_IP_MXS40PASS_CTB_INSTANCES 1u -// #define CY_IP_MXS40PASS_CTB_VERSION 2u #define CY_IP_MXPERI 1u #define CY_IP_MXPERI_INSTANCES 1u #define CY_IP_MXPERI_VERSION 2u @@ -507,9 +495,6 @@ typedef enum { #define CY_IP_MXS40SRSS_MCWDT 1u #define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u #define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -// #define CY_IP_MXTCPWM 1u -// #define CY_IP_MXTCPWM_INSTANCES 1u -// #define CY_IP_MXTCPWM_VERSION 2u #define CY_IP_MXUSBFS 1u #define CY_IP_MXUSBFS_INSTANCES 1u #define CY_IP_MXUSBFS_VERSION 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244lqi_s4d92.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244lqi_s4d92.h index 4d32909376..691a827509 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244lqi_s4d92.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244lqi_s4d92.h @@ -5,7 +5,7 @@ * CY8C6244LQI-S4D92 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -474,18 +474,6 @@ typedef enum { #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -// #define CY_IP_MXS40PASS 1u -// #define CY_IP_MXS40PASS_INSTANCES 1u -// #define CY_IP_MXS40PASS_VERSION 2u -// #define CY_IP_MXS40PASS_SAR 1u -// #define CY_IP_MXS40PASS_SAR_INSTANCES 2u -// #define CY_IP_MXS40PASS_SAR_VERSION 2u -// #define CY_IP_MXS40PASS_CTDAC 1u -// #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u -// #define CY_IP_MXS40PASS_CTDAC_VERSION 2u -// #define CY_IP_MXS40PASS_CTB 1u -// #define CY_IP_MXS40PASS_CTB_INSTANCES 1u -// #define CY_IP_MXS40PASS_CTB_VERSION 2u #define CY_IP_MXPERI 1u #define CY_IP_MXPERI_INSTANCES 1u #define CY_IP_MXPERI_VERSION 2u @@ -507,9 +495,6 @@ typedef enum { #define CY_IP_MXS40SRSS_MCWDT 1u #define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u #define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -// #define CY_IP_MXTCPWM 1u -// #define CY_IP_MXTCPWM_INSTANCES 1u -// #define CY_IP_MXTCPWM_VERSION 2u #define CY_IP_MXUSBFS 1u #define CY_IP_MXUSBFS_INSTANCES 1u #define CY_IP_MXUSBFS_VERSION 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d02.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d02.h index 1bf82702e2..4c6d484df2 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d02.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d02.h @@ -5,7 +5,7 @@ * CY8C6245AZI-S3D02 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -438,33 +438,9 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 2u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 7u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -474,33 +450,57 @@ typedef enum { #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 1u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXTTCANFD 1u -#define CY_IP_MXTTCANFD_INSTANCES 1u -#define CY_IP_MXTTCANFD_VERSION 1u -#define CY_IP_MXLPCOMP 1u -#define CY_IP_MXLPCOMP_INSTANCES 1u -#define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u #define CY_IP_MXS40IOSS 1u #define CY_IP_MXS40IOSS_INSTANCES 1u #define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_03_config.h" #include "gpio_psoc6_03_100_tqfp.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d12.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d12.h index f331ebb382..0efc17db40 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d12.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d12.h @@ -5,7 +5,7 @@ * CY8C6245AZI-S3D12 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -438,33 +438,9 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 2u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 7u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -474,33 +450,57 @@ typedef enum { #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 1u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXTTCANFD 1u -#define CY_IP_MXTTCANFD_INSTANCES 1u -#define CY_IP_MXTTCANFD_VERSION 1u -#define CY_IP_MXLPCOMP 1u -#define CY_IP_MXLPCOMP_INSTANCES 1u -#define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u #define CY_IP_MXS40IOSS 1u #define CY_IP_MXS40IOSS_INSTANCES 1u #define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_03_config.h" #include "gpio_psoc6_03_100_tqfp.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d42.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d42.h index e5c1033b2d..a884107ab7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d42.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d42.h @@ -5,7 +5,7 @@ * CY8C6245AZI-S3D42 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -438,33 +438,9 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 2u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 7u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -477,33 +453,57 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 1u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXTTCANFD 1u -#define CY_IP_MXTTCANFD_INSTANCES 1u -#define CY_IP_MXTTCANFD_VERSION 1u -#define CY_IP_MXLPCOMP 1u -#define CY_IP_MXLPCOMP_INSTANCES 1u -#define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u #define CY_IP_MXS40IOSS 1u #define CY_IP_MXS40IOSS_INSTANCES 1u #define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_03_config.h" #include "gpio_psoc6_03_100_tqfp.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d62.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d62.h index bab2db68fc..6888385c89 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d62.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d62.h @@ -5,7 +5,7 @@ * CY8C6245AZI-S3D62 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -438,33 +438,9 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 2u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 7u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -474,33 +450,57 @@ typedef enum { #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 1u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXTTCANFD 1u -#define CY_IP_MXTTCANFD_INSTANCES 1u -#define CY_IP_MXTTCANFD_VERSION 1u -#define CY_IP_MXLPCOMP 1u -#define CY_IP_MXLPCOMP_INSTANCES 1u -#define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u #define CY_IP_MXS40IOSS 1u #define CY_IP_MXS40IOSS_INSTANCES 1u #define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_03_config.h" #include "gpio_psoc6_03_100_tqfp.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d72.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d72.h index 7f36f357d6..4ec19d2952 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d72.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d72.h @@ -5,7 +5,7 @@ * CY8C6245AZI-S3D72 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -438,33 +438,9 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 2u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 7u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -477,33 +453,57 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 1u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXTTCANFD 1u -#define CY_IP_MXTTCANFD_INSTANCES 1u -#define CY_IP_MXTTCANFD_VERSION 1u -#define CY_IP_MXLPCOMP 1u -#define CY_IP_MXLPCOMP_INSTANCES 1u -#define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u #define CY_IP_MXS40IOSS 1u #define CY_IP_MXS40IOSS_INSTANCES 1u #define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_03_config.h" #include "gpio_psoc6_03_100_tqfp.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245fni_s3d11.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245fni_s3d11.h index 4c202a3b90..987412a9d2 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245fni_s3d11.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245fni_s3d11.h @@ -5,7 +5,7 @@ * CY8C6245FNI-S3D11 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -438,33 +438,9 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 2u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 7u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -474,30 +450,54 @@ typedef enum { #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 1u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXTTCANFD 1u -#define CY_IP_MXTTCANFD_INSTANCES 1u -#define CY_IP_MXTTCANFD_VERSION 1u -#define CY_IP_MXLPCOMP 1u -#define CY_IP_MXLPCOMP_INSTANCES 1u -#define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u #define CY_IP_MXS40IOSS 1u #define CY_IP_MXS40IOSS_INSTANCES 1u #define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u #include "psoc6_03_config.h" #include "gpio_psoc6_03_49_wlcsp.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245fni_s3d41.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245fni_s3d41.h index 3fc7981306..59a912d061 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245fni_s3d41.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245fni_s3d41.h @@ -5,7 +5,7 @@ * CY8C6245FNI-S3D41 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -438,33 +438,9 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 2u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 7u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -477,30 +453,54 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 1u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXTTCANFD 1u -#define CY_IP_MXTTCANFD_INSTANCES 1u -#define CY_IP_MXTTCANFD_VERSION 1u -#define CY_IP_MXLPCOMP 1u -#define CY_IP_MXLPCOMP_INSTANCES 1u -#define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u #define CY_IP_MXS40IOSS 1u #define CY_IP_MXS40IOSS_INSTANCES 1u #define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u #include "psoc6_03_config.h" #include "gpio_psoc6_03_49_wlcsp.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245fni_s3d71.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245fni_s3d71.h index 00015d6ba1..eaab1acdbe 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245fni_s3d71.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245fni_s3d71.h @@ -5,7 +5,7 @@ * CY8C6245FNI-S3D71 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -438,33 +438,9 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 2u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 7u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -477,30 +453,54 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 1u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXTTCANFD 1u -#define CY_IP_MXTTCANFD_INSTANCES 1u -#define CY_IP_MXTTCANFD_VERSION 1u -#define CY_IP_MXLPCOMP 1u -#define CY_IP_MXLPCOMP_INSTANCES 1u -#define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u #define CY_IP_MXS40IOSS 1u #define CY_IP_MXS40IOSS_INSTANCES 1u #define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u #include "psoc6_03_config.h" #include "gpio_psoc6_03_49_wlcsp.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d02.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d02.h index 3e5ac1609e..8089032e98 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d02.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d02.h @@ -5,7 +5,7 @@ * CY8C6245LQI-S3D02 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -438,33 +438,9 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 2u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 7u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -474,33 +450,57 @@ typedef enum { #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 1u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXTTCANFD 1u -#define CY_IP_MXTTCANFD_INSTANCES 1u -#define CY_IP_MXTTCANFD_VERSION 1u -#define CY_IP_MXLPCOMP 1u -#define CY_IP_MXLPCOMP_INSTANCES 1u -#define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u #define CY_IP_MXS40IOSS 1u #define CY_IP_MXS40IOSS_INSTANCES 1u #define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_03_config.h" #include "gpio_psoc6_03_68_qfn.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d12.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d12.h index 6ab5ce8e17..2ec7abfdb0 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d12.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d12.h @@ -5,7 +5,7 @@ * CY8C6245LQI-S3D12 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -438,33 +438,9 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 2u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 7u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -474,33 +450,57 @@ typedef enum { #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 1u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXTTCANFD 1u -#define CY_IP_MXTTCANFD_INSTANCES 1u -#define CY_IP_MXTTCANFD_VERSION 1u -#define CY_IP_MXLPCOMP 1u -#define CY_IP_MXLPCOMP_INSTANCES 1u -#define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u #define CY_IP_MXS40IOSS 1u #define CY_IP_MXS40IOSS_INSTANCES 1u #define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_03_config.h" #include "gpio_psoc6_03_68_qfn.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d42.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d42.h index 3d2137f6a6..0c0b492dc8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d42.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d42.h @@ -5,7 +5,7 @@ * CY8C6245LQI-S3D42 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -438,33 +438,9 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 2u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 7u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -477,33 +453,57 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 1u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXTTCANFD 1u -#define CY_IP_MXTTCANFD_INSTANCES 1u -#define CY_IP_MXTTCANFD_VERSION 1u -#define CY_IP_MXLPCOMP 1u -#define CY_IP_MXLPCOMP_INSTANCES 1u -#define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u #define CY_IP_MXS40IOSS 1u #define CY_IP_MXS40IOSS_INSTANCES 1u #define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_03_config.h" #include "gpio_psoc6_03_68_qfn.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d62.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d62.h index 58b40d1fa7..f0343467a5 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d62.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d62.h @@ -5,7 +5,7 @@ * CY8C6245LQI-S3D62 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -438,33 +438,9 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 2u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 7u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -474,33 +450,57 @@ typedef enum { #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 1u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXTTCANFD 1u -#define CY_IP_MXTTCANFD_INSTANCES 1u -#define CY_IP_MXTTCANFD_VERSION 1u -#define CY_IP_MXLPCOMP 1u -#define CY_IP_MXLPCOMP_INSTANCES 1u -#define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u #define CY_IP_MXS40IOSS 1u #define CY_IP_MXS40IOSS_INSTANCES 1u #define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_03_config.h" #include "gpio_psoc6_03_68_qfn.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d72.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d72.h index e457d2f362..8fba63cf58 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d72.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d72.h @@ -5,7 +5,7 @@ * CY8C6245LQI-S3D72 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -438,33 +438,9 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 2u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 7u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -477,33 +453,57 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 1u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXTTCANFD 1u -#define CY_IP_MXTTCANFD_INSTANCES 1u -#define CY_IP_MXTTCANFD_VERSION 1u -#define CY_IP_MXLPCOMP 1u -#define CY_IP_MXLPCOMP_INSTANCES 1u -#define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u #define CY_IP_MXS40IOSS 1u #define CY_IP_MXS40IOSS_INSTANCES 1u #define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_03_config.h" #include "gpio_psoc6_03_68_qfn.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6246bzi_d04.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6246bzi_d04.h index 431ba1b451..e9a38029e2 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6246bzi_d04.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6246bzi_d04.h @@ -5,7 +5,7 @@ * CY8C6246BZI-D04 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -471,42 +471,27 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -519,21 +504,36 @@ typedef enum { #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u #define CY_IP_MXS40PASS_CTDAC_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_124_bga.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bfi_d54.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bfi_d54.h index bd7b00a882..92282a683b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bfi_d54.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bfi_d54.h @@ -5,7 +5,7 @@ * CY8C6247BFI-D54 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -471,33 +471,9 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -507,9 +483,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -525,24 +510,39 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_124_bga.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bzi_aud54.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bzi_aud54.h index 2f03b7e9b4..42886db724 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bzi_aud54.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bzi_aud54.h @@ -5,7 +5,7 @@ * CY8C6247BZI-AUD54 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -471,33 +471,9 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -507,9 +483,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -525,24 +510,39 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_124_bga.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bzi_d34.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bzi_d34.h index 12930b3e72..3027b63d1e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bzi_d34.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bzi_d34.h @@ -5,7 +5,7 @@ * CY8C6247BZI-D34 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -471,42 +471,27 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -522,24 +507,39 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_124_bga.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bzi_d44.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bzi_d44.h index 3c2aed49e1..93c9a4d432 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bzi_d44.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bzi_d44.h @@ -5,7 +5,7 @@ * CY8C6247BZI-D44 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -471,33 +471,9 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -507,9 +483,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -522,21 +507,36 @@ typedef enum { #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u #define CY_IP_MXS40PASS_CTDAC_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_124_bga.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bzi_d54.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bzi_d54.h index 0091926267..dfb56179f7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bzi_d54.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bzi_d54.h @@ -5,7 +5,7 @@ * CY8C6247BZI-D54 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -471,33 +471,9 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -507,9 +483,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -525,24 +510,39 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_124_bga.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247fdi_d02.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247fdi_d02.h index d9f5e55e32..1a1b44ec4c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247fdi_d02.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247fdi_d02.h @@ -5,7 +5,7 @@ * CY8C6247FDI-D02 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -471,42 +471,27 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -519,21 +504,36 @@ typedef enum { #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u #define CY_IP_MXS40PASS_CTDAC_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_80_wlcsp.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247fdi_d32.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247fdi_d32.h index 3c39801b6f..8f08198b49 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247fdi_d32.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247fdi_d32.h @@ -5,7 +5,7 @@ * CY8C6247FDI-D32 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -471,42 +471,27 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -522,24 +507,39 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_80_wlcsp.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247fdi_d52.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247fdi_d52.h index 0d48922ada..d308237b4f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247fdi_d52.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247fdi_d52.h @@ -5,7 +5,7 @@ * CY8C6247FDI-D52 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -471,33 +471,9 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -507,9 +483,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -525,24 +510,39 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_80_wlcsp.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247fti_d52.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247fti_d52.h index 32d4145f78..22929ca019 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247fti_d52.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247fti_d52.h @@ -5,7 +5,7 @@ * CY8C6247FTI-D52 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -471,33 +471,9 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -507,9 +483,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -525,24 +510,39 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_80_wlcsp.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247wi_d54.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247wi_d54.h index 8c5cb07cda..a52d0601f2 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247wi_d54.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247wi_d54.h @@ -5,7 +5,7 @@ * CY8C6247WI-D54 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -471,33 +471,9 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -507,9 +483,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -525,24 +510,39 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_124_bga.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248azi_d14.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248azi_d14.h index 0bf271ac60..d6aafca4bf 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248azi_d14.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248azi_d14.h @@ -5,7 +5,7 @@ * CY8C6248AZI-D14 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -498,33 +498,9 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 13u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -534,36 +510,60 @@ typedef enum { #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 2u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 2u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_02_config.h" #include "gpio_psoc6_02_128_tqfp.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248azi_d44.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248azi_d44.h index 518bd64192..71d6c3cff0 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248azi_d44.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248azi_d44.h @@ -5,7 +5,7 @@ * CY8C6248AZI-D44 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -498,33 +498,9 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 13u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -537,36 +513,60 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 2u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 2u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_02_config.h" #include "gpio_psoc6_02_128_tqfp.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248azi_s2d14.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248azi_s2d14.h index e269123ca3..b72e5e696c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248azi_s2d14.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248azi_s2d14.h @@ -5,7 +5,7 @@ * CY8C6248AZI-S2D14 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -498,33 +498,9 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 13u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -534,42 +510,66 @@ typedef enum { #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 2u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 2u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_02_config.h" #include "gpio_psoc6_02_128_tqfp.h" #define CY_DEVICE_PSOC6A2M -#define CY_SILICON_ID 0xE4561102UL +#define CY_SILICON_ID 0xE4561202UL #define CY_HF_CLK_MAX_FREQ 150000000UL #define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248azi_s2d44.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248azi_s2d44.h index a940fe4ca1..40b3f817d7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248azi_s2d44.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248azi_s2d44.h @@ -5,7 +5,7 @@ * CY8C6248AZI-S2D44 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -498,33 +498,9 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 13u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -537,42 +513,66 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 2u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 2u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_02_config.h" #include "gpio_psoc6_02_128_tqfp.h" #define CY_DEVICE_PSOC6A2M -#define CY_SILICON_ID 0xE4581102UL +#define CY_SILICON_ID 0xE4581202UL #define CY_HF_CLK_MAX_FREQ 150000000UL #define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248bzi_d44.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248bzi_d44.h index a48712dcfd..bb3c195fb4 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248bzi_d44.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248bzi_d44.h @@ -5,7 +5,7 @@ * CY8C6248BZI-D44 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -498,33 +498,9 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 13u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -537,36 +513,60 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 2u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 2u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_02_config.h" #include "gpio_psoc6_02_124_bga.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248bzi_s2d44.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248bzi_s2d44.h index bd0213be30..421cd7744d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248bzi_s2d44.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248bzi_s2d44.h @@ -5,7 +5,7 @@ * CY8C6248BZI-S2D44 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -498,33 +498,9 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 13u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -537,42 +513,66 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 2u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 2u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_02_config.h" #include "gpio_psoc6_02_124_bga.h" #define CY_DEVICE_PSOC6A2M -#define CY_SILICON_ID 0xE4571102UL +#define CY_SILICON_ID 0xE4571202UL #define CY_HF_CLK_MAX_FREQ 150000000UL #define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248fni_d43.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248fni_d43.h index f8edfbda99..ce704005de 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248fni_d43.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248fni_d43.h @@ -5,7 +5,7 @@ * CY8C6248FNI-D43 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -498,33 +498,9 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 13u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -537,36 +513,60 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 2u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 2u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_02_config.h" #include "gpio_psoc6_02_100_wlcsp.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248fni_s2d43.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248fni_s2d43.h index 6b319f01cf..688f8994e6 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248fni_s2d43.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248fni_s2d43.h @@ -5,7 +5,7 @@ * CY8C6248FNI-S2D43 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -498,33 +498,9 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 13u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -537,42 +513,66 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 2u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 2u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_02_config.h" #include "gpio_psoc6_02_100_wlcsp.h" #define CY_DEVICE_PSOC6A2M -#define CY_SILICON_ID 0xE4591102UL +#define CY_SILICON_ID 0xE4591202UL #define CY_HF_CLK_MAX_FREQ 150000000UL #define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624aazi_d14.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624aazi_d14.h index 1ce42c13de..ee783fc545 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624aazi_d14.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624aazi_d14.h @@ -5,7 +5,7 @@ * CY8C624AAZI-D14 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -498,33 +498,9 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 13u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -534,36 +510,60 @@ typedef enum { #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 2u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 2u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_02_config.h" #include "gpio_psoc6_02_128_tqfp.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624aazi_d44.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624aazi_d44.h index 7b4f16f856..926bcf4555 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624aazi_d44.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624aazi_d44.h @@ -5,7 +5,7 @@ * CY8C624AAZI-D44 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -498,33 +498,9 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 13u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -537,36 +513,60 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 2u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 2u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_02_config.h" #include "gpio_psoc6_02_128_tqfp.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624aazi_s2d14.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624aazi_s2d14.h index 3867c46543..ed24eabf17 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624aazi_s2d14.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624aazi_s2d14.h @@ -5,7 +5,7 @@ * CY8C624AAZI-S2D14 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -498,33 +498,9 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 13u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -534,42 +510,66 @@ typedef enum { #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 2u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 2u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_02_config.h" #include "gpio_psoc6_02_128_tqfp.h" #define CY_DEVICE_PSOC6A2M -#define CY_SILICON_ID 0xE4521102UL +#define CY_SILICON_ID 0xE4521202UL #define CY_HF_CLK_MAX_FREQ 150000000UL #define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624aazi_s2d44.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624aazi_s2d44.h index d96817556a..d2684e625e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624aazi_s2d44.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624aazi_s2d44.h @@ -5,7 +5,7 @@ * CY8C624AAZI-S2D44 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -498,33 +498,9 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 13u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -537,42 +513,66 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 2u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 2u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_02_config.h" #include "gpio_psoc6_02_128_tqfp.h" #define CY_DEVICE_PSOC6A2M -#define CY_SILICON_ID 0xE4541102UL +#define CY_SILICON_ID 0xE4541202UL #define CY_HF_CLK_MAX_FREQ 150000000UL #define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_d04.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_d04.h index 3442371474..1651e60577 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_d04.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_d04.h @@ -5,7 +5,7 @@ * CY8C624ABZI-D04 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -498,33 +498,9 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 13u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -534,36 +510,60 @@ typedef enum { #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 2u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 2u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_02_config.h" #include "gpio_psoc6_02_124_bga.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_d14.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_d14.h index de4cf453ec..e23536f87b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_d14.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_d14.h @@ -5,7 +5,7 @@ * CY8C624ABZI-D14 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -498,33 +498,9 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 13u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -534,36 +510,60 @@ typedef enum { #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 2u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 2u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_02_config.h" #include "gpio_psoc6_02_124_bga.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_d44.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_d44.h index 789b68fc6a..62713cee3e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_d44.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_d44.h @@ -5,7 +5,7 @@ * CY8C624ABZI-D44 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -498,33 +498,9 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 13u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -537,36 +513,60 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 2u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 2u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_02_config.h" #include "gpio_psoc6_02_124_bga.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_s2d04.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_s2d04.h index 5d83053192..0a747caccb 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_s2d04.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_s2d04.h @@ -5,7 +5,7 @@ * CY8C624ABZI-S2D04 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -498,33 +498,9 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 13u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -534,42 +510,66 @@ typedef enum { #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 2u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 2u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_02_config.h" #include "gpio_psoc6_02_124_bga.h" #define CY_DEVICE_PSOC6A2M -#define CY_SILICON_ID 0xE4501102UL +#define CY_SILICON_ID 0xE4501202UL #define CY_HF_CLK_MAX_FREQ 150000000UL #define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_s2d14.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_s2d14.h index 37c2c628c0..305f7d2391 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_s2d14.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_s2d14.h @@ -5,7 +5,7 @@ * CY8C624ABZI-S2D14 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -498,33 +498,9 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 13u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -534,42 +510,66 @@ typedef enum { #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 2u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 2u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_02_config.h" #include "gpio_psoc6_02_124_bga.h" #define CY_DEVICE_PSOC6A2M -#define CY_SILICON_ID 0xE4511102UL +#define CY_SILICON_ID 0xE4511202UL #define CY_HF_CLK_MAX_FREQ 150000000UL #define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_s2d44.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_s2d44.h index 4e1d5613cb..c30199f639 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_s2d44.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_s2d44.h @@ -5,7 +5,7 @@ * CY8C624ABZI-S2D44 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -498,33 +498,9 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 13u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -537,42 +513,66 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 2u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 2u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_02_config.h" #include "gpio_psoc6_02_124_bga.h" #define CY_DEVICE_PSOC6A2M -#define CY_SILICON_ID 0xE4531102UL +#define CY_SILICON_ID 0xE4531202UL #define CY_HF_CLK_MAX_FREQ 150000000UL #define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_s2d44a0.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_s2d44a0.h index be92721b65..0eccaef7a4 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_s2d44a0.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_s2d44a0.h @@ -5,7 +5,7 @@ * CY8C624ABZI-S2D44A0 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -498,33 +498,9 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 13u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -537,36 +513,60 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 2u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 2u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_02_config.h" #include "gpio_psoc6_02_124_bga.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624afni_d43.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624afni_d43.h index cbd490e0eb..b43756d559 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624afni_d43.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624afni_d43.h @@ -5,7 +5,7 @@ * CY8C624AFNI-D43 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -498,33 +498,9 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 13u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -537,36 +513,60 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 2u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 2u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_02_config.h" #include "gpio_psoc6_02_100_wlcsp.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624afni_s2d43.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624afni_s2d43.h index 4fb52faadc..b957475870 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624afni_s2d43.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624afni_s2d43.h @@ -5,7 +5,7 @@ * CY8C624AFNI-S2D43 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -498,33 +498,9 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 13u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -537,42 +513,66 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 2u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 2u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_02_config.h" #include "gpio_psoc6_02_100_wlcsp.h" #define CY_DEVICE_PSOC6A2M -#define CY_SILICON_ID 0xE4551102UL +#define CY_SILICON_ID 0xE4551202UL #define CY_HF_CLK_MAX_FREQ 150000000UL #define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624alqi_d42.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624alqi_d42.h index 8e914645ef..0c4cfd449a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624alqi_d42.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624alqi_d42.h @@ -5,7 +5,7 @@ * CY8C624ALQI-D42 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -498,33 +498,9 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 13u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -537,36 +513,60 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 2u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 2u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_02_config.h" #include "gpio_psoc6_02_68_qfn.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6316bzi_blf03.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6316bzi_blf03.h index 1bb801a31f..b90a557d5b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6316bzi_blf03.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6316bzi_blf03.h @@ -5,7 +5,7 @@ * CY8C6316BZI-BLF03 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -246,45 +246,30 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -297,18 +282,33 @@ typedef enum { #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u #define CY_IP_MXS40PASS_CTDAC_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_116_bga_ble.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6316bzi_blf04.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6316bzi_blf04.h index b5475a7834..fa445dac1d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6316bzi_blf04.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6316bzi_blf04.h @@ -5,7 +5,7 @@ * CY8C6316BZI-BLF04 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -246,45 +246,30 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -297,21 +282,36 @@ typedef enum { #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u #define CY_IP_MXS40PASS_CTDAC_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_124_bga_sip.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6316bzi_blf53.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6316bzi_blf53.h index 96a82a3b51..7090b02439 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6316bzi_blf53.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6316bzi_blf53.h @@ -5,7 +5,7 @@ * CY8C6316BZI-BLF53 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -246,33 +246,12 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -282,12 +261,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -303,21 +288,36 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_116_bga_ble.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6316bzi_blf54.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6316bzi_blf54.h index a718fa3c42..66db34cf2e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6316bzi_blf54.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6316bzi_blf54.h @@ -5,7 +5,7 @@ * CY8C6316BZI-BLF54 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -246,33 +246,12 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -282,12 +261,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -303,24 +288,39 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_124_bga_sip.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336bzi_bld13.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336bzi_bld13.h index da964a150c..ffed7d0e0c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336bzi_bld13.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336bzi_bld13.h @@ -5,7 +5,7 @@ * CY8C6336BZI-BLD13 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -471,45 +471,30 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -522,18 +507,33 @@ typedef enum { #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u #define CY_IP_MXS40PASS_CTDAC_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_116_bga_ble.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336bzi_bld14.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336bzi_bld14.h index 8ab0c5fbcf..bba6cffa40 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336bzi_bld14.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336bzi_bld14.h @@ -5,7 +5,7 @@ * CY8C6336BZI-BLD14 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -471,45 +471,30 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -522,21 +507,36 @@ typedef enum { #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u #define CY_IP_MXS40PASS_CTDAC_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_124_bga_sip.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336bzi_blf03.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336bzi_blf03.h index a4f3344ead..e17764c398 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336bzi_blf03.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336bzi_blf03.h @@ -5,7 +5,7 @@ * CY8C6336BZI-BLF03 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -246,45 +246,30 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -297,18 +282,33 @@ typedef enum { #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u #define CY_IP_MXS40PASS_CTDAC_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_116_bga_ble.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336bzi_blf04.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336bzi_blf04.h index 17d7dd97c2..22b2e3d0ae 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336bzi_blf04.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336bzi_blf04.h @@ -5,7 +5,7 @@ * CY8C6336BZI-BLF04 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -246,45 +246,30 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -297,21 +282,36 @@ typedef enum { #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u #define CY_IP_MXS40PASS_CTDAC_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_124_bga_sip.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336bzi_bud13.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336bzi_bud13.h index 6cc693f496..e4f844d46e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336bzi_bud13.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336bzi_bud13.h @@ -5,7 +5,7 @@ * CY8C6336BZI-BUD13 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -471,45 +471,30 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -522,21 +507,36 @@ typedef enum { #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u #define CY_IP_MXS40PASS_CTDAC_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_116_bga_usb.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336lqi_blf02.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336lqi_blf02.h index 0e0cd80d89..8255d9cc56 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336lqi_blf02.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336lqi_blf02.h @@ -5,7 +5,7 @@ * CY8C6336LQI-BLF02 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -246,45 +246,30 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -297,18 +282,33 @@ typedef enum { #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u #define CY_IP_MXS40PASS_CTDAC_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_68_qfn_ble.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336lqi_blf42.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336lqi_blf42.h index 149b9b6092..652a3d8f6b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336lqi_blf42.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336lqi_blf42.h @@ -5,7 +5,7 @@ * CY8C6336LQI-BLF42 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -246,33 +246,12 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -282,12 +261,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -300,18 +285,33 @@ typedef enum { #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u #define CY_IP_MXS40PASS_CTDAC_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_68_qfn_ble.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6337bzi_blf13.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6337bzi_blf13.h index e6c0b087d5..1cd70d8fc0 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6337bzi_blf13.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6337bzi_blf13.h @@ -5,7 +5,7 @@ * CY8C6337BZI-BLF13 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -246,45 +246,30 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -297,18 +282,33 @@ typedef enum { #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u #define CY_IP_MXS40PASS_CTDAC_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_116_bga_ble.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld33.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld33.h index a3e84105b0..1989708c6d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld33.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld33.h @@ -5,7 +5,7 @@ * CY8C6347BZI-BLD33 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -471,45 +471,30 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -525,21 +510,36 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_116_bga_ble.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld34.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld34.h index 0a20b8d736..9499800b92 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld34.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld34.h @@ -5,7 +5,7 @@ * CY8C6347BZI-BLD34 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -471,45 +471,30 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -525,24 +510,39 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_124_bga_sip.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld43.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld43.h index 97c667d89b..22038ba5cb 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld43.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld43.h @@ -5,7 +5,7 @@ * CY8C6347BZI-BLD43 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -471,33 +471,12 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -507,12 +486,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -525,18 +510,33 @@ typedef enum { #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u #define CY_IP_MXS40PASS_CTDAC_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_116_bga_ble.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld44.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld44.h index 500ca63d6b..eefa5d26c8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld44.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld44.h @@ -5,7 +5,7 @@ * CY8C6347BZI-BLD44 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -471,33 +471,12 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -507,12 +486,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -525,21 +510,36 @@ typedef enum { #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u #define CY_IP_MXS40PASS_CTDAC_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_124_bga_sip.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld53.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld53.h index 438f2727e5..84e29a1511 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld53.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld53.h @@ -5,7 +5,7 @@ * CY8C6347BZI-BLD53 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -471,33 +471,12 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -507,12 +486,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -528,21 +513,36 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_116_bga_ble.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld54.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld54.h index e8189b720c..6e70c26a52 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld54.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld54.h @@ -5,7 +5,7 @@ * CY8C6347BZI-BLD54 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -471,33 +471,12 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -507,12 +486,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -528,24 +513,39 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_124_bga_sip.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bud33.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bud33.h index 9878c4c5b9..402957529e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bud33.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bud33.h @@ -5,7 +5,7 @@ * CY8C6347BZI-BUD33 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -471,45 +471,30 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -525,24 +510,39 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_116_bga_usb.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bud43.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bud43.h index 722601f5c1..8e1bdee8fe 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bud43.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bud43.h @@ -5,7 +5,7 @@ * CY8C6347BZI-BUD43 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -471,33 +471,12 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -507,12 +486,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -525,21 +510,36 @@ typedef enum { #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u #define CY_IP_MXS40PASS_CTDAC_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_116_bga_usb.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bud53.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bud53.h index 317f03391e..08ce89c475 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bud53.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bud53.h @@ -5,7 +5,7 @@ * CY8C6347BZI-BUD53 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -471,33 +471,12 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -507,12 +486,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -528,24 +513,39 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_116_bga_usb.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bld13.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bld13.h index c27a825f02..d647245770 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bld13.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bld13.h @@ -5,7 +5,7 @@ * CY8C6347FMI-BLD13 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -471,45 +471,30 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -522,18 +507,33 @@ typedef enum { #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u #define CY_IP_MXS40PASS_CTDAC_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_104_m_csp_ble.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bld33.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bld33.h index 55dea4a90e..80c44d62b8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bld33.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bld33.h @@ -5,7 +5,7 @@ * CY8C6347FMI-BLD33 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -471,45 +471,30 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -525,21 +510,36 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_104_m_csp_ble.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bld43.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bld43.h index 5c1f73feea..ac8e465794 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bld43.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bld43.h @@ -5,7 +5,7 @@ * CY8C6347FMI-BLD43 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -471,33 +471,12 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -507,12 +486,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -525,18 +510,33 @@ typedef enum { #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u #define CY_IP_MXS40PASS_CTDAC_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_104_m_csp_ble.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bld53.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bld53.h index 3481003d28..1051f9ed75 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bld53.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bld53.h @@ -5,7 +5,7 @@ * CY8C6347FMI-BLD53 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -471,33 +471,12 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -507,12 +486,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -528,21 +513,36 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_104_m_csp_ble.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bud13.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bud13.h index 560ef18678..9c574a3ff0 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bud13.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bud13.h @@ -5,7 +5,7 @@ * CY8C6347FMI-BUD13 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -471,45 +471,30 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -522,21 +507,36 @@ typedef enum { #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u #define CY_IP_MXS40PASS_CTDAC_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_104_m_csp_ble_usb.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bud33.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bud33.h index 03a38dae2d..537c5fbfcf 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bud33.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bud33.h @@ -5,7 +5,7 @@ * CY8C6347FMI-BUD33 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -471,45 +471,30 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -525,24 +510,39 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_104_m_csp_ble_usb.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bud43.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bud43.h index 0d72acc2db..6037d7c552 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bud43.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bud43.h @@ -5,7 +5,7 @@ * CY8C6347FMI-BUD43 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -471,33 +471,12 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -507,12 +486,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -525,21 +510,36 @@ typedef enum { #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u #define CY_IP_MXS40PASS_CTDAC_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_104_m_csp_ble_usb.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bud53.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bud53.h index de66e83332..10de9278ae 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bud53.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bud53.h @@ -5,7 +5,7 @@ * CY8C6347FMI-BUD53 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -471,33 +471,12 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -507,12 +486,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -528,24 +513,39 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_104_m_csp_ble_usb.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347lqi_bld52.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347lqi_bld52.h index 197da0a02c..0d4296de53 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347lqi_bld52.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347lqi_bld52.h @@ -5,7 +5,7 @@ * CY8C6347LQI-BLD52 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -471,33 +471,12 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -507,12 +486,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -528,21 +513,36 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_68_qfn_ble.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c637bzi_bld74.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c637bzi_bld74.h index 5e8c31951e..dc97f7bb37 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c637bzi_bld74.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c637bzi_bld74.h @@ -5,7 +5,7 @@ * CY8C637BZI-BLD74 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -471,33 +471,12 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -507,12 +486,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -528,21 +513,36 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_116_bga_ble.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c637bzi_md76.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c637bzi_md76.h index bcf47ca415..62106365ad 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c637bzi_md76.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c637bzi_md76.h @@ -5,7 +5,7 @@ * CY8C637BZI-MD76 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -471,33 +471,9 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -507,9 +483,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -525,24 +510,39 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_124_bga.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c637fmi_bld73.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c637fmi_bld73.h index 1f1bfd0f08..3603203c1f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c637fmi_bld73.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c637fmi_bld73.h @@ -5,7 +5,7 @@ * CY8C637FMI-BLD73 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -471,33 +471,12 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -507,12 +486,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -528,21 +513,36 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_104_m_csp_ble.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c68237bz_ble.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c68237bz_ble.h index 0e055e75f0..31a7a74b45 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c68237bz_ble.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c68237bz_ble.h @@ -5,7 +5,7 @@ * CY8C68237BZ-BLE device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -471,33 +471,12 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -507,30 +486,51 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_116_bga_ble.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c68237fm_ble.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c68237fm_ble.h index 8fa8a5ab17..8ea27b85b3 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c68237fm_ble.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c68237fm_ble.h @@ -5,7 +5,7 @@ * CY8C68237FM-BLE device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -471,33 +471,12 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -507,30 +486,51 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_104_m_csp_ble.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy_device_headers.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy_device_headers.h index 80384ff325..f172d53492 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy_device_headers.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy_device_headers.h @@ -5,7 +5,7 @@ * Common header file to be included by the drivers. * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -160,28 +160,6 @@ #include "cyb06447bzi_bld53.h" #elif defined (CYB06447BZI_D54) #include "cyb06447bzi_d54.h" -#elif defined (CY8C624ABZI_D44) - #include "cy8c624abzi_d44.h" -#elif defined (CY8C624AAZI_D44) - #include "cy8c624aazi_d44.h" -#elif defined (CY8C624AFNI_D43) - #include "cy8c624afni_d43.h" -#elif defined (CY8C624ABZI_D04) - #include "cy8c624abzi_d04.h" -#elif defined (CY8C624ABZI_D14) - #include "cy8c624abzi_d14.h" -#elif defined (CY8C624AAZI_D14) - #include "cy8c624aazi_d14.h" -#elif defined (CY8C6248AZI_D14) - #include "cy8c6248azi_d14.h" -#elif defined (CY8C6248BZI_D44) - #include "cy8c6248bzi_d44.h" -#elif defined (CY8C6248AZI_D44) - #include "cy8c6248azi_d44.h" -#elif defined (CY8C6248FNI_D43) - #include "cy8c6248fni_d43.h" -#elif defined (CY8C624ALQI_D42) - #include "cy8c624alqi_d42.h" #elif defined (CYB0644ABZI_S2D44) #include "cyb0644abzi_s2d44.h" #elif defined (CYS0644ABZI_S2D44) @@ -208,6 +186,48 @@ #include "cy8c6248azi_s2d44.h" #elif defined (CY8C6248FNI_S2D43) #include "cy8c6248fni_s2d43.h" +#elif defined (CY8C614ABZI_S2F04) + #include "cy8c614abzi_s2f04.h" +#elif defined (CY8C614AAZI_S2F04) + #include "cy8c614aazi_s2f04.h" +#elif defined (CY8C614AFNI_S2F03) + #include "cy8c614afni_s2f03.h" +#elif defined (CY8C614AAZI_S2F14) + #include "cy8c614aazi_s2f14.h" +#elif defined (CY8C614ABZI_S2F44) + #include "cy8c614abzi_s2f44.h" +#elif defined (CY8C614AAZI_S2F44) + #include "cy8c614aazi_s2f44.h" +#elif defined (CY8C614AFNI_S2F43) + #include "cy8c614afni_s2f43.h" +#elif defined (CY8C6148BZI_S2F44) + #include "cy8c6148bzi_s2f44.h" +#elif defined (CY8C6148AZI_S2F44) + #include "cy8c6148azi_s2f44.h" +#elif defined (CY8C6148FNI_S2F43) + #include "cy8c6148fni_s2f43.h" +#elif defined (CY8C624ABZI_D44) + #include "cy8c624abzi_d44.h" +#elif defined (CY8C624AAZI_D44) + #include "cy8c624aazi_d44.h" +#elif defined (CY8C624AFNI_D43) + #include "cy8c624afni_d43.h" +#elif defined (CY8C624ABZI_D04) + #include "cy8c624abzi_d04.h" +#elif defined (CY8C624ABZI_D14) + #include "cy8c624abzi_d14.h" +#elif defined (CY8C624AAZI_D14) + #include "cy8c624aazi_d14.h" +#elif defined (CY8C6248AZI_D14) + #include "cy8c6248azi_d14.h" +#elif defined (CY8C6248BZI_D44) + #include "cy8c6248bzi_d44.h" +#elif defined (CY8C6248AZI_D44) + #include "cy8c6248azi_d44.h" +#elif defined (CY8C6248FNI_D43) + #include "cy8c6248fni_d43.h" +#elif defined (CY8C624ALQI_D42) + #include "cy8c624alqi_d42.h" #elif defined (CY8C6245AZI_S3D72) #include "cy8c6245azi_s3d72.h" #elif defined (CY8C6245LQI_S3D72) @@ -236,8 +256,32 @@ #include "cy8c6245azi_s3d02.h" #elif defined (CY8C6245LQI_S3D02) #include "cy8c6245lqi_s3d02.h" -#elif defined (CY8C6245W_S3D72) - #include "cy8c6245w_s3d72.h" +#elif defined (CY8C6145AZI_S3F72) + #include "cy8c6145azi_s3f72.h" +#elif defined (CY8C6145LQI_S3F72) + #include "cy8c6145lqi_s3f72.h" +#elif defined (CY8C6145FNI_S3F71) + #include "cy8c6145fni_s3f71.h" +#elif defined (CY8C6145AZI_S3F62) + #include "cy8c6145azi_s3f62.h" +#elif defined (CY8C6145LQI_S3F62) + #include "cy8c6145lqi_s3f62.h" +#elif defined (CY8C6145AZI_S3F42) + #include "cy8c6145azi_s3f42.h" +#elif defined (CY8C6145LQI_S3F42) + #include "cy8c6145lqi_s3f42.h" +#elif defined (CY8C6145FNI_S3F41) + #include "cy8c6145fni_s3f41.h" +#elif defined (CY8C6145AZI_S3F12) + #include "cy8c6145azi_s3f12.h" +#elif defined (CY8C6145LQI_S3F12) + #include "cy8c6145lqi_s3f12.h" +#elif defined (CY8C6145FNI_S3F11) + #include "cy8c6145fni_s3f11.h" +#elif defined (CY8C6145AZI_S3F02) + #include "cy8c6145azi_s3f02.h" +#elif defined (CY8C6145LQI_S3F02) + #include "cy8c6145lqi_s3f02.h" #elif defined (CY8C6244AZI_S4D92) #include "cy8c6244azi_s4d92.h" #elif defined (CY8C6244LQI_S4D92) @@ -266,6 +310,26 @@ #include "cy8c4588azi_h675.h" #elif defined (CY8C4588AZI_H676) #include "cy8c4588azi_h676.h" +#elif defined (CY8C6144AZI_S4F92) + #include "cy8c6144azi_s4f92.h" +#elif defined (CY8C6144LQI_S4F92) + #include "cy8c6144lqi_s4f92.h" +#elif defined (CY8C6144AZI_S4F93) + #include "cy8c6144azi_s4f93.h" +#elif defined (CY8C6144AZI_S4F82) + #include "cy8c6144azi_s4f82.h" +#elif defined (CY8C6144LQI_S4F82) + #include "cy8c6144lqi_s4f82.h" +#elif defined (CY8C6144AZI_S4F83) + #include "cy8c6144azi_s4f83.h" +#elif defined (CY8C6144AZI_S4F62) + #include "cy8c6144azi_s4f62.h" +#elif defined (CY8C6144LQI_S4F62) + #include "cy8c6144lqi_s4f62.h" +#elif defined (CY8C6144AZI_S4F12) + #include "cy8c6144azi_s4f12.h" +#elif defined (CY8C6144LQI_S4F12) + #include "cy8c6144lqi_s4f12.h" #else #include "cy_device_common.h" #endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06445lqi_s3d42.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06445lqi_s3d42.h index 95a3807fa6..daee6ad7ff 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06445lqi_s3d42.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06445lqi_s3d42.h @@ -5,7 +5,7 @@ * CYB06445LQI-S3D42 device header * * \note -* Generator version: 1.6.0.215 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -438,33 +438,9 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 2u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 7u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -477,33 +453,57 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 1u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXTTCANFD 1u -#define CY_IP_MXTTCANFD_INSTANCES 1u -#define CY_IP_MXTTCANFD_VERSION 1u -#define CY_IP_MXLPCOMP 1u -#define CY_IP_MXLPCOMP_INSTANCES 1u -#define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u #define CY_IP_MXS40IOSS 1u #define CY_IP_MXS40IOSS_INSTANCES 1u #define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_03_config.h" #include "gpio_psoc6_03_68_qfn.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06447bzi_bld53.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06447bzi_bld53.h index db611a3787..6d2a478bfc 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06447bzi_bld53.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06447bzi_bld53.h @@ -5,7 +5,7 @@ * CYB06447BZI-BLD53 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -471,33 +471,12 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -507,12 +486,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -528,21 +513,36 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_116_bga_ble.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06447bzi_bld54.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06447bzi_bld54.h index d67bdc02cf..db5b772f49 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06447bzi_bld54.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06447bzi_bld54.h @@ -5,7 +5,7 @@ * CYB06447BZI-BLD54 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -471,33 +471,12 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -507,12 +486,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -528,24 +513,39 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_124_bga_sip.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06447bzi_d54.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06447bzi_d54.h index d5a7ec21f3..35a18b84f0 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06447bzi_d54.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06447bzi_d54.h @@ -5,7 +5,7 @@ * CYB06447BZI-D54 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -471,33 +471,9 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -507,9 +483,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -525,24 +510,39 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_124_bga.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb0644abzi_s2d44.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb0644abzi_s2d44.h index 7b87b6c156..2cd05d31af 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb0644abzi_s2d44.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb0644abzi_s2d44.h @@ -5,7 +5,7 @@ * CYB0644ABZI-S2D44 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -498,33 +498,9 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 13u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -537,36 +513,60 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 2u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 2u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_02_config.h" #include "gpio_psoc6_02_124_bga.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyble_416045_02.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyble_416045_02.h index 78087e463f..b96cf11de6 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyble_416045_02.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyble_416045_02.h @@ -5,7 +5,7 @@ * CYBLE-416045-02 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -471,33 +471,12 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -507,12 +486,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -528,18 +513,33 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_43_smt.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cys0644abzi_s2d44.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cys0644abzi_s2d44.h index 435d0e3a07..34d04241df 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cys0644abzi_s2d44.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cys0644abzi_s2d44.h @@ -5,7 +5,7 @@ * CYS0644ABZI-S2D44 device header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -498,33 +498,9 @@ typedef enum { #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 13u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -537,36 +513,60 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 2u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 2u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_02_config.h" #include "gpio_psoc6_02_124_bga.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_104_m_csp_ble.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_104_m_csp_ble.h index ab43a2f532..7fb0f99d57 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_104_m_csp_ble.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_104_m_csp_ble.h @@ -5,11 +5,11 @@ * PSoC6_01 device GPIO header for 104-M-CSP-BLE package * * \note -* Generator version: 1.5.0.1304 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -46,16 +46,16 @@ enum /* AMUXBUS Segments */ enum { - AMUXBUS_MAIN, AMUXBUS_ADFT0_VDDD, - AMUXBUS_NOISY, AMUXBUS_ADFT1_VDDD, - AMUXBUS_CSD0, - AMUXBUS_VDDIO_1, - AMUXBUS_CSD1, - AMUXBUS_SAR, - AMUXBUS_ANALOG_VDDD, AMUXBUS_ANALOG_VDDA, + AMUXBUS_ANALOG_VDDD, + AMUXBUS_CSD0, + AMUXBUS_CSD1, + AMUXBUS_MAIN, + AMUXBUS_NOISY, + AMUXBUS_SAR, + AMUXBUS_VDDIO_1, }; /* AMUX Splitter Controls */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_104_m_csp_ble_usb.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_104_m_csp_ble_usb.h index cc8661211b..728c8bcd12 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_104_m_csp_ble_usb.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_104_m_csp_ble_usb.h @@ -5,11 +5,11 @@ * PSoC6_01 device GPIO header for 104-M-CSP-BLE-USB package * * \note -* Generator version: 1.5.0.1304 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -46,16 +46,16 @@ enum /* AMUXBUS Segments */ enum { - AMUXBUS_MAIN, AMUXBUS_ADFT0_VDDD, - AMUXBUS_NOISY, AMUXBUS_ADFT1_VDDD, - AMUXBUS_CSD0, - AMUXBUS_VDDIO_1, - AMUXBUS_CSD1, - AMUXBUS_SAR, - AMUXBUS_ANALOG_VDDD, AMUXBUS_ANALOG_VDDA, + AMUXBUS_ANALOG_VDDD, + AMUXBUS_CSD0, + AMUXBUS_CSD1, + AMUXBUS_MAIN, + AMUXBUS_NOISY, + AMUXBUS_SAR, + AMUXBUS_VDDIO_1, }; /* AMUX Splitter Controls */ @@ -669,12 +669,6 @@ typedef enum P1_5_LCD_SEG11 = 13, /* Digital Deep Sleep - lcd.seg[11]:0 */ P1_5_SCB7_SPI_SELECT2 = 20, /* Digital Active - scb[7].spi_select2:0 */ - /* USBDM */ - USBDM_GPIO = 0, /* GPIO controls 'out' */ - - /* USBDP */ - USBDP_GPIO = 0, /* GPIO controls 'out' */ - /* P5.0 */ P5_0_GPIO = 0, /* GPIO controls 'out' */ P5_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ @@ -1822,7 +1816,13 @@ typedef enum P13_1_SCB6_UART_TX = 18, /* Digital Active - scb[6].uart_tx:1 */ P13_1_SCB6_I2C_SDA = 19, /* Digital Active - scb[6].i2c_sda:1 */ P13_1_SCB6_SPI_MISO = 20, /* Digital Active - scb[6].spi_miso:1 */ - P13_1_PERI_TR_IO_INPUT27 = 24 /* Digital Active - peri.tr_io_input[27]:0 */ + P13_1_PERI_TR_IO_INPUT27 = 24, /* Digital Active - peri.tr_io_input[27]:0 */ + + /* USBDP */ + USBDP_GPIO = 0, /* GPIO controls 'out' */ + + /* USBDM */ + USBDM_GPIO = 0 /* GPIO controls 'out' */ } en_hsiom_sel_t; #endif /* _GPIO_PSOC6_01_104_M_CSP_BLE_USB_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_116_bga_ble.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_116_bga_ble.h index 2c9b4f4532..9e7a36c19d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_116_bga_ble.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_116_bga_ble.h @@ -5,11 +5,11 @@ * PSoC6_01 device GPIO header for 116-BGA-BLE package * * \note -* Generator version: 1.5.0.1304 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -46,16 +46,16 @@ enum /* AMUXBUS Segments */ enum { - AMUXBUS_MAIN, AMUXBUS_ADFT0_VDDD, - AMUXBUS_NOISY, AMUXBUS_ADFT1_VDDD, - AMUXBUS_CSD0, - AMUXBUS_VDDIO_1, - AMUXBUS_CSD1, - AMUXBUS_SAR, - AMUXBUS_ANALOG_VDDD, AMUXBUS_ANALOG_VDDA, + AMUXBUS_ANALOG_VDDD, + AMUXBUS_CSD0, + AMUXBUS_CSD1, + AMUXBUS_MAIN, + AMUXBUS_NOISY, + AMUXBUS_SAR, + AMUXBUS_VDDIO_1, }; /* AMUX Splitter Controls */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_116_bga_usb.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_116_bga_usb.h index 08e39964d2..5ca4427fe7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_116_bga_usb.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_116_bga_usb.h @@ -5,11 +5,11 @@ * PSoC6_01 device GPIO header for 116-BGA-USB package * * \note -* Generator version: 1.5.0.1304 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -46,16 +46,16 @@ enum /* AMUXBUS Segments */ enum { - AMUXBUS_MAIN, AMUXBUS_ADFT0_VDDD, - AMUXBUS_NOISY, AMUXBUS_ADFT1_VDDD, - AMUXBUS_CSD0, - AMUXBUS_VDDIO_1, - AMUXBUS_CSD1, - AMUXBUS_SAR, - AMUXBUS_ANALOG_VDDD, AMUXBUS_ANALOG_VDDA, + AMUXBUS_ANALOG_VDDD, + AMUXBUS_CSD0, + AMUXBUS_CSD1, + AMUXBUS_MAIN, + AMUXBUS_NOISY, + AMUXBUS_SAR, + AMUXBUS_VDDIO_1, }; /* AMUX Splitter Controls */ @@ -687,12 +687,6 @@ typedef enum P1_2_SCB7_UART_RTS = 18, /* Digital Active - scb[7].uart_rts:0 */ P1_2_SCB7_SPI_CLK = 20, /* Digital Active - scb[7].spi_clk:0 */ - /* USBDM */ - USBDM_GPIO = 0, /* GPIO controls 'out' */ - - /* USBDP */ - USBDP_GPIO = 0, /* GPIO controls 'out' */ - /* P5.0 */ P5_0_GPIO = 0, /* GPIO controls 'out' */ P5_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ @@ -1959,7 +1953,13 @@ typedef enum P13_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:100 */ P13_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:100 */ P13_7_LCD_COM38 = 12, /* Digital Deep Sleep - lcd.com[38]:1 */ - P13_7_LCD_SEG38 = 13 /* Digital Deep Sleep - lcd.seg[38]:1 */ + P13_7_LCD_SEG38 = 13, /* Digital Deep Sleep - lcd.seg[38]:1 */ + + /* USBDP */ + USBDP_GPIO = 0, /* GPIO controls 'out' */ + + /* USBDM */ + USBDM_GPIO = 0 /* GPIO controls 'out' */ } en_hsiom_sel_t; #endif /* _GPIO_PSOC6_01_116_BGA_USB_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_124_bga.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_124_bga.h index f1f07c9a78..37af035c25 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_124_bga.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_124_bga.h @@ -5,11 +5,11 @@ * PSoC6_01 device GPIO header for 124-BGA package * * \note -* Generator version: 1.5.0.1304 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -46,16 +46,16 @@ enum /* AMUXBUS Segments */ enum { - AMUXBUS_MAIN, AMUXBUS_ADFT0_VDDD, - AMUXBUS_NOISY, AMUXBUS_ADFT1_VDDD, - AMUXBUS_CSD0, - AMUXBUS_VDDIO_1, - AMUXBUS_CSD1, - AMUXBUS_SAR, - AMUXBUS_ANALOG_VDDD, AMUXBUS_ANALOG_VDDA, + AMUXBUS_ANALOG_VDDD, + AMUXBUS_CSD0, + AMUXBUS_CSD1, + AMUXBUS_MAIN, + AMUXBUS_NOISY, + AMUXBUS_SAR, + AMUXBUS_VDDIO_1, }; /* AMUX Splitter Controls */ @@ -849,12 +849,6 @@ typedef enum P1_5_LCD_SEG11 = 13, /* Digital Deep Sleep - lcd.seg[11]:0 */ P1_5_SCB7_SPI_SELECT2 = 20, /* Digital Active - scb[7].spi_select2:0 */ - /* USBDM */ - USBDM_GPIO = 0, /* GPIO controls 'out' */ - - /* USBDP */ - USBDP_GPIO = 0, /* GPIO controls 'out' */ - /* P2.0 */ P2_0_GPIO = 0, /* GPIO controls 'out' */ P2_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ @@ -2533,7 +2527,13 @@ typedef enum P13_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:100 */ P13_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:100 */ P13_7_LCD_COM38 = 12, /* Digital Deep Sleep - lcd.com[38]:1 */ - P13_7_LCD_SEG38 = 13 /* Digital Deep Sleep - lcd.seg[38]:1 */ + P13_7_LCD_SEG38 = 13, /* Digital Deep Sleep - lcd.seg[38]:1 */ + + /* USBDP */ + USBDP_GPIO = 0, /* GPIO controls 'out' */ + + /* USBDM */ + USBDM_GPIO = 0 /* GPIO controls 'out' */ } en_hsiom_sel_t; #endif /* _GPIO_PSOC6_01_124_BGA_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_124_bga_sip.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_124_bga_sip.h index 15c7230c50..303f0706ce 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_124_bga_sip.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_124_bga_sip.h @@ -5,11 +5,11 @@ * PSoC6_01 device GPIO header for 124-BGA-SIP package * * \note -* Generator version: 1.5.0.1304 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -46,16 +46,16 @@ enum /* AMUXBUS Segments */ enum { - AMUXBUS_MAIN, AMUXBUS_ADFT0_VDDD, - AMUXBUS_NOISY, AMUXBUS_ADFT1_VDDD, - AMUXBUS_CSD0, - AMUXBUS_VDDIO_1, - AMUXBUS_CSD1, - AMUXBUS_SAR, - AMUXBUS_ANALOG_VDDD, AMUXBUS_ANALOG_VDDA, + AMUXBUS_ANALOG_VDDD, + AMUXBUS_CSD0, + AMUXBUS_CSD1, + AMUXBUS_MAIN, + AMUXBUS_NOISY, + AMUXBUS_SAR, + AMUXBUS_VDDIO_1, }; /* AMUX Splitter Controls */ @@ -779,12 +779,6 @@ typedef enum P1_5_LCD_SEG11 = 13, /* Digital Deep Sleep - lcd.seg[11]:0 */ P1_5_SCB7_SPI_SELECT2 = 20, /* Digital Active - scb[7].spi_select2:0 */ - /* USBDM */ - USBDM_GPIO = 0, /* GPIO controls 'out' */ - - /* USBDP */ - USBDP_GPIO = 0, /* GPIO controls 'out' */ - /* P5.0 */ P5_0_GPIO = 0, /* GPIO controls 'out' */ P5_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ @@ -2154,7 +2148,13 @@ typedef enum P13_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:100 */ P13_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:100 */ P13_7_LCD_COM38 = 12, /* Digital Deep Sleep - lcd.com[38]:1 */ - P13_7_LCD_SEG38 = 13 /* Digital Deep Sleep - lcd.seg[38]:1 */ + P13_7_LCD_SEG38 = 13, /* Digital Deep Sleep - lcd.seg[38]:1 */ + + /* USBDP */ + USBDP_GPIO = 0, /* GPIO controls 'out' */ + + /* USBDM */ + USBDM_GPIO = 0 /* GPIO controls 'out' */ } en_hsiom_sel_t; #endif /* _GPIO_PSOC6_01_124_BGA_SIP_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_43_smt.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_43_smt.h index fca88f2943..dae2d3d3b4 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_43_smt.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_43_smt.h @@ -5,11 +5,11 @@ * PSoC6_01 device GPIO header for 43-SMT package * * \note -* Generator version: 1.5.0.1304 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -46,16 +46,16 @@ enum /* AMUXBUS Segments */ enum { - AMUXBUS_MAIN, AMUXBUS_ADFT0_VDDD, - AMUXBUS_NOISY, AMUXBUS_ADFT1_VDDD, - AMUXBUS_CSD0, - AMUXBUS_VDDIO_1, - AMUXBUS_CSD1, - AMUXBUS_SAR, - AMUXBUS_ANALOG_VDDD, AMUXBUS_ANALOG_VDDA, + AMUXBUS_ANALOG_VDDD, + AMUXBUS_CSD0, + AMUXBUS_CSD1, + AMUXBUS_MAIN, + AMUXBUS_NOISY, + AMUXBUS_SAR, + AMUXBUS_VDDIO_1, }; /* AMUX Splitter Controls */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_68_qfn_ble.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_68_qfn_ble.h index 2719e9bda0..a0861f58ca 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_68_qfn_ble.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_68_qfn_ble.h @@ -5,11 +5,11 @@ * PSoC6_01 device GPIO header for 68-QFN-BLE package * * \note -* Generator version: 1.5.0.1304 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -46,16 +46,16 @@ enum /* AMUXBUS Segments */ enum { - AMUXBUS_MAIN, AMUXBUS_ADFT0_VDDD, - AMUXBUS_NOISY, AMUXBUS_ADFT1_VDDD, - AMUXBUS_CSD0, - AMUXBUS_VDDIO_1, - AMUXBUS_CSD1, - AMUXBUS_SAR, - AMUXBUS_ANALOG_VDDD, AMUXBUS_ANALOG_VDDA, + AMUXBUS_ANALOG_VDDD, + AMUXBUS_CSD0, + AMUXBUS_CSD1, + AMUXBUS_MAIN, + AMUXBUS_NOISY, + AMUXBUS_SAR, + AMUXBUS_VDDIO_1, }; /* AMUX Splitter Controls */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_80_wlcsp.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_80_wlcsp.h index 09f3677beb..983e926b14 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_80_wlcsp.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_80_wlcsp.h @@ -5,11 +5,11 @@ * PSoC6_01 device GPIO header for 80-WLCSP package * * \note -* Generator version: 1.5.0.1304 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -46,16 +46,16 @@ enum /* AMUXBUS Segments */ enum { - AMUXBUS_MAIN, AMUXBUS_ADFT0_VDDD, - AMUXBUS_NOISY, AMUXBUS_ADFT1_VDDD, - AMUXBUS_CSD0, - AMUXBUS_VDDIO_1, - AMUXBUS_CSD1, - AMUXBUS_SAR, - AMUXBUS_ANALOG_VDDD, AMUXBUS_ANALOG_VDDA, + AMUXBUS_ANALOG_VDDD, + AMUXBUS_CSD0, + AMUXBUS_CSD1, + AMUXBUS_MAIN, + AMUXBUS_NOISY, + AMUXBUS_SAR, + AMUXBUS_VDDIO_1, }; /* AMUX Splitter Controls */ @@ -641,12 +641,6 @@ typedef enum P1_5_LCD_SEG11 = 13, /* Digital Deep Sleep - lcd.seg[11]:0 */ P1_5_SCB7_SPI_SELECT2 = 20, /* Digital Active - scb[7].spi_select2:0 */ - /* USBDM */ - USBDM_GPIO = 0, /* GPIO controls 'out' */ - - /* USBDP */ - USBDP_GPIO = 0, /* GPIO controls 'out' */ - /* P5.0 */ P5_0_GPIO = 0, /* GPIO controls 'out' */ P5_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ @@ -1660,7 +1654,13 @@ typedef enum P12_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:92 */ P12_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:92 */ P12_7_LCD_COM30 = 12, /* Digital Deep Sleep - lcd.com[30]:1 */ - P12_7_LCD_SEG30 = 13 /* Digital Deep Sleep - lcd.seg[30]:1 */ + P12_7_LCD_SEG30 = 13, /* Digital Deep Sleep - lcd.seg[30]:1 */ + + /* USBDP */ + USBDP_GPIO = 0, /* GPIO controls 'out' */ + + /* USBDM */ + USBDM_GPIO = 0 /* GPIO controls 'out' */ } en_hsiom_sel_t; #endif /* _GPIO_PSOC6_01_80_WLCSP_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_02_100_wlcsp.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_02_100_wlcsp.h index e675fde8c5..0011261e4c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_02_100_wlcsp.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_02_100_wlcsp.h @@ -5,11 +5,11 @@ * PSoC6_02 device GPIO header for 100-WLCSP package * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -46,15 +46,15 @@ enum /* AMUXBUS Segments */ enum { - AMUXBUS_MAIN, AMUXBUS_ADFT0_VDDD, - AMUXBUS_NOISY, - AMUXBUS_CSD0, - AMUXBUS_VDDIO_1, - AMUXBUS_CSD1, - AMUXBUS_SAR, - AMUXBUS_ANALOG_VDDD, AMUXBUS_ANALOG_VDDA, + AMUXBUS_ANALOG_VDDD, + AMUXBUS_CSD0, + AMUXBUS_CSD1, + AMUXBUS_MAIN, + AMUXBUS_NOISY, + AMUXBUS_SAR, + AMUXBUS_VDDIO_1, }; /* AMUX Splitter Controls */ @@ -685,12 +685,6 @@ typedef enum P1_5_LCD_SEG11 = 13, /* Digital Deep Sleep - lcd.seg[11]:0 */ P1_5_SCB7_SPI_SELECT2 = 20, /* Digital Active - scb[7].spi_select2:0 */ - /* USBDM */ - USBDM_GPIO = 0, /* GPIO controls 'out' */ - - /* USBDP */ - USBDP_GPIO = 0, /* GPIO controls 'out' */ - /* P2.0 */ P2_0_GPIO = 0, /* GPIO controls 'out' */ P2_0_AMUXA = 4, /* Analog mux bus A */ @@ -1895,7 +1889,13 @@ typedef enum P13_7_LCD_COM38 = 12, /* Digital Deep Sleep - lcd.com[38]:1 */ P13_7_LCD_SEG38 = 13, /* Digital Deep Sleep - lcd.seg[38]:1 */ P13_7_SCB12_UART_CTS = 18, /* Digital Active - scb[12].uart_cts:0 */ - P13_7_SDHC1_CARD_DAT_7TO43 = 26 /* Digital Active - sdhc[1].card_dat_7to4[3] */ + P13_7_SDHC1_CARD_DAT_7TO43 = 26, /* Digital Active - sdhc[1].card_dat_7to4[3] */ + + /* USBDP */ + USBDP_GPIO = 0, /* GPIO controls 'out' */ + + /* USBDM */ + USBDM_GPIO = 0 /* GPIO controls 'out' */ } en_hsiom_sel_t; #endif /* _GPIO_PSOC6_02_100_WLCSP_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_02_124_bga.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_02_124_bga.h index a130bc75b2..2c31a3c7f6 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_02_124_bga.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_02_124_bga.h @@ -5,11 +5,11 @@ * PSoC6_02 device GPIO header for 124-BGA package * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -46,15 +46,15 @@ enum /* AMUXBUS Segments */ enum { - AMUXBUS_MAIN, AMUXBUS_ADFT0_VDDD, - AMUXBUS_NOISY, - AMUXBUS_CSD0, - AMUXBUS_VDDIO_1, - AMUXBUS_CSD1, - AMUXBUS_SAR, - AMUXBUS_ANALOG_VDDD, AMUXBUS_ANALOG_VDDA, + AMUXBUS_ANALOG_VDDD, + AMUXBUS_CSD0, + AMUXBUS_CSD1, + AMUXBUS_MAIN, + AMUXBUS_NOISY, + AMUXBUS_SAR, + AMUXBUS_VDDIO_1, }; /* AMUX Splitter Controls */ @@ -791,12 +791,6 @@ typedef enum P1_5_LCD_SEG11 = 13, /* Digital Deep Sleep - lcd.seg[11]:0 */ P1_5_SCB7_SPI_SELECT2 = 20, /* Digital Active - scb[7].spi_select2:0 */ - /* USBDM */ - USBDM_GPIO = 0, /* GPIO controls 'out' */ - - /* USBDP */ - USBDP_GPIO = 0, /* GPIO controls 'out' */ - /* P2.0 */ P2_0_GPIO = 0, /* GPIO controls 'out' */ P2_0_AMUXA = 4, /* Analog mux bus A */ @@ -2250,7 +2244,13 @@ typedef enum P13_7_LCD_COM38 = 12, /* Digital Deep Sleep - lcd.com[38]:1 */ P13_7_LCD_SEG38 = 13, /* Digital Deep Sleep - lcd.seg[38]:1 */ P13_7_SCB12_UART_CTS = 18, /* Digital Active - scb[12].uart_cts:0 */ - P13_7_SDHC1_CARD_DAT_7TO43 = 26 /* Digital Active - sdhc[1].card_dat_7to4[3] */ + P13_7_SDHC1_CARD_DAT_7TO43 = 26, /* Digital Active - sdhc[1].card_dat_7to4[3] */ + + /* USBDP */ + USBDP_GPIO = 0, /* GPIO controls 'out' */ + + /* USBDM */ + USBDM_GPIO = 0 /* GPIO controls 'out' */ } en_hsiom_sel_t; #endif /* _GPIO_PSOC6_02_124_BGA_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_02_128_tqfp.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_02_128_tqfp.h index a3e99fca78..7368823ad4 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_02_128_tqfp.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_02_128_tqfp.h @@ -5,11 +5,11 @@ * PSoC6_02 device GPIO header for 128-TQFP package * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -46,15 +46,15 @@ enum /* AMUXBUS Segments */ enum { - AMUXBUS_MAIN, AMUXBUS_ADFT0_VDDD, - AMUXBUS_NOISY, - AMUXBUS_CSD0, - AMUXBUS_VDDIO_1, - AMUXBUS_CSD1, - AMUXBUS_SAR, - AMUXBUS_ANALOG_VDDD, AMUXBUS_ANALOG_VDDA, + AMUXBUS_ANALOG_VDDD, + AMUXBUS_CSD0, + AMUXBUS_CSD1, + AMUXBUS_MAIN, + AMUXBUS_NOISY, + AMUXBUS_SAR, + AMUXBUS_VDDIO_1, }; /* AMUX Splitter Controls */ @@ -799,12 +799,6 @@ typedef enum P1_5_LCD_SEG11 = 13, /* Digital Deep Sleep - lcd.seg[11]:0 */ P1_5_SCB7_SPI_SELECT2 = 20, /* Digital Active - scb[7].spi_select2:0 */ - /* USBDM */ - USBDM_GPIO = 0, /* GPIO controls 'out' */ - - /* USBDP */ - USBDP_GPIO = 0, /* GPIO controls 'out' */ - /* P2.0 */ P2_0_GPIO = 0, /* GPIO controls 'out' */ P2_0_AMUXA = 4, /* Analog mux bus A */ @@ -2288,7 +2282,13 @@ typedef enum P13_7_LCD_COM38 = 12, /* Digital Deep Sleep - lcd.com[38]:1 */ P13_7_LCD_SEG38 = 13, /* Digital Deep Sleep - lcd.seg[38]:1 */ P13_7_SCB12_UART_CTS = 18, /* Digital Active - scb[12].uart_cts:0 */ - P13_7_SDHC1_CARD_DAT_7TO43 = 26 /* Digital Active - sdhc[1].card_dat_7to4[3] */ + P13_7_SDHC1_CARD_DAT_7TO43 = 26, /* Digital Active - sdhc[1].card_dat_7to4[3] */ + + /* USBDP */ + USBDP_GPIO = 0, /* GPIO controls 'out' */ + + /* USBDM */ + USBDM_GPIO = 0 /* GPIO controls 'out' */ } en_hsiom_sel_t; #endif /* _GPIO_PSOC6_02_128_TQFP_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_02_68_qfn.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_02_68_qfn.h index 6993974551..4b9259642d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_02_68_qfn.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_02_68_qfn.h @@ -5,11 +5,11 @@ * PSoC6_02 device GPIO header for 68-QFN package * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -46,15 +46,15 @@ enum /* AMUXBUS Segments */ enum { - AMUXBUS_MAIN, AMUXBUS_ADFT0_VDDD, - AMUXBUS_NOISY, - AMUXBUS_CSD0, - AMUXBUS_VDDIO_1, - AMUXBUS_CSD1, - AMUXBUS_SAR, - AMUXBUS_ANALOG_VDDD, AMUXBUS_ANALOG_VDDA, + AMUXBUS_ANALOG_VDDD, + AMUXBUS_CSD0, + AMUXBUS_CSD1, + AMUXBUS_MAIN, + AMUXBUS_NOISY, + AMUXBUS_SAR, + AMUXBUS_VDDIO_1, }; /* AMUX Splitter Controls */ @@ -499,12 +499,6 @@ typedef enum P0_5_SCB0_SPI_SELECT0 = 20, /* Digital Active - scb[0].spi_select0:0 */ P0_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:2 */ - /* USBDM */ - USBDM_GPIO = 0, /* GPIO controls 'out' */ - - /* USBDP */ - USBDP_GPIO = 0, /* GPIO controls 'out' */ - /* P2.0 */ P2_0_GPIO = 0, /* GPIO controls 'out' */ P2_0_AMUXA = 4, /* Analog mux bus A */ @@ -1293,7 +1287,13 @@ typedef enum P12_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:92 */ P12_7_LCD_COM30 = 12, /* Digital Deep Sleep - lcd.com[30]:1 */ P12_7_LCD_SEG30 = 13, /* Digital Deep Sleep - lcd.seg[30]:1 */ - P12_7_SDHC1_IO_VOLT_SEL = 26 /* Digital Active - sdhc[1].io_volt_sel */ + P12_7_SDHC1_IO_VOLT_SEL = 26, /* Digital Active - sdhc[1].io_volt_sel */ + + /* USBDP */ + USBDP_GPIO = 0, /* GPIO controls 'out' */ + + /* USBDM */ + USBDM_GPIO = 0 /* GPIO controls 'out' */ } en_hsiom_sel_t; #endif /* _GPIO_PSOC6_02_68_QFN_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_03_100_tqfp.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_03_100_tqfp.h index 6d543c0aec..d34f9e186e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_03_100_tqfp.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_03_100_tqfp.h @@ -5,11 +5,11 @@ * PSoC6_03 device GPIO header for 100-TQFP package * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -46,14 +46,14 @@ enum /* AMUXBUS Segments */ enum { - AMUXBUS_SRSS_AMUXBUSA_ADFT_VDDD, - AMUXBUS_SRSS_AMUXBUSB_ADFT_VDDD, - AMUXBUS_VSSA, - AMUXBUS_VDDIO_1, + AMUXBUS_ANALOG_VDDD, AMUXBUS_CSD0, AMUXBUS_CSD1, AMUXBUS_SAR, - AMUXBUS_ANALOG_VDDD, + AMUXBUS_VDDIO_1, + AMUXBUS_VSSA, + AMUXBUS_SRSS_AMUXBUSA_ADFT_VDDD, + AMUXBUS_SRSS_AMUXBUSB_ADFT_VDDD, }; /* AMUX Splitter Controls */ @@ -496,12 +496,6 @@ typedef enum P0_5_PERI_TR_IO_INPUT3 = 24, /* Digital Active - peri.tr_io_input[3]:0 */ P0_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:2 */ - /* USBDM */ - USBDM_GPIO = 0, /* GPIO controls 'out' */ - - /* USBDP */ - USBDP_GPIO = 0, /* GPIO controls 'out' */ - /* P2.0 */ P2_0_GPIO = 0, /* GPIO controls 'out' */ P2_0_AMUXA = 4, /* Analog mux bus A */ @@ -1428,7 +1422,13 @@ typedef enum P12_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:63 */ P12_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:63 */ P12_7_LCD_COM3 = 12, /* Digital Deep Sleep - lcd.com[3]:1 */ - P12_7_LCD_SEG3 = 13 /* Digital Deep Sleep - lcd.seg[3]:1 */ + P12_7_LCD_SEG3 = 13, /* Digital Deep Sleep - lcd.seg[3]:1 */ + + /* USBDP */ + USBDP_GPIO = 0, /* GPIO controls 'out' */ + + /* USBDM */ + USBDM_GPIO = 0 /* GPIO controls 'out' */ } en_hsiom_sel_t; #endif /* _GPIO_PSOC6_03_100_TQFP_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_03_49_wlcsp.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_03_49_wlcsp.h index e47a5345da..4eff9daf1b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_03_49_wlcsp.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_03_49_wlcsp.h @@ -5,11 +5,11 @@ * PSoC6_03 device GPIO header for 49-WLCSP package * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -46,14 +46,14 @@ enum /* AMUXBUS Segments */ enum { - AMUXBUS_SRSS_AMUXBUSA_ADFT_VDDD, - AMUXBUS_SRSS_AMUXBUSB_ADFT_VDDD, - AMUXBUS_VSSA, - AMUXBUS_VDDIO_1, + AMUXBUS_ANALOG_VDDD, AMUXBUS_CSD0, AMUXBUS_CSD1, AMUXBUS_SAR, - AMUXBUS_ANALOG_VDDD, + AMUXBUS_VDDIO_1, + AMUXBUS_VSSA, + AMUXBUS_SRSS_AMUXBUSA_ADFT_VDDD, + AMUXBUS_SRSS_AMUXBUSB_ADFT_VDDD, }; /* AMUX Splitter Controls */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_03_68_qfn.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_03_68_qfn.h index 3842d65925..2fecaeb37c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_03_68_qfn.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_03_68_qfn.h @@ -5,11 +5,11 @@ * PSoC6_03 device GPIO header for 68-QFN package * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -46,14 +46,14 @@ enum /* AMUXBUS Segments */ enum { - AMUXBUS_SRSS_AMUXBUSA_ADFT_VDDD, - AMUXBUS_SRSS_AMUXBUSB_ADFT_VDDD, - AMUXBUS_VSSA, - AMUXBUS_VDDIO_1, + AMUXBUS_ANALOG_VDDD, AMUXBUS_CSD0, AMUXBUS_CSD1, AMUXBUS_SAR, - AMUXBUS_ANALOG_VDDD, + AMUXBUS_VDDIO_1, + AMUXBUS_VSSA, + AMUXBUS_SRSS_AMUXBUSA_ADFT_VDDD, + AMUXBUS_SRSS_AMUXBUSB_ADFT_VDDD, }; /* AMUX Splitter Controls */ @@ -454,12 +454,6 @@ typedef enum P0_5_PERI_TR_IO_INPUT3 = 24, /* Digital Active - peri.tr_io_input[3]:0 */ P0_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:2 */ - /* USBDM */ - USBDM_GPIO = 0, /* GPIO controls 'out' */ - - /* USBDP */ - USBDP_GPIO = 0, /* GPIO controls 'out' */ - /* P2.0 */ P2_0_GPIO = 0, /* GPIO controls 'out' */ P2_0_AMUXA = 4, /* Analog mux bus A */ @@ -1218,7 +1212,13 @@ typedef enum P12_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:63 */ P12_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:63 */ P12_7_LCD_COM3 = 12, /* Digital Deep Sleep - lcd.com[3]:1 */ - P12_7_LCD_SEG3 = 13 /* Digital Deep Sleep - lcd.seg[3]:1 */ + P12_7_LCD_SEG3 = 13, /* Digital Deep Sleep - lcd.seg[3]:1 */ + + /* USBDP */ + USBDP_GPIO = 0, /* GPIO controls 'out' */ + + /* USBDM */ + USBDM_GPIO = 0 /* GPIO controls 'out' */ } en_hsiom_sel_t; #endif /* _GPIO_PSOC6_03_68_QFN_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_04_68_qfn.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_04_68_qfn.h index 69908631de..9509862d1c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_04_68_qfn.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_04_68_qfn.h @@ -5,7 +5,7 @@ * PSoC6_04 device GPIO header for 68-QFN package * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -477,12 +477,6 @@ typedef enum P0_5_PERI_TR_IO_INPUT3 = 24, /* Digital Active - peri.tr_io_input[3]:0 */ P0_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:2 */ - /* USBDM */ - USBDM_GPIO = 0, /* GPIO controls 'out' */ - - /* USBDP */ - USBDP_GPIO = 0, /* GPIO controls 'out' */ - /* P2.0 */ P2_0_GPIO = 0, /* GPIO controls 'out' */ P2_0_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:0 */ @@ -1157,7 +1151,13 @@ typedef enum P12_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:61 */ P12_7_LCD_COM3 = 12, /* Digital Deep Sleep - lcd.com[3]:1 */ P12_7_LCD_SEG3 = 13, /* Digital Deep Sleep - lcd.seg[3]:1 */ - P12_7_TCPWM0_TR_ONE_CNT_IN1 = 23 /* Digital Active - tcpwm[0].tr_one_cnt_in[1]:5 */ + P12_7_TCPWM0_TR_ONE_CNT_IN1 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[1]:5 */ + + /* USBDP */ + USBDP_GPIO = 0, /* GPIO controls 'out' */ + + /* USBDM */ + USBDM_GPIO = 0 /* GPIO controls 'out' */ } en_hsiom_sel_t; #endif /* _GPIO_PSOC6_04_68_QFN_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_ctbm_v2.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_ctbm_v2.h index 54b84f2af6..a8e1082aef 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_ctbm_v2.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_ctbm_v2.h @@ -5,11 +5,11 @@ * CTBM IP definitions * * \note -* Generator version: 1.5.1.36 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -61,7 +61,14 @@ typedef struct { __IOM uint32_t CTB_SW_DS_CTRL; /*!< 0x000000C0 CTB bus switch control */ __IOM uint32_t CTB_SW_SQ_CTRL; /*!< 0x000000C4 CTB bus switch Sar Sequencer control */ __IM uint32_t CTB_SW_STATUS; /*!< 0x000000C8 CTB bus switch control status */ -} CTBM_V2_Type; /*!< Size = 204 (0xCC) */ + __IM uint32_t RESERVED4[909]; + __IOM uint32_t OA0_OFFSET_TRIM; /*!< 0x00000F00 Opamp0 trim control */ + __IOM uint32_t OA0_SLOPE_OFFSET_TRIM; /*!< 0x00000F04 Opamp0 trim control */ + __IOM uint32_t OA0_COMP_TRIM; /*!< 0x00000F08 Opamp0 trim control */ + __IOM uint32_t OA1_OFFSET_TRIM; /*!< 0x00000F0C Opamp1 trim control */ + __IOM uint32_t OA1_SLOPE_OFFSET_TRIM; /*!< 0x00000F10 Opamp1 trim control */ + __IOM uint32_t OA1_COMP_TRIM; /*!< 0x00000F14 Opamp1 trim control */ +} CTBM_V2_Type; /*!< Size = 3864 (0xF18) */ /* CTBM.CTB_CTRL */ @@ -263,6 +270,24 @@ typedef struct { #define CTBM_V2_CTB_SW_STATUS_OA1O_D62_STAT_Msk 0x40000000UL #define CTBM_V2_CTB_SW_STATUS_CTD_COS_STAT_Pos 31UL #define CTBM_V2_CTB_SW_STATUS_CTD_COS_STAT_Msk 0x80000000UL +/* CTBM.OA0_OFFSET_TRIM */ +#define CTBM_V2_OA0_OFFSET_TRIM_OA0_OFFSET_TRIM_Pos 0UL +#define CTBM_V2_OA0_OFFSET_TRIM_OA0_OFFSET_TRIM_Msk 0x3FUL +/* CTBM.OA0_SLOPE_OFFSET_TRIM */ +#define CTBM_V2_OA0_SLOPE_OFFSET_TRIM_OA0_SLOPE_OFFSET_TRIM_Pos 0UL +#define CTBM_V2_OA0_SLOPE_OFFSET_TRIM_OA0_SLOPE_OFFSET_TRIM_Msk 0x3FUL +/* CTBM.OA0_COMP_TRIM */ +#define CTBM_V2_OA0_COMP_TRIM_OA0_COMP_TRIM_Pos 0UL +#define CTBM_V2_OA0_COMP_TRIM_OA0_COMP_TRIM_Msk 0x3UL +/* CTBM.OA1_OFFSET_TRIM */ +#define CTBM_V2_OA1_OFFSET_TRIM_OA1_OFFSET_TRIM_Pos 0UL +#define CTBM_V2_OA1_OFFSET_TRIM_OA1_OFFSET_TRIM_Msk 0x3FUL +/* CTBM.OA1_SLOPE_OFFSET_TRIM */ +#define CTBM_V2_OA1_SLOPE_OFFSET_TRIM_OA1_SLOPE_OFFSET_TRIM_Pos 0UL +#define CTBM_V2_OA1_SLOPE_OFFSET_TRIM_OA1_SLOPE_OFFSET_TRIM_Msk 0x3FUL +/* CTBM.OA1_COMP_TRIM */ +#define CTBM_V2_OA1_COMP_TRIM_OA1_COMP_TRIM_Pos 0UL +#define CTBM_V2_OA1_COMP_TRIM_OA1_COMP_TRIM_Msk 0x3UL #endif /* _CYIP_CTBM_V2_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_efuse.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_efuse.h index 93c7d9970d..9cf8bf4bc5 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_efuse.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_efuse.h @@ -5,7 +5,7 @@ * EFUSE IP definitions * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -37,7 +37,7 @@ #define EFUSE_SECTION_SIZE 0x00000080UL /** - * \brief 0x80 (EFUSE) + * \brief EFUSE MXS40 registers (EFUSE) */ typedef struct { __IOM uint32_t CTL; /*!< 0x00000000 Control */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_pass_v2.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_pass_v2.h index 532e009418..4dae9ca13b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_pass_v2.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_pass_v2.h @@ -5,7 +5,7 @@ * PASS IP definitions * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -56,7 +56,7 @@ typedef struct { typedef struct { __IOM uint32_t CTRL; /*!< 0x00000000 Low Power Oscillator control */ __IOM uint32_t CONFIG; /*!< 0x00000004 Low Power Oscillator configuration register */ - __IOM uint32_t ADFT; /*!< 0x00000008 Retention */ + __IOM uint32_t ADFT; /*!< 0x00000008 Retention, Hidden */ __IM uint32_t RESERVED[61]; } PASS_LPOSC_V2_Type; /*!< Size = 256 (0x100) */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_sar_v2.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_sar_v2.h index 40d096bbeb..8296082ec1 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_sar_v2.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_sar_v2.h @@ -5,11 +5,11 @@ * SAR IP definitions * * \note -* Generator version: 1.5.1.36 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -73,13 +73,17 @@ typedef struct { __IOM uint32_t RANGE_INTR_MASK; /*!< 0x00000238 Range detect interrupt mask register. */ __IM uint32_t RANGE_INTR_MASKED; /*!< 0x0000023C Range interrupt masked request register */ __IM uint32_t INTR_CAUSE; /*!< 0x00000240 Interrupt cause register */ - __IM uint32_t RESERVED5[23]; + __IM uint32_t RESERVED5[15]; + __IOM uint32_t INJ_CHAN_CONFIG; /*!< 0x00000280 Injection channel configuration register. */ + __IM uint32_t RESERVED6[3]; + __IM uint32_t INJ_RESULT; /*!< 0x00000290 Injection channel result register */ + __IM uint32_t RESERVED7[3]; __IM uint32_t STATUS; /*!< 0x000002A0 Current status of internal SAR registers (mostly for debug) */ __IM uint32_t AVG_STAT; /*!< 0x000002A4 Current averaging status (for debug) */ - __IM uint32_t RESERVED6[22]; + __IM uint32_t RESERVED8[22]; __IOM uint32_t MUX_SWITCH0; /*!< 0x00000300 SARMUX Firmware switch controls */ __IOM uint32_t MUX_SWITCH_CLEAR0; /*!< 0x00000304 SARMUX Firmware switch control clear */ - __IM uint32_t RESERVED7[15]; + __IM uint32_t RESERVED9[15]; __IOM uint32_t MUX_SWITCH_SQ_CTRL; /*!< 0x00000344 SARMUX switch Sar Sequencer control */ __IM uint32_t MUX_SWITCH_STATUS; /*!< 0x00000348 SARMUX switch status */ } SAR_V2_Type; /*!< Size = 844 (0x34C) */ @@ -337,6 +341,34 @@ typedef struct { #define SAR_V2_INTR_CAUSE_SATURATE_MASKED_RED_Msk 0x40000000UL #define SAR_V2_INTR_CAUSE_RANGE_MASKED_RED_Pos 31UL #define SAR_V2_INTR_CAUSE_RANGE_MASKED_RED_Msk 0x80000000UL +/* SAR.INJ_CHAN_CONFIG */ +#define SAR_V2_INJ_CHAN_CONFIG_INJ_PIN_ADDR_Pos 0UL +#define SAR_V2_INJ_CHAN_CONFIG_INJ_PIN_ADDR_Msk 0x7UL +#define SAR_V2_INJ_CHAN_CONFIG_INJ_PORT_ADDR_Pos 4UL +#define SAR_V2_INJ_CHAN_CONFIG_INJ_PORT_ADDR_Msk 0x70UL +#define SAR_V2_INJ_CHAN_CONFIG_INJ_DIFFERENTIAL_EN_Pos 8UL +#define SAR_V2_INJ_CHAN_CONFIG_INJ_DIFFERENTIAL_EN_Msk 0x100UL +#define SAR_V2_INJ_CHAN_CONFIG_INJ_AVG_EN_Pos 10UL +#define SAR_V2_INJ_CHAN_CONFIG_INJ_AVG_EN_Msk 0x400UL +#define SAR_V2_INJ_CHAN_CONFIG_INJ_SAMPLE_TIME_SEL_Pos 12UL +#define SAR_V2_INJ_CHAN_CONFIG_INJ_SAMPLE_TIME_SEL_Msk 0x3000UL +#define SAR_V2_INJ_CHAN_CONFIG_INJ_TAILGATING_Pos 30UL +#define SAR_V2_INJ_CHAN_CONFIG_INJ_TAILGATING_Msk 0x40000000UL +#define SAR_V2_INJ_CHAN_CONFIG_INJ_START_EN_Pos 31UL +#define SAR_V2_INJ_CHAN_CONFIG_INJ_START_EN_Msk 0x80000000UL +/* SAR.INJ_RESULT */ +#define SAR_V2_INJ_RESULT_INJ_RESULT_Pos 0UL +#define SAR_V2_INJ_RESULT_INJ_RESULT_Msk 0xFFFFUL +#define SAR_V2_INJ_RESULT_INJ_NEWVALUE_Pos 27UL +#define SAR_V2_INJ_RESULT_INJ_NEWVALUE_Msk 0x8000000UL +#define SAR_V2_INJ_RESULT_INJ_COLLISION_INTR_MIR_Pos 28UL +#define SAR_V2_INJ_RESULT_INJ_COLLISION_INTR_MIR_Msk 0x10000000UL +#define SAR_V2_INJ_RESULT_INJ_SATURATE_INTR_MIR_Pos 29UL +#define SAR_V2_INJ_RESULT_INJ_SATURATE_INTR_MIR_Msk 0x20000000UL +#define SAR_V2_INJ_RESULT_INJ_RANGE_INTR_MIR_Pos 30UL +#define SAR_V2_INJ_RESULT_INJ_RANGE_INTR_MIR_Msk 0x40000000UL +#define SAR_V2_INJ_RESULT_INJ_EOC_INTR_MIR_Pos 31UL +#define SAR_V2_INJ_RESULT_INJ_EOC_INTR_MIR_Msk 0x80000000UL /* SAR.STATUS */ #define SAR_V2_STATUS_CUR_CHAN_Pos 0UL #define SAR_V2_STATUS_CUR_CHAN_Msk 0x1FUL diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_sflash.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_sflash.h index cb25d51364..212ce16816 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_sflash.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_sflash.h @@ -5,7 +5,7 @@ * SFLASH IP definitions * * \note -* Generator version: 1.6.0.111 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -47,18 +47,11 @@ typedef struct { __IOM uint16_t FAMILY_ID; /*!< 0x0000000C Indicates Family ID of the device */ __IM uint16_t RESERVED2[3]; __IOM uint32_t CPUSS_WOUNDING; /*!< 0x00000014 CPUSS Wounding */ - __IM uint32_t RESERVED3[2]; - __IOM uint8_t S1_TESTPGM_REV; /*!< 0x00000020 S1_testpgm_rev */ - __IOM uint8_t S2_TESTPGM_REV; /*!< 0x00000021 S2_testpgm_rev */ - __IOM uint8_t S3_TESTPGM_REV; /*!< 0x00000022 S3_testpgm_rev */ - __IOM uint8_t CRI_TESTPGM_REV; /*!< 0x00000023 CRI_testpgm_rev */ - __IOM uint8_t CRI_AB_REV; /*!< 0x00000024 CRI AB Revision */ - __IOM uint8_t CHI_TESTPGM_REV; /*!< 0x00000025 CHI_testpgm_rev */ - __IM uint16_t RESERVED4; + __IM uint32_t RESERVED3[4]; __IOM uint32_t SFLASH_SVN; /*!< 0x00000028 SFLASH Subversion */ - __IM uint32_t RESERVED5[20]; + __IM uint32_t RESERVED4[20]; __IOM uint32_t FB_FLAGS; /*!< 0x0000007C Flash boot flags */ - __IM uint32_t RESERVED6[352]; + __IM uint32_t RESERVED5[352]; __IOM uint8_t DIE_LOT[3]; /*!< 0x00000600 Lot Number (3 bytes) */ __IOM uint8_t DIE_WAFER; /*!< 0x00000603 Wafer Number */ __IOM uint8_t DIE_X; /*!< 0x00000604 X Position on Wafer, CRI Pass/Fail Bin */ @@ -68,20 +61,20 @@ typedef struct { __IOM uint8_t DIE_DAY; /*!< 0x00000608 Day number */ __IOM uint8_t DIE_MONTH; /*!< 0x00000609 Month number */ __IOM uint8_t DIE_YEAR; /*!< 0x0000060A Year number */ - __IM uint8_t RESERVED7[61]; + __IM uint8_t RESERVED6[61]; __IOM uint16_t SAR_TEMP_MULTIPLIER; /*!< 0x00000648 SAR Temperature Sensor Multiplication Factor */ __IOM uint16_t SAR_TEMP_OFFSET; /*!< 0x0000064A SAR Temperature Sensor Offset */ - __IM uint32_t RESERVED8[8]; + __IM uint32_t RESERVED7[8]; __IOM uint32_t CSP_PANEL_ID; /*!< 0x0000066C CSP Panel Id to record panel ID of CSP die */ - __IM uint32_t RESERVED9[52]; + __IM uint32_t RESERVED8[52]; __IOM uint8_t LDO_0P9V_TRIM; /*!< 0x00000740 LDO_0P9V_TRIM */ __IOM uint8_t LDO_1P1V_TRIM; /*!< 0x00000741 LDO_1P1V_TRIM */ - __IM uint16_t RESERVED10[95]; + __IM uint16_t RESERVED9[95]; __IOM uint32_t BLE_DEVICE_ADDRESS[128]; /*!< 0x00000800 BLE_DEVICE_ADDRESS */ __IOM uint32_t USER_FREE_ROW1[128]; /*!< 0x00000A00 USER_FREE_ROW1 */ __IOM uint32_t USER_FREE_ROW2[128]; /*!< 0x00000C00 USER_FREE_ROW2 */ __IOM uint32_t USER_FREE_ROW3[128]; /*!< 0x00000E00 USER_FREE_ROW3 */ - __IM uint32_t RESERVED11[302]; + __IM uint32_t RESERVED10[302]; __IOM uint8_t DEVICE_UID[16]; /*!< 0x000014B8 Unique Identifier Number for each device */ __IOM uint8_t MASTER_KEY[16]; /*!< 0x000014C8 Master key to change other keys */ __IOM uint32_t STANDARD_SMPU_STRUCT_SLAVE_ADDR[16]; /*!< 0x000014D8 Standard SMPU STRUCT Slave Address value */ @@ -89,36 +82,36 @@ typedef struct { __IOM uint32_t STANDARD_SMPU_STRUCT_MASTER_ATTR[16]; /*!< 0x00001558 Standard SMPU STRUCT Master Attribute value */ __IOM uint32_t STANDARD_MPU_STRUCT[16]; /*!< 0x00001598 Standard MPU STRUCT */ __IOM uint32_t STANDARD_PPU_STRUCT[16]; /*!< 0x000015D8 Standard PPU STRUCT */ - __IM uint32_t RESERVED12[122]; + __IM uint32_t RESERVED11[122]; __IOM uint16_t PILO_FREQ_STEP; /*!< 0x00001800 Resolution step for PILO at class in BCD format */ - __IM uint16_t RESERVED13; + __IM uint16_t RESERVED12; __IOM uint32_t CSDV2_CSD0_ADC_VREF0; /*!< 0x00001804 CSD 1p2 & 1p6 voltage levels for accuracy */ __IOM uint32_t CSDV2_CSD0_ADC_VREF1; /*!< 0x00001808 CSD 2p1 & 0p8 voltage levels for accuracy */ __IOM uint32_t CSDV2_CSD0_ADC_VREF2; /*!< 0x0000180C CSD calibration spare voltage level for accuracy */ __IOM uint32_t PWR_TRIM_WAKE_CTL; /*!< 0x00001810 Wakeup delay */ - __IM uint16_t RESERVED14; + __IM uint16_t RESERVED13; __IOM uint16_t RADIO_LDO_TRIMS; /*!< 0x00001816 Radio LDO Trims */ __IOM uint32_t CPUSS_TRIM_ROM_CTL_ULP; /*!< 0x00001818 CPUSS TRIM ROM CTL ULP value */ __IOM uint32_t CPUSS_TRIM_RAM_CTL_ULP; /*!< 0x0000181C CPUSS TRIM RAM CTL ULP value */ __IOM uint32_t CPUSS_TRIM_ROM_CTL_LP; /*!< 0x00001820 CPUSS TRIM ROM CTL LP value */ __IOM uint32_t CPUSS_TRIM_RAM_CTL_LP; /*!< 0x00001824 CPUSS TRIM RAM CTL LP value */ - __IM uint32_t RESERVED15[7]; + __IM uint32_t RESERVED14[7]; __IOM uint32_t CPUSS_TRIM_ROM_CTL_HALF_ULP; /*!< 0x00001844 CPUSS TRIM ROM CTL HALF ULP value */ __IOM uint32_t CPUSS_TRIM_RAM_CTL_HALF_ULP; /*!< 0x00001848 CPUSS TRIM RAM CTL HALF ULP value */ __IOM uint32_t CPUSS_TRIM_ROM_CTL_HALF_LP; /*!< 0x0000184C CPUSS TRIM ROM CTL HALF LP value */ __IOM uint32_t CPUSS_TRIM_RAM_CTL_HALF_LP; /*!< 0x00001850 CPUSS TRIM RAM CTL HALF LP value */ - __IM uint32_t RESERVED16[491]; + __IM uint32_t RESERVED15[491]; __IOM uint32_t FLASH_BOOT_OBJECT_SIZE; /*!< 0x00002000 Flash Boot - Object Size */ __IOM uint32_t FLASH_BOOT_APP_ID; /*!< 0x00002004 Flash Boot - Application ID/Version */ __IOM uint32_t FLASH_BOOT_ATTRIBUTE; /*!< 0x00002008 N/A */ __IOM uint32_t FLASH_BOOT_N_CORES; /*!< 0x0000200C Flash Boot - Number of Cores(N) */ __IOM uint32_t FLASH_BOOT_VT_OFFSET; /*!< 0x00002010 Flash Boot - Core Vector Table offset */ __IOM uint32_t FLASH_BOOT_CORE_CPUID; /*!< 0x00002014 Flash Boot - Core CPU ID/Core Index */ - __IM uint32_t RESERVED17[48]; + __IM uint32_t RESERVED16[48]; __IOM uint8_t FLASH_BOOT_CODE[14632]; /*!< 0x000020D8 Flash Boot - Code and Data */ __IOM uint8_t PUBLIC_KEY[3072]; /*!< 0x00005A00 Public key for signature verification (max RSA key size 4096) */ __IOM uint32_t BOOT_PROT_SETTINGS[384]; /*!< 0x00006600 Boot protection settings (not present in PSOC6ABLE2) */ - __IM uint32_t RESERVED18[768]; + __IM uint32_t RESERVED17[768]; __IOM uint32_t TOC1_OBJECT_SIZE; /*!< 0x00007800 Object size in bytes for CRC calculation starting from offset 0x00 */ __IOM uint32_t TOC1_MAGIC_NUMBER; /*!< 0x00007804 Magic number(0x01211219) */ @@ -129,7 +122,7 @@ typedef struct { __IOM uint32_t TOC1_FB_OBJECT_ADDR; /*!< 0x00007814 Addresss of FLASH Boot(FB) object that include FLASH patch also */ __IOM uint32_t TOC1_SYSCALL_TABLE_ADDR_UNUSED; /*!< 0x00007818 Unused (Address is Hardcoded in ROM) */ __IOM uint32_t TOC1_OBJECT_ADDR_UNUSED; /*!< 0x0000781C Unused (Address is Hardcoded in ROM) */ - __IM uint32_t RESERVED19[119]; + __IM uint32_t RESERVED18[119]; __IOM uint32_t TOC1_CRC_ADDR; /*!< 0x000079FC Upper 2 bytes contain CRC16-CCITT and lower 2 bytes are 0 */ __IOM uint32_t RTOC1_OBJECT_SIZE; /*!< 0x00007A00 Redundant Object size in bytes for CRC calculation starting from offset 0x00 */ @@ -142,7 +135,7 @@ typedef struct { patch also */ __IOM uint32_t RTOC1_SYSCALL_TABLE_ADDR_UNUSED; /*!< 0x00007A18 Redundant Unused (Address is Hardcoded in ROM) */ __IOM uint32_t RTOC1_OBJECT_ADDR_UNUSED; /*!< 0x00007A1C Redundant Unused (Address is Hardcoded in ROM) */ - __IM uint32_t RESERVED20[119]; + __IM uint32_t RESERVED19[119]; __IOM uint32_t RTOC1_CRC_ADDR; /*!< 0x00007BFC Redundant CRC,Upper 2 bytes contain CRC16-CCITT and lower 2 bytes are 0 */ __IOM uint32_t TOC2_OBJECT_SIZE; /*!< 0x00007C00 Object size in bytes for CRC calculation starting from offset @@ -162,7 +155,7 @@ typedef struct { SECURE_HASH(SHASH) */ __IOM uint32_t TOC2_SIGNATURE_VERIF_KEY; /*!< 0x00007C24 Address of signature verification key (0 if none).The object is signature specific key. It is the public key in case of RSA */ - __IM uint32_t RESERVED21[115]; + __IM uint32_t RESERVED20[115]; __IOM uint32_t TOC2_REVISION; /*!< 0x00007DF4 Indicates TOC2 Revision. It is not used now. */ __IOM uint32_t TOC2_FLAGS; /*!< 0x00007DF8 TOC2_FLAGS */ __IOM uint32_t TOC2_CRC_ADDR; /*!< 0x00007DFC CRC,Upper 2 bytes contain CRC16-CCITT and lower 2 bytes are 0 */ @@ -184,7 +177,7 @@ typedef struct { __IOM uint32_t RTOC2_SIGNATURE_VERIF_KEY; /*!< 0x00007E24 Redundant Address of signature verification key (0 if none).The object is signature specific key. It is the public key in case of RSA */ - __IM uint32_t RESERVED22[115]; + __IM uint32_t RESERVED21[115]; __IOM uint32_t RTOC2_REVISION; /*!< 0x00007FF4 Indicates RTOC2 Revision. It is not used now. */ __IOM uint32_t RTOC2_FLAGS; /*!< 0x00007FF8 RTOC2_FLAGS */ __IOM uint32_t RTOC2_CRC_ADDR; /*!< 0x00007FFC Redundant CRC,Upper 2 bytes contain CRC16-CCITT and lower 2 @@ -204,24 +197,6 @@ typedef struct { /* SFLASH.CPUSS_WOUNDING */ #define SFLASH_CPUSS_WOUNDING_CPUSS_WOUNDING_Pos 0UL #define SFLASH_CPUSS_WOUNDING_CPUSS_WOUNDING_Msk 0xFFFFFFFFUL -/* SFLASH.S1_TESTPGM_REV */ -#define SFLASH_S1_TESTPGM_REV_DATA_Pos 0UL -#define SFLASH_S1_TESTPGM_REV_DATA_Msk 0xFFUL -/* SFLASH.S2_TESTPGM_REV */ -#define SFLASH_S2_TESTPGM_REV_DATA_Pos 0UL -#define SFLASH_S2_TESTPGM_REV_DATA_Msk 0xFFUL -/* SFLASH.S3_TESTPGM_REV */ -#define SFLASH_S3_TESTPGM_REV_DATA_Pos 0UL -#define SFLASH_S3_TESTPGM_REV_DATA_Msk 0xFFUL -/* SFLASH.CRI_TESTPGM_REV */ -#define SFLASH_CRI_TESTPGM_REV_DATA_Pos 0UL -#define SFLASH_CRI_TESTPGM_REV_DATA_Msk 0xFFUL -/* SFLASH.CRI_AB_REV */ -#define SFLASH_CRI_AB_REV_DATA_Pos 0UL -#define SFLASH_CRI_AB_REV_DATA_Msk 0xFFUL -/* SFLASH.CHI_TESTPGM_REV */ -#define SFLASH_CHI_TESTPGM_REV_DATA_Pos 0UL -#define SFLASH_CHI_TESTPGM_REV_DATA_Msk 0xFFUL /* SFLASH.SFLASH_SVN */ #define SFLASH_SFLASH_SVN_DATA32_Pos 0UL #define SFLASH_SFLASH_SVN_DATA32_Msk 0xFFFFFFFFUL diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/psoc6_01_config.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/psoc6_01_config.h index 321f0398b4..2a3783af52 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/psoc6_01_config.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/psoc6_01_config.h @@ -5,11 +5,11 @@ * PSoC6_01 device configuration header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -1405,39 +1405,22 @@ typedef enum } en_trig_type_t; /* Trigger Type Defines */ -/* TCPWM Trigger Types */ -#define TRIGGER_TYPE_TCPWM_LINE TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_TCPWM_LINE_COMPL TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_TCPWM_TR_IN__LEVEL TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_TCPWM_TR_IN__EDGE TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_TCPWM_TR_OVERFLOW TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_TCPWM_TR_COMPARE_MATCH TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_TCPWM_TR_UNDERFLOW TRIGGER_TYPE_EDGE -/* CSD Trigger Types */ -#define TRIGGER_TYPE_CSD_DSI_SAMPLE_OUT TRIGGER_TYPE_EDGE -/* SCB Trigger Types */ -#define TRIGGER_TYPE_SCB_TR_TX_REQ TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_SCB_TR_RX_REQ TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_SCB_TR_I2C_SCL_FILTERED TRIGGER_TYPE_LEVEL -/* PERI Trigger Types */ -#define TRIGGER_TYPE_PERI_TR_IO_INPUT__LEVEL TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_PERI_TR_IO_INPUT__EDGE TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_PERI_TR_IO_OUTPUT__LEVEL TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_PERI_TR_IO_OUTPUT__EDGE TRIGGER_TYPE_EDGE +/* AUDIOSS Trigger Types */ +#define TRIGGER_TYPE_AUDIOSS_TR_I2S_RX_REQ TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_AUDIOSS_TR_I2S_TX_REQ TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_AUDIOSS_TR_PDM_RX_REQ TRIGGER_TYPE_LEVEL /* CPUSS Trigger Types */ +#define TRIGGER_TYPE_CPUSS_CTI_TR_IN TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_CTI_TR_OUT TRIGGER_TYPE_EDGE #define TRIGGER_TYPE_CPUSS_DW0_TR_IN__LEVEL TRIGGER_TYPE_LEVEL #define TRIGGER_TYPE_CPUSS_DW0_TR_IN__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_DW0_TR_OUT TRIGGER_TYPE_EDGE #define TRIGGER_TYPE_CPUSS_DW1_TR_IN__LEVEL TRIGGER_TYPE_LEVEL #define TRIGGER_TYPE_CPUSS_DW1_TR_IN__EDGE TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_CPUSS_CTI_TR_IN TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_CPUSS_DW0_TR_OUT TRIGGER_TYPE_EDGE #define TRIGGER_TYPE_CPUSS_DW1_TR_OUT TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_CPUSS_CTI_TR_OUT TRIGGER_TYPE_EDGE #define TRIGGER_TYPE_CPUSS_TR_FAULT TRIGGER_TYPE_EDGE -/* AUDIOSS Trigger Types */ -#define TRIGGER_TYPE_AUDIOSS_TR_PDM_RX_REQ TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_AUDIOSS_TR_I2S_TX_REQ TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_AUDIOSS_TR_I2S_RX_REQ TRIGGER_TYPE_LEVEL +/* CSD Trigger Types */ +#define TRIGGER_TYPE_CSD_DSI_SAMPLE_OUT TRIGGER_TYPE_EDGE /* LPCOMP Trigger Types */ #define TRIGGER_TYPE_LPCOMP_DSI_COMP0 TRIGGER_TYPE_LEVEL #define TRIGGER_TYPE_LPCOMP_DSI_COMP1 TRIGGER_TYPE_LEVEL @@ -1446,33 +1429,50 @@ typedef enum #define TRIGGER_TYPE_PASS_DSI_CTB_CMP0__EDGE TRIGGER_TYPE_EDGE #define TRIGGER_TYPE_PASS_DSI_CTB_CMP1__LEVEL TRIGGER_TYPE_LEVEL #define TRIGGER_TYPE_PASS_DSI_CTB_CMP1__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_PASS_TR_CTDAC_EMPTY TRIGGER_TYPE_EDGE #define TRIGGER_TYPE_PASS_TR_SAR_IN__LEVEL TRIGGER_TYPE_LEVEL #define TRIGGER_TYPE_PASS_TR_SAR_IN__EDGE TRIGGER_TYPE_EDGE #define TRIGGER_TYPE_PASS_TR_SAR_OUT TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_PASS_TR_CTDAC_EMPTY TRIGGER_TYPE_EDGE -/* SMIF Trigger Types */ -#define TRIGGER_TYPE_SMIF_TR_TX_REQ TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_SMIF_TR_RX_REQ TRIGGER_TYPE_LEVEL -/* USB Trigger Types */ -#define TRIGGER_TYPE_USB_DMA_BURSTEND TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_USB_DMA_REQ TRIGGER_TYPE_EDGE -/* UDB Trigger Types */ -#define TRIGGER_TYPE_UDB_TR_IN__LEVEL TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_UDB_TR_IN__EDGE TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_UDB_TR_DW_ACK__LEVEL TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_UDB_TR_DW_ACK__EDGE TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_UDB_TR_UDB__LEVEL TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_UDB_TR_UDB__EDGE TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_UDB_DSI_OUT_TR__LEVEL TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_UDB_DSI_OUT_TR__EDGE TRIGGER_TYPE_EDGE +/* PERI Trigger Types */ +#define TRIGGER_TYPE_PERI_TR_IO_INPUT__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_PERI_TR_IO_INPUT__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_PERI_TR_IO_OUTPUT__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_PERI_TR_IO_OUTPUT__EDGE TRIGGER_TYPE_EDGE /* PROFILE Trigger Types */ #define TRIGGER_TYPE_PROFILE_TR_START TRIGGER_TYPE_EDGE #define TRIGGER_TYPE_PROFILE_TR_STOP TRIGGER_TYPE_EDGE +/* SCB Trigger Types */ +#define TRIGGER_TYPE_SCB_TR_I2C_SCL_FILTERED TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_SCB_TR_RX_REQ TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_SCB_TR_TX_REQ TRIGGER_TYPE_LEVEL +/* SMIF Trigger Types */ +#define TRIGGER_TYPE_SMIF_TR_RX_REQ TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_SMIF_TR_TX_REQ TRIGGER_TYPE_LEVEL +/* TCPWM Trigger Types */ +#define TRIGGER_TYPE_TCPWM_LINE TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_TCPWM_LINE_COMPL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_TCPWM_TR_COMPARE_MATCH TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_TCPWM_TR_IN__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_TCPWM_TR_IN__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_TCPWM_TR_OVERFLOW TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_TCPWM_TR_UNDERFLOW TRIGGER_TYPE_EDGE /* TR_GROUP Trigger Types */ -#define TRIGGER_TYPE_TR_GROUP_OUTPUT__LEVEL TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_TR_GROUP_OUTPUT__EDGE TRIGGER_TYPE_EDGE #define TRIGGER_TYPE_TR_GROUP_INPUT__LEVEL TRIGGER_TYPE_LEVEL #define TRIGGER_TYPE_TR_GROUP_INPUT__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_TR_GROUP_OUTPUT__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_TR_GROUP_OUTPUT__EDGE TRIGGER_TYPE_EDGE +/* UDB Trigger Types */ +#define TRIGGER_TYPE_UDB_DSI_OUT_TR__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_UDB_DSI_OUT_TR__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_UDB_TR_DW_ACK__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_UDB_TR_DW_ACK__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_UDB_TR_IN__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_UDB_TR_IN__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_UDB_TR_UDB__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_UDB_TR_UDB__EDGE TRIGGER_TYPE_EDGE +/* USB Trigger Types */ +#define TRIGGER_TYPE_USB_DMA_BURSTEND TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_USB_DMA_REQ TRIGGER_TYPE_EDGE /* Monitor Signal Defines */ typedef enum @@ -1631,75 +1631,186 @@ typedef I2S_V1_Type I2S_Type; typedef PDM_V1_Type PDM_Type; /* Parameter Defines */ -/* Number of regulator modules instantiated within SRSS */ -#define SRSS_NUM_ACTREG_PWRMOD 2u -/* Number of shorting switches between vccd and vccact */ -#define SRSS_NUM_ACTIVE_SWITCH 3u -/* ULP linear regulator system is present */ -#define SRSS_ULPLINREG_PRESENT 1u -/* HT linear regulator system is present */ -#define SRSS_HTLINREG_PRESENT 0u -/* SIMO buck core regulator is present. Only compatible with ULP linear regulator - system (ULPLINREG_PRESENT==1). */ -#define SRSS_SIMOBUCK_PRESENT 1u -/* Precision ILO (PILO) is present */ -#define SRSS_PILO_PRESENT 1u -/* External Crystal Oscillator is present (high frequency) */ -#define SRSS_ECO_PRESENT 1u -/* System Buck-Boost is present */ -#define SRSS_SYSBB_PRESENT 0u -/* Number of clock paths. Must be > 0 */ -#define SRSS_NUM_CLKPATH 5u -/* Number of PLLs present. Must be <= NUM_CLKPATH */ -#define SRSS_NUM_PLL 1u -/* Number of HFCLK roots present. Must be > 0 */ -#define SRSS_NUM_HFROOT 5u -/* Number of PWR_HIB_DATA registers */ -#define SRSS_NUM_HIBDATA 1u -/* Backup domain is present */ -#define SRSS_BACKUP_PRESENT 1u -/* Mask of HFCLK root clock supervisors (CSV). For each clock root i, bit[i] of - mask indicates presence of a CSV. */ -#define SRSS_MASK_HFCSV 0u -/* Clock supervisor is present on WCO. Must be 0 if BACKUP_PRESENT==0. */ -#define SRSS_WCOCSV_PRESENT 0u -/* Number of software watchdog timers. */ -#define SRSS_NUM_MCWDT 2u -/* Number of DSI inputs into clock muxes. This is used for logic optimization. */ -#define SRSS_NUM_DSI 2u -/* Alternate high-frequency clock is present. This is used for logic optimization. */ -#define SRSS_ALTHF_PRESENT 1u -/* Alternate low-frequency clock is present. This is used for logic optimization. */ -#define SRSS_ALTLF_PRESENT 0u -/* Use the hardened clkactfllmux block */ -#define SRSS_USE_HARD_CLKACTFLLMUX 1u -/* Number of clock paths, including direct paths in hardened clkactfllmux block - (Must be >= NUM_CLKPATH) */ -#define SRSS_HARD_CLKPATH 6u -/* Number of clock paths with muxes in hardened clkactfllmux block (Must be >= - NUM_PLL+1) */ -#define SRSS_HARD_CLKPATHMUX 6u -/* Number of HFCLKS present in hardened clkactfllmux block (Must be >= NUM_HFROOT) */ -#define SRSS_HARD_HFROOT 6u -/* ECO mux is present in hardened clkactfllmux block (Must be >= ECO_PRESENT) */ -#define SRSS_HARD_ECOMUX_PRESENT 1u -/* ALTHF mux is present in hardened clkactfllmux block (Must be >= ALTHF_PRESENT) */ -#define SRSS_HARD_ALTHFMUX_PRESENT 1u -/* Low-current buck regulator present. Can be derived from S40S_SISOBUCKLC_PRESENT - or SIMOBUCK_PRESENT. */ -#define SRSS_BUCKCTL_PRESENT 1u -/* Low-current SISO buck core regulator is present. Only compatible with ULP - linear regulator system (ULPLINREG_PRESENT==1). */ -#define SRSS_S40S_SISOBUCKLC_PRESENT 0u -/* Backup memory is present (only used when BACKUP_PRESENT==1) */ -#define SRSS_BACKUP_BMEM_PRESENT 0u -/* Number of Backup registers to include (each is 32b). Only used when - BACKUP_PRESENT==1. */ -#define SRSS_BACKUP_NUM_BREG 16u -/* Number of AMUX splitter cells */ -#define IOSS_HSIOM_AMUX_SPLIT_NR 9u -/* Number of HSIOM ports in device (same as GPIO.GPIO_PRT_NR) */ -#define IOSS_HSIOM_HSIOM_PORT_NR 15u +/* I2S capable? (0=No,1=Yes) */ +#define AUDIOSS_I2S 1u +/* PDM capable? (0=No,1=Yes) */ +#define AUDIOSS_PDM 1u +/* UDB present or not ('0': no, '1': yes) */ +#define CPUSS_UDB_PRESENT 1u +/* System RAM 0 size in kilobytes */ +#define CPUSS_SRAM0_SIZE 288u +/* Number of macros used to implement System RAM 0. Example: 8 if 256 KB System + SRAM0 is implemented with 8 32KB macros. */ +#define CPUSS_RAMC0_MACRO_NR 9u +/* System RAM 1 present or not (0=No, 1=Yes) */ +#define CPUSS_RAMC1_PRESENT 0u +/* System RAM 1 size in kilobytes */ +#define CPUSS_SRAM1_SIZE 32u +/* Number of macros used to implement System RAM 1. Example: 8 if 256 KB System + RAM 1 is implemented with 8 32KB macros. */ +#define CPUSS_RAMC1_MACRO_NR 1u +/* System RAM 2 present or not (0=No, 1=Yes) */ +#define CPUSS_RAMC2_PRESENT 0u +/* System RAM 2 size in kilobytes */ +#define CPUSS_SRAM2_SIZE 256u +/* Number of macros used to implement System RAM 2. Example: 8 if 256 KB System + RAM 2 is implemented with 8 32KB macros. */ +#define CPUSS_RAMC2_MACRO_NR 16u +/* System ROM size in KB */ +#define CPUSS_ROM_SIZE 128u +/* Flash main region size in KB */ +#define CPUSS_FLASH_SIZE 1024u +/* Flash work region size in KB (EEPROM emulation, data) */ +#define CPUSS_WFLASH_SIZE 32u +/* Flash supervisory region size in KB */ +#define CPUSS_SFLASH_SIZE 32u +/* Flash data output size (in Bytes) */ +#define CPUSS_FLASHC_WORD_SIZE 16u +/* Flash row address width */ +#define CPUSS_FLASHC_ROW_ADDR_WIDTH 12u +/* Flash column address width */ +#define CPUSS_FLASHC_COL_ADDR_WIDTH 5u +/* Number of external slaves directly connected to slow AHB-Lite infrastructure. + Maximum nubmer of slave supported is 4. Width of this parameter is 4-bits. + 1-bit mask for each slave indicating present or not. Example: 4'b0011 - slave + 0 and slave 1 are present. Note: The SLOW_SLx_ADDR and SLOW_SLx_MASK + parameters (for the slaves present) should be derived from the Memory Map. */ +#define CPUSS_SLOW_SL_PRESENT 1u +/* Number of external slaves directly connected to fast AHB-Lite infrastructure. + Maximum nubmer of slave supported is 4. Width of this parameter is 4-bits. + 1-bit mask for each slave indicating present or not. Example: 4'b0011 - slave + 0 and slave 1 are present. Note: The FAST_SLx_ADDR and FAST_SLx_MASK + parameters (for the slaves present) should be derived from the Memory Map. */ +#define CPUSS_FAST_SL_PRESENT 1u +/* Number of external masters driving the slow AHB-Lite infrastructure. Maximum + number of masters supported is 2. Width of this parameter is 2-bits. 1-bit + mask for each master indicating present or not. Example: 2'b01 - master 0 is + present. */ +#define CPUSS_SLOW_MS_PRESENT 0u +/* Number of total interrupt request inputs to CPUSS */ +#define CPUSS_IRQ_NR 147u +/* Number of DeepSleep wakeup interrupt inputs to CPUSS */ +#define CPUSS_DPSLP_IRQ_NR 41u +/* Number of DeepSleep wakeup interrupt inputs to CM0+ (product configuration) */ +#define CPUSS_CM0_DPSLP_IRQ_NR 8u +/* Width of the CM4 interrupt priority bits. Legal range [3,8] Example: 3 = 8 + levels of priority 8 = 256 levels of priority */ +#define CPUSS_CM4_LVL_WIDTH 3u +/* CM4 Floating point unit present or not (0=No, 1=Yes) */ +#define CPUSS_CM4_FPU_PRESENT 1u +/* Debug level. Legal range [0,3] */ +#define CPUSS_DEBUG_LVL 3u +/* Trace level. Legal range [0,2] Note: CM4 HTM is not supported. Hence vaule 3 + for trace level is not supported in CPUSS. */ +#define CPUSS_TRACE_LVL 2u +/* Embedded Trace Buffer present or not (0=No, 1=Yes) */ +#define CPUSS_ETB_PRESENT 0u +/* CM0+ MTB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */ +#define CPUSS_MTB_SRAM_SIZE 4u +/* CM4 ETB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */ +#define CPUSS_ETB_SRAM_SIZE 16u +/* PTM interface present (0=No, 1=Yes) */ +#define CPUSS_PTM_PRESENT 1u +/* Width of the PTM interface in bits ([2,32]) */ +#define CPUSS_PTM_WIDTH 8u +/* Width of the TPIU interface in bits ([1,32]) */ +#define CPUSS_TPIU_WIDTH 4u +/* CoreSight Part Identification Number */ +#define CPUSS_JEPID 52u +/* CoreSight Part Identification Number */ +#define CPUSS_JEPCONTINUATION 0u +/* CoreSight Part Identification Number */ +#define CPUSS_FAMILYID 256u +/* Cryptography IP present or not (0=No, 1=Yes) */ +#define CPUSS_CRYPTO_PRESENT 1u +/* DataWire 0 present or not (0=No, 1=Yes) */ +#define CPUSS_DW0_PRESENT 1u +/* Number of DataWire 0 channels (8, 16 or 32) */ +#define CPUSS_DW0_CH_NR 16u +/* DataWire 1 present or not (0=No, 1=Yes) */ +#define CPUSS_DW1_PRESENT 1u +/* Number of DataWire 1 channels (8, 16 or 32) */ +#define CPUSS_DW1_CH_NR 16u +/* AES cipher support (0 = no support, 1 = support */ +#define CPUSS_CRYPTO_AES 1u +/* (Tripple) DES cipher support (0 = no support, 1 = support */ +#define CPUSS_CRYPTO_DES 1u +/* Pseudo random number generation support (0 = no support, 1 = support) */ +#define CPUSS_CRYPTO_PR 1u +/* SHA support included */ +#define CPUSS_CRYPTO_SHA 1u +/* SHA1 hash support (0 = no support, 1 = support) */ +#define CPUSS_CRYPTO_SHA1 1u +/* SHA256 hash support (0 = no support, 1 = support) */ +#define CPUSS_CRYPTO_SHA256 1u +/* SHA512 hash support (0 = no support, 1 = support) */ +#define CPUSS_CRYPTO_SHA512 1u +/* Cyclic Redundancy Check support (0 = no support, 1 = support) */ +#define CPUSS_CRYPTO_CRC 1u +/* Vector unit support (0 = no support, 1 = support) */ +#define CPUSS_CRYPTO_VU 1u +/* True random number generation support (0 = no support, 1 = support) */ +#define CPUSS_CRYPTO_TR 1u +/* String support (0 = no support, 1 = support) */ +#define CPUSS_CRYPTO_STR 1u +/* AHB-Lite master interface support (0 = no support, 1 = support) */ +#define CPUSS_CRYPTO_MASTER_IF 1u +/* Number of 32-bit words in the IP internal memory buffer (from the set [64, 128, + 256, 512, 1024, 2048, 4096], to allow for a 256 B, 512 B, 1 kB, 2 kB, 4 kB, 8 + kB and 16 kB memory buffer) */ +#define CPUSS_CRYPTO_BUFF_SIZE 1024u +/* Number of DataWire controllers present (max 2) */ +#define CPUSS_DW_NR 2u +/* Number of channels in each DataWire controller (must be the same for now) */ +#define CPUSS_DW_CH_NR 16u +/* Number of fault structures. Legal range [1, 4] */ +#define CPUSS_FAULT_FAULT_NR 2u +/* Number of Flash BIST_DATA registers */ +#define CPUSS_FLASHC_FLASHC_BIST_DATA_NR 4u +/* Page size in # of 32-bit words (1: 4 bytes, 2: 8 bytes, ... */ +#define CPUSS_FLASHC_PA_SIZE 128u +/* Number of IPC structures. Legal range [1, 16] */ +#define CPUSS_IPC_IPC_NR 16u +/* Number of IPC interrupt structures. Legal range [1, 16] */ +#define CPUSS_IPC_IPC_IRQ_NR 16u +/* Master 0 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS0_PC_NR_MINUS1 7u +/* Master 1 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS1_PC_NR_MINUS1 7u +/* Master 2 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS2_PC_NR_MINUS1 0u +/* Master 3 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS3_PC_NR_MINUS1 0u +/* Master 4 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS4_PC_NR_MINUS1 0u +/* Master 5 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS5_PC_NR_MINUS1 0u +/* Master 6 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS6_PC_NR_MINUS1 0u +/* Master 7 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS7_PC_NR_MINUS1 0u +/* Master 8 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS8_PC_NR_MINUS1 0u +/* Master 9 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS9_PC_NR_MINUS1 0u +/* Master 10 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS10_PC_NR_MINUS1 0u +/* Master 11 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS11_PC_NR_MINUS1 0u +/* Master 12 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS12_PC_NR_MINUS1 0u +/* Master 13 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS13_PC_NR_MINUS1 0u +/* Master 14 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS14_PC_NR_MINUS1 7u +/* Master 15 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS15_PC_NR_MINUS1 7u +/* Number of SMPU protection structures */ +#define CPUSS_PROT_SMPU_STRUCT_NR 16u +/* Number of protection contexts supported minus 1. Legal range [1,16] */ +#define CPUSS_SMPU_STRUCT_PC_NR_MINUS1 7u +/* Number of instantiated eFUSE macros (256 bit macros). Legal range [1, 16] */ +#define EFUSE_EFUSE_NR 4u /* Number of GPIO ports in range 0..31 */ #define IOSS_GPIO_GPIO_PORT_NR_0_31 15u /* Number of GPIO ports in range 32..63 */ @@ -1710,8 +1821,53 @@ typedef PDM_V1_Type PDM_Type; #define IOSS_GPIO_GPIO_PORT_NR_96_127 0u /* Number of ports in device */ #define IOSS_GPIO_GPIO_PORT_NR 15u +/* Number of AMUX splitter cells */ +#define IOSS_HSIOM_AMUX_SPLIT_NR 9u +/* Number of HSIOM ports in device (same as GPIO.GPIO_PRT_NR) */ +#define IOSS_HSIOM_HSIOM_PORT_NR 15u /* Mask of SMARTIO instances presence */ #define IOSS_SMARTIO_SMARTIO_MASK 768u +/* Number of ports supoprting up to 4 COMs */ +#define LCD_NUMPORTS 8u +/* Number of ports supporting up to 8 COMs */ +#define LCD_NUMPORTS8 8u +/* Number of ports supporting up to 16 COMs */ +#define LCD_NUMPORTS16 0u +/* Max number of LCD commons supported */ +#define LCD_CHIP_TOP_COM_NR 8u +/* Max number of LCD pins (total) supported */ +#define LCD_CHIP_TOP_PIN_NR 62u +/* Number of IREF outputs from AREF */ +#define PASS_NR_IREFS 4u +/* Number of CTBs in the Subsystem */ +#define PASS_NR_CTBS 1u +/* Number of CTDACs in the Subsystem */ +#define PASS_NR_CTDACS 1u +/* CTB0 Exists */ +#define PASS_CTB0_EXISTS 1u +/* CTB1 Exists */ +#define PASS_CTB1_EXISTS 0u +/* CTB2 Exists */ +#define PASS_CTB2_EXISTS 0u +/* CTB3 Exists */ +#define PASS_CTB3_EXISTS 0u +/* CTDAC0 Exists */ +#define PASS_CTDAC0_EXISTS 1u +/* CTDAC1 Exists */ +#define PASS_CTDAC1_EXISTS 0u +/* CTDAC2 Exists */ +#define PASS_CTDAC2_EXISTS 0u +/* CTDAC3 Exists */ +#define PASS_CTDAC3_EXISTS 0u +#define PASS_CTBM_CTDAC_PRESENT 1u +/* Number of SAR channels */ +#define PASS_SAR_SAR_CHANNELS 16u +/* Averaging logic present in SAR */ +#define PASS_SAR_SAR_AVERAGE 1u +/* Range detect logic present in SAR */ +#define PASS_SAR_SAR_RANGEDET 1u +/* Support for UAB sampling */ +#define PASS_SAR_SAR_UAB 0u /* The number of protection contexts ([2, 16]). */ #define PERI_PC_NR 8u /* Master interface presence mask (4 bits) */ @@ -2284,208 +2440,10 @@ typedef PDM_V1_Type PDM_Type; #define PERI_PPU_FIXED_STRUCT_PC_NR_MINUS1 7u /* The number of protection contexts minus 1 ([1, 15]). */ #define PERI_PPU_PROG_STRUCT_PC_NR_MINUS1 7u -/* UDB present or not ('0': no, '1': yes) */ -#define CPUSS_UDB_PRESENT 1u -/* System RAM 0 size in kilobytes */ -#define CPUSS_SRAM0_SIZE 288u -/* Number of macros used to implement System RAM 0. Example: 8 if 256 KB System - SRAM0 is implemented with 8 32KB macros. */ -#define CPUSS_RAMC0_MACRO_NR 9u -/* System RAM 1 present or not (0=No, 1=Yes) */ -#define CPUSS_RAMC1_PRESENT 0u -/* System RAM 1 size in kilobytes */ -#define CPUSS_SRAM1_SIZE 32u -/* Number of macros used to implement System RAM 1. Example: 8 if 256 KB System - RAM 1 is implemented with 8 32KB macros. */ -#define CPUSS_RAMC1_MACRO_NR 1u -/* System RAM 2 present or not (0=No, 1=Yes) */ -#define CPUSS_RAMC2_PRESENT 0u -/* System RAM 2 size in kilobytes */ -#define CPUSS_SRAM2_SIZE 256u -/* Number of macros used to implement System RAM 2. Example: 8 if 256 KB System - RAM 2 is implemented with 8 32KB macros. */ -#define CPUSS_RAMC2_MACRO_NR 16u -/* System ROM size in KB */ -#define CPUSS_ROM_SIZE 128u -/* Flash main region size in KB */ -#define CPUSS_FLASH_SIZE 1024u -/* Flash work region size in KB (EEPROM emulation, data) */ -#define CPUSS_WFLASH_SIZE 32u -/* Flash supervisory region size in KB */ -#define CPUSS_SFLASH_SIZE 32u -/* Flash data output size (in Bytes) */ -#define CPUSS_FLASHC_WORD_SIZE 16u -/* Flash row address width */ -#define CPUSS_FLASHC_ROW_ADDR_WIDTH 12u -/* Flash column address width */ -#define CPUSS_FLASHC_COL_ADDR_WIDTH 5u -/* Number of external slaves directly connected to slow AHB-Lite infrastructure. - Maximum nubmer of slave supported is 4. Width of this parameter is 4-bits. - 1-bit mask for each slave indicating present or not. Example: 4'b0011 - slave - 0 and slave 1 are present. Note: The SLOW_SLx_ADDR and SLOW_SLx_MASK - parameters (for the slaves present) should be derived from the Memory Map. */ -#define CPUSS_SLOW_SL_PRESENT 1u -/* Number of external slaves directly connected to fast AHB-Lite infrastructure. - Maximum nubmer of slave supported is 4. Width of this parameter is 4-bits. - 1-bit mask for each slave indicating present or not. Example: 4'b0011 - slave - 0 and slave 1 are present. Note: The FAST_SLx_ADDR and FAST_SLx_MASK - parameters (for the slaves present) should be derived from the Memory Map. */ -#define CPUSS_FAST_SL_PRESENT 1u -/* Number of external masters driving the slow AHB-Lite infrastructure. Maximum - number of masters supported is 2. Width of this parameter is 2-bits. 1-bit - mask for each master indicating present or not. Example: 2'b01 - master 0 is - present. */ -#define CPUSS_SLOW_MS_PRESENT 0u -/* Number of total interrupt request inputs to CPUSS */ -#define CPUSS_IRQ_NR 147u -/* Number of DeepSleep wakeup interrupt inputs to CPUSS */ -#define CPUSS_DPSLP_IRQ_NR 41u -/* Number of DeepSleep wakeup interrupt inputs to CM0+ (product configuration) */ -#define CPUSS_CM0_DPSLP_IRQ_NR 8u -/* Width of the CM4 interrupt priority bits. Legal range [3,8] Example: 3 = 8 - levels of priority 8 = 256 levels of priority */ -#define CPUSS_CM4_LVL_WIDTH 3u -/* CM4 Floating point unit present or not (0=No, 1=Yes) */ -#define CPUSS_CM4_FPU_PRESENT 1u -/* Debug level. Legal range [0,3] */ -#define CPUSS_DEBUG_LVL 3u -/* Trace level. Legal range [0,2] Note: CM4 HTM is not supported. Hence vaule 3 - for trace level is not supported in CPUSS. */ -#define CPUSS_TRACE_LVL 2u -/* Embedded Trace Buffer present or not (0=No, 1=Yes) */ -#define CPUSS_ETB_PRESENT 0u -/* CM0+ MTB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */ -#define CPUSS_MTB_SRAM_SIZE 4u -/* CM4 ETB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */ -#define CPUSS_ETB_SRAM_SIZE 16u -/* PTM interface present (0=No, 1=Yes) */ -#define CPUSS_PTM_PRESENT 1u -/* Width of the PTM interface in bits ([2,32]) */ -#define CPUSS_PTM_WIDTH 8u -/* Width of the TPIU interface in bits ([1,32]) */ -#define CPUSS_TPIU_WIDTH 4u -/* CoreSight Part Identification Number */ -#define CPUSS_JEPID 52u -/* CoreSight Part Identification Number */ -#define CPUSS_JEPCONTINUATION 0u -/* CoreSight Part Identification Number */ -#define CPUSS_FAMILYID 256u -/* Cryptography IP present or not (0=No, 1=Yes) */ -#define CPUSS_CRYPTO_PRESENT 1u -/* DataWire 0 present or not (0=No, 1=Yes) */ -#define CPUSS_DW0_PRESENT 1u -/* Number of DataWire 0 channels (8, 16 or 32) */ -#define CPUSS_DW0_CH_NR 16u -/* DataWire 1 present or not (0=No, 1=Yes) */ -#define CPUSS_DW1_PRESENT 1u -/* Number of DataWire 1 channels (8, 16 or 32) */ -#define CPUSS_DW1_CH_NR 16u -/* Number of Flash BIST_DATA registers */ -#define CPUSS_FLASHC_FLASHC_BIST_DATA_NR 4u -/* Page size in # of 32-bit words (1: 4 bytes, 2: 8 bytes, ... */ -#define CPUSS_FLASHC_PA_SIZE 128u -/* AES cipher support (0 = no support, 1 = support */ -#define CPUSS_CRYPTO_AES 1u -/* (Tripple) DES cipher support (0 = no support, 1 = support */ -#define CPUSS_CRYPTO_DES 1u -/* Pseudo random number generation support (0 = no support, 1 = support) */ -#define CPUSS_CRYPTO_PR 1u -/* SHA support included */ -#define CPUSS_CRYPTO_SHA 1u -/* SHA1 hash support (0 = no support, 1 = support) */ -#define CPUSS_CRYPTO_SHA1 1u -/* SHA256 hash support (0 = no support, 1 = support) */ -#define CPUSS_CRYPTO_SHA256 1u -/* SHA512 hash support (0 = no support, 1 = support) */ -#define CPUSS_CRYPTO_SHA512 1u -/* Cyclic Redundancy Check support (0 = no support, 1 = support) */ -#define CPUSS_CRYPTO_CRC 1u -/* Vector unit support (0 = no support, 1 = support) */ -#define CPUSS_CRYPTO_VU 1u -/* True random number generation support (0 = no support, 1 = support) */ -#define CPUSS_CRYPTO_TR 1u -/* String support (0 = no support, 1 = support) */ -#define CPUSS_CRYPTO_STR 1u -/* AHB-Lite master interface support (0 = no support, 1 = support) */ -#define CPUSS_CRYPTO_MASTER_IF 1u -/* Number of 32-bit words in the IP internal memory buffer (from the set [64, 128, - 256, 512, 1024, 2048, 4096], to allow for a 256 B, 512 B, 1 kB, 2 kB, 4 kB, 8 - kB and 16 kB memory buffer) */ -#define CPUSS_CRYPTO_BUFF_SIZE 1024u -/* Number of fault structures. Legal range [1, 4] */ -#define CPUSS_FAULT_FAULT_NR 2u -/* Number of IPC structures. Legal range [1, 16] */ -#define CPUSS_IPC_IPC_NR 16u -/* Number of IPC interrupt structures. Legal range [1, 16] */ -#define CPUSS_IPC_IPC_IRQ_NR 16u -/* Master 0 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS0_PC_NR_MINUS1 7u -/* Master 1 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS1_PC_NR_MINUS1 7u -/* Master 2 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS2_PC_NR_MINUS1 0u -/* Master 3 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS3_PC_NR_MINUS1 0u -/* Master 4 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS4_PC_NR_MINUS1 0u -/* Master 5 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS5_PC_NR_MINUS1 0u -/* Master 6 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS6_PC_NR_MINUS1 0u -/* Master 7 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS7_PC_NR_MINUS1 0u -/* Master 8 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS8_PC_NR_MINUS1 0u -/* Master 9 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS9_PC_NR_MINUS1 0u -/* Master 10 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS10_PC_NR_MINUS1 0u -/* Master 11 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS11_PC_NR_MINUS1 0u -/* Master 12 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS12_PC_NR_MINUS1 0u -/* Master 13 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS13_PC_NR_MINUS1 0u -/* Master 14 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS14_PC_NR_MINUS1 7u -/* Master 15 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS15_PC_NR_MINUS1 7u -/* Number of SMPU protection structures */ -#define CPUSS_PROT_SMPU_STRUCT_NR 16u -/* Number of protection contexts supported minus 1. Legal range [1,16] */ -#define CPUSS_SMPU_STRUCT_PC_NR_MINUS1 7u -/* Number of DataWire controllers present (max 2) */ -#define CPUSS_DW_NR 2u -/* Number of channels in each DataWire controller (must be the same for now) */ -#define CPUSS_DW_CH_NR 16u /* Number of profiling counters. Legal range [1, 32] */ #define PROFILE_PRFL_CNT_NR 8u /* Number of monitor event signals. Legal range [1, 128] */ #define PROFILE_PRFL_MONITOR_NR 128u -/* Number of instantiated eFUSE macros (256 bit macros). Legal range [1, 16] */ -#define EFUSE_EFUSE_NR 4u -/* SONOS Flash is used or not ('0': no, '1': yes) */ -#define SFLASH_FLASHC_IS_SONOS 1u -/* CPUSS_WOUNDING_PRESENT or not ('0': no, '1': yes) */ -#define SFLASH_CPUSS_WOUNDING_PRESENT 1u -/* Number of UDB Interrupts */ -#define UDB_NUMINT 16u -/* Number of triggers */ -#define UDB_NUMTR 16u -/* Number of UDB array rows (must be multiple of 2) */ -#define UDB_NUMROW 2u -/* Number of UDB array columns */ -#define UDB_NUMCOL 6u -/* DSI on bottom (1) or on bottom and top (2) of UDB array */ -#define UDB_DSISIDES 2u -/* Number of UDBs = NUMROW * NUMCOL */ -#define UDB_NUMUDB 12u -/* Number of UDB pairs = NUMUDB / 2 */ -#define UDB_NUMUDBPAIR 6u -/* Number of DSIs = NUMCOL * DSISIDES */ -#define UDB_NUMDSI 12u -/* Number of quad clocks */ -#define UDB_NUMQCLK 3u /* DeepSleep support ('0':no, '1': yes) */ #define SCB0_DEEPSLEEP 0u /* Externally clocked support? ('0': no, '1': yes) */ @@ -2936,55 +2894,10 @@ typedef PDM_V1_Type PDM_Type; #define SCB8_I2C_FAST_PLUS 1u /* Number of used spi_select signals (max 4) */ #define SCB8_CHIP_TOP_SPI_SEL_NR 1u -/* Number of counters per IP (1..8) */ -#define TCPWM0_CNT_NR 8u -/* Counter width (in number of bits) */ -#define TCPWM0_CNT_CNT_WIDTH 32u -/* Number of counters per IP (1..8) */ -#define TCPWM1_CNT_NR 24u -/* Counter width (in number of bits) */ -#define TCPWM1_CNT_CNT_WIDTH 16u -/* Number of ports supoprting up to 4 COMs */ -#define LCD_NUMPORTS 8u -/* Number of ports supporting up to 8 COMs */ -#define LCD_NUMPORTS8 8u -/* Number of ports supporting up to 16 COMs */ -#define LCD_NUMPORTS16 0u -/* Max number of LCD commons supported */ -#define LCD_CHIP_TOP_COM_NR 8u -/* Max number of LCD pins (total) supported */ -#define LCD_CHIP_TOP_PIN_NR 62u -/* Number of IREF outputs from AREF */ -#define PASS_NR_IREFS 4u -/* Number of CTBs in the Subsystem */ -#define PASS_NR_CTBS 1u -/* Number of CTDACs in the Subsystem */ -#define PASS_NR_CTDACS 1u -/* CTB0 Exists */ -#define PASS_CTB0_EXISTS 1u -/* CTB1 Exists */ -#define PASS_CTB1_EXISTS 0u -/* CTB2 Exists */ -#define PASS_CTB2_EXISTS 0u -/* CTB3 Exists */ -#define PASS_CTB3_EXISTS 0u -/* CTDAC0 Exists */ -#define PASS_CTDAC0_EXISTS 1u -/* CTDAC1 Exists */ -#define PASS_CTDAC1_EXISTS 0u -/* CTDAC2 Exists */ -#define PASS_CTDAC2_EXISTS 0u -/* CTDAC3 Exists */ -#define PASS_CTDAC3_EXISTS 0u -/* Number of SAR channels */ -#define PASS_SAR_SAR_CHANNELS 16u -/* Averaging logic present in SAR */ -#define PASS_SAR_SAR_AVERAGE 1u -/* Range detect logic present in SAR */ -#define PASS_SAR_SAR_RANGEDET 1u -/* Support for UAB sampling */ -#define PASS_SAR_SAR_UAB 0u -#define PASS_CTBM_CTDAC_PRESENT 1u +/* SONOS Flash is used or not ('0': no, '1': yes) */ +#define SFLASH_FLASHC_IS_SONOS 1u +/* CPUSS_WOUNDING_PRESENT or not ('0': no, '1': yes) */ +#define SFLASH_CPUSS_WOUNDING_PRESENT 1u /* Number of AHB-Lite "hmaster[]" bits ([1, 8]) */ #define SMIF_MASTER_WIDTH 8u /* Base address of the SMIF XIP memory region. This address must be a multiple of @@ -3010,10 +2923,97 @@ typedef PDM_V1_Type PDM_Type; #define SMIF_CHIP_TOP_DATA8_PRESENT 1u /* Number of used spi_select signals (max 4) */ #define SMIF_CHIP_TOP_SPI_SEL_NR 4u -/* I2S capable? (0=No,1=Yes) */ -#define AUDIOSS_I2S 1u -/* PDM capable? (0=No,1=Yes) */ -#define AUDIOSS_PDM 1u +/* Number of regulator modules instantiated within SRSS */ +#define SRSS_NUM_ACTREG_PWRMOD 2u +/* Number of shorting switches between vccd and vccact */ +#define SRSS_NUM_ACTIVE_SWITCH 3u +/* ULP linear regulator system is present */ +#define SRSS_ULPLINREG_PRESENT 1u +/* HT linear regulator system is present */ +#define SRSS_HTLINREG_PRESENT 0u +/* SIMO buck core regulator is present. Only compatible with ULP linear regulator + system (ULPLINREG_PRESENT==1). */ +#define SRSS_SIMOBUCK_PRESENT 1u +/* Precision ILO (PILO) is present */ +#define SRSS_PILO_PRESENT 1u +/* External Crystal Oscillator is present (high frequency) */ +#define SRSS_ECO_PRESENT 1u +/* System Buck-Boost is present */ +#define SRSS_SYSBB_PRESENT 0u +/* Number of clock paths. Must be > 0 */ +#define SRSS_NUM_CLKPATH 5u +/* Number of PLLs present. Must be <= NUM_CLKPATH */ +#define SRSS_NUM_PLL 1u +/* Number of HFCLK roots present. Must be > 0 */ +#define SRSS_NUM_HFROOT 5u +/* Number of PWR_HIB_DATA registers */ +#define SRSS_NUM_HIBDATA 1u +/* Backup domain is present */ +#define SRSS_BACKUP_PRESENT 1u +/* Mask of HFCLK root clock supervisors (CSV). For each clock root i, bit[i] of + mask indicates presence of a CSV. */ +#define SRSS_MASK_HFCSV 0u +/* Clock supervisor is present on WCO. Must be 0 if BACKUP_PRESENT==0. */ +#define SRSS_WCOCSV_PRESENT 0u +/* Number of software watchdog timers. */ +#define SRSS_NUM_MCWDT 2u +/* Number of DSI inputs into clock muxes. This is used for logic optimization. */ +#define SRSS_NUM_DSI 2u +/* Alternate high-frequency clock is present. This is used for logic optimization. */ +#define SRSS_ALTHF_PRESENT 1u +/* Alternate low-frequency clock is present. This is used for logic optimization. */ +#define SRSS_ALTLF_PRESENT 0u +/* Use the hardened clkactfllmux block */ +#define SRSS_USE_HARD_CLKACTFLLMUX 1u +/* Number of clock paths, including direct paths in hardened clkactfllmux block + (Must be >= NUM_CLKPATH) */ +#define SRSS_HARD_CLKPATH 6u +/* Number of clock paths with muxes in hardened clkactfllmux block (Must be >= + NUM_PLL+1) */ +#define SRSS_HARD_CLKPATHMUX 6u +/* Number of HFCLKS present in hardened clkactfllmux block (Must be >= NUM_HFROOT) */ +#define SRSS_HARD_HFROOT 6u +/* ECO mux is present in hardened clkactfllmux block (Must be >= ECO_PRESENT) */ +#define SRSS_HARD_ECOMUX_PRESENT 1u +/* ALTHF mux is present in hardened clkactfllmux block (Must be >= ALTHF_PRESENT) */ +#define SRSS_HARD_ALTHFMUX_PRESENT 1u +/* Low-current buck regulator present. Can be derived from S40S_SISOBUCKLC_PRESENT + or SIMOBUCK_PRESENT. */ +#define SRSS_BUCKCTL_PRESENT 1u +/* Low-current SISO buck core regulator is present. Only compatible with ULP + linear regulator system (ULPLINREG_PRESENT==1). */ +#define SRSS_S40S_SISOBUCKLC_PRESENT 0u +/* Backup memory is present (only used when BACKUP_PRESENT==1) */ +#define SRSS_BACKUP_BMEM_PRESENT 0u +/* Number of Backup registers to include (each is 32b). Only used when + BACKUP_PRESENT==1. */ +#define SRSS_BACKUP_NUM_BREG 16u +/* Number of counters per IP (1..8) */ +#define TCPWM0_CNT_NR 8u +/* Counter width (in number of bits) */ +#define TCPWM0_CNT_CNT_WIDTH 32u +/* Number of counters per IP (1..8) */ +#define TCPWM1_CNT_NR 24u +/* Counter width (in number of bits) */ +#define TCPWM1_CNT_CNT_WIDTH 16u +/* Number of UDB Interrupts */ +#define UDB_NUMINT 16u +/* Number of triggers */ +#define UDB_NUMTR 16u +/* Number of UDB array rows (must be multiple of 2) */ +#define UDB_NUMROW 2u +/* Number of UDB array columns */ +#define UDB_NUMCOL 6u +/* DSI on bottom (1) or on bottom and top (2) of UDB array */ +#define UDB_DSISIDES 2u +/* Number of UDBs = NUMROW * NUMCOL */ +#define UDB_NUMUDB 12u +/* Number of UDB pairs = NUMUDB / 2 */ +#define UDB_NUMUDBPAIR 6u +/* Number of DSIs = NUMCOL * DSISIDES */ +#define UDB_NUMDSI 12u +/* Number of quad clocks */ +#define UDB_NUMQCLK 3u /* MMIO Targets Defines */ #define CY_MMIO_CRYPTO_GROUP_NR 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/psoc6_02_config.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/psoc6_02_config.h index e131351a4a..974842e1b4 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/psoc6_02_config.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/psoc6_02_config.h @@ -5,7 +5,7 @@ * PSoC6_02 device configuration header * * \note -* Generator version: 1.6.0.111 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -1537,59 +1537,59 @@ typedef enum } en_trig_type_t; /* Trigger Type Defines */ -/* TCPWM Trigger Types */ -#define TRIGGER_TYPE_TCPWM_LINE TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_TCPWM_LINE_COMPL TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_TCPWM_TR_OVERFLOW TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_TCPWM_TR_COMPARE_MATCH TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_TCPWM_TR_UNDERFLOW TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_TCPWM_TR_IN__LEVEL TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_TCPWM_TR_IN__EDGE TRIGGER_TYPE_EDGE +/* AUDIOSS Trigger Types */ +#define TRIGGER_TYPE_AUDIOSS_TR_I2S_RX_REQ TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_AUDIOSS_TR_I2S_TX_REQ TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_AUDIOSS_TR_PDM_RX_REQ TRIGGER_TYPE_LEVEL +/* CPUSS Trigger Types */ +#define TRIGGER_TYPE_CPUSS_CTI_TR_IN TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_CTI_TR_OUT TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_DMAC_TR_IN__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_CPUSS_DMAC_TR_IN__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_DMAC_TR_OUT TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_DW0_TR_IN__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_CPUSS_DW0_TR_IN__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_DW0_TR_OUT TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_DW1_TR_IN__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_CPUSS_DW1_TR_IN__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_DW1_TR_OUT TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_TR_FAULT TRIGGER_TYPE_EDGE /* CSD Trigger Types */ #define TRIGGER_TYPE_CSD_DSI_SAMPLE_OUT TRIGGER_TYPE_EDGE -/* SCB Trigger Types */ -#define TRIGGER_TYPE_SCB_TR_I2C_SCL_FILTERED TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_SCB_TR_TX_REQ TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_SCB_TR_RX_REQ TRIGGER_TYPE_LEVEL +/* LPCOMP Trigger Types */ +#define TRIGGER_TYPE_LPCOMP_DSI_COMP0 TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_LPCOMP_DSI_COMP1 TRIGGER_TYPE_LEVEL +/* PASS Trigger Types */ +#define TRIGGER_TYPE_PASS_TR_SAR_IN__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_PASS_TR_SAR_IN__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_PASS_TR_SAR_OUT TRIGGER_TYPE_EDGE /* PERI Trigger Types */ +#define TRIGGER_TYPE_PERI_TR_DBG_FREEZE TRIGGER_TYPE_LEVEL #define TRIGGER_TYPE_PERI_TR_IO_INPUT__LEVEL TRIGGER_TYPE_LEVEL #define TRIGGER_TYPE_PERI_TR_IO_INPUT__EDGE TRIGGER_TYPE_EDGE #define TRIGGER_TYPE_PERI_TR_IO_OUTPUT__LEVEL TRIGGER_TYPE_LEVEL #define TRIGGER_TYPE_PERI_TR_IO_OUTPUT__EDGE TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_PERI_TR_DBG_FREEZE TRIGGER_TYPE_LEVEL -/* CPUSS Trigger Types */ -#define TRIGGER_TYPE_CPUSS_DW0_TR_IN__LEVEL TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_CPUSS_DW0_TR_IN__EDGE TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_CPUSS_DW1_TR_IN__LEVEL TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_CPUSS_DW1_TR_IN__EDGE TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_CPUSS_DMAC_TR_IN__LEVEL TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_CPUSS_DMAC_TR_IN__EDGE TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_CPUSS_DW0_TR_OUT TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_CPUSS_DW1_TR_OUT TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_CPUSS_DMAC_TR_OUT TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_CPUSS_CTI_TR_OUT TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_CPUSS_TR_FAULT TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_CPUSS_CTI_TR_IN TRIGGER_TYPE_EDGE -/* AUDIOSS Trigger Types */ -#define TRIGGER_TYPE_AUDIOSS_TR_I2S_TX_REQ TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_AUDIOSS_TR_I2S_RX_REQ TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_AUDIOSS_TR_PDM_RX_REQ TRIGGER_TYPE_LEVEL -/* LPCOMP Trigger Types */ -#define TRIGGER_TYPE_LPCOMP_DSI_COMP0 TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_LPCOMP_DSI_COMP1 TRIGGER_TYPE_LEVEL -/* SMIF Trigger Types */ -#define TRIGGER_TYPE_SMIF_TR_TX_REQ TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_SMIF_TR_RX_REQ TRIGGER_TYPE_LEVEL -/* USB Trigger Types */ -#define TRIGGER_TYPE_USB_DMA_REQ TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_USB_DMA_BURSTEND TRIGGER_TYPE_EDGE -/* PASS Trigger Types */ -#define TRIGGER_TYPE_PASS_TR_SAR_OUT TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_PASS_TR_SAR_IN__LEVEL TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_PASS_TR_SAR_IN__EDGE TRIGGER_TYPE_EDGE /* PROFILE Trigger Types */ #define TRIGGER_TYPE_PROFILE_TR_START TRIGGER_TYPE_EDGE #define TRIGGER_TYPE_PROFILE_TR_STOP TRIGGER_TYPE_EDGE +/* SCB Trigger Types */ +#define TRIGGER_TYPE_SCB_TR_I2C_SCL_FILTERED TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_SCB_TR_RX_REQ TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_SCB_TR_TX_REQ TRIGGER_TYPE_LEVEL +/* SMIF Trigger Types */ +#define TRIGGER_TYPE_SMIF_TR_RX_REQ TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_SMIF_TR_TX_REQ TRIGGER_TYPE_LEVEL +/* TCPWM Trigger Types */ +#define TRIGGER_TYPE_TCPWM_LINE TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_TCPWM_LINE_COMPL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_TCPWM_TR_COMPARE_MATCH TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_TCPWM_TR_IN__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_TCPWM_TR_IN__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_TCPWM_TR_OVERFLOW TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_TCPWM_TR_UNDERFLOW TRIGGER_TYPE_EDGE +/* USB Trigger Types */ +#define TRIGGER_TYPE_USB_DMA_BURSTEND TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_USB_DMA_REQ TRIGGER_TYPE_EDGE /* Monitor Signal Defines */ typedef enum @@ -1746,89 +1746,268 @@ typedef PDM_V1_Type PDM_Type; typedef I2S_V1_Type I2S_Type; /* Parameter Defines */ -/* Number of regulator modules instantiated within SRSS, start with estimate, - update after CMR feedback */ -#define SRSS_NUM_ACTREG_PWRMOD 2u -/* Number of shorting switches between vccd and vccact (target dynamic voltage - drop < 10mV) */ -#define SRSS_NUM_ACTIVE_SWITCH 3u -/* ULP linear regulator system is present */ -#define SRSS_ULPLINREG_PRESENT 1u -/* HT linear regulator system is present */ -#define SRSS_HTLINREG_PRESENT 0u -/* Low-current buck regulator present. Can be derived from S40S_SISOBUCKLC_PRESENT - or SIMOBUCK_PRESENT. */ -#define SRSS_BUCKCTL_PRESENT 1u -/* Low-current SISO buck core regulator is present. Only compatible with ULP - linear regulator system (ULPLINREG_PRESENT==1). */ -#define SRSS_S40S_SISOBUCKLC_PRESENT 1u -/* SIMO buck core regulator is present. Only compatible with ULP linear regulator - system (ULPLINREG_PRESENT==1). */ -#define SRSS_SIMOBUCK_PRESENT 0u -/* Precision ILO (PILO) is present */ -#define SRSS_PILO_PRESENT 0u -/* External Crystal Oscillator is present (high frequency) */ -#define SRSS_ECO_PRESENT 1u -/* System Buck-Boost is present */ -#define SRSS_SYSBB_PRESENT 0u -/* Number of clock paths. Must be > 0 */ -#define SRSS_NUM_CLKPATH 6u -/* Number of PLLs present. Must be <= NUM_CLKPATH */ -#define SRSS_NUM_PLL 2u -/* Number of HFCLK roots present. Must be > 0 */ -#define SRSS_NUM_HFROOT 6u -/* Number of PWR_HIB_DATA registers, should not be needed if BACKUP_PRESENT */ -#define SRSS_NUM_HIBDATA 1u -/* Backup domain is present (includes RTC and WCO) */ -#define SRSS_BACKUP_PRESENT 1u -/* Mask of HFCLK root clock supervisors (CSV). For each clock root i, bit[i] of - mask indicates presence of a CSV. */ -#define SRSS_MASK_HFCSV 0u -/* Clock supervisor is present on WCO. Must be 0 if BACKUP_PRESENT==0. */ -#define SRSS_WCOCSV_PRESENT 0u -/* Number of software watchdog timers. */ -#define SRSS_NUM_MCWDT 2u -/* Number of DSI inputs into clock muxes. This is used for logic optimization. */ -#define SRSS_NUM_DSI 0u -/* Alternate high-frequency clock is present. This is used for logic optimization. */ -#define SRSS_ALTHF_PRESENT 0u -/* Alternate low-frequency clock is present. This is used for logic optimization. */ -#define SRSS_ALTLF_PRESENT 0u -/* Use the hardened clkactfllmux block */ -#define SRSS_USE_HARD_CLKACTFLLMUX 1u -/* Number of clock paths, including direct paths in hardened clkactfllmux block - (Must be >= NUM_CLKPATH) */ -#define SRSS_HARD_CLKPATH 6u -/* Number of clock paths with muxes in hardened clkactfllmux block (Must be >= - NUM_PLL+1) */ -#define SRSS_HARD_CLKPATHMUX 6u -/* Number of HFCLKS present in hardened clkactfllmux block (Must be >= NUM_HFROOT) */ -#define SRSS_HARD_HFROOT 6u -/* ECO mux is present in hardened clkactfllmux block (Must be >= ECO_PRESENT) */ -#define SRSS_HARD_ECOMUX_PRESENT 1u -/* ALTHF mux is present in hardened clkactfllmux block (Must be >= ALTHF_PRESENT) */ -#define SRSS_HARD_ALTHFMUX_PRESENT 1u -/* Backup memory is present (only used when BACKUP_PRESENT==1) */ -#define SRSS_BACKUP_BMEM_PRESENT 0u -/* Number of Backup registers to include (each is 32b). Only used when - BACKUP_PRESENT==1. */ -#define SRSS_BACKUP_NUM_BREG 16u -/* Number of AMUX splitter cells */ -#define IOSS_HSIOM_AMUX_SPLIT_NR 8u -/* Number of HSIOM ports in device (same as GPIO.GPIO_PRT_NR) */ -#define IOSS_HSIOM_HSIOM_PORT_NR 15u -/* Number of PWR/GND MONITOR CELLs in the device */ -#define IOSS_HSIOM_MONITOR_NR 0u -/* Number of PWR/GND MONITOR CELLs in range 0..31 */ -#define IOSS_HSIOM_MONITOR_NR_0_31 0u -/* Number of PWR/GND MONITOR CELLs in range 32..63 */ -#define IOSS_HSIOM_MONITOR_NR_32_63 0u -/* Number of PWR/GND MONITOR CELLs in range 64..95 */ -#define IOSS_HSIOM_MONITOR_NR_64_95 0u -/* Number of PWR/GND MONITOR CELLs in range 96..127 */ -#define IOSS_HSIOM_MONITOR_NR_96_127 0u -/* Indicates the presence of alternate JTAG interface */ -#define IOSS_HSIOM_ALTJTAG_PRESENT 0u +/* I2S capable? (0=No,1=Yes) */ +#define AUDIOSS0_I2S 1u +/* PDM capable? (0=No,1=Yes) */ +#define AUDIOSS0_PDM 1u +/* I2S capable? (0=No,1=Yes) */ +#define AUDIOSS1_I2S 1u +/* PDM capable? (0=No,1=Yes) */ +#define AUDIOSS1_PDM 0u +/* UDB present or not ('0': no, '1': yes) */ +#define CPUSS_UDB_PRESENT 0u +/* MBIST MMIO for Synopsys MBIST ('0': no, '1': yes). Set this to '1' only for the + chips which doesn't use mxdft. */ +#define CPUSS_MBIST_MMIO_PRESENT 1u +/* System RAM 0 size in kilobytes */ +#define CPUSS_SRAM0_SIZE 512u +/* Number of macros used to implement System RAM 0. Example: 8 if 256 KB System + SRAM0 is implemented with 8 32KB macros. */ +#define CPUSS_RAMC0_MACRO_NR 16u +/* System RAM 1 present or not (0=No, 1=Yes) */ +#define CPUSS_RAMC1_PRESENT 1u +/* System RAM 1 size in kilobytes */ +#define CPUSS_SRAM1_SIZE 256u +/* Number of macros used to implement System RAM 1. Example: 8 if 256 KB System + RAM 1 is implemented with 8 32KB macros. */ +#define CPUSS_RAMC1_MACRO_NR 8u +/* System RAM 2 present or not (0=No, 1=Yes) */ +#define CPUSS_RAMC2_PRESENT 1u +/* System RAM 2 size in kilobytes */ +#define CPUSS_SRAM2_SIZE 256u +/* Number of macros used to implement System RAM 2. Example: 8 if 256 KB System + RAM 2 is implemented with 8 32KB macros. */ +#define CPUSS_RAMC2_MACRO_NR 8u +/* System SRAM(s) ECC present or not ('0': no, '1': yes) */ +#define CPUSS_RAMC_ECC_PRESENT 0u +/* System SRAM(s) address ECC present or not ('0': no, '1': yes) */ +#define CPUSS_RAMC_ECC_ADDR_PRESENT 0u +/* ECC present in either system RAM or interrupt handler (RAMC_ECC_PRESENT) */ +#define CPUSS_ECC_PRESENT 0u +/* DataWire SRAMs ECC present or not ('0': no, '1': yes) */ +#define CPUSS_DW_ECC_PRESENT 0u +/* DataWire SRAMs address ECC present or not ('0': no, '1': yes) */ +#define CPUSS_DW_ECC_ADDR_PRESENT 0u +/* System ROM size in KB */ +#define CPUSS_ROM_SIZE 64u +/* Number of macros used to implement system ROM. Example: 4 if 512 KB system ROM + is implemented with 4 128KB macros. */ +#define CPUSS_ROMC_MACRO_NR 1u +/* Flash memory type ('0' : SONOS, '1': ECT) */ +#define CPUSS_FLASHC_ECT 0u +/* Flash main region size in KB */ +#define CPUSS_FLASH_SIZE 2048u +/* Flash work region size in KB (EEPROM emulation, data) */ +#define CPUSS_WFLASH_SIZE 32u +/* Flash supervisory region size in KB */ +#define CPUSS_SFLASH_SIZE 32u +/* Flash data output word size (in Bytes) */ +#define CPUSS_FLASHC_MAIN_DATA_WIDTH 16u +/* SONOS Flash RWW present or not ('0': no, '1': yes) When RWW is '0', No special + sectors present in Flash. Part of main sector 0 is allowcated for Supervisory + Flash, and no Work Flash present. */ +#define CPUSS_FLASHC_SONOS_RWW 1u +/* SONOS Flash, number of main sectors. */ +#define CPUSS_FLASHC_SONOS_MAIN_SECTORS 8u +/* SONOS Flash, number of rows per main sector. */ +#define CPUSS_FLASHC_SONOS_MAIN_ROWS 512u +/* SONOS Flash, number of words per row of main sector. */ +#define CPUSS_FLASHC_SONOS_MAIN_WORDS 128u +/* SONOS Flash, number of special sectors. */ +#define CPUSS_FLASHC_SONOS_SPL_SECTORS 2u +/* SONOS Flash, number of rows per special sector. */ +#define CPUSS_FLASHC_SONOS_SPL_ROWS 64u +/* Flash memory ECC present or not ('0': no, '1': yes) */ +#define CPUSS_FLASHC_FLASH_ECC_PRESENT 0u +/* Flash cache SRAM(s) ECC present or not ('0': no, '1': yes) */ +#define CPUSS_FLASHC_RAM_ECC_PRESENT 0u +/* Number of external slaves directly connected to slow AHB-Lite infrastructure. + Maximum nubmer of slave supported is 4. Width of this parameter is 4-bits. + 1-bit mask for each slave indicating present or not. Example: 4'b0011 - slave + 0 and slave 1 are present. Note: The SLOW_SLx_ADDR and SLOW_SLx_MASK + parameters (for the slaves present) should be derived from the Memory Map. */ +#define CPUSS_SLOW_SL_PRESENT 1u +/* Number of external slaves directly connected to fast AHB-Lite infrastructure. + Maximum nubmer of slave supported is 4. Width of this parameter is 4-bits. + 1-bit mask for each slave indicating present or not. Example: 4'b0011 - slave + 0 and slave 1 are present. Note: The FAST_SLx_ADDR and FAST_SLx_MASK + parameters (for the slaves present) should be derived from the Memory Map. */ +#define CPUSS_FAST_SL_PRESENT 1u +/* Number of external masters driving the slow AHB-Lite infrastructure. Maximum + number of masters supported is 2. Width of this parameter is 2-bits. 1-bit + mask for each master indicating present or not. Example: 2'b01 - master 0 is + present. */ +#define CPUSS_SLOW_MS_PRESENT 3u +/* System interrupt functionality present or not ('0': no; '1': yes). Not used for + CM0+ PCU, which always uses system interrupt functionality. */ +#define CPUSS_SYSTEM_IRQ_PRESENT 0u +/* Number of total interrupt request inputs to CPUSS */ +#define CPUSS_SYSTEM_INT_NR 168u +/* Number of DeepSleep wakeup interrupt inputs to CPUSS */ +#define CPUSS_SYSTEM_DPSLP_INT_NR 39u +/* Width of the CM4 interrupt priority bits. Legal range [3,8] Example: 3 = 8 + levels of priority 8 = 256 levels of priority */ +#define CPUSS_CM4_LVL_WIDTH 3u +/* CM4 Floating point unit present or not (0=No, 1=Yes) */ +#define CPUSS_CM4_FPU_PRESENT 1u +/* Debug level. Legal range [0,3] (0= No support, 1= Minimum: CM0/4 both 2 + breakpoints +1 watchpoint, 2= Full debug: CM0/4 have 4/6 breakpoints, 2/4 + watchpoints and 0/2 literal compare, 3= Full debug + data matching) */ +#define CPUSS_DEBUG_LVL 3u +/* Trace level. Legal range [0,2] (0= No tracing, 1= ITM + TPIU + SWO, 2= ITM + + ETM + TPIU + SWO) Note: CM4 HTM is not supported. Hence vaule 3 for trace + level is not supported in CPUSS. */ +#define CPUSS_TRACE_LVL 2u +/* Embedded Trace Buffer present or not (0=No, 1=Yes) */ +#define CPUSS_ETB_PRESENT 0u +/* CM0+ MTB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */ +#define CPUSS_MTB_SRAM_SIZE 4u +/* CM4 ETB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */ +#define CPUSS_ETB_SRAM_SIZE 8u +/* PTM interface present (0=No, 1=Yes) */ +#define CPUSS_PTM_PRESENT 0u +/* Width of the PTM interface in bits ([2,32]) */ +#define CPUSS_PTM_WIDTH 1u +/* Width of the TPIU interface in bits ([1,4]) */ +#define CPUSS_TPIU_WIDTH 4u +/* CoreSight Part Identification Number */ +#define CPUSS_JEPID 52u +/* CoreSight Part Identification Number */ +#define CPUSS_JEPCONTINUATION 0u +/* CoreSight Part Identification Number */ +#define CPUSS_FAMILYID 258u +/* ROM trim register width (for ARM 3, for Synopsys 5) */ +#define CPUSS_ROM_TRIM_WIDTH 5u +/* ROM trim register default (for both ARM and Synopsys 0x0000_0012) */ +#define CPUSS_ROM_TRIM_DEFAULT 18u +/* RAM trim register width (for ARM 8, for Synopsys 15) */ +#define CPUSS_RAM_TRIM_WIDTH 15u +/* RAM trim register default (for ARM 0x0000_0062 and for Synopsys 0x0000_6012) */ +#define CPUSS_RAM_TRIM_DEFAULT 24594u +/* Cryptography IP present or not (0=No, 1=Yes) */ +#define CPUSS_CRYPTO_PRESENT 1u +/* DataWire and DMAC SW trigger per channel present or not ('0': no, '1': yes) */ +#define CPUSS_SW_TR_PRESENT 0u +/* DataWire 0 present or not (0=No, 1=Yes) */ +#define CPUSS_DW0_PRESENT 1u +/* Number of DataWire 0 channels (8, 16 or 32) */ +#define CPUSS_DW0_CH_NR 29u +/* DataWire 1 present or not (0=No, 1=Yes) */ +#define CPUSS_DW1_PRESENT 1u +/* Number of DataWire 1 channels (8, 16 or 32) */ +#define CPUSS_DW1_CH_NR 29u +/* DMA controller present or not ('0': no, '1': yes) */ +#define CPUSS_DMAC_PRESENT 1u +/* Number of DMA controller channels ([1, 8]) */ +#define CPUSS_DMAC_CH_NR 4u +/* DMAC SW trigger per channel present or not ('0': no, '1': yes) */ +#define CPUSS_CH_SW_TR_PRESENT 0u +/* See MMIO2 instantiation or not */ +#define CPUSS_CHIP_TOP_PROFILER_PRESENT 1u +/* ETAS Calibration support pin out present (automotive only) */ +#define CPUSS_CHIP_TOP_CAL_SUP_NZ_PRESENT 0u +/* TRACE_LVL>0 */ +#define CPUSS_CHIP_TOP_TRACE_PRESENT 1u +/* DataWire SW trigger per channel present or not ('0': no, '1': yes) */ +#define CPUSS_CH_STRUCT_SW_TR_PRESENT 0u +/* Number of DataWire controllers present (max 2) (same as DW.NR above) */ +#define CPUSS_CPUSS_DW_DW_NR 2u +/* Number of channels in each DataWire controller */ +#define CPUSS_CPUSS_DW_DW_NR0_DW_CH_NR 29u +/* Width of a channel number in bits */ +#define CPUSS_CPUSS_DW_DW_NR0_DW_CH_NR_WIDTH 5u +/* Number of channels in each DataWire controller */ +#define CPUSS_CPUSS_DW_DW_NR1_DW_CH_NR 29u +/* Width of a channel number in bits */ +#define CPUSS_CPUSS_DW_DW_NR1_DW_CH_NR_WIDTH 5u +/* Cryptography SRAMs ECC present or not ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_ECC_PRESENT 0u +/* Cryptography SRAMs address ECC present or not ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_ECC_ADDR_PRESENT 0u +/* AES cipher support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_AES 1u +/* (Tripple) DES cipher support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_DES 1u +/* Chacha support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_CHACHA 1u +/* Pseudo random number generation support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_PR 1u +/* SHA1 hash support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_SHA1 1u +/* SHA2 hash support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_SHA2 1u +/* SHA3 hash support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_SHA3 1u +/* Cyclic Redundancy Check support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_CRC 1u +/* True random number generation support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_TR 1u +/* Vector unit support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_VU 1u +/* Galios/Counter Mode (GCM) support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_GCM 1u +/* Number of 32-bit words in the IP internal memory buffer (from the set [64, 128, + 256, 512, 1024, 2048, 4096], to allow for a 256 B, 512 B, 1 kB, 2 kB, 4 kB, 8 + kB and 16 kB memory buffer) */ +#define CPUSS_CRYPTO_BUFF_SIZE 1024u +/* Number of DMA controller channels ([1, 8]) */ +#define CPUSS_DMAC_CH_NR 4u +/* Number of DataWire controllers present (max 2) */ +#define CPUSS_DW_NR 2u +/* DataWire SRAMs ECC present or not ('0': no, '1': yes) */ +#define CPUSS_DW_ECC_PRESENT 0u +/* Number of fault structures. Legal range [1, 4] */ +#define CPUSS_FAULT_FAULT_NR 2u +/* Number of Flash BIST_DATA registers */ +#define CPUSS_FLASHC_FLASHC_BIST_DATA_NR 4u +/* Page size in # of 32-bit words (1: 4 bytes, 2: 8 bytes, ... */ +#define CPUSS_FLASHC_PA_SIZE 128u +/* SONOS Flash is used or not ('0': no, '1': yes) */ +#define CPUSS_FLASHC_FLASHC_IS_SONOS 1u +/* eCT Flash is used or not ('0': no, '1': yes) */ +#define CPUSS_FLASHC_FLASHC_IS_ECT 0u +/* Number of IPC structures. Legal range [1, 16] */ +#define CPUSS_IPC_IPC_NR 16u +/* Number of IPC interrupt structures. Legal range [1, 16] */ +#define CPUSS_IPC_IPC_IRQ_NR 16u +/* Master 0 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS0_PC_NR_MINUS1 7u +/* Master 1 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS1_PC_NR_MINUS1 0u +/* Master 2 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS2_PC_NR_MINUS1 0u +/* Master 3 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS3_PC_NR_MINUS1 0u +/* Master 4 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS4_PC_NR_MINUS1 0u +/* Master 5 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS5_PC_NR_MINUS1 7u +/* Master 6 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS6_PC_NR_MINUS1 7u +/* Master 7 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS7_PC_NR_MINUS1 0u +/* Master 8 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS8_PC_NR_MINUS1 0u +/* Master 9 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS9_PC_NR_MINUS1 0u +/* Master 10 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS10_PC_NR_MINUS1 0u +/* Master 11 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS11_PC_NR_MINUS1 0u +/* Master 12 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS12_PC_NR_MINUS1 0u +/* Master 13 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS13_PC_NR_MINUS1 0u +/* Master 14 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS14_PC_NR_MINUS1 7u +/* Master 15 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS15_PC_NR_MINUS1 7u +/* Number of SMPU protection structures */ +#define CPUSS_PROT_SMPU_STRUCT_NR 16u +/* Number of protection contexts supported minus 1. Legal range [1,16] */ +#define CPUSS_SMPU_STRUCT_PC_NR_MINUS1 7u +/* Number of instantiated eFUSE macros (256 bit macros). Legal range [1, 16] */ +#define EFUSE_EFUSE_NR 4u /* Number of GPIO ports in range 0..31 */ #define IOSS_GPIO_GPIO_PORT_NR_0_31 15u /* Number of GPIO ports in range 32..63 */ @@ -2169,8 +2348,65 @@ typedef I2S_V1_Type I2S_Type; #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO6 0u /* Indicates that pin #7 exists for this port with slew control feature */ #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO7 0u +/* Number of AMUX splitter cells */ +#define IOSS_HSIOM_AMUX_SPLIT_NR 8u +/* Number of HSIOM ports in device (same as GPIO.GPIO_PRT_NR) */ +#define IOSS_HSIOM_HSIOM_PORT_NR 15u +/* Number of PWR/GND MONITOR CELLs in the device */ +#define IOSS_HSIOM_MONITOR_NR 0u +/* Number of PWR/GND MONITOR CELLs in range 0..31 */ +#define IOSS_HSIOM_MONITOR_NR_0_31 0u +/* Number of PWR/GND MONITOR CELLs in range 32..63 */ +#define IOSS_HSIOM_MONITOR_NR_32_63 0u +/* Number of PWR/GND MONITOR CELLs in range 64..95 */ +#define IOSS_HSIOM_MONITOR_NR_64_95 0u +/* Number of PWR/GND MONITOR CELLs in range 96..127 */ +#define IOSS_HSIOM_MONITOR_NR_96_127 0u +/* Indicates the presence of alternate JTAG interface */ +#define IOSS_HSIOM_ALTJTAG_PRESENT 0u /* Mask of SMARTIO instances presence */ #define IOSS_SMARTIO_SMARTIO_MASK 768u +/* Number of ports supoprting up to 4 COMs */ +#define LCD_NUMPORTS 8u +/* Number of ports supporting up to 8 COMs */ +#define LCD_NUMPORTS8 8u +/* Number of ports supporting up to 16 COMs */ +#define LCD_NUMPORTS16 0u +/* Max number of LCD commons supported */ +#define LCD_CHIP_TOP_COM_NR 8u +/* Max number of LCD pins (total) supported */ +#define LCD_CHIP_TOP_PIN_NR 62u +/* Number of IREF outputs from AREF */ +#define PASS_NR_IREFS 4u +/* Number of CTBs in the Subsystem */ +#define PASS_NR_CTBS 0u +/* Number of CTDACs in the Subsystem */ +#define PASS_NR_CTDACS 0u +/* CTB0 Exists */ +#define PASS_CTB0_EXISTS 0u +/* CTB1 Exists */ +#define PASS_CTB1_EXISTS 0u +/* CTB2 Exists */ +#define PASS_CTB2_EXISTS 0u +/* CTB3 Exists */ +#define PASS_CTB3_EXISTS 0u +/* CTDAC0 Exists */ +#define PASS_CTDAC0_EXISTS 0u +/* CTDAC1 Exists */ +#define PASS_CTDAC1_EXISTS 0u +/* CTDAC2 Exists */ +#define PASS_CTDAC2_EXISTS 0u +/* CTDAC3 Exists */ +#define PASS_CTDAC3_EXISTS 0u +#define PASS_CTBM_CTDAC_PRESENT 0u +/* Number of SAR channels */ +#define PASS_SAR_SAR_CHANNELS 16u +/* Averaging logic present in SAR */ +#define PASS_SAR_SAR_AVERAGE 1u +/* Range detect logic present in SAR */ +#define PASS_SAR_SAR_RANGEDET 1u +/* Support for UAB sampling */ +#define PASS_SAR_SAR_UAB 0u /* The number of protection contexts ([2, 16]). */ #define PERI_PC_NR 8u /* Master interface presence mask (4 bits) */ @@ -2777,268 +3013,10 @@ typedef I2S_V1_Type I2S_Type; #define PERI_TR_1TO1_GROUP_NR6_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ #define PERI_MASTER_WIDTH 8u -/* UDB present or not ('0': no, '1': yes) */ -#define CPUSS_UDB_PRESENT 0u -/* MBIST MMIO for Synopsys MBIST ('0': no, '1': yes). Set this to '1' only for the - chips which doesn't use mxdft. */ -#define CPUSS_MBIST_MMIO_PRESENT 1u -/* System RAM 0 size in kilobytes */ -#define CPUSS_SRAM0_SIZE 512u -/* Number of macros used to implement System RAM 0. Example: 8 if 256 KB System - SRAM0 is implemented with 8 32KB macros. */ -#define CPUSS_RAMC0_MACRO_NR 16u -/* System RAM 1 present or not (0=No, 1=Yes) */ -#define CPUSS_RAMC1_PRESENT 1u -/* System RAM 1 size in kilobytes */ -#define CPUSS_SRAM1_SIZE 256u -/* Number of macros used to implement System RAM 1. Example: 8 if 256 KB System - RAM 1 is implemented with 8 32KB macros. */ -#define CPUSS_RAMC1_MACRO_NR 8u -/* System RAM 2 present or not (0=No, 1=Yes) */ -#define CPUSS_RAMC2_PRESENT 1u -/* System RAM 2 size in kilobytes */ -#define CPUSS_SRAM2_SIZE 256u -/* Number of macros used to implement System RAM 2. Example: 8 if 256 KB System - RAM 2 is implemented with 8 32KB macros. */ -#define CPUSS_RAMC2_MACRO_NR 8u -/* System SRAM(s) ECC present or not ('0': no, '1': yes) */ -#define CPUSS_RAMC_ECC_PRESENT 0u -/* System SRAM(s) address ECC present or not ('0': no, '1': yes) */ -#define CPUSS_RAMC_ECC_ADDR_PRESENT 0u -/* ECC present in either system RAM or interrupt handler (RAMC_ECC_PRESENT) */ -#define CPUSS_ECC_PRESENT 0u -/* DataWire SRAMs ECC present or not ('0': no, '1': yes) */ -#define CPUSS_DW_ECC_PRESENT 0u -/* DataWire SRAMs address ECC present or not ('0': no, '1': yes) */ -#define CPUSS_DW_ECC_ADDR_PRESENT 0u -/* System ROM size in KB */ -#define CPUSS_ROM_SIZE 64u -/* Number of macros used to implement system ROM. Example: 4 if 512 KB system ROM - is implemented with 4 128KB macros. */ -#define CPUSS_ROMC_MACRO_NR 1u -/* Flash memory type ('0' : SONOS, '1': ECT) */ -#define CPUSS_FLASHC_ECT 0u -/* Flash main region size in KB */ -#define CPUSS_FLASH_SIZE 2048u -/* Flash work region size in KB (EEPROM emulation, data) */ -#define CPUSS_WFLASH_SIZE 32u -/* Flash supervisory region size in KB */ -#define CPUSS_SFLASH_SIZE 32u -/* Flash data output word size (in Bytes) */ -#define CPUSS_FLASHC_MAIN_DATA_WIDTH 16u -/* SONOS Flash RWW present or not ('0': no, '1': yes) When RWW is '0', No special - sectors present in Flash. Part of main sector 0 is allowcated for Supervisory - Flash, and no Work Flash present. */ -#define CPUSS_FLASHC_SONOS_RWW 1u -/* SONOS Flash, number of main sectors. */ -#define CPUSS_FLASHC_SONOS_MAIN_SECTORS 8u -/* SONOS Flash, number of rows per main sector. */ -#define CPUSS_FLASHC_SONOS_MAIN_ROWS 512u -/* SONOS Flash, number of words per row of main sector. */ -#define CPUSS_FLASHC_SONOS_MAIN_WORDS 128u -/* SONOS Flash, number of special sectors. */ -#define CPUSS_FLASHC_SONOS_SPL_SECTORS 2u -/* SONOS Flash, number of rows per special sector. */ -#define CPUSS_FLASHC_SONOS_SPL_ROWS 64u -/* Flash memory ECC present or not ('0': no, '1': yes) */ -#define CPUSS_FLASHC_FLASH_ECC_PRESENT 0u -/* Flash cache SRAM(s) ECC present or not ('0': no, '1': yes) */ -#define CPUSS_FLASHC_RAM_ECC_PRESENT 0u -/* Number of external slaves directly connected to slow AHB-Lite infrastructure. - Maximum nubmer of slave supported is 4. Width of this parameter is 4-bits. - 1-bit mask for each slave indicating present or not. Example: 4'b0011 - slave - 0 and slave 1 are present. Note: The SLOW_SLx_ADDR and SLOW_SLx_MASK - parameters (for the slaves present) should be derived from the Memory Map. */ -#define CPUSS_SLOW_SL_PRESENT 1u -/* Number of external slaves directly connected to fast AHB-Lite infrastructure. - Maximum nubmer of slave supported is 4. Width of this parameter is 4-bits. - 1-bit mask for each slave indicating present or not. Example: 4'b0011 - slave - 0 and slave 1 are present. Note: The FAST_SLx_ADDR and FAST_SLx_MASK - parameters (for the slaves present) should be derived from the Memory Map. */ -#define CPUSS_FAST_SL_PRESENT 1u -/* Number of external masters driving the slow AHB-Lite infrastructure. Maximum - number of masters supported is 2. Width of this parameter is 2-bits. 1-bit - mask for each master indicating present or not. Example: 2'b01 - master 0 is - present. */ -#define CPUSS_SLOW_MS_PRESENT 3u -/* System interrupt functionality present or not ('0': no; '1': yes). Not used for - CM0+ PCU, which always uses system interrupt functionality. */ -#define CPUSS_SYSTEM_IRQ_PRESENT 0u -/* Number of total interrupt request inputs to CPUSS */ -#define CPUSS_SYSTEM_INT_NR 168u -/* Number of DeepSleep wakeup interrupt inputs to CPUSS */ -#define CPUSS_SYSTEM_DPSLP_INT_NR 39u -/* Width of the CM4 interrupt priority bits. Legal range [3,8] Example: 3 = 8 - levels of priority 8 = 256 levels of priority */ -#define CPUSS_CM4_LVL_WIDTH 3u -/* CM4 Floating point unit present or not (0=No, 1=Yes) */ -#define CPUSS_CM4_FPU_PRESENT 1u -/* Debug level. Legal range [0,3] (0= No support, 1= Minimum: CM0/4 both 2 - breakpoints +1 watchpoint, 2= Full debug: CM0/4 have 4/6 breakpoints, 2/4 - watchpoints and 0/2 literal compare, 3= Full debug + data matching) */ -#define CPUSS_DEBUG_LVL 3u -/* Trace level. Legal range [0,2] (0= No tracing, 1= ITM + TPIU + SWO, 2= ITM + - ETM + TPIU + SWO) Note: CM4 HTM is not supported. Hence vaule 3 for trace - level is not supported in CPUSS. */ -#define CPUSS_TRACE_LVL 2u -/* Embedded Trace Buffer present or not (0=No, 1=Yes) */ -#define CPUSS_ETB_PRESENT 0u -/* CM0+ MTB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */ -#define CPUSS_MTB_SRAM_SIZE 4u -/* CM4 ETB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */ -#define CPUSS_ETB_SRAM_SIZE 8u -/* PTM interface present (0=No, 1=Yes) */ -#define CPUSS_PTM_PRESENT 0u -/* Width of the PTM interface in bits ([2,32]) */ -#define CPUSS_PTM_WIDTH 1u -/* Width of the TPIU interface in bits ([1,4]) */ -#define CPUSS_TPIU_WIDTH 4u -/* CoreSight Part Identification Number */ -#define CPUSS_JEPID 52u -/* CoreSight Part Identification Number */ -#define CPUSS_JEPCONTINUATION 0u -/* CoreSight Part Identification Number */ -#define CPUSS_FAMILYID 258u -/* ROM trim register width (for ARM 3, for Synopsys 5) */ -#define CPUSS_ROM_TRIM_WIDTH 5u -/* ROM trim register default (for both ARM and Synopsys 0x0000_0012) */ -#define CPUSS_ROM_TRIM_DEFAULT 18u -/* RAM trim register width (for ARM 8, for Synopsys 15) */ -#define CPUSS_RAM_TRIM_WIDTH 15u -/* RAM trim register default (for ARM 0x0000_0062 and for Synopsys 0x0000_6012) */ -#define CPUSS_RAM_TRIM_DEFAULT 24594u -/* Cryptography IP present or not (0=No, 1=Yes) */ -#define CPUSS_CRYPTO_PRESENT 1u -/* DataWire and DMAC SW trigger per channel present or not ('0': no, '1': yes) */ -#define CPUSS_SW_TR_PRESENT 0u -/* DataWire 0 present or not (0=No, 1=Yes) */ -#define CPUSS_DW0_PRESENT 1u -/* Number of DataWire 0 channels (8, 16 or 32) */ -#define CPUSS_DW0_CH_NR 29u -/* DataWire 1 present or not (0=No, 1=Yes) */ -#define CPUSS_DW1_PRESENT 1u -/* Number of DataWire 1 channels (8, 16 or 32) */ -#define CPUSS_DW1_CH_NR 29u -/* DMA controller present or not ('0': no, '1': yes) */ -#define CPUSS_DMAC_PRESENT 1u -/* Number of DMA controller channels ([1, 8]) */ -#define CPUSS_DMAC_CH_NR 4u -/* Number of Flash BIST_DATA registers */ -#define CPUSS_FLASHC_FLASHC_BIST_DATA_NR 4u -/* Page size in # of 32-bit words (1: 4 bytes, 2: 8 bytes, ... */ -#define CPUSS_FLASHC_PA_SIZE 128u -/* SONOS Flash is used or not ('0': no, '1': yes) */ -#define CPUSS_FLASHC_FLASHC_IS_SONOS 1u -/* eCT Flash is used or not ('0': no, '1': yes) */ -#define CPUSS_FLASHC_FLASHC_IS_ECT 0u -/* Cryptography SRAMs ECC present or not ('0': no, '1': yes) */ -#define CPUSS_CRYPTO_ECC_PRESENT 0u -/* Cryptography SRAMs address ECC present or not ('0': no, '1': yes) */ -#define CPUSS_CRYPTO_ECC_ADDR_PRESENT 0u -/* AES cipher support ('0': no, '1': yes) */ -#define CPUSS_CRYPTO_AES 1u -/* (Tripple) DES cipher support ('0': no, '1': yes) */ -#define CPUSS_CRYPTO_DES 1u -/* Chacha support ('0': no, '1': yes) */ -#define CPUSS_CRYPTO_CHACHA 1u -/* Pseudo random number generation support ('0': no, '1': yes) */ -#define CPUSS_CRYPTO_PR 1u -/* SHA1 hash support ('0': no, '1': yes) */ -#define CPUSS_CRYPTO_SHA1 1u -/* SHA2 hash support ('0': no, '1': yes) */ -#define CPUSS_CRYPTO_SHA2 1u -/* SHA3 hash support ('0': no, '1': yes) */ -#define CPUSS_CRYPTO_SHA3 1u -/* Cyclic Redundancy Check support ('0': no, '1': yes) */ -#define CPUSS_CRYPTO_CRC 1u -/* True random number generation support ('0': no, '1': yes) */ -#define CPUSS_CRYPTO_TR 1u -/* Vector unit support ('0': no, '1': yes) */ -#define CPUSS_CRYPTO_VU 1u -/* Galios/Counter Mode (GCM) support ('0': no, '1': yes) */ -#define CPUSS_CRYPTO_GCM 1u -/* Number of 32-bit words in the IP internal memory buffer (from the set [64, 128, - 256, 512, 1024, 2048, 4096], to allow for a 256 B, 512 B, 1 kB, 2 kB, 4 kB, 8 - kB and 16 kB memory buffer) */ -#define CPUSS_CRYPTO_BUFF_SIZE 1024u -/* Number of fault structures. Legal range [1, 4] */ -#define CPUSS_FAULT_FAULT_NR 2u -/* Number of IPC structures. Legal range [1, 16] */ -#define CPUSS_IPC_IPC_NR 16u -/* Number of IPC interrupt structures. Legal range [1, 16] */ -#define CPUSS_IPC_IPC_IRQ_NR 16u -/* Master 0 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS0_PC_NR_MINUS1 7u -/* Master 1 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS1_PC_NR_MINUS1 0u -/* Master 2 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS2_PC_NR_MINUS1 0u -/* Master 3 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS3_PC_NR_MINUS1 0u -/* Master 4 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS4_PC_NR_MINUS1 0u -/* Master 5 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS5_PC_NR_MINUS1 7u -/* Master 6 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS6_PC_NR_MINUS1 7u -/* Master 7 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS7_PC_NR_MINUS1 0u -/* Master 8 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS8_PC_NR_MINUS1 0u -/* Master 9 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS9_PC_NR_MINUS1 0u -/* Master 10 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS10_PC_NR_MINUS1 0u -/* Master 11 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS11_PC_NR_MINUS1 0u -/* Master 12 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS12_PC_NR_MINUS1 0u -/* Master 13 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS13_PC_NR_MINUS1 0u -/* Master 14 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS14_PC_NR_MINUS1 7u -/* Master 15 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS15_PC_NR_MINUS1 7u -/* Number of SMPU protection structures */ -#define CPUSS_PROT_SMPU_STRUCT_NR 16u -/* Number of protection contexts supported minus 1. Legal range [1,16] */ -#define CPUSS_SMPU_STRUCT_PC_NR_MINUS1 7u -/* Number of DataWire controllers present (max 2) */ -#define CPUSS_DW_NR 2u -/* DataWire SRAMs ECC present or not ('0': no, '1': yes) */ -#define CPUSS_DW_ECC_PRESENT 0u -/* DataWire SW trigger per channel present or not ('0': no, '1': yes) */ -#define CPUSS_CH_STRUCT_SW_TR_PRESENT 0u -/* Number of DataWire controllers present (max 2) (same as DW.NR above) */ -#define CPUSS_CPUSS_DW_DW_NR 2u -/* Number of channels in each DataWire controller */ -#define CPUSS_CPUSS_DW_DW_NR0_DW_CH_NR 29u -/* Width of a channel number in bits */ -#define CPUSS_CPUSS_DW_DW_NR0_DW_CH_NR_WIDTH 5u -/* Number of channels in each DataWire controller */ -#define CPUSS_CPUSS_DW_DW_NR1_DW_CH_NR 29u -/* Width of a channel number in bits */ -#define CPUSS_CPUSS_DW_DW_NR1_DW_CH_NR_WIDTH 5u -/* Number of DMA controller channels ([1, 8]) */ -#define CPUSS_DMAC_CH_NR 4u -/* DMAC SW trigger per channel present or not ('0': no, '1': yes) */ -#define CPUSS_CH_SW_TR_PRESENT 0u -/* See MMIO2 instantiation or not */ -#define CPUSS_CHIP_TOP_PROFILER_PRESENT 1u -/* ETAS Calibration support pin out present (automotive only) */ -#define CPUSS_CHIP_TOP_CAL_SUP_NZ_PRESENT 0u -/* TRACE_LVL>0 */ -#define CPUSS_CHIP_TOP_TRACE_PRESENT 1u /* Number of profiling counters. Legal range [1, 32] */ #define PROFILE_PRFL_CNT_NR 8u /* Number of monitor event signals. Legal range [1, 128] */ #define PROFILE_PRFL_MONITOR_NR 128u -/* Number of instantiated eFUSE macros (256 bit macros). Legal range [1, 16] */ -#define EFUSE_EFUSE_NR 4u -/* SONOS Flash is used or not ('0': no, '1': yes) */ -#define SFLASH_FLASHC_IS_SONOS 1u -/* CPUSS_WOUNDING_PRESENT or not ('0': no, '1': yes) */ -#define SFLASH_CPUSS_WOUNDING_PRESENT 0u /* DeepSleep support ('0':no, '1': yes) */ #define SCB0_DEEPSLEEP 0u /* Externally clocked support? ('0': no, '1': yes) */ @@ -3138,7 +3116,7 @@ typedef I2S_V1_Type I2S_Type; /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ #define SCB1_I2C_FAST_PLUS 1u /* Number of used spi_select signals (max 4) */ -#define SCB1_CHIP_TOP_SPI_SEL_NR 3u +#define SCB1_CHIP_TOP_SPI_SEL_NR 4u /* DeepSleep support ('0':no, '1': yes) */ #define SCB2_DEEPSLEEP 0u /* Externally clocked support? ('0': no, '1': yes) */ @@ -3188,7 +3166,7 @@ typedef I2S_V1_Type I2S_Type; /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ #define SCB2_I2C_FAST_PLUS 1u /* Number of used spi_select signals (max 4) */ -#define SCB2_CHIP_TOP_SPI_SEL_NR 3u +#define SCB2_CHIP_TOP_SPI_SEL_NR 4u /* DeepSleep support ('0':no, '1': yes) */ #define SCB3_DEEPSLEEP 0u /* Externally clocked support? ('0': no, '1': yes) */ @@ -3238,7 +3216,7 @@ typedef I2S_V1_Type I2S_Type; /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ #define SCB3_I2C_FAST_PLUS 1u /* Number of used spi_select signals (max 4) */ -#define SCB3_CHIP_TOP_SPI_SEL_NR 3u +#define SCB3_CHIP_TOP_SPI_SEL_NR 4u /* DeepSleep support ('0':no, '1': yes) */ #define SCB4_DEEPSLEEP 0u /* Externally clocked support? ('0': no, '1': yes) */ @@ -3288,7 +3266,7 @@ typedef I2S_V1_Type I2S_Type; /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ #define SCB4_I2C_FAST_PLUS 1u /* Number of used spi_select signals (max 4) */ -#define SCB4_CHIP_TOP_SPI_SEL_NR 3u +#define SCB4_CHIP_TOP_SPI_SEL_NR 4u /* DeepSleep support ('0':no, '1': yes) */ #define SCB5_DEEPSLEEP 0u /* Externally clocked support? ('0': no, '1': yes) */ @@ -3338,7 +3316,7 @@ typedef I2S_V1_Type I2S_Type; /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ #define SCB5_I2C_FAST_PLUS 1u /* Number of used spi_select signals (max 4) */ -#define SCB5_CHIP_TOP_SPI_SEL_NR 3u +#define SCB5_CHIP_TOP_SPI_SEL_NR 4u /* DeepSleep support ('0':no, '1': yes) */ #define SCB6_DEEPSLEEP 0u /* Externally clocked support? ('0': no, '1': yes) */ @@ -3388,7 +3366,7 @@ typedef I2S_V1_Type I2S_Type; /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ #define SCB6_I2C_FAST_PLUS 1u /* Number of used spi_select signals (max 4) */ -#define SCB6_CHIP_TOP_SPI_SEL_NR 3u +#define SCB6_CHIP_TOP_SPI_SEL_NR 4u /* DeepSleep support ('0':no, '1': yes) */ #define SCB7_DEEPSLEEP 0u /* Externally clocked support? ('0': no, '1': yes) */ @@ -3689,55 +3667,92 @@ typedef I2S_V1_Type I2S_Type; #define SCB12_I2C_FAST_PLUS 1u /* Number of used spi_select signals (max 4) */ #define SCB12_CHIP_TOP_SPI_SEL_NR 0u -/* Number of counters per IP (1..32) */ -#define TCPWM0_CNT_NR 8u -/* Counter width (in number of bits) */ -#define TCPWM0_CNT_CNT_WIDTH 32u -/* Number of counters per IP (1..32) */ -#define TCPWM1_CNT_NR 24u -/* Counter width (in number of bits) */ -#define TCPWM1_CNT_CNT_WIDTH 16u -/* Number of ports supoprting up to 4 COMs */ -#define LCD_NUMPORTS 8u -/* Number of ports supporting up to 8 COMs */ -#define LCD_NUMPORTS8 8u -/* Number of ports supporting up to 16 COMs */ -#define LCD_NUMPORTS16 0u -/* Max number of LCD commons supported */ -#define LCD_CHIP_TOP_COM_NR 8u -/* Max number of LCD pins (total) supported */ -#define LCD_CHIP_TOP_PIN_NR 62u -/* Number of IREF outputs from AREF */ -#define PASS_NR_IREFS 4u -/* Number of CTBs in the Subsystem */ -#define PASS_NR_CTBS 0u -/* Number of CTDACs in the Subsystem */ -#define PASS_NR_CTDACS 0u -/* CTB0 Exists */ -#define PASS_CTB0_EXISTS 0u -/* CTB1 Exists */ -#define PASS_CTB1_EXISTS 0u -/* CTB2 Exists */ -#define PASS_CTB2_EXISTS 0u -/* CTB3 Exists */ -#define PASS_CTB3_EXISTS 0u -/* CTDAC0 Exists */ -#define PASS_CTDAC0_EXISTS 0u -/* CTDAC1 Exists */ -#define PASS_CTDAC1_EXISTS 0u -/* CTDAC2 Exists */ -#define PASS_CTDAC2_EXISTS 0u -/* CTDAC3 Exists */ -#define PASS_CTDAC3_EXISTS 0u -/* Number of SAR channels */ -#define PASS_SAR_SAR_CHANNELS 16u -/* Averaging logic present in SAR */ -#define PASS_SAR_SAR_AVERAGE 1u -/* Range detect logic present in SAR */ -#define PASS_SAR_SAR_RANGEDET 1u -/* Support for UAB sampling */ -#define PASS_SAR_SAR_UAB 0u -#define PASS_CTBM_CTDAC_PRESENT 0u +/* Basically the max packet size, which gets double buffered in RAM 0: 512B + (implies 1KB of RAM space for data) 1: 1KB (implies 2KB of RAM space for + data) */ +#define SDHC0_MAX_BLK_SIZE 0u +/* 0: No Command Queuing Engine present 1: Command Queuing Engine present; this + adds 288 bytes of space to the RAM for this purpose. */ +#define SDHC0_CQE_PRESENT 0u +/* 0: no retention of any SDHC_CORE regs 1: retention of SDHC_CORE regs that have + the Retention flag (Note, CTL.ENABLE is always retained irrespective of this + parameter) */ +#define SDHC0_RETENTION_PRESENT 1u +/* Chip top connect all 8 data pins (0= connect 4 data pins, 1= connect 8 data + pins) */ +#define SDHC0_CHIP_TOP_DATA8_PRESENT 0u +/* Chip top connect card_detect */ +#define SDHC0_CHIP_TOP_CARD_DETECT_PRESENT 1u +/* Chip top connect card_mech_write_prot_in */ +#define SDHC0_CHIP_TOP_CARD_WRITE_PROT_PRESENT 1u +/* Chip top connect led_ctrl_out and led_ctrl_out_en */ +#define SDHC0_CHIP_TOP_LED_CTRL_PRESENT 0u +/* Chip top connect io_volt_sel_out and io_volt_sel_out_en */ +#define SDHC0_CHIP_TOP_IO_VOLT_SEL_PRESENT 1u +/* Chip top connect io_drive_strength_out and io_drive_strength_out_en */ +#define SDHC0_CHIP_TOP_IO_DRIVE_STRENGTH_PRESENT 0u +/* Chip top connect card_if_pwr_en_out and card_if_pwr_en_out_en */ +#define SDHC0_CHIP_TOP_CARD_IF_PWR_EN_PRESENT 1u +/* Chip top connect card_emmc_reset_n_out and card_emmc_reset_n_out_en */ +#define SDHC0_CHIP_TOP_CARD_EMMC_RESET_PRESENT 0u +/* Chip top connect interrupt_wakeup (not used for eMMC) */ +#define SDHC0_CHIP_TOP_INTERRUPT_WAKEUP_PRESENT 1u +/* Basically the max packet size, which gets double buffered in RAM 0: 512B + (implies 1KB of RAM space for data) 1: 1KB (implies 2KB of RAM space for + data) */ +#define SDHC0_CORE_MAX_BLK_SIZE 0u +/* 0: No Command Queuing Engine present 1: Command Queuing Engine present; this + adds 288 bytes of space to the RAM for this purpose. */ +#define SDHC0_CORE_CQE_PRESENT 0u +/* 0: no retention of any SDHC_CORE regs 1: retention of SDHC_CORE regs that have + the Retention flag (Note, CTL.ENABLE is always retained irrespective of this + parameter) */ +#define SDHC0_CORE_RETENTION_PRESENT 1u +/* Basically the max packet size, which gets double buffered in RAM 0: 512B + (implies 1KB of RAM space for data) 1: 1KB (implies 2KB of RAM space for + data) */ +#define SDHC1_MAX_BLK_SIZE 0u +/* 0: No Command Queuing Engine present 1: Command Queuing Engine present; this + adds 288 bytes of space to the RAM for this purpose. */ +#define SDHC1_CQE_PRESENT 0u +/* 0: no retention of any SDHC_CORE regs 1: retention of SDHC_CORE regs that have + the Retention flag (Note, CTL.ENABLE is always retained irrespective of this + parameter) */ +#define SDHC1_RETENTION_PRESENT 1u +/* Chip top connect all 8 data pins (0= connect 4 data pins, 1= connect 8 data + pins) */ +#define SDHC1_CHIP_TOP_DATA8_PRESENT 1u +/* Chip top connect card_detect */ +#define SDHC1_CHIP_TOP_CARD_DETECT_PRESENT 1u +/* Chip top connect card_mech_write_prot_in */ +#define SDHC1_CHIP_TOP_CARD_WRITE_PROT_PRESENT 1u +/* Chip top connect led_ctrl_out and led_ctrl_out_en */ +#define SDHC1_CHIP_TOP_LED_CTRL_PRESENT 1u +/* Chip top connect io_volt_sel_out and io_volt_sel_out_en */ +#define SDHC1_CHIP_TOP_IO_VOLT_SEL_PRESENT 1u +/* Chip top connect io_drive_strength_out and io_drive_strength_out_en */ +#define SDHC1_CHIP_TOP_IO_DRIVE_STRENGTH_PRESENT 0u +/* Chip top connect card_if_pwr_en_out and card_if_pwr_en_out_en */ +#define SDHC1_CHIP_TOP_CARD_IF_PWR_EN_PRESENT 1u +/* Chip top connect card_emmc_reset_n_out and card_emmc_reset_n_out_en */ +#define SDHC1_CHIP_TOP_CARD_EMMC_RESET_PRESENT 1u +/* Chip top connect interrupt_wakeup (not used for eMMC) */ +#define SDHC1_CHIP_TOP_INTERRUPT_WAKEUP_PRESENT 1u +/* Basically the max packet size, which gets double buffered in RAM 0: 512B + (implies 1KB of RAM space for data) 1: 1KB (implies 2KB of RAM space for + data) */ +#define SDHC1_CORE_MAX_BLK_SIZE 0u +/* 0: No Command Queuing Engine present 1: Command Queuing Engine present; this + adds 288 bytes of space to the RAM for this purpose. */ +#define SDHC1_CORE_CQE_PRESENT 0u +/* 0: no retention of any SDHC_CORE regs 1: retention of SDHC_CORE regs that have + the Retention flag (Note, CTL.ENABLE is always retained irrespective of this + parameter) */ +#define SDHC1_CORE_RETENTION_PRESENT 1u +/* SONOS Flash is used or not ('0': no, '1': yes) */ +#define SFLASH_FLASHC_IS_SONOS 1u +/* CPUSS_WOUNDING_PRESENT or not ('0': no, '1': yes) */ +#define SFLASH_CPUSS_WOUNDING_PRESENT 0u /* Base address of the SMIF XIP memory region. This address must be a multiple of the SMIF XIP memory capacity. This address must be a multiple of 64 KB. This address must be in the [0x0000:0000, 0x1fff:ffff] memory region. The XIP @@ -3763,96 +3778,81 @@ typedef I2S_V1_Type I2S_Type; #define SMIF_CHIP_TOP_DATA8_PRESENT 1u /* Number of used spi_select signals (max 4) */ #define SMIF_CHIP_TOP_SPI_SEL_NR 4u -/* I2S capable? (0=No,1=Yes) */ -#define AUDIOSS0_I2S 1u -/* PDM capable? (0=No,1=Yes) */ -#define AUDIOSS0_PDM 1u -/* I2S capable? (0=No,1=Yes) */ -#define AUDIOSS1_I2S 1u -/* PDM capable? (0=No,1=Yes) */ -#define AUDIOSS1_PDM 0u -/* Basically the max packet size, which gets double buffered in RAM 0: 512B - (implies 1KB of RAM space for data) 1: 1KB (implies 2KB of RAM space for - data) */ -#define SDHC0_MAX_BLK_SIZE 0u -/* 0: No Command Queuing Engine present 1: Command Queuing Engine present; this - adds 288 bytes of space to the RAM for this purpose. */ -#define SDHC0_CQE_PRESENT 0u -/* 0: no retention of any SDHC_CORE regs 1: retention of SDHC_CORE regs that have - the Retention flag (Note, CTL.ENABLE is always retained irrespective of this - parameter) */ -#define SDHC0_RETENTION_PRESENT 1u -/* Basically the max packet size, which gets double buffered in RAM 0: 512B - (implies 1KB of RAM space for data) 1: 1KB (implies 2KB of RAM space for - data) */ -#define SDHC0_CORE_MAX_BLK_SIZE 0u -/* 0: No Command Queuing Engine present 1: Command Queuing Engine present; this - adds 288 bytes of space to the RAM for this purpose. */ -#define SDHC0_CORE_CQE_PRESENT 0u -/* 0: no retention of any SDHC_CORE regs 1: retention of SDHC_CORE regs that have - the Retention flag (Note, CTL.ENABLE is always retained irrespective of this - parameter) */ -#define SDHC0_CORE_RETENTION_PRESENT 1u -/* Chip top connect all 8 data pins (0= connect 4 data pins, 1= connect 8 data - pins) */ -#define SDHC0_CHIP_TOP_DATA8_PRESENT 0u -/* Chip top connect card_detect */ -#define SDHC0_CHIP_TOP_CARD_DETECT_PRESENT 1u -/* Chip top connect card_mech_write_prot_in */ -#define SDHC0_CHIP_TOP_CARD_WRITE_PROT_PRESENT 1u -/* Chip top connect led_ctrl_out and led_ctrl_out_en */ -#define SDHC0_CHIP_TOP_LED_CTRL_PRESENT 0u -/* Chip top connect io_volt_sel_out and io_volt_sel_out_en */ -#define SDHC0_CHIP_TOP_IO_VOLT_SEL_PRESENT 1u -/* Chip top connect io_drive_strength_out and io_drive_strength_out_en */ -#define SDHC0_CHIP_TOP_IO_DRIVE_STRENGTH_PRESENT 0u -/* Chip top connect card_if_pwr_en_out and card_if_pwr_en_out_en */ -#define SDHC0_CHIP_TOP_CARD_IF_PWR_EN_PRESENT 1u -/* Chip top connect card_emmc_reset_n_out and card_emmc_reset_n_out_en */ -#define SDHC0_CHIP_TOP_CARD_EMMC_RESET_PRESENT 0u -/* Chip top connect interrupt_wakeup (not used for eMMC) */ -#define SDHC0_CHIP_TOP_INTERRUPT_WAKEUP_PRESENT 1u -/* Basically the max packet size, which gets double buffered in RAM 0: 512B - (implies 1KB of RAM space for data) 1: 1KB (implies 2KB of RAM space for - data) */ -#define SDHC1_MAX_BLK_SIZE 0u -/* 0: No Command Queuing Engine present 1: Command Queuing Engine present; this - adds 288 bytes of space to the RAM for this purpose. */ -#define SDHC1_CQE_PRESENT 0u -/* 0: no retention of any SDHC_CORE regs 1: retention of SDHC_CORE regs that have - the Retention flag (Note, CTL.ENABLE is always retained irrespective of this - parameter) */ -#define SDHC1_RETENTION_PRESENT 1u -/* Basically the max packet size, which gets double buffered in RAM 0: 512B - (implies 1KB of RAM space for data) 1: 1KB (implies 2KB of RAM space for - data) */ -#define SDHC1_CORE_MAX_BLK_SIZE 0u -/* 0: No Command Queuing Engine present 1: Command Queuing Engine present; this - adds 288 bytes of space to the RAM for this purpose. */ -#define SDHC1_CORE_CQE_PRESENT 0u -/* 0: no retention of any SDHC_CORE regs 1: retention of SDHC_CORE regs that have - the Retention flag (Note, CTL.ENABLE is always retained irrespective of this - parameter) */ -#define SDHC1_CORE_RETENTION_PRESENT 1u -/* Chip top connect all 8 data pins (0= connect 4 data pins, 1= connect 8 data - pins) */ -#define SDHC1_CHIP_TOP_DATA8_PRESENT 1u -/* Chip top connect card_detect */ -#define SDHC1_CHIP_TOP_CARD_DETECT_PRESENT 1u -/* Chip top connect card_mech_write_prot_in */ -#define SDHC1_CHIP_TOP_CARD_WRITE_PROT_PRESENT 1u -/* Chip top connect led_ctrl_out and led_ctrl_out_en */ -#define SDHC1_CHIP_TOP_LED_CTRL_PRESENT 1u -/* Chip top connect io_volt_sel_out and io_volt_sel_out_en */ -#define SDHC1_CHIP_TOP_IO_VOLT_SEL_PRESENT 1u -/* Chip top connect io_drive_strength_out and io_drive_strength_out_en */ -#define SDHC1_CHIP_TOP_IO_DRIVE_STRENGTH_PRESENT 0u -/* Chip top connect card_if_pwr_en_out and card_if_pwr_en_out_en */ -#define SDHC1_CHIP_TOP_CARD_IF_PWR_EN_PRESENT 1u -/* Chip top connect card_emmc_reset_n_out and card_emmc_reset_n_out_en */ -#define SDHC1_CHIP_TOP_CARD_EMMC_RESET_PRESENT 1u -/* Chip top connect interrupt_wakeup (not used for eMMC) */ -#define SDHC1_CHIP_TOP_INTERRUPT_WAKEUP_PRESENT 1u +/* Number of regulator modules instantiated within SRSS, start with estimate, + update after CMR feedback */ +#define SRSS_NUM_ACTREG_PWRMOD 2u +/* Number of shorting switches between vccd and vccact (target dynamic voltage + drop < 10mV) */ +#define SRSS_NUM_ACTIVE_SWITCH 3u +/* ULP linear regulator system is present */ +#define SRSS_ULPLINREG_PRESENT 1u +/* HT linear regulator system is present */ +#define SRSS_HTLINREG_PRESENT 0u +/* Low-current buck regulator present. Can be derived from S40S_SISOBUCKLC_PRESENT + or SIMOBUCK_PRESENT. */ +#define SRSS_BUCKCTL_PRESENT 1u +/* Low-current SISO buck core regulator is present. Only compatible with ULP + linear regulator system (ULPLINREG_PRESENT==1). */ +#define SRSS_S40S_SISOBUCKLC_PRESENT 1u +/* SIMO buck core regulator is present. Only compatible with ULP linear regulator + system (ULPLINREG_PRESENT==1). */ +#define SRSS_SIMOBUCK_PRESENT 0u +/* Precision ILO (PILO) is present */ +#define SRSS_PILO_PRESENT 0u +/* External Crystal Oscillator is present (high frequency) */ +#define SRSS_ECO_PRESENT 1u +/* System Buck-Boost is present */ +#define SRSS_SYSBB_PRESENT 0u +/* Number of clock paths. Must be > 0 */ +#define SRSS_NUM_CLKPATH 6u +/* Number of PLLs present. Must be <= NUM_CLKPATH */ +#define SRSS_NUM_PLL 2u +/* Number of HFCLK roots present. Must be > 0 */ +#define SRSS_NUM_HFROOT 6u +/* Number of PWR_HIB_DATA registers, should not be needed if BACKUP_PRESENT */ +#define SRSS_NUM_HIBDATA 1u +/* Backup domain is present (includes RTC and WCO) */ +#define SRSS_BACKUP_PRESENT 1u +/* Mask of HFCLK root clock supervisors (CSV). For each clock root i, bit[i] of + mask indicates presence of a CSV. */ +#define SRSS_MASK_HFCSV 0u +/* Clock supervisor is present on WCO. Must be 0 if BACKUP_PRESENT==0. */ +#define SRSS_WCOCSV_PRESENT 0u +/* Number of software watchdog timers. */ +#define SRSS_NUM_MCWDT 2u +/* Number of DSI inputs into clock muxes. This is used for logic optimization. */ +#define SRSS_NUM_DSI 0u +/* Alternate high-frequency clock is present. This is used for logic optimization. */ +#define SRSS_ALTHF_PRESENT 0u +/* Alternate low-frequency clock is present. This is used for logic optimization. */ +#define SRSS_ALTLF_PRESENT 0u +/* Use the hardened clkactfllmux block */ +#define SRSS_USE_HARD_CLKACTFLLMUX 1u +/* Number of clock paths, including direct paths in hardened clkactfllmux block + (Must be >= NUM_CLKPATH) */ +#define SRSS_HARD_CLKPATH 6u +/* Number of clock paths with muxes in hardened clkactfllmux block (Must be >= + NUM_PLL+1) */ +#define SRSS_HARD_CLKPATHMUX 6u +/* Number of HFCLKS present in hardened clkactfllmux block (Must be >= NUM_HFROOT) */ +#define SRSS_HARD_HFROOT 6u +/* ECO mux is present in hardened clkactfllmux block (Must be >= ECO_PRESENT) */ +#define SRSS_HARD_ECOMUX_PRESENT 1u +/* ALTHF mux is present in hardened clkactfllmux block (Must be >= ALTHF_PRESENT) */ +#define SRSS_HARD_ALTHFMUX_PRESENT 1u +/* Backup memory is present (only used when BACKUP_PRESENT==1) */ +#define SRSS_BACKUP_BMEM_PRESENT 0u +/* Number of Backup registers to include (each is 32b). Only used when + BACKUP_PRESENT==1. */ +#define SRSS_BACKUP_NUM_BREG 16u +/* Number of counters per IP (1..32) */ +#define TCPWM0_CNT_NR 8u +/* Counter width (in number of bits) */ +#define TCPWM0_CNT_CNT_WIDTH 32u +/* Number of counters per IP (1..32) */ +#define TCPWM1_CNT_NR 24u +/* Counter width (in number of bits) */ +#define TCPWM1_CNT_CNT_WIDTH 16u /* MMIO Targets Defines */ #define CY_MMIO_CRYPTO_GROUP_NR 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/psoc6_03_config.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/psoc6_03_config.h index 2d00cd97ce..31cc4ea980 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/psoc6_03_config.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/psoc6_03_config.h @@ -5,7 +5,7 @@ * PSoC6_03 device configuration header * * \note -* Generator version: 1.6.0.111 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -1058,12 +1058,6 @@ typedef enum TRIG_OUT_1TO1_4_CAN_FIFO1_TO_PDMA1_TR_IN31 = 0x40001402u /* From canfd[0].tr_fifo1[0] to cpuss.dw1_tr_in[31] */ } en_trig_output_1to1_can_dw_tr_t; -/* Trigger Output Group 7 - Acknowledge dma request triggers from DW0 to CAN (OneToOne) */ -typedef enum -{ - TRIG_OUT_1TO1_7_PDMA1_TR_OUT29_ACK_TO_CAN_0 = 0x40001700u /* From cpuss.dw1_tr_out[29] to canfd[0].tr_dbg_dma_ack[0] */ -} en_trig_output_1to1_can0_dw_ack_t; - /* Trigger Output Group 5 - USB PDMA0 Triggers (OneToOne) */ typedef enum { @@ -1090,6 +1084,12 @@ typedef enum TRIG_OUT_1TO1_6_PDMA0_TR_OUT15_TO_USB_ACK7 = 0x40001607u /* From cpuss.dw0_tr_out[15] to usb.dma_burstend[7] */ } en_trig_output_1to1_usb_pdma0_ack_tr_t; +/* Trigger Output Group 7 - Acknowledge dma request triggers from DW0 to CAN (OneToOne) */ +typedef enum +{ + TRIG_OUT_1TO1_7_PDMA1_TR_OUT29_ACK_TO_CAN_0 = 0x40001700u /* From cpuss.dw1_tr_out[29] to canfd[0].tr_dbg_dma_ack[0] */ +} en_trig_output_1to1_can0_dw_ack_t; + /* Level or edge detection setting for a trigger mux */ typedef enum { @@ -1101,59 +1101,59 @@ typedef enum } en_trig_type_t; /* Trigger Type Defines */ -/* TCPWM Trigger Types */ -#define TRIGGER_TYPE_TCPWM_LINE TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_TCPWM_LINE_COMPL TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_TCPWM_TR_OVERFLOW TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_TCPWM_TR_COMPARE_MATCH TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_TCPWM_TR_UNDERFLOW TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_TCPWM_TR_IN__LEVEL TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_TCPWM_TR_IN__EDGE TRIGGER_TYPE_EDGE +/* CANFD Trigger Types */ +#define TRIGGER_TYPE_CANFD_TR_DBG_DMA_ACK TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CANFD_TR_DBG_DMA_REQ TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_CANFD_TR_EVT_SWT_IN TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CANFD_TR_FIFO0 TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_CANFD_TR_FIFO1 TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_CANFD_TR_TMP_RTP_OUT TRIGGER_TYPE_EDGE +/* CPUSS Trigger Types */ +#define TRIGGER_TYPE_CPUSS_CTI_TR_IN TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_CTI_TR_OUT TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_DMAC_TR_IN__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_CPUSS_DMAC_TR_IN__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_DMAC_TR_OUT TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_DW0_TR_IN__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_CPUSS_DW0_TR_IN__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_DW0_TR_OUT TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_DW1_TR_IN__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_CPUSS_DW1_TR_IN__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_DW1_TR_OUT TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_TR_FAULT TRIGGER_TYPE_EDGE /* CSD Trigger Types */ #define TRIGGER_TYPE_CSD_DSI_SAMPLE_OUT TRIGGER_TYPE_EDGE -/* SCB Trigger Types */ -#define TRIGGER_TYPE_SCB_TR_I2C_SCL_FILTERED TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_SCB_TR_TX_REQ TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_SCB_TR_RX_REQ TRIGGER_TYPE_LEVEL +/* LPCOMP Trigger Types */ +#define TRIGGER_TYPE_LPCOMP_DSI_COMP0 TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_LPCOMP_DSI_COMP1 TRIGGER_TYPE_LEVEL +/* PASS Trigger Types */ +#define TRIGGER_TYPE_PASS_TR_SAR_IN__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_PASS_TR_SAR_IN__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_PASS_TR_SAR_OUT TRIGGER_TYPE_EDGE /* PERI Trigger Types */ +#define TRIGGER_TYPE_PERI_TR_DBG_FREEZE TRIGGER_TYPE_LEVEL #define TRIGGER_TYPE_PERI_TR_IO_INPUT__LEVEL TRIGGER_TYPE_LEVEL #define TRIGGER_TYPE_PERI_TR_IO_INPUT__EDGE TRIGGER_TYPE_EDGE #define TRIGGER_TYPE_PERI_TR_IO_OUTPUT__LEVEL TRIGGER_TYPE_LEVEL #define TRIGGER_TYPE_PERI_TR_IO_OUTPUT__EDGE TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_PERI_TR_DBG_FREEZE TRIGGER_TYPE_LEVEL -/* CPUSS Trigger Types */ -#define TRIGGER_TYPE_CPUSS_DW0_TR_IN__LEVEL TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_CPUSS_DW0_TR_IN__EDGE TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_CPUSS_DW1_TR_IN__LEVEL TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_CPUSS_DW1_TR_IN__EDGE TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_CPUSS_DMAC_TR_IN__LEVEL TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_CPUSS_DMAC_TR_IN__EDGE TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_CPUSS_DW0_TR_OUT TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_CPUSS_DW1_TR_OUT TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_CPUSS_DMAC_TR_OUT TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_CPUSS_CTI_TR_OUT TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_CPUSS_TR_FAULT TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_CPUSS_CTI_TR_IN TRIGGER_TYPE_EDGE -/* CANFD Trigger Types */ -#define TRIGGER_TYPE_CANFD_TR_TMP_RTP_OUT TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_CANFD_TR_EVT_SWT_IN TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_CANFD_TR_DBG_DMA_REQ TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_CANFD_TR_FIFO0 TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_CANFD_TR_FIFO1 TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_CANFD_TR_DBG_DMA_ACK TRIGGER_TYPE_EDGE -/* LPCOMP Trigger Types */ -#define TRIGGER_TYPE_LPCOMP_DSI_COMP0 TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_LPCOMP_DSI_COMP1 TRIGGER_TYPE_LEVEL +/* SCB Trigger Types */ +#define TRIGGER_TYPE_SCB_TR_I2C_SCL_FILTERED TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_SCB_TR_RX_REQ TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_SCB_TR_TX_REQ TRIGGER_TYPE_LEVEL /* SMIF Trigger Types */ -#define TRIGGER_TYPE_SMIF_TR_TX_REQ TRIGGER_TYPE_LEVEL #define TRIGGER_TYPE_SMIF_TR_RX_REQ TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_SMIF_TR_TX_REQ TRIGGER_TYPE_LEVEL +/* TCPWM Trigger Types */ +#define TRIGGER_TYPE_TCPWM_LINE TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_TCPWM_LINE_COMPL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_TCPWM_TR_COMPARE_MATCH TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_TCPWM_TR_IN__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_TCPWM_TR_IN__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_TCPWM_TR_OVERFLOW TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_TCPWM_TR_UNDERFLOW TRIGGER_TYPE_EDGE /* USB Trigger Types */ -#define TRIGGER_TYPE_USB_DMA_REQ TRIGGER_TYPE_EDGE #define TRIGGER_TYPE_USB_DMA_BURSTEND TRIGGER_TYPE_EDGE -/* PASS Trigger Types */ -#define TRIGGER_TYPE_PASS_TR_SAR_OUT TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_PASS_TR_SAR_IN__LEVEL TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_PASS_TR_SAR_IN__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_USB_DMA_REQ TRIGGER_TYPE_EDGE /* Bus masters */ typedef enum @@ -1267,92 +1267,273 @@ typedef PASS_AREF_V1_Type PASS_AREF_Type; typedef PASS_V1_Type PASS_Type; /* Parameter Defines */ -/* Number of regulator modules instantiated within SRSS, start with estimate, - update after CMR feedback */ -#define SRSS_NUM_ACTREG_PWRMOD 2u -/* Number of shorting switches between vccd and vccact (target dynamic voltage - drop < 10mV) */ -#define SRSS_NUM_ACTIVE_SWITCH 3u -/* ULP linear regulator system is present */ -#define SRSS_ULPLINREG_PRESENT 1u -/* HT linear regulator system is present */ -#define SRSS_HTLINREG_PRESENT 0u -/* Low-current buck regulator present. Can be derived from S40S_SISOBUCKLC_PRESENT - or SIMOBUCK_PRESENT. */ -#define SRSS_BUCKCTL_PRESENT 1u -/* Low-current SISO buck core regulator is present. Only compatible with ULP - linear regulator system (ULPLINREG_PRESENT==1). */ -#define SRSS_S40S_SISOBUCKLC_PRESENT 1u -/* SIMO buck core regulator is present. Only compatible with ULP linear regulator - system (ULPLINREG_PRESENT==1). */ -#define SRSS_SIMOBUCK_PRESENT 0u -/* Precision ILO (PILO) is present */ -#define SRSS_PILO_PRESENT 0u -/* External Crystal Oscillator is present (high frequency) */ -#define SRSS_ECO_PRESENT 1u -/* System Buck-Boost is present */ -#define SRSS_SYSBB_PRESENT 0u -/* Number of clock paths. Must be > 0 */ -#define SRSS_NUM_CLKPATH 5u -/* Number of PLLs present. Must be <= NUM_CLKPATH */ -#define SRSS_NUM_PLL 1u -/* Number of HFCLK roots present. Must be > 0 */ -#define SRSS_NUM_HFROOT 5u -/* Number of PWR_HIB_DATA registers, should not be needed if BACKUP_PRESENT */ -#define SRSS_NUM_HIBDATA 1u -/* Backup domain is present (includes RTC and WCO) */ -#define SRSS_BACKUP_PRESENT 1u -/* Mask of HFCLK root clock supervisors (CSV). For each clock root i, bit[i] of - mask indicates presence of a CSV. */ -#define SRSS_MASK_HFCSV 0u -/* Clock supervisor is present on WCO. Must be 0 if BACKUP_PRESENT==0. */ -#define SRSS_WCOCSV_PRESENT 0u -/* Number of software watchdog timers. */ -#define SRSS_NUM_MCWDT 2u -/* Number of DSI inputs into clock muxes. This is used for logic optimization. */ -#define SRSS_NUM_DSI 0u -/* Alternate high-frequency clock is present. This is used for logic optimization. */ -#define SRSS_ALTHF_PRESENT 0u -/* Alternate low-frequency clock is present. This is used for logic optimization. */ -#define SRSS_ALTLF_PRESENT 0u -/* Use the hardened clkactfllmux block */ -#define SRSS_USE_HARD_CLKACTFLLMUX 1u -/* Number of clock paths, including direct paths in hardened clkactfllmux block - (Must be >= NUM_CLKPATH) */ -#define SRSS_HARD_CLKPATH 6u -/* Number of clock paths with muxes in hardened clkactfllmux block (Must be >= - NUM_PLL+1) */ -#define SRSS_HARD_CLKPATHMUX 6u -/* Number of HFCLKS present in hardened clkactfllmux block (Must be >= NUM_HFROOT) */ -#define SRSS_HARD_HFROOT 6u -/* ECO mux is present in hardened clkactfllmux block (Must be >= ECO_PRESENT) */ -#define SRSS_HARD_ECOMUX_PRESENT 1u -/* ALTHF mux is present in hardened clkactfllmux block (Must be >= ALTHF_PRESENT) */ -#define SRSS_HARD_ALTHFMUX_PRESENT 1u -/* SRSS version is at least SRSS_VER1P3. Set to 1 for new products. Set to 0 for - PSoC6ABLE2, PSoC6A2M. */ -#define SRSS_SRSS_VER1P3 1u -/* Backup memory is present (only used when BACKUP_PRESENT==1) */ -#define SRSS_BACKUP_BMEM_PRESENT 0u -/* Number of Backup registers to include (each is 32b). Only used when - BACKUP_PRESENT==1. */ -#define SRSS_BACKUP_NUM_BREG 16u -/* Number of AMUX splitter cells */ -#define IOSS_HSIOM_AMUX_SPLIT_NR 6u -/* Number of HSIOM ports in device (same as GPIO.GPIO_PRT_NR) */ -#define IOSS_HSIOM_HSIOM_PORT_NR 15u -/* Number of PWR/GND MONITOR CELLs in the device */ -#define IOSS_HSIOM_MONITOR_NR 0u -/* Number of PWR/GND MONITOR CELLs in range 0..31 */ -#define IOSS_HSIOM_MONITOR_NR_0_31 0u -/* Number of PWR/GND MONITOR CELLs in range 32..63 */ -#define IOSS_HSIOM_MONITOR_NR_32_63 0u -/* Number of PWR/GND MONITOR CELLs in range 64..95 */ -#define IOSS_HSIOM_MONITOR_NR_64_95 0u -/* Number of PWR/GND MONITOR CELLs in range 96..127 */ -#define IOSS_HSIOM_MONITOR_NR_96_127 0u -/* Indicates the presence of alternate JTAG interface */ -#define IOSS_HSIOM_ALTJTAG_PRESENT 0u +/* Number of TTCAN instances */ +#define CANFD_CAN_NR 1u +/* ECC logic present or not */ +#define CANFD_ECC_PRESENT 0u +/* address included in ECC logic or not */ +#define CANFD_ECC_ADDR_PRESENT 0u +/* Time Stamp counter present or not (required for instance 0, otherwise not + allowed) */ +#define CANFD_TS_PRESENT 1u +/* Message RAM size in KB */ +#define CANFD_MRAM_SIZE 4u +/* Message RAM address width */ +#define CANFD_MRAM_ADDR_WIDTH 10u +/* UDB present or not ('0': no, '1': yes) */ +#define CPUSS_UDB_PRESENT 0u +/* MBIST MMIO for Synopsys MBIST ('0': no, '1': yes). Set this to '1' only for the + chips which doesn't use mxdft. */ +#define CPUSS_MBIST_MMIO_PRESENT 1u +/* System RAM 0 size in kilobytes */ +#define CPUSS_SRAM0_SIZE 256u +/* Number of macros used to implement System RAM 0. Example: 8 if 256 KB System + SRAM0 is implemented with 8 32KB macros. */ +#define CPUSS_RAMC0_MACRO_NR 8u +/* System RAM 1 present or not (0=No, 1=Yes) */ +#define CPUSS_RAMC1_PRESENT 0u +/* System RAM 1 size in kilobytes */ +#define CPUSS_SRAM1_SIZE 1u +/* Number of macros used to implement System RAM 1. Example: 8 if 256 KB System + RAM 1 is implemented with 8 32KB macros. */ +#define CPUSS_RAMC1_MACRO_NR 1u +/* System RAM 2 present or not (0=No, 1=Yes) */ +#define CPUSS_RAMC2_PRESENT 0u +/* System RAM 2 size in kilobytes */ +#define CPUSS_SRAM2_SIZE 1u +/* Number of macros used to implement System RAM 2. Example: 8 if 256 KB System + RAM 2 is implemented with 8 32KB macros. */ +#define CPUSS_RAMC2_MACRO_NR 1u +/* System SRAM(s) ECC present or not ('0': no, '1': yes) */ +#define CPUSS_RAMC_ECC_PRESENT 0u +/* System SRAM(s) address ECC present or not ('0': no, '1': yes) */ +#define CPUSS_RAMC_ECC_ADDR_PRESENT 0u +/* ECC present in either system RAM or interrupt handler (RAMC_ECC_PRESENT) */ +#define CPUSS_ECC_PRESENT 0u +/* DataWire SRAMs ECC present or not ('0': no, '1': yes) */ +#define CPUSS_DW_ECC_PRESENT 0u +/* DataWire SRAMs address ECC present or not ('0': no, '1': yes) */ +#define CPUSS_DW_ECC_ADDR_PRESENT 0u +/* System ROM size in KB */ +#define CPUSS_ROM_SIZE 64u +/* Number of macros used to implement system ROM. Example: 4 if 512 KB system ROM + is implemented with 4 128KB macros. */ +#define CPUSS_ROMC_MACRO_NR 1u +/* Flash memory type ('0' : SONOS, '1': ECT) */ +#define CPUSS_FLASHC_ECT 0u +/* Flash main region size in KB */ +#define CPUSS_FLASH_SIZE 512u +/* Flash work region size in KB (EEPROM emulation, data) */ +#define CPUSS_WFLASH_SIZE 32u +/* Flash supervisory region size in KB */ +#define CPUSS_SFLASH_SIZE 32u +/* Flash data output word size (in Bytes) */ +#define CPUSS_FLASHC_MAIN_DATA_WIDTH 16u +/* SONOS Flash RWW present or not ('0': no, '1': yes) When RWW is '0', No special + sectors present in Flash. Part of main sector 0 is allowcated for Supervisory + Flash, and no Work Flash present. */ +#define CPUSS_FLASHC_SONOS_RWW 1u +/* SONOS Flash, number of main sectors. */ +#define CPUSS_FLASHC_SONOS_MAIN_SECTORS 2u +/* SONOS Flash, number of rows per main sector. */ +#define CPUSS_FLASHC_SONOS_MAIN_ROWS 512u +/* SONOS Flash, number of words per row of main sector. */ +#define CPUSS_FLASHC_SONOS_MAIN_WORDS 128u +/* SONOS Flash, number of special sectors. */ +#define CPUSS_FLASHC_SONOS_SPL_SECTORS 2u +/* SONOS Flash, number of rows per special sector. */ +#define CPUSS_FLASHC_SONOS_SPL_ROWS 64u +/* Flash memory ECC present or not ('0': no, '1': yes) */ +#define CPUSS_FLASHC_FLASH_ECC_PRESENT 0u +/* Flash cache SRAM(s) ECC present or not ('0': no, '1': yes) */ +#define CPUSS_FLASHC_RAM_ECC_PRESENT 0u +/* Number of external slaves directly connected to slow AHB-Lite infrastructure. + Maximum nubmer of slave supported is 4. Width of this parameter is 4-bits. + 1-bit mask for each slave indicating present or not. Example: 4'b0011 - slave + 0 and slave 1 are present. Note: The SLOW_SLx_ADDR and SLOW_SLx_MASK + parameters (for the slaves present) should be derived from the Memory Map. */ +#define CPUSS_SLOW_SL_PRESENT 1u +/* Number of external slaves directly connected to fast AHB-Lite infrastructure. + Maximum nubmer of slave supported is 4. Width of this parameter is 4-bits. + 1-bit mask for each slave indicating present or not. Example: 4'b0011 - slave + 0 and slave 1 are present. Note: The FAST_SLx_ADDR and FAST_SLx_MASK + parameters (for the slaves present) should be derived from the Memory Map. */ +#define CPUSS_FAST_SL_PRESENT 1u +/* Number of external masters driving the slow AHB-Lite infrastructure. Maximum + number of masters supported is 2. Width of this parameter is 2-bits. 1-bit + mask for each master indicating present or not. Example: 2'b01 - master 0 is + present. */ +#define CPUSS_SLOW_MS_PRESENT 1u +/* System interrupt functionality present or not ('0': no; '1': yes). Not used for + CM0+ PCU, which always uses system interrupt functionality. */ +#define CPUSS_SYSTEM_IRQ_PRESENT 0u +/* Number of total interrupt request inputs to CPUSS */ +#define CPUSS_SYSTEM_INT_NR 174u +/* Number of DeepSleep wakeup interrupt inputs to CPUSS */ +#define CPUSS_SYSTEM_DPSLP_INT_NR 39u +/* Width of the CM4 interrupt priority bits. Legal range [3,8] Example: 3 = 8 + levels of priority 8 = 256 levels of priority */ +#define CPUSS_CM4_LVL_WIDTH 3u +/* CM4 Floating point unit present or not (0=No, 1=Yes) */ +#define CPUSS_CM4_FPU_PRESENT 1u +/* Debug level. Legal range [0,3] (0= No support, 1= Minimum: CM0/4 both 2 + breakpoints +1 watchpoint, 2= Full debug: CM0/4 have 4/6 breakpoints, 2/4 + watchpoints and 0/2 literal compare, 3= Full debug + data matching) */ +#define CPUSS_DEBUG_LVL 3u +/* Trace level. Legal range [0,2] (0= No tracing, 1= ITM + TPIU + SWO, 2= ITM + + ETM + TPIU + SWO) Note: CM4 HTM is not supported. Hence vaule 3 for trace + level is not supported in CPUSS. */ +#define CPUSS_TRACE_LVL 2u +/* Embedded Trace Buffer present or not (0=No, 1=Yes) */ +#define CPUSS_ETB_PRESENT 0u +/* CM0+ MTB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */ +#define CPUSS_MTB_SRAM_SIZE 4u +/* CM4 ETB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */ +#define CPUSS_ETB_SRAM_SIZE 8u +/* PTM interface present (0=No, 1=Yes) */ +#define CPUSS_PTM_PRESENT 0u +/* Width of the PTM interface in bits ([2,32]) */ +#define CPUSS_PTM_WIDTH 1u +/* Width of the TPIU interface in bits ([1,4]) */ +#define CPUSS_TPIU_WIDTH 4u +/* CoreSight Part Identification Number */ +#define CPUSS_JEPID 52u +/* CoreSight Part Identification Number */ +#define CPUSS_JEPCONTINUATION 0u +/* CoreSight Part Identification Number */ +#define CPUSS_FAMILYID 261u +/* ROM trim register width (for ARM 3, for Synopsys 5) */ +#define CPUSS_ROM_TRIM_WIDTH 5u +/* ROM trim register default (for both ARM and Synopsys 0x0000_0012) */ +#define CPUSS_ROM_TRIM_DEFAULT 18u +/* RAM trim register width (for ARM 8, for Synopsys 15) */ +#define CPUSS_RAM_TRIM_WIDTH 15u +/* RAM trim register default (for ARM 0x0000_0062 and for Synopsys 0x0000_6012) */ +#define CPUSS_RAM_TRIM_DEFAULT 24594u +/* Cryptography IP present or not (0=No, 1=Yes) */ +#define CPUSS_CRYPTO_PRESENT 1u +/* DataWire and DMAC SW trigger per channel present or not ('0': no, '1': yes) */ +#define CPUSS_SW_TR_PRESENT 0u +/* DataWire 0 present or not (0=No, 1=Yes) */ +#define CPUSS_DW0_PRESENT 1u +/* Number of DataWire 0 channels (8, 16 or 32) */ +#define CPUSS_DW0_CH_NR 29u +/* DataWire 1 present or not (0=No, 1=Yes) */ +#define CPUSS_DW1_PRESENT 1u +/* Number of DataWire 1 channels (8, 16 or 32) */ +#define CPUSS_DW1_CH_NR 32u +/* DMA controller present or not ('0': no, '1': yes) */ +#define CPUSS_DMAC_PRESENT 1u +/* Number of DMA controller channels ([1, 8]) */ +#define CPUSS_DMAC_CH_NR 2u +/* DMAC SW trigger per channel present or not ('0': no, '1': yes) */ +#define CPUSS_CH_SW_TR_PRESENT 0u +/* Copy value from Globals */ +#define CPUSS_CHIP_TOP_PROFILER_PRESENT 0u +/* ETAS Calibration support pin out present (automotive only) */ +#define CPUSS_CHIP_TOP_CAL_SUP_NZ_PRESENT 0u +/* TRACE_LVL>0 */ +#define CPUSS_CHIP_TOP_TRACE_PRESENT 1u +/* DataWire SW trigger per channel present or not ('0': no, '1': yes) */ +#define CPUSS_CH_STRUCT_SW_TR_PRESENT 0u +/* Number of DataWire controllers present (max 2) (same as DW.NR above) */ +#define CPUSS_CPUSS_DW_DW_NR 2u +/* Number of channels in each DataWire controller */ +#define CPUSS_CPUSS_DW_DW_NR0_DW_CH_NR 29u +/* Width of a channel number in bits */ +#define CPUSS_CPUSS_DW_DW_NR0_DW_CH_NR_WIDTH 5u +/* Number of channels in each DataWire controller */ +#define CPUSS_CPUSS_DW_DW_NR1_DW_CH_NR 32u +/* Width of a channel number in bits */ +#define CPUSS_CPUSS_DW_DW_NR1_DW_CH_NR_WIDTH 5u +/* Cryptography SRAMs ECC present or not ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_ECC_PRESENT 0u +/* Cryptography SRAMs address ECC present or not ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_ECC_ADDR_PRESENT 0u +/* AES cipher support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_AES 1u +/* (Tripple) DES cipher support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_DES 1u +/* Chacha support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_CHACHA 1u +/* Pseudo random number generation support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_PR 1u +/* SHA1 hash support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_SHA1 1u +/* SHA2 hash support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_SHA2 1u +/* SHA3 hash support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_SHA3 1u +/* Cyclic Redundancy Check support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_CRC 1u +/* True random number generation support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_TR 1u +/* Vector unit support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_VU 1u +/* Galios/Counter Mode (GCM) support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_GCM 1u +/* Number of 32-bit words in the IP internal memory buffer (from the set [64, 128, + 256, 512, 1024, 2048, 4096], to allow for a 256 B, 512 B, 1 kB, 2 kB, 4 kB, 8 + kB and 16 kB memory buffer) */ +#define CPUSS_CRYPTO_BUFF_SIZE 1024u +/* Number of DMA controller channels ([1, 8]) */ +#define CPUSS_DMAC_CH_NR 2u +/* Number of DataWire controllers present (max 2) */ +#define CPUSS_DW_NR 2u +/* DataWire SRAMs ECC present or not ('0': no, '1': yes) */ +#define CPUSS_DW_ECC_PRESENT 0u +/* Number of fault structures. Legal range [1, 4] */ +#define CPUSS_FAULT_FAULT_NR 2u +/* Number of Flash BIST_DATA registers */ +#define CPUSS_FLASHC_FLASHC_BIST_DATA_NR 4u +/* Page size in # of 32-bit words (1: 4 bytes, 2: 8 bytes, ... */ +#define CPUSS_FLASHC_PA_SIZE 128u +/* SONOS Flash is used or not ('0': no, '1': yes) */ +#define CPUSS_FLASHC_FLASHC_IS_SONOS 1u +/* eCT Flash is used or not ('0': no, '1': yes) */ +#define CPUSS_FLASHC_FLASHC_IS_ECT 0u +/* Number of IPC structures. Legal range [1, 16] */ +#define CPUSS_IPC_IPC_NR 16u +/* Number of IPC interrupt structures. Legal range [1, 16] */ +#define CPUSS_IPC_IPC_IRQ_NR 16u +/* Master 0 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS0_PC_NR_MINUS1 7u +/* Master 1 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS1_PC_NR_MINUS1 0u +/* Master 2 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS2_PC_NR_MINUS1 0u +/* Master 3 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS3_PC_NR_MINUS1 0u +/* Master 4 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS4_PC_NR_MINUS1 0u +/* Master 5 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS5_PC_NR_MINUS1 7u +/* Master 6 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS6_PC_NR_MINUS1 0u +/* Master 7 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS7_PC_NR_MINUS1 0u +/* Master 8 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS8_PC_NR_MINUS1 0u +/* Master 9 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS9_PC_NR_MINUS1 0u +/* Master 10 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS10_PC_NR_MINUS1 0u +/* Master 11 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS11_PC_NR_MINUS1 0u +/* Master 12 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS12_PC_NR_MINUS1 0u +/* Master 13 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS13_PC_NR_MINUS1 0u +/* Master 14 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS14_PC_NR_MINUS1 7u +/* Master 15 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS15_PC_NR_MINUS1 7u +/* Number of SMPU protection structures */ +#define CPUSS_PROT_SMPU_STRUCT_NR 16u +/* Number of protection contexts supported minus 1. Legal range [1,16] */ +#define CPUSS_SMPU_STRUCT_PC_NR_MINUS1 7u +/* Number of instantiated eFUSE macros (256 bit macros). Legal range [1, 16] */ +#define EFUSE_EFUSE_NR 4u /* Number of GPIO ports in range 0..31 */ #define IOSS_GPIO_GPIO_PORT_NR_0_31 15u /* Number of GPIO ports in range 32..63 */ @@ -1693,8 +1874,65 @@ typedef PASS_V1_Type PASS_Type; #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO6 0u /* Indicates that pin #7 exists for this port with slew control feature */ #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO7 0u +/* Number of AMUX splitter cells */ +#define IOSS_HSIOM_AMUX_SPLIT_NR 6u +/* Number of HSIOM ports in device (same as GPIO.GPIO_PRT_NR) */ +#define IOSS_HSIOM_HSIOM_PORT_NR 15u +/* Number of PWR/GND MONITOR CELLs in the device */ +#define IOSS_HSIOM_MONITOR_NR 0u +/* Number of PWR/GND MONITOR CELLs in range 0..31 */ +#define IOSS_HSIOM_MONITOR_NR_0_31 0u +/* Number of PWR/GND MONITOR CELLs in range 32..63 */ +#define IOSS_HSIOM_MONITOR_NR_32_63 0u +/* Number of PWR/GND MONITOR CELLs in range 64..95 */ +#define IOSS_HSIOM_MONITOR_NR_64_95 0u +/* Number of PWR/GND MONITOR CELLs in range 96..127 */ +#define IOSS_HSIOM_MONITOR_NR_96_127 0u +/* Indicates the presence of alternate JTAG interface */ +#define IOSS_HSIOM_ALTJTAG_PRESENT 0u /* Mask of SMARTIO instances presence */ #define IOSS_SMARTIO_SMARTIO_MASK 768u +/* Number of ports supoprting up to 4 COMs */ +#define LCD_NUMPORTS 8u +/* Number of ports supporting up to 8 COMs */ +#define LCD_NUMPORTS8 8u +/* Number of ports supporting up to 16 COMs */ +#define LCD_NUMPORTS16 0u +/* Max number of LCD commons supported */ +#define LCD_CHIP_TOP_COM_NR 8u +/* Max number of LCD pins (total) supported */ +#define LCD_CHIP_TOP_PIN_NR 60u +/* Number of IREF outputs from AREF */ +#define PASS_NR_IREFS 4u +/* Number of CTBs in the Subsystem */ +#define PASS_NR_CTBS 0u +/* Number of CTDACs in the Subsystem */ +#define PASS_NR_CTDACS 0u +/* CTB0 Exists */ +#define PASS_CTB0_EXISTS 0u +/* CTB1 Exists */ +#define PASS_CTB1_EXISTS 0u +/* CTB2 Exists */ +#define PASS_CTB2_EXISTS 0u +/* CTB3 Exists */ +#define PASS_CTB3_EXISTS 0u +/* CTDAC0 Exists */ +#define PASS_CTDAC0_EXISTS 0u +/* CTDAC1 Exists */ +#define PASS_CTDAC1_EXISTS 0u +/* CTDAC2 Exists */ +#define PASS_CTDAC2_EXISTS 0u +/* CTDAC3 Exists */ +#define PASS_CTDAC3_EXISTS 0u +#define PASS_CTBM_CTDAC_PRESENT 0u +/* Number of SAR channels */ +#define PASS_SAR_SAR_CHANNELS 16u +/* Averaging logic present in SAR */ +#define PASS_SAR_SAR_AVERAGE 1u +/* Range detect logic present in SAR */ +#define PASS_SAR_SAR_RANGEDET 1u +/* Support for UAB sampling */ +#define PASS_SAR_SAR_UAB 0u /* The number of protection contexts ([2, 16]). */ #define PERI_PC_NR 8u /* Master interface presence mask (4 bits) */ @@ -2305,264 +2543,6 @@ typedef PASS_V1_Type PASS_Type; #define PERI_TR_1TO1_GROUP_NR7_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ #define PERI_MASTER_WIDTH 8u -/* UDB present or not ('0': no, '1': yes) */ -#define CPUSS_UDB_PRESENT 0u -/* MBIST MMIO for Synopsys MBIST ('0': no, '1': yes). Set this to '1' only for the - chips which doesn't use mxdft. */ -#define CPUSS_MBIST_MMIO_PRESENT 1u -/* System RAM 0 size in kilobytes */ -#define CPUSS_SRAM0_SIZE 256u -/* Number of macros used to implement System RAM 0. Example: 8 if 256 KB System - SRAM0 is implemented with 8 32KB macros. */ -#define CPUSS_RAMC0_MACRO_NR 8u -/* System RAM 1 present or not (0=No, 1=Yes) */ -#define CPUSS_RAMC1_PRESENT 0u -/* System RAM 1 size in kilobytes */ -#define CPUSS_SRAM1_SIZE 1u -/* Number of macros used to implement System RAM 1. Example: 8 if 256 KB System - RAM 1 is implemented with 8 32KB macros. */ -#define CPUSS_RAMC1_MACRO_NR 1u -/* System RAM 2 present or not (0=No, 1=Yes) */ -#define CPUSS_RAMC2_PRESENT 0u -/* System RAM 2 size in kilobytes */ -#define CPUSS_SRAM2_SIZE 1u -/* Number of macros used to implement System RAM 2. Example: 8 if 256 KB System - RAM 2 is implemented with 8 32KB macros. */ -#define CPUSS_RAMC2_MACRO_NR 1u -/* System SRAM(s) ECC present or not ('0': no, '1': yes) */ -#define CPUSS_RAMC_ECC_PRESENT 0u -/* System SRAM(s) address ECC present or not ('0': no, '1': yes) */ -#define CPUSS_RAMC_ECC_ADDR_PRESENT 0u -/* ECC present in either system RAM or interrupt handler (RAMC_ECC_PRESENT) */ -#define CPUSS_ECC_PRESENT 0u -/* DataWire SRAMs ECC present or not ('0': no, '1': yes) */ -#define CPUSS_DW_ECC_PRESENT 0u -/* DataWire SRAMs address ECC present or not ('0': no, '1': yes) */ -#define CPUSS_DW_ECC_ADDR_PRESENT 0u -/* System ROM size in KB */ -#define CPUSS_ROM_SIZE 64u -/* Number of macros used to implement system ROM. Example: 4 if 512 KB system ROM - is implemented with 4 128KB macros. */ -#define CPUSS_ROMC_MACRO_NR 1u -/* Flash memory type ('0' : SONOS, '1': ECT) */ -#define CPUSS_FLASHC_ECT 0u -/* Flash main region size in KB */ -#define CPUSS_FLASH_SIZE 512u -/* Flash work region size in KB (EEPROM emulation, data) */ -#define CPUSS_WFLASH_SIZE 32u -/* Flash supervisory region size in KB */ -#define CPUSS_SFLASH_SIZE 32u -/* Flash data output word size (in Bytes) */ -#define CPUSS_FLASHC_MAIN_DATA_WIDTH 16u -/* SONOS Flash RWW present or not ('0': no, '1': yes) When RWW is '0', No special - sectors present in Flash. Part of main sector 0 is allowcated for Supervisory - Flash, and no Work Flash present. */ -#define CPUSS_FLASHC_SONOS_RWW 1u -/* SONOS Flash, number of main sectors. */ -#define CPUSS_FLASHC_SONOS_MAIN_SECTORS 2u -/* SONOS Flash, number of rows per main sector. */ -#define CPUSS_FLASHC_SONOS_MAIN_ROWS 512u -/* SONOS Flash, number of words per row of main sector. */ -#define CPUSS_FLASHC_SONOS_MAIN_WORDS 128u -/* SONOS Flash, number of special sectors. */ -#define CPUSS_FLASHC_SONOS_SPL_SECTORS 2u -/* SONOS Flash, number of rows per special sector. */ -#define CPUSS_FLASHC_SONOS_SPL_ROWS 64u -/* Flash memory ECC present or not ('0': no, '1': yes) */ -#define CPUSS_FLASHC_FLASH_ECC_PRESENT 0u -/* Flash cache SRAM(s) ECC present or not ('0': no, '1': yes) */ -#define CPUSS_FLASHC_RAM_ECC_PRESENT 0u -/* Number of external slaves directly connected to slow AHB-Lite infrastructure. - Maximum nubmer of slave supported is 4. Width of this parameter is 4-bits. - 1-bit mask for each slave indicating present or not. Example: 4'b0011 - slave - 0 and slave 1 are present. Note: The SLOW_SLx_ADDR and SLOW_SLx_MASK - parameters (for the slaves present) should be derived from the Memory Map. */ -#define CPUSS_SLOW_SL_PRESENT 1u -/* Number of external slaves directly connected to fast AHB-Lite infrastructure. - Maximum nubmer of slave supported is 4. Width of this parameter is 4-bits. - 1-bit mask for each slave indicating present or not. Example: 4'b0011 - slave - 0 and slave 1 are present. Note: The FAST_SLx_ADDR and FAST_SLx_MASK - parameters (for the slaves present) should be derived from the Memory Map. */ -#define CPUSS_FAST_SL_PRESENT 1u -/* Number of external masters driving the slow AHB-Lite infrastructure. Maximum - number of masters supported is 2. Width of this parameter is 2-bits. 1-bit - mask for each master indicating present or not. Example: 2'b01 - master 0 is - present. */ -#define CPUSS_SLOW_MS_PRESENT 1u -/* System interrupt functionality present or not ('0': no; '1': yes). Not used for - CM0+ PCU, which always uses system interrupt functionality. */ -#define CPUSS_SYSTEM_IRQ_PRESENT 0u -/* Number of total interrupt request inputs to CPUSS */ -#define CPUSS_SYSTEM_INT_NR 174u -/* Number of DeepSleep wakeup interrupt inputs to CPUSS */ -#define CPUSS_SYSTEM_DPSLP_INT_NR 39u -/* Width of the CM4 interrupt priority bits. Legal range [3,8] Example: 3 = 8 - levels of priority 8 = 256 levels of priority */ -#define CPUSS_CM4_LVL_WIDTH 3u -/* CM4 Floating point unit present or not (0=No, 1=Yes) */ -#define CPUSS_CM4_FPU_PRESENT 1u -/* Debug level. Legal range [0,3] (0= No support, 1= Minimum: CM0/4 both 2 - breakpoints +1 watchpoint, 2= Full debug: CM0/4 have 4/6 breakpoints, 2/4 - watchpoints and 0/2 literal compare, 3= Full debug + data matching) */ -#define CPUSS_DEBUG_LVL 3u -/* Trace level. Legal range [0,2] (0= No tracing, 1= ITM + TPIU + SWO, 2= ITM + - ETM + TPIU + SWO) Note: CM4 HTM is not supported. Hence vaule 3 for trace - level is not supported in CPUSS. */ -#define CPUSS_TRACE_LVL 2u -/* Embedded Trace Buffer present or not (0=No, 1=Yes) */ -#define CPUSS_ETB_PRESENT 0u -/* CM0+ MTB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */ -#define CPUSS_MTB_SRAM_SIZE 4u -/* CM4 ETB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */ -#define CPUSS_ETB_SRAM_SIZE 8u -/* PTM interface present (0=No, 1=Yes) */ -#define CPUSS_PTM_PRESENT 0u -/* Width of the PTM interface in bits ([2,32]) */ -#define CPUSS_PTM_WIDTH 1u -/* Width of the TPIU interface in bits ([1,4]) */ -#define CPUSS_TPIU_WIDTH 4u -/* CoreSight Part Identification Number */ -#define CPUSS_JEPID 52u -/* CoreSight Part Identification Number */ -#define CPUSS_JEPCONTINUATION 0u -/* CoreSight Part Identification Number */ -#define CPUSS_FAMILYID 261u -/* ROM trim register width (for ARM 3, for Synopsys 5) */ -#define CPUSS_ROM_TRIM_WIDTH 5u -/* ROM trim register default (for both ARM and Synopsys 0x0000_0012) */ -#define CPUSS_ROM_TRIM_DEFAULT 18u -/* RAM trim register width (for ARM 8, for Synopsys 15) */ -#define CPUSS_RAM_TRIM_WIDTH 15u -/* RAM trim register default (for ARM 0x0000_0062 and for Synopsys 0x0000_6012) */ -#define CPUSS_RAM_TRIM_DEFAULT 24594u -/* Cryptography IP present or not (0=No, 1=Yes) */ -#define CPUSS_CRYPTO_PRESENT 1u -/* DataWire and DMAC SW trigger per channel present or not ('0': no, '1': yes) */ -#define CPUSS_SW_TR_PRESENT 0u -/* DataWire 0 present or not (0=No, 1=Yes) */ -#define CPUSS_DW0_PRESENT 1u -/* Number of DataWire 0 channels (8, 16 or 32) */ -#define CPUSS_DW0_CH_NR 29u -/* DataWire 1 present or not (0=No, 1=Yes) */ -#define CPUSS_DW1_PRESENT 1u -/* Number of DataWire 1 channels (8, 16 or 32) */ -#define CPUSS_DW1_CH_NR 32u -/* DMA controller present or not ('0': no, '1': yes) */ -#define CPUSS_DMAC_PRESENT 1u -/* Number of DMA controller channels ([1, 8]) */ -#define CPUSS_DMAC_CH_NR 2u -/* Number of Flash BIST_DATA registers */ -#define CPUSS_FLASHC_FLASHC_BIST_DATA_NR 4u -/* Page size in # of 32-bit words (1: 4 bytes, 2: 8 bytes, ... */ -#define CPUSS_FLASHC_PA_SIZE 128u -/* SONOS Flash is used or not ('0': no, '1': yes) */ -#define CPUSS_FLASHC_FLASHC_IS_SONOS 1u -/* eCT Flash is used or not ('0': no, '1': yes) */ -#define CPUSS_FLASHC_FLASHC_IS_ECT 0u -/* Cryptography SRAMs ECC present or not ('0': no, '1': yes) */ -#define CPUSS_CRYPTO_ECC_PRESENT 0u -/* Cryptography SRAMs address ECC present or not ('0': no, '1': yes) */ -#define CPUSS_CRYPTO_ECC_ADDR_PRESENT 0u -/* AES cipher support ('0': no, '1': yes) */ -#define CPUSS_CRYPTO_AES 1u -/* (Tripple) DES cipher support ('0': no, '1': yes) */ -#define CPUSS_CRYPTO_DES 1u -/* Chacha support ('0': no, '1': yes) */ -#define CPUSS_CRYPTO_CHACHA 1u -/* Pseudo random number generation support ('0': no, '1': yes) */ -#define CPUSS_CRYPTO_PR 1u -/* SHA1 hash support ('0': no, '1': yes) */ -#define CPUSS_CRYPTO_SHA1 1u -/* SHA2 hash support ('0': no, '1': yes) */ -#define CPUSS_CRYPTO_SHA2 1u -/* SHA3 hash support ('0': no, '1': yes) */ -#define CPUSS_CRYPTO_SHA3 1u -/* Cyclic Redundancy Check support ('0': no, '1': yes) */ -#define CPUSS_CRYPTO_CRC 1u -/* True random number generation support ('0': no, '1': yes) */ -#define CPUSS_CRYPTO_TR 1u -/* Vector unit support ('0': no, '1': yes) */ -#define CPUSS_CRYPTO_VU 1u -/* Galios/Counter Mode (GCM) support ('0': no, '1': yes) */ -#define CPUSS_CRYPTO_GCM 1u -/* Number of 32-bit words in the IP internal memory buffer (from the set [64, 128, - 256, 512, 1024, 2048, 4096], to allow for a 256 B, 512 B, 1 kB, 2 kB, 4 kB, 8 - kB and 16 kB memory buffer) */ -#define CPUSS_CRYPTO_BUFF_SIZE 1024u -/* Number of fault structures. Legal range [1, 4] */ -#define CPUSS_FAULT_FAULT_NR 2u -/* Number of IPC structures. Legal range [1, 16] */ -#define CPUSS_IPC_IPC_NR 16u -/* Number of IPC interrupt structures. Legal range [1, 16] */ -#define CPUSS_IPC_IPC_IRQ_NR 16u -/* Master 0 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS0_PC_NR_MINUS1 7u -/* Master 1 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS1_PC_NR_MINUS1 0u -/* Master 2 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS2_PC_NR_MINUS1 0u -/* Master 3 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS3_PC_NR_MINUS1 0u -/* Master 4 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS4_PC_NR_MINUS1 0u -/* Master 5 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS5_PC_NR_MINUS1 7u -/* Master 6 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS6_PC_NR_MINUS1 0u -/* Master 7 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS7_PC_NR_MINUS1 0u -/* Master 8 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS8_PC_NR_MINUS1 0u -/* Master 9 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS9_PC_NR_MINUS1 0u -/* Master 10 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS10_PC_NR_MINUS1 0u -/* Master 11 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS11_PC_NR_MINUS1 0u -/* Master 12 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS12_PC_NR_MINUS1 0u -/* Master 13 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS13_PC_NR_MINUS1 0u -/* Master 14 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS14_PC_NR_MINUS1 7u -/* Master 15 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS15_PC_NR_MINUS1 7u -/* Number of SMPU protection structures */ -#define CPUSS_PROT_SMPU_STRUCT_NR 16u -/* Number of protection contexts supported minus 1. Legal range [1,16] */ -#define CPUSS_SMPU_STRUCT_PC_NR_MINUS1 7u -/* Number of DataWire controllers present (max 2) */ -#define CPUSS_DW_NR 2u -/* DataWire SRAMs ECC present or not ('0': no, '1': yes) */ -#define CPUSS_DW_ECC_PRESENT 0u -/* DataWire SW trigger per channel present or not ('0': no, '1': yes) */ -#define CPUSS_CH_STRUCT_SW_TR_PRESENT 0u -/* Number of DataWire controllers present (max 2) (same as DW.NR above) */ -#define CPUSS_CPUSS_DW_DW_NR 2u -/* Number of channels in each DataWire controller */ -#define CPUSS_CPUSS_DW_DW_NR0_DW_CH_NR 29u -/* Width of a channel number in bits */ -#define CPUSS_CPUSS_DW_DW_NR0_DW_CH_NR_WIDTH 5u -/* Number of channels in each DataWire controller */ -#define CPUSS_CPUSS_DW_DW_NR1_DW_CH_NR 32u -/* Width of a channel number in bits */ -#define CPUSS_CPUSS_DW_DW_NR1_DW_CH_NR_WIDTH 5u -/* Number of DMA controller channels ([1, 8]) */ -#define CPUSS_DMAC_CH_NR 2u -/* DMAC SW trigger per channel present or not ('0': no, '1': yes) */ -#define CPUSS_CH_SW_TR_PRESENT 0u -/* Copy value from Globals */ -#define CPUSS_CHIP_TOP_PROFILER_PRESENT 0u -/* ETAS Calibration support pin out present (automotive only) */ -#define CPUSS_CHIP_TOP_CAL_SUP_NZ_PRESENT 0u -/* TRACE_LVL>0 */ -#define CPUSS_CHIP_TOP_TRACE_PRESENT 1u -/* Number of instantiated eFUSE macros (256 bit macros). Legal range [1, 16] */ -#define EFUSE_EFUSE_NR 4u -/* SONOS Flash is used or not ('0': no, '1': yes) */ -#define SFLASH_FLASHC_IS_SONOS 1u -/* CPUSS_WOUNDING_PRESENT or not ('0': no, '1': yes) */ -#define SFLASH_CPUSS_WOUNDING_PRESENT 0u /* DeepSleep support ('0':no, '1': yes) */ #define SCB0_DEEPSLEEP 0u /* Externally clocked support? ('0': no, '1': yes) */ @@ -2913,55 +2893,51 @@ typedef PASS_V1_Type PASS_Type; #define SCB6_I2C_FAST_PLUS 1u /* Number of used spi_select signals (max 4) */ #define SCB6_CHIP_TOP_SPI_SEL_NR 1u -/* Number of counters per IP (1..32) */ -#define TCPWM0_CNT_NR 4u -/* Counter width (in number of bits) */ -#define TCPWM0_CNT_CNT_WIDTH 32u -/* Number of counters per IP (1..32) */ -#define TCPWM1_CNT_NR 8u -/* Counter width (in number of bits) */ -#define TCPWM1_CNT_CNT_WIDTH 16u -/* Number of ports supoprting up to 4 COMs */ -#define LCD_NUMPORTS 8u -/* Number of ports supporting up to 8 COMs */ -#define LCD_NUMPORTS8 8u -/* Number of ports supporting up to 16 COMs */ -#define LCD_NUMPORTS16 0u -/* Max number of LCD commons supported */ -#define LCD_CHIP_TOP_COM_NR 8u -/* Max number of LCD pins (total) supported */ -#define LCD_CHIP_TOP_PIN_NR 60u -/* Number of IREF outputs from AREF */ -#define PASS_NR_IREFS 4u -/* Number of CTBs in the Subsystem */ -#define PASS_NR_CTBS 0u -/* Number of CTDACs in the Subsystem */ -#define PASS_NR_CTDACS 0u -/* CTB0 Exists */ -#define PASS_CTB0_EXISTS 0u -/* CTB1 Exists */ -#define PASS_CTB1_EXISTS 0u -/* CTB2 Exists */ -#define PASS_CTB2_EXISTS 0u -/* CTB3 Exists */ -#define PASS_CTB3_EXISTS 0u -/* CTDAC0 Exists */ -#define PASS_CTDAC0_EXISTS 0u -/* CTDAC1 Exists */ -#define PASS_CTDAC1_EXISTS 0u -/* CTDAC2 Exists */ -#define PASS_CTDAC2_EXISTS 0u -/* CTDAC3 Exists */ -#define PASS_CTDAC3_EXISTS 0u -/* Number of SAR channels */ -#define PASS_SAR_SAR_CHANNELS 16u -/* Averaging logic present in SAR */ -#define PASS_SAR_SAR_AVERAGE 1u -/* Range detect logic present in SAR */ -#define PASS_SAR_SAR_RANGEDET 1u -/* Support for UAB sampling */ -#define PASS_SAR_SAR_UAB 0u -#define PASS_CTBM_CTDAC_PRESENT 0u +/* Basically the max packet size, which gets double buffered in RAM 0: 512B + (implies 1KB of RAM space for data) 1: 1KB (implies 2KB of RAM space for + data) */ +#define SDHC_MAX_BLK_SIZE 0u +/* 0: No Command Queuing Engine present 1: Command Queuing Engine present; this + adds 288 bytes of space to the RAM for this purpose. */ +#define SDHC_CQE_PRESENT 0u +/* 0: no retention of any SDHC_CORE regs 1: retention of SDHC_CORE regs that have + the Retention flag (Note, CTL.ENABLE is always retained irrespective of this + parameter) */ +#define SDHC_RETENTION_PRESENT 1u +/* Chip top connect all 8 data pins (0= connect 4 data pins, 1= connect 8 data + pins) */ +#define SDHC_CHIP_TOP_DATA8_PRESENT 0u +/* Chip top connect card_detect */ +#define SDHC_CHIP_TOP_CARD_DETECT_PRESENT 1u +/* Chip top connect card_mech_write_prot_in */ +#define SDHC_CHIP_TOP_CARD_WRITE_PROT_PRESENT 1u +/* Chip top connect led_ctrl_out and led_ctrl_out_en */ +#define SDHC_CHIP_TOP_LED_CTRL_PRESENT 0u +/* Chip top connect io_volt_sel_out and io_volt_sel_out_en */ +#define SDHC_CHIP_TOP_IO_VOLT_SEL_PRESENT 1u +/* Chip top connect io_drive_strength_out and io_drive_strength_out_en */ +#define SDHC_CHIP_TOP_IO_DRIVE_STRENGTH_PRESENT 0u +/* Chip top connect card_if_pwr_en_out and card_if_pwr_en_out_en */ +#define SDHC_CHIP_TOP_CARD_IF_PWR_EN_PRESENT 1u +/* Chip top connect card_emmc_reset_n_out and card_emmc_reset_n_out_en */ +#define SDHC_CHIP_TOP_CARD_EMMC_RESET_PRESENT 0u +/* Chip top connect interrupt_wakeup (not used for eMMC) */ +#define SDHC_CHIP_TOP_INTERRUPT_WAKEUP_PRESENT 1u +/* Basically the max packet size, which gets double buffered in RAM 0: 512B + (implies 1KB of RAM space for data) 1: 1KB (implies 2KB of RAM space for + data) */ +#define SDHC_CORE_MAX_BLK_SIZE 0u +/* 0: No Command Queuing Engine present 1: Command Queuing Engine present; this + adds 288 bytes of space to the RAM for this purpose. */ +#define SDHC_CORE_CQE_PRESENT 0u +/* 0: no retention of any SDHC_CORE regs 1: retention of SDHC_CORE regs that have + the Retention flag (Note, CTL.ENABLE is always retained irrespective of this + parameter) */ +#define SDHC_CORE_RETENTION_PRESENT 1u +/* SONOS Flash is used or not ('0': no, '1': yes) */ +#define SFLASH_FLASHC_IS_SONOS 1u +/* CPUSS_WOUNDING_PRESENT or not ('0': no, '1': yes) */ +#define SFLASH_CPUSS_WOUNDING_PRESENT 0u /* Base address of the SMIF XIP memory region. This address must be a multiple of the SMIF XIP memory capacity. This address must be a multiple of 64 KB. This address must be in the [0x0000:0000, 0x1fff:ffff] memory region. The XIP @@ -2987,60 +2963,84 @@ typedef PASS_V1_Type PASS_Type; #define SMIF_CHIP_TOP_DATA8_PRESENT 0u /* Number of used spi_select signals (max 4) */ #define SMIF_CHIP_TOP_SPI_SEL_NR 3u -/* Basically the max packet size, which gets double buffered in RAM 0: 512B - (implies 1KB of RAM space for data) 1: 1KB (implies 2KB of RAM space for - data) */ -#define SDHC_MAX_BLK_SIZE 0u -/* 0: No Command Queuing Engine present 1: Command Queuing Engine present; this - adds 288 bytes of space to the RAM for this purpose. */ -#define SDHC_CQE_PRESENT 0u -/* 0: no retention of any SDHC_CORE regs 1: retention of SDHC_CORE regs that have - the Retention flag (Note, CTL.ENABLE is always retained irrespective of this - parameter) */ -#define SDHC_RETENTION_PRESENT 1u -/* Basically the max packet size, which gets double buffered in RAM 0: 512B - (implies 1KB of RAM space for data) 1: 1KB (implies 2KB of RAM space for - data) */ -#define SDHC_CORE_MAX_BLK_SIZE 0u -/* 0: No Command Queuing Engine present 1: Command Queuing Engine present; this - adds 288 bytes of space to the RAM for this purpose. */ -#define SDHC_CORE_CQE_PRESENT 0u -/* 0: no retention of any SDHC_CORE regs 1: retention of SDHC_CORE regs that have - the Retention flag (Note, CTL.ENABLE is always retained irrespective of this - parameter) */ -#define SDHC_CORE_RETENTION_PRESENT 1u -/* Chip top connect all 8 data pins (0= connect 4 data pins, 1= connect 8 data - pins) */ -#define SDHC_CHIP_TOP_DATA8_PRESENT 0u -/* Chip top connect card_detect */ -#define SDHC_CHIP_TOP_CARD_DETECT_PRESENT 1u -/* Chip top connect card_mech_write_prot_in */ -#define SDHC_CHIP_TOP_CARD_WRITE_PROT_PRESENT 1u -/* Chip top connect led_ctrl_out and led_ctrl_out_en */ -#define SDHC_CHIP_TOP_LED_CTRL_PRESENT 0u -/* Chip top connect io_volt_sel_out and io_volt_sel_out_en */ -#define SDHC_CHIP_TOP_IO_VOLT_SEL_PRESENT 1u -/* Chip top connect io_drive_strength_out and io_drive_strength_out_en */ -#define SDHC_CHIP_TOP_IO_DRIVE_STRENGTH_PRESENT 0u -/* Chip top connect card_if_pwr_en_out and card_if_pwr_en_out_en */ -#define SDHC_CHIP_TOP_CARD_IF_PWR_EN_PRESENT 1u -/* Chip top connect card_emmc_reset_n_out and card_emmc_reset_n_out_en */ -#define SDHC_CHIP_TOP_CARD_EMMC_RESET_PRESENT 0u -/* Chip top connect interrupt_wakeup (not used for eMMC) */ -#define SDHC_CHIP_TOP_INTERRUPT_WAKEUP_PRESENT 1u -/* Number of TTCAN instances */ -#define CANFD_CAN_NR 1u -/* ECC logic present or not */ -#define CANFD_ECC_PRESENT 0u -/* address included in ECC logic or not */ -#define CANFD_ECC_ADDR_PRESENT 0u -/* Time Stamp counter present or not (required for instance 0, otherwise not - allowed) */ -#define CANFD_TS_PRESENT 1u -/* Message RAM size in KB */ -#define CANFD_MRAM_SIZE 4u -/* Message RAM address width */ -#define CANFD_MRAM_ADDR_WIDTH 10u +/* Number of regulator modules instantiated within SRSS, start with estimate, + update after CMR feedback */ +#define SRSS_NUM_ACTREG_PWRMOD 2u +/* Number of shorting switches between vccd and vccact (target dynamic voltage + drop < 10mV) */ +#define SRSS_NUM_ACTIVE_SWITCH 3u +/* ULP linear regulator system is present */ +#define SRSS_ULPLINREG_PRESENT 1u +/* HT linear regulator system is present */ +#define SRSS_HTLINREG_PRESENT 0u +/* Low-current buck regulator present. Can be derived from S40S_SISOBUCKLC_PRESENT + or SIMOBUCK_PRESENT. */ +#define SRSS_BUCKCTL_PRESENT 1u +/* Low-current SISO buck core regulator is present. Only compatible with ULP + linear regulator system (ULPLINREG_PRESENT==1). */ +#define SRSS_S40S_SISOBUCKLC_PRESENT 1u +/* SIMO buck core regulator is present. Only compatible with ULP linear regulator + system (ULPLINREG_PRESENT==1). */ +#define SRSS_SIMOBUCK_PRESENT 0u +/* Precision ILO (PILO) is present */ +#define SRSS_PILO_PRESENT 0u +/* External Crystal Oscillator is present (high frequency) */ +#define SRSS_ECO_PRESENT 1u +/* System Buck-Boost is present */ +#define SRSS_SYSBB_PRESENT 0u +/* Number of clock paths. Must be > 0 */ +#define SRSS_NUM_CLKPATH 5u +/* Number of PLLs present. Must be <= NUM_CLKPATH */ +#define SRSS_NUM_PLL 1u +/* Number of HFCLK roots present. Must be > 0 */ +#define SRSS_NUM_HFROOT 5u +/* Number of PWR_HIB_DATA registers, should not be needed if BACKUP_PRESENT */ +#define SRSS_NUM_HIBDATA 1u +/* Backup domain is present (includes RTC and WCO) */ +#define SRSS_BACKUP_PRESENT 1u +/* Mask of HFCLK root clock supervisors (CSV). For each clock root i, bit[i] of + mask indicates presence of a CSV. */ +#define SRSS_MASK_HFCSV 0u +/* Clock supervisor is present on WCO. Must be 0 if BACKUP_PRESENT==0. */ +#define SRSS_WCOCSV_PRESENT 0u +/* Number of software watchdog timers. */ +#define SRSS_NUM_MCWDT 2u +/* Number of DSI inputs into clock muxes. This is used for logic optimization. */ +#define SRSS_NUM_DSI 0u +/* Alternate high-frequency clock is present. This is used for logic optimization. */ +#define SRSS_ALTHF_PRESENT 0u +/* Alternate low-frequency clock is present. This is used for logic optimization. */ +#define SRSS_ALTLF_PRESENT 0u +/* Use the hardened clkactfllmux block */ +#define SRSS_USE_HARD_CLKACTFLLMUX 1u +/* Number of clock paths, including direct paths in hardened clkactfllmux block + (Must be >= NUM_CLKPATH) */ +#define SRSS_HARD_CLKPATH 6u +/* Number of clock paths with muxes in hardened clkactfllmux block (Must be >= + NUM_PLL+1) */ +#define SRSS_HARD_CLKPATHMUX 6u +/* Number of HFCLKS present in hardened clkactfllmux block (Must be >= NUM_HFROOT) */ +#define SRSS_HARD_HFROOT 6u +/* ECO mux is present in hardened clkactfllmux block (Must be >= ECO_PRESENT) */ +#define SRSS_HARD_ECOMUX_PRESENT 1u +/* ALTHF mux is present in hardened clkactfllmux block (Must be >= ALTHF_PRESENT) */ +#define SRSS_HARD_ALTHFMUX_PRESENT 1u +/* SRSS version is at least SRSS_VER1P3. Set to 1 for new products. Set to 0 for + PSoC6ABLE2, PSoC6A2M. */ +#define SRSS_SRSS_VER1P3 1u +/* Backup memory is present (only used when BACKUP_PRESENT==1) */ +#define SRSS_BACKUP_BMEM_PRESENT 0u +/* Number of Backup registers to include (each is 32b). Only used when + BACKUP_PRESENT==1. */ +#define SRSS_BACKUP_NUM_BREG 16u +/* Number of counters per IP (1..32) */ +#define TCPWM0_CNT_NR 4u +/* Counter width (in number of bits) */ +#define TCPWM0_CNT_CNT_WIDTH 32u +/* Number of counters per IP (1..32) */ +#define TCPWM1_CNT_NR 8u +/* Counter width (in number of bits) */ +#define TCPWM1_CNT_CNT_WIDTH 16u /* MMIO Targets Defines */ #define CY_MMIO_CRYPTO_GROUP_NR 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/psoc6_04_config.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/psoc6_04_config.h index 5bdbba77b7..0a6f3cd8ab 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/psoc6_04_config.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/psoc6_04_config.h @@ -5,7 +5,7 @@ * PSoC6_04 device configuration header * * \note -* Generator version: 1.6.0.150 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -1162,7 +1162,6 @@ typedef enum #include "ip/cyip_smif.h" #include "ip/cyip_canfd.h" #include "ip/cyip_scb.h" -#include "ip/cyip_scb.h" #include "ip/cyip_ctbm_v2.h" #include "ip/cyip_ctdac_v2.h" #include "ip/cyip_sar_v2.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_device.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_device.h index b600245eaf..44dca6df2b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_device.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_device.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_device.h -* \version 2.10 +* \version 2.20 * * This file specifies the structure for core and peripheral block HW base * addresses, versions, and parameters. @@ -120,6 +120,7 @@ typedef struct uint8_t srssNumClkpath; uint8_t srssNumPll; uint8_t srssNumHfroot; + uint8_t srssIsPiloPresent; uint8_t periClockNr; uint8_t smifDeviceNr; uint8_t passSarChannels; @@ -220,6 +221,8 @@ void Cy_PDL_Init(const cy_stc_device_t * device); #define CY_SRSS_V1_3 (0x13U == cy_device->srssVersion) #define CY_SRSS_MFO_PRESENT (CY_SRSS_V1_3) +#define CY_SRSS_PILO_PRESENT (1U == cy_device->srssIsPiloPresent) + #define CY_SRSS_NUM_CLKPATH ((uint32_t)(cy_device->srssNumClkpath)) #define CY_SRSS_NUM_PLL ((uint32_t)(cy_device->srssNumPll)) #define CY_SRSS_NUM_HFROOT ((uint32_t)(cy_device->srssNumHfroot)) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_flash.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_flash.h index 740235c141..453cdd617f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_flash.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_flash.h @@ -258,7 +258,7 @@ * * 3.40 * Updated Cy_Flash_OperationStatus() to access protected registers. -* Added PSoC64 device support. +* Added PSoC 64 device support. * * * 3.30.4 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_lvd.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_lvd.h index 1f4ebb1765..222faf49e5 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_lvd.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_lvd.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_lvd.h -* \version 1.10.1 +* \version 1.20 * * The header file of the LVD driver. * @@ -99,9 +99,15 @@ * * * -* -* -* +* +* +* * * * @@ -156,7 +162,7 @@ extern "C" { #define CY_LVD_DRV_VERSION_MAJOR 1 /** The driver minor version */ -#define CY_LVD_DRV_VERSION_MINOR 10 +#define CY_LVD_DRV_VERSION_MINOR 20 /** The LVD driver identifier */ #define CY_LVD_ID (CY_PDL_DRV_ID(0x39U)) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_pra.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_pra.h index a4fbd0ae6a..a202a2e801 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_pra.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_pra.h @@ -27,15 +27,15 @@ * \addtogroup group_pra * \{ * The Protected Register Access (PRA) driver used to provice access to the -* protected registers to a non-secure application on PSoC64 devices. +* protected registers to a non-secure application on PSoC 64 devices. * * The PRA PDL driver is only intended for the PSoC 64 devices as it provides -* access only to the registers that have PSoC64 access restrictions. Refer to +* access only to the registers that have PSoC 64 access restrictions. Refer to * device technical reference manual (TRM) for the list of the protected * registers. * * The driver is not expected to be used directly, instead the PDL functions -* affected by PSoC64 access restrictions are updated to access registers with +* affected by PSoC 64 access restrictions are updated to access registers with * PRA API. * * \section group_pra_more_information More Information @@ -124,7 +124,7 @@ extern "C" { /** \cond INTERNAL */ -#define CYPRA_REG_INDEX_COUNT 16U +#define CY_PRA_REG_INDEX_COUNT (16U) #define CY_PRA_MSG_TYPE_REG32_GET (1U) #define CY_PRA_MSG_TYPE_REG32_CLR_SET (2U) @@ -134,7 +134,6 @@ extern "C" { #define CY_PRA_MSG_TYPE_SECURE_ONLY (6U) #define CY_PRA_MSG_TYPE_FUNC_POLICY (7U) - /* IPC */ #define CY_PRA_IPC_NOTIFY_INTR (0x1UL << CY_IPC_INTR_PRA) #define CY_PRA_IPC_CHAN_INTR (0x1UL << CY_IPC_CHAN_PRA) @@ -157,16 +156,12 @@ extern "C" { #define CY_PRA_INDX_SRSS_PWR_HIBERNATE (12U) #define CY_PRA_INDX_SRSS_CLK_MFO_CONFIG (13U) #define CY_PRA_INDX_SRSS_CLK_MF_SELECT (14U) +#define CY_PRA_INDX_FLASHC_FM_CTL_BOOKMARK (15U) /* Functions Index */ #define CY_PRA_FUNC_INIT_CYCFG_DEVICE (0U) -#define CY_PRA_PM_FUNC_HIBERNATE (2U) -#define CY_PRA_PM_FUNC_CM4_DP_FLAG_SET (3U) -#define CY_PRA_PM_FUNC_LDO_SET_VOLTAGE (4U) -#define CY_PRA_PM_FUNC_BUCK_ENABLE (5U) -#define CY_PRA_PM_FUNC_SET_MIN_CURRENT (6U) -#define CY_PRA_PM_FUNC_SET_NORMAL_CURRENT (7U) + #define CY_PRA_CLK_FUNC_ECO_DISABLE (8U) #define CY_PRA_CLK_FUNC_FLL_DISABLE (9U) #define CY_PRA_CLK_FUNC_PLL_DISABLE (10U) @@ -207,6 +202,16 @@ extern "C" { #define CY_PRA_CLK_FUNC_DS_AFTER_TRANSITION (45U) #define CY_PRA_CLK_FUNC_EXT_CLK_SET_FREQUENCY (46U) +#define CY_PRA_PM_FUNC_HIBERNATE (102U) +#define CY_PRA_PM_FUNC_CM4_DP_FLAG_SET (103U) +#define CY_PRA_PM_FUNC_LDO_SET_VOLTAGE (104U) +#define CY_PRA_PM_FUNC_BUCK_ENABLE (105U) +#define CY_PRA_PM_FUNC_SET_MIN_CURRENT (106U) +#define CY_PRA_PM_FUNC_SET_NORMAL_CURRENT (107U) +#define CY_PRA_PM_FUNC_BUCK_ENABLE_VOLTAGE2 (108U) +#define CY_PRA_PM_FUNC_BUCK_DISABLE_VOLTAGE2 (109U) +#define CY_PRA_PM_FUNC_BUCK_VOLTAGE2_HW_CTRL (110U) +#define CY_PRA_PM_FUNC_BUCK_SET_VOLTAGE2 (111U) /** Driver major version */ #define CY_PRA_DRV_VERSION_MAJOR 1 @@ -343,7 +348,7 @@ typedef enum typedef struct { volatile uint32_t * addr; /**< Register address */ - uint32_t writeMask; /**< Write mask */ + uint32_t writeMask; /**< Write mask. Zero grants access, one - no access */ } cy_stc_pra_reg_policy_t; /** Message used for communication */ @@ -358,7 +363,7 @@ typedef struct /** \} group_pra_data_structures */ /** \cond INTERNAL */ -extern cy_stc_pra_reg_policy_t regIndexToAddr[CYPRA_REG_INDEX_COUNT]; +extern cy_stc_pra_reg_policy_t regIndexToAddr[CY_PRA_REG_INDEX_COUNT]; /** \endcond */ @@ -370,9 +375,9 @@ extern cy_stc_pra_reg_policy_t regIndexToAddr[CYPRA_REG_INDEX_COUNT]; * \addtogroup group_pra_functions * \{ */ +void Cy_PRA_Init(void); #if (CY_CPU_CORTEX_M0P) || defined (CY_DOXYGEN) - void Cy_PRA_Init(void); void Cy_PRA_CloseSrssMain2(void); void Cy_PRA_OpenSrssMain2(void); #endif /* (CY_CPU_CORTEX_M0P) */ @@ -435,7 +440,7 @@ extern cy_stc_pra_reg_policy_t regIndexToAddr[CYPRA_REG_INDEX_COUNT]; /******************************************************************************* -* Macro Name: CY_PRA_CM0_WAKEUP(regIndex) +* Macro Name: CY_PRA_CM0_WAKEUP() ****************************************************************************//** * * A simple request to wake up Cortex-M0+ core. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_common.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_common.h index f1a4b524f5..ff67c0e5d9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_common.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_common.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_scb_common.h -* \version 2.40.2 +* \version 2.50 * * Provides common API declarations of the SCB driver. * @@ -137,6 +137,12 @@ *
VersionChangesReason of Change
1.10.1Minor documentation updates.Documentation enhancement.1.20 + Updated the following functions for the PSoC 64 devices: + \ref Cy_LVD_Enable, \ref Cy_LVD_Disable, \ref Cy_LVD_SetThreshold, + \ref Cy_LVD_ClearInterrupt, \ref Cy_LVD_SetInterrupt, + \ref Cy_LVD_SetInterruptMask, \ref Cy_LVD_ClearInterruptMask, and + \ref Cy_LVD_SetInterruptConfig. + Added PSoC 64 device support.
1.10
* * +* +* +* +* +* * * * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_ezi2c.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_ezi2c.h index acd40061c3..3f1607992b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_ezi2c.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_ezi2c.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_scb_ezi2c.h -* \version 2.40.2 +* \version 2.50 * * Provides EZI2C API declarations of the SCB driver. * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_i2c.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_i2c.h index d2772a3d43..bf4d0512d1 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_i2c.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_i2c.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_scb_i2c.h -* \version 2.40.2 +* \version 2.50 * * Provides I2C API declarations of the SCB driver. * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_spi.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_spi.h index 16e68e7b51..29cc50a4a2 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_spi.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_spi.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_scb_spi.h -* \version 2.40.2 +* \version 2.50 * * Provides SPI API declarations of the SCB driver. * @@ -954,7 +954,7 @@ __STATIC_INLINE void Cy_SCB_SPI_SetActiveSlaveSelectPolarity(CySCB_Type *base, CY_ASSERT_L3(CY_SCB_SPI_IS_SLAVE_SEL_VALID(slaveSelect)); CY_ASSERT_L3(CY_SCB_SPI_IS_POLARITY_VALID (polarity)); - if (CY_SCB_SPI_ACTIVE_HIGH != polarity) + if (CY_SCB_SPI_ACTIVE_HIGH == polarity) { SCB_SPI_CTRL(base) |= (uint32_t) mask; } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_uart.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_uart.h index 1b1b8aef10..9f54f412a1 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_uart.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_uart.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_scb_uart.h -* \version 2.40.2 +* \version 2.50 * * Provides UART API declarations of the SCB driver. * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_syslib.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_syslib.h index 9d420c048b..c61aad00e1 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_syslib.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_syslib.h @@ -154,10 +154,10 @@ * * * -* +* * * * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_syspm.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_syspm.h index 51c547b378..01b483f9a8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_syspm.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_syspm.h @@ -726,7 +726,7 @@ * * * * * -* -* +* * * * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_wdt.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_wdt.h index bd6fb8ce5d..2586e2493b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_wdt.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_wdt.h @@ -192,9 +192,9 @@ * * * -* -* +* * * * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_device.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_device.c index a3358e3dde..7d9e3a2748 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_device.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_device.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_device.c -* \version 2.10 +* \version 2.20 * * This file provides the definitions for core and peripheral block HW base * addresses, versions, and parameters. @@ -69,6 +69,7 @@ const cy_stc_device_t cy_deviceIpBlockCfgPSoC6_01 = /* srssNumClkpath */ 5U, /* srssNumPll */ 1U, /* srssNumHfroot */ 5U, + /* srssIsPiloPresent */ 1U, /* periClockNr */ 59U, /* smifDeviceNr */ 4U, /* passSarChannels */ 16U, @@ -177,6 +178,7 @@ const cy_stc_device_t cy_deviceIpBlockCfgPSoC6_02 = /* srssNumClkpath */ 6U, /* srssNumPll */ 2U, /* srssNumHfroot */ 6U, + /* srssIsPiloPresent */ 0U, /* periClockNr */ 54U, /* smifDeviceNr */ 4U, /* passSarChannels */ 16U, @@ -284,6 +286,7 @@ const cy_stc_device_t cy_deviceIpBlockCfgPSoC6_03 = /* srssNumClkpath */ 5U, /* srssNumPll */ 1U, /* srssNumHfroot */ 5U, + /* srssIsPiloPresent */ 0U, /* periClockNr */ 28U, /* smifDeviceNr */ 3U, /* passSarChannels */ 16U, @@ -391,6 +394,7 @@ const cy_stc_device_t cy_deviceIpBlockCfgPSoC6_04 = /* srssNumClkpath */ 5U, /* srssNumPll */ 1U, /* srssNumHfroot */ 4U, + /* srssIsPiloPresent */ 0U, /* periClockNr */ 28U, /* smifDeviceNr */ 3U, /* passSarChannels */ 16U, diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_flash.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_flash.c index f495db27ba..013ddea6b1 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_flash.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_flash.c @@ -272,7 +272,9 @@ static volatile cy_stc_flash_context_t flashContext; #endif static void Cy_Flash_NotifyHandler(uint32_t * msgPtr) { + #if !((CY_CPU_CORTEX_M0P) && (defined(CY_DEVICE_SECURE))) uint32_t intr; + #endif /* !((CY_CPU_CORTEX_M0P) && (defined(CY_DEVICE_SECURE))) */ static uint32_t semaIndex; static uint32_t semaMask; static volatile uint32_t *semaPtr; @@ -282,7 +284,9 @@ static volatile cy_stc_flash_context_t flashContext; if (CY_FLASH_ENTER_WAIT_LOOP == ipcMsgPtr->pktType) { + #if !((CY_CPU_CORTEX_M0P) && (defined(CY_DEVICE_SECURE))) intr = Cy_SysLib_EnterCriticalSection(); + #endif /* !((CY_CPU_CORTEX_M0P) && (defined(CY_DEVICE_SECURE))) */ /* Get pointer to structure */ semaStruct = (cy_stc_ipc_sema_t *)Cy_IPC_Drv_ReadDataValue(Cy_IPC_Drv_GetIpcBaseAddress(CY_IPC_CHAN_SEMA)); @@ -300,7 +304,9 @@ static volatile cy_stc_flash_context_t flashContext; { } + #if !((CY_CPU_CORTEX_M0P) && (defined(CY_DEVICE_SECURE))) Cy_SysLib_ExitCriticalSection(intr); + #endif /* !((CY_CPU_CORTEX_M0P) && (defined(CY_DEVICE_SECURE))) */ } } CY_RAMFUNC_END @@ -578,7 +584,11 @@ CY_RAMFUNC_END IPC_STRUCT_Type * locIpcBase = Cy_IPC_Drv_GetIpcBaseAddress(CY_IPC_CHAN_CYPIPE_EP0); uint32_t bookmark; - bookmark = FLASHC_FM_CTL_BOOKMARK & 0xffffUL; + #if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + bookmark = CY_PRA_REG32_GET(CY_PRA_INDX_FLASHC_FM_CTL_BOOKMARK) & 0xffffUL; + #else + bookmark = FLASHC_FM_CTL_BOOKMARK & 0xffffUL; + #endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ uint32_t intr = Cy_SysLib_EnterCriticalSection(); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_lvd.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_lvd.c index 1cd9d47db4..eea207e846 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_lvd.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_lvd.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_lvd.c -* \version 1.10.1 +* \version 1.20 * * The source code file for the LVD driver. * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_pra.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_pra.c index 23a6cbe6b5..a98d12e20a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_pra.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_pra.c @@ -33,9 +33,14 @@ #if defined (CY_DEVICE_SECURE) || defined (CY_DOXYGEN) #define CY_PRA_REG_POLICY_WRITE_ALL (0x00000000UL) +#define CY_PRA_REG_POLICY_WRITE_NONE (0xFFFFFFFFUL) /* Table to get register/function address based on its index */ -cy_stc_pra_reg_policy_t regIndexToAddr[CYPRA_REG_INDEX_COUNT]; +cy_stc_pra_reg_policy_t regIndexToAddr[CY_PRA_REG_INDEX_COUNT]; + +#if (CY_CPU_CORTEX_M4) + static IPC_STRUCT_Type *ipcPraBase = NULL; +#endif /* (CY_CPU_CORTEX_M0P) */ #if (CY_CPU_CORTEX_M0P) || defined (CY_DOXYGEN) @@ -45,10 +50,10 @@ cy_stc_pra_reg_policy_t regIndexToAddr[CYPRA_REG_INDEX_COUNT]; static void Cy_PRA_PmCm4DpFlagSet(void); static cy_en_pra_status_t Cy_PRA_ClkDSBeforeTransition(void); static cy_en_pra_status_t Cy_PRA_ClkDSAfterTransition(void); + static bool Cy_PRA_RegAccessRangeValid(uint16_t index); #endif /* (CY_CPU_CORTEX_M0P) || defined (CY_DOXYGEN) */ -#if (CY_CPU_CORTEX_M0P) || defined (CY_DOXYGEN) /******************************************************************************* * Function Name: Cy_PRA_Init ****************************************************************************//** @@ -58,7 +63,9 @@ cy_stc_pra_reg_policy_t regIndexToAddr[CYPRA_REG_INDEX_COUNT]; *******************************************************************************/ void Cy_PRA_Init(void) { - for (uint32_t i = 0UL; i < (sizeof(regIndexToAddr)/sizeof(regIndexToAddr[0U])); i++) + +#if (CY_CPU_CORTEX_M0P) + for (uint32_t i = 0UL; i < CY_PRA_REG_INDEX_COUNT; i++) { regIndexToAddr[i].writeMask = CY_PRA_REG_POLICY_WRITE_ALL; } @@ -82,6 +89,8 @@ void Cy_PRA_Init(void) SRSS_PWR_HIBERNATE_MASK_HIBWDT_Msk); regIndexToAddr[CY_PRA_INDX_SRSS_CLK_MFO_CONFIG].addr = &SRSS_CLK_MFO_CONFIG; regIndexToAddr[CY_PRA_INDX_SRSS_CLK_MF_SELECT].addr = &SRSS_CLK_MF_SELECT; + regIndexToAddr[CY_PRA_INDX_FLASHC_FM_CTL_BOOKMARK].addr = &FLASHC_FM_CTL_BOOKMARK; + regIndexToAddr[CY_PRA_INDX_FLASHC_FM_CTL_BOOKMARK].writeMask= CY_PRA_REG_POLICY_WRITE_NONE; /* Configure the IPC interrupt handler. */ Cy_IPC_Drv_SetInterruptMask(Cy_IPC_Drv_GetIntrBaseAddr(CY_IPC_INTR_PRA), CY_PRA_IPC_NONE_INTR, CY_PRA_IPC_CHAN_INTR); @@ -92,9 +101,17 @@ void Cy_PRA_Init(void) }; (void) Cy_SysInt_Init(&intr, &Cy_PRA_Handler); NVIC_EnableIRQ(intr.intrSrc); +#else + + /* Need to get this address in RAM, because there are use cases + * where this address is used but flash is not accesible + */ + ipcPraBase = Cy_IPC_Drv_GetIpcBaseAddress(CY_IPC_CHAN_PRA); +#endif /* (CY_CPU_CORTEX_M0P) */ } +#if (CY_CPU_CORTEX_M0P) || defined (CY_DOXYGEN) /******************************************************************************* * Function Name: Cy_PRA_Handler ****************************************************************************//** @@ -135,31 +152,24 @@ static void Cy_PRA_ProcessCmd(cy_stc_pra_msg_t *message) static uint32_t structInit = CY_PRA_STRUCT_NOT_INITIALIZED; static cy_stc_pra_system_config_t structCpy = {0UL}; - if ((CY_PRA_MSG_TYPE_REG32_GET == message->praCommand) || - (CY_PRA_MSG_TYPE_REG32_CLR_SET == message->praCommand) || - (CY_PRA_MSG_TYPE_REG32_SET == message->praCommand)) - { - /* Check if access is within array range */ - if ((message->praIndex) > (sizeof(regIndexToAddr)/sizeof(regIndexToAddr[0U]))) - { - message->praStatus = CY_PRA_STATUS_ACCESS_DENIED; - } + CY_ASSERT_L1(NULL != message); - /* Some registers do not exist for some families */ - if (regIndexToAddr[message->praIndex].addr == (const volatile uint32_t *) 0U) - { - message->praStatus = CY_PRA_STATUS_ACCESS_DENIED; - } - } switch (message->praCommand) { case CY_PRA_MSG_TYPE_REG32_CLR_SET: - if (0U == (message->praData2 & regIndexToAddr[message->praIndex].writeMask)) + /* Report error if any of the following conditions is false: + * - New value (message->praData2) has zeros in the write-protected fields + * - Register index is within the valid range + */ + if ((0U == (message->praData2 & regIndexToAddr[message->praIndex].writeMask)) && + (CY_PRA_REG_POLICY_WRITE_NONE != regIndexToAddr[message->praIndex].writeMask) && + (Cy_PRA_RegAccessRangeValid(message->praIndex))) { uint32_t tmp; tmp = CY_GET_REG32(regIndexToAddr[message->praIndex].addr); + tmp &= (message->praData1 | regIndexToAddr[message->praIndex].writeMask); tmp |= message->praData2; CY_SET_REG32(regIndexToAddr[message->praIndex].addr, tmp); @@ -172,9 +182,26 @@ static void Cy_PRA_ProcessCmd(cy_stc_pra_msg_t *message) break; case CY_PRA_MSG_TYPE_REG32_SET: - if (0U == (message->praData1 & regIndexToAddr[message->praIndex].writeMask)) + /* Report error if any of the following conditions is false: + * - New value (message->praData1) has zeros in the write-protected fields + * - Register index is within the valid range + */ + if ((0U == (message->praData1 & regIndexToAddr[message->praIndex].writeMask)) && + (CY_PRA_REG_POLICY_WRITE_NONE != regIndexToAddr[message->praIndex].writeMask) && + (Cy_PRA_RegAccessRangeValid(message->praIndex))) { - CY_SET_REG32(regIndexToAddr[message->praIndex].addr, message->praData1); + uint32_t tmp; + + tmp = CY_GET_REG32(regIndexToAddr[message->praIndex].addr); + + /* Clear bits allowed to write */ + tmp &= regIndexToAddr[message->praIndex].writeMask; + + /* Set allowed bits based on new value. + Write-protected fields have zeros in the new value, so no additional checks needed + */ + tmp |= message->praData1; + CY_SET_REG32(regIndexToAddr[message->praIndex].addr, tmp); message->praStatus = CY_PRA_STATUS_SUCCESS; } else @@ -184,8 +211,15 @@ static void Cy_PRA_ProcessCmd(cy_stc_pra_msg_t *message) break; case CY_PRA_MSG_TYPE_REG32_GET: - message->praData1 = CY_GET_REG32(regIndexToAddr[message->praIndex].addr); - message->praStatus = CY_PRA_STATUS_SUCCESS; + if (Cy_PRA_RegAccessRangeValid(message->praIndex)) + { + message->praData1 = CY_GET_REG32(regIndexToAddr[message->praIndex].addr); + message->praStatus = CY_PRA_STATUS_SUCCESS; + } + else + { + message->praStatus = CY_PRA_STATUS_ACCESS_DENIED; + } break; case CY_PRA_MSG_TYPE_CM0_WAKEUP: @@ -230,6 +264,34 @@ static void Cy_PRA_ProcessCmd(cy_stc_pra_msg_t *message) message->praStatus = Cy_PRA_ClkDSAfterTransition(); break; + case CY_PRA_PM_FUNC_BUCK_ENABLE_VOLTAGE2: + Cy_SysPm_BuckEnableVoltage2(); + message->praStatus = CY_PRA_STATUS_SUCCESS; + break; + + case CY_PRA_PM_FUNC_BUCK_DISABLE_VOLTAGE2: + Cy_SysPm_BuckDisableVoltage2(); + message->praStatus = CY_PRA_STATUS_SUCCESS; + break; + + case CY_PRA_PM_FUNC_BUCK_VOLTAGE2_HW_CTRL: + Cy_SysPm_BuckSetVoltage2HwControl((bool) message->praData1); + message->praStatus = CY_PRA_STATUS_SUCCESS; + break; + + case CY_PRA_PM_FUNC_BUCK_SET_VOLTAGE2: + if (CY_SYSPM_IS_BUCK_VOLTAGE2_VALID(((cy_stc_pra_voltage2_t *) message->praData1)->praVoltage)) + { + Cy_SysPm_BuckSetVoltage2(((cy_stc_pra_voltage2_t *) message->praData1)->praVoltage, + ((cy_stc_pra_voltage2_t *) message->praData1)->praWaitToSettle); + message->praStatus = CY_PRA_STATUS_SUCCESS; + } + else + { + message->praStatus = CY_PRA_STATUS_INVALID_PARAM; + } + break; + default: message->praStatus = CY_PRA_STATUS_ACCESS_DENIED; break; @@ -1465,55 +1527,72 @@ static void Cy_PRA_ProcessCmd(cy_stc_pra_msg_t *message) * value is returned. * *******************************************************************************/ -cy_en_pra_status_t Cy_PRA_SendCmd(uint16_t cmd, uint16_t regIndex, uint32_t clearMask, uint32_t setMask) -{ - cy_en_pra_status_t status; - CY_ALIGN(4UL) cy_stc_pra_msg_t ipcMsg; - IPC_STRUCT_Type *ipcPraBase = Cy_IPC_Drv_GetIpcBaseAddress(CY_IPC_CHAN_PRA); - uint32_t interruptState; +#if defined(CY_DEVICE_PSOC6ABLE2) - ipcMsg.praCommand = cmd; - ipcMsg.praStatus = CY_PRA_STATUS_REQUEST_SENT; - ipcMsg.praIndex = regIndex; - ipcMsg.praData1 = clearMask; - ipcMsg.praData2 = setMask; - - interruptState = Cy_SysLib_EnterCriticalSection(); - - while (CY_IPC_DRV_SUCCESS != Cy_IPC_Drv_SendMsgWord(ipcPraBase, CY_PRA_IPC_NOTIFY_INTR, (uint32_t)&ipcMsg)) + CY_RAMFUNC_BEGIN + #if !defined (__ICCARM__) + CY_NOINLINE + #endif +#endif /* defined(CY_DEVICE_PSOC6ABLE2) */ + cy_en_pra_status_t Cy_PRA_SendCmd(uint16_t cmd, uint16_t regIndex, uint32_t clearMask, uint32_t setMask) { - /* Try to acquire the PRA IPC structure and pass the arguments */ + CY_ASSERT_L1(NULL != ipcPraBase); + + cy_en_pra_status_t status; + CY_ALIGN(4UL) cy_stc_pra_msg_t ipcMsg; + uint32_t interruptState; + + ipcMsg.praCommand = cmd; + ipcMsg.praStatus = CY_PRA_STATUS_REQUEST_SENT; + ipcMsg.praIndex = regIndex; + ipcMsg.praData1 = clearMask; + ipcMsg.praData2 = setMask; + + interruptState = Cy_SysLib_EnterCriticalSection(); + + while (0U == _FLD2VAL(IPC_STRUCT_ACQUIRE_SUCCESS, REG_IPC_STRUCT_ACQUIRE(ipcPraBase))) + { + /* Wait until the PRA IPC structure is acquired */ + } + + /* Send the message */ + REG_IPC_STRUCT_DATA(ipcPraBase) = (uint32_t) &ipcMsg; + + /* Generate an acquire notification event by PRA IPC interrupt structure */ + REG_IPC_STRUCT_NOTIFY(ipcPraBase) = _VAL2FLD(IPC_STRUCT_NOTIFY_INTR_NOTIFY, CY_PRA_IPC_NOTIFY_INTR); + + while (0U != _FLD2VAL(IPC_STRUCT_ACQUIRE_SUCCESS, REG_IPC_STRUCT_LOCK_STATUS(ipcPraBase))) + { + /* Wait until the PRA IPC structure is released */ + } + + Cy_SysLib_ExitCriticalSection(interruptState); + + /* Cortex-M0+ has updated ipcMsg variable */ + + status = (cy_en_pra_status_t) ipcMsg.praStatus; + + if (CY_PRA_STATUS_ACCESS_DENIED == status) + { + CY_HALT(); + } + + if (CY_PRA_MSG_TYPE_SYS_CFG_FUNC == ipcMsg.praCommand) + { + SystemCoreClockUpdate(); + } + + if (CY_PRA_MSG_TYPE_REG32_GET == ipcMsg.praCommand) + { + status = (cy_en_pra_status_t)ipcMsg.praData1; + } + + return status; } +#if defined(CY_DEVICE_PSOC6ABLE2) + CY_RAMFUNC_END +#endif /* defined(CY_DEVICE_PSOC6ABLE2) */ - /* Checks whether the IPC structure is not locked */ - while (Cy_IPC_Drv_IsLockAcquired(ipcPraBase)) - { - /* Polls whether the IPC is released */ - } - - Cy_SysLib_ExitCriticalSection(interruptState); - - /* Cortex-M0+ has updated ipcMsg variable */ - - status = (cy_en_pra_status_t) ipcMsg.praStatus; - - if (CY_PRA_STATUS_ACCESS_DENIED == status) - { - CY_HALT(); - } - - if (CY_PRA_MSG_TYPE_SYS_CFG_FUNC == ipcMsg.praCommand) - { - SystemCoreClockUpdate(); - } - - if (CY_PRA_MSG_TYPE_REG32_GET == ipcMsg.praCommand) - { - status = (cy_en_pra_status_t)ipcMsg.praData1; - } - - return status; -} #endif /* (CY_CPU_CORTEX_M4) */ @@ -1627,6 +1706,7 @@ static void Cy_PRA_PmCm4DpFlagSet(void) static uint16_t changedSourcePaths = CY_PRA_DEFAULT_ZERO; static uint16_t pllAutoModes = CY_PRA_DEFAULT_ZERO; + /******************************************************************************* * Function Name: Cy_PRA_ClkDSBeforeTransition ****************************************************************************//** @@ -1790,6 +1870,37 @@ static cy_en_pra_status_t Cy_PRA_ClkDSAfterTransition(void) } +/******************************************************************************* +* Function Name: Cy_PRA_RegAccessRangeValid +****************************************************************************//** +* +* Check if access is within valid range and access address is non-zero. +* +* \param index Index of the accessed register. +* +* \return Return true for valid access. +* +*******************************************************************************/ +static bool Cy_PRA_RegAccessRangeValid(uint16_t index) +{ + bool accessValid = true; + + /* Check if access is within array range */ + if (index >= CY_PRA_REG_INDEX_COUNT) + { + accessValid = false; + } + + /* Some registers do not exist for some families */ + if (regIndexToAddr[index].addr == (const volatile uint32_t *) 0U) + { + accessValid = false; + } + + return accessValid; +} + + #endif /* (CY_CPU_CORTEX_M0P) */ #endif /* (CY_DEVICE_SECURE) */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_pra_cfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_pra_cfg.c index 4ca026a4e4..140a3d2d62 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_pra_cfg.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_pra_cfg.c @@ -50,6 +50,7 @@ __STATIC_INLINE void Cy_PRA_ExtClkInit( const cy_stc_pra_system_config_t *devCon __STATIC_INLINE cy_en_pra_status_t Cy_PRA_EcoInit(const cy_stc_pra_system_config_t *devConfig); #if defined(CY_IP_MXBLESS) __STATIC_INLINE cy_en_pra_status_t Cy_PRA_AltHfInit(const cy_stc_pra_system_config_t *devConfig); +__STATIC_INLINE void Cy_PRA_AltHfReset(const cy_stc_pra_system_config_t *devConfig); static cy_en_pra_status_t Cy_PRA_ValidateAltHf(const cy_stc_pra_system_config_t *devConfig); #endif __STATIC_INLINE void Cy_PRA_PiloInit(void); @@ -412,6 +413,29 @@ __STATIC_INLINE cy_en_pra_status_t Cy_PRA_AltHfInit(const cy_stc_pra_system_conf return CY_PRA_STATUS_SUCCESS; } + +/******************************************************************************* +* Function Name: Cy_PRA_AltHfReset +****************************************************************************//** +* +* Reset Alternative High-Frequency Clock +* +* \param devConfig +* +*******************************************************************************/ +__STATIC_INLINE void Cy_PRA_AltHfReset(const cy_stc_pra_system_config_t *devConfig) +{ + static bool firstEntryAfterReset = true; + + /* Cy_BLE_EcoReset is called when this function is called firsttime + * after Reset or ECO state changed from ENABLE to DISABLE at runtime */ + if (firstEntryAfterReset || (Cy_BLE_EcoIsEnabled() && !(devConfig->clkAltHfEnable))) + { + Cy_BLE_EcoReset(); + firstEntryAfterReset = false; + } +} + #endif /* CY_IP_MXBLESS */ @@ -605,7 +629,7 @@ __STATIC_INLINE cy_en_pra_status_t Cy_PRA_PowerInit(const cy_stc_pra_system_conf *******************************************************************************/ static uint32_t Cy_PRA_GetInputPathMuxFrq(cy_en_clkpath_in_sources_t pathMuxSrc, const cy_stc_pra_system_config_t *devConfig) { - uint32_t srcFreq; /* Hz */ + uint32_t srcFreq = CY_PRA_DEFAULT_SRC_FREQUENCY; /* Hz */ switch (pathMuxSrc) { @@ -641,7 +665,10 @@ static uint32_t Cy_PRA_GetInputPathMuxFrq(cy_en_clkpath_in_sources_t pathMuxSrc, break; case CY_SYSCLK_CLKPATH_IN_PILO: { - srcFreq = CY_PRA_PILO_SRC_FREQUENCY; /* PILO Freq = 32.768 KHz */ + if(CY_SRSS_PILO_PRESENT) + { + srcFreq = CY_PRA_PILO_SRC_FREQUENCY; /* PILO Freq = 32.768 KHz */ + } } break; default: @@ -811,7 +838,7 @@ static uint32_t Cy_PRA_GetClkLfFreq(const cy_stc_pra_system_config_t *devConfig) break; case CY_SYSCLK_CLKLF_IN_PILO: { - if (devConfig->piloEnable) + if ((devConfig->piloEnable) && (CY_SRSS_PILO_PRESENT)) { freq = CY_PRA_PILO_SRC_FREQUENCY; } @@ -1459,7 +1486,7 @@ static cy_en_pra_status_t Cy_PRA_ValidateClkLf(const cy_stc_pra_system_config_t break; case CY_SYSCLK_CLKLF_IN_PILO: { - (devConfig->piloEnable) ? (retStatus = CY_PRA_STATUS_SUCCESS) : (retStatus = CY_PRA_STATUS_INVALID_PARAM_CLKLF); + ((devConfig->piloEnable) && (CY_SRSS_PILO_PRESENT)) ? (retStatus = CY_PRA_STATUS_SUCCESS) : (retStatus = CY_PRA_STATUS_INVALID_PARAM_CLKLF); } break; default: @@ -1526,7 +1553,7 @@ static cy_en_pra_status_t Cy_PRA_ValidateClkPathMux(cy_en_clkpath_in_sources_t p break; case CY_SYSCLK_CLKPATH_IN_PILO: { - (devConfig->piloEnable) ? (status = CY_PRA_STATUS_SUCCESS) : (status = CY_PRA_STATUS_INVALID_PARAM); + ((devConfig->piloEnable) && (CY_SRSS_PILO_PRESENT)) ? (status = CY_PRA_STATUS_SUCCESS) : (status = CY_PRA_STATUS_INVALID_PARAM); } break; default: @@ -1901,6 +1928,10 @@ static cy_en_pra_status_t Cy_PRA_ValidateClkPump(const cy_stc_pra_system_config_ return CY_PRA_STATUS_INVALID_PARAM_CLKPUMP; } } + else + { + status = CY_PRA_STATUS_INVALID_PARAM_CLKPUMP; + } } return status; @@ -2608,6 +2639,7 @@ cy_en_pra_status_t Cy_PRA_SystemConfig(const cy_stc_pra_system_config_t *devConf if ((CY_SRSS_NUM_PLL >= CY_PRA_CLKPLL_1) && (!devConfig->pll0Enable)) { + SystemCoreClockUpdate(); sysClkStatus = Cy_SysClk_PllDisable(CY_PRA_CLKPLL_1); } @@ -2618,6 +2650,7 @@ cy_en_pra_status_t Cy_PRA_SystemConfig(const cy_stc_pra_system_config_t *devConf if ((CY_SRSS_NUM_PLL >= CY_PRA_CLKPLL_2) && (!devConfig->pll1Enable)) { + SystemCoreClockUpdate(); sysClkStatus = Cy_SysClk_PllDisable(CY_PRA_CLKPLL_2); } @@ -2665,22 +2698,28 @@ cy_en_pra_status_t Cy_PRA_SystemConfig(const cy_stc_pra_system_config_t *devConf return CY_PRA_STATUS_ERROR_PROCESSING_CLKHF0; } } + #ifdef CY_IP_MXBLESS - (void)Cy_BLE_EcoReset(); + Cy_PRA_AltHfReset(devConfig); #endif - /* Enable all source clocks */ - if (devConfig->piloEnable) + if(CY_SRSS_PILO_PRESENT) { - Cy_PRA_PiloInit(); - } - else - { - Cy_SysClk_PiloDisable(); + /* Enable all source clocks */ + if (devConfig->piloEnable) + { + SystemCoreClockUpdate(); + Cy_PRA_PiloInit(); + } + else + { + Cy_SysClk_PiloDisable(); + } } if (devConfig->wcoEnable) { + SystemCoreClockUpdate(); status = Cy_PRA_WcoInit(devConfig); if (CY_PRA_STATUS_SUCCESS != status) { @@ -2703,6 +2742,7 @@ cy_en_pra_status_t Cy_PRA_SystemConfig(const cy_stc_pra_system_config_t *devConf #if defined(CY_IP_MXBLESS) if (devConfig->clkAltHfEnable) { + SystemCoreClockUpdate(); status = Cy_PRA_AltHfInit(devConfig); if (CY_PRA_STATUS_SUCCESS != status) { @@ -2715,6 +2755,7 @@ cy_en_pra_status_t Cy_PRA_SystemConfig(const cy_stc_pra_system_config_t *devConf { if (devConfig->ecoEnable) { + SystemCoreClockUpdate(); status = Cy_PRA_EcoInit(devConfig); if (CY_PRA_STATUS_SUCCESS != status) { @@ -2820,6 +2861,7 @@ cy_en_pra_status_t Cy_PRA_SystemConfig(const cy_stc_pra_system_config_t *devConf if ((!Cy_SysClk_FllIsEnabled()) && (devConfig->fllEnable)) { + SystemCoreClockUpdate(); status = Cy_PRA_FllInit(devConfig); if (CY_PRA_STATUS_SUCCESS != status) { @@ -2869,6 +2911,7 @@ cy_en_pra_status_t Cy_PRA_SystemConfig(const cy_stc_pra_system_config_t *devConf .outputMode = devConfig->pll0OutputMode, }; + SystemCoreClockUpdate(); status = Cy_PRA_PllInit(CY_PRA_CLKPLL_1, &pll0Config); if (CY_PRA_STATUS_SUCCESS != status) { @@ -2890,6 +2933,7 @@ cy_en_pra_status_t Cy_PRA_SystemConfig(const cy_stc_pra_system_config_t *devConf .outputMode = devConfig->pll1OutputMode, }; + SystemCoreClockUpdate(); status = Cy_PRA_PllInit(CY_PRA_CLKPLL_2, &pll1Config); if (CY_PRA_STATUS_SUCCESS != status) { diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_common.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_common.c index bf74f482ca..f1021185b5 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_common.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_common.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_scb_common.c -* \version 2.40.2 +* \version 2.50 * * Provides common API implementation of the SCB driver. * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_ezi2c.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_ezi2c.c index 6ab97776af..03c9d7ab56 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_ezi2c.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_ezi2c.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_scb_ezi2c.c -* \version 2.40.2 +* \version 2.50 * * Provides EZI2C API implementation of the SCB driver. * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_i2c.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_i2c.c index ae2408cb69..206cdbbce7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_i2c.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_i2c.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_scb_i2c.c -* \version 2.40.2 +* \version 2.50 * * Provides I2C API implementation of the SCB driver. * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_spi.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_spi.c index 0c2a68b708..4203bc95c0 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_spi.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_spi.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_scb_spi.c -* \version 2.40.2 +* \version 2.50 * * Provides SPI API implementation of the SCB driver. * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_uart.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_uart.c index 9203096260..0603780a80 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_uart.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_uart.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_scb_uart.c -* \version 2.40.2 +* \version 2.50 * * Provides UART API implementation of the SCB driver. * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_syspm.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_syspm.c index 1163a2f945..495e164edc 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_syspm.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_syspm.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_syspm.c -* \version 5.0 +* \version 5.10 * * This driver provides the source code for API power management. * @@ -26,10 +26,10 @@ #include "cy_ipc_sema.h" #include "cy_ipc_pipe.h" #include "cy_prot.h" -#if defined(CY_DEVICE_SECURE) - #include "cy_pra.h" -#endif /* defined(CY_DEVICE_SECURE) */ +#if ((CY_CPU_CORTEX_M0P) && (defined(CY_DEVICE_SECURE))) + #include "cy_pra_cfg.h" +#endif /* #if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ /******************************************************************************* * Internal Functions @@ -1964,7 +1964,7 @@ cy_en_syspm_status_t Cy_SysPm_BuckEnable(cy_en_syspm_buck_voltage1_t voltage) * \snippet syspm/snippet/main.c snippet_Cy_SysPm_VoltageRegulator * * \sideeffect -* For PSoC64 series devices Cy_SysPm_BuckSetVoltage1() has the same functional +* For PSoC 64 series devices Cy_SysPm_BuckSetVoltage1() has the same functional * behavior as \ref Cy_SysPm_BuckEnable() function. * *******************************************************************************/ @@ -2097,7 +2097,6 @@ bool Cy_SysPm_BuckIsOutputEnabled(cy_en_syspm_buck_out_t output) } -#if !((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) /******************************************************************************* * Function Name: Cy_SysPm_BuckEnableVoltage2 ****************************************************************************//** @@ -2127,6 +2126,10 @@ bool Cy_SysPm_BuckIsOutputEnabled(cy_en_syspm_buck_out_t output) *******************************************************************************/ void Cy_SysPm_BuckEnableVoltage2(void) { +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + CY_PRA_FUNCTION_CALL_VOID_VOID(CY_PRA_MSG_TYPE_SECURE_ONLY, + CY_PRA_PM_FUNC_BUCK_ENABLE_VOLTAGE2); +#else /* Do nothing if device does not have the second Buck output (SIMO) */ if (0U != cy_device->sysPmSimoPresent) { @@ -2142,8 +2145,8 @@ void Cy_SysPm_BuckEnableVoltage2(void) /* Wait until the output is stable */ Cy_SysLib_DelayUs(BUCK_OUT2_INIT_DELAY_US); } +#endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ } -#endif /* !((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ /******************************************************************************* @@ -2177,7 +2180,15 @@ void Cy_SysPm_BuckEnableVoltage2(void) *******************************************************************************/ void Cy_SysPm_BuckSetVoltage2(cy_en_syspm_buck_voltage2_t voltage, bool waitToSettle) { -#if !((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + cy_stc_pra_voltage2_t voltageSettings; + voltageSettings.praVoltage = voltage; + voltageSettings.praWaitToSettle = waitToSettle; + + CY_PRA_FUNCTION_CALL_VOID_PARAM(CY_PRA_MSG_TYPE_SECURE_ONLY, + CY_PRA_PM_FUNC_BUCK_SET_VOLTAGE2, + &voltageSettings); +#else /* Do nothing if device does not have the second Buck output (SIMO) */ if (0U != cy_device->sysPmSimoPresent) { @@ -2202,10 +2213,7 @@ void Cy_SysPm_BuckSetVoltage2(cy_en_syspm_buck_voltage2_t voltage, bool waitToSe } } } -#else - (void)voltage; - (void)waitToSettle; -#endif /* !((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ +#endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ } @@ -2399,7 +2407,7 @@ cy_en_syspm_status_t Cy_SysPm_LdoSetVoltage(cy_en_syspm_ldo_voltage_t voltage) * \ref cy_en_pra_status_t for more details. * * \sideeffect -* For PSoC64 series devices CY_SYSPM_LDO_MODE_DISABLED mode is not supported. +* For PSoC 64 series devices CY_SYSPM_LDO_MODE_DISABLED mode is not supported. * Use \ref Cy_SysPm_BuckEnable() instead. * *******************************************************************************/ @@ -3078,16 +3086,17 @@ void Cy_SysPm_RestoreRegisters(cy_stc_syspm_backup_regs_t const *regs) * - false - System Deep Sleep was not occurred. * *******************************************************************************/ -#if defined (__ICCARM__) - #pragma diag_suppress=Ta023 - __ramfunc -#else - CY_SECTION(".cy_ramfunc") CY_NOINLINE +CY_RAMFUNC_BEGIN +#if !defined (__ICCARM__) + CY_NOINLINE #endif static void EnterDeepSleepRam(cy_en_syspm_waitfor_t waitFor) { +#if !((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + /* Store the address of the Deep Sleep indicator into the RAM */ volatile uint32_t *delayDoneFlag = &FLASHC_BIST_DATA_0; +#endif /* !((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ #if (CY_CPU_CORTEX_M4) @@ -3126,8 +3135,13 @@ static void EnterDeepSleepRam(cy_en_syspm_waitfor_t waitFor) #if (CY_CPU_CORTEX_M4) } while (_FLD2VAL(CPUSS_CM4_PWR_CTL_PWR_MODE, (*cpussCm4PwrCtlAddr)) == CM4_PWR_STS_RETAINED); + + #if defined(CY_DEVICE_SECURE) + CY_PRA_CM0_WAKEUP(); + #endif /* defined(CY_DEVICE_SECURE) */ #endif /* (CY_CPU_CORTEX_M4) */ +#if !((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) /* Set 10 uS delay only under condition that the FLASHC_BIST_DATA[0] is * cleared. Cypress ID #288510 */ @@ -3137,6 +3151,10 @@ static void EnterDeepSleepRam(cy_en_syspm_waitfor_t waitFor) uint32_t clkOutputSlow; uint32_t ddftFastCtl; + #if defined(CY_DEVICE_SECURE) + Cy_PRA_CloseSrssMain2(); + #endif /* defined(CY_DEVICE_SECURE) */ + /* Save timer configuration */ ddftSlowCtl = SRSS_TST_DDFT_SLOW_CTL_REG; clkOutputSlow = SRSS_CLK_OUTPUT_SLOW; @@ -3162,11 +3180,14 @@ static void EnterDeepSleepRam(cy_en_syspm_waitfor_t waitFor) SRSS_TST_DDFT_SLOW_CTL_REG = ddftSlowCtl; SRSS_CLK_OUTPUT_SLOW = clkOutputSlow; SRSS_TST_DDFT_FAST_CTL_REG = ddftFastCtl; + + #if defined(CY_DEVICE_SECURE) + Cy_PRA_OpenSrssMain2(); + #endif /* defined(CY_DEVICE_SECURE) */ } +#endif /* !((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ } -#if defined (__ICCARM__) - #pragma diag_default=Ta023 -#endif +CY_RAMFUNC_END #if !((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_systick.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_systick.c index 1636e323ac..bf39e493ce 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_systick.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_systick.c @@ -117,7 +117,7 @@ void Cy_SysTick_Disable(void) * called to compensate this change. * * \param clockSource \ref cy_en_systick_clock_source_t Clock source. -* For the PSoC64 devices, passing any other value than +* For the PSoC 64 devices, passing any other value than * CY_SYSTICK_CLOCK_SOURCE_CLK_CPU will not affect clock source * and it will be as \ref Cy_SysTick_GetClockSource() reports. * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/althf_bleeco-1.0.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/althf_bleeco-1.0.cypersonality index 25b48f7215..21d2bb8fb4 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/althf_bleeco-1.0.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/althf_bleeco-1.0.cypersonality @@ -69,6 +69,6 @@ - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/eco-2.0.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/eco-2.0.cypersonality index 8c9b4a9258..abd1e00e19 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/eco-2.0.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/eco-2.0.cypersonality @@ -97,6 +97,6 @@ - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/extclk-1.1.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/extclk-1.1.cypersonality index a9cf6d12e7..1c01168ca9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/extclk-1.1.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/extclk-1.1.cypersonality @@ -65,6 +65,6 @@ - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/pilo-1.0.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/pilo-1.0.cypersonality index fdf1726052..ba6a8dc117 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/pilo-1.0.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/pilo-1.0.cypersonality @@ -47,6 +47,6 @@ - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/pumpclk-1.0.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/pumpclk-1.0.cypersonality index 777f1df435..19d681543f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/pumpclk-1.0.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/pumpclk-1.0.cypersonality @@ -96,6 +96,6 @@ - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/sysclock-1.2.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/sysclock-1.2.cypersonality index 46bd98d706..e3648391b5 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/sysclock-1.2.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/sysclock-1.2.cypersonality @@ -650,7 +650,7 @@ - + @@ -720,7 +720,7 @@ - + @@ -848,13 +848,10 @@ - - - - - - - + + + + @@ -887,6 +884,17 @@ + + + + + + + + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/althf_bleeco-1.0.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/althf_bleeco-1.0.cypersonality index 25b48f7215..21d2bb8fb4 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/althf_bleeco-1.0.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/althf_bleeco-1.0.cypersonality @@ -69,6 +69,6 @@ - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/eco-2.0.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/eco-2.0.cypersonality index 8c9b4a9258..abd1e00e19 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/eco-2.0.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/eco-2.0.cypersonality @@ -97,6 +97,6 @@ - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/extclk-1.1.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/extclk-1.1.cypersonality index a9cf6d12e7..1c01168ca9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/extclk-1.1.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/extclk-1.1.cypersonality @@ -65,6 +65,6 @@ - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/pilo-1.0.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/pilo-1.0.cypersonality index fdf1726052..ba6a8dc117 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/pilo-1.0.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/pilo-1.0.cypersonality @@ -47,6 +47,6 @@ - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/pumpclk-1.0.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/pumpclk-1.0.cypersonality index 777f1df435..19d681543f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/pumpclk-1.0.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/pumpclk-1.0.cypersonality @@ -96,6 +96,6 @@ - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/sysclock-1.2.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/sysclock-1.2.cypersonality index 46bd98d706..e3648391b5 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/sysclock-1.2.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/sysclock-1.2.cypersonality @@ -650,7 +650,7 @@ - + @@ -720,7 +720,7 @@ - + @@ -848,13 +848,10 @@ - - - - - - - + + + + @@ -887,6 +884,17 @@ + + + + + + + + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/001-91989.revision b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/001-91989.revision index 0a9e1e1b5d..be80172872 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/001-91989.revision +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/001-91989.revision @@ -1 +1 @@ -CK +CM \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148AZI-S2F44/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148AZI-S2F44/base/view.xml new file mode 100755 index 0000000000..b336259045 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148AZI-S2F44/base/view.xml @@ -0,0 +1,11 @@ + + + CortexM4 + Cypress + 1048576 + 524288 + 128-TQFP + 1700 + 3600 + The CY8C6148AZI-S2F44 device. + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148AZI-S2F44/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148AZI-S2F44/info.xml new file mode 100755 index 0000000000..d9596f1f22 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148AZI-S2F44/info.xml @@ -0,0 +1,6 @@ + + + CY8C6148AZI-S2F44 + The CY8C6148AZI-S2F44 devices + true + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148AZI-S2F44/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148AZI-S2F44/studio/presentation new file mode 100755 index 0000000000..5a9f775be9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148AZI-S2F44/studio/presentation @@ -0,0 +1,2 @@ +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148AZI-S2F44/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148AZI-S2F44/studio/view.xml new file mode 100755 index 0000000000..8a77a3340b --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148AZI-S2F44/studio/view.xml @@ -0,0 +1,62 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148BZI-S2F44/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148BZI-S2F44/base/view.xml new file mode 100755 index 0000000000..9726d863f3 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148BZI-S2F44/base/view.xml @@ -0,0 +1,11 @@ + + + CortexM4 + Cypress + 1048576 + 524288 + 124-BGA + 1700 + 3600 + The CY8C6148BZI-S2F44 device. + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148BZI-S2F44/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148BZI-S2F44/info.xml new file mode 100755 index 0000000000..9b0700c770 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148BZI-S2F44/info.xml @@ -0,0 +1,6 @@ + + + CY8C6148BZI-S2F44 + The CY8C6148BZI-S2F44 devices + true + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148BZI-S2F44/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148BZI-S2F44/studio/presentation new file mode 100755 index 0000000000..5a9f775be9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148BZI-S2F44/studio/presentation @@ -0,0 +1,2 @@ +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148BZI-S2F44/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148BZI-S2F44/studio/view.xml new file mode 100755 index 0000000000..24ba4cc571 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148BZI-S2F44/studio/view.xml @@ -0,0 +1,62 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148FNI-S2F43/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148FNI-S2F43/base/view.xml new file mode 100755 index 0000000000..23896f5685 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148FNI-S2F43/base/view.xml @@ -0,0 +1,11 @@ + + + CortexM4 + Cypress + 1048576 + 524288 + 100-WLCSP + 1700 + 3600 + The CY8C6148FNI-S2F43 device. + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148FNI-S2F43/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148FNI-S2F43/info.xml new file mode 100755 index 0000000000..dc57614cec --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148FNI-S2F43/info.xml @@ -0,0 +1,6 @@ + + + CY8C6148FNI-S2F43 + The CY8C6148FNI-S2F43 devices + true + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148FNI-S2F43/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148FNI-S2F43/studio/presentation new file mode 100755 index 0000000000..5a9f775be9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148FNI-S2F43/studio/presentation @@ -0,0 +1,2 @@ +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148FNI-S2F43/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148FNI-S2F43/studio/view.xml new file mode 100755 index 0000000000..578e964a19 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148FNI-S2F43/studio/view.xml @@ -0,0 +1,62 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F04/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F04/base/view.xml new file mode 100755 index 0000000000..5ffbbf47f4 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F04/base/view.xml @@ -0,0 +1,11 @@ + + + CortexM4 + Cypress + 2097152 + 1048576 + 128-TQFP + 1700 + 3600 + The CY8C614AAZI-S2F04 device. + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F04/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F04/info.xml new file mode 100755 index 0000000000..117bde59cb --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F04/info.xml @@ -0,0 +1,6 @@ + + + CY8C614AAZI-S2F04 + The CY8C614AAZI-S2F04 devices + true + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F04/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F04/studio/presentation new file mode 100755 index 0000000000..5a9f775be9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F04/studio/presentation @@ -0,0 +1,2 @@ +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F04/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F04/studio/view.xml new file mode 100755 index 0000000000..1d66a71ab9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F04/studio/view.xml @@ -0,0 +1,62 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F14/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F14/base/view.xml new file mode 100755 index 0000000000..e55ef035c4 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F14/base/view.xml @@ -0,0 +1,11 @@ + + + CortexM4 + Cypress + 2097152 + 1048576 + 128-TQFP + 1700 + 3600 + The CY8C614AAZI-S2F14 device. + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F14/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F14/info.xml new file mode 100755 index 0000000000..fb2a7c07cf --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F14/info.xml @@ -0,0 +1,6 @@ + + + CY8C614AAZI-S2F14 + The CY8C614AAZI-S2F14 devices + true + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F14/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F14/studio/presentation new file mode 100755 index 0000000000..5a9f775be9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F14/studio/presentation @@ -0,0 +1,2 @@ +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F14/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F14/studio/view.xml new file mode 100755 index 0000000000..016902db8f --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F14/studio/view.xml @@ -0,0 +1,62 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F44/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F44/base/view.xml new file mode 100755 index 0000000000..c9c63eaf94 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F44/base/view.xml @@ -0,0 +1,11 @@ + + + CortexM4 + Cypress + 2097152 + 1048576 + 128-TQFP + 1700 + 3600 + The CY8C614AAZI-S2F44 device. + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F44/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F44/info.xml new file mode 100755 index 0000000000..009794e379 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F44/info.xml @@ -0,0 +1,6 @@ + + + CY8C614AAZI-S2F44 + The CY8C614AAZI-S2F44 devices + true + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F44/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F44/studio/presentation new file mode 100755 index 0000000000..5a9f775be9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F44/studio/presentation @@ -0,0 +1,2 @@ +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AAZI-D44/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F44/studio/view.xml similarity index 80% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AAZI-D44/studio/view.xml rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F44/studio/view.xml index 14cb3ddbce..d25a8c6a8c 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AAZI-D44/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F44/studio/view.xml @@ -1,12 +1,12 @@ - + - - + + @@ -27,7 +27,7 @@ - + @@ -38,7 +38,10 @@ - + + + + @@ -49,11 +52,11 @@ - + - + - + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614ABZI-S2F04/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614ABZI-S2F04/base/view.xml new file mode 100755 index 0000000000..c15bf0c405 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614ABZI-S2F04/base/view.xml @@ -0,0 +1,11 @@ + + + CortexM4 + Cypress + 2097152 + 1048576 + 124-BGA + 1700 + 3600 + The CY8C614ABZI-S2F04 device. + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614ABZI-S2F04/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614ABZI-S2F04/info.xml new file mode 100755 index 0000000000..c4d0f818d5 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614ABZI-S2F04/info.xml @@ -0,0 +1,6 @@ + + + CY8C614ABZI-S2F04 + The CY8C614ABZI-S2F04 devices + true + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614ABZI-S2F04/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614ABZI-S2F04/studio/presentation new file mode 100755 index 0000000000..5a9f775be9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614ABZI-S2F04/studio/presentation @@ -0,0 +1,2 @@ +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614ABZI-S2F04/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614ABZI-S2F04/studio/view.xml new file mode 100755 index 0000000000..0096375f9b --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614ABZI-S2F04/studio/view.xml @@ -0,0 +1,62 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614ABZI-S2F44/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614ABZI-S2F44/base/view.xml new file mode 100755 index 0000000000..9041d1d9c7 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614ABZI-S2F44/base/view.xml @@ -0,0 +1,11 @@ + + + CortexM4 + Cypress + 2097152 + 1048576 + 124-BGA + 1700 + 3600 + The CY8C614ABZI-S2F44 device. + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614ABZI-S2F44/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614ABZI-S2F44/info.xml new file mode 100755 index 0000000000..d62601cbb9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614ABZI-S2F44/info.xml @@ -0,0 +1,6 @@ + + + CY8C614ABZI-S2F44 + The CY8C614ABZI-S2F44 devices + true + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614ABZI-S2F44/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614ABZI-S2F44/studio/presentation new file mode 100755 index 0000000000..5a9f775be9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614ABZI-S2F44/studio/presentation @@ -0,0 +1,2 @@ +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ALQI-D42/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614ABZI-S2F44/studio/view.xml similarity index 77% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ALQI-D42/studio/view.xml rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614ABZI-S2F44/studio/view.xml index 87a81855a4..c4887e517e 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ALQI-D42/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614ABZI-S2F44/studio/view.xml @@ -1,12 +1,12 @@ - + - - - + + + @@ -27,7 +27,7 @@ - + @@ -38,22 +38,25 @@ - + + + + - + - + - + - + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AFNI-S2F03/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AFNI-S2F03/base/view.xml new file mode 100755 index 0000000000..578236fa1f --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AFNI-S2F03/base/view.xml @@ -0,0 +1,11 @@ + + + CortexM4 + Cypress + 2097152 + 1048576 + 100-WLCSP + 1700 + 3600 + The CY8C614AFNI-S2F03 device. + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AFNI-S2F03/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AFNI-S2F03/info.xml new file mode 100755 index 0000000000..94154852a0 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AFNI-S2F03/info.xml @@ -0,0 +1,6 @@ + + + CY8C614AFNI-S2F03 + The CY8C614AFNI-S2F03 devices + true + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AFNI-S2F03/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AFNI-S2F03/studio/presentation new file mode 100755 index 0000000000..5a9f775be9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AFNI-S2F03/studio/presentation @@ -0,0 +1,2 @@ +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AFNI-S2F03/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AFNI-S2F03/studio/view.xml new file mode 100755 index 0000000000..9bb376409a --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AFNI-S2F03/studio/view.xml @@ -0,0 +1,62 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AFNI-S2F43/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AFNI-S2F43/base/view.xml new file mode 100755 index 0000000000..870c15970e --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AFNI-S2F43/base/view.xml @@ -0,0 +1,11 @@ + + + CortexM4 + Cypress + 2097152 + 1048576 + 100-WLCSP + 1700 + 3600 + The CY8C614AFNI-S2F43 device. + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AFNI-S2F43/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AFNI-S2F43/info.xml new file mode 100755 index 0000000000..4df60a93c6 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AFNI-S2F43/info.xml @@ -0,0 +1,6 @@ + + + CY8C614AFNI-S2F43 + The CY8C614AFNI-S2F43 devices + true + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AFNI-S2F43/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AFNI-S2F43/studio/presentation new file mode 100755 index 0000000000..5a9f775be9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AFNI-S2F43/studio/presentation @@ -0,0 +1,2 @@ +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AFNI-D43/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AFNI-S2F43/studio/view.xml similarity index 79% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AFNI-D43/studio/view.xml rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AFNI-S2F43/studio/view.xml index bd790c90c5..3ca7d4fac5 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AFNI-D43/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AFNI-S2F43/studio/view.xml @@ -1,12 +1,12 @@ - + - - + + @@ -27,7 +27,7 @@ - + @@ -38,22 +38,25 @@ - + + + + - + - + - + - + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248AZI-S2D14/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248AZI-S2D14/studio/view.xml index 9ff84b1255..f4e15510b7 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248AZI-S2D14/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248AZI-S2D14/studio/view.xml @@ -27,7 +27,7 @@ - + @@ -38,7 +38,10 @@ - + + + + @@ -49,7 +52,7 @@ - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248AZI-S2D44/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248AZI-S2D44/studio/view.xml index d6f743043e..d73eef77d4 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248AZI-S2D44/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248AZI-S2D44/studio/view.xml @@ -27,7 +27,7 @@ - + @@ -38,7 +38,10 @@ - + + + + @@ -49,7 +52,7 @@ - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248BZI-S2D44/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248BZI-S2D44/studio/view.xml index d50d4042d1..f31edc3704 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248BZI-S2D44/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248BZI-S2D44/studio/view.xml @@ -27,7 +27,7 @@ - + @@ -38,18 +38,21 @@ - + + + + - + - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248FNI-S2D43/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248FNI-S2D43/studio/view.xml index 139dd05aa3..aafbfcc5c3 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248FNI-S2D43/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248FNI-S2D43/studio/view.xml @@ -27,7 +27,7 @@ - + @@ -38,18 +38,21 @@ - + + + + - + - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AAZI-D44/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AAZI-D44/studio/presentation deleted file mode 100755 index 33e940a6d9..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AAZI-D44/studio/presentation +++ /dev/null @@ -1,2 +0,0 @@ -PSoC 6 -PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AAZI-S2D14/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AAZI-S2D14/studio/view.xml index 028ec1e66c..1ce1c60886 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AAZI-S2D14/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AAZI-S2D14/studio/view.xml @@ -27,7 +27,7 @@ - + @@ -38,7 +38,10 @@ - + + + + @@ -49,7 +52,7 @@ - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AAZI-S2D44/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AAZI-S2D44/studio/view.xml index 87558bc93f..86c155b646 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AAZI-S2D44/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AAZI-S2D44/studio/view.xml @@ -27,7 +27,7 @@ - + @@ -38,7 +38,10 @@ - + + + + @@ -49,7 +52,7 @@ - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-D44/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-D44/studio/view.xml index 03efa630a7..ff70184fa5 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-D44/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-D44/studio/view.xml @@ -27,7 +27,7 @@ - + @@ -38,11 +38,14 @@ - + + + + - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D04/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D04/studio/view.xml index 9c6b20cb6a..2340a24e41 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D04/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D04/studio/view.xml @@ -27,7 +27,7 @@ - + @@ -38,18 +38,21 @@ - + + + + - + - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D14/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D14/studio/view.xml index dc21f4e3b1..fbfb08f0dc 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D14/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D14/studio/view.xml @@ -27,7 +27,7 @@ - + @@ -38,18 +38,21 @@ - + + + + - + - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D44/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D44/studio/view.xml index 093f101bbc..2b0108c881 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D44/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D44/studio/view.xml @@ -27,7 +27,7 @@ - + @@ -38,18 +38,21 @@ - + + + + - + - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D44A0/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D44A0/studio/view.xml index 659fe77bd1..091795d0af 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D44A0/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D44A0/studio/view.xml @@ -27,7 +27,7 @@ - + @@ -38,11 +38,14 @@ - + + + + - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AFNI-D43/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AFNI-D43/studio/presentation deleted file mode 100755 index 33e940a6d9..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AFNI-D43/studio/presentation +++ /dev/null @@ -1,2 +0,0 @@ -PSoC 6 -PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AFNI-S2D43/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AFNI-S2D43/studio/view.xml index fa71a63f01..6f32c1d346 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AFNI-S2D43/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AFNI-S2D43/studio/view.xml @@ -27,7 +27,7 @@ - + @@ -38,18 +38,21 @@ - + + + + - + - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ALQI-D42/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ALQI-D42/studio/presentation deleted file mode 100755 index 33e940a6d9..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ALQI-D42/studio/presentation +++ /dev/null @@ -1,2 +0,0 @@ -PSoC 6 -PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-S2D44/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-S2D44/studio/view.xml index 5c81c57df5..71aa157292 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-S2D44/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-S2D44/studio/view.xml @@ -27,7 +27,7 @@ - + @@ -38,11 +38,14 @@ - + + + + - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYS0644ABZI-S2D44/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYS0644ABZI-S2D44/studio/view.xml index 7ab485cbb7..ae4c3ff4a3 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYS0644ABZI-S2D44/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYS0644ABZI-S2D44/studio/view.xml @@ -27,7 +27,7 @@ - + @@ -38,11 +38,14 @@ - + + + + - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245W-S3D72/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F02/base/view.xml similarity index 68% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245W-S3D72/base/view.xml rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F02/base/view.xml index 8d06343874..0d5e870182 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245W-S3D72/base/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F02/base/view.xml @@ -1,11 +1,11 @@  - CortexM0p,CortexM4 + CortexM4 Cypress 524288 262144 100-TQFP 1700 3600 - The CY8C6245W-S3D72 device. + The CY8C6145AZI-S3F02 device. \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F02/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F02/info.xml new file mode 100755 index 0000000000..a29246d584 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F02/info.xml @@ -0,0 +1,6 @@ + + + CY8C6145AZI-S3F02 + The CY8C6145AZI-S3F02 devices + true + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F02/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F02/studio/presentation new file mode 100755 index 0000000000..5a9f775be9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F02/studio/presentation @@ -0,0 +1,2 @@ +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F02/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F02/studio/view.xml new file mode 100755 index 0000000000..dd13b175bb --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F02/studio/view.xml @@ -0,0 +1,63 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F12/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F12/base/view.xml new file mode 100755 index 0000000000..1d1d61ca5e --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F12/base/view.xml @@ -0,0 +1,11 @@ + + + CortexM4 + Cypress + 524288 + 262144 + 100-TQFP + 1700 + 3600 + The CY8C6145AZI-S3F12 device. + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F12/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F12/info.xml new file mode 100755 index 0000000000..b4d733d1df --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F12/info.xml @@ -0,0 +1,6 @@ + + + CY8C6145AZI-S3F12 + The CY8C6145AZI-S3F12 devices + true + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F12/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F12/studio/presentation new file mode 100755 index 0000000000..5a9f775be9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F12/studio/presentation @@ -0,0 +1,2 @@ +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F12/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F12/studio/view.xml new file mode 100755 index 0000000000..634df9e928 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F12/studio/view.xml @@ -0,0 +1,63 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F42/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F42/base/view.xml new file mode 100755 index 0000000000..42b3d79a9a --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F42/base/view.xml @@ -0,0 +1,11 @@ + + + CortexM4 + Cypress + 524288 + 262144 + 100-TQFP + 1700 + 3600 + The CY8C6145AZI-S3F42 device. + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F42/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F42/info.xml new file mode 100755 index 0000000000..0e632b7bdd --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F42/info.xml @@ -0,0 +1,6 @@ + + + CY8C6145AZI-S3F42 + The CY8C6145AZI-S3F42 devices + true + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F42/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F42/studio/presentation new file mode 100755 index 0000000000..5a9f775be9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F42/studio/presentation @@ -0,0 +1,2 @@ +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F42/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F42/studio/view.xml new file mode 100755 index 0000000000..461c93e045 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F42/studio/view.xml @@ -0,0 +1,63 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F62/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F62/base/view.xml new file mode 100755 index 0000000000..a1b623d8a2 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F62/base/view.xml @@ -0,0 +1,11 @@ + + + CortexM4 + Cypress + 524288 + 262144 + 100-TQFP + 1700 + 3600 + The CY8C6145AZI-S3F62 device. + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F62/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F62/info.xml new file mode 100755 index 0000000000..de518d6d73 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F62/info.xml @@ -0,0 +1,6 @@ + + + CY8C6145AZI-S3F62 + The CY8C6145AZI-S3F62 devices + true + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F62/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F62/studio/presentation new file mode 100755 index 0000000000..5a9f775be9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F62/studio/presentation @@ -0,0 +1,2 @@ +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F62/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F62/studio/view.xml new file mode 100755 index 0000000000..546999273b --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F62/studio/view.xml @@ -0,0 +1,63 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F72/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F72/base/view.xml new file mode 100755 index 0000000000..9da47dde19 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F72/base/view.xml @@ -0,0 +1,11 @@ + + + CortexM4 + Cypress + 524288 + 262144 + 100-TQFP + 1700 + 3600 + The CY8C6145AZI-S3F72 device. + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F72/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F72/info.xml new file mode 100755 index 0000000000..51773ff2cb --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F72/info.xml @@ -0,0 +1,6 @@ + + + CY8C6145AZI-S3F72 + The CY8C6145AZI-S3F72 devices + true + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F72/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F72/studio/presentation new file mode 100755 index 0000000000..5a9f775be9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F72/studio/presentation @@ -0,0 +1,2 @@ +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245W-S3D72/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F72/studio/view.xml similarity index 77% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245W-S3D72/studio/view.xml rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F72/studio/view.xml index 25edc41dc5..3de5870b92 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245W-S3D72/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F72/studio/view.xml @@ -1,12 +1,12 @@ - + - - + + @@ -27,7 +27,7 @@ - + @@ -39,10 +39,13 @@ - + + + + - - + + @@ -50,11 +53,11 @@ - + - + - + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F11/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F11/base/view.xml new file mode 100755 index 0000000000..4b5b8168f0 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F11/base/view.xml @@ -0,0 +1,11 @@ + + + CortexM4 + Cypress + 524288 + 262144 + 49-WLCSP + 1700 + 3600 + The CY8C6145FNI-S3F11 device. + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F11/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F11/info.xml new file mode 100755 index 0000000000..c0f9ceb284 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F11/info.xml @@ -0,0 +1,6 @@ + + + CY8C6145FNI-S3F11 + The CY8C6145FNI-S3F11 devices + true + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F11/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F11/studio/presentation new file mode 100755 index 0000000000..5a9f775be9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F11/studio/presentation @@ -0,0 +1,2 @@ +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F11/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F11/studio/view.xml new file mode 100755 index 0000000000..b1e40f1cf1 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F11/studio/view.xml @@ -0,0 +1,63 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F41/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F41/base/view.xml new file mode 100755 index 0000000000..1c60164c11 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F41/base/view.xml @@ -0,0 +1,11 @@ + + + CortexM4 + Cypress + 524288 + 262144 + 49-WLCSP + 1700 + 3600 + The CY8C6145FNI-S3F41 device. + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F41/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F41/info.xml new file mode 100755 index 0000000000..73cbd0aef2 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F41/info.xml @@ -0,0 +1,6 @@ + + + CY8C6145FNI-S3F41 + The CY8C6145FNI-S3F41 devices + true + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F41/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F41/studio/presentation new file mode 100755 index 0000000000..5a9f775be9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F41/studio/presentation @@ -0,0 +1,2 @@ +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F41/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F41/studio/view.xml new file mode 100755 index 0000000000..71a8f76b56 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F41/studio/view.xml @@ -0,0 +1,63 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F71/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F71/base/view.xml new file mode 100755 index 0000000000..68d8f20e36 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F71/base/view.xml @@ -0,0 +1,11 @@ + + + CortexM4 + Cypress + 524288 + 262144 + 49-WLCSP + 1700 + 3600 + The CY8C6145FNI-S3F71 device. + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F71/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F71/info.xml new file mode 100755 index 0000000000..203a82a05b --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F71/info.xml @@ -0,0 +1,6 @@ + + + CY8C6145FNI-S3F71 + The CY8C6145FNI-S3F71 devices + true + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F71/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F71/studio/presentation new file mode 100755 index 0000000000..5a9f775be9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F71/studio/presentation @@ -0,0 +1,2 @@ +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F71/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F71/studio/view.xml new file mode 100755 index 0000000000..082ac2f8e6 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F71/studio/view.xml @@ -0,0 +1,63 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F02/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F02/base/view.xml new file mode 100755 index 0000000000..8ca085c1fa --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F02/base/view.xml @@ -0,0 +1,11 @@ + + + CortexM4 + Cypress + 524288 + 262144 + 68-QFN + 1700 + 3600 + The CY8C6145LQI-S3F02 device. + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F02/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F02/info.xml new file mode 100755 index 0000000000..e304f655ea --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F02/info.xml @@ -0,0 +1,6 @@ + + + CY8C6145LQI-S3F02 + The CY8C6145LQI-S3F02 devices + true + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F02/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F02/studio/presentation new file mode 100755 index 0000000000..5a9f775be9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F02/studio/presentation @@ -0,0 +1,2 @@ +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F02/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F02/studio/view.xml new file mode 100755 index 0000000000..079b249013 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F02/studio/view.xml @@ -0,0 +1,63 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F12/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F12/base/view.xml new file mode 100755 index 0000000000..3be8ad70e6 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F12/base/view.xml @@ -0,0 +1,11 @@ + + + CortexM4 + Cypress + 524288 + 262144 + 68-QFN + 1700 + 3600 + The CY8C6145LQI-S3F12 device. + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F12/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F12/info.xml new file mode 100755 index 0000000000..5d7a88d83c --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F12/info.xml @@ -0,0 +1,6 @@ + + + CY8C6145LQI-S3F12 + The CY8C6145LQI-S3F12 devices + true + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F12/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F12/studio/presentation new file mode 100755 index 0000000000..5a9f775be9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F12/studio/presentation @@ -0,0 +1,2 @@ +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F12/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F12/studio/view.xml new file mode 100755 index 0000000000..7482ff3be5 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F12/studio/view.xml @@ -0,0 +1,63 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F42/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F42/base/view.xml new file mode 100755 index 0000000000..64704c1eaa --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F42/base/view.xml @@ -0,0 +1,11 @@ + + + CortexM4 + Cypress + 524288 + 262144 + 68-QFN + 1700 + 3600 + The CY8C6145LQI-S3F42 device. + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F42/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F42/info.xml new file mode 100755 index 0000000000..303a4bb1c7 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F42/info.xml @@ -0,0 +1,6 @@ + + + CY8C6145LQI-S3F42 + The CY8C6145LQI-S3F42 devices + true + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F42/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F42/studio/presentation new file mode 100755 index 0000000000..5a9f775be9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F42/studio/presentation @@ -0,0 +1,2 @@ +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F42/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F42/studio/view.xml new file mode 100755 index 0000000000..54aa0f12ee --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F42/studio/view.xml @@ -0,0 +1,63 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F62/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F62/base/view.xml new file mode 100755 index 0000000000..59a43571e3 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F62/base/view.xml @@ -0,0 +1,11 @@ + + + CortexM4 + Cypress + 524288 + 262144 + 68-QFN + 1700 + 3600 + The CY8C6145LQI-S3F62 device. + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F62/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F62/info.xml new file mode 100755 index 0000000000..c49f4ab424 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F62/info.xml @@ -0,0 +1,6 @@ + + + CY8C6145LQI-S3F62 + The CY8C6145LQI-S3F62 devices + true + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F62/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F62/studio/presentation new file mode 100755 index 0000000000..5a9f775be9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F62/studio/presentation @@ -0,0 +1,2 @@ +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F62/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F62/studio/view.xml new file mode 100755 index 0000000000..3b943a683e --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F62/studio/view.xml @@ -0,0 +1,63 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F72/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F72/base/view.xml new file mode 100755 index 0000000000..92ffecb55d --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F72/base/view.xml @@ -0,0 +1,11 @@ + + + CortexM4 + Cypress + 524288 + 262144 + 68-QFN + 1700 + 3600 + The CY8C6145LQI-S3F72 device. + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F72/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F72/info.xml new file mode 100755 index 0000000000..6d124be9c6 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F72/info.xml @@ -0,0 +1,6 @@ + + + CY8C6145LQI-S3F72 + The CY8C6145LQI-S3F72 devices + true + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F72/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F72/studio/presentation new file mode 100755 index 0000000000..5a9f775be9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F72/studio/presentation @@ -0,0 +1,2 @@ +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F72/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F72/studio/view.xml new file mode 100755 index 0000000000..caa7c517f3 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F72/studio/view.xml @@ -0,0 +1,63 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D02/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D02/studio/view.xml index 306679f90f..4955ba143d 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D02/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D02/studio/view.xml @@ -27,7 +27,7 @@ - + @@ -39,10 +39,13 @@ - + + + + - - + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D12/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D12/studio/view.xml index 302831c12e..7710c14c58 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D12/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D12/studio/view.xml @@ -27,7 +27,7 @@ - + @@ -39,10 +39,13 @@ - + + + + - - + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D42/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D42/studio/view.xml index d6657915b0..98c605a9cd 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D42/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D42/studio/view.xml @@ -27,7 +27,7 @@ - + @@ -39,10 +39,13 @@ - + + + + - - + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D62/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D62/studio/view.xml index 04e01b0f81..f60b03e33c 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D62/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D62/studio/view.xml @@ -27,7 +27,7 @@ - + @@ -39,10 +39,13 @@ - + + + + - - + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D72/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D72/studio/view.xml index ef1b0e33ee..0b0230e5f6 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D72/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D72/studio/view.xml @@ -27,7 +27,7 @@ - + @@ -39,10 +39,13 @@ - + + + + - - + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D11/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D11/studio/view.xml index 7ca1b42772..428528067b 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D11/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D11/studio/view.xml @@ -27,7 +27,7 @@ - + @@ -39,11 +39,14 @@ - + + + + - - - + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D41/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D41/studio/view.xml index d83afd9ca8..60b0852708 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D41/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D41/studio/view.xml @@ -27,7 +27,7 @@ - + @@ -39,11 +39,14 @@ - + + + + - - - + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D71/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D71/studio/view.xml index 06ef5b7909..579cc793b3 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D71/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D71/studio/view.xml @@ -27,7 +27,7 @@ - + @@ -39,11 +39,14 @@ - + + + + - - - + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D02/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D02/studio/view.xml index 2e907e5081..3a86611345 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D02/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D02/studio/view.xml @@ -27,7 +27,7 @@ - + @@ -39,11 +39,14 @@ - + + + + - - - + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D12/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D12/studio/view.xml index 2c2634da09..ac94984ddf 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D12/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D12/studio/view.xml @@ -27,7 +27,7 @@ - + @@ -39,11 +39,14 @@ - + + + + - - - + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D42/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D42/studio/view.xml index 091479e9c2..7f9b052553 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D42/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D42/studio/view.xml @@ -27,7 +27,7 @@ - + @@ -39,11 +39,14 @@ - + + + + - - - + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D62/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D62/studio/view.xml index b0af013f36..e635efe1e5 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D62/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D62/studio/view.xml @@ -27,7 +27,7 @@ - + @@ -39,11 +39,14 @@ - + + + + - - - + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D72/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D72/studio/view.xml index 8751845d52..10739295a2 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D72/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D72/studio/view.xml @@ -27,7 +27,7 @@ - + @@ -39,11 +39,14 @@ - + + + + - - - + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245W-S3D72/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245W-S3D72/info.xml deleted file mode 100755 index 1204849e13..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245W-S3D72/info.xml +++ /dev/null @@ -1,6 +0,0 @@ - - - CY8C6245W-S3D72 - The CY8C6245W-S3D72 devices - true - \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245W-S3D72/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245W-S3D72/studio/presentation deleted file mode 100755 index 33e940a6d9..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245W-S3D72/studio/presentation +++ /dev/null @@ -1,2 +0,0 @@ -PSoC 6 -PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CYB06445LQI-S3D42/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CYB06445LQI-S3D42/studio/view.xml index 9d4b1e2af3..fbc47ada6d 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CYB06445LQI-S3D42/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CYB06445LQI-S3D42/studio/view.xml @@ -27,7 +27,7 @@ - + @@ -39,11 +39,14 @@ - + + + + - - - + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6016BZI-F04/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6016BZI-F04/studio/view.xml index 67119b768b..8d2b81143b 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6016BZI-F04/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6016BZI-F04/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6036BZI-F04/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6036BZI-F04/studio/view.xml index 607131a1f2..cbc09d674f 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6036BZI-F04/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6036BZI-F04/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6116BZI-F54/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6116BZI-F54/studio/view.xml index 65937588cb..f81c747ef8 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6116BZI-F54/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6116BZI-F54/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6117BZI-F34/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6117BZI-F34/studio/view.xml index 0eec5ef29e..540fe89bd7 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6117BZI-F34/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6117BZI-F34/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6117FDI-F02/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6117FDI-F02/studio/view.xml index 64cc75026a..907583f3da 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6117FDI-F02/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6117FDI-F02/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6117WI-F34/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6117WI-F34/studio/view.xml index 2652b7739f..76deb98685 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6117WI-F34/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6117WI-F34/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136BZI-F14/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136BZI-F14/studio/view.xml index 98d2217c6a..5faa4ba97c 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136BZI-F14/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136BZI-F14/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136BZI-F34/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136BZI-F34/studio/view.xml index 022ce8bff3..0812ea676e 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136BZI-F34/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136BZI-F34/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136FDI-F42/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136FDI-F42/studio/view.xml index 80c6d8877f..563fb0c5e1 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136FDI-F42/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136FDI-F42/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136FTI-F42/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136FTI-F42/studio/view.xml index c82d5714f6..b9e488e88b 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136FTI-F42/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136FTI-F42/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137BZI-F14/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137BZI-F14/studio/view.xml index 402cee19a4..f505e1d257 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137BZI-F14/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137BZI-F14/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137BZI-F34/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137BZI-F34/studio/view.xml index 8acedecafa..58d78594fd 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137BZI-F34/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137BZI-F34/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137BZI-F54/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137BZI-F54/studio/view.xml index b9e269ee2c..a557a0f02e 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137BZI-F54/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137BZI-F54/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137FDI-F02/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137FDI-F02/studio/view.xml index ada24afd8b..d91c6952ec 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137FDI-F02/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137FDI-F02/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137WI-F54/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137WI-F54/studio/view.xml index 7d3475d977..9b0581df5e 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137WI-F54/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137WI-F54/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6246BZI-D04/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6246BZI-D04/studio/view.xml index e6b33fda98..d0e4b06f0b 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6246BZI-D04/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6246BZI-D04/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BFI-D54/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BFI-D54/studio/view.xml index 0fb9e56d7a..1ed97c8487 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BFI-D54/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BFI-D54/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-AUD54/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-AUD54/studio/view.xml index b1c1248b3b..b170e5371c 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-AUD54/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-AUD54/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-D34/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-D34/studio/view.xml index b7d95b894a..59bf9166e6 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-D34/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-D34/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-D44/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-D44/studio/view.xml index 4548961b2e..6c81a44357 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-D44/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-D44/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-D54/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-D54/studio/view.xml index fe4edc4135..7b14363141 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-D54/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-D54/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FDI-D02/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FDI-D02/studio/view.xml index 493454bfd3..d004d337c4 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FDI-D02/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FDI-D02/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FDI-D32/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FDI-D32/studio/view.xml index 3ee96a9bff..dabd587e7c 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FDI-D32/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FDI-D32/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FDI-D52/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FDI-D52/studio/view.xml index 7efd340464..7da0077bd9 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FDI-D52/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FDI-D52/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FTI-D52/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FTI-D52/studio/view.xml index 44ec071d7f..63baacb1ff 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FTI-D52/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FTI-D52/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247WI-D54/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247WI-D54/studio/view.xml index e58adb5dbd..eb3dfbe0e8 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247WI-D54/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247WI-D54/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF03/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF03/studio/view.xml index 9975e58450..fec0a2fa74 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF03/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF03/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF04/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF04/studio/view.xml index 0b1ad376e0..6d2d86d7fb 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF04/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF04/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF53/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF53/studio/view.xml index f29e045e81..578c06a300 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF53/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF53/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF54/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF54/studio/view.xml index f378c17c32..b19845419c 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF54/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF54/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLD13/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLD13/studio/view.xml index d3cacc356d..e4453c57b6 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLD13/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLD13/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLD14/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLD14/studio/view.xml index 84e159f6e9..31d8c18aed 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLD14/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLD14/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLF03/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLF03/studio/view.xml index 03493ab6fa..5a991843ef 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLF03/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLF03/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLF04/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLF04/studio/view.xml index 737f025c42..0401ea002f 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLF04/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLF04/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BUD13/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BUD13/studio/view.xml index 65c2e46cfe..c670204260 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BUD13/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BUD13/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336LQI-BLF02/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336LQI-BLF02/studio/view.xml index fd68bf32a8..ff06c0d603 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336LQI-BLF02/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336LQI-BLF02/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336LQI-BLF42/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336LQI-BLF42/studio/view.xml index 0d5fab01d1..39798623db 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336LQI-BLF42/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336LQI-BLF42/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6337BZI-BLF13/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6337BZI-BLF13/studio/view.xml index 9fe0cdccd5..fa1dfb3c15 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6337BZI-BLF13/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6337BZI-BLF13/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD33/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD33/studio/view.xml index 226916d729..3e596ad8ae 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD33/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD33/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD34/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD34/studio/view.xml index 61af522e29..79f1e2accc 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD34/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD34/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD43/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD43/studio/view.xml index 3baba51028..e5373fd860 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD43/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD43/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD44/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD44/studio/view.xml index 955cf80e8f..c0011ee6d5 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD44/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD44/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD53/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD53/studio/view.xml index 6e72f32f8f..5def549190 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD53/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD53/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD54/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD54/studio/view.xml index cb40c6073f..b31840756c 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD54/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD54/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BUD33/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BUD33/studio/view.xml index 7f401613b3..7950ee0133 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BUD33/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BUD33/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BUD43/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BUD43/studio/view.xml index afcb9f1b34..eb0381e4ca 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BUD43/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BUD43/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BUD53/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BUD53/studio/view.xml index 316ef0718b..88e5bb3f38 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BUD53/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BUD53/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD13/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD13/studio/view.xml index 232bd19b46..31efde07a9 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD13/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD13/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD33/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD33/studio/view.xml index cdc915cf45..35ceda4838 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD33/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD33/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD43/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD43/studio/view.xml index 36340b5112..d866e101a5 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD43/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD43/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD53/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD53/studio/view.xml index 8022f45319..bcc087757d 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD53/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD53/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD13/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD13/studio/view.xml index cfede5daad..aed94c922c 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD13/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD13/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD33/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD33/studio/view.xml index fc0cd78720..ba1a54de70 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD33/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD33/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD43/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD43/studio/view.xml index e71bfba693..d41824c2bb 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD43/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD43/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD53/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD53/studio/view.xml index 0e25d64e94..f3418ad864 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD53/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD53/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347LQI-BLD52/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347LQI-BLD52/studio/view.xml index 7e2de6c1ef..058cec52e1 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347LQI-BLD52/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347LQI-BLD52/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C637BZI-BLD74/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C637BZI-BLD74/studio/view.xml index 9d20d02774..eec5fe41eb 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C637BZI-BLD74/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C637BZI-BLD74/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C637BZI-MD76/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C637BZI-MD76/studio/view.xml index 46ec52afff..80ed20816b 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C637BZI-MD76/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C637BZI-MD76/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C637FMI-BLD73/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C637FMI-BLD73/studio/view.xml index 9c48742a08..f17ecb0ecd 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C637FMI-BLD73/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C637FMI-BLD73/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C68237BZ-BLE/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C68237BZ-BLE/studio/view.xml index d4c9de2743..2d9743741b 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C68237BZ-BLE/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C68237BZ-BLE/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C68237FM-BLE/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C68237FM-BLE/studio/view.xml index a59eb6f6ff..65b6d8fd74 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C68237FM-BLE/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C68237FM-BLE/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-BLD53/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-BLD53/studio/view.xml index e38453199e..b7132cbc39 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-BLD53/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-BLD53/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-BLD54/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-BLD54/studio/view.xml index 9b78aba279..ac6b682147 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-BLD54/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-BLD54/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-D54/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-D54/studio/view.xml index 5bdca55eb7..345a40395b 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-D54/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-D54/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYBLE-416045-02/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYBLE-416045-02/studio/view.xml index 88a4d7a7d6..277ac06765 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYBLE-416045-02/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYBLE-416045-02/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/features.mk b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/features.mk index 9ebc6baf81..a8dff07bb6 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/features.mk +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/features.mk @@ -2,36 +2,36 @@ # list of the MPNs that have that capability or feature. # Major device capabilities. -CY_DEVICES_WITH_M0P=CY8C6246BZI-D04 CY8C6247BZI-D44 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C6336BZI-BLD13 CY8C6347BZI-BLD43 CY8C6347BZI-BLD33 CY8C6347BZI-BLD53 CY8C6347FMI-BLD13 CY8C6347FMI-BLD43 CY8C6347FMI-BLD33 CY8C6347FMI-BLD53 CY8C637BZI-MD76 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C68237BZ-BLE CY8C68237FM-BLE CY8C6247FDI-D02 CY8C6247FDI-D32 CY8C6336BZI-BUD13 CY8C6347BZI-BUD43 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 CY8C6247FDI-D52 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6336BZI-BLD14 CY8C6347BZI-BLD44 CY8C6347BZI-BLD34 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CYBLE-416045-02 CY8C6347FMI-BUD53 CY8C6347FMI-BUD13 CY8C6347FMI-BUD43 CY8C6347FMI-BUD33 CY8C6247WI-D54 CY8C6347LQI-BLD52 CYB06447BZI-BLD54 CYB06447BZI-BLD53 CYB06447BZI-D54 CY8C624ABZI-D44 CY8C624AAZI-D44 CY8C624AFNI-D43 CY8C624ABZI-D04 CY8C624ABZI-D14 CY8C624AAZI-D14 CY8C6248AZI-D14 CY8C6248BZI-D44 CY8C6248AZI-D44 CY8C6248FNI-D43 CY8C624ALQI-D42 CYB0644ABZI-S2D44 CYS0644ABZI-S2D44 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624AAZI-S2D44 CY8C624AFNI-S2D43 CY8C624ABZI-S2D04 CY8C624ABZI-S2D14 CY8C624AAZI-S2D14 CY8C6248AZI-S2D14 CY8C6248BZI-S2D44 CY8C6248AZI-S2D44 CY8C6248FNI-S2D43 CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245FNI-S3D71 CY8C6245AZI-S3D62 CY8C6245LQI-S3D62 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CYB06445LQI-S3D42 CY8C6245FNI-S3D41 CY8C6245AZI-S3D12 CY8C6245LQI-S3D12 CY8C6245FNI-S3D11 CY8C6245AZI-S3D02 CY8C6245LQI-S3D02 CY8C6245W-S3D72 +CY_DEVICES_WITH_M0P=CY8C6246BZI-D04 CY8C6247BZI-D44 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C6336BZI-BLD13 CY8C6347BZI-BLD43 CY8C6347BZI-BLD33 CY8C6347BZI-BLD53 CY8C6347FMI-BLD13 CY8C6347FMI-BLD43 CY8C6347FMI-BLD33 CY8C6347FMI-BLD53 CY8C637BZI-MD76 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C68237BZ-BLE CY8C68237FM-BLE CY8C6247FDI-D02 CY8C6247FDI-D32 CY8C6336BZI-BUD13 CY8C6347BZI-BUD43 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 CY8C6247FDI-D52 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6336BZI-BLD14 CY8C6347BZI-BLD44 CY8C6347BZI-BLD34 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CYBLE-416045-02 CY8C6347FMI-BUD53 CY8C6347FMI-BUD13 CY8C6347FMI-BUD43 CY8C6347FMI-BUD33 CY8C6247WI-D54 CY8C6347LQI-BLD52 CYB06447BZI-BLD54 CYB06447BZI-BLD53 CYB06447BZI-D54 CYB0644ABZI-S2D44 CYS0644ABZI-S2D44 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624AAZI-S2D44 CY8C624AFNI-S2D43 CY8C624ABZI-S2D04 CY8C624ABZI-S2D14 CY8C624AAZI-S2D14 CY8C6248AZI-S2D14 CY8C6248BZI-S2D44 CY8C6248AZI-S2D44 CY8C6248FNI-S2D43 CY8C624ABZI-D44 CY8C624AAZI-D44 CY8C624AFNI-D43 CY8C624ABZI-D04 CY8C624ABZI-D14 CY8C624AAZI-D14 CY8C6248AZI-D14 CY8C6248BZI-D44 CY8C6248AZI-D44 CY8C6248FNI-D43 CY8C624ALQI-D42 CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245FNI-S3D71 CY8C6245AZI-S3D62 CY8C6245LQI-S3D62 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CYB06445LQI-S3D42 CY8C6245FNI-S3D41 CY8C6245AZI-S3D12 CY8C6245LQI-S3D12 CY8C6245FNI-S3D11 CY8C6245AZI-S3D02 CY8C6245LQI-S3D02 CY8C6245WI-S3D72 CY_DEVICES_WITH_BLE=CY8C6336BZI-BLF03 CY8C6316BZI-BLF03 CY8C6316BZI-BLF53 CY8C6336BZI-BLD13 CY8C6347BZI-BLD43 CY8C6347BZI-BLD33 CY8C6347BZI-BLD53 CY8C6347FMI-BLD13 CY8C6347FMI-BLD43 CY8C6347FMI-BLD33 CY8C6347FMI-BLD53 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C68237BZ-BLE CY8C68237FM-BLE CY8C6336BZI-BUD13 CY8C6347BZI-BUD43 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 CY8C6337BZI-BLF13 CY8C6336BZI-BLF04 CY8C6316BZI-BLF04 CY8C6316BZI-BLF54 CY8C6336BZI-BLD14 CY8C6347BZI-BLD44 CY8C6347BZI-BLD34 CY8C6347BZI-BLD54 CYBLE-416045-02 CY8C6347FMI-BUD53 CY8C6347FMI-BUD13 CY8C6347FMI-BUD43 CY8C6347FMI-BUD33 CY8C6336LQI-BLF02 CY8C6336LQI-BLF42 CY8C6347LQI-BLD52 CYB06447BZI-BLD54 CYB06447BZI-BLD53 CY_DEVICES_WITH_UDBS=CY8C6116BZI-F54 CY8C6136BZI-F34 CY8C6137BZI-F34 CY8C6137BZI-F54 CY8C6117BZI-F34 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C6316BZI-BLF53 CY8C6347BZI-BLD33 CY8C6347BZI-BLD53 CY8C6347FMI-BLD33 CY8C6347FMI-BLD53 CY8C637BZI-MD76 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C6247FDI-D32 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 CY8C6247FDI-D52 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6316BZI-BLF54 CY8C6347BZI-BLD34 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CYBLE-416045-02 CY8C6347FMI-BUD53 CY8C6347FMI-BUD33 CY8C6137WI-F54 CY8C6117WI-F34 CY8C6247WI-D54 CY8C6347LQI-BLD52 CYB06447BZI-BLD54 CYB06447BZI-BLD53 CYB06447BZI-D54 -CY_DEVICES_WITH_FS_USB=CY8C6036BZI-F04 CY8C6016BZI-F04 CY8C6116BZI-F54 CY8C6136BZI-F14 CY8C6136BZI-F34 CY8C6137BZI-F14 CY8C6137BZI-F34 CY8C6137BZI-F54 CY8C6117BZI-F34 CY8C6246BZI-D04 CY8C6247BZI-D44 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C637BZI-MD76 CY8C6137FDI-F02 CY8C6117FDI-F02 CY8C6247FDI-D02 CY8C6247FDI-D32 CY8C6336BZI-BUD13 CY8C6347BZI-BUD43 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 CY8C6136FDI-F42 CY8C6247FDI-D52 CY8C6136FTI-F42 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6336BZI-BLF04 CY8C6316BZI-BLF04 CY8C6316BZI-BLF54 CY8C6336BZI-BLD14 CY8C6347BZI-BLD44 CY8C6347BZI-BLD34 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CY8C6347FMI-BUD53 CY8C6347FMI-BUD13 CY8C6347FMI-BUD43 CY8C6347FMI-BUD33 CY8C6137WI-F54 CY8C6117WI-F34 CY8C6247WI-D54 CYB06447BZI-BLD54 CYB06447BZI-D54 CY8C624ABZI-D44 CY8C624AAZI-D44 CY8C624AFNI-D43 CY8C624ABZI-D04 CY8C624ABZI-D14 CY8C624AAZI-D14 CY8C6248AZI-D14 CY8C6248BZI-D44 CY8C6248AZI-D44 CY8C6248FNI-D43 CY8C624ALQI-D42 CYB0644ABZI-S2D44 CYS0644ABZI-S2D44 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624AAZI-S2D44 CY8C624AFNI-S2D43 CY8C624ABZI-S2D04 CY8C624ABZI-S2D14 CY8C624AAZI-S2D14 CY8C6248AZI-S2D14 CY8C6248BZI-S2D44 CY8C6248AZI-S2D44 CY8C6248FNI-S2D43 CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245AZI-S3D62 CY8C6245LQI-S3D62 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CYB06445LQI-S3D42 CY8C6245AZI-S3D12 CY8C6245LQI-S3D12 CY8C6245AZI-S3D02 CY8C6245LQI-S3D02 CY8C6245W-S3D72 -CY_DEVICES_WITH_CAPSENSE=CY8C6116BZI-F54 CY8C6136BZI-F14 CY8C6136BZI-F34 CY8C6137BZI-F14 CY8C6137BZI-F34 CY8C6137BZI-F54 CY8C6117BZI-F34 CY8C6247BZI-D44 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C6316BZI-BLF53 CY8C6336BZI-BLD13 CY8C6347BZI-BLD43 CY8C6347BZI-BLD33 CY8C6347BZI-BLD53 CY8C6347FMI-BLD13 CY8C6347FMI-BLD43 CY8C6347FMI-BLD33 CY8C6347FMI-BLD53 CY8C637BZI-MD76 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C68237BZ-BLE CY8C68237FM-BLE CY8C6247FDI-D32 CY8C6336BZI-BUD13 CY8C6347BZI-BUD43 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 CY8C6337BZI-BLF13 CY8C6136FDI-F42 CY8C6247FDI-D52 CY8C6136FTI-F42 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6316BZI-BLF54 CY8C6336BZI-BLD14 CY8C6347BZI-BLD44 CY8C6347BZI-BLD34 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CYBLE-416045-02 CY8C6347FMI-BUD53 CY8C6347FMI-BUD13 CY8C6347FMI-BUD43 CY8C6347FMI-BUD33 CY8C6137WI-F54 CY8C6117WI-F34 CY8C6247WI-D54 CY8C6336LQI-BLF42 CY8C6347LQI-BLD52 CYB06447BZI-BLD54 CYB06447BZI-BLD53 CYB06447BZI-D54 CY8C624ABZI-D44 CY8C624AAZI-D44 CY8C624AFNI-D43 CY8C624ABZI-D14 CY8C624AAZI-D14 CY8C6248AZI-D14 CY8C6248BZI-D44 CY8C6248AZI-D44 CY8C6248FNI-D43 CY8C624ALQI-D42 CYB0644ABZI-S2D44 CYS0644ABZI-S2D44 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624AAZI-S2D44 CY8C624AFNI-S2D43 CY8C624ABZI-S2D14 CY8C624AAZI-S2D14 CY8C6248AZI-S2D14 CY8C6248BZI-S2D44 CY8C6248AZI-S2D44 CY8C6248FNI-S2D43 CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245FNI-S3D71 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CYB06445LQI-S3D42 CY8C6245FNI-S3D41 CY8C6245AZI-S3D12 CY8C6245LQI-S3D12 CY8C6245FNI-S3D11 CY8C6245W-S3D72 -CY_DEVICES_WITH_CRYPTO=CY8C6116BZI-F54 CY8C6137BZI-F54 CY8C6247BZI-D44 CY8C6247BZI-D54 CY8C6316BZI-BLF53 CY8C6347BZI-BLD43 CY8C6347BZI-BLD53 CY8C6347FMI-BLD43 CY8C6347FMI-BLD53 CY8C637BZI-MD76 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C68237BZ-BLE CY8C68237FM-BLE CY8C6347BZI-BUD43 CY8C6347BZI-BUD53 CY8C6136FDI-F42 CY8C6247FDI-D52 CY8C6136FTI-F42 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6316BZI-BLF54 CY8C6347BZI-BLD44 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CYBLE-416045-02 CY8C6347FMI-BUD53 CY8C6347FMI-BUD43 CY8C6137WI-F54 CY8C6247WI-D54 CY8C6336LQI-BLF42 CY8C6347LQI-BLD52 CYB06447BZI-BLD54 CYB06447BZI-BLD53 CYB06447BZI-D54 CY8C624ABZI-D44 CY8C624AAZI-D44 CY8C624AFNI-D43 CY8C6248BZI-D44 CY8C6248AZI-D44 CY8C6248FNI-D43 CY8C624ALQI-D42 CYB0644ABZI-S2D44 CYS0644ABZI-S2D44 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624AAZI-S2D44 CY8C624AFNI-S2D43 CY8C6248BZI-S2D44 CY8C6248AZI-S2D44 CY8C6248FNI-S2D43 CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245FNI-S3D71 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CYB06445LQI-S3D42 CY8C6245FNI-S3D41 CY8C6245W-S3D72 +CY_DEVICES_WITH_FS_USB=CY8C6036BZI-F04 CY8C6016BZI-F04 CY8C6116BZI-F54 CY8C6136BZI-F14 CY8C6136BZI-F34 CY8C6137BZI-F14 CY8C6137BZI-F34 CY8C6137BZI-F54 CY8C6117BZI-F34 CY8C6246BZI-D04 CY8C6247BZI-D44 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C637BZI-MD76 CY8C6137FDI-F02 CY8C6117FDI-F02 CY8C6247FDI-D02 CY8C6247FDI-D32 CY8C6336BZI-BUD13 CY8C6347BZI-BUD43 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 CY8C6136FDI-F42 CY8C6247FDI-D52 CY8C6136FTI-F42 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6336BZI-BLF04 CY8C6316BZI-BLF04 CY8C6316BZI-BLF54 CY8C6336BZI-BLD14 CY8C6347BZI-BLD44 CY8C6347BZI-BLD34 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CY8C6347FMI-BUD53 CY8C6347FMI-BUD13 CY8C6347FMI-BUD43 CY8C6347FMI-BUD33 CY8C6137WI-F54 CY8C6117WI-F34 CY8C6247WI-D54 CYB06447BZI-BLD54 CYB06447BZI-D54 CYB0644ABZI-S2D44 CYS0644ABZI-S2D44 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624AAZI-S2D44 CY8C624AFNI-S2D43 CY8C624ABZI-S2D04 CY8C624ABZI-S2D14 CY8C624AAZI-S2D14 CY8C6248AZI-S2D14 CY8C6248BZI-S2D44 CY8C6248AZI-S2D44 CY8C6248FNI-S2D43 CY8C614ABZI-S2F04 CY8C614AAZI-S2F04 CY8C614AFNI-S2F03 CY8C614AAZI-S2F14 CY8C614ABZI-S2F44 CY8C614AAZI-S2F44 CY8C614AFNI-S2F43 CY8C6148BZI-S2F44 CY8C6148AZI-S2F44 CY8C6148FNI-S2F43 CY8C624ABZI-D44 CY8C624AAZI-D44 CY8C624AFNI-D43 CY8C624ABZI-D04 CY8C624ABZI-D14 CY8C624AAZI-D14 CY8C6248AZI-D14 CY8C6248BZI-D44 CY8C6248AZI-D44 CY8C6248FNI-D43 CY8C624ALQI-D42 CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245AZI-S3D62 CY8C6245LQI-S3D62 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CYB06445LQI-S3D42 CY8C6245AZI-S3D12 CY8C6245LQI-S3D12 CY8C6245AZI-S3D02 CY8C6245LQI-S3D02 CY8C6245WI-S3D72 CY8C6145AZI-S3F72 CY8C6145LQI-S3F72 CY8C6145AZI-S3F62 CY8C6145LQI-S3F62 CY8C6145AZI-S3F42 CY8C6145LQI-S3F42 CY8C6145AZI-S3F12 CY8C6145LQI-S3F12 CY8C6145AZI-S3F02 CY8C6145LQI-S3F02 +CY_DEVICES_WITH_CAPSENSE=CY8C6116BZI-F54 CY8C6136BZI-F14 CY8C6136BZI-F34 CY8C6137BZI-F14 CY8C6137BZI-F34 CY8C6137BZI-F54 CY8C6117BZI-F34 CY8C6247BZI-D44 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C6316BZI-BLF53 CY8C6336BZI-BLD13 CY8C6347BZI-BLD43 CY8C6347BZI-BLD33 CY8C6347BZI-BLD53 CY8C6347FMI-BLD13 CY8C6347FMI-BLD43 CY8C6347FMI-BLD33 CY8C6347FMI-BLD53 CY8C637BZI-MD76 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C68237BZ-BLE CY8C68237FM-BLE CY8C6247FDI-D32 CY8C6336BZI-BUD13 CY8C6347BZI-BUD43 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 CY8C6337BZI-BLF13 CY8C6136FDI-F42 CY8C6247FDI-D52 CY8C6136FTI-F42 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6316BZI-BLF54 CY8C6336BZI-BLD14 CY8C6347BZI-BLD44 CY8C6347BZI-BLD34 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CYBLE-416045-02 CY8C6347FMI-BUD53 CY8C6347FMI-BUD13 CY8C6347FMI-BUD43 CY8C6347FMI-BUD33 CY8C6137WI-F54 CY8C6117WI-F34 CY8C6247WI-D54 CY8C6336LQI-BLF42 CY8C6347LQI-BLD52 CYB06447BZI-BLD54 CYB06447BZI-BLD53 CYB06447BZI-D54 CYB0644ABZI-S2D44 CYS0644ABZI-S2D44 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624AAZI-S2D44 CY8C624AFNI-S2D43 CY8C624ABZI-S2D14 CY8C624AAZI-S2D14 CY8C6248AZI-S2D14 CY8C6248BZI-S2D44 CY8C6248AZI-S2D44 CY8C6248FNI-S2D43 CY8C614AAZI-S2F14 CY8C614ABZI-S2F44 CY8C614AAZI-S2F44 CY8C614AFNI-S2F43 CY8C6148BZI-S2F44 CY8C6148AZI-S2F44 CY8C6148FNI-S2F43 CY8C624ABZI-D44 CY8C624AAZI-D44 CY8C624AFNI-D43 CY8C624ABZI-D14 CY8C624AAZI-D14 CY8C6248AZI-D14 CY8C6248BZI-D44 CY8C6248AZI-D44 CY8C6248FNI-D43 CY8C624ALQI-D42 CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245FNI-S3D71 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CYB06445LQI-S3D42 CY8C6245FNI-S3D41 CY8C6245AZI-S3D12 CY8C6245LQI-S3D12 CY8C6245FNI-S3D11 CY8C6245WI-S3D72 CY8C6145AZI-S3F72 CY8C6145LQI-S3F72 CY8C6145FNI-S3F71 CY8C6145AZI-S3F42 CY8C6145LQI-S3F42 CY8C6145FNI-S3F41 CY8C6145AZI-S3F12 CY8C6145LQI-S3F12 CY8C6145FNI-S3F11 +CY_DEVICES_WITH_CRYPTO=CY8C6116BZI-F54 CY8C6137BZI-F54 CY8C6247BZI-D44 CY8C6247BZI-D54 CY8C6316BZI-BLF53 CY8C6347BZI-BLD43 CY8C6347BZI-BLD53 CY8C6347FMI-BLD43 CY8C6347FMI-BLD53 CY8C637BZI-MD76 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C68237BZ-BLE CY8C68237FM-BLE CY8C6347BZI-BUD43 CY8C6347BZI-BUD53 CY8C6136FDI-F42 CY8C6247FDI-D52 CY8C6136FTI-F42 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6316BZI-BLF54 CY8C6347BZI-BLD44 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CYBLE-416045-02 CY8C6347FMI-BUD53 CY8C6347FMI-BUD43 CY8C6137WI-F54 CY8C6247WI-D54 CY8C6336LQI-BLF42 CY8C6347LQI-BLD52 CYB06447BZI-BLD54 CYB06447BZI-BLD53 CYB06447BZI-D54 CYB0644ABZI-S2D44 CYS0644ABZI-S2D44 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624AAZI-S2D44 CY8C624AFNI-S2D43 CY8C6248BZI-S2D44 CY8C6248AZI-S2D44 CY8C6248FNI-S2D43 CY8C614ABZI-S2F44 CY8C614AAZI-S2F44 CY8C614AFNI-S2F43 CY8C6148BZI-S2F44 CY8C6148AZI-S2F44 CY8C6148FNI-S2F43 CY8C624ABZI-D44 CY8C624AAZI-D44 CY8C624AFNI-D43 CY8C6248BZI-D44 CY8C6248AZI-D44 CY8C6248FNI-D43 CY8C624ALQI-D42 CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245FNI-S3D71 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CYB06445LQI-S3D42 CY8C6245FNI-S3D41 CY8C6245WI-S3D72 CY8C6145AZI-S3F72 CY8C6145LQI-S3F72 CY8C6145FNI-S3F71 CY8C6145AZI-S3F42 CY8C6145LQI-S3F42 CY8C6145FNI-S3F41 CY_DEVICES_SECURE=CYB06447BZI-BLD54 CYB06447BZI-BLD53 CYB06447BZI-D54 CYB0644ABZI-S2D44 CYS0644ABZI-S2D44 CYB06445LQI-S3D42 # Different classifications of devices. CY_DEVICES_WITH_DIE_PSOC6ABLE2=CY8C6036BZI-F04 CY8C6016BZI-F04 CY8C6116BZI-F54 CY8C6136BZI-F14 CY8C6136BZI-F34 CY8C6137BZI-F14 CY8C6137BZI-F34 CY8C6137BZI-F54 CY8C6117BZI-F34 CY8C6246BZI-D04 CY8C6247BZI-D44 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C6336BZI-BLF03 CY8C6316BZI-BLF03 CY8C6316BZI-BLF53 CY8C6336BZI-BLD13 CY8C6347BZI-BLD43 CY8C6347BZI-BLD33 CY8C6347BZI-BLD53 CY8C6347FMI-BLD13 CY8C6347FMI-BLD43 CY8C6347FMI-BLD33 CY8C6347FMI-BLD53 CY8C637BZI-MD76 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C68237BZ-BLE CY8C68237FM-BLE CY8C6137FDI-F02 CY8C6117FDI-F02 CY8C6247FDI-D02 CY8C6247FDI-D32 CY8C6336BZI-BUD13 CY8C6347BZI-BUD43 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 CY8C6337BZI-BLF13 CY8C6136FDI-F42 CY8C6247FDI-D52 CY8C6136FTI-F42 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6336BZI-BLF04 CY8C6316BZI-BLF04 CY8C6316BZI-BLF54 CY8C6336BZI-BLD14 CY8C6347BZI-BLD44 CY8C6347BZI-BLD34 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CYBLE-416045-02 CY8C6347FMI-BUD53 CY8C6347FMI-BUD13 CY8C6347FMI-BUD43 CY8C6347FMI-BUD33 CY8C6137WI-F54 CY8C6117WI-F34 CY8C6247WI-D54 CY8C6336LQI-BLF02 CY8C6336LQI-BLF42 CY8C6347LQI-BLD52 CYB06447BZI-BLD54 CYB06447BZI-BLD53 CYB06447BZI-D54 -CY_DEVICES_WITH_DIE_PSOC6A2M=CY8C624ABZI-D44 CY8C624AAZI-D44 CY8C624AFNI-D43 CY8C624ABZI-D04 CY8C624ABZI-D14 CY8C624AAZI-D14 CY8C6248AZI-D14 CY8C6248BZI-D44 CY8C6248AZI-D44 CY8C6248FNI-D43 CY8C624ALQI-D42 CYB0644ABZI-S2D44 CYS0644ABZI-S2D44 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624AAZI-S2D44 CY8C624AFNI-S2D43 CY8C624ABZI-S2D04 CY8C624ABZI-S2D14 CY8C624AAZI-S2D14 CY8C6248AZI-S2D14 CY8C6248BZI-S2D44 CY8C6248AZI-S2D44 CY8C6248FNI-S2D43 -CY_DEVICES_WITH_DIE_PSOC6A512K=CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245FNI-S3D71 CY8C6245AZI-S3D62 CY8C6245LQI-S3D62 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CYB06445LQI-S3D42 CY8C6245FNI-S3D41 CY8C6245AZI-S3D12 CY8C6245LQI-S3D12 CY8C6245FNI-S3D11 CY8C6245AZI-S3D02 CY8C6245LQI-S3D02 CY8C6245W-S3D72 +CY_DEVICES_WITH_DIE_PSOC6A2M=CYB0644ABZI-S2D44 CYS0644ABZI-S2D44 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624AAZI-S2D44 CY8C624AFNI-S2D43 CY8C624ABZI-S2D04 CY8C624ABZI-S2D14 CY8C624AAZI-S2D14 CY8C6248AZI-S2D14 CY8C6248BZI-S2D44 CY8C6248AZI-S2D44 CY8C6248FNI-S2D43 CY8C614ABZI-S2F04 CY8C614AAZI-S2F04 CY8C614AFNI-S2F03 CY8C614AAZI-S2F14 CY8C614ABZI-S2F44 CY8C614AAZI-S2F44 CY8C614AFNI-S2F43 CY8C6148BZI-S2F44 CY8C6148AZI-S2F44 CY8C6148FNI-S2F43 CY8C624ABZI-D44 CY8C624AAZI-D44 CY8C624AFNI-D43 CY8C624ABZI-D04 CY8C624ABZI-D14 CY8C624AAZI-D14 CY8C6248AZI-D14 CY8C6248BZI-D44 CY8C6248AZI-D44 CY8C6248FNI-D43 CY8C624ALQI-D42 +CY_DEVICES_WITH_DIE_PSOC6A512K=CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245FNI-S3D71 CY8C6245AZI-S3D62 CY8C6245LQI-S3D62 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CYB06445LQI-S3D42 CY8C6245FNI-S3D41 CY8C6245AZI-S3D12 CY8C6245LQI-S3D12 CY8C6245FNI-S3D11 CY8C6245AZI-S3D02 CY8C6245LQI-S3D02 CY8C6245WI-S3D72 CY8C6145AZI-S3F72 CY8C6145LQI-S3F72 CY8C6145FNI-S3F71 CY8C6145AZI-S3F62 CY8C6145LQI-S3F62 CY8C6145AZI-S3F42 CY8C6145LQI-S3F42 CY8C6145FNI-S3F41 CY8C6145AZI-S3F12 CY8C6145LQI-S3F12 CY8C6145FNI-S3F11 CY8C6145AZI-S3F02 CY8C6145LQI-S3F02 -CY_DEVICES_WITH_FLASH_KB_512=CY8C6036BZI-F04 CY8C6016BZI-F04 CY8C6116BZI-F54 CY8C6136BZI-F14 CY8C6136BZI-F34 CY8C6246BZI-D04 CY8C6336BZI-BLF03 CY8C6316BZI-BLF03 CY8C6316BZI-BLF53 CY8C6336BZI-BLD13 CY8C6336BZI-BUD13 CY8C6136FDI-F42 CY8C6136FTI-F42 CY8C6336BZI-BLF04 CY8C6316BZI-BLF04 CY8C6316BZI-BLF54 CY8C6336BZI-BLD14 CY8C6336LQI-BLF02 CY8C6336LQI-BLF42 CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245FNI-S3D71 CY8C6245AZI-S3D62 CY8C6245LQI-S3D62 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CY8C6245FNI-S3D41 CY8C6245AZI-S3D12 CY8C6245LQI-S3D12 CY8C6245FNI-S3D11 CY8C6245AZI-S3D02 CY8C6245LQI-S3D02 CY8C6245W-S3D72 -CY_DEVICES_WITH_FLASH_KB_1024=CY8C6137BZI-F14 CY8C6137BZI-F34 CY8C6137BZI-F54 CY8C6117BZI-F34 CY8C6247BZI-D44 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C6347BZI-BLD43 CY8C6347BZI-BLD33 CY8C6347BZI-BLD53 CY8C6347FMI-BLD13 CY8C6347FMI-BLD43 CY8C6347FMI-BLD33 CY8C6347FMI-BLD53 CY8C637BZI-MD76 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C68237BZ-BLE CY8C68237FM-BLE CY8C6137FDI-F02 CY8C6117FDI-F02 CY8C6247FDI-D02 CY8C6247FDI-D32 CY8C6347BZI-BUD43 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 CY8C6337BZI-BLF13 CY8C6247FDI-D52 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6347BZI-BLD44 CY8C6347BZI-BLD34 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CYBLE-416045-02 CY8C6347FMI-BUD53 CY8C6347FMI-BUD13 CY8C6347FMI-BUD43 CY8C6347FMI-BUD33 CY8C6137WI-F54 CY8C6117WI-F34 CY8C6247WI-D54 CY8C6347LQI-BLD52 CY8C6248BZI-D44 CY8C6248AZI-D44 CY8C6248FNI-D43 CY8C6248BZI-S2D44 CY8C6248AZI-S2D44 CY8C6248FNI-S2D43 +CY_DEVICES_WITH_FLASH_KB_512=CY8C6036BZI-F04 CY8C6016BZI-F04 CY8C6116BZI-F54 CY8C6136BZI-F14 CY8C6136BZI-F34 CY8C6246BZI-D04 CY8C6336BZI-BLF03 CY8C6316BZI-BLF03 CY8C6316BZI-BLF53 CY8C6336BZI-BLD13 CY8C6336BZI-BUD13 CY8C6136FDI-F42 CY8C6136FTI-F42 CY8C6336BZI-BLF04 CY8C6316BZI-BLF04 CY8C6316BZI-BLF54 CY8C6336BZI-BLD14 CY8C6336LQI-BLF02 CY8C6336LQI-BLF42 CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245FNI-S3D71 CY8C6245AZI-S3D62 CY8C6245LQI-S3D62 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CY8C6245FNI-S3D41 CY8C6245AZI-S3D12 CY8C6245LQI-S3D12 CY8C6245FNI-S3D11 CY8C6245AZI-S3D02 CY8C6245LQI-S3D02 CY8C6245WI-S3D72 CY8C6145AZI-S3F72 CY8C6145LQI-S3F72 CY8C6145FNI-S3F71 CY8C6145AZI-S3F62 CY8C6145LQI-S3F62 CY8C6145AZI-S3F42 CY8C6145LQI-S3F42 CY8C6145FNI-S3F41 CY8C6145AZI-S3F12 CY8C6145LQI-S3F12 CY8C6145FNI-S3F11 CY8C6145AZI-S3F02 CY8C6145LQI-S3F02 +CY_DEVICES_WITH_FLASH_KB_1024=CY8C6137BZI-F14 CY8C6137BZI-F34 CY8C6137BZI-F54 CY8C6117BZI-F34 CY8C6247BZI-D44 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C6347BZI-BLD43 CY8C6347BZI-BLD33 CY8C6347BZI-BLD53 CY8C6347FMI-BLD13 CY8C6347FMI-BLD43 CY8C6347FMI-BLD33 CY8C6347FMI-BLD53 CY8C637BZI-MD76 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C68237BZ-BLE CY8C68237FM-BLE CY8C6137FDI-F02 CY8C6117FDI-F02 CY8C6247FDI-D02 CY8C6247FDI-D32 CY8C6347BZI-BUD43 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 CY8C6337BZI-BLF13 CY8C6247FDI-D52 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6347BZI-BLD44 CY8C6347BZI-BLD34 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CYBLE-416045-02 CY8C6347FMI-BUD53 CY8C6347FMI-BUD13 CY8C6347FMI-BUD43 CY8C6347FMI-BUD33 CY8C6137WI-F54 CY8C6117WI-F34 CY8C6247WI-D54 CY8C6347LQI-BLD52 CY8C6248BZI-S2D44 CY8C6248AZI-S2D44 CY8C6248FNI-S2D43 CY8C6148BZI-S2F44 CY8C6148AZI-S2F44 CY8C6148FNI-S2F43 CY8C6248BZI-D44 CY8C6248AZI-D44 CY8C6248FNI-D43 CY_DEVICES_WITH_FLASH_KB_832=CYB06447BZI-BLD54 CYB06447BZI-BLD53 CYB06447BZI-D54 -CY_DEVICES_WITH_FLASH_KB_2048=CY8C624ABZI-D44 CY8C624AAZI-D44 CY8C624AFNI-D43 CY8C624ABZI-D04 CY8C624ABZI-D14 CY8C624AAZI-D14 CY8C6248AZI-D14 CY8C624ALQI-D42 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624AAZI-S2D44 CY8C624AFNI-S2D43 CY8C624ABZI-S2D04 CY8C624ABZI-S2D14 CY8C624AAZI-S2D14 CY8C6248AZI-S2D14 CY_DEVICES_WITH_FLASH_KB_1856=CYB0644ABZI-S2D44 CYS0644ABZI-S2D44 +CY_DEVICES_WITH_FLASH_KB_2048=CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624AAZI-S2D44 CY8C624AFNI-S2D43 CY8C624ABZI-S2D04 CY8C624ABZI-S2D14 CY8C624AAZI-S2D14 CY8C6248AZI-S2D14 CY8C614ABZI-S2F04 CY8C614AAZI-S2F04 CY8C614AFNI-S2F03 CY8C614AAZI-S2F14 CY8C614ABZI-S2F44 CY8C614AAZI-S2F44 CY8C614AFNI-S2F43 CY8C624ABZI-D44 CY8C624AAZI-D44 CY8C624AFNI-D43 CY8C624ABZI-D04 CY8C624ABZI-D14 CY8C624AAZI-D14 CY8C6248AZI-D14 CY8C624ALQI-D42 CY_DEVICES_WITH_FLASH_KB_448=CYB06445LQI-S3D42 CY_DEVICES_WITH_SRAM_KB_128=CY8C6036BZI-F04 CY8C6016BZI-F04 CY8C6116BZI-F54 CY8C6136BZI-F14 CY8C6136BZI-F34 CY8C6246BZI-D04 CY8C6336BZI-BLF03 CY8C6316BZI-BLF03 CY8C6316BZI-BLF53 CY8C6336BZI-BLD13 CY8C6336BZI-BUD13 CY8C6136FDI-F42 CY8C6136FTI-F42 CY8C6336BZI-BLF04 CY8C6316BZI-BLF04 CY8C6316BZI-BLF54 CY8C6336BZI-BLD14 CY8C6336LQI-BLF02 CY8C6336LQI-BLF42 CY_DEVICES_WITH_SRAM_KB_288=CY8C6137BZI-F14 CY8C6137BZI-F34 CY8C6137BZI-F54 CY8C6117BZI-F34 CY8C6247BZI-D44 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C6347BZI-BLD43 CY8C6347BZI-BLD33 CY8C6347BZI-BLD53 CY8C6347FMI-BLD13 CY8C6347FMI-BLD43 CY8C6347FMI-BLD33 CY8C6347FMI-BLD53 CY8C637BZI-MD76 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C68237BZ-BLE CY8C68237FM-BLE CY8C6137FDI-F02 CY8C6117FDI-F02 CY8C6247FDI-D02 CY8C6247FDI-D32 CY8C6347BZI-BUD43 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 CY8C6337BZI-BLF13 CY8C6247FDI-D52 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6347BZI-BLD44 CY8C6347BZI-BLD34 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CYBLE-416045-02 CY8C6347FMI-BUD53 CY8C6347FMI-BUD13 CY8C6347FMI-BUD43 CY8C6347FMI-BUD33 CY8C6137WI-F54 CY8C6117WI-F34 CY8C6247WI-D54 CY8C6347LQI-BLD52 CYB06447BZI-BLD54 CYB06447BZI-BLD53 CYB06447BZI-D54 -CY_DEVICES_WITH_SRAM_KB_1024=CY8C624ABZI-D44 CY8C624AAZI-D44 CY8C624AFNI-D43 CY8C624ABZI-D04 CY8C624ABZI-D14 CY8C624AAZI-D14 CY8C6248AZI-D14 CY8C624ALQI-D42 CYB0644ABZI-S2D44 CYS0644ABZI-S2D44 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624AAZI-S2D44 CY8C624AFNI-S2D43 CY8C624ABZI-S2D04 CY8C624ABZI-S2D14 CY8C624AAZI-S2D14 CY8C6248AZI-S2D14 -CY_DEVICES_WITH_SRAM_KB_512=CY8C6248BZI-D44 CY8C6248AZI-D44 CY8C6248FNI-D43 CY8C6248BZI-S2D44 CY8C6248AZI-S2D44 CY8C6248FNI-S2D43 -CY_DEVICES_WITH_SRAM_KB_256=CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245FNI-S3D71 CY8C6245AZI-S3D62 CY8C6245LQI-S3D62 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CYB06445LQI-S3D42 CY8C6245FNI-S3D41 CY8C6245AZI-S3D12 CY8C6245LQI-S3D12 CY8C6245FNI-S3D11 CY8C6245AZI-S3D02 CY8C6245LQI-S3D02 CY8C6245W-S3D72 +CY_DEVICES_WITH_SRAM_KB_1024=CYB0644ABZI-S2D44 CYS0644ABZI-S2D44 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624AAZI-S2D44 CY8C624AFNI-S2D43 CY8C624ABZI-S2D04 CY8C624ABZI-S2D14 CY8C624AAZI-S2D14 CY8C6248AZI-S2D14 CY8C614ABZI-S2F04 CY8C614AAZI-S2F04 CY8C614AFNI-S2F03 CY8C614AAZI-S2F14 CY8C614ABZI-S2F44 CY8C614AAZI-S2F44 CY8C614AFNI-S2F43 CY8C624ABZI-D44 CY8C624AAZI-D44 CY8C624AFNI-D43 CY8C624ABZI-D04 CY8C624ABZI-D14 CY8C624AAZI-D14 CY8C6248AZI-D14 CY8C624ALQI-D42 +CY_DEVICES_WITH_SRAM_KB_512=CY8C6248BZI-S2D44 CY8C6248AZI-S2D44 CY8C6248FNI-S2D43 CY8C6148BZI-S2F44 CY8C6148AZI-S2F44 CY8C6148FNI-S2F43 CY8C6248BZI-D44 CY8C6248AZI-D44 CY8C6248FNI-D43 +CY_DEVICES_WITH_SRAM_KB_256=CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245FNI-S3D71 CY8C6245AZI-S3D62 CY8C6245LQI-S3D62 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CYB06445LQI-S3D42 CY8C6245FNI-S3D41 CY8C6245AZI-S3D12 CY8C6245LQI-S3D12 CY8C6245FNI-S3D11 CY8C6245AZI-S3D02 CY8C6245LQI-S3D02 CY8C6245WI-S3D72 CY8C6145AZI-S3F72 CY8C6145LQI-S3F72 CY8C6145FNI-S3F71 CY8C6145AZI-S3F62 CY8C6145LQI-S3F62 CY8C6145AZI-S3F42 CY8C6145LQI-S3F42 CY8C6145FNI-S3F41 CY8C6145AZI-S3F12 CY8C6145LQI-S3F12 CY8C6145FNI-S3F11 CY8C6145AZI-S3F02 CY8C6145LQI-S3F02 -CY_DEVICES_WITH_MAX_SPEED_MHZ_150=CY8C6036BZI-F04 CY8C6136BZI-F14 CY8C6136BZI-F34 CY8C6137BZI-F14 CY8C6137BZI-F34 CY8C6137BZI-F54 CY8C6246BZI-D04 CY8C6247BZI-D44 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C6336BZI-BLF03 CY8C6336BZI-BLD13 CY8C6347BZI-BLD43 CY8C6347BZI-BLD33 CY8C6347BZI-BLD53 CY8C6347FMI-BLD13 CY8C6347FMI-BLD43 CY8C6347FMI-BLD33 CY8C6347FMI-BLD53 CY8C637BZI-MD76 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C68237BZ-BLE CY8C68237FM-BLE CY8C6137FDI-F02 CY8C6247FDI-D02 CY8C6247FDI-D32 CY8C6336BZI-BUD13 CY8C6347BZI-BUD43 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 CY8C6337BZI-BLF13 CY8C6136FDI-F42 CY8C6247FDI-D52 CY8C6136FTI-F42 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6336BZI-BLF04 CY8C6336BZI-BLD14 CY8C6347BZI-BLD44 CY8C6347BZI-BLD34 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CYBLE-416045-02 CY8C6347FMI-BUD53 CY8C6347FMI-BUD13 CY8C6347FMI-BUD43 CY8C6347FMI-BUD33 CY8C6137WI-F54 CY8C6247WI-D54 CY8C6336LQI-BLF02 CY8C6336LQI-BLF42 CY8C6347LQI-BLD52 CYB06447BZI-BLD54 CYB06447BZI-BLD53 CYB06447BZI-D54 CY8C624ABZI-D44 CY8C624AAZI-D44 CY8C624AFNI-D43 CY8C624ABZI-D04 CY8C624ABZI-D14 CY8C624AAZI-D14 CY8C6248AZI-D14 CY8C6248BZI-D44 CY8C6248AZI-D44 CY8C6248FNI-D43 CY8C624ALQI-D42 CYB0644ABZI-S2D44 CYS0644ABZI-S2D44 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624AAZI-S2D44 CY8C624AFNI-S2D43 CY8C624ABZI-S2D04 CY8C624ABZI-S2D14 CY8C624AAZI-S2D14 CY8C6248AZI-S2D14 CY8C6248BZI-S2D44 CY8C6248AZI-S2D44 CY8C6248FNI-S2D43 CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245FNI-S3D71 CY8C6245AZI-S3D62 CY8C6245LQI-S3D62 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CYB06445LQI-S3D42 CY8C6245FNI-S3D41 CY8C6245AZI-S3D12 CY8C6245LQI-S3D12 CY8C6245FNI-S3D11 CY8C6245AZI-S3D02 CY8C6245LQI-S3D02 CY8C6245W-S3D72 +CY_DEVICES_WITH_MAX_SPEED_MHZ_150=CY8C6036BZI-F04 CY8C6136BZI-F14 CY8C6136BZI-F34 CY8C6137BZI-F14 CY8C6137BZI-F34 CY8C6137BZI-F54 CY8C6246BZI-D04 CY8C6247BZI-D44 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C6336BZI-BLF03 CY8C6336BZI-BLD13 CY8C6347BZI-BLD43 CY8C6347BZI-BLD33 CY8C6347BZI-BLD53 CY8C6347FMI-BLD13 CY8C6347FMI-BLD43 CY8C6347FMI-BLD33 CY8C6347FMI-BLD53 CY8C637BZI-MD76 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C68237BZ-BLE CY8C68237FM-BLE CY8C6137FDI-F02 CY8C6247FDI-D02 CY8C6247FDI-D32 CY8C6336BZI-BUD13 CY8C6347BZI-BUD43 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 CY8C6337BZI-BLF13 CY8C6136FDI-F42 CY8C6247FDI-D52 CY8C6136FTI-F42 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6336BZI-BLF04 CY8C6336BZI-BLD14 CY8C6347BZI-BLD44 CY8C6347BZI-BLD34 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CYBLE-416045-02 CY8C6347FMI-BUD53 CY8C6347FMI-BUD13 CY8C6347FMI-BUD43 CY8C6347FMI-BUD33 CY8C6137WI-F54 CY8C6247WI-D54 CY8C6336LQI-BLF02 CY8C6336LQI-BLF42 CY8C6347LQI-BLD52 CYB06447BZI-BLD54 CYB06447BZI-BLD53 CYB06447BZI-D54 CYB0644ABZI-S2D44 CYS0644ABZI-S2D44 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624AAZI-S2D44 CY8C624AFNI-S2D43 CY8C624ABZI-S2D04 CY8C624ABZI-S2D14 CY8C624AAZI-S2D14 CY8C6248AZI-S2D14 CY8C6248BZI-S2D44 CY8C6248AZI-S2D44 CY8C6248FNI-S2D43 CY8C614ABZI-S2F04 CY8C614AAZI-S2F04 CY8C614AFNI-S2F03 CY8C614AAZI-S2F14 CY8C614ABZI-S2F44 CY8C614AAZI-S2F44 CY8C614AFNI-S2F43 CY8C6148BZI-S2F44 CY8C6148AZI-S2F44 CY8C6148FNI-S2F43 CY8C624ABZI-D44 CY8C624AAZI-D44 CY8C624AFNI-D43 CY8C624ABZI-D04 CY8C624ABZI-D14 CY8C624AAZI-D14 CY8C6248AZI-D14 CY8C6248BZI-D44 CY8C6248AZI-D44 CY8C6248FNI-D43 CY8C624ALQI-D42 CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245FNI-S3D71 CY8C6245AZI-S3D62 CY8C6245LQI-S3D62 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CYB06445LQI-S3D42 CY8C6245FNI-S3D41 CY8C6245AZI-S3D12 CY8C6245LQI-S3D12 CY8C6245FNI-S3D11 CY8C6245AZI-S3D02 CY8C6245LQI-S3D02 CY8C6245WI-S3D72 CY8C6145AZI-S3F72 CY8C6145LQI-S3F72 CY8C6145FNI-S3F71 CY8C6145AZI-S3F62 CY8C6145LQI-S3F62 CY8C6145AZI-S3F42 CY8C6145LQI-S3F42 CY8C6145FNI-S3F41 CY8C6145AZI-S3F12 CY8C6145LQI-S3F12 CY8C6145FNI-S3F11 CY8C6145AZI-S3F02 CY8C6145LQI-S3F02 CY_DEVICES_WITH_MAX_SPEED_MHZ_50=CY8C6016BZI-F04 CY8C6116BZI-F54 CY8C6117BZI-F34 CY8C6316BZI-BLF03 CY8C6316BZI-BLF53 CY8C6117FDI-F02 CY8C6316BZI-BLF04 CY8C6316BZI-BLF54 CY8C6117WI-F34 -CY_DEVICES_WITH_PACKAGE_124-BGA=CY8C6036BZI-F04 CY8C6016BZI-F04 CY8C6116BZI-F54 CY8C6136BZI-F14 CY8C6136BZI-F34 CY8C6137BZI-F14 CY8C6137BZI-F34 CY8C6137BZI-F54 CY8C6117BZI-F34 CY8C6246BZI-D04 CY8C6247BZI-D44 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C637BZI-MD76 CY8C6247BZI-AUD54 CY8C6247BFI-D54 CY8C6137WI-F54 CY8C6117WI-F34 CY8C6247WI-D54 CYB06447BZI-D54 CY8C624ABZI-D44 CY8C624ABZI-D04 CY8C624ABZI-D14 CY8C6248BZI-D44 CYB0644ABZI-S2D44 CYS0644ABZI-S2D44 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624ABZI-S2D04 CY8C624ABZI-S2D14 CY8C6248BZI-S2D44 +CY_DEVICES_WITH_PACKAGE_124-BGA=CY8C6036BZI-F04 CY8C6016BZI-F04 CY8C6116BZI-F54 CY8C6136BZI-F14 CY8C6136BZI-F34 CY8C6137BZI-F14 CY8C6137BZI-F34 CY8C6137BZI-F54 CY8C6117BZI-F34 CY8C6246BZI-D04 CY8C6247BZI-D44 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C637BZI-MD76 CY8C6247BZI-AUD54 CY8C6247BFI-D54 CY8C6137WI-F54 CY8C6117WI-F34 CY8C6247WI-D54 CYB06447BZI-D54 CYB0644ABZI-S2D44 CYS0644ABZI-S2D44 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624ABZI-S2D04 CY8C624ABZI-S2D14 CY8C6248BZI-S2D44 CY8C614ABZI-S2F04 CY8C614ABZI-S2F44 CY8C6148BZI-S2F44 CY8C624ABZI-D44 CY8C624ABZI-D04 CY8C624ABZI-D14 CY8C6248BZI-D44 CY_DEVICES_WITH_PACKAGE_116-BGA-BLE=CY8C6336BZI-BLF03 CY8C6316BZI-BLF03 CY8C6316BZI-BLF53 CY8C6336BZI-BLD13 CY8C6347BZI-BLD43 CY8C6347BZI-BLD33 CY8C6347BZI-BLD53 CY8C637BZI-BLD74 CY8C68237BZ-BLE CY8C6337BZI-BLF13 CYB06447BZI-BLD53 CY_DEVICES_WITH_PACKAGE_104-M-CSP-BLE=CY8C6347FMI-BLD13 CY8C6347FMI-BLD43 CY8C6347FMI-BLD33 CY8C6347FMI-BLD53 CY8C637FMI-BLD73 CY8C68237FM-BLE CY_DEVICES_WITH_PACKAGE_80-WLCSP=CY8C6137FDI-F02 CY8C6117FDI-F02 CY8C6247FDI-D02 CY8C6247FDI-D32 CY8C6136FDI-F42 CY8C6247FDI-D52 CY8C6136FTI-F42 CY8C6247FTI-D52 @@ -40,9 +40,10 @@ CY_DEVICES_WITH_PACKAGE_124-BGA-SIP=CY8C6336BZI-BLF04 CY8C6316BZI-BLF04 CY8C6316 CY_DEVICES_WITH_PACKAGE_43-SMT=CYBLE-416045-02 CY_DEVICES_WITH_PACKAGE_104-M-CSP-BLE-USB=CY8C6347FMI-BUD53 CY8C6347FMI-BUD13 CY8C6347FMI-BUD43 CY8C6347FMI-BUD33 CY_DEVICES_WITH_PACKAGE_68-QFN-BLE=CY8C6336LQI-BLF02 CY8C6336LQI-BLF42 CY8C6347LQI-BLD52 -CY_DEVICES_WITH_PACKAGE_128-TQFP=CY8C624AAZI-D44 CY8C624AAZI-D14 CY8C6248AZI-D14 CY8C6248AZI-D44 CY8C624AAZI-S2D44 CY8C624AAZI-S2D14 CY8C6248AZI-S2D14 CY8C6248AZI-S2D44 -CY_DEVICES_WITH_PACKAGE_100-WLCSP=CY8C624AFNI-D43 CY8C6248FNI-D43 CY8C624AFNI-S2D43 CY8C6248FNI-S2D43 -CY_DEVICES_WITH_PACKAGE_68-QFN=CY8C624ALQI-D42 CY8C6245LQI-S3D72 CY8C6245LQI-S3D62 CY8C6245LQI-S3D42 CYB06445LQI-S3D42 CY8C6245LQI-S3D12 CY8C6245LQI-S3D02 -CY_DEVICES_WITH_PACKAGE_100-TQFP=CY8C6245AZI-S3D72 CY8C6245AZI-S3D62 CY8C6245AZI-S3D42 CY8C6245AZI-S3D12 CY8C6245AZI-S3D02 CY8C6245W-S3D72 -CY_DEVICES_WITH_PACKAGE_49-WLCSP=CY8C6245FNI-S3D71 CY8C6245FNI-S3D41 CY8C6245FNI-S3D11 +CY_DEVICES_WITH_PACKAGE_128-TQFP=CY8C624AAZI-S2D44 CY8C624AAZI-S2D14 CY8C6248AZI-S2D14 CY8C6248AZI-S2D44 CY8C614AAZI-S2F04 CY8C614AAZI-S2F14 CY8C614AAZI-S2F44 CY8C6148AZI-S2F44 CY8C624AAZI-D44 CY8C624AAZI-D14 CY8C6248AZI-D14 CY8C6248AZI-D44 +CY_DEVICES_WITH_PACKAGE_100-WLCSP=CY8C624AFNI-S2D43 CY8C6248FNI-S2D43 CY8C614AFNI-S2F03 CY8C614AFNI-S2F43 CY8C6148FNI-S2F43 CY8C624AFNI-D43 CY8C6248FNI-D43 +CY_DEVICES_WITH_PACKAGE_68-QFN=CY8C624ALQI-D42 CY8C6245LQI-S3D72 CY8C6245LQI-S3D62 CY8C6245LQI-S3D42 CYB06445LQI-S3D42 CY8C6245LQI-S3D12 CY8C6245LQI-S3D02 CY8C6145LQI-S3F72 CY8C6145LQI-S3F62 CY8C6145LQI-S3F42 CY8C6145LQI-S3F12 CY8C6145LQI-S3F02 +CY_DEVICES_WITH_PACKAGE_100-TQFP=CY8C6245AZI-S3D72 CY8C6245AZI-S3D62 CY8C6245AZI-S3D42 CY8C6245AZI-S3D12 CY8C6245AZI-S3D02 CY8C6145AZI-S3F72 CY8C6145AZI-S3F62 CY8C6145AZI-S3F42 CY8C6145AZI-S3F12 CY8C6145AZI-S3F02 +CY_DEVICES_WITH_PACKAGE_49-WLCSP=CY8C6245FNI-S3D71 CY8C6245FNI-S3D41 CY8C6245FNI-S3D11 CY8C6145FNI-S3F71 CY8C6145FNI-S3F41 CY8C6145FNI-S3F11 +CY_DEVICES_WITH_PACKAGE_KGD=CY8C6245WI-S3D72 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/version.dat b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/version.dat index 90dd74527c..4e0b7bf12f 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/version.dat +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/version.dat @@ -1 +1 @@ -1.2.0.300 +1.2.0.370 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/version.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/version.xml index bc261c6090..a0729c2a6c 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/version.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/version.xml @@ -1 +1 @@ -1.2.0.300 +1.2.0.370 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/version.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/version.xml index a9cb8609c5..61ef2216a6 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/version.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/version.xml @@ -1 +1 @@ -1.6.0.3875 +1.6.0.4172
VersionChangesReason for Change
2.50Fixed the \ref Cy_SCB_SPI_SetActiveSlaveSelectPolarity function to +* properly configure the polarity of the slave select line. \ref Cy_SCB_SPI_SetActiveSlaveSelectPolarity function works incorrectly.
2.40.2Minor documentation updates.Documentation enhancement.
VersionChangesReason for Change
2.60Updated the following functions for the PSoC64 devices: +* Updated the following functions for the PSoC 64 devices: * \ref Cy_SysLib_ClearFlashCacheAndBuffer, \ref Cy_SysLib_ClearResetReason, * \ref Cy_SysLib_SetWaitStates. -* Added PSoC64 device support.Added PSoC 64 device support.
Minor documentation updates.
5.10 -* Updated the following functions for the PSoC64 devices: +* Updated the following functions for the PSoC 64 devices: * \ref Cy_SysPm_CpuEnterDeepSleep(), \ref Cy_SysPm_SystemEnterLp(), * \ref Cy_SysPm_SystemEnterUlp, \ref Cy_SysPm_SystemEnterHibernate, * \ref Cy_SysPm_SetHibernateWakeupSource, @@ -735,7 +735,7 @@ * \ref Cy_SysPm_SystemSetNormalRegulatorCurrent, * \ref Cy_SysPm_LdoSetVoltage, \ref Cy_SysPm_LdoSetMode, * \ref Cy_SysPm_BuckEnable, \ref Cy_SysPm_BuckSetVoltage1, -* Following functions are updated as unavailble for PSoC64 devices: +* Following functions are updated as unavailble for PSoC 64 devices: * \ref Cy_SysPm_WriteVoltageBitForFlash, \ref Cy_SysPm_SaveRegisters, * \ref Cy_SysPm_RestoreRegisters, * \ref Cy_SysPm_BuckSetVoltage2, \ref Cy_SysPm_BuckEnableVoltage2, @@ -1290,6 +1290,9 @@ #include "cy_device.h" #include "cy_device_headers.h" #include "cy_syslib.h" +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + #include "cy_pra.h" +#endif /* #if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ #ifdef __cplusplus extern "C" { @@ -1794,6 +1797,15 @@ typedef struct uint32_t CY_SYSPM_CM0_CLOCK_CTL_REG; /**< CPUSS CM0+ clock control register */ uint32_t CY_SYSPM_CM4_CLOCK_CTL_REG; /**< CPUSS CM4 clock control register */ } cy_stc_syspm_backup_regs_t; + +#if (defined(CY_DEVICE_SECURE)) +/** PRA structure for Cy_SysPm_BuckSetVoltage2 function parameters */ +typedef struct +{ + cy_en_syspm_buck_voltage2_t praVoltage; /**< The voltage of the Buck regulator output 2 */ + bool praWaitToSettle; /**< Enable/disable the delay after setting a higher voltage */ +} cy_stc_pra_voltage2_t; +#endif /* (defined(CY_DEVICE_SECURE)) */ /** \} group_syspm_data_structures */ /** @@ -1911,10 +1923,8 @@ cy_en_syspm_status_t Cy_SysPm_BuckSetVoltage1(cy_en_syspm_buck_voltage1_t voltag __STATIC_INLINE cy_en_syspm_buck_voltage1_t Cy_SysPm_BuckGetVoltage1(void); void Cy_SysPm_BuckSetVoltage2(cy_en_syspm_buck_voltage2_t voltage, bool waitToSettle); __STATIC_INLINE cy_en_syspm_buck_voltage2_t Cy_SysPm_BuckGetVoltage2(void); -#if !((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) void Cy_SysPm_BuckEnableVoltage2(void); __STATIC_INLINE void Cy_SysPm_BuckDisableVoltage2(void); -#endif /* !((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ __STATIC_INLINE void Cy_SysPm_BuckSetVoltage2HwControl(bool hwControl); __STATIC_INLINE bool Cy_SysPm_BuckIsVoltage2HwControlled(void); bool Cy_SysPm_BuckIsOutputEnabled(cy_en_syspm_buck_out_t output); @@ -2226,7 +2236,6 @@ __STATIC_INLINE cy_en_syspm_buck_voltage2_t Cy_SysPm_BuckGetVoltage2(void) } -#if !((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) /******************************************************************************* * Function Name: Cy_SysPm_BuckDisableVoltage2 ****************************************************************************//** @@ -2252,13 +2261,18 @@ __STATIC_INLINE cy_en_syspm_buck_voltage2_t Cy_SysPm_BuckGetVoltage2(void) *******************************************************************************/ __STATIC_INLINE void Cy_SysPm_BuckDisableVoltage2(void) { +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + CY_PRA_FUNCTION_CALL_VOID_VOID(CY_PRA_MSG_TYPE_SECURE_ONLY, + CY_PRA_PM_FUNC_BUCK_DISABLE_VOLTAGE2); +#else if (0U != cy_device->sysPmSimoPresent) { /* Disable the Vbuck2 output */ SRSS_PWR_BUCK_CTL2 &= (uint32_t) ~_VAL2FLD(SRSS_PWR_BUCK_CTL2_BUCK_OUT2_EN, 1U); } +#endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ } -#endif /* !((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ + /******************************************************************************* @@ -2287,7 +2301,11 @@ __STATIC_INLINE void Cy_SysPm_BuckDisableVoltage2(void) *******************************************************************************/ __STATIC_INLINE void Cy_SysPm_BuckSetVoltage2HwControl(bool hwControl) { -#if !((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + CY_PRA_FUNCTION_CALL_VOID_PARAM(CY_PRA_MSG_TYPE_SECURE_ONLY, + CY_PRA_PM_FUNC_BUCK_VOLTAGE2_HW_CTRL, + hwControl); +#else bool isBuckEnabled = Cy_SysPm_BuckIsEnabled(); if ((0U != cy_device->sysPmSimoPresent) && isBuckEnabled) @@ -2301,9 +2319,7 @@ __STATIC_INLINE void Cy_SysPm_BuckSetVoltage2HwControl(bool hwControl) SRSS_PWR_BUCK_CTL2 &= (uint32_t) ~_VAL2FLD(SRSS_PWR_BUCK_CTL2_BUCK_OUT2_HW_SEL, 1U); } } -#else - (void)hwControl; -#endif /* !((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ +#endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_systick.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_systick.h index db48014f5d..f78f333504 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_systick.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_systick.h @@ -82,11 +82,11 @@ *
VersionChangesReason for Change
1.20.Updated Cy_SysTick_SetClockSource() for the PSoC64 devices, +* Updated Cy_SysTick_SetClockSource() for the PSoC 64 devices, * so that passing any other value than CY_SYSTICK_CLOCK_SOURCE_CLK_CPU * will not affect clock source and it will be as * \ref Cy_SysTick_GetClockSource() reports.Added PSoC64 devices support.Added PSoC 64 devices support.
Minor documentation updates.
VersionChangesReason for Change
1.30Updated the following functions for the PSoC64 devices: \ref Cy_WDT_ClearInterrupt(), +* Updated the following functions for the PSoC 64 devices: \ref Cy_WDT_ClearInterrupt(), * \ref Cy_WDT_MaskInterrupt(), and \ref Cy_WDT_UnmaskInterrupt().Added PSoC64 device support.Added PSoC 64 device support.
Minor documentation updates.