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Fixed style and build issue

pull/1547/head
Parthasarathy.S 2016-02-14 21:31:51 +05:30
parent 86b8516024
commit a8e52a9fc0
9 changed files with 26 additions and 28 deletions
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24
libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/PeripheralPins.c
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@ -205,18 +205,18 @@ const struct pwm_pin_channel pwn_pins[] = {
{PA17, PWM_2, 1}, {PA17, PWM_2, 1},
{PA18, PWM_0, 2}, {PA18, PWM_0, 2},
{PA19, PWM_0, 3}, {PA19, PWM_0, 3},
{PA20, PWM_0, 6}, {PA20, PWM_0, 6},
{PA22, PWM_0, 4}, {PA22, PWM_0, 4},
{PA23, PWM_0, 5}, {PA23, PWM_0, 5},
{PA24, PWM_1, 2}, {PA24, PWM_1, 2},
{PA25, PWM_1, 3}, {PA25, PWM_1, 3},
{PA30, PWM_1, 0}, {PA30, PWM_1, 0},
{PA31, PWM_1, 1}, {PA31, PWM_1, 1},
{PB16, PWM_0, 4}, {PB16, PWM_0, 4},
{PB17, PWM_0, 5}, {PB17, PWM_0, 5},
{PB30, PWM_0, 0}, {PB30, PWM_0, 0},
{PB31, PWM_0, 1}, {PB31, PWM_0, 1},
/* Not connected */ /* Not connected */
{(PinName) NC ,(PWMName) NC ,(uint8_t) NC} {(PinName) NC ,(PWMName) NC ,(uint8_t) NC}
}; };

4
libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/dma_api.c
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@ -301,8 +301,8 @@ bool dma_is_transfer_complete(int channelid)
if (channel_index >= CONF_MAX_USED_CHANNEL_NUM) { if (channel_index >= CONF_MAX_USED_CHANNEL_NUM) {
/* This channel is not active! return zero for now */ /* This channel is not active! return zero for now */
// res = 0; // res = 0;
return 0; return 0;
} }
return (STATUS_OK == dma_get_job_status(&dma_channels[channel_index].resource)); return (STATUS_OK == dma_get_job_status(&dma_channels[channel_index].resource));

9
libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAMD21/clock.c
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@ -487,10 +487,9 @@ enum status_code system_clock_source_write_calibration(
{ {
switch (clock_source) { switch (clock_source) {
case SYSTEM_CLOCK_SOURCE_OSC8M: case SYSTEM_CLOCK_SOURCE_OSC8M:
if (calibration_value > 0xfff || freq_range > 4) if (calibration_value > 0xfff || freq_range > 4) {
{ return STATUS_ERR_INVALID_ARG;
return STATUS_ERR_INVALID_ARG; }
}
SYSCTRL->OSC8M.bit.CALIB = calibration_value; SYSCTRL->OSC8M.bit.CALIB = calibration_value;
SYSCTRL->OSC8M.bit.FRANGE = freq_range; SYSCTRL->OSC8M.bit.FRANGE = freq_range;
break; break;
@ -510,7 +509,7 @@ enum status_code system_clock_source_write_calibration(
default: default:
Assert(false); Assert(false);
return STATUS_ERR_INVALID_ARG; return STATUS_ERR_INVALID_ARG;
} }
return STATUS_OK; return STATUS_OK;
} }

2
libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAMR21/clock.c
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@ -518,7 +518,7 @@ enum status_code system_clock_source_write_calibration(
default: default:
Assert(false); Assert(false);
return STATUS_ERR_INVALID_ARG; return STATUS_ERR_INVALID_ARG;
} }
return STATUS_OK; return STATUS_OK;

2
libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/gpio_api.c
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@ -75,7 +75,7 @@ void gpio_dir(gpio_t *obj, PinDirection direction)
{ {
MBED_ASSERT(obj->pin != (PinName)NC); MBED_ASSERT(obj->pin != (PinName)NC);
struct port_config pin_conf; struct port_config pin_conf;
obj->direction = direction; obj->direction = direction;
pin_conf.input_pull = (enum port_pin_pull)obj->mode; pin_conf.input_pull = (enum port_pin_pull)obj->mode;
pin_conf.powersave = obj->powersave; pin_conf.powersave = obj->powersave;
switch (direction) { switch (direction) {

8
libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/i2c_api.c
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@ -924,20 +924,20 @@ uint32_t i2c_irq_handler_asynch(i2c_t *obj)
uint32_t event_mask = pI2C_S(obj)->events; uint32_t event_mask = pI2C_S(obj)->events;
/* TODO: Current implementation is interrupt based only */ /* TODO: Current implementation is interrupt based only */
switch (pI2C_S(obj)->master.status) { switch (pI2C_S(obj)->master.status) {
case STATUS_OK: case STATUS_OK:
/* Transfer is complete */ /* Transfer is complete */
return (I2C_EVENT_TRANSFER_COMPLETE & event_mask); return (I2C_EVENT_TRANSFER_COMPLETE & event_mask);
case STATUS_ERR_BAD_ADDRESS: case STATUS_ERR_BAD_ADDRESS:
/* Received a NACK */ /* Received a NACK */
return (I2C_EVENT_ERROR_NO_SLAVE & event_mask); return (I2C_EVENT_ERROR_NO_SLAVE & event_mask);
case STATUS_ERR_PACKET_COLLISION: case STATUS_ERR_PACKET_COLLISION:
/* An error occurred in between transfer */ /* An error occurred in between transfer */
return (I2C_EVENT_ERROR & event_mask); return (I2C_EVENT_ERROR & event_mask);
default: default:
return 0; return 0;
} }

2
libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/serial_api.c
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@ -104,7 +104,7 @@ static inline void reset_usart(serial_t *obj)
/* Reset module */ /* Reset module */
_USART(obj).CTRLA.reg = SERCOM_USART_CTRLA_SWRST; _USART(obj).CTRLA.reg = SERCOM_USART_CTRLA_SWRST;
SUPPRESS_WARNING(reset_usart); SUPPRESS_WARNING(reset_usart);
} }
uint32_t serial_find_mux_settings (serial_t *obj) uint32_t serial_find_mux_settings (serial_t *obj)

2
libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/spi_api.c
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@ -863,7 +863,7 @@ static enum status_code _spi_transceive_buffer(spi_t *obj)
void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint) void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint)
{ {
uint16_t dummy_read; uint16_t dummy_read;
(void) dummy_read; (void) dummy_read;
/* Sanity check arguments */ /* Sanity check arguments */
MBED_ASSERT(obj); MBED_ASSERT(obj);

1
libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/us_ticker.c
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@ -109,7 +109,6 @@ void us_ticker_init(void)
/* Initialize the timer */ /* Initialize the timer */
tc_init(&us_ticker_module, TICKER_COUNTER_uS, &config_tc); tc_init(&us_ticker_module, TICKER_COUNTER_uS, &config_tc);
MBED_ASSERT(ret_status == STATUS_OK);
/* Register callback function */ /* Register callback function */
tc_register_callback(&us_ticker_module, (tc_callback_t)us_ticker_irq_handler_internal, TC_CALLBACK_CC_CHANNEL0); tc_register_callback(&us_ticker_module, (tc_callback_t)us_ticker_irq_handler_internal, TC_CALLBACK_CC_CHANNEL0);