mirror of https://github.com/ARMmbed/mbed-os.git
Fix #4613: remove duplicated startup files for MICRONFCBOARD
Inherits from LPC11U34_421, that defines startup. They were identical.pull/4756/head
Martin Kojtal
parent
aae62bd990
commit
a7f9dc66b8
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@ -1,17 +0,0 @@
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LR_IROM1 0x00000000 0xC000 { ; load region size_region (48k)
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ER_IROM1 0x00000000 0xC000 { ; load address = execution address
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*.o (RESET, +First)
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*(InRoot$$Sections)
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.ANY (+RO)
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}
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; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
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; 8KB - 0xC0 = 0x1F40
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RW_IRAM1 0x100000C0 0x1F40 {
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.ANY (+RW +ZI)
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}
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RW_IRAM2 0x20004000 0x800 { ; RW data, USB RAM
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.ANY (USBRAM)
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}
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}
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@ -1,325 +0,0 @@
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;/*****************************************************************************
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; * @file: startup_LPC11xx.s
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; * @purpose: CMSIS Cortex-M0 Core Device Startup File
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; * for the NXP LPC11xx Device Series
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; * @version: V1.0
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; * @date: 25. Nov. 2008
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; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
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; *
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; * Copyright (C) 2008 ARM Limited. All rights reserved.
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; * ARM Limited (ARM) is supplying this software for use with Cortex-M0
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; * processor based microcontrollers. This file can be freely distributed
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; * within development tools that are supporting such ARM based processors.
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; *
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; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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; *
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; *****************************************************************************/
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Stack_Size EQU 0x00000400
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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EXPORT __initial_sp
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Stack_Mem SPACE Stack_Size
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__initial_sp EQU 0x10002000 ; Top of RAM from LPC11U
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Heap_Size EQU 0x00000000
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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EXPORT __heap_base
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EXPORT __heap_limit
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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__Vectors DCD __initial_sp ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD MemManage_Handler ; MPU Fault Handler
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DCD BusFault_Handler ; Bus Fault Handler
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DCD UsageFault_Handler ; Usage Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD DebugMon_Handler ; Debug Monitor Handler
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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; for LPC11Uxx (With USB)
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DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx
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DCD FLEX_INT1_IRQHandler
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DCD FLEX_INT2_IRQHandler
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DCD FLEX_INT3_IRQHandler
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DCD FLEX_INT4_IRQHandler
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DCD FLEX_INT5_IRQHandler
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DCD FLEX_INT6_IRQHandler
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DCD FLEX_INT7_IRQHandler
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DCD GINT0_IRQHandler
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DCD GINT1_IRQHandler ; PIO0 (0:7)
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DCD Reserved_IRQHandler ; Reserved
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DCD Reserved_IRQHandler
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DCD Reserved_IRQHandler
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DCD Reserved_IRQHandler
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DCD SSP1_IRQHandler ; SSP1
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DCD I2C_IRQHandler ; I2C
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DCD TIMER16_0_IRQHandler ; 16-bit Timer0
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DCD TIMER16_1_IRQHandler ; 16-bit Timer1
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DCD TIMER32_0_IRQHandler ; 32-bit Timer0
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DCD TIMER32_1_IRQHandler ; 32-bit Timer1
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DCD SSP0_IRQHandler ; SSP0
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DCD UART_IRQHandler ; UART
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DCD USB_IRQHandler ; USB IRQ
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DCD USB_FIQHandler ; USB FIQ
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DCD ADC_IRQHandler ; A/D Converter
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DCD WDT_IRQHandler ; Watchdog timer
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DCD BOD_IRQHandler ; Brown Out Detect
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DCD FMC_IRQHandler ; IP2111 Flash Memory Controller
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DCD Reserved_IRQHandler ; Reserved
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DCD Reserved_IRQHandler ; Reserved
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DCD USBWakeup_IRQHandler ; USB wake up
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DCD Reserved_IRQHandler ; Reserved
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;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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IF :LNOT::DEF:NO_CRP
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AREA |.ARM.__at_0x02FC|, CODE, READONLY
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CRP_Key DCD 0xFFFFFFFF
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ENDIF
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AREA |.text|, CODE, READONLY
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; Reset Handler
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT SystemInit
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IMPORT __main
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__main
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BX R0
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ENDP
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; Dummy Exception Handlers (infinite loops which can be modified)
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; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled
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; for particular peripheral.
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;NMI_Handler PROC
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; EXPORT NMI_Handler [WEAK]
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; B .
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; ENDP
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HardFault_Handler\
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PROC
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EXPORT HardFault_Handler [WEAK]
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B .
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ENDP
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MemManage_Handler\
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PROC
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EXPORT MemManage_Handler [WEAK]
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B .
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ENDP
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BusFault_Handler\
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PROC
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EXPORT BusFault_Handler [WEAK]
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B .
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ENDP
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UsageFault_Handler\
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PROC
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EXPORT UsageFault_Handler [WEAK]
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B .
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ENDP
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SVC_Handler PROC
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EXPORT SVC_Handler [WEAK]
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B .
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ENDP
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DebugMon_Handler\
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PROC
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EXPORT DebugMon_Handler [WEAK]
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B .
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ENDP
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PendSV_Handler PROC
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EXPORT PendSV_Handler [WEAK]
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B .
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ENDP
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SysTick_Handler PROC
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EXPORT SysTick_Handler [WEAK]
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B .
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ENDP
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Reserved_IRQHandler PROC
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EXPORT Reserved_IRQHandler [WEAK]
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B .
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ENDP
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Default_Handler PROC
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; for LPC11Uxx (With USB)
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EXPORT NMI_Handler [WEAK]
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EXPORT FLEX_INT0_IRQHandler [WEAK]
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EXPORT FLEX_INT1_IRQHandler [WEAK]
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EXPORT FLEX_INT2_IRQHandler [WEAK]
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EXPORT FLEX_INT3_IRQHandler [WEAK]
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EXPORT FLEX_INT4_IRQHandler [WEAK]
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EXPORT FLEX_INT5_IRQHandler [WEAK]
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EXPORT FLEX_INT6_IRQHandler [WEAK]
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EXPORT FLEX_INT7_IRQHandler [WEAK]
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EXPORT GINT0_IRQHandler [WEAK]
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EXPORT GINT1_IRQHandler [WEAK]
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EXPORT SSP1_IRQHandler [WEAK]
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EXPORT I2C_IRQHandler [WEAK]
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EXPORT TIMER16_0_IRQHandler [WEAK]
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EXPORT TIMER16_1_IRQHandler [WEAK]
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EXPORT TIMER32_0_IRQHandler [WEAK]
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EXPORT TIMER32_1_IRQHandler [WEAK]
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EXPORT SSP0_IRQHandler [WEAK]
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EXPORT UART_IRQHandler [WEAK]
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EXPORT USB_IRQHandler [WEAK]
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EXPORT USB_FIQHandler [WEAK]
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EXPORT ADC_IRQHandler [WEAK]
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EXPORT WDT_IRQHandler [WEAK]
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EXPORT BOD_IRQHandler [WEAK]
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EXPORT FMC_IRQHandler [WEAK]
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EXPORT USBWakeup_IRQHandler [WEAK]
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NMI_Handler
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FLEX_INT0_IRQHandler
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FLEX_INT1_IRQHandler
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FLEX_INT2_IRQHandler
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FLEX_INT3_IRQHandler
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FLEX_INT4_IRQHandler
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FLEX_INT5_IRQHandler
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FLEX_INT6_IRQHandler
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FLEX_INT7_IRQHandler
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GINT0_IRQHandler
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GINT1_IRQHandler
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SSP1_IRQHandler
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I2C_IRQHandler
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TIMER16_0_IRQHandler
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TIMER16_1_IRQHandler
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TIMER32_0_IRQHandler
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TIMER32_1_IRQHandler
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SSP0_IRQHandler
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UART_IRQHandler
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USB_IRQHandler
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USB_FIQHandler
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ADC_IRQHandler
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WDT_IRQHandler
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BOD_IRQHandler
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FMC_IRQHandler
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USBWakeup_IRQHandler
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B .
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ENDP
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ALIGN
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END
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@ -1,17 +0,0 @@
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LR_IROM1 0x00000000 0xC000 { ; load region size_region (48k)
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ER_IROM1 0x00000000 0xC000 { ; load address = execution address
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*.o (RESET, +First)
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*(InRoot$$Sections)
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.ANY (+RO)
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}
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; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
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; 8KB - 0xC0 = 0x1F40
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RW_IRAM1 0x100000C0 0x1F40 {
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.ANY (+RW +ZI)
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}
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RW_IRAM2 0x20004000 0x800 { ; RW data, USB RAM
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.ANY (USBRAM)
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}
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}
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@ -1,308 +0,0 @@
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;/*****************************************************************************
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; * @file: startup_LPC11xx.s
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; * @purpose: CMSIS Cortex-M0 Core Device Startup File
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; * for the NXP LPC11xx Device Series
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; * @version: V1.0
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; * @date: 25. Nov. 2008
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; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
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; *
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; * Copyright (C) 2008 ARM Limited. All rights reserved.
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; * ARM Limited (ARM) is supplying this software for use with Cortex-M0
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; * processor based microcontrollers. This file can be freely distributed
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; * within development tools that are supporting such ARM based processors.
|
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; *
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; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
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; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
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; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
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; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
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; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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; *
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; *****************************************************************************/
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__initial_sp EQU 0x10002000 ; Top of RAM from LPC11U
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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__Vectors DCD __initial_sp ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD MemManage_Handler ; MPU Fault Handler
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DCD BusFault_Handler ; Bus Fault Handler
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DCD UsageFault_Handler ; Usage Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD DebugMon_Handler ; Debug Monitor Handler
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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; for LPC11Uxx (With USB)
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DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx
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DCD FLEX_INT1_IRQHandler
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DCD FLEX_INT2_IRQHandler
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DCD FLEX_INT3_IRQHandler
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DCD FLEX_INT4_IRQHandler
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DCD FLEX_INT5_IRQHandler
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DCD FLEX_INT6_IRQHandler
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DCD FLEX_INT7_IRQHandler
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DCD GINT0_IRQHandler
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DCD GINT1_IRQHandler ; PIO0 (0:7)
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DCD Reserved_IRQHandler ; Reserved
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DCD Reserved_IRQHandler
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DCD Reserved_IRQHandler
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DCD Reserved_IRQHandler
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DCD SSP1_IRQHandler ; SSP1
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DCD I2C_IRQHandler ; I2C
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DCD TIMER16_0_IRQHandler ; 16-bit Timer0
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DCD TIMER16_1_IRQHandler ; 16-bit Timer1
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DCD TIMER32_0_IRQHandler ; 32-bit Timer0
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DCD TIMER32_1_IRQHandler ; 32-bit Timer1
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DCD SSP0_IRQHandler ; SSP0
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DCD UART_IRQHandler ; UART
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DCD USB_IRQHandler ; USB IRQ
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DCD USB_FIQHandler ; USB FIQ
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DCD ADC_IRQHandler ; A/D Converter
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DCD WDT_IRQHandler ; Watchdog timer
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DCD BOD_IRQHandler ; Brown Out Detect
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DCD FMC_IRQHandler ; IP2111 Flash Memory Controller
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DCD Reserved_IRQHandler ; Reserved
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DCD Reserved_IRQHandler ; Reserved
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DCD USBWakeup_IRQHandler ; USB wake up
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DCD Reserved_IRQHandler ; Reserved
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;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
|
||||
IF :LNOT::DEF:NO_CRP
|
||||
AREA |.ARM.__at_0x02FC|, CODE, READONLY
|
||||
CRP_Key DCD 0xFFFFFFFF
|
||||
ENDIF
|
||||
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled
|
||||
; for particular peripheral.
|
||||
;NMI_Handler PROC
|
||||
; EXPORT NMI_Handler [WEAK]
|
||||
; B .
|
||||
; ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
Reserved_IRQHandler PROC
|
||||
EXPORT Reserved_IRQHandler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
; for LPC11Uxx (With USB)
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
EXPORT FLEX_INT0_IRQHandler [WEAK]
|
||||
EXPORT FLEX_INT1_IRQHandler [WEAK]
|
||||
EXPORT FLEX_INT2_IRQHandler [WEAK]
|
||||
EXPORT FLEX_INT3_IRQHandler [WEAK]
|
||||
EXPORT FLEX_INT4_IRQHandler [WEAK]
|
||||
EXPORT FLEX_INT5_IRQHandler [WEAK]
|
||||
EXPORT FLEX_INT6_IRQHandler [WEAK]
|
||||
EXPORT FLEX_INT7_IRQHandler [WEAK]
|
||||
EXPORT GINT0_IRQHandler [WEAK]
|
||||
EXPORT GINT1_IRQHandler [WEAK]
|
||||
EXPORT SSP1_IRQHandler [WEAK]
|
||||
EXPORT I2C_IRQHandler [WEAK]
|
||||
EXPORT TIMER16_0_IRQHandler [WEAK]
|
||||
EXPORT TIMER16_1_IRQHandler [WEAK]
|
||||
EXPORT TIMER32_0_IRQHandler [WEAK]
|
||||
EXPORT TIMER32_1_IRQHandler [WEAK]
|
||||
EXPORT SSP0_IRQHandler [WEAK]
|
||||
EXPORT UART_IRQHandler [WEAK]
|
||||
|
||||
EXPORT USB_IRQHandler [WEAK]
|
||||
EXPORT USB_FIQHandler [WEAK]
|
||||
EXPORT ADC_IRQHandler [WEAK]
|
||||
EXPORT WDT_IRQHandler [WEAK]
|
||||
EXPORT BOD_IRQHandler [WEAK]
|
||||
EXPORT FMC_IRQHandler [WEAK]
|
||||
EXPORT USBWakeup_IRQHandler [WEAK]
|
||||
|
||||
NMI_Handler
|
||||
FLEX_INT0_IRQHandler
|
||||
FLEX_INT1_IRQHandler
|
||||
FLEX_INT2_IRQHandler
|
||||
FLEX_INT3_IRQHandler
|
||||
FLEX_INT4_IRQHandler
|
||||
FLEX_INT5_IRQHandler
|
||||
FLEX_INT6_IRQHandler
|
||||
FLEX_INT7_IRQHandler
|
||||
GINT0_IRQHandler
|
||||
GINT1_IRQHandler
|
||||
SSP1_IRQHandler
|
||||
I2C_IRQHandler
|
||||
TIMER16_0_IRQHandler
|
||||
TIMER16_1_IRQHandler
|
||||
TIMER32_0_IRQHandler
|
||||
TIMER32_1_IRQHandler
|
||||
SSP0_IRQHandler
|
||||
UART_IRQHandler
|
||||
USB_IRQHandler
|
||||
USB_FIQHandler
|
||||
ADC_IRQHandler
|
||||
WDT_IRQHandler
|
||||
BOD_IRQHandler
|
||||
FMC_IRQHandler
|
||||
USBWakeup_IRQHandler
|
||||
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
END
|
||||
|
|
@ -1,151 +0,0 @@
|
|||
/* Linker script to configure memory regions. */
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 48K
|
||||
RAM (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x1F40
|
||||
USB_RAM (rwx): ORIGIN = 0x20004000, LENGTH = 0x800
|
||||
}
|
||||
|
||||
/* Linker script to place sections and symbol values. Should be used together
|
||||
* with other linker script that defines memory regions FLASH and RAM.
|
||||
* It references following symbols, which must be defined in code:
|
||||
* Reset_Handler : Entry of reset handler
|
||||
*
|
||||
* It defines following symbols, which code can use without definition:
|
||||
* __exidx_start
|
||||
* __exidx_end
|
||||
* __etext
|
||||
* __data_start__
|
||||
* __preinit_array_start
|
||||
* __preinit_array_end
|
||||
* __init_array_start
|
||||
* __init_array_end
|
||||
* __fini_array_start
|
||||
* __fini_array_end
|
||||
* __data_end__
|
||||
* __bss_start__
|
||||
* __bss_end__
|
||||
* __end__
|
||||
* end
|
||||
* __HeapLimit
|
||||
* __StackLimit
|
||||
* __StackTop
|
||||
* __stack
|
||||
*/
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
KEEP(*(.isr_vector))
|
||||
*(.text.Reset_Handler)
|
||||
|
||||
/* Only vectors and code running at reset are safe to be in first 512
|
||||
bytes since RAM can be mapped into this area for RAM based interrupt
|
||||
vectors. */
|
||||
. = 0x00000200;
|
||||
*(.text*)
|
||||
|
||||
KEEP(*(.init))
|
||||
KEEP(*(.fini))
|
||||
|
||||
/* .ctors */
|
||||
*crtbegin.o(.ctors)
|
||||
*crtbegin?.o(.ctors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
|
||||
*(SORT(.ctors.*))
|
||||
*(.ctors)
|
||||
|
||||
/* .dtors */
|
||||
*crtbegin.o(.dtors)
|
||||
*crtbegin?.o(.dtors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
|
||||
*(SORT(.dtors.*))
|
||||
*(.dtors)
|
||||
|
||||
*(.rodata*)
|
||||
|
||||
KEEP(*(.eh_frame*))
|
||||
} > FLASH
|
||||
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > FLASH
|
||||
|
||||
__exidx_start = .;
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > FLASH
|
||||
__exidx_end = .;
|
||||
|
||||
__etext = .;
|
||||
|
||||
.data : AT (__etext)
|
||||
{
|
||||
__data_start__ = .;
|
||||
*(vtable)
|
||||
*(.data*)
|
||||
|
||||
. = ALIGN(4);
|
||||
/* preinit data */
|
||||
PROVIDE (__preinit_array_start = .);
|
||||
KEEP(*(.preinit_array))
|
||||
PROVIDE (__preinit_array_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
/* init data */
|
||||
PROVIDE (__init_array_start = .);
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
PROVIDE (__init_array_end = .);
|
||||
|
||||
|
||||
. = ALIGN(4);
|
||||
/* finit data */
|
||||
PROVIDE (__fini_array_start = .);
|
||||
KEEP(*(SORT(.fini_array.*)))
|
||||
KEEP(*(.fini_array))
|
||||
PROVIDE (__fini_array_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
/* All data end */
|
||||
__data_end__ = .;
|
||||
|
||||
} > RAM
|
||||
|
||||
.bss :
|
||||
{
|
||||
__bss_start__ = .;
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
__bss_end__ = .;
|
||||
} > RAM
|
||||
|
||||
.heap :
|
||||
{
|
||||
__end__ = .;
|
||||
end = __end__;
|
||||
*(.heap*)
|
||||
__HeapLimit = .;
|
||||
} > RAM
|
||||
|
||||
/* .stack_dummy section doesn't contains any symbols. It is only
|
||||
* used for linker to calculate size of stack sections, and assign
|
||||
* values to stack symbols later */
|
||||
.stack_dummy :
|
||||
{
|
||||
*(.stack)
|
||||
} > RAM
|
||||
|
||||
/* Set stack top to end of RAM, and stack limit move down by
|
||||
* size of stack_dummy section */
|
||||
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
|
||||
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
|
||||
PROVIDE(__stack = __StackTop);
|
||||
|
||||
/* Check if data + heap + stack exceeds RAM limit */
|
||||
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
|
||||
}
|
||||
Loading…
Reference in New Issue