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Merge pull request #494 from 0xc0170/Sissors-master 

Extended #476, which does not break ethernet for K64F
pull/497/head
Bogdan Marinescu 2014-09-18 13:46:50 +01:00
parent b031920624 b051dbd717
commit a73f28e6fb
297 changed files with 221973 additions and 101513 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10137
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/MK22F51212.h Normal file
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File diff suppressed because it is too large Load Diff

13
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_ARM_STD/MK22F51212.sct Normal file
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@ -0,0 +1,13 @@
LR_IROM1 0x00000000 0x80000 { ; load region size_region (512k)
ER_IROM1 0x00000000 0x80000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; 8_byte_aligned(62 vect * 4 bytes) = 8_byte_aligned(0x194) = 0x198
; 0x20000 - 0x198 = 0x1FE68
RW_IRAM1 0x1FFF0198 0x1FE68 {
.ANY (+RW +ZI)
}
}

679
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_ARM_STD/startup_MK22F12.s Normal file
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;/*****************************************************************************
; * @file: startup_MK22F12.s
; * @purpose: CMSIS Cortex-M4 Core Device Startup File for the
; * MK22F12
; * @version: 1.5
; * @date: 2013-5-16
; *
; * Copyright: 1997 - 2013 Freescale Semiconductor, Inc. All Rights Reserved.
;*
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
; *
; *****************************************************************************/
__initial_sp EQU 0x20010000 ; Top of RAM
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD DMA0_IRQHandler ; DMA Channel 0 Transfer Complete
DCD DMA1_IRQHandler ; DMA Channel 1 Transfer Complete
DCD DMA2_IRQHandler ; DMA Channel 2 Transfer Complete
DCD DMA3_IRQHandler ; DMA Channel 3 Transfer Complete
DCD DMA4_IRQHandler ; DMA Channel 4 Transfer Complete
DCD DMA5_IRQHandler ; DMA Channel 5 Transfer Complete
DCD DMA6_IRQHandler ; DMA Channel 6 Transfer Complete
DCD DMA7_IRQHandler ; DMA Channel 7 Transfer Complete
DCD DMA8_IRQHandler ; DMA Channel 8 Transfer Complete
DCD DMA9_IRQHandler ; DMA Channel 9 Transfer Complete
DCD DMA10_IRQHandler ; DMA Channel 10 Transfer Complete
DCD DMA11_IRQHandler ; DMA Channel 11 Transfer Complete
DCD DMA12_IRQHandler ; DMA Channel 12 Transfer Complete
DCD DMA13_IRQHandler ; DMA Channel 13 Transfer Complete
DCD DMA14_IRQHandler ; DMA Channel 14 Transfer Complete
DCD DMA15_IRQHandler ; DMA Channel 15 Transfer Complete
DCD DMA_Error_IRQHandler ; DMA Error Interrupt
DCD MCM_IRQHandler ; Normal Interrupt
DCD FTFE_IRQHandler ; FTFE Command complete interrupt
DCD Read_Collision_IRQHandler ; Read Collision Interrupt
DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
DCD LLW_IRQHandler ; Low Leakage Wakeup
DCD Watchdog_IRQHandler ; WDOG Interrupt
DCD Reserved39_IRQHandler ; Reserved Interrupt 39
DCD I2C0_IRQHandler ; I2C0 interrupt
DCD I2C1_IRQHandler ; I2C1 interrupt
DCD SPI0_IRQHandler ; SPI0 Interrupt
DCD SPI1_IRQHandler ; SPI1 Interrupt
DCD I2S0_Tx_IRQHandler ; I2S0 transmit interrupt
DCD I2S0_Rx_IRQHandler ; I2S0 receive interrupt
DCD UART0_LON_IRQHandler ; UART0 LON interrupt
DCD UART0_RX_TX_IRQHandler ; UART0 Receive/Transmit interrupt
DCD UART0_ERR_IRQHandler ; UART0 Error interrupt
DCD UART1_RX_TX_IRQHandler ; UART1 Receive/Transmit interrupt
DCD UART1_ERR_IRQHandler ; UART1 Error interrupt
DCD UART2_RX_TX_IRQHandler ; UART2 Receive/Transmit interrupt
DCD UART2_ERR_IRQHandler ; UART2 Error interrupt
DCD UART3_RX_TX_IRQHandler ; UART3 Receive/Transmit interrupt
DCD UART3_ERR_IRQHandler ; UART3 Error interrupt
DCD ADC0_IRQHandler ; ADC0 interrupt
DCD CMP0_IRQHandler ; CMP0 interrupt
DCD CMP1_IRQHandler ; CMP1 interrupt
DCD FTM0_IRQHandler ; FTM0 fault, overflow and channels interrupt
DCD FTM1_IRQHandler ; FTM1 fault, overflow and channels interrupt
DCD FTM2_IRQHandler ; FTM2 fault, overflow and channels interrupt
DCD CMT_IRQHandler ; CMT interrupt
DCD RTC_IRQHandler ; RTC interrupt
DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
DCD PIT0_IRQHandler ; PIT timer channel 0 interrupt
DCD PIT1_IRQHandler ; PIT timer channel 1 interrupt
DCD PIT2_IRQHandler ; PIT timer channel 2 interrupt
DCD PIT3_IRQHandler ; PIT timer channel 3 interrupt
DCD PDB0_IRQHandler ; PDB0 Interrupt
DCD USB0_IRQHandler ; USB0 interrupt
DCD USBDCD_IRQHandler ; USBDCD Interrupt
DCD Reserved71_IRQHandler ; Reserved interrupt 71
DCD DAC0_IRQHandler ; DAC0 interrupt
DCD MCG_IRQHandler ; MCG Interrupt
DCD LPTimer_IRQHandler ; LPTimer interrupt
DCD PORTA_IRQHandler ; Port A interrupt
DCD PORTB_IRQHandler ; Port B interrupt
DCD PORTC_IRQHandler ; Port C interrupt
DCD PORTD_IRQHandler ; Port D interrupt
DCD PORTE_IRQHandler ; Port E interrupt
DCD SWI_IRQHandler ; Software interrupt
DCD SPI2_IRQHandler ; SPI2 Interrupt
DCD UART4_RX_TX_IRQHandler ; UART4 Receive/Transmit interrupt
DCD UART4_ERR_IRQHandler ; UART4 Error interrupt
DCD UART5_RX_TX_IRQHandler ; UART5 Receive/Transmit interrupt
DCD UART5_ERR_IRQHandler ; UART5 Error interrupt
DCD CMP2_IRQHandler ; CMP2 interrupt
DCD FTM3_IRQHandler ; FTM3 fault, overflow and channels interrupt
DCD DAC1_IRQHandler ; DAC1 interrupt
DCD ADC1_IRQHandler ; ADC1 interrupt
DCD I2C2_IRQHandler ; I2C2 interrupt
DCD CAN0_ORed_Message_buffer_IRQHandler ; CAN0 OR'd message buffers interrupt
DCD CAN0_Bus_Off_IRQHandler ; CAN0 bus off interrupt
DCD CAN0_Error_IRQHandler ; CAN0 error interrupt
DCD CAN0_Tx_Warning_IRQHandler ; CAN0 Tx warning interrupt
DCD CAN0_Rx_Warning_IRQHandler ; CAN0 Rx warning interrupt
DCD CAN0_Wake_Up_IRQHandler ; CAN0 wake up interrupt
DCD SDHC_IRQHandler ; SDHC interrupt
DCD DefaultISR ; 98
DCD DefaultISR ; 99
DCD DefaultISR ; 100
DCD DefaultISR ; 101
DCD DefaultISR ; 102
DCD DefaultISR ; 103
DCD DefaultISR ; 104
DCD DefaultISR ; 105
DCD DefaultISR ; 106
DCD DefaultISR ; 107
DCD DefaultISR ; 108
DCD DefaultISR ; 109
DCD DefaultISR ; 110
DCD DefaultISR ; 111
DCD DefaultISR ; 112
DCD DefaultISR ; 113
DCD DefaultISR ; 114
DCD DefaultISR ; 115
DCD DefaultISR ; 116
DCD DefaultISR ; 117
DCD DefaultISR ; 118
DCD DefaultISR ; 119
DCD DefaultISR ; 120
DCD DefaultISR ; 121
DCD DefaultISR ; 122
DCD DefaultISR ; 123
DCD DefaultISR ; 124
DCD DefaultISR ; 125
DCD DefaultISR ; 126
DCD DefaultISR ; 127
DCD DefaultISR ; 128
DCD DefaultISR ; 129
DCD DefaultISR ; 130
DCD DefaultISR ; 131
DCD DefaultISR ; 132
DCD DefaultISR ; 133
DCD DefaultISR ; 134
DCD DefaultISR ; 135
DCD DefaultISR ; 136
DCD DefaultISR ; 137
DCD DefaultISR ; 138
DCD DefaultISR ; 139
DCD DefaultISR ; 140
DCD DefaultISR ; 141
DCD DefaultISR ; 142
DCD DefaultISR ; 143
DCD DefaultISR ; 144
DCD DefaultISR ; 145
DCD DefaultISR ; 146
DCD DefaultISR ; 147
DCD DefaultISR ; 148
DCD DefaultISR ; 149
DCD DefaultISR ; 150
DCD DefaultISR ; 151
DCD DefaultISR ; 152
DCD DefaultISR ; 153
DCD DefaultISR ; 154
DCD DefaultISR ; 155
DCD DefaultISR ; 156
DCD DefaultISR ; 157
DCD DefaultISR ; 158
DCD DefaultISR ; 159
DCD DefaultISR ; 160
DCD DefaultISR ; 161
DCD DefaultISR ; 162
DCD DefaultISR ; 163
DCD DefaultISR ; 164
DCD DefaultISR ; 165
DCD DefaultISR ; 166
DCD DefaultISR ; 167
DCD DefaultISR ; 168
DCD DefaultISR ; 169
DCD DefaultISR ; 170
DCD DefaultISR ; 171
DCD DefaultISR ; 172
DCD DefaultISR ; 173
DCD DefaultISR ; 174
DCD DefaultISR ; 175
DCD DefaultISR ; 176
DCD DefaultISR ; 177
DCD DefaultISR ; 178
DCD DefaultISR ; 179
DCD DefaultISR ; 180
DCD DefaultISR ; 181
DCD DefaultISR ; 182
DCD DefaultISR ; 183
DCD DefaultISR ; 184
DCD DefaultISR ; 185
DCD DefaultISR ; 186
DCD DefaultISR ; 187
DCD DefaultISR ; 188
DCD DefaultISR ; 189
DCD DefaultISR ; 190
DCD DefaultISR ; 191
DCD DefaultISR ; 192
DCD DefaultISR ; 193
DCD DefaultISR ; 194
DCD DefaultISR ; 195
DCD DefaultISR ; 196
DCD DefaultISR ; 197
DCD DefaultISR ; 198
DCD DefaultISR ; 199
DCD DefaultISR ; 200
DCD DefaultISR ; 201
DCD DefaultISR ; 202
DCD DefaultISR ; 203
DCD DefaultISR ; 204
DCD DefaultISR ; 205
DCD DefaultISR ; 206
DCD DefaultISR ; 207
DCD DefaultISR ; 208
DCD DefaultISR ; 209
DCD DefaultISR ; 210
DCD DefaultISR ; 211
DCD DefaultISR ; 212
DCD DefaultISR ; 213
DCD DefaultISR ; 214
DCD DefaultISR ; 215
DCD DefaultISR ; 216
DCD DefaultISR ; 217
DCD DefaultISR ; 218
DCD DefaultISR ; 219
DCD DefaultISR ; 220
DCD DefaultISR ; 221
DCD DefaultISR ; 222
DCD DefaultISR ; 223
DCD DefaultISR ; 224
DCD DefaultISR ; 225
DCD DefaultISR ; 226
DCD DefaultISR ; 227
DCD DefaultISR ; 228
DCD DefaultISR ; 229
DCD DefaultISR ; 230
DCD DefaultISR ; 231
DCD DefaultISR ; 232
DCD DefaultISR ; 233
DCD DefaultISR ; 234
DCD DefaultISR ; 235
DCD DefaultISR ; 236
DCD DefaultISR ; 237
DCD DefaultISR ; 238
DCD DefaultISR ; 239
DCD DefaultISR ; 240
DCD DefaultISR ; 241
DCD DefaultISR ; 242
DCD DefaultISR ; 243
DCD DefaultISR ; 244
DCD DefaultISR ; 245
DCD DefaultISR ; 246
DCD DefaultISR ; 247
DCD DefaultISR ; 248
DCD DefaultISR ; 249
DCD DefaultISR ; 250
DCD DefaultISR ; 251
DCD DefaultISR ; 252
DCD DefaultISR ; 253
DCD DefaultISR ; 254
DCD DefaultISR ; 255
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
; <h> Flash Configuration
; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
; <i> and security information that allows the MCU to restrict acces to the FTFL module.
; <h> Backdoor Comparison Key
; <o0> Backdoor Key 0 <0x0-0xFF:2>
; <o1> Backdoor Key 1 <0x0-0xFF:2>
; <o2> Backdoor Key 2 <0x0-0xFF:2>
; <o3> Backdoor Key 3 <0x0-0xFF:2>
; <o4> Backdoor Key 4 <0x0-0xFF:2>
; <o5> Backdoor Key 5 <0x0-0xFF:2>
; <o6> Backdoor Key 6 <0x0-0xFF:2>
; <o7> Backdoor Key 7 <0x0-0xFF:2>
BackDoorK0 EQU 0xFF
BackDoorK1 EQU 0xFF
BackDoorK2 EQU 0xFF
BackDoorK3 EQU 0xFF
BackDoorK4 EQU 0xFF
BackDoorK5 EQU 0xFF
BackDoorK6 EQU 0xFF
BackDoorK7 EQU 0xFF
; </h>
; <h> Program flash protection bytes (FPROT)
; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
; <i> Each bit protects a 1/32 region of the program flash memory.
; <h> FPROT0
; <i> Program flash protection bytes
; <i> 1/32 - 8/32 region
; <o.0> FPROT0.0
; <o.1> FPROT0.1
; <o.2> FPROT0.2
; <o.3> FPROT0.3
; <o.4> FPROT0.4
; <o.5> FPROT0.5
; <o.6> FPROT0.6
; <o.7> FPROT0.7
nFPROT0 EQU 0x00
FPROT0 EQU nFPROT0:EOR:0xFF
; </h>
; <h> FPROT1
; <i> Program Flash Region Protect Register 1
; <i> 9/32 - 16/32 region
; <o.0> FPROT1.0
; <o.1> FPROT1.1
; <o.2> FPROT1.2
; <o.3> FPROT1.3
; <o.4> FPROT1.4
; <o.5> FPROT1.5
; <o.6> FPROT1.6
; <o.7> FPROT1.7
nFPROT1 EQU 0x00
FPROT1 EQU nFPROT1:EOR:0xFF
; </h>
; <h> FPROT2
; <i> Program Flash Region Protect Register 2
; <i> 17/32 - 24/32 region
; <o.0> FPROT2.0
; <o.1> FPROT2.1
; <o.2> FPROT2.2
; <o.3> FPROT2.3
; <o.4> FPROT2.4
; <o.5> FPROT2.5
; <o.6> FPROT2.6
; <o.7> FPROT2.7
nFPROT2 EQU 0x00
FPROT2 EQU nFPROT2:EOR:0xFF
; </h>
; <h> FPROT3
; <i> Program Flash Region Protect Register 3
; <i> 25/32 - 32/32 region
; <o.0> FPROT3.0
; <o.1> FPROT3.1
; <o.2> FPROT3.2
; <o.3> FPROT3.3
; <o.4> FPROT3.4
; <o.5> FPROT3.5
; <o.6> FPROT3.6
; <o.7> FPROT3.7
nFPROT3 EQU 0x00
FPROT3 EQU nFPROT3:EOR:0xFF
; </h>
; </h>
; <h> Data flash protection byte (FDPROT)
; <i> Each bit protects a 1/8 region of the data flash memory.
; <i> (Program flash only devices: Reserved)
; <o.0> FDPROT.0
; <o.1> FDPROT.1
; <o.2> FDPROT.2
; <o.3> FDPROT.3
; <o.4> FDPROT.4
; <o.5> FDPROT.5
; <o.6> FDPROT.6
; <o.7> FDPROT.7
nFDPROT EQU 0x00
FDPROT EQU nFDPROT:EOR:0xFF
; </h>
; <h> EEPROM protection byte (FEPROT)
; <i> FlexNVM devices: Each bit protects a 1/8 region of the EEPROM.
; <i> (Program flash only devices: Reserved)
; <o.0> FEPROT.0
; <o.1> FEPROT.1
; <o.2> FEPROT.2
; <o.3> FEPROT.3
; <o.4> FEPROT.4
; <o.5> FEPROT.5
; <o.6> FEPROT.6
; <o.7> FEPROT.7
nFEPROT EQU 0x00
FEPROT EQU nFEPROT:EOR:0xFF
; </h>
; <h> Flash nonvolatile option byte (FOPT)
; <i> Allows the user to customize the operation of the MCU at boot time.
; <o.0> LPBOOT
; <0=> Low-power boot
; <1=> normal boot
; <o.1> EZPORT_DIS
; <0=> EzPort operation is enabled
; <1=> EzPort operation is disabled
FOPT EQU 0xFF
; </h>
; <h> Flash security byte (FSEC)
; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
; <o.0..1> SEC
; <2=> MCU security status is unsecure
; <3=> MCU security status is secure
; <i> Flash Security
; <i> This bits define the security state of the MCU.
; <o.2..3> FSLACC
; <2=> Freescale factory access denied
; <3=> Freescale factory access granted
; <i> Freescale Failure Analysis Access Code
; <i> This bits define the security state of the MCU.
; <o.4..5> MEEN
; <2=> Mass erase is disabled
; <3=> Mass erase is enabled
; <i> Mass Erase Enable Bits
; <i> Enables and disables mass erase capability of the FTFL module
; <o.6..7> KEYEN
; <2=> Backdoor key access enabled
; <3=> Backdoor key access disabled
; <i> Backdoor key Security Enable
; <i> These bits enable and disable backdoor key access to the FTFL module.
FSEC EQU 0xFE
; </h>
; </h>
IF :LNOT::DEF:RAM_TARGET
AREA |.ARM.__at_0x400|, CODE, READONLY
DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
DCB FPROT0, FPROT1, FPROT2, FPROT3
DCB FSEC, FOPT, FEPROT, FDPROT
ENDIF
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT DMA0_IRQHandler [WEAK]
EXPORT DMA1_IRQHandler [WEAK]
EXPORT DMA2_IRQHandler [WEAK]
EXPORT DMA3_IRQHandler [WEAK]
EXPORT DMA4_IRQHandler [WEAK]
EXPORT DMA5_IRQHandler [WEAK]
EXPORT DMA6_IRQHandler [WEAK]
EXPORT DMA7_IRQHandler [WEAK]
EXPORT DMA8_IRQHandler [WEAK]
EXPORT DMA9_IRQHandler [WEAK]
EXPORT DMA10_IRQHandler [WEAK]
EXPORT DMA11_IRQHandler [WEAK]
EXPORT DMA12_IRQHandler [WEAK]
EXPORT DMA13_IRQHandler [WEAK]
EXPORT DMA14_IRQHandler [WEAK]
EXPORT DMA15_IRQHandler [WEAK]
EXPORT DMA_Error_IRQHandler [WEAK]
EXPORT MCM_IRQHandler [WEAK]
EXPORT FTFE_IRQHandler [WEAK]
EXPORT Read_Collision_IRQHandler [WEAK]
EXPORT LVD_LVW_IRQHandler [WEAK]
EXPORT LLW_IRQHandler [WEAK]
EXPORT Watchdog_IRQHandler [WEAK]
EXPORT Reserved39_IRQHandler [WEAK]
EXPORT I2C0_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT SPI0_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT I2S0_Tx_IRQHandler [WEAK]
EXPORT I2S0_Rx_IRQHandler [WEAK]
EXPORT UART0_LON_IRQHandler [WEAK]
EXPORT UART0_RX_TX_IRQHandler [WEAK]
EXPORT UART0_ERR_IRQHandler [WEAK]
EXPORT UART1_RX_TX_IRQHandler [WEAK]
EXPORT UART1_ERR_IRQHandler [WEAK]
EXPORT UART2_RX_TX_IRQHandler [WEAK]
EXPORT UART2_ERR_IRQHandler [WEAK]
EXPORT UART3_RX_TX_IRQHandler [WEAK]
EXPORT UART3_ERR_IRQHandler [WEAK]
EXPORT ADC0_IRQHandler [WEAK]
EXPORT CMP0_IRQHandler [WEAK]
EXPORT CMP1_IRQHandler [WEAK]
EXPORT FTM0_IRQHandler [WEAK]
EXPORT FTM1_IRQHandler [WEAK]
EXPORT FTM2_IRQHandler [WEAK]
EXPORT CMT_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT RTC_Seconds_IRQHandler [WEAK]
EXPORT PIT0_IRQHandler [WEAK]
EXPORT PIT1_IRQHandler [WEAK]
EXPORT PIT2_IRQHandler [WEAK]
EXPORT PIT3_IRQHandler [WEAK]
EXPORT PDB0_IRQHandler [WEAK]
EXPORT USB0_IRQHandler [WEAK]
EXPORT USBDCD_IRQHandler [WEAK]
EXPORT Reserved71_IRQHandler [WEAK]
EXPORT DAC0_IRQHandler [WEAK]
EXPORT MCG_IRQHandler [WEAK]
EXPORT LPTimer_IRQHandler [WEAK]
EXPORT PORTA_IRQHandler [WEAK]
EXPORT PORTB_IRQHandler [WEAK]
EXPORT PORTC_IRQHandler [WEAK]
EXPORT PORTD_IRQHandler [WEAK]
EXPORT PORTE_IRQHandler [WEAK]
EXPORT SWI_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT UART4_RX_TX_IRQHandler [WEAK]
EXPORT UART4_ERR_IRQHandler [WEAK]
EXPORT UART5_RX_TX_IRQHandler [WEAK]
EXPORT UART5_ERR_IRQHandler [WEAK]
EXPORT CMP2_IRQHandler [WEAK]
EXPORT FTM3_IRQHandler [WEAK]
EXPORT DAC1_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT I2C2_IRQHandler [WEAK]
EXPORT CAN0_ORed_Message_buffer_IRQHandler [WEAK]
EXPORT CAN0_Bus_Off_IRQHandler [WEAK]
EXPORT CAN0_Error_IRQHandler [WEAK]
EXPORT CAN0_Tx_Warning_IRQHandler [WEAK]
EXPORT CAN0_Rx_Warning_IRQHandler [WEAK]
EXPORT CAN0_Wake_Up_IRQHandler [WEAK]
EXPORT SDHC_IRQHandler [WEAK]
EXPORT DefaultISR [WEAK]
DMA0_IRQHandler
DMA1_IRQHandler
DMA2_IRQHandler
DMA3_IRQHandler
DMA4_IRQHandler
DMA5_IRQHandler
DMA6_IRQHandler
DMA7_IRQHandler
DMA8_IRQHandler
DMA9_IRQHandler
DMA10_IRQHandler
DMA11_IRQHandler
DMA12_IRQHandler
DMA13_IRQHandler
DMA14_IRQHandler
DMA15_IRQHandler
DMA_Error_IRQHandler
MCM_IRQHandler
FTFE_IRQHandler
Read_Collision_IRQHandler
LVD_LVW_IRQHandler
LLW_IRQHandler
Watchdog_IRQHandler
Reserved39_IRQHandler
I2C0_IRQHandler
I2C1_IRQHandler
SPI0_IRQHandler
SPI1_IRQHandler
I2S0_Tx_IRQHandler
I2S0_Rx_IRQHandler
UART0_LON_IRQHandler
UART0_RX_TX_IRQHandler
UART0_ERR_IRQHandler
UART1_RX_TX_IRQHandler
UART1_ERR_IRQHandler
UART2_RX_TX_IRQHandler
UART2_ERR_IRQHandler
UART3_RX_TX_IRQHandler
UART3_ERR_IRQHandler
ADC0_IRQHandler
CMP0_IRQHandler
CMP1_IRQHandler
FTM0_IRQHandler
FTM1_IRQHandler
FTM2_IRQHandler
CMT_IRQHandler
RTC_IRQHandler
RTC_Seconds_IRQHandler
PIT0_IRQHandler
PIT1_IRQHandler
PIT2_IRQHandler
PIT3_IRQHandler
PDB0_IRQHandler
USB0_IRQHandler
USBDCD_IRQHandler
Reserved71_IRQHandler
DAC0_IRQHandler
MCG_IRQHandler
LPTimer_IRQHandler
PORTA_IRQHandler
PORTB_IRQHandler
PORTC_IRQHandler
PORTD_IRQHandler
PORTE_IRQHandler
SWI_IRQHandler
SPI2_IRQHandler
UART4_RX_TX_IRQHandler
UART4_ERR_IRQHandler
UART5_RX_TX_IRQHandler
UART5_ERR_IRQHandler
CMP2_IRQHandler
FTM3_IRQHandler
DAC1_IRQHandler
ADC1_IRQHandler
I2C2_IRQHandler
CAN0_ORed_Message_buffer_IRQHandler
CAN0_Bus_Off_IRQHandler
CAN0_Error_IRQHandler
CAN0_Tx_Warning_IRQHandler
CAN0_Rx_Warning_IRQHandler
CAN0_Wake_Up_IRQHandler
SDHC_IRQHandler
DefaultISR
B .
ENDP
ALIGN
END

31
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_ARM_STD/sys.cpp Normal file
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@ -0,0 +1,31 @@
/* mbed Microcontroller Library - stackheap
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
*
* Setup a fixed single stack/heap memory model,
* between the top of the RW/ZI region and the stackpointer
*/
#ifdef __cplusplus
extern "C" {
#endif
#include <rt_misc.h>
#include <stdint.h>
extern char Image$$RW_IRAM1$$ZI$$Limit[];
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
uint32_t sp_limit = __current_sp();
zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
struct __initial_stackheap r;
r.heap_base = zi_limit;
r.heap_limit = sp_limit;
return r;
}
#ifdef __cplusplus
}
#endif

13
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis.h Normal file
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@ -0,0 +1,13 @@
/* mbed Microcontroller Library - CMSIS
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
*
* A generic CMSIS include header, pulling in LPC11U24 specifics
*/
#ifndef MBED_CMSIS_H
#define MBED_CMSIS_H
#include "MK22F51212.h"
#include "cmsis_nvic.h"
#endif

30
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/* mbed Microcontroller Library - cmsis_nvic for LPC11U24
* Copyright (c) 2011 ARM Limited. All rights reserved.
*
* CMSIS-style functionality to support dynamic vectors
*/
#include "cmsis_nvic.h"
#define NVIC_RAM_VECTOR_ADDRESS (0x1FFFE000) // Vectors positioned at start of RAM
#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
uint32_t *vectors = (uint32_t*)SCB->VTOR;
uint32_t i;
// Copy and switch to dynamic vectors if the first time called
if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
uint32_t *old_vectors = vectors;
vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
for (i=0; i<NVIC_NUM_VECTORS; i++) {
vectors[i] = old_vectors[i];
}
SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
}
vectors[IRQn + 16] = vector;
}
uint32_t NVIC_GetVector(IRQn_Type IRQn) {
uint32_t *vectors = (uint32_t*)SCB->VTOR;
return vectors[IRQn + 16];
}

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/* mbed Microcontroller Library - cmsis_nvic
* Copyright (c) 2009-2011 ARM Limited. All rights reserved.
*
* CMSIS-style functionality to support dynamic vectors
*/
#ifndef MBED_CMSIS_NVIC_H
#define MBED_CMSIS_NVIC_H
#define NVIC_NUM_VECTORS (16 + 46) // CORE + MCU Peripherals
#define NVIC_USER_IRQ_OFFSET 16
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
uint32_t NVIC_GetVector(IRQn_Type IRQn);
#ifdef __cplusplus
}
#endif
#endif

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/*
** ###################################################################
** Compilers: Keil ARM C/C++ Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** GNU C Compiler - CodeSourcery Sourcery G++
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
** Version: rev. 2.5, 2014-05-06
** Build: b140611
**
** Abstract:
** Provides a system configuration function and a global variable that
** contains the system frequency. It configures the device and initializes
** the oscillator (PLL) that is part of the microcontroller device.
**
** Copyright (c) 2014 Freescale Semiconductor, Inc.
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** Revisions:
** - rev. 1.0 (2013-07-23)
** Initial version.
** - rev. 1.1 (2013-09-17)
** RM rev. 0.4 update.
** - rev. 2.0 (2013-10-29)
** Register accessor macros added to the memory map.
** Symbols for Processor Expert memory map compatibility added to the memory map.
** Startup file for gcc has been updated according to CMSIS 3.2.
** System initialization updated.
** - rev. 2.1 (2013-10-30)
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
** - rev. 2.2 (2013-12-20)
** Update according to reference manual rev. 0.6,
** - rev. 2.3 (2014-01-13)
** Update according to reference manual rev. 0.61,
** - rev. 2.4 (2014-02-10)
** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
** - rev. 2.5 (2014-05-06)
** Update according to reference manual rev. 1.0,
** Update of system and startup files.
** Module access macro module_BASES replaced by module_BASE_PTRS.
**
** ###################################################################
*/
/*!
* @file MK22F51212
* @version 2.5
* @date 2014-05-06
* @brief Device specific configuration file for MK22F51212 (implementation file)
*
* Provides a system configuration function and a global variable that contains
* the system frequency. It configures the device and initializes the oscillator
* (PLL) that is part of the microcontroller device.
*/
#include <stdint.h>
#include "cmsis.h"
/* ----------------------------------------------------------------------------
-- Core clock
---------------------------------------------------------------------------- */
uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
/* ----------------------------------------------------------------------------
-- SystemInit()
---------------------------------------------------------------------------- */
void SystemInit (void) {
#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
#if (DISABLE_WDOG)
/* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
/* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
/* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
WDOG_STCTRLH_WAITEN_MASK |
WDOG_STCTRLH_STOPEN_MASK |
WDOG_STCTRLH_ALLOWUPDATE_MASK |
WDOG_STCTRLH_CLKSRC_MASK |
0x0100U;
#endif /* (DISABLE_WDOG) */
if((RCM->SRS0 & RCM_SRS0_WAKEUP_MASK) != 0x00U)
{
if((PMC->REGSC & PMC_REGSC_ACKISO_MASK) != 0x00U)
{
PMC->REGSC |= PMC_REGSC_ACKISO_MASK; /* Release hold with ACKISO: Only has an effect if recovering from VLLSx.*/
}
} else {
#ifdef SYSTEM_RTC_CR_VALUE
SIM_SCGC6 |= SIM_SCGC6_RTC_MASK;
if ((RTC_CR & RTC_CR_OSCE_MASK) == 0x00U) { /* Only if the OSCILLATOR is not already enabled */
RTC_CR = (uint32_t)((RTC_CR & (uint32_t)~(uint32_t)(RTC_CR_SC2P_MASK | RTC_CR_SC4P_MASK | RTC_CR_SC8P_MASK | RTC_CR_SC16P_MASK)) | (uint32_t)SYSTEM_RTC_CR_VALUE);
RTC_CR |= (uint32_t)RTC_CR_OSCE_MASK;
RTC_CR &= (uint32_t)~(uint32_t)RTC_CR_CLKO_MASK;
}
#endif
}
/* Power mode protection initialization */
#ifdef SYSTEM_SMC_PMPROT_VALUE
SMC->PMPROT = SYSTEM_SMC_PMPROT_VALUE;
#endif
/* High speed run mode enable */
#if (((SYSTEM_SMC_PMCTRL_VALUE) & SMC_PMCTRL_RUNM_MASK) == (0x03U << SMC_PMCTRL_RUNM_SHIFT))
SMC->PMCTRL = (uint8_t)((SYSTEM_SMC_PMCTRL_VALUE) & (SMC_PMCTRL_RUNM_MASK)); /* Enable HSRUN mode */
while(SMC->PMSTAT != 0x80U) { /* Wait until the system is in HSRUN mode */
}
#endif
/* System clock initialization */
/* Internal reference clock trim initialization */
#if defined(SLOW_TRIM_ADDRESS)
if ( *((uint8_t*)SLOW_TRIM_ADDRESS) != 0xFFU) { /* Skip if non-volatile flash memory is erased */
MCG->C3 = *((uint8_t*)SLOW_TRIM_ADDRESS);
#endif /* defined(SLOW_TRIM_ADDRESS) */
#if defined(SLOW_FINE_TRIM_ADDRESS)
MCG->C4 = (MCG->C4 & ~(MCG_C4_SCFTRIM_MASK)) | ((*((uint8_t*) SLOW_FINE_TRIM_ADDRESS)) & MCG_C4_SCFTRIM_MASK);
#endif
#if defined(FAST_TRIM_ADDRESS)
MCG->C4 = (MCG->C4 & ~(MCG_C4_FCTRIM_MASK)) |((*((uint8_t*) FAST_TRIM_ADDRESS)) & MCG_C4_FCTRIM_MASK);
#endif
#if defined(FAST_FINE_TRIM_ADDRESS)
MCG->C2 = (MCG->C2 & ~(MCG_C2_FCFTRIM_MASK)) | ((*((uint8_t*)FAST_TRIM_ADDRESS)) & MCG_C2_FCFTRIM_MASK);
#endif /* defined(FAST_FINE_TRIM_ADDRESS) */
#if defined(SLOW_TRIM_ADDRESS)
}
#endif /* defined(SLOW_TRIM_ADDRESS) */
/* Set system prescalers and clock sources */
SIM->CLKDIV1 = SYSTEM_SIM_CLKDIV1_VALUE; /* Set system prescalers */
SIM->SOPT1 = ((SIM->SOPT1) & (uint32_t)(~(SIM_SOPT1_OSC32KSEL_MASK))) | ((SYSTEM_SIM_SOPT1_VALUE) & (SIM_SOPT1_OSC32KSEL_MASK)); /* Set 32 kHz clock source (ERCLK32K) */
SIM->SOPT2 = ((SIM->SOPT2) & (uint32_t)(~(SIM_SOPT2_PLLFLLSEL_MASK))) | ((SYSTEM_SIM_SOPT2_VALUE) & (SIM_SOPT2_PLLFLLSEL_MASK)); /* Selects the high frequency clock for various peripheral clocking options. */
#if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI))
/* Set MCG and OSC */
#if ((((SYSTEM_OSC_CR_VALUE) & OSC_CR_ERCLKEN_MASK) != 0x00U) || ((((SYSTEM_MCG_C5_VALUE) & MCG_C5_PLLCLKEN0_MASK) != 0x00U) && (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)))
/* SIM_SCGC5: PORTA=1 */
SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
/* PORTA_PCR18: ISF=0,MUX=0 */
PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
if (((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) {
/* PORTA_PCR19: ISF=0,MUX=0 */
PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
}
#endif
MCG->SC = SYSTEM_MCG_SC_VALUE; /* Set SC (fast clock internal reference divider) */
MCG->C1 = SYSTEM_MCG_C1_VALUE; /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) */
/* Check that the source of the FLL reference clock is the requested one. */
if (((SYSTEM_MCG_C1_VALUE) & MCG_C1_IREFS_MASK) != 0x00U) {
while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) {
}
} else {
while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) {
}
}
MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C2_LP_MASK))); /* Set C2 (freq. range, ext. and int. reference selection etc. excluding trim bits; low power bit is set later) */
MCG->C4 = ((SYSTEM_MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG->C4 & (MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK)); /* Set C4 (FLL output; trim values not changed) */
OSC->CR = SYSTEM_OSC_CR_VALUE; /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */
MCG->C7 = SYSTEM_MCG_C7_VALUE; /* Set C7 (OSC Clock Select) */
#if (MCG_MODE == MCG_MODE_BLPI)
/* BLPI specific */
MCG->C2 |= (MCG_C2_LP_MASK); /* Disable FLL and PLL in bypass mode */
#endif
#else /* MCG_MODE */
/* Set MCG and OSC */
#if (((SYSTEM_OSC_CR_VALUE) & OSC_CR_ERCLKEN_MASK) != 0x00U) || (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)
/* SIM_SCGC5: PORTA=1 */
SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
/* PORTA_PCR18: ISF=0,MUX=0 */
PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
if (((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) {
/* PORTA_PCR19: ISF=0,MUX=0 */
PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
}
#endif
MCG->SC = SYSTEM_MCG_SC_VALUE; /* Set SC (fast clock internal reference divider) */
MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C2_LP_MASK))); /* Set C2 (freq. range, ext. and int. reference selection etc. excluding trim bits; low power bit is set later) */
OSC->CR = SYSTEM_OSC_CR_VALUE; /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */
MCG->C7 = SYSTEM_MCG_C7_VALUE; /* Set C7 (OSC Clock Select) */
#if (MCG_MODE == MCG_MODE_PEE)
MCG->C1 = (SYSTEM_MCG_C1_VALUE) | MCG_C1_CLKS(0x02); /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) - PBE mode*/
#else
MCG->C1 = SYSTEM_MCG_C1_VALUE; /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) */
#endif
if ((((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) && (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)) {
while((MCG->S & MCG_S_OSCINIT0_MASK) == 0x00U) { /* Check that the oscillator is running */
}
}
/* Check that the source of the FLL reference clock is the requested one. */
if (((SYSTEM_MCG_C1_VALUE) & MCG_C1_IREFS_MASK) != 0x00U) {
while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) {
}
} else {
while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) {
}
}
MCG->C4 = ((SYSTEM_MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG->C4 & (MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK)); /* Set C4 (FLL output; trim values not changed) */
#endif /* MCG_MODE */
/* Common for all MCG modes */
/* PLL clock can be used to generate clock for some devices regardless of clock generator (MCGOUTCLK) mode. */
MCG->C5 = (SYSTEM_MCG_C5_VALUE) & (uint8_t)(~(MCG_C5_PLLCLKEN0_MASK)); /* Set C5 (PLL settings, PLL reference divider etc.) */
MCG->C6 = (SYSTEM_MCG_C6_VALUE) & (uint8_t)~(MCG_C6_PLLS_MASK); /* Set C6 (PLL select, VCO divider etc.) */
if ((SYSTEM_MCG_C5_VALUE) & MCG_C5_PLLCLKEN0_MASK) {
MCG->C5 |= MCG_C5_PLLCLKEN0_MASK; /* PLL clock enable in mode other than PEE or PBE */
}
/* BLPE, PEE and PBE MCG mode specific */
#if (MCG_MODE == MCG_MODE_BLPE)
MCG->C2 |= (MCG_C2_LP_MASK); /* Disable FLL and PLL in bypass mode */
#elif ((MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_PEE))
MCG->C6 |= (MCG_C6_PLLS_MASK); /* Set C6 (PLL select, VCO divider etc.) */
while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until PLL is locked*/
}
#if (MCG_MODE == MCG_MODE_PEE)
MCG->C1 &= (uint8_t)~(MCG_C1_CLKS_MASK);
#endif
#endif
#if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FEE))
while((MCG->S & MCG_S_CLKST_MASK) != 0x00U) { /* Wait until output of the FLL is selected */
}
#elif ((MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI))
while((MCG->S & MCG_S_CLKST_MASK) != 0x04U) { /* Wait until internal reference clock is selected as MCG output */
}
#elif ((MCG_MODE == MCG_MODE_FBE) || (MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_BLPE))
while((MCG->S & MCG_S_CLKST_MASK) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
}
#elif (MCG_MODE == MCG_MODE_PEE)
while((MCG->S & MCG_S_CLKST_MASK) != 0x0CU) { /* Wait until output of the PLL is selected */
}
#endif
#if (((SYSTEM_SMC_PMCTRL_VALUE) & SMC_PMCTRL_RUNM_MASK) == (0x02U << SMC_PMCTRL_RUNM_SHIFT))
SMC->PMCTRL = (uint8_t)((SYSTEM_SMC_PMCTRL_VALUE) & (SMC_PMCTRL_RUNM_MASK)); /* Enable VLPR mode */
while(SMC->PMSTAT != 0x04U) { /* Wait until the system is in VLPR mode */
}
#endif
#if defined(SYSTEM_SIM_CLKDIV2_VALUE)
SIM->CLKDIV2 = ((SIM->CLKDIV2) & (uint32_t)(~(SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK))) | ((SYSTEM_SIM_CLKDIV2_VALUE) & (SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK)); /* Selects the USB clock divider. */
#endif
/* PLL loss of lock interrupt request initialization */
if (((SYSTEM_MCG_C6_VALUE) & MCG_C6_LOLIE0_MASK) != 0U) {
NVIC_EnableIRQ(MCG_IRQn); /* Enable PLL loss of lock interrupt request */
}
}
/* ----------------------------------------------------------------------------
-- SystemCoreClockUpdate()
---------------------------------------------------------------------------- */
void SystemCoreClockUpdate (void) {
uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
uint16_t Divider;
if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
/* Output of FLL or PLL is selected */
if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) {
/* FLL is selected */
if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
/* External reference clock is selected */
switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
case 0x00U:
MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
break;
case 0x01U:
MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
break;
case 0x02U:
default:
MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
break;
}
if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
case 0x38U:
Divider = 1536U;
break;
case 0x30U:
Divider = 1280U;
break;
default:
Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
break;
}
} else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
}
MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
} else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
} /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
/* Select correct multiplier to calculate the MCG output clock */
switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
case 0x00U:
MCGOUTClock *= 640U;
break;
case 0x20U:
MCGOUTClock *= 1280U;
break;
case 0x40U:
MCGOUTClock *= 1920U;
break;
case 0x60U:
MCGOUTClock *= 2560U;
break;
case 0x80U:
MCGOUTClock *= 732U;
break;
case 0xA0U:
MCGOUTClock *= 1464U;
break;
case 0xC0U:
MCGOUTClock *= 2197U;
break;
case 0xE0U:
MCGOUTClock *= 2929U;
break;
default:
break;
}
} else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
/* PLL is selected */
Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U);
MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U);
MCGOUTClock *= Divider; /* Calculate the MCG output clock */
} /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
} else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
/* Internal reference clock is selected */
if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
} else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
} /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
} else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
/* External reference clock is selected */
switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
case 0x00U:
MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
break;
case 0x01U:
MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
break;
case 0x02U:
default:
MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
break;
}
} else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
/* Reserved value */
return;
} /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
}

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/*
** ###################################################################
** Compilers: Keil ARM C/C++ Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** GNU C Compiler - CodeSourcery Sourcery G++
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
** Version: rev. 2.5, 2014-05-06
** Build: b140611
**
** Abstract:
** Provides a system configuration function and a global variable that
** contains the system frequency. It configures the device and initializes
** the oscillator (PLL) that is part of the microcontroller device.
**
** Copyright (c) 2014 Freescale Semiconductor, Inc.
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** Revisions:
** - rev. 1.0 (2013-07-23)
** Initial version.
** - rev. 1.1 (2013-09-17)
** RM rev. 0.4 update.
** - rev. 2.0 (2013-10-29)
** Register accessor macros added to the memory map.
** Symbols for Processor Expert memory map compatibility added to the memory map.
** Startup file for gcc has been updated according to CMSIS 3.2.
** System initialization updated.
** - rev. 2.1 (2013-10-30)
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
** - rev. 2.2 (2013-12-20)
** Update according to reference manual rev. 0.6,
** - rev. 2.3 (2014-01-13)
** Update according to reference manual rev. 0.61,
** - rev. 2.4 (2014-02-10)
** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
** - rev. 2.5 (2014-05-06)
** Update according to reference manual rev. 1.0,
** Update of system and startup files.
** Module access macro module_BASES replaced by module_BASE_PTRS.
**
** ###################################################################
*/
/*!
* @file MK22F51212
* @version 2.5
* @date 2014-05-06
* @brief Device specific configuration file for MK22F51212 (header file)
*
* Provides a system configuration function and a global variable that contains
* the system frequency. It configures the device and initializes the oscillator
* (PLL) that is part of the microcontroller device.
*/
#ifndef SYSTEM_MK22F51212_H_
#define SYSTEM_MK22F51212_H_ /**< Symbol preventing repeated inclusion */
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#define DISABLE_WDOG 1
#ifndef CLOCK_SETUP
#define CLOCK_SETUP 4
#endif
/* MCG mode constants */
#define MCG_MODE_FEI 0U
#define MCG_MODE_FBI 1U
#define MCG_MODE_BLPI 2U
#define MCG_MODE_FEE 3U
#define MCG_MODE_FBE 4U
#define MCG_MODE_BLPE 5U
#define MCG_MODE_PBE 6U
#define MCG_MODE_PEE 7U
/* Predefined clock setups
0 ... Default part configuration
Multipurpose Clock Generator (MCG) in FEI mode.
Reference clock source for MCG module: Slow internal reference clock
Core clock = 20.97152MHz
Bus clock = 20.97152MHz
1 ... Maximum achievable clock frequency configuration
Multipurpose Clock Generator (MCG) in PEE mode.
Reference clock source for MCG module: System oscillator 0 reference clock
Core clock = 120MHz
Bus clock = 60MHz
2 ... Chip internaly clocked, ready for Very Low Power Run mode.
Multipurpose Clock Generator (MCG) in BLPI mode.
Reference clock source for MCG module: Fast internal reference clock
Core clock = 4MHz
Bus clock = 4MHz
3 ... Chip externally clocked, ready for Very Low Power Run mode.
Multipurpose Clock Generator (MCG) in BLPE mode.
Reference clock source for MCG module: System oscillator 0 reference clock
Core clock = 4MHz
Bus clock = 4MHz
4 ... USB clock setup
Multipurpose Clock Generator (MCG) in PEE mode.
Reference clock source for MCG module: System oscillator 0 reference clock
Core clock = 120MHz
Bus clock = 60MHz
5 ... Maximum achievable clock frequency configuration in RUN mode
Multipurpose Clock Generator (MCG) in PEE mode.
Reference clock source for MCG module: System oscillator 0 reference clock
Core clock = 80MHz
Bus clock = 40MHz
*/
/* Define clock source values */
#define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
#define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */
/* RTC oscillator setting */
/* RTC_CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0,CLKO=1,OSCE=1,WPS=0,UM=0,SUP=0,WPE=0,SWR=0 */
#define SYSTEM_RTC_CR_VALUE 0x0300U /* RTC_CR */
/* Low power mode enable */
/* SMC_PMPROT: AHSRUN=1,AVLP=1,ALLS=1,AVLLS=1 */
#define SYSTEM_SMC_PMPROT_VALUE 0xAAU /* SMC_PMPROT */
/* Internal reference clock trim */
/* #undef SLOW_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
/* #undef SLOW_FINE_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
/* #undef FAST_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
/* #undef FAST_FINE_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
#if (CLOCK_SETUP == 0)
#define DEFAULT_SYSTEM_CLOCK 20971520u /* Default System clock value */
#define MCG_MODE MCG_MODE_FEI /* Clock generator mode */
/* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
#define SYSTEM_MCG_C1_VALUE 0x06U /* MCG_C1 */
/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
#define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
#define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
/* MCG_C7: OSCSEL=0 */
#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
/* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
#define SYSTEM_OSC_CR_VALUE 0x00U /* OSC_CR */
/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1 */
#define SYSTEM_SIM_CLKDIV1_VALUE 0x00110000U /* SIM_CLKDIV1 */
/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */
#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
/* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=0,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
#define SYSTEM_SIM_SOPT2_VALUE 0x00U /* SIM_SOPT2 */
#elif (CLOCK_SETUP == 1)
#define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value */
#define MCG_MODE MCG_MODE_PEE /* Clock generator mode */
/* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
#define SYSTEM_MCG_C1_VALUE 0x1AU /* MCG_C1 */
/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
#define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */
#define SYSTEM_MCG_C5_VALUE 0x01U /* MCG_C5 */
/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=6 */
#define SYSTEM_MCG_C6_VALUE 0x46U /* MCG_C6 */
/* MCG_C7: OSCSEL=0 */
#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
/* SMC_PMCTRL: RUNM=3,STOPA=0,STOPM=0 */
#define SYSTEM_SMC_PMCTRL_VALUE 0x60U /* SMC_PMCTRL */
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */
#define SYSTEM_SIM_CLKDIV1_VALUE 0x01140000U /* SIM_CLKDIV1 */
/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */
#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
/* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
#define SYSTEM_SIM_SOPT2_VALUE 0x00010000U /* SIM_SOPT2 */
#elif (CLOCK_SETUP == 2)
#define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */
#define MCG_MODE MCG_MODE_BLPI /* Clock generator mode */
/* MCG_C1: CLKS=1,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
#define SYSTEM_MCG_C1_VALUE 0x46U /* MCG_C1 */
/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=1,IRCS=1 */
#define SYSTEM_MCG_C2_VALUE 0x27U /* MCG_C2 */
/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
#define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
/* MCG_C7: OSCSEL=0 */
#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=4 */
#define SYSTEM_SIM_CLKDIV1_VALUE 0x00040000U /* SIM_CLKDIV1 */
/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */
#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
/* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
#define SYSTEM_SIM_SOPT2_VALUE 0x00030000U /* SIM_SOPT2 */
#elif (CLOCK_SETUP == 3)
#define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */
#define MCG_MODE MCG_MODE_BLPE /* Clock generator mode */
/* MCG_C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
#define SYSTEM_MCG_C1_VALUE 0x9AU /* MCG_C1 */
/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=1,IRCS=1 */
#define SYSTEM_MCG_C2_VALUE 0x27U /* MCG_C2 */
/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=1,LOCS0=0 */
#define SYSTEM_MCG_SC_VALUE 0x02U /* MCG_SC */
/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
#define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
/* MCG_C7: OSCSEL=0 */
#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
/* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
#define SYSTEM_OSC_CR_VALUE 0x00U /* OSC_CR */
/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
/* SIM_CLKDIV1: OUTDIV1=1,OUTDIV2=1,OUTDIV3=1,OUTDIV4=7 */
#define SYSTEM_SIM_CLKDIV1_VALUE 0x11170000U /* SIM_CLKDIV1 */
/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */
#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
/* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
#define SYSTEM_SIM_SOPT2_VALUE 0x00030000U /* SIM_SOPT2 */
#elif (CLOCK_SETUP == 4)
#define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value */
#define MCG_MODE MCG_MODE_PEE /* Clock generator mode */
/* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
#define SYSTEM_MCG_C1_VALUE 0x1AU /* MCG_C1 */
/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
#define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */
#define SYSTEM_MCG_C5_VALUE 0x01U /* MCG_C5 */
/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=6 */
#define SYSTEM_MCG_C6_VALUE 0x46U /* MCG_C6 */
/* MCG_C7: OSCSEL=0 */
#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
/* SMC_PMCTRL: RUNM=3,STOPA=0,STOPM=0 */
#define SYSTEM_SMC_PMCTRL_VALUE 0x60U /* SMC_PMCTRL */
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */
#define SYSTEM_SIM_CLKDIV1_VALUE 0x01140000U /* SIM_CLKDIV1 */
/* SIM_CLKDIV2: USBDIV=4,USBFRAC=1 */
#define SYSTEM_SIM_CLKDIV2_VALUE 0x09U /* SIM_CLKDIV2 */
/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */
#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
/* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
#define SYSTEM_SIM_SOPT2_VALUE 0x00010000U /* SIM_SOPT2 */
#elif (CLOCK_SETUP == 5)
#define DEFAULT_SYSTEM_CLOCK 80000000u /* Default System clock value */
#define MCG_MODE MCG_MODE_PEE /* Clock generator mode */
/* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
#define SYSTEM_MCG_C1_VALUE 0x1AU /* MCG_C1 */
/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
#define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=3 */
#define SYSTEM_MCG_C5_VALUE 0x03U /* MCG_C5 */
/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0x10 */
#define SYSTEM_MCG_C6_VALUE 0x50U /* MCG_C6 */
/* MCG_C7: OSCSEL=0 */
#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=3 */
#define SYSTEM_SIM_CLKDIV1_VALUE 0x01130000U /* SIM_CLKDIV1 */
/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */
#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
/* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
#define SYSTEM_SIM_SOPT2_VALUE 0x00010000U /* SIM_SOPT2 */
#endif
/**
* @brief System clock frequency (core clock)
*
* The system clock frequency supplied to the SysTick timer and the processor
* core clock. This variable can be used by the user application to setup the
* SysTick timer or configure other parameters. It may also be used by debugger to
* query the frequency of the debug timer or configure the trace clock speed
* SystemCoreClock is initialized with a correct predefined value.
*/
extern uint32_t SystemCoreClock;
/**
* @brief Setup the microcontroller system.
*
* Typically this function configures the oscillator (PLL) that is part of the
* microcontroller device. For systems with variable clock speed it also updates
* the variable SystemCoreClock. SystemInit is called from startup_device file.
*/
void SystemInit (void);
/**
* @brief Updates the SystemCoreClock variable.
*
* It must be called whenever the core clock is changed during program
* execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
* the current core clock.
*/
void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* #if !defined(SYSTEM_MK22F51212_H_) */

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593
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@ -1,21 +1,48 @@
/*
** ###################################################################
** Processor: MK64FN1M0VMD12
** Compilers: ARM Compiler
** Compilers: Keil ARM C/C++ Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** GNU C Compiler - CodeSourcery Sourcery G++
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manual: K64P144M120SF5RM, Rev.1, July 2013
** Version: rev. 2.1, 2013-10-29
** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
** Version: rev. 2.5, 2014-02-10
** Build: b140611
**
** Abstract:
** Provides a system configuration function and a global variable that
** contains the system frequency. It configures the device and initializes
** the oscillator (PLL) that is part of the microcontroller device.
**
** Copyright: 2013 Freescale, Inc. All Rights Reserved.
** Copyright (c) 2014 Freescale Semiconductor, Inc.
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.freescale.com
** mail: support@freescale.com
@ -30,16 +57,29 @@
** System initialization updated.
** MCG - registers updated.
** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
** - rev. 2.1 (2013-10-29)
** - rev. 2.1 (2013-10-30)
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
** - rev. 2.2 (2013-12-09)
** DMA - EARS register removed.
** AIPS0, AIPS1 - MPRA register updated.
** - rev. 2.3 (2014-01-24)
** Update according to reference manual rev. 2
** ENET, MCG, MCM, SIM, USB - registers updated
** - rev. 2.4 (2014-02-10)
** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
** Update of SystemInit() and SystemCoreClockUpdate() functions.
** - rev. 2.5 (2014-02-10)
** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
** Update of SystemInit() and SystemCoreClockUpdate() functions.
** Module access macro module_BASES replaced by module_BASE_PTRS.
**
** ###################################################################
*/
/*!
* @file MK64F12
* @version 2.1
* @date 2013-10-29
* @version 2.5
* @date 2014-02-10
* @brief Device specific configuration file for MK64F12 (implementation file)
*
* Provides a system configuration function and a global variable that contains
@ -48,72 +88,8 @@
*/
#include <stdint.h>
#include "MK64F12.h"
#include "cmsis.h"
#define DISABLE_WDOG 1
#ifndef CLOCK_SETUP
#define CLOCK_SETUP 4
#endif
/* Predefined clock setups
0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
Default part configuration.
Reference clock source for MCG module is the slow internal clock source 32.768kHz
Core clock = 20.97MHz, BusClock = 20.97MHz
1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
Maximum achievable clock frequency configuration.
Reference clock source for MCG module is an external clock source 50MHz
Core clock = 120MHz, BusClock = 60MHz
2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power Internal (BLPI) mode
Core clock/Bus clock derived directly from an fast internal clock 4MHz with no multiplication
The clock settings is ready for Very Low Power Run mode.
Core clock = 4MHz, BusClock = 4MHz
3 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode
Core clock/Bus clock derived directly from the RTC oscillator clock source 32.768kHz
The clock settings is ready for Very Low Power Run mode.
Core clock = 32.768kHz, BusClock = 32.768kHz
4 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
USB clock setup
USB clock divider is set for USB to receive 48MHz input clock.
Reference clock source for MCG module is an external clock source 50MHz
USB clock divider is set for USB to receive 48MHz input clock.
Core clock = 120MHz, BusClock = 60MHz
*/
/*----------------------------------------------------------------------------
Define clock source values
*----------------------------------------------------------------------------*/
#if (CLOCK_SETUP == 0)
#define CPU_XTAL_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */
#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
#define DEFAULT_SYSTEM_CLOCK 20485760u /* Default System clock value */
#elif (CLOCK_SETUP == 1)
#define CPU_XTAL_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */
#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
#define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value */
#elif (CLOCK_SETUP == 2)
#define CPU_XTAL_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */
#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
#define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */
#elif (CLOCK_SETUP == 3)
#define CPU_XTAL_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */
#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
#define DEFAULT_SYSTEM_CLOCK 32768u /* Default System clock value */
#elif (CLOCK_SETUP == 4)
#define CPU_XTAL_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */
#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
#define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value */
#endif /* (CLOCK_SETUP == 4) */
/* ----------------------------------------------------------------------------
@ -131,7 +107,6 @@ void SystemInit (void) {
SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
#if (DISABLE_WDOG)
/* Disable the WDOG module */
/* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
/* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
@ -144,197 +119,165 @@ void SystemInit (void) {
WDOG_STCTRLH_CLKSRC_MASK |
0x0100U;
#endif /* (DISABLE_WDOG) */
/*
* Release hold with ACKISO: Only has an effect if recovering from VLLSx.
* if ACKISO is set you must clear ackiso before initializing the PLL
* if osc enabled in low power modes - enable it first before ack
*/
if (PMC->REGSC & PMC_REGSC_ACKISO_MASK)
if((RCM->SRS0 & RCM_SRS0_WAKEUP_MASK) != 0x00U)
{
PMC->REGSC |= PMC_REGSC_ACKISO_MASK;
if((PMC->REGSC & PMC_REGSC_ACKISO_MASK) != 0x00U)
{
PMC->REGSC |= PMC_REGSC_ACKISO_MASK; /* Release hold with ACKISO: Only has an effect if recovering from VLLSx.*/
}
} else {
#ifdef SYSTEM_RTC_CR_VALUE
SIM_SCGC6 |= SIM_SCGC6_RTC_MASK;
if ((RTC_CR & RTC_CR_OSCE_MASK) == 0x00U) { /* Only if the OSCILLATOR is not already enabled */
RTC_CR = (uint32_t)((RTC_CR & (uint32_t)~(uint32_t)(RTC_CR_SC2P_MASK | RTC_CR_SC4P_MASK | RTC_CR_SC8P_MASK | RTC_CR_SC16P_MASK)) | (uint32_t)SYSTEM_RTC_CR_VALUE);
RTC_CR |= (uint32_t)RTC_CR_OSCE_MASK;
RTC_CR &= (uint32_t)~(uint32_t)RTC_CR_CLKO_MASK;
}
#endif
}
#if (CLOCK_SETUP == 0)
/* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0 */
SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |
SIM_CLKDIV1_OUTDIV2(0x00) |
SIM_CLKDIV1_OUTDIV3(0x01) |
SIM_CLKDIV1_OUTDIV4(0x01); /* Update system prescalers */
/* SIM->SOPT2: PLLFLLSEL=0 */
SIM->SOPT2 &= (uint32_t)~(uint32_t)(SIM_SOPT2_PLLFLLSEL_MASK); /* Select FLL as a clock source for various peripherals */
/* SIM->SOPT1: OSC32KSEL=3 */
SIM->SOPT1 |= SIM_SOPT1_OSC32KSEL(0x03); /* LPO 1kHz oscillator drives 32 kHz clock for various peripherals */
/* Switch to FEI Mode */
/* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
MCG->C1 = MCG_C1_CLKS(0x00) |
MCG_C1_FRDIV(0x00) |
MCG_C1_IREFS_MASK |
MCG_C1_IRCLKEN_MASK;
/* MCG->C2: LOCRE0=0,?=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
MCG->C2 = MCG_C2_RANGE0(0x00);
/* MCG->C4: DMX32=0,DRST_DRS=0 */
MCG->C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03)));
/* OSC->CR: ERCLKEN=1,?=0,EREFSTEN=0,?=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
OSC->CR = OSC_CR_ERCLKEN_MASK;
/* MCG->C7: OSCSEL=0 */
MCG->C7 &= (uint8_t)~(uint8_t)(MCG_C7_OSCSEL_MASK);
/* MCG->C5: ?=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
MCG->C5 = MCG_C5_PRDIV0(0x00);
/* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
MCG->C6 = MCG_C6_VDIV0(0x00);
while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
}
while((MCG->S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */
}
#elif (CLOCK_SETUP == 1) || (CLOCK_SETUP == 4)
/* SIM->SCGC5: PORTA=1 */
SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK; /* Enable clock gate for ports to enable pin routing */
/* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0 */
SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |
SIM_CLKDIV1_OUTDIV2(0x01) |
SIM_CLKDIV1_OUTDIV3(0x02) |
SIM_CLKDIV1_OUTDIV4(0x04); /* Update system prescalers */
/* SIM->SOPT2: PLLFLLSEL=1 */
SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK; /* Select PLL as a clock source for various peripherals */
/* SIM->SOPT1: OSC32KSEL=3 */
SIM->SOPT1 |= SIM_SOPT1_OSC32KSEL(0x03); /* LPO 1kHz oscillator drives 32 kHz clock for various peripherals */
/* PORTA->PCR[18]: ISF=0,MUX=0 */
PORTA->PCR[18] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
/* Switch to FBE Mode */
/* MCG->C2: LOCRE0=0,?=0,RANGE0=2,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
MCG->C2 = MCG_C2_RANGE0(0x02);
/* OSC->CR: ERCLKEN=1,?=0,EREFSTEN=0,?=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
OSC->CR = OSC_CR_ERCLKEN_MASK;
/* MCG->C7: OSCSEL=0 */
MCG->C7 &= (uint8_t)~(uint8_t)(MCG_C7_OSCSEL_MASK);
/* MCG->C1: CLKS=2,FRDIV=5,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
MCG->C1 = (MCG_C1_CLKS(0x02) | MCG_C1_FRDIV(0x07) | MCG_C1_IRCLKEN_MASK);
/* MCG->C4: DMX32=0,DRST_DRS=0 */
MCG->C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03)));
/* MCG->C5: ?=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0x13 */
MCG->C5 = MCG_C5_PRDIV0(0x13);
/* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0x18 */
MCG->C6 = MCG_C6_VDIV0(0x18);
while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
}
while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
}
/* Switch to PBE Mode */
/* MCG->C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0x18 */
MCG->C6 = (MCG_C6_PLLS_MASK | MCG_C6_VDIV0(0x18));
while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
}
while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until locked */
}
/* Switch to PEE Mode */
/* MCG->C1: CLKS=0,FRDIV=5,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
MCG->C1 = (MCG_C1_CLKS(0x00) | MCG_C1_FRDIV(0x05) | MCG_C1_IRCLKEN_MASK);
while((MCG->S & 0x0CU) != 0x0CU) { /* Wait until output of the PLL is selected */
}
#if (CLOCK_SETUP == 4)
/* Set USB input clock to 48MHz */
/* SIM->CLKDIV2: USBDIV=4,USBFRAC=1 */
SIM->CLKDIV2 = (uint32_t)((SIM->CLKDIV2 & (uint32_t)~(uint32_t)(
SIM_CLKDIV2_USBDIV(0x03)
)) | (uint32_t)(
SIM_CLKDIV2_USBDIV(0x04) |
SIM_CLKDIV2_USBFRAC_MASK
));
/* Power mode protection initialization */
#ifdef SYSTEM_SMC_PMPROT_VALUE
SMC->PMPROT = SYSTEM_SMC_PMPROT_VALUE;
#endif
/* System clock initialization */
/* Internal reference clock trim initialization */
#if defined(SLOW_TRIM_ADDRESS)
if ( *((uint8_t*)SLOW_TRIM_ADDRESS) != 0xFFU) { /* Skip if non-volatile flash memory is erased */
MCG->C3 = *((uint8_t*)SLOW_TRIM_ADDRESS);
#endif /* defined(SLOW_TRIM_ADDRESS) */
#if defined(SLOW_FINE_TRIM_ADDRESS)
MCG->C4 = (MCG->C4 & ~(MCG_C4_SCFTRIM_MASK)) | ((*((uint8_t*) SLOW_FINE_TRIM_ADDRESS)) & MCG_C4_SCFTRIM_MASK);
#endif
#elif (CLOCK_SETUP == 2)
/* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=4,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0 */
SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |
SIM_CLKDIV1_OUTDIV2(0x00) |
SIM_CLKDIV1_OUTDIV3(0x00) |
SIM_CLKDIV1_OUTDIV4(0x04); /* Update system prescalers */
/* SIM->SOPT2: PLLFLLSEL=0 */
SIM->SOPT2 &= (uint32_t)~(uint32_t)(SIM_SOPT2_PLLFLLSEL_MASK); /* Select FLL as a clock source for various peripherals */
/* SIM->SOPT1: OSC32KSEL=3 */
SIM->SOPT1 |= SIM_SOPT1_OSC32KSEL(0x03); /* LPO 1kHz oscillator drives 32 kHz clock for various peripherals */
/* MCG->SC: FCRDIV=0 */
MCG->SC &= (uint8_t)~(uint8_t)(MCG_SC_FCRDIV(0x07));
/* Switch to FBI Mode */
/* MCG->C1: CLKS=1,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
MCG->C1 = MCG_C1_CLKS(0x01) |
MCG_C1_FRDIV(0x00) |
MCG_C1_IREFS_MASK |
MCG_C1_IRCLKEN_MASK;
/* MCG->C2: LOCRE0=0,?=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=1 */
MCG->C2 = (MCG_C2_RANGE0(0x00) | MCG_C2_IRCS_MASK);
/* MCG->C4: DMX32=0,DRST_DRS=0 */
MCG->C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03)));
/* OSC->CR: ERCLKEN=1,?=0,EREFSTEN=0,?=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
OSC->CR = OSC_CR_ERCLKEN_MASK;
/* MCG->C7: OSCSEL=0 */
MCG->C7 &= (uint8_t)~(uint8_t)(MCG_C7_OSCSEL_MASK);
/* MCG->C5: ?=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
MCG->C5 = MCG_C5_PRDIV0(0x00);
/* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
MCG->C6 = MCG_C6_VDIV0(0x00);
while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
#if defined(FAST_TRIM_ADDRESS)
MCG->C4 = (MCG->C4 & ~(MCG_C4_FCTRIM_MASK)) |((*((uint8_t*) FAST_TRIM_ADDRESS)) & MCG_C4_FCTRIM_MASK);
#endif
#if defined(FAST_FINE_TRIM_ADDRESS)
MCG->C2 = (MCG->C2 & ~(MCG_C2_FCFTRIM_MASK)) | ((*((uint8_t*)FAST_TRIM_ADDRESS)) & MCG_C2_FCFTRIM_MASK);
#endif /* defined(FAST_FINE_TRIM_ADDRESS) */
#if defined(SLOW_TRIM_ADDRESS)
}
while((MCG->S & 0x0CU) != 0x04U) { /* Wait until internal reference clock is selected as MCG output */
}
/* Switch to BLPI Mode */
/* MCG->C2: LOCRE0=0,?=0,RANGE0=0,HGO0=0,EREFS0=0,LP=1,IRCS=1 */
MCG->C2 = (MCG_C2_RANGE0(0x00) | MCG_C2_LP_MASK | MCG_C2_IRCS_MASK);
while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
}
while((MCG->S & MCG_S_IRCST_MASK) == 0x00U) { /* Check that the fast external reference clock is selected. */
}
#elif (CLOCK_SETUP == 3)
/* SIM->SCGC6: RTC=1 */
SIM->SCGC6 |= SIM_SCGC6_RTC_MASK;
if ((RTC->CR & RTC_CR_OSCE_MASK) == 0u) { /* Only if the OSCILLATOR is not already enabled */
/* RTC->CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
RTC->CR &= (uint32_t)~(uint32_t)(
RTC_CR_SC2P_MASK |
RTC_CR_SC4P_MASK |
RTC_CR_SC8P_MASK |
RTC_CR_SC16P_MASK
);
/* RTC->CR: OSCE=1 */
RTC->CR |= RTC_CR_OSCE_MASK;
/* RTC->CR: CLKO=0 */
RTC->CR &= (uint32_t)~(uint32_t)(RTC_CR_CLKO_MASK);
}
/* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0 */
SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |
SIM_CLKDIV1_OUTDIV2(0x00) |
SIM_CLKDIV1_OUTDIV3(0x00) |
SIM_CLKDIV1_OUTDIV4(0x00); /* Update system prescalers */
/* SIM->SOPT1: OSC32KSEL=2 */
SIM->SOPT1 = (uint32_t)((SIM->SOPT1 & (uint32_t)~(uint32_t)(
SIM_SOPT1_OSC32KSEL(0x01)
)) | (uint32_t)(
SIM_SOPT1_OSC32KSEL(0x02)
)); /* System oscillator drives 32 kHz clock for various peripherals */
/* Switch to FBE Mode */
/* MCG->C2: LOCRE0=0,?=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
MCG->C2 = MCG_C2_RANGE0(0x00);
/* OSC->CR: ERCLKEN=1,?=0,EREFSTEN=0,?=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
OSC->CR = OSC_CR_ERCLKEN_MASK;
/* MCG->C7: OSCSEL=1 */
MCG->C7 |= MCG_C7_OSCSEL_MASK;
/* MCG->C1: CLKS=2,FRDIV=0,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
MCG->C1 = (MCG_C1_CLKS(0x02) | MCG_C1_FRDIV(0x00) | MCG_C1_IRCLKEN_MASK);
/* MCG->C4: DMX32=0,DRST_DRS=0 */
MCG->C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03)));
/* MCG->C5: ?=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
MCG->C5 = MCG_C5_PRDIV0(0x00);
/* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
MCG->C6 = MCG_C6_VDIV0(0x00);
while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
}
while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
}
/* Switch to BLPE Mode */
/* MCG->C2: LOCRE0=0,?=0,RANGE0=0,HGO0=0,EREFS0=0,LP=1,IRCS=0 */
MCG->C2 = (MCG_C2_RANGE0(0x00) | MCG_C2_LP_MASK);
while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
#endif /* defined(SLOW_TRIM_ADDRESS) */
/* Set system prescalers and clock sources */
SIM->CLKDIV1 = SYSTEM_SIM_CLKDIV1_VALUE; /* Set system prescalers */
SIM->SOPT1 = ((SIM->SOPT1) & (uint32_t)(~(SIM_SOPT1_OSC32KSEL_MASK))) | ((SYSTEM_SIM_SOPT1_VALUE) & (SIM_SOPT1_OSC32KSEL_MASK)); /* Set 32 kHz clock source (ERCLK32K) */
SIM->SOPT2 = ((SIM->SOPT2) & (uint32_t)(~(SIM_SOPT2_PLLFLLSEL_MASK))) | ((SYSTEM_SIM_SOPT2_VALUE) & (SIM_SOPT2_PLLFLLSEL_MASK)); /* Selects the high frequency clock for various peripheral clocking options. */
#if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI))
/* Set MCG and OSC */
#if ((((SYSTEM_OSC_CR_VALUE) & OSC_CR_ERCLKEN_MASK) != 0x00U) || ((((SYSTEM_MCG_C5_VALUE) & MCG_C5_PLLCLKEN0_MASK) != 0x00U) && (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)))
/* SIM_SCGC5: PORTA=1 */
SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
/* PORTA_PCR18: ISF=0,MUX=0 */
PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
if (((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) {
/* PORTA_PCR19: ISF=0,MUX=0 */
PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
}
#endif
MCG->SC = SYSTEM_MCG_SC_VALUE; /* Set SC (fast clock internal reference divider) */
MCG->C1 = SYSTEM_MCG_C1_VALUE; /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) */
/* Check that the source of the FLL reference clock is the requested one. */
if (((SYSTEM_MCG_C1_VALUE) & MCG_C1_IREFS_MASK) != 0x00U) {
while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) {
}
} else {
while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) {
}
}
MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C2_LP_MASK))); /* Set C2 (freq. range, ext. and int. reference selection etc. excluding trim bits; low power bit is set later) */
MCG->C4 = ((SYSTEM_MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG->C4 & (MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK)); /* Set C4 (FLL output; trim values not changed) */
OSC->CR = SYSTEM_OSC_CR_VALUE; /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */
MCG->C7 = SYSTEM_MCG_C7_VALUE; /* Set C7 (OSC Clock Select) */
#if (MCG_MODE == MCG_MODE_BLPI)
/* BLPI specific */
MCG->C2 |= (MCG_C2_LP_MASK); /* Disable FLL and PLL in bypass mode */
#endif
#else /* MCG_MODE */
/* Set MCG and OSC */
#if (((SYSTEM_OSC_CR_VALUE) & OSC_CR_ERCLKEN_MASK) != 0x00U) || (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)
/* SIM_SCGC5: PORTA=1 */
SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
/* PORTA_PCR18: ISF=0,MUX=0 */
PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
if (((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) {
/* PORTA_PCR19: ISF=0,MUX=0 */
PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
}
#endif
MCG->SC = SYSTEM_MCG_SC_VALUE; /* Set SC (fast clock internal reference divider) */
MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C2_LP_MASK))); /* Set C2 (freq. range, ext. and int. reference selection etc. excluding trim bits; low power bit is set later) */
OSC->CR = SYSTEM_OSC_CR_VALUE; /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */
MCG->C7 = SYSTEM_MCG_C7_VALUE; /* Set C7 (OSC Clock Select) */
#if (MCG_MODE == MCG_MODE_PEE)
MCG->C1 = (SYSTEM_MCG_C1_VALUE) | MCG_C1_CLKS(0x02); /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) - PBE mode*/
#else
MCG->C1 = SYSTEM_MCG_C1_VALUE; /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) */
#endif
if ((((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) && (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)) {
while((MCG->S & MCG_S_OSCINIT0_MASK) == 0x00U) { /* Check that the oscillator is running */
}
}
/* Check that the source of the FLL reference clock is the requested one. */
if (((SYSTEM_MCG_C1_VALUE) & MCG_C1_IREFS_MASK) != 0x00U) {
while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) {
}
} else {
while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) {
}
}
MCG->C4 = ((SYSTEM_MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG->C4 & (MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK)); /* Set C4 (FLL output; trim values not changed) */
#endif /* MCG_MODE */
/* Common for all MCG modes */
/* PLL clock can be used to generate clock for some devices regardless of clock generator (MCGOUTCLK) mode. */
MCG->C5 = (SYSTEM_MCG_C5_VALUE) & (uint8_t)(~(MCG_C5_PLLCLKEN0_MASK)); /* Set C5 (PLL settings, PLL reference divider etc.) */
MCG->C6 = (SYSTEM_MCG_C6_VALUE) & (uint8_t)~(MCG_C6_PLLS_MASK); /* Set C6 (PLL select, VCO divider etc.) */
if ((SYSTEM_MCG_C5_VALUE) & MCG_C5_PLLCLKEN0_MASK) {
MCG->C5 |= MCG_C5_PLLCLKEN0_MASK; /* PLL clock enable in mode other than PEE or PBE */
}
/* BLPE, PEE and PBE MCG mode specific */
#if (MCG_MODE == MCG_MODE_BLPE)
MCG->C2 |= (MCG_C2_LP_MASK); /* Disable FLL and PLL in bypass mode */
#elif ((MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_PEE))
MCG->C6 |= (MCG_C6_PLLS_MASK); /* Set C6 (PLL select, VCO divider etc.) */
while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until PLL is locked*/
}
#if (MCG_MODE == MCG_MODE_PEE)
MCG->C1 &= (uint8_t)~(MCG_C1_CLKS_MASK);
#endif
#endif
#if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FEE))
while((MCG->S & MCG_S_CLKST_MASK) != 0x00U) { /* Wait until output of the FLL is selected */
}
#elif ((MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI))
while((MCG->S & MCG_S_CLKST_MASK) != 0x04U) { /* Wait until internal reference clock is selected as MCG output */
}
#elif ((MCG_MODE == MCG_MODE_FBE) || (MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_BLPE))
while((MCG->S & MCG_S_CLKST_MASK) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
}
#elif (MCG_MODE == MCG_MODE_PEE)
while((MCG->S & MCG_S_CLKST_MASK) != 0x0CU) { /* Wait until output of the PLL is selected */
}
#endif
#if (((SYSTEM_SMC_PMCTRL_VALUE) & SMC_PMCTRL_RUNM_MASK) == (0x02U << SMC_PMCTRL_RUNM_SHIFT))
SMC->PMCTRL = (uint8_t)((SYSTEM_SMC_PMCTRL_VALUE) & (SMC_PMCTRL_RUNM_MASK)); /* Enable VLPR mode */
while(SMC->PMSTAT != 0x04U) { /* Wait until the system is in VLPR mode */
}
#endif
#if defined(SYSTEM_SIM_CLKDIV2_VALUE)
SIM->CLKDIV2 = ((SIM->CLKDIV2) & (uint32_t)(~(SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK))) | ((SYSTEM_SIM_CLKDIV2_VALUE) & (SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK)); /* Selects the USB clock divider. */
#endif
/* PLL loss of lock interrupt request initialization */
if (((SYSTEM_MCG_C6_VALUE) & MCG_C6_LOLIE0_MASK) != 0U) {
NVIC_EnableIRQ(MCG_IRQn); /* Enable PLL loss of lock interrupt request */
}
}
/* ----------------------------------------------------------------------------
@ -342,81 +285,107 @@ void SystemInit (void) {
---------------------------------------------------------------------------- */
void SystemCoreClockUpdate (void) {
uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
uint8_t Divider;
uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
uint16_t Divider;
if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) {
if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
/* Output of FLL or PLL is selected */
if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) {
if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) {
/* FLL is selected */
if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) {
if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
/* External reference clock is selected */
if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) {
MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
} else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
} /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) {
MCGOUTClock /= 32u; /* If high range is enabled, additional 32 divider is active */
} /* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) */
} else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
} /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
case 0x00U:
MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
break;
case 0x01U:
MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
break;
case 0x02U:
default:
MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
break;
}
if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
case 0x38U:
Divider = 1536U;
break;
case 0x30U:
Divider = 1280U;
break;
default:
Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
break;
}
} else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
}
MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
} else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
} /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
/* Select correct multiplier to calculate the MCG output clock */
switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
case 0x0u:
MCGOUTClock *= 640u;
case 0x00U:
MCGOUTClock *= 640U;
break;
case 0x20u:
MCGOUTClock *= 1280u;
case 0x20U:
MCGOUTClock *= 1280U;
break;
case 0x40u:
MCGOUTClock *= 1920u;
case 0x40U:
MCGOUTClock *= 1920U;
break;
case 0x60u:
MCGOUTClock *= 2560u;
case 0x60U:
MCGOUTClock *= 2560U;
break;
case 0x80u:
MCGOUTClock *= 732u;
case 0x80U:
MCGOUTClock *= 732U;
break;
case 0xA0u:
MCGOUTClock *= 1464u;
case 0xA0U:
MCGOUTClock *= 1464U;
break;
case 0xC0u:
MCGOUTClock *= 2197u;
case 0xC0U:
MCGOUTClock *= 2197U;
break;
case 0xE0u:
MCGOUTClock *= 2929u;
case 0xE0U:
MCGOUTClock *= 2929U;
break;
default:
break;
}
} else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
} else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
/* PLL is selected */
Divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
Divider = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
MCGOUTClock *= Divider; /* Calculate the MCG output clock */
} /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
} else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) {
Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U);
MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U);
MCGOUTClock *= Divider; /* Calculate the MCG output clock */
} /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
} else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
/* Internal reference clock is selected */
if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) {
MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
} else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); /* Fast internal reference clock selected */
} /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
} else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) {
if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
} else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
} /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
} else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
/* External reference clock is selected */
if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) {
MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
} else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
} /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
} else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
case 0x00U:
MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
break;
case 0x01U:
MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
break;
case 0x02U:
default:
MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
break;
}
} else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
/* Reserved value */
return;
} /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
} /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
}

261
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/system_MK64F12.h
View File

@ -1,21 +1,48 @@
/*
** ###################################################################
** Processor: MK64FN1M0VMD12
** Compilers: ARM Compiler
** Compilers: Keil ARM C/C++ Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** GNU C Compiler - CodeSourcery Sourcery G++
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manual: K64P144M120SF5RM, Rev.1, July 2013
** Version: rev. 2.1, 2013-10-29
** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
** Version: rev. 2.5, 2014-02-10
** Build: b140611
**
** Abstract:
** Provides a system configuration function and a global variable that
** contains the system frequency. It configures the device and initializes
** the oscillator (PLL) that is part of the microcontroller device.
**
** Copyright: 2013 Freescale, Inc. All Rights Reserved.
** Copyright (c) 2014 Freescale Semiconductor, Inc.
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.freescale.com
** mail: support@freescale.com
@ -30,16 +57,29 @@
** System initialization updated.
** MCG - registers updated.
** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
** - rev. 2.1 (2013-10-29)
** - rev. 2.1 (2013-10-30)
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
** - rev. 2.2 (2013-12-09)
** DMA - EARS register removed.
** AIPS0, AIPS1 - MPRA register updated.
** - rev. 2.3 (2014-01-24)
** Update according to reference manual rev. 2
** ENET, MCG, MCM, SIM, USB - registers updated
** - rev. 2.4 (2014-02-10)
** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
** Update of SystemInit() and SystemCoreClockUpdate() functions.
** - rev. 2.5 (2014-02-10)
** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
** Update of SystemInit() and SystemCoreClockUpdate() functions.
** Module access macro module_BASES replaced by module_BASE_PTRS.
**
** ###################################################################
*/
/*!
* @file MK64F12
* @version 2.1
* @date 2013-10-29
* @version 2.5
* @date 2014-02-10
* @brief Device specific configuration file for MK64F12 (header file)
*
* Provides a system configuration function and a global variable that contains
@ -56,6 +96,213 @@ extern "C" {
#include <stdint.h>
#define DISABLE_WDOG 1
#ifndef CLOCK_SETUP
#define CLOCK_SETUP 4
#endif
/* MCG mode constants */
#define MCG_MODE_FEI 0U
#define MCG_MODE_FBI 1U
#define MCG_MODE_BLPI 2U
#define MCG_MODE_FEE 3U
#define MCG_MODE_FBE 4U
#define MCG_MODE_BLPE 5U
#define MCG_MODE_PBE 6U
#define MCG_MODE_PEE 7U
/* Predefined clock setups
0 ... Default part configuration
Multipurpose Clock Generator (MCG) in FEI mode.
Reference clock source for MCG module: Slow internal reference clock
Core clock = 20.97152MHz
Bus clock = 20.97152MHz
1 ... Maximum achievable clock frequency configuration
Multipurpose Clock Generator (MCG) in PEE mode.
Reference clock source for MCG module: System oscillator 0 reference clock
Core clock = 120MHz
Bus clock = 60MHz
2 ... Chip internaly clocked, ready for Very Low Power Run mode.
Multipurpose Clock Generator (MCG) in BLPI mode.
Reference clock source for MCG module: Fast internal reference clock
Core clock = 4MHz
Bus clock = 4MHz
3 ... Chip externally clocked, ready for Very Low Power Run mode.
Multipurpose Clock Generator (MCG) in BLPE mode.
Reference clock source for MCG module: RTC oscillator reference clock
Core clock = 0.032768MHz
Bus clock = 0.032768MHz
4 ... USB clock setup
Multipurpose Clock Generator (MCG) in PEE mode.
Reference clock source for MCG module: System oscillator 0 reference clock
Core clock = 120MHz
Bus clock = 60MHz
*/
/* Define clock source values */
#define CPU_XTAL_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */
#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
#define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */
/* RTC oscillator setting */
/* RTC_CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0,CLKO=1,OSCE=1,WPS=0,UM=0,SUP=0,WPE=0,SWR=0 */
#define SYSTEM_RTC_CR_VALUE 0x0300U /* RTC_CR */
/* Low power mode enable */
/* SMC_PMPROT: AVLP=1,ALLS=1,AVLLS=1 */
#define SYSTEM_SMC_PMPROT_VALUE 0x2AU /* SMC_PMPROT */
/* Internal reference clock trim */
/* #undef SLOW_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
/* #undef SLOW_FINE_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
/* #undef FAST_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
/* #undef FAST_FINE_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
#if (CLOCK_SETUP == 0)
#define DEFAULT_SYSTEM_CLOCK 20971520u /* Default System clock value */
#define MCG_MODE MCG_MODE_FEI /* Clock generator mode */
/* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
#define SYSTEM_MCG_C1_VALUE 0x06U /* MCG_C1 */
/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=0,IRCS=0 */
#define SYSTEM_MCG_C2_VALUE 0x20U /* MCG_C2 */
/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
#define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
/* MCG_C7: OSCSEL=0 */
#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
/* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
#define SYSTEM_OSC_CR_VALUE 0x00U /* OSC_CR */
/* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1 */
#define SYSTEM_SIM_CLKDIV1_VALUE 0x00110000U /* SIM_CLKDIV1 */
/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
/* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=0,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
#define SYSTEM_SIM_SOPT2_VALUE 0x00U /* SIM_SOPT2 */
#elif (CLOCK_SETUP == 1)
#define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value */
#define MCG_MODE MCG_MODE_PEE /* Clock generator mode */
/* MCG_C1: CLKS=0,FRDIV=7,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
#define SYSTEM_MCG_C1_VALUE 0x3AU /* MCG_C1 */
/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=0,IRCS=0 */
#define SYSTEM_MCG_C2_VALUE 0x20U /* MCG_C2 */
/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0x13 */
#define SYSTEM_MCG_C5_VALUE 0x13U /* MCG_C5 */
/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0x18 */
#define SYSTEM_MCG_C6_VALUE 0x58U /* MCG_C6 */
/* MCG_C7: OSCSEL=0 */
#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
/* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */
#define SYSTEM_SIM_CLKDIV1_VALUE 0x01140000U /* SIM_CLKDIV1 */
/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
/* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
#define SYSTEM_SIM_SOPT2_VALUE 0x00010000U /* SIM_SOPT2 */
#elif (CLOCK_SETUP == 2)
#define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */
#define MCG_MODE MCG_MODE_BLPI /* Clock generator mode */
/* MCG_C1: CLKS=1,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
#define SYSTEM_MCG_C1_VALUE 0x46U /* MCG_C1 */
/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=1,IRCS=1 */
#define SYSTEM_MCG_C2_VALUE 0x23U /* MCG_C2 */
/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
#define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
/* MCG_C7: OSCSEL=0 */
#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
/* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=4 */
#define SYSTEM_SIM_CLKDIV1_VALUE 0x00040000U /* SIM_CLKDIV1 */
/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
/* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
#define SYSTEM_SIM_SOPT2_VALUE 0x00030000U /* SIM_SOPT2 */
#elif (CLOCK_SETUP == 3)
#define DEFAULT_SYSTEM_CLOCK 32768u /* Default System clock value */
#define MCG_MODE MCG_MODE_BLPE /* Clock generator mode */
/* MCG_C1: CLKS=2,FRDIV=0,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
#define SYSTEM_MCG_C1_VALUE 0x82U /* MCG_C1 */
/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=1,IRCS=1 */
#define SYSTEM_MCG_C2_VALUE 0x23U /* MCG_C2 */
/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=1,LOCS0=0 */
#define SYSTEM_MCG_SC_VALUE 0x02U /* MCG_SC */
/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
#define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
/* MCG_C7: OSCSEL=1 */
#define SYSTEM_MCG_C7_VALUE 0x01U /* MCG_C7 */
/* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
#define SYSTEM_OSC_CR_VALUE 0x00U /* OSC_CR */
/* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=0 */
#define SYSTEM_SIM_CLKDIV1_VALUE 0x00U /* SIM_CLKDIV1 */
/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
/* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
#define SYSTEM_SIM_SOPT2_VALUE 0x00030000U /* SIM_SOPT2 */
#elif (CLOCK_SETUP == 4)
#define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value */
#define MCG_MODE MCG_MODE_PEE /* Clock generator mode */
/* MCG_C1: CLKS=0,FRDIV=7,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
#define SYSTEM_MCG_C1_VALUE 0x3AU /* MCG_C1 */
/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=0,IRCS=0 */
#define SYSTEM_MCG_C2_VALUE 0x20U /* MCG_C2 */
/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0x13 */
#define SYSTEM_MCG_C5_VALUE 0x13U /* MCG_C5 */
/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0x18 */
#define SYSTEM_MCG_C6_VALUE 0x58U /* MCG_C6 */
/* MCG_C7: OSCSEL=0 */
#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
/* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */
#define SYSTEM_SIM_CLKDIV1_VALUE 0x01140000U /* SIM_CLKDIV1 */
/* SIM_CLKDIV2: USBDIV=4,USBFRAC=1 */
#define SYSTEM_SIM_CLKDIV2_VALUE 0x09U /* SIM_CLKDIV2 */
/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
/* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
#define SYSTEM_SIM_SOPT2_VALUE 0x00010000U /* SIM_SOPT2 */
#endif
/**
* @brief System clock frequency (core clock)
*

0
libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/PeripheralPins.h → libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/PeripheralPins.h
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0
libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/PortNames.h → libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/PortNames.h
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libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/MK22F51212/fsl_clock_K22F51212.c Normal file
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/*
* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <stdint.h>
#include <stdlib.h>
#include <stdbool.h>
#include "fsl_device_registers.h"
#include "fsl_sim_hal.h"
#include "fsl_clock_manager.h"
#include "fsl_osc_hal.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/* Table of base addresses for instances. */
extern const uint32_t g_simBaseAddr[];
extern const uint32_t g_mcgBaseAddr[];
const uint32_t g_oscBaseAddr[] = OSC_BASE_ADDRS;
/*******************************************************************************
* Code
******************************************************************************/
/*FUNCTION**********************************************************************
*
* Function Name : CLOCK_SYS_GetDmaFreq
* Description : Gets the clock frequency for DMA module
* This function gets the clock frequency for DMA moudle.
*
*END**************************************************************************/
uint32_t CLOCK_SYS_GetDmaFreq(uint32_t instance)
{
uint32_t freq = 0;
CLOCK_SYS_GetFreq(kSystemClock, &freq);
return freq;
}
/*FUNCTION**********************************************************************
*
* Function Name : CLOCK_SYS_GetDmamuxFreq
* Description : Gets the clock frequency for DMAMUX module
* This function gets the clock frequency for DMAMUX moudle.
*
*END**************************************************************************/
uint32_t CLOCK_SYS_GetDmamuxFreq(uint32_t instance)
{
uint32_t freq = 0;
CLOCK_SYS_GetFreq(kBusClock, &freq);
return freq;
}
/*FUNCTION**********************************************************************
*
* Function Name : CLOCK_SYS_GetPortFreq
* Description : Gets the clock frequency for PORT module
* This function gets the clock frequency for PORT moudle.
*
*END**************************************************************************/
uint32_t CLOCK_SYS_GetPortFreq(uint32_t instance)
{
uint32_t freq = 0;
CLOCK_SYS_GetFreq(kLpoClock, &freq);
return freq;
}
/*FUNCTION**********************************************************************
*
* Function Name : CLOCK_SYS_GetEwmFreq
* Description : Gets the clock frequency for Ewm module
* This function gets the clock frequency for Ewm moudle.
*
*END**************************************************************************/
uint32_t CLOCK_SYS_GetEwmFreq(uint32_t instance)
{
uint32_t freq = 0;
CLOCK_SYS_GetFreq(kLpoClock, &freq);
return freq;
}
/*FUNCTION**********************************************************************
*
* Function Name : CLOCK_SYS_GetFlexbusFreq
* Description : Gets the clock frequency for FLEXBUS module
* This function gets the clock frequency for FLEXBUS moudle.
*
*END**************************************************************************/
uint32_t CLOCK_SYS_GetFlexbusFreq(uint32_t instance)
{
uint32_t freq = 0;
CLOCK_SYS_GetFreq(kSystemClock, &freq);
return freq;
}
/*FUNCTION**********************************************************************
*
* Function Name : CLOCK_SYS_GetFtfFreq
* Description : Gets the clock frequency for FTF module. (Flash Memory)
* This function gets the clock frequency for FTF moudle.
*
*END**************************************************************************/
uint32_t CLOCK_SYS_GetFtfFreq(uint32_t instance)
{
uint32_t freq = 0;
CLOCK_SYS_GetFreq(kFlashClock, &freq);
return freq;
}
/*FUNCTION**********************************************************************
*
* Function Name : CLOCK_SYS_GetCrcFreq
* Description : Gets the clock frequency for CRC module
* This function gets the clock frequency for CRC moudle.
*
*END**************************************************************************/
uint32_t CLOCK_SYS_GetCrcFreq(uint32_t instance)
{
uint32_t freq = 0;
CLOCK_SYS_GetFreq(kBusClock, &freq);
return freq;
}
/*FUNCTION**********************************************************************
*
* Function Name : CLOCK_SYS_GetRngaFreq
* Description : Gets the clock frequency for RNGA module
* This function gets the clock frequency for RNGA moudle.
*
*END**************************************************************************/
uint32_t CLOCK_SYS_GetRngaFreq(uint32_t instance)
{
uint32_t freq = 0;
CLOCK_SYS_GetFreq(kBusClock, &freq);
return freq;
}
/*FUNCTION**********************************************************************
*
* Function Name : CLOCK_SYS_GetAdcFreq
* Description : Gets the clock frequency for ADC module
* This function gets the clock frequency for ADC moudle.
*
*END**************************************************************************/
uint32_t CLOCK_SYS_GetAdcFreq(uint32_t instance)
{
uint32_t freq = 0;
uint32_t divider;
CLOCK_SYS_GetFreq(kOsc0ErClock, &freq);
divider = OSC_HAL_GetExternalRefClkDivCmd(g_oscBaseAddr[0]);
freq = freq >> divider; /* 2 bits divider, divide by 1/2/4/8 */
return freq;
}
/*FUNCTION**********************************************************************
*
* Function Name : CLOCK_SYS_GetCmpFreq
* Description : Gets the clock frequency for CMP module
* This function gets the clock frequency for CMP moudle.
*
*END**************************************************************************/
uint32_t CLOCK_SYS_GetCmpFreq(uint32_t instance)
{
uint32_t freq = 0;
CLOCK_SYS_GetFreq(kBusClock, &freq);
return freq;
}
/*FUNCTION**********************************************************************
*
* Function Name : CLOCK_SYS_GetVrefFreq
* Description : Gets the clock frequency for VREF module
* This function gets the clock frequency for VREF moudle.
*
*END**************************************************************************/
uint32_t CLOCK_SYS_GetVrefFreq(uint32_t instance)
{
uint32_t freq = 0;
CLOCK_SYS_GetFreq(kBusClock, &freq);
return freq;
}
/*FUNCTION**********************************************************************
*
* Function Name : CLOCK_SYS_GetPdbFreq
* Description : Gets the clock frequency for PDB module
* This function gets the clock frequency for PDB moudle.
*
*END**************************************************************************/
uint32_t CLOCK_SYS_GetPdbFreq(uint32_t instance)
{
uint32_t freq = 0;
CLOCK_SYS_GetFreq(kBusClock, &freq);
return freq;
}
/*FUNCTION**********************************************************************
*
* Function Name : CLOCK_SYS_GetFtmFreq
* Description : Gets the clock frequency for FTM module. (FlexTimers)
* This function gets the clock frequency for FTM moudle.
*
*END**************************************************************************/
uint32_t CLOCK_SYS_GetFtmFreq(uint32_t instance)
{
uint32_t freq = 0;
CLOCK_SYS_GetFreq(kMcgFfClock, &freq);
return freq;
}
/*FUNCTION**********************************************************************
*
* Function Name : CLOCK_SYS_GetPitFreq
* Description : Gets the clock frequency for Pit module.
* This function gets the clock frequency for Pit moudle.
*
*END**************************************************************************/
uint32_t CLOCK_SYS_GetPitFreq(uint32_t instance)
{
uint32_t freq = 0;
CLOCK_SYS_GetFreq(kBusClock, &freq);
return freq;
}
/*FUNCTION**********************************************************************
*
* Function Name : CLOCK_SYS_GetUsbFreq
* Description : Gets the clock frequency for USB FS OTG module.
* This function gets the clock frequency for USB FS OTG moudle.
*
*END**************************************************************************/
uint32_t CLOCK_SYS_GetUsbFreq(uint32_t instance)
{
uint32_t freq = 0;
uint8_t setting;
clock_names_t clockName;
uint32_t frac = 0;
uint32_t divider = 0;
/* get the sim clock source setting*/
if (CLOCK_HAL_GetSource(g_simBaseAddr[0], kClockUsbSrc, &setting) != kSimHalSuccess)
{
return freq;
}
switch ((sim_usb_clock_source_t)setting)
{
case kSimUsbSrcClkIn: /* Core/system clock */
clockName = kUSB_CLKIN;
break;
case kSimUsbSrcPllFllSel: /* clock as selected by SOPT2[PLLFLLSEL]. */
/* get the sim clock source setting*/
if (CLOCK_HAL_GetSource(g_simBaseAddr[0], kClockPllfllSel, &setting) != kSimHalSuccess)
{
return freq;
}
switch ((sim_pllfll_clock_sel_t)setting)
{
case kSimPllFllSelFll: /* Fll clock */
clockName = kMcgFllClock;
break;
case kSimPllFllSelPll: /* Pll0 clock */
clockName = kMcgPll0Clock;
break;
case kSimPllFllSelIrc: /* Irc 48Mhz clock */
clockName = kIrc48mClock;
break;
default:
clockName = kReserved;
break;
}
break;
default:
clockName = kReserved;
break;
}
/* Get ref clock freq */
CLOCK_SYS_GetFreq(clockName, &freq);
/* Get divider and frac */
CLOCK_HAL_GetDivider(g_simBaseAddr[0], kClockDividerUsbDiv, &divider);
CLOCK_HAL_GetDivider(g_simBaseAddr[0], kClockDividerUsbFrac, &frac);
/* Divider output clock = Divider input clock × [ (FRAC+1) / (DIV+1) ]*/
freq = (freq) * (frac + 1) / (divider + 1);
return freq;
}
/*FUNCTION**********************************************************************
*
* Function Name : CLOCK_SYS_GetSpiFreq
* Description : Gets the clock frequency for SPI module.
* This function gets the clock frequency for SPI moudle.
*
*END**************************************************************************/
uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance)
{
uint32_t freq = 0;
CLOCK_SYS_GetFreq(kBusClock, &freq);
return freq;
}
/*FUNCTION**********************************************************************
*
* Function Name : CLOCK_SYS_GetI2cFreq
* Description : Gets the clock frequency for I2C module.
* This function gets the clock frequency for I2C moudle.
*
*END**************************************************************************/
uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance)
{
uint32_t freq = 0;
CLOCK_SYS_GetFreq(kBusClock, &freq);
return freq;
}
/*FUNCTION**********************************************************************
*
* Function Name : CLOCK_SYS_GetUartFreq
* Description : Gets the clock frequency for UART module.
* This function gets the clock frequency for UART moudle.
*
*END**************************************************************************/
uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance)
{
uint32_t freq = 0;
switch (instance)
{
case 0:
case 1:
CLOCK_SYS_GetFreq(kSystemClock, &freq);
break;
case 2:
CLOCK_SYS_GetFreq(kBusClock, &freq);
break;
default:
break;
}
return freq;
}
/*FUNCTION**********************************************************************
*
* Function Name : CLOCK_SYS_GetLpuartFreq
* Description : Gets the clock frequency for LPUART module.
* This function gets the clock frequency for LPUART moudle.
*
*END**************************************************************************/
uint32_t CLOCK_SYS_GetLpuartFreq(uint32_t instance)
{
uint32_t freq = 0;
uint8_t setting;
uint8_t setting1;
clock_names_t clockName;
uint32_t divider = 0;
/* get the sim clock source setting*/
if (CLOCK_HAL_GetSource(g_simBaseAddr[0], kClockLpuartSrc, &setting) != kSimHalSuccess)
{
return freq;
}
switch ((sim_lpuart_clock_source_t)setting)
{
case kSimLpuartSrcPllFllSel: /* clock as selected by SOPT2[PLLFLLSEL]. */
/* get the sim clock source setting*/
if (CLOCK_HAL_GetSource(g_simBaseAddr[0], kClockPllfllSel, &setting1) != kSimHalSuccess)
{
return freq;
}
switch ((sim_pllfll_clock_sel_t)setting1)
{
case kSimPllFllSelFll: /* Fll clock */
clockName = kMcgFllClock;
break;
case kSimPllFllSelPll: /* Pll0 clock */
clockName = kMcgPll0Clock;
break;
case kSimPllFllSelIrc: /* Irc 48Mhz clock */
clockName = kIrc48mClock;
break;
default:
clockName = kReserved;
break;
}
break;
case kSimLpuartSrcOscErclk: /* OscErClk with divider */
clockName = kOsc0ErClock;
break;
case kSimLpuartSrcMcgIrclk: /* MCGIRCLK */
clockName = kMcgIrClock;
break;
default:
clockName = kReserved;
break;
}
/* Get ref clock freq */
CLOCK_SYS_GetFreq(clockName, &freq);
if ((sim_lpuart_clock_source_t)setting == kSimLpuartSrcOscErclk)
{
divider = OSC_HAL_GetExternalRefClkDivCmd(g_oscBaseAddr[0]);
freq = freq >> divider; /* 2 bits divider, divide by 1/2/4/8 */
}
return freq;
}
/*FUNCTION**********************************************************************
*
* Function Name : CLOCK_SYS_GetSaiFreq
* Description : Gets the clock frequency for I2S module
* This function gets the clock frequency for I2S moudle.
*
*END**************************************************************************/
uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance)
{
uint32_t freq = 0;
CLOCK_SYS_GetFreq(kBusClock, &freq);
return freq;
}
/*FUNCTION**********************************************************************
*
* Function Name : CLOCK_SYS_GetGpioFreq
* Description : Gets the clock frequency for GPIO module.
* This function gets the clock frequency for GPIO moudle.
*
*END**************************************************************************/
uint32_t CLOCK_SYS_GetGpioFreq(uint32_t instance)
{
uint32_t freq = 0;
CLOCK_SYS_GetFreq(kPlatformClock, &freq);
return freq;
}
/*******************************************************************************
* EOF
******************************************************************************/

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libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/MK22F51212/fsl_sim_hal_K22F51212.c Normal file
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/*
* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#if !defined(__FSL_SIM_HAL_K22F51212_H__)
#define __FSL_SIM_HAL_K22F51212_H__
/*! @addtogroup sim_hal*/
/*! @{*/
/*! @file*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @brief SIM USB clock source */
typedef enum _sim_usb_clock_source
{
kSimUsbSrcClkIn, /* USB CLKIN Clock */
kSimUsbSrcPllFllSel /* clock as selected by SOPT2[PLLFLLSEL] */
} sim_usb_clock_source_t;
/*! @brief SIM LPUART clock source */
typedef enum _sim_lpuart_clock_source
{
kSimLpuartSrcNone, /* Clock disabled */
kSimLpuartSrcPllFllSel, /* Clock as selected by SOPT2[PLLFLLSEL] */
kSimLpuartSrcOscErclk, /* OscErClk with special divider */
kSimLpuartSrcMcgIrclk /* MCGIRCLK */
} sim_lpuart_clock_source_t;
/*! @brief SIM PLLFLLSEL clock source select */
typedef enum _sim_pllfll_clock_sel
{
kSimPllFllSelFll, /* Fll clock */
kSimPllFllSelPll, /* Pll0 clock */
kSimPllFllSelNone, /* reserved */
kSimPllFllSelIrc /* IRC 48Mhz */
} sim_pllfll_clock_sel_t;
/*! @brief SIM OSC32KSEL clock source select */
typedef enum _sim_osc32k_clock_sel
{
kSimOsc32kSelOsc32k, /* OSC 32k clock */
kSimOsc32kSelReserved, /* Reserved */
kSimOsc32kSelRtc32k, /* RTC 32k clock */
kSimOsc32kSelLpo /* LPO clock */
} sim_osc32k_clock_sel_t;
/*! @brief SIM TRACESEL clock source select */
typedef enum _sim_trace_clock_sel
{
kSimTraceMcgoutClk, /* MCG out clock */
kSimTraceCoreClk /* core clock */
} sim_trace_clock_sel_t;
/*! @brief SIM CLKOUT_SEL clock source select */
typedef enum _sim_clkout_clock_sel
{
kSimClkoutFlexbusClk, /* Flexbus clock */
kSimClkoutReserved, /* Reserved */
kSimClkoutFlashClk, /* Flash clock */
kSimClkoutLpoClk, /* LPO clock */
kSimClkoutMcgIrcClk, /* MCG out clock */
kSimClkoutRtc32kClk, /* RTC 32k clock */
kSimClkoutOscErClk,
KsimClkoutIrcClk
} sim_clkout_clock_sel_t;
/*! @brief SIM RTCCLKOUTSEL clock source select */
typedef enum _sim_rtcclkout_clock_sel
{
kSimRtcClkout1hzClk, /* 1Hz clock */
kSimRtcClkout32kClk /* 32KHz clock */
} sim_rtcclkout_clock_sel_t;
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*! @name IP related clock feature APIs*/
/*@{*/
/*!
* @brief Enable the clock for DMA module.
*
* This function enables the clock for DMA moudle.
* @param instance module device instance
*/
void SIM_HAL_EnableDmaClock(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Disable the clock for DMA module.
*
* This function disables the clock for DMA moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
*/
void SIM_HAL_DisableDmaClock(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Get the the clock gate state for DMA module.
*
* This function will get the clock gate state for DMA moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
* @return state true - ungated(Enabled), false - gated (Disabled)
*/
bool SIM_HAL_GetDmaGateCmd(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Enable the clock for DMAMUX module.
*
* This function enables the clock for DMAMUX moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
*/
void SIM_HAL_EnableDmamuxClock(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Disable the clock for DMAMUX module.
*
* This function disables the clock for DMAMUX moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
*/
void SIM_HAL_DisableDmamuxClock(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Get the the clock gate state for DMAMUX module.
*
* This function will get the clock gate state for DMAMUX moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
* @return state true - ungated(Enabled), false - gated (Disabled)
*/
bool SIM_HAL_GetDmamuxGateCmd(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Enable the clock for PORT module.
*
* This function enables the clock for PORT moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
*/
void SIM_HAL_EnablePortClock(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Disable the clock for PORT module.
*
* This function disables the clock for PORT moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
*/
void SIM_HAL_DisablePortClock(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Get the the clock gate state for PORT module.
*
* This function will get the clock gate state for PORT moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
* @return state true - ungated(Enabled), false - gated (Disabled)
*/
bool SIM_HAL_GetPortGateCmd(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Enable the clock for EWM module.
*
* This function enables the clock for EWM moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
*/
void SIM_HAL_EnableEwmClock(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Disable the clock for EWM module.
*
* This function disables the clock for EWM moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
*/
void SIM_HAL_DisableEwmClock(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Get the the clock gate state for EWM module.
*
* This function will get the clock gate state for EWM moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
* @return state true - ungated(Enabled), false - gated (Disabled)
*/
bool SIM_HAL_GetEwmGateCmd(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Enable the clock for FLEXBUS module.
*
* This function enables the clock for FLEXBUS moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
*/
void SIM_HAL_EnableFlexbusClock(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Disable the clock for FLEXBUS module.
*
* This function disables the clock for FLEXBUS moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
*/
void SIM_HAL_DisableFlexbusClock(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Get the the clock gate state for FLEXBUS module.
*
* This function will get the clock gate state for FLEXBUS moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
* @return state true - ungated(Enabled), false - gated (Disabled)
*/
bool SIM_HAL_GetFlexbusGateCmd(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Enable the clock for FTF module.
*
* This function enables the clock for FTF moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
*/
void SIM_HAL_EnableFtfClock(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Disable the clock for FTF module.
*
* This function disables the clock for FTF moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
*/
void SIM_HAL_DisableFtfClock(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Get the the clock gate state for FTF module.
*
* This function will get the clock gate state for FTF moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
* @return state true - ungated(Enabled), false - gated (Disabled)
*/
bool SIM_HAL_GetFtfGateCmd(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Enable the clock for CRC module.
*
* This function enables the clock for CRC moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
*/
void SIM_HAL_EnableCrcClock(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Disable the clock for CRC module.
*
* This function disables the clock for CRC moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
*/
void SIM_HAL_DisableCrcClock(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Get the the clock gate state for CRC module.
*
* This function will get the clock gate state for CRC moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
* @return state true - ungated(Enabled), false - gated (Disabled)
*/
bool SIM_HAL_GetCrcGateCmd(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Enable the clock for RNGA module.
*
* This function enables the clock for RNGA moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
*/
void SIM_HAL_EnableRngaClock(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Disable the clock for RNGA module.
*
* This function disables the clock for RNGA moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
*/
void SIM_HAL_DisableRngaClock(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Get the the clock gate state for RNGA module.
*
* This function will get the clock gate state for RNGA moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
* @return state true - ungated(Enabled), false - gated (Disabled)
*/
bool SIM_HAL_GetRngaGateCmd(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Enable the clock for ADC module.
*
* This function enables the clock for ADC moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
*/
void SIM_HAL_EnableAdcClock(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Disable the clock for ADC module.
*
* This function disables the clock for ADC moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
*/
void SIM_HAL_DisableAdcClock(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Get the the clock gate state for ADC module.
*
* This function will get the clock gate state for ADC moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
* @return state true - ungated(Enabled), false - gated (Disabled)
*/
bool SIM_HAL_GetAdcGateCmd(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Enable the clock for CMP module.
*
* This function enables the clock for CMP moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
*/
void SIM_HAL_EnableCmpClock(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Disable the clock for CMP module.
*
* This function disables the clock for CMP moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
*/
void SIM_HAL_DisableCmpClock(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Get the the clock gate state for CMP module.
*
* This function will get the clock gate state for CMP moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
* @return state true - ungated(Enabled), false - gated (Disabled)
*/
bool SIM_HAL_GetCmpGateCmd(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Enable the clock for DAC module.
*
* This function enables the clock for DAC moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
*/
void SIM_HAL_EnableDacClock(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Disable the clock for DAC module.
*
* This function disables the clock for DAC moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
*/
void SIM_HAL_DisableDacClock(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Get the the clock gate state for DAC module.
*
* This function will get the clock gate state for DAC moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
* @return state true - ungated(Enabled), false - gated (Disabled)
*/
bool SIM_HAL_GetDacGateCmd(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Enable the clock for VREF module.
*
* This function enables the clock for VREF moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
*/
void SIM_HAL_EnableVrefClock(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Disable the clock for VREF module.
*
* This function disables the clock for VREF moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
*/
void SIM_HAL_DisableVrefClock(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Get the the clock gate state for VREF module.
*
* This function will get the clock gate state for VREF moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
* @return state true - ungated(Enabled), false - gated (Disabled)
*/
bool SIM_HAL_GetVrefGateCmd(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Enable the clock for SAI module.
*
* This function enables the clock for SAI moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
*/
void SIM_HAL_EnableSaiClock(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Disable the clock for SAI module.
*
* This function disables the clock for SAI moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
*/
void SIM_HAL_DisableSaiClock(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Get the the clock gate state for SAI module.
*
* This function will get the clock gate state for SAI moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
* @return state true - ungated(Enabled), false - gated (Disabled)
*/
bool SIM_HAL_GetSaiGateCmd(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Enable the clock for PDB module.
*
* This function enables the clock for PDB moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
*/
void SIM_HAL_EnablePdbClock(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Disable the clock for PDB module.
*
* This function disables the clock for PDB moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
*/
void SIM_HAL_DisablePdbClock(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Get the the clock gate state for PDB module.
*
* This function will get the clock gate state for PDB moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
* @return state true - ungated(Enabled), false - gated (Disabled)
*/
bool SIM_HAL_GetPdbGateCmd(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Enable the clock for FTM module.
*
* This function enables the clock for FTM moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
*/
void SIM_HAL_EnableFtmClock(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Disable the clock for FTM module.
*
* This function disables the clock for FTM moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
*/
void SIM_HAL_DisableFtmClock(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Get the the clock gate state for FTM module.
*
* This function will get the clock gate state for FTM moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
* @return state true - ungated(Enabled), false - gated (Disabled)
*/
bool SIM_HAL_GetFtmGateCmd(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Enable the clock for PIT module.
*
* This function enables the clock for PIT moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
*/
void SIM_HAL_EnablePitClock(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Disable the clock for PIT module.
*
* This function disables the clock for PIT moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
*/
void SIM_HAL_DisablePitClock(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Get the the clock gate state for PIT module.
*
* This function will get the clock gate state for PIT moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
* @return state true - ungated(Enabled), false - gated (Disabled)
*/
bool SIM_HAL_GetPitGateCmd(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Enable the clock for LPTIMER module.
*
* This function enables the clock for LPTIMER moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
*/
void SIM_HAL_EnableLptimerClock(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Disable the clock for LPTIMER module.
*
* This function disables the clock for LPTIMER moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
*/
void SIM_HAL_DisableLptimerClock(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Get the the clock gate state for LPTIMER module.
*
* This function will get the clock gate state for LPTIMER moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
* @return state true - ungated(Enabled), false - gated (Disabled)
*/
bool SIM_HAL_GetLptimerGateCmd(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Enable the clock for RTC module.
*
* This function enables the clock for RTC moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
*/
void SIM_HAL_EnableRtcClock(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Disable the clock for RTC module.
*
* This function disables the clock for RTC moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
*/
void SIM_HAL_DisableRtcClock(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Get the the clock gate state for RTC module.
*
* This function will get the clock gate state for RTC moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
* @return state true - ungated(Enabled), false - gated (Disabled)
*/
bool SIM_HAL_GetRtcGateCmd(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Enable the clock for USBFS module.
*
* This function enables the clock for USBFS moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
*/
void SIM_HAL_EnableUsbClock(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Disable the clock for USBFS module.
*
* This function disables the clock for USBFS moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
*/
void SIM_HAL_DisableUsbClock(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Get the the clock gate state for USB module.
*
* This function will get the clock gate state for USB moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
* @return state true - ungated(Enabled), false - gated (Disabled)
*/
bool SIM_HAL_GetUsbGateCmd(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Enable the clock for SPI module.
*
* This function enables the clock for SPI moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
*/
void SIM_HAL_EnableSpiClock(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Disable the clock for SPI module.
*
* This function disables the clock for SPI moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
*/
void SIM_HAL_DisableSpiClock(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Get the the clock gate state for SPI module.
*
* This function will get the clock gate state for SPI moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
* @return state true - ungated(Enabled), false - gated (Disabled)
*/
bool SIM_HAL_GetSpiGateCmd(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Enable the clock for I2C module.
*
* This function enables the clock for I2C moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
*/
void SIM_HAL_EnableI2cClock(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Disable the clock for I2C module.
*
* This function disables the clock for I2C moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
*/
void SIM_HAL_DisableI2cClock(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Get the the clock gate state for I2C module.
*
* This function will get the clock gate state for I2C moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
* @return state true - ungated(Enabled), false - gated (Disabled)
*/
bool SIM_HAL_GetI2cGateCmd(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Enable the clock for UART module.
*
* This function enables the clock for UART moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
*/
void SIM_HAL_EnableUartClock(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Disable the clock for UART module.
*
* This function disables the clock for UART moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
*/
void SIM_HAL_DisableUartClock(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Get the the clock gate state for UART module.
*
* This function will get the clock gate state for UART moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
* @return state true - ungated(Enabled), false - gated (Disabled)
*/
bool SIM_HAL_GetUartGateCmd(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Enable the clock for LPUART module.
*
* This function enables the clock for LPUART moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
*/
void SIM_HAL_EnableLpuartClock(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Disable the clock for LPUART module.
*
* This function disables the clock for LPUART moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
*/
void SIM_HAL_DisableLpuartClock(uint32_t baseAddr, uint32_t instance);
/*!
* @brief Get the the clock gate state for LPUART module.
*
* This function will get the clock gate state for LPUART moudle.
*
* @param baseAddr Base address for current SIM instance.
* @param instance module device instance
* @return state true - ungated(Enabled), false - gated (Disabled)
*/
bool SIM_HAL_GetLpuartGateCmd(uint32_t baseAddr, uint32_t instance);
/*@}*/
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*! @}*/
#endif /* __FSL_SIM_HAL_K22F51212_H__ */
/*******************************************************************************
* EOF
******************************************************************************/

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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
OSC32KCLK = 0,
} RTCName;
typedef enum {
UART_0 = 0,
UART_1 = 1,
UART_2 = 2,
} UARTName;
#define STDIO_UART_TX USBTX
#define STDIO_UART_RX USBRX
#define STDIO_UART UART_1
typedef enum {
I2C_0 = 0,
I2C_1 = 1,
} I2CName;
#define TPM_SHIFT 8
typedef enum {
PWM_00 = (0 << TPM_SHIFT) | (0), // FTM0 CH0
PWM_01 = (0 << TPM_SHIFT) | (1), // FTM0 CH1
PWM_02 = (0 << TPM_SHIFT) | (2), // FTM0 CH2
PWM_03 = (0 << TPM_SHIFT) | (3), // FTM0 CH3
PWM_04 = (0 << TPM_SHIFT) | (4), // FTM0 CH4
PWM_05 = (0 << TPM_SHIFT) | (5), // FTM0 CH5
PWM_06 = (0 << TPM_SHIFT) | (6), // FTM0 CH6
PWM_07 = (0 << TPM_SHIFT) | (7), // FTM0 CH7
PWM_10 = (1 << TPM_SHIFT) | (0), // FTM1 CH0
PWM_11 = (1 << TPM_SHIFT) | (1), // FTM1 CH1
PWM_12 = (1 << TPM_SHIFT) | (2), // FTM1 CH2
PWM_13 = (1 << TPM_SHIFT) | (3), // FTM1 CH3
PWM_14 = (1 << TPM_SHIFT) | (4), // FTM1 CH4
PWM_15 = (1 << TPM_SHIFT) | (5), // FTM1 CH5
PWM_16 = (1 << TPM_SHIFT) | (6), // FTM1 CH6
PWM_17 = (1 << TPM_SHIFT) | (7), // FTM1 CH7
PWM_20 = (2 << TPM_SHIFT) | (0), // FTM2 CH0
PWM_21 = (2 << TPM_SHIFT) | (1), // FTM2 CH1
PWM_22 = (2 << TPM_SHIFT) | (2), // FTM2 CH2
PWM_23 = (2 << TPM_SHIFT) | (3), // FTM2 CH3
PWM_24 = (2 << TPM_SHIFT) | (4), // FTM2 CH4
PWM_25 = (2 << TPM_SHIFT) | (5), // FTM2 CH5
PWM_26 = (2 << TPM_SHIFT) | (6), // FTM2 CH6
PWM_27 = (2 << TPM_SHIFT) | (7), // FTM2 CH7
PWM_30 = (3 << TPM_SHIFT) | (0), // FTM3 CH0
PWM_31 = (3 << TPM_SHIFT) | (1), // FTM3 CH1
PWM_32 = (3 << TPM_SHIFT) | (2), // FTM3 CH2
PWM_33 = (3 << TPM_SHIFT) | (3), // FTM3 CH3
PWM_34 = (3 << TPM_SHIFT) | (4), // FTM3 CH4
PWM_35 = (3 << TPM_SHIFT) | (5), // FTM3 CH5
PWM_36 = (3 << TPM_SHIFT) | (6), // FTM3 CH6
PWM_37 = (3 << TPM_SHIFT) | (7), // FTM3 CH7
} PWMName;
#define ADC_INSTANCE_SHIFT 8
#define ADC_B_CHANNEL_SHIFT 5
typedef enum {
ADC0_SE4b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 4,
ADC0_SE5b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 5,
ADC0_SE6b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 6,
ADC0_SE7b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 7,
ADC0_SE8 = (0 << ADC_INSTANCE_SHIFT) | 8,
ADC0_SE9 = (0 << ADC_INSTANCE_SHIFT) | 9,
ADC0_SE12 = (0 << ADC_INSTANCE_SHIFT) | 12,
ADC0_SE13 = (0 << ADC_INSTANCE_SHIFT) | 13,
ADC0_SE14 = (0 << ADC_INSTANCE_SHIFT) | 14,
ADC0_SE15 = (0 << ADC_INSTANCE_SHIFT) | 15,
ADC0_SE16 = (0 << ADC_INSTANCE_SHIFT) | 16,
ADC0_SE17 = (0 << ADC_INSTANCE_SHIFT) | 17,
ADC0_SE18 = (0 << ADC_INSTANCE_SHIFT) | 18,
ADC1_SE4b = (1 << ADC_INSTANCE_SHIFT) | 4,
ADC1_SE5b = (1 << ADC_INSTANCE_SHIFT) | 5,
ADC1_SE6b = (1 << ADC_INSTANCE_SHIFT) | 6,
ADC1_SE7b = (1 << ADC_INSTANCE_SHIFT) | 7,
ADC1_SE8 = (1 << ADC_INSTANCE_SHIFT) | 8,
ADC1_SE9 = (1 << ADC_INSTANCE_SHIFT) | 9,
ADC1_SE12 = (1 << ADC_INSTANCE_SHIFT) | 12,
ADC1_SE13 = (1 << ADC_INSTANCE_SHIFT) | 13,
ADC1_SE14 = (1 << ADC_INSTANCE_SHIFT) | 14,
ADC1_SE15 = (1 << ADC_INSTANCE_SHIFT) | 15,
ADC1_SE16 = (1 << ADC_INSTANCE_SHIFT) | 16,
ADC1_SE17 = (1 << ADC_INSTANCE_SHIFT) | 17,
ADC1_SE18 = (1 << ADC_INSTANCE_SHIFT) | 18,
} ADCName;
typedef enum {
DAC_0 = 0
} DACName;
typedef enum {
SPI_0 = 0,
SPI_1 = 1,
} SPIName;
#ifdef __cplusplus
}
#endif
#endif

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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "PeripheralPins.h"
/************RTC***************/
const PinMap PinMap_RTC[] = {
{NC, OSC32KCLK, 0},
};
/************ADC***************/
const PinMap PinMap_ADC[] = {
{PTC2, ADC0_SE4b, 0},
{PTC8, ADC1_SE4b, 0},
{PTC9, ADC1_SE5b, 0},
{PTD1, ADC0_SE5b, 0},
{PTC10, ADC1_SE6b, 0},
{PTD5, ADC0_SE6b, 0},
{PTC11, ADC1_SE7b, 0},
{PTD6, ADC0_SE7b, 0},
{PTB0 , ADC0_SE8 , 0},
{PTB1 , ADC0_SE9 , 0},
{PTB2 , ADC0_SE12, 0},
{PTB3 , ADC0_SE13, 0},
{PTC0 , ADC0_SE14, 0},
{PTB10, ADC1_SE14, 0},
{PTB11, ADC1_SE15, 0},
{PTC1 , ADC0_SE15, 0},
{PTA17, ADC1_SE17, 0},
//{PTE24, ADC0_SE17, 0}, //I2C pull up
//{PTE25, ADC0_SE18, 0}, //I2C pull up
{NC , NC , 0}
};
/************DAC***************/
const PinMap PinMap_DAC[] = {
{DAC0_OUT, DAC_0, 0},
{NC , NC , 0}
};
/************I2C***************/
const PinMap PinMap_I2C_SDA[] = {
{PTB1 , I2C_0 , 2},
{PTB3 , I2C_0 , 2},
{PTC11, I2C_1 , 2},
{PTD3 , I2C_0 , 7},
{PTD9 , I2C_0 , 2},
{PTE0 , I2C_1 , 6},
{PTE25, I2C_0 , 5},
{NC , NC , 0}
};
const PinMap PinMap_I2C_SCL[] = {
{PTB0 , I2C_0 , 2},
{PTB2 , I2C_0 , 2},
{PTC10, I2C_1 , 2},
{PTD2 , I2C_0 , 7},
{PTD8 , I2C_0 , 2},
{PTE1 , I2C_1 , 6},
{PTE24, I2C_0 , 5},
{NC , NC , 0}
};
/************UART***************/
const PinMap PinMap_UART_TX[] = {
{PTA2, UART_0, 2},
{PTE0, UART_1, 3},
{PTD3, UART_2, 3},
{NC , NC , 0}
};
const PinMap PinMap_UART_RX[] = {
{PTA1, UART_0, 2},
{PTE1, UART_1, 3},
{PTD2, UART_2, 3},
{NC , NC , 0}
};
/************SPI***************/
const PinMap PinMap_SPI_SCLK[] = {
{PTD1 , SPI_0, 2},
{PTE2 , SPI_1, 2},
{PTA15, SPI_0, 2},
{PTB11, SPI_1, 2},
{PTC5 , SPI_0, 2},
{PTD5 , SPI_1, 7},
{NC , NC , 0}
};
const PinMap PinMap_SPI_MOSI[] = {
{PTD2 , SPI_0, 2},
{PTE1 , SPI_1, 2},
{PTE3 , SPI_1, 7},
{PTA16, SPI_0, 2},
{PTB16, SPI_1, 2},
{PTC6 , SPI_0, 2},
{PTD6 , SPI_1, 7},
{NC , NC , 0}
};
const PinMap PinMap_SPI_MISO[] = {
{PTD3 , SPI_0, 2},
{PTE1 , SPI_1, 7},
{PTE3 , SPI_1, 2},
{PTA17, SPI_0, 2},
{PTB17, SPI_1, 2},
{PTC7 , SPI_0, 2},
{PTD7 , SPI_1, 7},
{NC , NC , 0}
};
const PinMap PinMap_SPI_SSEL[] = {
{PTD0 , SPI_0, 2},
{PTE4 , SPI_1, 2},
{PTA14, SPI_0, 2},
{PTB10, SPI_1, 2},
{PTC4 , SPI_0, 2},
{PTD4 , SPI_1, 7},
{NC , NC , 0}
};
/************PWM***************/
const PinMap PinMap_PWM[] = {
{PTA0 , PWM_05, 3},
{PTA1 , PWM_06, 3},
{PTA2 , PWM_07, 3},
{PTA3 , PWM_00, 3},
{PTA4 , PWM_01, 3},
{PTA5 , PWM_02, 3},
{PTA10, PWM_20, 3},
{PTA11, PWM_21, 3},
{PTA12, PWM_10, 3},
{PTA13, PWM_11, 3},
{PTB0 , PWM_10, 3},
{PTB1 , PWM_11, 3},
{PTB18, PWM_20, 3},
{PTB19, PWM_21, 3},
{PTC1 , PWM_00, 4},
{PTC2 , PWM_01, 4},
{PTC3 , PWM_02, 4},
{PTC4 , PWM_03, 4},
{PTC5 , PWM_02, 7},
{PTD0 , PWM_30, 4},
{PTD1 , PWM_31, 4},
{PTD2 , PWM_32, 4},
{PTD3 , PWM_33, 4},
{PTD4 , PWM_04, 4},
{PTD5 , PWM_05, 4},
{PTD6 , PWM_06, 4},
{PTD7 , PWM_07, 4},
{PTE5 , PWM_30, 6},
{PTE6 , PWM_31, 6},
{NC , NC , 0}
};

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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
#define GPIO_PORT_SHIFT 12
typedef enum {
PTA0 = (0 << GPIO_PORT_SHIFT | 0 ),
PTA1 = (0 << GPIO_PORT_SHIFT | 1 ),
PTA2 = (0 << GPIO_PORT_SHIFT | 2 ),
PTA3 = (0 << GPIO_PORT_SHIFT | 3 ),
PTA4 = (0 << GPIO_PORT_SHIFT | 4 ),
PTA5 = (0 << GPIO_PORT_SHIFT | 5 ),
PTA6 = (0 << GPIO_PORT_SHIFT | 6 ),
PTA7 = (0 << GPIO_PORT_SHIFT | 7 ),
PTA8 = (0 << GPIO_PORT_SHIFT | 8 ),
PTA9 = (0 << GPIO_PORT_SHIFT | 9 ),
PTA10 = (0 << GPIO_PORT_SHIFT | 10),
PTA11 = (0 << GPIO_PORT_SHIFT | 11),
PTA12 = (0 << GPIO_PORT_SHIFT | 12),
PTA13 = (0 << GPIO_PORT_SHIFT | 13),
PTA14 = (0 << GPIO_PORT_SHIFT | 14),
PTA15 = (0 << GPIO_PORT_SHIFT | 15),
PTA16 = (0 << GPIO_PORT_SHIFT | 16),
PTA17 = (0 << GPIO_PORT_SHIFT | 17),
PTA18 = (0 << GPIO_PORT_SHIFT | 18),
PTA19 = (0 << GPIO_PORT_SHIFT | 19),
PTA20 = (0 << GPIO_PORT_SHIFT | 20),
PTA21 = (0 << GPIO_PORT_SHIFT | 21),
PTA22 = (0 << GPIO_PORT_SHIFT | 22),
PTA23 = (0 << GPIO_PORT_SHIFT | 23),
PTA24 = (0 << GPIO_PORT_SHIFT | 24),
PTA25 = (0 << GPIO_PORT_SHIFT | 25),
PTA26 = (0 << GPIO_PORT_SHIFT | 26),
PTA27 = (0 << GPIO_PORT_SHIFT | 27),
PTA28 = (0 << GPIO_PORT_SHIFT | 28),
PTA29 = (0 << GPIO_PORT_SHIFT | 29),
PTA30 = (0 << GPIO_PORT_SHIFT | 30),
PTA31 = (0 << GPIO_PORT_SHIFT | 31),
PTB0 = (1 << GPIO_PORT_SHIFT | 0 ),
PTB1 = (1 << GPIO_PORT_SHIFT | 1 ),
PTB2 = (1 << GPIO_PORT_SHIFT | 2 ),
PTB3 = (1 << GPIO_PORT_SHIFT | 3 ),
PTB4 = (1 << GPIO_PORT_SHIFT | 4 ),
PTB5 = (1 << GPIO_PORT_SHIFT | 5 ),
PTB6 = (1 << GPIO_PORT_SHIFT | 6 ),
PTB7 = (1 << GPIO_PORT_SHIFT | 7 ),
PTB8 = (1 << GPIO_PORT_SHIFT | 8 ),
PTB9 = (1 << GPIO_PORT_SHIFT | 9 ),
PTB10 = (1 << GPIO_PORT_SHIFT | 10),
PTB11 = (1 << GPIO_PORT_SHIFT | 11),
PTB12 = (1 << GPIO_PORT_SHIFT | 12),
PTB13 = (1 << GPIO_PORT_SHIFT | 13),
PTB14 = (1 << GPIO_PORT_SHIFT | 14),
PTB15 = (1 << GPIO_PORT_SHIFT | 15),
PTB16 = (1 << GPIO_PORT_SHIFT | 16),
PTB17 = (1 << GPIO_PORT_SHIFT | 17),
PTB18 = (1 << GPIO_PORT_SHIFT | 18),
PTB19 = (1 << GPIO_PORT_SHIFT | 19),
PTB20 = (1 << GPIO_PORT_SHIFT | 20),
PTB21 = (1 << GPIO_PORT_SHIFT | 21),
PTB22 = (1 << GPIO_PORT_SHIFT | 22),
PTB23 = (1 << GPIO_PORT_SHIFT | 23),
PTB24 = (1 << GPIO_PORT_SHIFT | 24),
PTB25 = (1 << GPIO_PORT_SHIFT | 25),
PTB26 = (1 << GPIO_PORT_SHIFT | 26),
PTB27 = (1 << GPIO_PORT_SHIFT | 27),
PTB28 = (1 << GPIO_PORT_SHIFT | 28),
PTB29 = (1 << GPIO_PORT_SHIFT | 29),
PTB30 = (1 << GPIO_PORT_SHIFT | 30),
PTB31 = (1 << GPIO_PORT_SHIFT | 31),
PTC0 = (2 << GPIO_PORT_SHIFT | 0 ),
PTC1 = (2 << GPIO_PORT_SHIFT | 1 ),
PTC2 = (2 << GPIO_PORT_SHIFT | 2 ),
PTC3 = (2 << GPIO_PORT_SHIFT | 3 ),
PTC4 = (2 << GPIO_PORT_SHIFT | 4 ),
PTC5 = (2 << GPIO_PORT_SHIFT | 5 ),
PTC6 = (2 << GPIO_PORT_SHIFT | 6 ),
PTC7 = (2 << GPIO_PORT_SHIFT | 7 ),
PTC8 = (2 << GPIO_PORT_SHIFT | 8 ),
PTC9 = (2 << GPIO_PORT_SHIFT | 9 ),
PTC10 = (2 << GPIO_PORT_SHIFT | 10),
PTC11 = (2 << GPIO_PORT_SHIFT | 11),
PTC12 = (2 << GPIO_PORT_SHIFT | 12),
PTC13 = (2 << GPIO_PORT_SHIFT | 13),
PTC14 = (2 << GPIO_PORT_SHIFT | 14),
PTC15 = (2 << GPIO_PORT_SHIFT | 15),
PTC16 = (2 << GPIO_PORT_SHIFT | 16),
PTC17 = (2 << GPIO_PORT_SHIFT | 17),
PTC18 = (2 << GPIO_PORT_SHIFT | 18),
PTC19 = (2 << GPIO_PORT_SHIFT | 19),
PTC20 = (2 << GPIO_PORT_SHIFT | 20),
PTC21 = (2 << GPIO_PORT_SHIFT | 21),
PTC22 = (2 << GPIO_PORT_SHIFT | 22),
PTC23 = (2 << GPIO_PORT_SHIFT | 23),
PTC24 = (2 << GPIO_PORT_SHIFT | 24),
PTC25 = (2 << GPIO_PORT_SHIFT | 25),
PTC26 = (2 << GPIO_PORT_SHIFT | 26),
PTC27 = (2 << GPIO_PORT_SHIFT | 27),
PTC28 = (2 << GPIO_PORT_SHIFT | 28),
PTC29 = (2 << GPIO_PORT_SHIFT | 29),
PTC30 = (2 << GPIO_PORT_SHIFT | 30),
PTC31 = (2 << GPIO_PORT_SHIFT | 31),
PTD0 = (3 << GPIO_PORT_SHIFT | 0 ),
PTD1 = (3 << GPIO_PORT_SHIFT | 1 ),
PTD2 = (3 << GPIO_PORT_SHIFT | 2 ),
PTD3 = (3 << GPIO_PORT_SHIFT | 3 ),
PTD4 = (3 << GPIO_PORT_SHIFT | 4 ),
PTD5 = (3 << GPIO_PORT_SHIFT | 5 ),
PTD6 = (3 << GPIO_PORT_SHIFT | 6 ),
PTD7 = (3 << GPIO_PORT_SHIFT | 7 ),
PTD8 = (3 << GPIO_PORT_SHIFT | 8 ),
PTD9 = (3 << GPIO_PORT_SHIFT | 9 ),
PTD10 = (3 << GPIO_PORT_SHIFT | 10),
PTD11 = (3 << GPIO_PORT_SHIFT | 11),
PTD12 = (3 << GPIO_PORT_SHIFT | 12),
PTD13 = (3 << GPIO_PORT_SHIFT | 13),
PTD14 = (3 << GPIO_PORT_SHIFT | 14),
PTD15 = (3 << GPIO_PORT_SHIFT | 15),
PTD16 = (3 << GPIO_PORT_SHIFT | 16),
PTD17 = (3 << GPIO_PORT_SHIFT | 17),
PTD18 = (3 << GPIO_PORT_SHIFT | 18),
PTD19 = (3 << GPIO_PORT_SHIFT | 19),
PTD20 = (3 << GPIO_PORT_SHIFT | 20),
PTD21 = (3 << GPIO_PORT_SHIFT | 21),
PTD22 = (3 << GPIO_PORT_SHIFT | 22),
PTD23 = (3 << GPIO_PORT_SHIFT | 23),
PTD24 = (3 << GPIO_PORT_SHIFT | 24),
PTD25 = (3 << GPIO_PORT_SHIFT | 25),
PTD26 = (3 << GPIO_PORT_SHIFT | 26),
PTD27 = (3 << GPIO_PORT_SHIFT | 27),
PTD28 = (3 << GPIO_PORT_SHIFT | 28),
PTD29 = (3 << GPIO_PORT_SHIFT | 29),
PTD30 = (3 << GPIO_PORT_SHIFT | 30),
PTD31 = (3 << GPIO_PORT_SHIFT | 31),
PTE0 = (4 << GPIO_PORT_SHIFT | 0 ),
PTE1 = (4 << GPIO_PORT_SHIFT | 1 ),
PTE2 = (4 << GPIO_PORT_SHIFT | 2 ),
PTE3 = (4 << GPIO_PORT_SHIFT | 3 ),
PTE4 = (4 << GPIO_PORT_SHIFT | 4 ),
PTE5 = (4 << GPIO_PORT_SHIFT | 5 ),
PTE6 = (4 << GPIO_PORT_SHIFT | 6 ),
PTE7 = (4 << GPIO_PORT_SHIFT | 7 ),
PTE8 = (4 << GPIO_PORT_SHIFT | 8 ),
PTE9 = (4 << GPIO_PORT_SHIFT | 9 ),
PTE10 = (4 << GPIO_PORT_SHIFT | 10),
PTE11 = (4 << GPIO_PORT_SHIFT | 11),
PTE12 = (4 << GPIO_PORT_SHIFT | 12),
PTE13 = (4 << GPIO_PORT_SHIFT | 13),
PTE14 = (4 << GPIO_PORT_SHIFT | 14),
PTE15 = (4 << GPIO_PORT_SHIFT | 15),
PTE16 = (4 << GPIO_PORT_SHIFT | 16),
PTE17 = (4 << GPIO_PORT_SHIFT | 17),
PTE18 = (4 << GPIO_PORT_SHIFT | 18),
PTE19 = (4 << GPIO_PORT_SHIFT | 19),
PTE20 = (4 << GPIO_PORT_SHIFT | 20),
PTE21 = (4 << GPIO_PORT_SHIFT | 21),
PTE22 = (4 << GPIO_PORT_SHIFT | 22),
PTE23 = (4 << GPIO_PORT_SHIFT | 23),
PTE24 = (4 << GPIO_PORT_SHIFT | 24),
PTE25 = (4 << GPIO_PORT_SHIFT | 25),
PTE26 = (4 << GPIO_PORT_SHIFT | 26),
PTE27 = (4 << GPIO_PORT_SHIFT | 27),
PTE28 = (4 << GPIO_PORT_SHIFT | 28),
PTE29 = (4 << GPIO_PORT_SHIFT | 29),
PTE30 = (4 << GPIO_PORT_SHIFT | 30),
PTE31 = (4 << GPIO_PORT_SHIFT | 31),
LED_RED = PTA1,
LED_GREEN = PTA2,
LED_BLUE = PTD5,
// mbed original LED naming
LED1 = LED_RED,
LED2 = LED_GREEN,
LED3 = LED_BLUE,
LED4 = LED_RED,
//Push buttons
SW2 = PTC1,
SW3 = PTB17,
// USB Pins
USBTX = PTE0,
USBRX = PTE1,
// Arduino Headers
D0 = PTD2,
D1 = PTD3,
D2 = PTB16,
D3 = PTA2,
D4 = PTA4,
D5 = PTB18,
D6 = PTC3,
D7 = PTC6,
D8 = PTB19,
D9 = PTA1,
D10 = PTD4,
D11 = PTD6,
D12 = PTD7,
D13 = PTD5,
D14 = PTE0,
D15 = PTE1,
I2C_SCL = D15,
I2C_SDA = D14,
A0 = PTB0,
A1 = PTB1,
A2 = PTC1,
A3 = PTC2,
A4 = PTB3,
A5 = PTB2,
DAC0_OUT = 0xFEFE, /* DAC does not have Pin Name in RM */
// Not connected
NC = (int)0xFFFFFFFF
} PinName;
typedef enum {
PullNone = 0,
PullDown = 1,
PullUp = 2,
PullDefault = PullUp
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#define DEVICE_PORTIN 1
#define DEVICE_PORTOUT 1
#define DEVICE_PORTINOUT 1
#define DEVICE_INTERRUPTIN 1
#define DEVICE_ANALOGIN 1
#define DEVICE_ANALOGOUT 1
#define DEVICE_SERIAL 1
#define DEVICE_I2C 1
#define DEVICE_I2CSLAVE 1
#define DEVICE_SPI 1
#define DEVICE_SPISLAVE 1
#define DEVICE_CAN 0
#define DEVICE_RTC 1
#define DEVICE_ETHERNET 0
#define DEVICE_PWMOUT 1
#define DEVICE_SEMIHOST 0
#define DEVICE_LOCALFILESYSTEM 0
#define DEVICE_ID_LENGTH 24
#define DEVICE_SLEEP 1
#define DEVICE_DEBUG_AWARENESS 0
#define DEVICE_STDIO_MESSAGES 1
#define DEVICE_ERROR_RED 1
#include "objects.h"
#endif

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/*
** ###################################################################
** Compilers: Keil ARM C/C++ Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
** Version: rev. 2.5, 2014-05-06
** Build: b140604
**
** Abstract:
** Extension to the CMSIS register access layer header.
**
** Copyright (c) 2014 Freescale Semiconductor, Inc.
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** Revisions:
** - rev. 1.0 (2013-07-23)
** Initial version.
** - rev. 1.1 (2013-09-17)
** RM rev. 0.4 update.
** - rev. 2.0 (2013-10-29)
** Register accessor macros added to the memory map.
** Symbols for Processor Expert memory map compatibility added to the memory map.
** Startup file for gcc has been updated according to CMSIS 3.2.
** System initialization updated.
** - rev. 2.1 (2013-10-30)
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
** - rev. 2.2 (2013-12-20)
** Update according to reference manual rev. 0.6,
** - rev. 2.3 (2014-01-13)
** Update according to reference manual rev. 0.61,
** - rev. 2.4 (2014-02-10)
** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
** - rev. 2.5 (2014-05-06)
** Update according to reference manual rev. 1.0,
** Update of system and startup files.
** Module access macro module_BASES replaced by module_BASE_PTRS.
**
** ###################################################################
*/
/*
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
*
* This file was generated automatically and any changes may be lost.
*/
#ifndef __HW_CMP_REGISTERS_H__
#define __HW_CMP_REGISTERS_H__
#include "MK22F51212.h"
#include "fsl_bitaccess.h"
/*
* MK22F51212 CMP
*
* High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX)
*
* Registers defined in this header file:
* - HW_CMP_CR0 - CMP Control Register 0
* - HW_CMP_CR1 - CMP Control Register 1
* - HW_CMP_FPR - CMP Filter Period Register
* - HW_CMP_SCR - CMP Status and Control Register
* - HW_CMP_DACCR - DAC Control Register
* - HW_CMP_MUXCR - MUX Control Register
*
* - hw_cmp_t - Struct containing all module registers.
*/
#define HW_CMP_INSTANCE_COUNT (2U) /*!< Number of instances of the CMP module. */
#define HW_CMP0 (0U) /*!< Instance number for CMP0. */
#define HW_CMP1 (1U) /*!< Instance number for CMP1. */
/*******************************************************************************
* HW_CMP_CR0 - CMP Control Register 0
******************************************************************************/
/*!
* @brief HW_CMP_CR0 - CMP Control Register 0 (RW)
*
* Reset value: 0x00U
*/
typedef union _hw_cmp_cr0
{
uint8_t U;
struct _hw_cmp_cr0_bitfields
{
uint8_t HYSTCTR : 2; /*!< [1:0] Comparator hard block hysteresis
* control */
uint8_t RESERVED0 : 2; /*!< [3:2] */
uint8_t FILTER_CNT : 3; /*!< [6:4] Filter Sample Count */
uint8_t RESERVED1 : 1; /*!< [7] */
} B;
} hw_cmp_cr0_t;
/*!
* @name Constants and macros for entire CMP_CR0 register
*/
/*@{*/
#define HW_CMP_CR0_ADDR(x) ((x) + 0x0U)
#define HW_CMP_CR0(x) (*(__IO hw_cmp_cr0_t *) HW_CMP_CR0_ADDR(x))
#define HW_CMP_CR0_RD(x) (HW_CMP_CR0(x).U)
#define HW_CMP_CR0_WR(x, v) (HW_CMP_CR0(x).U = (v))
#define HW_CMP_CR0_SET(x, v) (HW_CMP_CR0_WR(x, HW_CMP_CR0_RD(x) | (v)))
#define HW_CMP_CR0_CLR(x, v) (HW_CMP_CR0_WR(x, HW_CMP_CR0_RD(x) & ~(v)))
#define HW_CMP_CR0_TOG(x, v) (HW_CMP_CR0_WR(x, HW_CMP_CR0_RD(x) ^ (v)))
/*@}*/
/*
* Constants & macros for individual CMP_CR0 bitfields
*/
/*!
* @name Register CMP_CR0, field HYSTCTR[1:0] (RW)
*
* Defines the programmable hysteresis level. The hysteresis values associated
* with each level are device-specific. See the Data Sheet of the device for the
* exact values.
*
* Values:
* - 00 - Level 0
* - 01 - Level 1
* - 10 - Level 2
* - 11 - Level 3
*/
/*@{*/
#define BP_CMP_CR0_HYSTCTR (0U) /*!< Bit position for CMP_CR0_HYSTCTR. */
#define BM_CMP_CR0_HYSTCTR (0x03U) /*!< Bit mask for CMP_CR0_HYSTCTR. */
#define BS_CMP_CR0_HYSTCTR (2U) /*!< Bit field size in bits for CMP_CR0_HYSTCTR. */
/*! @brief Read current value of the CMP_CR0_HYSTCTR field. */
#define BR_CMP_CR0_HYSTCTR(x) (HW_CMP_CR0(x).B.HYSTCTR)
/*! @brief Format value for bitfield CMP_CR0_HYSTCTR. */
#define BF_CMP_CR0_HYSTCTR(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR0_HYSTCTR) & BM_CMP_CR0_HYSTCTR)
/*! @brief Set the HYSTCTR field to a new value. */
#define BW_CMP_CR0_HYSTCTR(x, v) (HW_CMP_CR0_WR(x, (HW_CMP_CR0_RD(x) & ~BM_CMP_CR0_HYSTCTR) | BF_CMP_CR0_HYSTCTR(v)))
/*@}*/
/*!
* @name Register CMP_CR0, field FILTER_CNT[6:4] (RW)
*
* Represents the number of consecutive samples that must agree prior to the
* comparator ouput filter accepting a new output state. For information regarding
* filter programming and latency, see the Functional descriptionThe CMP module
* can be used to compare two analog input voltages applied to INP and INM. .
*
* Values:
* - 000 - Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a
* legal state, and is not recommended. If SE = 0, COUT = COUTA.
* - 001 - One sample must agree. The comparator output is simply sampled.
* - 010 - 2 consecutive samples must agree.
* - 011 - 3 consecutive samples must agree.
* - 100 - 4 consecutive samples must agree.
* - 101 - 5 consecutive samples must agree.
* - 110 - 6 consecutive samples must agree.
* - 111 - 7 consecutive samples must agree.
*/
/*@{*/
#define BP_CMP_CR0_FILTER_CNT (4U) /*!< Bit position for CMP_CR0_FILTER_CNT. */
#define BM_CMP_CR0_FILTER_CNT (0x70U) /*!< Bit mask for CMP_CR0_FILTER_CNT. */
#define BS_CMP_CR0_FILTER_CNT (3U) /*!< Bit field size in bits for CMP_CR0_FILTER_CNT. */
/*! @brief Read current value of the CMP_CR0_FILTER_CNT field. */
#define BR_CMP_CR0_FILTER_CNT(x) (HW_CMP_CR0(x).B.FILTER_CNT)
/*! @brief Format value for bitfield CMP_CR0_FILTER_CNT. */
#define BF_CMP_CR0_FILTER_CNT(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR0_FILTER_CNT) & BM_CMP_CR0_FILTER_CNT)
/*! @brief Set the FILTER_CNT field to a new value. */
#define BW_CMP_CR0_FILTER_CNT(x, v) (HW_CMP_CR0_WR(x, (HW_CMP_CR0_RD(x) & ~BM_CMP_CR0_FILTER_CNT) | BF_CMP_CR0_FILTER_CNT(v)))
/*@}*/
/*******************************************************************************
* HW_CMP_CR1 - CMP Control Register 1
******************************************************************************/
/*!
* @brief HW_CMP_CR1 - CMP Control Register 1 (RW)
*
* Reset value: 0x00U
*/
typedef union _hw_cmp_cr1
{
uint8_t U;
struct _hw_cmp_cr1_bitfields
{
uint8_t EN : 1; /*!< [0] Comparator Module Enable */
uint8_t OPE : 1; /*!< [1] Comparator Output Pin Enable */
uint8_t COS : 1; /*!< [2] Comparator Output Select */
uint8_t INV : 1; /*!< [3] Comparator INVERT */
uint8_t PMODE : 1; /*!< [4] Power Mode Select */
uint8_t TRIGM : 1; /*!< [5] Trigger Mode Enable */
uint8_t WE : 1; /*!< [6] Windowing Enable */
uint8_t SE : 1; /*!< [7] Sample Enable */
} B;
} hw_cmp_cr1_t;
/*!
* @name Constants and macros for entire CMP_CR1 register
*/
/*@{*/
#define HW_CMP_CR1_ADDR(x) ((x) + 0x1U)
#define HW_CMP_CR1(x) (*(__IO hw_cmp_cr1_t *) HW_CMP_CR1_ADDR(x))
#define HW_CMP_CR1_RD(x) (HW_CMP_CR1(x).U)
#define HW_CMP_CR1_WR(x, v) (HW_CMP_CR1(x).U = (v))
#define HW_CMP_CR1_SET(x, v) (HW_CMP_CR1_WR(x, HW_CMP_CR1_RD(x) | (v)))
#define HW_CMP_CR1_CLR(x, v) (HW_CMP_CR1_WR(x, HW_CMP_CR1_RD(x) & ~(v)))
#define HW_CMP_CR1_TOG(x, v) (HW_CMP_CR1_WR(x, HW_CMP_CR1_RD(x) ^ (v)))
/*@}*/
/*
* Constants & macros for individual CMP_CR1 bitfields
*/
/*!
* @name Register CMP_CR1, field EN[0] (RW)
*
* Enables the Analog Comparator module. When the module is not enabled, it
* remains in the off state, and consumes no power. When the user selects the same
* input from analog mux to the positive and negative port, the comparator is
* disabled automatically.
*
* Values:
* - 0 - Analog Comparator is disabled.
* - 1 - Analog Comparator is enabled.
*/
/*@{*/
#define BP_CMP_CR1_EN (0U) /*!< Bit position for CMP_CR1_EN. */
#define BM_CMP_CR1_EN (0x01U) /*!< Bit mask for CMP_CR1_EN. */
#define BS_CMP_CR1_EN (1U) /*!< Bit field size in bits for CMP_CR1_EN. */
/*! @brief Read current value of the CMP_CR1_EN field. */
#define BR_CMP_CR1_EN(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_EN))
/*! @brief Format value for bitfield CMP_CR1_EN. */
#define BF_CMP_CR1_EN(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_EN) & BM_CMP_CR1_EN)
/*! @brief Set the EN field to a new value. */
#define BW_CMP_CR1_EN(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_EN) = (v))
/*@}*/
/*!
* @name Register CMP_CR1, field OPE[1] (RW)
*
* Values:
* - 0 - CMPO is not available on the associated CMPO output pin. If the
* comparator does not own the pin, this field has no effect.
* - 1 - CMPO is available on the associated CMPO output pin. The comparator
* output (CMPO) is driven out on the associated CMPO output pin if the
* comparator owns the pin. If the comparator does not own the field, this bit has no
* effect.
*/
/*@{*/
#define BP_CMP_CR1_OPE (1U) /*!< Bit position for CMP_CR1_OPE. */
#define BM_CMP_CR1_OPE (0x02U) /*!< Bit mask for CMP_CR1_OPE. */
#define BS_CMP_CR1_OPE (1U) /*!< Bit field size in bits for CMP_CR1_OPE. */
/*! @brief Read current value of the CMP_CR1_OPE field. */
#define BR_CMP_CR1_OPE(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_OPE))
/*! @brief Format value for bitfield CMP_CR1_OPE. */
#define BF_CMP_CR1_OPE(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_OPE) & BM_CMP_CR1_OPE)
/*! @brief Set the OPE field to a new value. */
#define BW_CMP_CR1_OPE(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_OPE) = (v))
/*@}*/
/*!
* @name Register CMP_CR1, field COS[2] (RW)
*
* Values:
* - 0 - Set the filtered comparator output (CMPO) to equal COUT.
* - 1 - Set the unfiltered comparator output (CMPO) to equal COUTA.
*/
/*@{*/
#define BP_CMP_CR1_COS (2U) /*!< Bit position for CMP_CR1_COS. */
#define BM_CMP_CR1_COS (0x04U) /*!< Bit mask for CMP_CR1_COS. */
#define BS_CMP_CR1_COS (1U) /*!< Bit field size in bits for CMP_CR1_COS. */
/*! @brief Read current value of the CMP_CR1_COS field. */
#define BR_CMP_CR1_COS(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_COS))
/*! @brief Format value for bitfield CMP_CR1_COS. */
#define BF_CMP_CR1_COS(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_COS) & BM_CMP_CR1_COS)
/*! @brief Set the COS field to a new value. */
#define BW_CMP_CR1_COS(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_COS) = (v))
/*@}*/
/*!
* @name Register CMP_CR1, field INV[3] (RW)
*
* Allows selection of the polarity of the analog comparator function. It is
* also driven to the COUT output, on both the device pin and as SCR[COUT], when
* OPE=0.
*
* Values:
* - 0 - Does not invert the comparator output.
* - 1 - Inverts the comparator output.
*/
/*@{*/
#define BP_CMP_CR1_INV (3U) /*!< Bit position for CMP_CR1_INV. */
#define BM_CMP_CR1_INV (0x08U) /*!< Bit mask for CMP_CR1_INV. */
#define BS_CMP_CR1_INV (1U) /*!< Bit field size in bits for CMP_CR1_INV. */
/*! @brief Read current value of the CMP_CR1_INV field. */
#define BR_CMP_CR1_INV(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_INV))
/*! @brief Format value for bitfield CMP_CR1_INV. */
#define BF_CMP_CR1_INV(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_INV) & BM_CMP_CR1_INV)
/*! @brief Set the INV field to a new value. */
#define BW_CMP_CR1_INV(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_INV) = (v))
/*@}*/
/*!
* @name Register CMP_CR1, field PMODE[4] (RW)
*
* See the electrical specifications table in the device Data Sheet for details.
*
* Values:
* - 0 - Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower
* output propagation delay and lower current consumption.
* - 1 - High-Speed (HS) Comparison mode selected. In this mode, CMP has faster
* output propagation delay and higher current consumption.
*/
/*@{*/
#define BP_CMP_CR1_PMODE (4U) /*!< Bit position for CMP_CR1_PMODE. */
#define BM_CMP_CR1_PMODE (0x10U) /*!< Bit mask for CMP_CR1_PMODE. */
#define BS_CMP_CR1_PMODE (1U) /*!< Bit field size in bits for CMP_CR1_PMODE. */
/*! @brief Read current value of the CMP_CR1_PMODE field. */
#define BR_CMP_CR1_PMODE(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_PMODE))
/*! @brief Format value for bitfield CMP_CR1_PMODE. */
#define BF_CMP_CR1_PMODE(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_PMODE) & BM_CMP_CR1_PMODE)
/*! @brief Set the PMODE field to a new value. */
#define BW_CMP_CR1_PMODE(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_PMODE) = (v))
/*@}*/
/*!
* @name Register CMP_CR1, field TRIGM[5] (RW)
*
* CMP and DAC are configured to CMP Trigger mode when CMP_CR1[TRIGM] is set to
* 1. In addition, the CMP should be enabled. If the DAC is to be used as a
* reference to the CMP, it should also be enabled. CMP Trigger mode depends on an
* external timer resource to periodically enable the CMP and 6-bit DAC in order to
* generate a triggered compare. Upon setting TRIGM, the CMP and DAC are placed
* in a standby state until an external timer resource trigger is received. See
* the chip configuration for details about the external timer resource.
*
* Values:
* - 0 - Trigger mode is disabled.
* - 1 - Trigger mode is enabled.
*/
/*@{*/
#define BP_CMP_CR1_TRIGM (5U) /*!< Bit position for CMP_CR1_TRIGM. */
#define BM_CMP_CR1_TRIGM (0x20U) /*!< Bit mask for CMP_CR1_TRIGM. */
#define BS_CMP_CR1_TRIGM (1U) /*!< Bit field size in bits for CMP_CR1_TRIGM. */
/*! @brief Read current value of the CMP_CR1_TRIGM field. */
#define BR_CMP_CR1_TRIGM(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_TRIGM))
/*! @brief Format value for bitfield CMP_CR1_TRIGM. */
#define BF_CMP_CR1_TRIGM(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_TRIGM) & BM_CMP_CR1_TRIGM)
/*! @brief Set the TRIGM field to a new value. */
#define BW_CMP_CR1_TRIGM(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_TRIGM) = (v))
/*@}*/
/*!
* @name Register CMP_CR1, field WE[6] (RW)
*
* At any given time, either SE or WE can be set. If a write to this register
* attempts to set both, then SE is set and WE is cleared. However, avoid writing
* 1s to both field locations because this "11" case is reserved and may change in
* future implementations.
*
* Values:
* - 0 - Windowing mode is not selected.
* - 1 - Windowing mode is selected.
*/
/*@{*/
#define BP_CMP_CR1_WE (6U) /*!< Bit position for CMP_CR1_WE. */
#define BM_CMP_CR1_WE (0x40U) /*!< Bit mask for CMP_CR1_WE. */
#define BS_CMP_CR1_WE (1U) /*!< Bit field size in bits for CMP_CR1_WE. */
/*! @brief Read current value of the CMP_CR1_WE field. */
#define BR_CMP_CR1_WE(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_WE))
/*! @brief Format value for bitfield CMP_CR1_WE. */
#define BF_CMP_CR1_WE(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_WE) & BM_CMP_CR1_WE)
/*! @brief Set the WE field to a new value. */
#define BW_CMP_CR1_WE(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_WE) = (v))
/*@}*/
/*!
* @name Register CMP_CR1, field SE[7] (RW)
*
* At any given time, either SE or WE can be set. If a write to this register
* attempts to set both, then SE is set and WE is cleared. However, avoid writing
* 1s to both field locations because this "11" case is reserved and may change in
* future implementations.
*
* Values:
* - 0 - Sampling mode is not selected.
* - 1 - Sampling mode is selected.
*/
/*@{*/
#define BP_CMP_CR1_SE (7U) /*!< Bit position for CMP_CR1_SE. */
#define BM_CMP_CR1_SE (0x80U) /*!< Bit mask for CMP_CR1_SE. */
#define BS_CMP_CR1_SE (1U) /*!< Bit field size in bits for CMP_CR1_SE. */
/*! @brief Read current value of the CMP_CR1_SE field. */
#define BR_CMP_CR1_SE(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_SE))
/*! @brief Format value for bitfield CMP_CR1_SE. */
#define BF_CMP_CR1_SE(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_SE) & BM_CMP_CR1_SE)
/*! @brief Set the SE field to a new value. */
#define BW_CMP_CR1_SE(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_SE) = (v))
/*@}*/
/*******************************************************************************
* HW_CMP_FPR - CMP Filter Period Register
******************************************************************************/
/*!
* @brief HW_CMP_FPR - CMP Filter Period Register (RW)
*
* Reset value: 0x00U
*/
typedef union _hw_cmp_fpr
{
uint8_t U;
struct _hw_cmp_fpr_bitfields
{
uint8_t FILT_PER : 8; /*!< [7:0] Filter Sample Period */
} B;
} hw_cmp_fpr_t;
/*!
* @name Constants and macros for entire CMP_FPR register
*/
/*@{*/
#define HW_CMP_FPR_ADDR(x) ((x) + 0x2U)
#define HW_CMP_FPR(x) (*(__IO hw_cmp_fpr_t *) HW_CMP_FPR_ADDR(x))
#define HW_CMP_FPR_RD(x) (HW_CMP_FPR(x).U)
#define HW_CMP_FPR_WR(x, v) (HW_CMP_FPR(x).U = (v))
#define HW_CMP_FPR_SET(x, v) (HW_CMP_FPR_WR(x, HW_CMP_FPR_RD(x) | (v)))
#define HW_CMP_FPR_CLR(x, v) (HW_CMP_FPR_WR(x, HW_CMP_FPR_RD(x) & ~(v)))
#define HW_CMP_FPR_TOG(x, v) (HW_CMP_FPR_WR(x, HW_CMP_FPR_RD(x) ^ (v)))
/*@}*/
/*
* Constants & macros for individual CMP_FPR bitfields
*/
/*!
* @name Register CMP_FPR, field FILT_PER[7:0] (RW)
*
* Specifies the sampling period, in bus clock cycles, of the comparator output
* filter, when CR1[SE]=0. Setting FILT_PER to 0x0 disables the filter. Filter
* programming and latency details appear in the Functional descriptionThe CMP
* module can be used to compare two analog input voltages applied to INP and INM. .
* This field has no effect when CR1[SE]=1. In that case, the external SAMPLE
* signal is used to determine the sampling period.
*/
/*@{*/
#define BP_CMP_FPR_FILT_PER (0U) /*!< Bit position for CMP_FPR_FILT_PER. */
#define BM_CMP_FPR_FILT_PER (0xFFU) /*!< Bit mask for CMP_FPR_FILT_PER. */
#define BS_CMP_FPR_FILT_PER (8U) /*!< Bit field size in bits for CMP_FPR_FILT_PER. */
/*! @brief Read current value of the CMP_FPR_FILT_PER field. */
#define BR_CMP_FPR_FILT_PER(x) (HW_CMP_FPR(x).U)
/*! @brief Format value for bitfield CMP_FPR_FILT_PER. */
#define BF_CMP_FPR_FILT_PER(v) ((uint8_t)((uint8_t)(v) << BP_CMP_FPR_FILT_PER) & BM_CMP_FPR_FILT_PER)
/*! @brief Set the FILT_PER field to a new value. */
#define BW_CMP_FPR_FILT_PER(x, v) (HW_CMP_FPR_WR(x, v))
/*@}*/
/*******************************************************************************
* HW_CMP_SCR - CMP Status and Control Register
******************************************************************************/
/*!
* @brief HW_CMP_SCR - CMP Status and Control Register (RW)
*
* Reset value: 0x00U
*/
typedef union _hw_cmp_scr
{
uint8_t U;
struct _hw_cmp_scr_bitfields
{
uint8_t COUT : 1; /*!< [0] Analog Comparator Output */
uint8_t CFF : 1; /*!< [1] Analog Comparator Flag Falling */
uint8_t CFR : 1; /*!< [2] Analog Comparator Flag Rising */
uint8_t IEF : 1; /*!< [3] Comparator Interrupt Enable Falling */
uint8_t IER : 1; /*!< [4] Comparator Interrupt Enable Rising */
uint8_t RESERVED0 : 1; /*!< [5] */
uint8_t DMAEN : 1; /*!< [6] DMA Enable Control */
uint8_t RESERVED1 : 1; /*!< [7] */
} B;
} hw_cmp_scr_t;
/*!
* @name Constants and macros for entire CMP_SCR register
*/
/*@{*/
#define HW_CMP_SCR_ADDR(x) ((x) + 0x3U)
#define HW_CMP_SCR(x) (*(__IO hw_cmp_scr_t *) HW_CMP_SCR_ADDR(x))
#define HW_CMP_SCR_RD(x) (HW_CMP_SCR(x).U)
#define HW_CMP_SCR_WR(x, v) (HW_CMP_SCR(x).U = (v))
#define HW_CMP_SCR_SET(x, v) (HW_CMP_SCR_WR(x, HW_CMP_SCR_RD(x) | (v)))
#define HW_CMP_SCR_CLR(x, v) (HW_CMP_SCR_WR(x, HW_CMP_SCR_RD(x) & ~(v)))
#define HW_CMP_SCR_TOG(x, v) (HW_CMP_SCR_WR(x, HW_CMP_SCR_RD(x) ^ (v)))
/*@}*/
/*
* Constants & macros for individual CMP_SCR bitfields
*/
/*!
* @name Register CMP_SCR, field COUT[0] (RO)
*
* Returns the current value of the Analog Comparator output, when read. The
* field is reset to 0 and will read as CR1[INV] when the Analog Comparator module
* is disabled, that is, when CR1[EN] = 0. Writes to this field are ignored.
*/
/*@{*/
#define BP_CMP_SCR_COUT (0U) /*!< Bit position for CMP_SCR_COUT. */
#define BM_CMP_SCR_COUT (0x01U) /*!< Bit mask for CMP_SCR_COUT. */
#define BS_CMP_SCR_COUT (1U) /*!< Bit field size in bits for CMP_SCR_COUT. */
/*! @brief Read current value of the CMP_SCR_COUT field. */
#define BR_CMP_SCR_COUT(x) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_COUT))
/*@}*/
/*!
* @name Register CMP_SCR, field CFF[1] (W1C)
*
* Detects a falling-edge on COUT, when set, during normal operation. CFF is
* cleared by writing 1 to it. During Stop modes, CFF is level sensitive .
*
* Values:
* - 0 - Falling-edge on COUT has not been detected.
* - 1 - Falling-edge on COUT has occurred.
*/
/*@{*/
#define BP_CMP_SCR_CFF (1U) /*!< Bit position for CMP_SCR_CFF. */
#define BM_CMP_SCR_CFF (0x02U) /*!< Bit mask for CMP_SCR_CFF. */
#define BS_CMP_SCR_CFF (1U) /*!< Bit field size in bits for CMP_SCR_CFF. */
/*! @brief Read current value of the CMP_SCR_CFF field. */
#define BR_CMP_SCR_CFF(x) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_CFF))
/*! @brief Format value for bitfield CMP_SCR_CFF. */
#define BF_CMP_SCR_CFF(v) ((uint8_t)((uint8_t)(v) << BP_CMP_SCR_CFF) & BM_CMP_SCR_CFF)
/*! @brief Set the CFF field to a new value. */
#define BW_CMP_SCR_CFF(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_CFF) = (v))
/*@}*/
/*!
* @name Register CMP_SCR, field CFR[2] (W1C)
*
* Detects a rising-edge on COUT, when set, during normal operation. CFR is
* cleared by writing 1 to it. During Stop modes, CFR is level sensitive .
*
* Values:
* - 0 - Rising-edge on COUT has not been detected.
* - 1 - Rising-edge on COUT has occurred.
*/
/*@{*/
#define BP_CMP_SCR_CFR (2U) /*!< Bit position for CMP_SCR_CFR. */
#define BM_CMP_SCR_CFR (0x04U) /*!< Bit mask for CMP_SCR_CFR. */
#define BS_CMP_SCR_CFR (1U) /*!< Bit field size in bits for CMP_SCR_CFR. */
/*! @brief Read current value of the CMP_SCR_CFR field. */
#define BR_CMP_SCR_CFR(x) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_CFR))
/*! @brief Format value for bitfield CMP_SCR_CFR. */
#define BF_CMP_SCR_CFR(v) ((uint8_t)((uint8_t)(v) << BP_CMP_SCR_CFR) & BM_CMP_SCR_CFR)
/*! @brief Set the CFR field to a new value. */
#define BW_CMP_SCR_CFR(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_CFR) = (v))
/*@}*/
/*!
* @name Register CMP_SCR, field IEF[3] (RW)
*
* Enables the CFF interrupt from the CMP. When this field is set, an interrupt
* will be asserted when CFF is set.
*
* Values:
* - 0 - Interrupt is disabled.
* - 1 - Interrupt is enabled.
*/
/*@{*/
#define BP_CMP_SCR_IEF (3U) /*!< Bit position for CMP_SCR_IEF. */
#define BM_CMP_SCR_IEF (0x08U) /*!< Bit mask for CMP_SCR_IEF. */
#define BS_CMP_SCR_IEF (1U) /*!< Bit field size in bits for CMP_SCR_IEF. */
/*! @brief Read current value of the CMP_SCR_IEF field. */
#define BR_CMP_SCR_IEF(x) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_IEF))
/*! @brief Format value for bitfield CMP_SCR_IEF. */
#define BF_CMP_SCR_IEF(v) ((uint8_t)((uint8_t)(v) << BP_CMP_SCR_IEF) & BM_CMP_SCR_IEF)
/*! @brief Set the IEF field to a new value. */
#define BW_CMP_SCR_IEF(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_IEF) = (v))
/*@}*/
/*!
* @name Register CMP_SCR, field IER[4] (RW)
*
* Enables the CFR interrupt from the CMP. When this field is set, an interrupt
* will be asserted when CFR is set.
*
* Values:
* - 0 - Interrupt is disabled.
* - 1 - Interrupt is enabled.
*/
/*@{*/
#define BP_CMP_SCR_IER (4U) /*!< Bit position for CMP_SCR_IER. */
#define BM_CMP_SCR_IER (0x10U) /*!< Bit mask for CMP_SCR_IER. */
#define BS_CMP_SCR_IER (1U) /*!< Bit field size in bits for CMP_SCR_IER. */
/*! @brief Read current value of the CMP_SCR_IER field. */
#define BR_CMP_SCR_IER(x) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_IER))
/*! @brief Format value for bitfield CMP_SCR_IER. */
#define BF_CMP_SCR_IER(v) ((uint8_t)((uint8_t)(v) << BP_CMP_SCR_IER) & BM_CMP_SCR_IER)
/*! @brief Set the IER field to a new value. */
#define BW_CMP_SCR_IER(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_IER) = (v))
/*@}*/
/*!
* @name Register CMP_SCR, field DMAEN[6] (RW)
*
* Enables the DMA transfer triggered from the CMP module. When this field is
* set, a DMA request is asserted when CFR or CFF is set.
*
* Values:
* - 0 - DMA is disabled.
* - 1 - DMA is enabled.
*/
/*@{*/
#define BP_CMP_SCR_DMAEN (6U) /*!< Bit position for CMP_SCR_DMAEN. */
#define BM_CMP_SCR_DMAEN (0x40U) /*!< Bit mask for CMP_SCR_DMAEN. */
#define BS_CMP_SCR_DMAEN (1U) /*!< Bit field size in bits for CMP_SCR_DMAEN. */
/*! @brief Read current value of the CMP_SCR_DMAEN field. */
#define BR_CMP_SCR_DMAEN(x) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_DMAEN))
/*! @brief Format value for bitfield CMP_SCR_DMAEN. */
#define BF_CMP_SCR_DMAEN(v) ((uint8_t)((uint8_t)(v) << BP_CMP_SCR_DMAEN) & BM_CMP_SCR_DMAEN)
/*! @brief Set the DMAEN field to a new value. */
#define BW_CMP_SCR_DMAEN(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_DMAEN) = (v))
/*@}*/
/*******************************************************************************
* HW_CMP_DACCR - DAC Control Register
******************************************************************************/
/*!
* @brief HW_CMP_DACCR - DAC Control Register (RW)
*
* Reset value: 0x00U
*/
typedef union _hw_cmp_daccr
{
uint8_t U;
struct _hw_cmp_daccr_bitfields
{
uint8_t VOSEL : 6; /*!< [5:0] DAC Output Voltage Select */
uint8_t VRSEL : 1; /*!< [6] Supply Voltage Reference Source Select */
uint8_t DACEN : 1; /*!< [7] DAC Enable */
} B;
} hw_cmp_daccr_t;
/*!
* @name Constants and macros for entire CMP_DACCR register
*/
/*@{*/
#define HW_CMP_DACCR_ADDR(x) ((x) + 0x4U)
#define HW_CMP_DACCR(x) (*(__IO hw_cmp_daccr_t *) HW_CMP_DACCR_ADDR(x))
#define HW_CMP_DACCR_RD(x) (HW_CMP_DACCR(x).U)
#define HW_CMP_DACCR_WR(x, v) (HW_CMP_DACCR(x).U = (v))
#define HW_CMP_DACCR_SET(x, v) (HW_CMP_DACCR_WR(x, HW_CMP_DACCR_RD(x) | (v)))
#define HW_CMP_DACCR_CLR(x, v) (HW_CMP_DACCR_WR(x, HW_CMP_DACCR_RD(x) & ~(v)))
#define HW_CMP_DACCR_TOG(x, v) (HW_CMP_DACCR_WR(x, HW_CMP_DACCR_RD(x) ^ (v)))
/*@}*/
/*
* Constants & macros for individual CMP_DACCR bitfields
*/
/*!
* @name Register CMP_DACCR, field VOSEL[5:0] (RW)
*
* Selects an output voltage from one of 64 distinct levels. DACO = (V in /64) *
* (VOSEL[5:0] + 1) , so the DACO range is from V in /64 to V in .
*/
/*@{*/
#define BP_CMP_DACCR_VOSEL (0U) /*!< Bit position for CMP_DACCR_VOSEL. */
#define BM_CMP_DACCR_VOSEL (0x3FU) /*!< Bit mask for CMP_DACCR_VOSEL. */
#define BS_CMP_DACCR_VOSEL (6U) /*!< Bit field size in bits for CMP_DACCR_VOSEL. */
/*! @brief Read current value of the CMP_DACCR_VOSEL field. */
#define BR_CMP_DACCR_VOSEL(x) (HW_CMP_DACCR(x).B.VOSEL)
/*! @brief Format value for bitfield CMP_DACCR_VOSEL. */
#define BF_CMP_DACCR_VOSEL(v) ((uint8_t)((uint8_t)(v) << BP_CMP_DACCR_VOSEL) & BM_CMP_DACCR_VOSEL)
/*! @brief Set the VOSEL field to a new value. */
#define BW_CMP_DACCR_VOSEL(x, v) (HW_CMP_DACCR_WR(x, (HW_CMP_DACCR_RD(x) & ~BM_CMP_DACCR_VOSEL) | BF_CMP_DACCR_VOSEL(v)))
/*@}*/
/*!
* @name Register CMP_DACCR, field VRSEL[6] (RW)
*
* Values:
* - 0 - V is selected as resistor ladder network supply reference V. in1 in
* - 1 - V is selected as resistor ladder network supply reference V. in2 in
*/
/*@{*/
#define BP_CMP_DACCR_VRSEL (6U) /*!< Bit position for CMP_DACCR_VRSEL. */
#define BM_CMP_DACCR_VRSEL (0x40U) /*!< Bit mask for CMP_DACCR_VRSEL. */
#define BS_CMP_DACCR_VRSEL (1U) /*!< Bit field size in bits for CMP_DACCR_VRSEL. */
/*! @brief Read current value of the CMP_DACCR_VRSEL field. */
#define BR_CMP_DACCR_VRSEL(x) (BITBAND_ACCESS8(HW_CMP_DACCR_ADDR(x), BP_CMP_DACCR_VRSEL))
/*! @brief Format value for bitfield CMP_DACCR_VRSEL. */
#define BF_CMP_DACCR_VRSEL(v) ((uint8_t)((uint8_t)(v) << BP_CMP_DACCR_VRSEL) & BM_CMP_DACCR_VRSEL)
/*! @brief Set the VRSEL field to a new value. */
#define BW_CMP_DACCR_VRSEL(x, v) (BITBAND_ACCESS8(HW_CMP_DACCR_ADDR(x), BP_CMP_DACCR_VRSEL) = (v))
/*@}*/
/*!
* @name Register CMP_DACCR, field DACEN[7] (RW)
*
* Enables the DAC. When the DAC is disabled, it is powered down to conserve
* power.
*
* Values:
* - 0 - DAC is disabled.
* - 1 - DAC is enabled.
*/
/*@{*/
#define BP_CMP_DACCR_DACEN (7U) /*!< Bit position for CMP_DACCR_DACEN. */
#define BM_CMP_DACCR_DACEN (0x80U) /*!< Bit mask for CMP_DACCR_DACEN. */
#define BS_CMP_DACCR_DACEN (1U) /*!< Bit field size in bits for CMP_DACCR_DACEN. */
/*! @brief Read current value of the CMP_DACCR_DACEN field. */
#define BR_CMP_DACCR_DACEN(x) (BITBAND_ACCESS8(HW_CMP_DACCR_ADDR(x), BP_CMP_DACCR_DACEN))
/*! @brief Format value for bitfield CMP_DACCR_DACEN. */
#define BF_CMP_DACCR_DACEN(v) ((uint8_t)((uint8_t)(v) << BP_CMP_DACCR_DACEN) & BM_CMP_DACCR_DACEN)
/*! @brief Set the DACEN field to a new value. */
#define BW_CMP_DACCR_DACEN(x, v) (BITBAND_ACCESS8(HW_CMP_DACCR_ADDR(x), BP_CMP_DACCR_DACEN) = (v))
/*@}*/
/*******************************************************************************
* HW_CMP_MUXCR - MUX Control Register
******************************************************************************/
/*!
* @brief HW_CMP_MUXCR - MUX Control Register (RW)
*
* Reset value: 0x00U
*/
typedef union _hw_cmp_muxcr
{
uint8_t U;
struct _hw_cmp_muxcr_bitfields
{
uint8_t MSEL : 3; /*!< [2:0] Minus Input Mux Control */
uint8_t PSEL : 3; /*!< [5:3] Plus Input Mux Control */
uint8_t RESERVED0 : 2; /*!< [7:6] Bit can be programmed to zero only
* . */
} B;
} hw_cmp_muxcr_t;
/*!
* @name Constants and macros for entire CMP_MUXCR register
*/
/*@{*/
#define HW_CMP_MUXCR_ADDR(x) ((x) + 0x5U)
#define HW_CMP_MUXCR(x) (*(__IO hw_cmp_muxcr_t *) HW_CMP_MUXCR_ADDR(x))
#define HW_CMP_MUXCR_RD(x) (HW_CMP_MUXCR(x).U)
#define HW_CMP_MUXCR_WR(x, v) (HW_CMP_MUXCR(x).U = (v))
#define HW_CMP_MUXCR_SET(x, v) (HW_CMP_MUXCR_WR(x, HW_CMP_MUXCR_RD(x) | (v)))
#define HW_CMP_MUXCR_CLR(x, v) (HW_CMP_MUXCR_WR(x, HW_CMP_MUXCR_RD(x) & ~(v)))
#define HW_CMP_MUXCR_TOG(x, v) (HW_CMP_MUXCR_WR(x, HW_CMP_MUXCR_RD(x) ^ (v)))
/*@}*/
/*
* Constants & macros for individual CMP_MUXCR bitfields
*/
/*!
* @name Register CMP_MUXCR, field MSEL[2:0] (RW)
*
* Determines which input is selected for the minus input of the comparator. For
* INx inputs, see CMP, DAC, and ANMUX block diagrams. When an inappropriate
* operation selects the same input for both muxes, the comparator automatically
* shuts down to prevent itself from becoming a noise generator.
*
* Values:
* - 000 - IN0
* - 001 - IN1
* - 010 - IN2
* - 011 - IN3
* - 100 - IN4
* - 101 - IN5
* - 110 - IN6
* - 111 - IN7
*/
/*@{*/
#define BP_CMP_MUXCR_MSEL (0U) /*!< Bit position for CMP_MUXCR_MSEL. */
#define BM_CMP_MUXCR_MSEL (0x07U) /*!< Bit mask for CMP_MUXCR_MSEL. */
#define BS_CMP_MUXCR_MSEL (3U) /*!< Bit field size in bits for CMP_MUXCR_MSEL. */
/*! @brief Read current value of the CMP_MUXCR_MSEL field. */
#define BR_CMP_MUXCR_MSEL(x) (HW_CMP_MUXCR(x).B.MSEL)
/*! @brief Format value for bitfield CMP_MUXCR_MSEL. */
#define BF_CMP_MUXCR_MSEL(v) ((uint8_t)((uint8_t)(v) << BP_CMP_MUXCR_MSEL) & BM_CMP_MUXCR_MSEL)
/*! @brief Set the MSEL field to a new value. */
#define BW_CMP_MUXCR_MSEL(x, v) (HW_CMP_MUXCR_WR(x, (HW_CMP_MUXCR_RD(x) & ~BM_CMP_MUXCR_MSEL) | BF_CMP_MUXCR_MSEL(v)))
/*@}*/
/*!
* @name Register CMP_MUXCR, field PSEL[5:3] (RW)
*
* Determines which input is selected for the plus input of the comparator. For
* INx inputs, see CMP, DAC, and ANMUX block diagrams. When an inappropriate
* operation selects the same input for both muxes, the comparator automatically
* shuts down to prevent itself from becoming a noise generator.
*
* Values:
* - 000 - IN0
* - 001 - IN1
* - 010 - IN2
* - 011 - IN3
* - 100 - IN4
* - 101 - IN5
* - 110 - IN6
* - 111 - IN7
*/
/*@{*/
#define BP_CMP_MUXCR_PSEL (3U) /*!< Bit position for CMP_MUXCR_PSEL. */
#define BM_CMP_MUXCR_PSEL (0x38U) /*!< Bit mask for CMP_MUXCR_PSEL. */
#define BS_CMP_MUXCR_PSEL (3U) /*!< Bit field size in bits for CMP_MUXCR_PSEL. */
/*! @brief Read current value of the CMP_MUXCR_PSEL field. */
#define BR_CMP_MUXCR_PSEL(x) (HW_CMP_MUXCR(x).B.PSEL)
/*! @brief Format value for bitfield CMP_MUXCR_PSEL. */
#define BF_CMP_MUXCR_PSEL(v) ((uint8_t)((uint8_t)(v) << BP_CMP_MUXCR_PSEL) & BM_CMP_MUXCR_PSEL)
/*! @brief Set the PSEL field to a new value. */
#define BW_CMP_MUXCR_PSEL(x, v) (HW_CMP_MUXCR_WR(x, (HW_CMP_MUXCR_RD(x) & ~BM_CMP_MUXCR_PSEL) | BF_CMP_MUXCR_PSEL(v)))
/*@}*/
/*******************************************************************************
* hw_cmp_t - module struct
******************************************************************************/
/*!
* @brief All CMP module registers.
*/
#pragma pack(1)
typedef struct _hw_cmp
{
__IO hw_cmp_cr0_t CR0; /*!< [0x0] CMP Control Register 0 */
__IO hw_cmp_cr1_t CR1; /*!< [0x1] CMP Control Register 1 */
__IO hw_cmp_fpr_t FPR; /*!< [0x2] CMP Filter Period Register */
__IO hw_cmp_scr_t SCR; /*!< [0x3] CMP Status and Control Register */
__IO hw_cmp_daccr_t DACCR; /*!< [0x4] DAC Control Register */
__IO hw_cmp_muxcr_t MUXCR; /*!< [0x5] MUX Control Register */
} hw_cmp_t;
#pragma pack()
/*! @brief Macro to access all CMP registers. */
/*! @param x CMP module instance base address. */
/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
* use the '&' operator, like <code>&HW_CMP(CMP0_BASE)</code>. */
#define HW_CMP(x) (*(hw_cmp_t *)(x))
#endif /* __HW_CMP_REGISTERS_H__ */
/* EOF */

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/*
** ###################################################################
** Compilers: Keil ARM C/C++ Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
** Version: rev. 2.5, 2014-05-06
** Build: b140604
**
** Abstract:
** Extension to the CMSIS register access layer header.
**
** Copyright (c) 2014 Freescale Semiconductor, Inc.
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** Revisions:
** - rev. 1.0 (2013-07-23)
** Initial version.
** - rev. 1.1 (2013-09-17)
** RM rev. 0.4 update.
** - rev. 2.0 (2013-10-29)
** Register accessor macros added to the memory map.
** Symbols for Processor Expert memory map compatibility added to the memory map.
** Startup file for gcc has been updated according to CMSIS 3.2.
** System initialization updated.
** - rev. 2.1 (2013-10-30)
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
** - rev. 2.2 (2013-12-20)
** Update according to reference manual rev. 0.6,
** - rev. 2.3 (2014-01-13)
** Update according to reference manual rev. 0.61,
** - rev. 2.4 (2014-02-10)
** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
** - rev. 2.5 (2014-05-06)
** Update according to reference manual rev. 1.0,
** Update of system and startup files.
** Module access macro module_BASES replaced by module_BASE_PTRS.
**
** ###################################################################
*/
/*
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
*
* This file was generated automatically and any changes may be lost.
*/
#ifndef __HW_DAC_REGISTERS_H__
#define __HW_DAC_REGISTERS_H__
#include "MK22F51212.h"
#include "fsl_bitaccess.h"
/*
* MK22F51212 DAC
*
* 12-Bit Digital-to-Analog Converter
*
* Registers defined in this header file:
* - HW_DAC_DATnL - DAC Data Low Register
* - HW_DAC_DATnH - DAC Data High Register
* - HW_DAC_SR - DAC Status Register
* - HW_DAC_C0 - DAC Control Register
* - HW_DAC_C1 - DAC Control Register 1
* - HW_DAC_C2 - DAC Control Register 2
*
* - hw_dac_t - Struct containing all module registers.
*/
#define HW_DAC_INSTANCE_COUNT (2U) /*!< Number of instances of the DAC module. */
#define HW_DAC0 (0U) /*!< Instance number for DAC0. */
#define HW_DAC1 (1U) /*!< Instance number for DAC1. */
/*******************************************************************************
* HW_DAC_DATnL - DAC Data Low Register
******************************************************************************/
/*!
* @brief HW_DAC_DATnL - DAC Data Low Register (RW)
*
* Reset value: 0x00U
*/
typedef union _hw_dac_datnl
{
uint8_t U;
struct _hw_dac_datnl_bitfields
{
uint8_t DATA0 : 8; /*!< [7:0] */
} B;
} hw_dac_datnl_t;
/*!
* @name Constants and macros for entire DAC_DATnL register
*/
/*@{*/
#define HW_DAC_DATnL_COUNT (16U)
#define HW_DAC_DATnL_ADDR(x, n) ((x) + 0x0U + (0x2U * (n)))
#define HW_DAC_DATnL(x, n) (*(__IO hw_dac_datnl_t *) HW_DAC_DATnL_ADDR(x, n))
#define HW_DAC_DATnL_RD(x, n) (HW_DAC_DATnL(x, n).U)
#define HW_DAC_DATnL_WR(x, n, v) (HW_DAC_DATnL(x, n).U = (v))
#define HW_DAC_DATnL_SET(x, n, v) (HW_DAC_DATnL_WR(x, n, HW_DAC_DATnL_RD(x, n) | (v)))
#define HW_DAC_DATnL_CLR(x, n, v) (HW_DAC_DATnL_WR(x, n, HW_DAC_DATnL_RD(x, n) & ~(v)))
#define HW_DAC_DATnL_TOG(x, n, v) (HW_DAC_DATnL_WR(x, n, HW_DAC_DATnL_RD(x, n) ^ (v)))
/*@}*/
/*
* Constants & macros for individual DAC_DATnL bitfields
*/
/*!
* @name Register DAC_DATnL, field DATA0[7:0] (RW)
*
* When the DAC buffer is not enabled, DATA[11:0] controls the output voltage
* based on the following formula: V out = V in * (1 + DACDAT0[11:0])/4096 When the
* DAC buffer is enabled, DATA is mapped to the 16-word buffer.
*/
/*@{*/
#define BP_DAC_DATnL_DATA0 (0U) /*!< Bit position for DAC_DATnL_DATA0. */
#define BM_DAC_DATnL_DATA0 (0xFFU) /*!< Bit mask for DAC_DATnL_DATA0. */
#define BS_DAC_DATnL_DATA0 (8U) /*!< Bit field size in bits for DAC_DATnL_DATA0. */
/*! @brief Read current value of the DAC_DATnL_DATA0 field. */
#define BR_DAC_DATnL_DATA0(x, n) (HW_DAC_DATnL(x, n).U)
/*! @brief Format value for bitfield DAC_DATnL_DATA0. */
#define BF_DAC_DATnL_DATA0(v) ((uint8_t)((uint8_t)(v) << BP_DAC_DATnL_DATA0) & BM_DAC_DATnL_DATA0)
/*! @brief Set the DATA0 field to a new value. */
#define BW_DAC_DATnL_DATA0(x, n, v) (HW_DAC_DATnL_WR(x, n, v))
/*@}*/
/*******************************************************************************
* HW_DAC_DATnH - DAC Data High Register
******************************************************************************/
/*!
* @brief HW_DAC_DATnH - DAC Data High Register (RW)
*
* Reset value: 0x00U
*/
typedef union _hw_dac_datnh
{
uint8_t U;
struct _hw_dac_datnh_bitfields
{
uint8_t DATA1 : 4; /*!< [3:0] */
uint8_t RESERVED0 : 4; /*!< [7:4] */
} B;
} hw_dac_datnh_t;
/*!
* @name Constants and macros for entire DAC_DATnH register
*/
/*@{*/
#define HW_DAC_DATnH_COUNT (16U)
#define HW_DAC_DATnH_ADDR(x, n) ((x) + 0x1U + (0x2U * (n)))
#define HW_DAC_DATnH(x, n) (*(__IO hw_dac_datnh_t *) HW_DAC_DATnH_ADDR(x, n))
#define HW_DAC_DATnH_RD(x, n) (HW_DAC_DATnH(x, n).U)
#define HW_DAC_DATnH_WR(x, n, v) (HW_DAC_DATnH(x, n).U = (v))
#define HW_DAC_DATnH_SET(x, n, v) (HW_DAC_DATnH_WR(x, n, HW_DAC_DATnH_RD(x, n) | (v)))
#define HW_DAC_DATnH_CLR(x, n, v) (HW_DAC_DATnH_WR(x, n, HW_DAC_DATnH_RD(x, n) & ~(v)))
#define HW_DAC_DATnH_TOG(x, n, v) (HW_DAC_DATnH_WR(x, n, HW_DAC_DATnH_RD(x, n) ^ (v)))
/*@}*/
/*
* Constants & macros for individual DAC_DATnH bitfields
*/
/*!
* @name Register DAC_DATnH, field DATA1[3:0] (RW)
*
* When the DAC Buffer is not enabled, DATA[11:0] controls the output voltage
* based on the following formula. V out = V in * (1 + DACDAT0[11:0])/4096 When the
* DAC buffer is enabled, DATA[11:0] is mapped to the 16-word buffer.
*/
/*@{*/
#define BP_DAC_DATnH_DATA1 (0U) /*!< Bit position for DAC_DATnH_DATA1. */
#define BM_DAC_DATnH_DATA1 (0x0FU) /*!< Bit mask for DAC_DATnH_DATA1. */
#define BS_DAC_DATnH_DATA1 (4U) /*!< Bit field size in bits for DAC_DATnH_DATA1. */
/*! @brief Read current value of the DAC_DATnH_DATA1 field. */
#define BR_DAC_DATnH_DATA1(x, n) (HW_DAC_DATnH(x, n).B.DATA1)
/*! @brief Format value for bitfield DAC_DATnH_DATA1. */
#define BF_DAC_DATnH_DATA1(v) ((uint8_t)((uint8_t)(v) << BP_DAC_DATnH_DATA1) & BM_DAC_DATnH_DATA1)
/*! @brief Set the DATA1 field to a new value. */
#define BW_DAC_DATnH_DATA1(x, n, v) (HW_DAC_DATnH_WR(x, n, (HW_DAC_DATnH_RD(x, n) & ~BM_DAC_DATnH_DATA1) | BF_DAC_DATnH_DATA1(v)))
/*@}*/
/*******************************************************************************
* HW_DAC_SR - DAC Status Register
******************************************************************************/
/*!
* @brief HW_DAC_SR - DAC Status Register (RW)
*
* Reset value: 0x02U
*
* If DMA is enabled, the flags can be cleared automatically by DMA when the DMA
* request is done. Writing 0 to a field clears it whereas writing 1 has no
* effect. After reset, DACBFRPTF is set and can be cleared by software, if needed.
* The flags are set only when the data buffer status is changed.
*/
typedef union _hw_dac_sr
{
uint8_t U;
struct _hw_dac_sr_bitfields
{
uint8_t DACBFRPBF : 1; /*!< [0] DAC Buffer Read Pointer Bottom
* Position Flag */
uint8_t DACBFRPTF : 1; /*!< [1] DAC Buffer Read Pointer Top Position
* Flag */
uint8_t DACBFWMF : 1; /*!< [2] DAC Buffer Watermark Flag */
uint8_t RESERVED0 : 5; /*!< [7:3] */
} B;
} hw_dac_sr_t;
/*!
* @name Constants and macros for entire DAC_SR register
*/
/*@{*/
#define HW_DAC_SR_ADDR(x) ((x) + 0x20U)
#define HW_DAC_SR(x) (*(__IO hw_dac_sr_t *) HW_DAC_SR_ADDR(x))
#define HW_DAC_SR_RD(x) (HW_DAC_SR(x).U)
#define HW_DAC_SR_WR(x, v) (HW_DAC_SR(x).U = (v))
#define HW_DAC_SR_SET(x, v) (HW_DAC_SR_WR(x, HW_DAC_SR_RD(x) | (v)))
#define HW_DAC_SR_CLR(x, v) (HW_DAC_SR_WR(x, HW_DAC_SR_RD(x) & ~(v)))
#define HW_DAC_SR_TOG(x, v) (HW_DAC_SR_WR(x, HW_DAC_SR_RD(x) ^ (v)))
/*@}*/
/*
* Constants & macros for individual DAC_SR bitfields
*/
/*!
* @name Register DAC_SR, field DACBFRPBF[0] (RW)
*
* In FIFO mode, it is FIFO FULL status bit. It means FIFO read pointer equals
* Write Pointer because of Write Pointer increase. If this bit is set, any write
* to FIFO from either DMA or CPU is ignored by DAC. It is cleared if there is
* any DAC trigger making the DAC read pointer increase. Write to this bit is
* ignored in FIFO mode.
*
* Values:
* - 0 - The DAC buffer read pointer is not equal to C2[DACBFUP].
* - 1 - The DAC buffer read pointer is equal to C2[DACBFUP].
*/
/*@{*/
#define BP_DAC_SR_DACBFRPBF (0U) /*!< Bit position for DAC_SR_DACBFRPBF. */
#define BM_DAC_SR_DACBFRPBF (0x01U) /*!< Bit mask for DAC_SR_DACBFRPBF. */
#define BS_DAC_SR_DACBFRPBF (1U) /*!< Bit field size in bits for DAC_SR_DACBFRPBF. */
/*! @brief Read current value of the DAC_SR_DACBFRPBF field. */
#define BR_DAC_SR_DACBFRPBF(x) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFRPBF))
/*! @brief Format value for bitfield DAC_SR_DACBFRPBF. */
#define BF_DAC_SR_DACBFRPBF(v) ((uint8_t)((uint8_t)(v) << BP_DAC_SR_DACBFRPBF) & BM_DAC_SR_DACBFRPBF)
/*! @brief Set the DACBFRPBF field to a new value. */
#define BW_DAC_SR_DACBFRPBF(x, v) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFRPBF) = (v))
/*@}*/
/*!
* @name Register DAC_SR, field DACBFRPTF[1] (RW)
*
* In FIFO mode, it is FIFO nearly empty flag. It is set when only one data
* remains in FIFO. Any DAC trigger does not increase the Read Pointer if this bit is
* set to avoid any possible glitch or abrupt change at DAC output. It is
* cleared automatically if FIFO is not empty.
*
* Values:
* - 0 - The DAC buffer read pointer is not zero.
* - 1 - The DAC buffer read pointer is zero.
*/
/*@{*/
#define BP_DAC_SR_DACBFRPTF (1U) /*!< Bit position for DAC_SR_DACBFRPTF. */
#define BM_DAC_SR_DACBFRPTF (0x02U) /*!< Bit mask for DAC_SR_DACBFRPTF. */
#define BS_DAC_SR_DACBFRPTF (1U) /*!< Bit field size in bits for DAC_SR_DACBFRPTF. */
/*! @brief Read current value of the DAC_SR_DACBFRPTF field. */
#define BR_DAC_SR_DACBFRPTF(x) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFRPTF))
/*! @brief Format value for bitfield DAC_SR_DACBFRPTF. */
#define BF_DAC_SR_DACBFRPTF(v) ((uint8_t)((uint8_t)(v) << BP_DAC_SR_DACBFRPTF) & BM_DAC_SR_DACBFRPTF)
/*! @brief Set the DACBFRPTF field to a new value. */
#define BW_DAC_SR_DACBFRPTF(x, v) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFRPTF) = (v))
/*@}*/
/*!
* @name Register DAC_SR, field DACBFWMF[2] (RW)
*
* This bit is set if the remaining FIFO data is less than the watermark
* setting. It is cleared automatically by writing data into FIFO by DMA or CPU. Write
* to this bit is ignored in FIFO mode.
*
* Values:
* - 0 - The DAC buffer read pointer has not reached the watermark level.
* - 1 - The DAC buffer read pointer has reached the watermark level.
*/
/*@{*/
#define BP_DAC_SR_DACBFWMF (2U) /*!< Bit position for DAC_SR_DACBFWMF. */
#define BM_DAC_SR_DACBFWMF (0x04U) /*!< Bit mask for DAC_SR_DACBFWMF. */
#define BS_DAC_SR_DACBFWMF (1U) /*!< Bit field size in bits for DAC_SR_DACBFWMF. */
/*! @brief Read current value of the DAC_SR_DACBFWMF field. */
#define BR_DAC_SR_DACBFWMF(x) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFWMF))
/*! @brief Format value for bitfield DAC_SR_DACBFWMF. */
#define BF_DAC_SR_DACBFWMF(v) ((uint8_t)((uint8_t)(v) << BP_DAC_SR_DACBFWMF) & BM_DAC_SR_DACBFWMF)
/*! @brief Set the DACBFWMF field to a new value. */
#define BW_DAC_SR_DACBFWMF(x, v) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFWMF) = (v))
/*@}*/
/*******************************************************************************
* HW_DAC_C0 - DAC Control Register
******************************************************************************/
/*!
* @brief HW_DAC_C0 - DAC Control Register (RW)
*
* Reset value: 0x00U
*/
typedef union _hw_dac_c0
{
uint8_t U;
struct _hw_dac_c0_bitfields
{
uint8_t DACBBIEN : 1; /*!< [0] DAC Buffer Read Pointer Bottom Flag
* Interrupt Enable */
uint8_t DACBTIEN : 1; /*!< [1] DAC Buffer Read Pointer Top Flag
* Interrupt Enable */
uint8_t DACBWIEN : 1; /*!< [2] DAC Buffer Watermark Interrupt Enable
* */
uint8_t LPEN : 1; /*!< [3] DAC Low Power Control */
uint8_t DACSWTRG : 1; /*!< [4] DAC Software Trigger */
uint8_t DACTRGSEL : 1; /*!< [5] DAC Trigger Select */
uint8_t DACRFS : 1; /*!< [6] DAC Reference Select */
uint8_t DACEN : 1; /*!< [7] DAC Enable */
} B;
} hw_dac_c0_t;
/*!
* @name Constants and macros for entire DAC_C0 register
*/
/*@{*/
#define HW_DAC_C0_ADDR(x) ((x) + 0x21U)
#define HW_DAC_C0(x) (*(__IO hw_dac_c0_t *) HW_DAC_C0_ADDR(x))
#define HW_DAC_C0_RD(x) (HW_DAC_C0(x).U)
#define HW_DAC_C0_WR(x, v) (HW_DAC_C0(x).U = (v))
#define HW_DAC_C0_SET(x, v) (HW_DAC_C0_WR(x, HW_DAC_C0_RD(x) | (v)))
#define HW_DAC_C0_CLR(x, v) (HW_DAC_C0_WR(x, HW_DAC_C0_RD(x) & ~(v)))
#define HW_DAC_C0_TOG(x, v) (HW_DAC_C0_WR(x, HW_DAC_C0_RD(x) ^ (v)))
/*@}*/
/*
* Constants & macros for individual DAC_C0 bitfields
*/
/*!
* @name Register DAC_C0, field DACBBIEN[0] (RW)
*
* Values:
* - 0 - The DAC buffer read pointer bottom flag interrupt is disabled.
* - 1 - The DAC buffer read pointer bottom flag interrupt is enabled.
*/
/*@{*/
#define BP_DAC_C0_DACBBIEN (0U) /*!< Bit position for DAC_C0_DACBBIEN. */
#define BM_DAC_C0_DACBBIEN (0x01U) /*!< Bit mask for DAC_C0_DACBBIEN. */
#define BS_DAC_C0_DACBBIEN (1U) /*!< Bit field size in bits for DAC_C0_DACBBIEN. */
/*! @brief Read current value of the DAC_C0_DACBBIEN field. */
#define BR_DAC_C0_DACBBIEN(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBBIEN))
/*! @brief Format value for bitfield DAC_C0_DACBBIEN. */
#define BF_DAC_C0_DACBBIEN(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C0_DACBBIEN) & BM_DAC_C0_DACBBIEN)
/*! @brief Set the DACBBIEN field to a new value. */
#define BW_DAC_C0_DACBBIEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBBIEN) = (v))
/*@}*/
/*!
* @name Register DAC_C0, field DACBTIEN[1] (RW)
*
* Values:
* - 0 - The DAC buffer read pointer top flag interrupt is disabled.
* - 1 - The DAC buffer read pointer top flag interrupt is enabled.
*/
/*@{*/
#define BP_DAC_C0_DACBTIEN (1U) /*!< Bit position for DAC_C0_DACBTIEN. */
#define BM_DAC_C0_DACBTIEN (0x02U) /*!< Bit mask for DAC_C0_DACBTIEN. */
#define BS_DAC_C0_DACBTIEN (1U) /*!< Bit field size in bits for DAC_C0_DACBTIEN. */
/*! @brief Read current value of the DAC_C0_DACBTIEN field. */
#define BR_DAC_C0_DACBTIEN(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBTIEN))
/*! @brief Format value for bitfield DAC_C0_DACBTIEN. */
#define BF_DAC_C0_DACBTIEN(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C0_DACBTIEN) & BM_DAC_C0_DACBTIEN)
/*! @brief Set the DACBTIEN field to a new value. */
#define BW_DAC_C0_DACBTIEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBTIEN) = (v))
/*@}*/
/*!
* @name Register DAC_C0, field DACBWIEN[2] (RW)
*
* Values:
* - 0 - The DAC buffer watermark interrupt is disabled.
* - 1 - The DAC buffer watermark interrupt is enabled.
*/
/*@{*/
#define BP_DAC_C0_DACBWIEN (2U) /*!< Bit position for DAC_C0_DACBWIEN. */
#define BM_DAC_C0_DACBWIEN (0x04U) /*!< Bit mask for DAC_C0_DACBWIEN. */
#define BS_DAC_C0_DACBWIEN (1U) /*!< Bit field size in bits for DAC_C0_DACBWIEN. */
/*! @brief Read current value of the DAC_C0_DACBWIEN field. */
#define BR_DAC_C0_DACBWIEN(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBWIEN))
/*! @brief Format value for bitfield DAC_C0_DACBWIEN. */
#define BF_DAC_C0_DACBWIEN(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C0_DACBWIEN) & BM_DAC_C0_DACBWIEN)
/*! @brief Set the DACBWIEN field to a new value. */
#define BW_DAC_C0_DACBWIEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBWIEN) = (v))
/*@}*/
/*!
* @name Register DAC_C0, field LPEN[3] (RW)
*
* See the 12-bit DAC electrical characteristics of the device data sheet for
* details on the impact of the modes below.
*
* Values:
* - 0 - High-Power mode
* - 1 - Low-Power mode
*/
/*@{*/
#define BP_DAC_C0_LPEN (3U) /*!< Bit position for DAC_C0_LPEN. */
#define BM_DAC_C0_LPEN (0x08U) /*!< Bit mask for DAC_C0_LPEN. */
#define BS_DAC_C0_LPEN (1U) /*!< Bit field size in bits for DAC_C0_LPEN. */
/*! @brief Read current value of the DAC_C0_LPEN field. */
#define BR_DAC_C0_LPEN(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_LPEN))
/*! @brief Format value for bitfield DAC_C0_LPEN. */
#define BF_DAC_C0_LPEN(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C0_LPEN) & BM_DAC_C0_LPEN)
/*! @brief Set the LPEN field to a new value. */
#define BW_DAC_C0_LPEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_LPEN) = (v))
/*@}*/
/*!
* @name Register DAC_C0, field DACSWTRG[4] (WORZ)
*
* Active high. This is a write-only field, which always reads 0. If DAC
* software trigger is selected and buffer is enabled, writing 1 to this field will
* advance the buffer read pointer once.
*
* Values:
* - 0 - The DAC soft trigger is not valid.
* - 1 - The DAC soft trigger is valid.
*/
/*@{*/
#define BP_DAC_C0_DACSWTRG (4U) /*!< Bit position for DAC_C0_DACSWTRG. */
#define BM_DAC_C0_DACSWTRG (0x10U) /*!< Bit mask for DAC_C0_DACSWTRG. */
#define BS_DAC_C0_DACSWTRG (1U) /*!< Bit field size in bits for DAC_C0_DACSWTRG. */
/*! @brief Format value for bitfield DAC_C0_DACSWTRG. */
#define BF_DAC_C0_DACSWTRG(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C0_DACSWTRG) & BM_DAC_C0_DACSWTRG)
/*! @brief Set the DACSWTRG field to a new value. */
#define BW_DAC_C0_DACSWTRG(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACSWTRG) = (v))
/*@}*/
/*!
* @name Register DAC_C0, field DACTRGSEL[5] (RW)
*
* Values:
* - 0 - The DAC hardware trigger is selected.
* - 1 - The DAC software trigger is selected.
*/
/*@{*/
#define BP_DAC_C0_DACTRGSEL (5U) /*!< Bit position for DAC_C0_DACTRGSEL. */
#define BM_DAC_C0_DACTRGSEL (0x20U) /*!< Bit mask for DAC_C0_DACTRGSEL. */
#define BS_DAC_C0_DACTRGSEL (1U) /*!< Bit field size in bits for DAC_C0_DACTRGSEL. */
/*! @brief Read current value of the DAC_C0_DACTRGSEL field. */
#define BR_DAC_C0_DACTRGSEL(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACTRGSEL))
/*! @brief Format value for bitfield DAC_C0_DACTRGSEL. */
#define BF_DAC_C0_DACTRGSEL(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C0_DACTRGSEL) & BM_DAC_C0_DACTRGSEL)
/*! @brief Set the DACTRGSEL field to a new value. */
#define BW_DAC_C0_DACTRGSEL(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACTRGSEL) = (v))
/*@}*/
/*!
* @name Register DAC_C0, field DACRFS[6] (RW)
*
* Values:
* - 0 - The DAC selects DACREF_1 as the reference voltage.
* - 1 - The DAC selects DACREF_2 as the reference voltage.
*/
/*@{*/
#define BP_DAC_C0_DACRFS (6U) /*!< Bit position for DAC_C0_DACRFS. */
#define BM_DAC_C0_DACRFS (0x40U) /*!< Bit mask for DAC_C0_DACRFS. */
#define BS_DAC_C0_DACRFS (1U) /*!< Bit field size in bits for DAC_C0_DACRFS. */
/*! @brief Read current value of the DAC_C0_DACRFS field. */
#define BR_DAC_C0_DACRFS(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACRFS))
/*! @brief Format value for bitfield DAC_C0_DACRFS. */
#define BF_DAC_C0_DACRFS(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C0_DACRFS) & BM_DAC_C0_DACRFS)
/*! @brief Set the DACRFS field to a new value. */
#define BW_DAC_C0_DACRFS(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACRFS) = (v))
/*@}*/
/*!
* @name Register DAC_C0, field DACEN[7] (RW)
*
* Starts the Programmable Reference Generator operation.
*
* Values:
* - 0 - The DAC system is disabled.
* - 1 - The DAC system is enabled.
*/
/*@{*/
#define BP_DAC_C0_DACEN (7U) /*!< Bit position for DAC_C0_DACEN. */
#define BM_DAC_C0_DACEN (0x80U) /*!< Bit mask for DAC_C0_DACEN. */
#define BS_DAC_C0_DACEN (1U) /*!< Bit field size in bits for DAC_C0_DACEN. */
/*! @brief Read current value of the DAC_C0_DACEN field. */
#define BR_DAC_C0_DACEN(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACEN))
/*! @brief Format value for bitfield DAC_C0_DACEN. */
#define BF_DAC_C0_DACEN(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C0_DACEN) & BM_DAC_C0_DACEN)
/*! @brief Set the DACEN field to a new value. */
#define BW_DAC_C0_DACEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACEN) = (v))
/*@}*/
/*******************************************************************************
* HW_DAC_C1 - DAC Control Register 1
******************************************************************************/
/*!
* @brief HW_DAC_C1 - DAC Control Register 1 (RW)
*
* Reset value: 0x00U
*/
typedef union _hw_dac_c1
{
uint8_t U;
struct _hw_dac_c1_bitfields
{
uint8_t DACBFEN : 1; /*!< [0] DAC Buffer Enable */
uint8_t DACBFMD : 2; /*!< [2:1] DAC Buffer Work Mode Select */
uint8_t DACBFWM : 2; /*!< [4:3] DAC Buffer Watermark Select */
uint8_t RESERVED0 : 2; /*!< [6:5] */
uint8_t DMAEN : 1; /*!< [7] DMA Enable Select */
} B;
} hw_dac_c1_t;
/*!
* @name Constants and macros for entire DAC_C1 register
*/
/*@{*/
#define HW_DAC_C1_ADDR(x) ((x) + 0x22U)
#define HW_DAC_C1(x) (*(__IO hw_dac_c1_t *) HW_DAC_C1_ADDR(x))
#define HW_DAC_C1_RD(x) (HW_DAC_C1(x).U)
#define HW_DAC_C1_WR(x, v) (HW_DAC_C1(x).U = (v))
#define HW_DAC_C1_SET(x, v) (HW_DAC_C1_WR(x, HW_DAC_C1_RD(x) | (v)))
#define HW_DAC_C1_CLR(x, v) (HW_DAC_C1_WR(x, HW_DAC_C1_RD(x) & ~(v)))
#define HW_DAC_C1_TOG(x, v) (HW_DAC_C1_WR(x, HW_DAC_C1_RD(x) ^ (v)))
/*@}*/
/*
* Constants & macros for individual DAC_C1 bitfields
*/
/*!
* @name Register DAC_C1, field DACBFEN[0] (RW)
*
* Values:
* - 0 - Buffer read pointer is disabled. The converted data is always the first
* word of the buffer.
* - 1 - Buffer read pointer is enabled. The converted data is the word that the
* read pointer points to. It means converted data can be from any word of
* the buffer.
*/
/*@{*/
#define BP_DAC_C1_DACBFEN (0U) /*!< Bit position for DAC_C1_DACBFEN. */
#define BM_DAC_C1_DACBFEN (0x01U) /*!< Bit mask for DAC_C1_DACBFEN. */
#define BS_DAC_C1_DACBFEN (1U) /*!< Bit field size in bits for DAC_C1_DACBFEN. */
/*! @brief Read current value of the DAC_C1_DACBFEN field. */
#define BR_DAC_C1_DACBFEN(x) (BITBAND_ACCESS8(HW_DAC_C1_ADDR(x), BP_DAC_C1_DACBFEN))
/*! @brief Format value for bitfield DAC_C1_DACBFEN. */
#define BF_DAC_C1_DACBFEN(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C1_DACBFEN) & BM_DAC_C1_DACBFEN)
/*! @brief Set the DACBFEN field to a new value. */
#define BW_DAC_C1_DACBFEN(x, v) (BITBAND_ACCESS8(HW_DAC_C1_ADDR(x), BP_DAC_C1_DACBFEN) = (v))
/*@}*/
/*!
* @name Register DAC_C1, field DACBFMD[2:1] (RW)
*
* Values:
* - 00 - Normal mode
* - 01 - Swing mode
* - 10 - One-Time Scan mode
* - 11 - FIFO mode
*/
/*@{*/
#define BP_DAC_C1_DACBFMD (1U) /*!< Bit position for DAC_C1_DACBFMD. */
#define BM_DAC_C1_DACBFMD (0x06U) /*!< Bit mask for DAC_C1_DACBFMD. */
#define BS_DAC_C1_DACBFMD (2U) /*!< Bit field size in bits for DAC_C1_DACBFMD. */
/*! @brief Read current value of the DAC_C1_DACBFMD field. */
#define BR_DAC_C1_DACBFMD(x) (HW_DAC_C1(x).B.DACBFMD)
/*! @brief Format value for bitfield DAC_C1_DACBFMD. */
#define BF_DAC_C1_DACBFMD(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C1_DACBFMD) & BM_DAC_C1_DACBFMD)
/*! @brief Set the DACBFMD field to a new value. */
#define BW_DAC_C1_DACBFMD(x, v) (HW_DAC_C1_WR(x, (HW_DAC_C1_RD(x) & ~BM_DAC_C1_DACBFMD) | BF_DAC_C1_DACBFMD(v)))
/*@}*/
/*!
* @name Register DAC_C1, field DACBFWM[4:3] (RW)
*
* In normal mode it controls when SR[DACBFWMF] is set. When the DAC buffer read
* pointer reaches the word defined by this field, which is 1-4 words away from
* the upper limit (DACBUP), SR[DACBFWMF] will be set. This allows user
* configuration of the watermark interrupt. In FIFO mode, it is FIFO watermark select
* field.
*
* Values:
* - 00 - In normal mode, 1 word . In FIFO mode, 2 or less than 2 data remaining
* in FIFO will set watermark status bit.
* - 01 - In normal mode, 2 words . In FIFO mode, Max/4 or less than Max/4 data
* remaining in FIFO will set watermark status bit.
* - 10 - In normal mode, 3 words . In FIFO mode, Max/2 or less than Max/2 data
* remaining in FIFO will set watermark status bit.
* - 11 - In normal mode, 4 words . In FIFO mode, Max-2 or less than Max-2 data
* remaining in FIFO will set watermark status bit.
*/
/*@{*/
#define BP_DAC_C1_DACBFWM (3U) /*!< Bit position for DAC_C1_DACBFWM. */
#define BM_DAC_C1_DACBFWM (0x18U) /*!< Bit mask for DAC_C1_DACBFWM. */
#define BS_DAC_C1_DACBFWM (2U) /*!< Bit field size in bits for DAC_C1_DACBFWM. */
/*! @brief Read current value of the DAC_C1_DACBFWM field. */
#define BR_DAC_C1_DACBFWM(x) (HW_DAC_C1(x).B.DACBFWM)
/*! @brief Format value for bitfield DAC_C1_DACBFWM. */
#define BF_DAC_C1_DACBFWM(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C1_DACBFWM) & BM_DAC_C1_DACBFWM)
/*! @brief Set the DACBFWM field to a new value. */
#define BW_DAC_C1_DACBFWM(x, v) (HW_DAC_C1_WR(x, (HW_DAC_C1_RD(x) & ~BM_DAC_C1_DACBFWM) | BF_DAC_C1_DACBFWM(v)))
/*@}*/
/*!
* @name Register DAC_C1, field DMAEN[7] (RW)
*
* Values:
* - 0 - DMA is disabled.
* - 1 - DMA is enabled. When DMA is enabled, the DMA request will be generated
* by original interrupts. The interrupts will not be presented on this
* module at the same time.
*/
/*@{*/
#define BP_DAC_C1_DMAEN (7U) /*!< Bit position for DAC_C1_DMAEN. */
#define BM_DAC_C1_DMAEN (0x80U) /*!< Bit mask for DAC_C1_DMAEN. */
#define BS_DAC_C1_DMAEN (1U) /*!< Bit field size in bits for DAC_C1_DMAEN. */
/*! @brief Read current value of the DAC_C1_DMAEN field. */
#define BR_DAC_C1_DMAEN(x) (BITBAND_ACCESS8(HW_DAC_C1_ADDR(x), BP_DAC_C1_DMAEN))
/*! @brief Format value for bitfield DAC_C1_DMAEN. */
#define BF_DAC_C1_DMAEN(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C1_DMAEN) & BM_DAC_C1_DMAEN)
/*! @brief Set the DMAEN field to a new value. */
#define BW_DAC_C1_DMAEN(x, v) (BITBAND_ACCESS8(HW_DAC_C1_ADDR(x), BP_DAC_C1_DMAEN) = (v))
/*@}*/
/*******************************************************************************
* HW_DAC_C2 - DAC Control Register 2
******************************************************************************/
/*!
* @brief HW_DAC_C2 - DAC Control Register 2 (RW)
*
* Reset value: 0x0FU
*/
typedef union _hw_dac_c2
{
uint8_t U;
struct _hw_dac_c2_bitfields
{
uint8_t DACBFUP : 4; /*!< [3:0] DAC Buffer Upper Limit */
uint8_t DACBFRP : 4; /*!< [7:4] DAC Buffer Read Pointer */
} B;
} hw_dac_c2_t;
/*!
* @name Constants and macros for entire DAC_C2 register
*/
/*@{*/
#define HW_DAC_C2_ADDR(x) ((x) + 0x23U)
#define HW_DAC_C2(x) (*(__IO hw_dac_c2_t *) HW_DAC_C2_ADDR(x))
#define HW_DAC_C2_RD(x) (HW_DAC_C2(x).U)
#define HW_DAC_C2_WR(x, v) (HW_DAC_C2(x).U = (v))
#define HW_DAC_C2_SET(x, v) (HW_DAC_C2_WR(x, HW_DAC_C2_RD(x) | (v)))
#define HW_DAC_C2_CLR(x, v) (HW_DAC_C2_WR(x, HW_DAC_C2_RD(x) & ~(v)))
#define HW_DAC_C2_TOG(x, v) (HW_DAC_C2_WR(x, HW_DAC_C2_RD(x) ^ (v)))
/*@}*/
/*
* Constants & macros for individual DAC_C2 bitfields
*/
/*!
* @name Register DAC_C2, field DACBFUP[3:0] (RW)
*
* In normal mode it selects the upper limit of the DAC buffer. The buffer read
* pointer cannot exceed it. In FIFO mode it is the FIFO write pointer. User
* cannot set Buffer Up limit in FIFO mode. In Normal mode its reset value is MAX.
* When IP is configured to FIFO mode, this register becomes Write_Pointer, and its
* value is initially set to equal READ_POINTER automatically, and the FIFO
* status is empty. It is writable and user can configure it to the same address to
* reset FIFO as empty.
*/
/*@{*/
#define BP_DAC_C2_DACBFUP (0U) /*!< Bit position for DAC_C2_DACBFUP. */
#define BM_DAC_C2_DACBFUP (0x0FU) /*!< Bit mask for DAC_C2_DACBFUP. */
#define BS_DAC_C2_DACBFUP (4U) /*!< Bit field size in bits for DAC_C2_DACBFUP. */
/*! @brief Read current value of the DAC_C2_DACBFUP field. */
#define BR_DAC_C2_DACBFUP(x) (HW_DAC_C2(x).B.DACBFUP)
/*! @brief Format value for bitfield DAC_C2_DACBFUP. */
#define BF_DAC_C2_DACBFUP(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C2_DACBFUP) & BM_DAC_C2_DACBFUP)
/*! @brief Set the DACBFUP field to a new value. */
#define BW_DAC_C2_DACBFUP(x, v) (HW_DAC_C2_WR(x, (HW_DAC_C2_RD(x) & ~BM_DAC_C2_DACBFUP) | BF_DAC_C2_DACBFUP(v)))
/*@}*/
/*!
* @name Register DAC_C2, field DACBFRP[7:4] (RW)
*
* In normal mode it keeps the current value of the buffer read pointer. FIFO
* mode, it is the FIFO read pointer. It is writable in FIFO mode. User can
* configure it to same address to reset FIFO as empty.
*/
/*@{*/
#define BP_DAC_C2_DACBFRP (4U) /*!< Bit position for DAC_C2_DACBFRP. */
#define BM_DAC_C2_DACBFRP (0xF0U) /*!< Bit mask for DAC_C2_DACBFRP. */
#define BS_DAC_C2_DACBFRP (4U) /*!< Bit field size in bits for DAC_C2_DACBFRP. */
/*! @brief Read current value of the DAC_C2_DACBFRP field. */
#define BR_DAC_C2_DACBFRP(x) (HW_DAC_C2(x).B.DACBFRP)
/*! @brief Format value for bitfield DAC_C2_DACBFRP. */
#define BF_DAC_C2_DACBFRP(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C2_DACBFRP) & BM_DAC_C2_DACBFRP)
/*! @brief Set the DACBFRP field to a new value. */
#define BW_DAC_C2_DACBFRP(x, v) (HW_DAC_C2_WR(x, (HW_DAC_C2_RD(x) & ~BM_DAC_C2_DACBFRP) | BF_DAC_C2_DACBFRP(v)))
/*@}*/
/*******************************************************************************
* hw_dac_t - module struct
******************************************************************************/
/*!
* @brief All DAC module registers.
*/
#pragma pack(1)
typedef struct _hw_dac
{
struct {
__IO hw_dac_datnl_t DATnL; /*!< [0x0] DAC Data Low Register */
__IO hw_dac_datnh_t DATnH; /*!< [0x1] DAC Data High Register */
} DAT[16];
__IO hw_dac_sr_t SR; /*!< [0x20] DAC Status Register */
__IO hw_dac_c0_t C0; /*!< [0x21] DAC Control Register */
__IO hw_dac_c1_t C1; /*!< [0x22] DAC Control Register 1 */
__IO hw_dac_c2_t C2; /*!< [0x23] DAC Control Register 2 */
} hw_dac_t;
#pragma pack()
/*! @brief Macro to access all DAC registers. */
/*! @param x DAC module instance base address. */
/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
* use the '&' operator, like <code>&HW_DAC(DAC0_BASE)</code>. */
#define HW_DAC(x) (*(hw_dac_t *)(x))
#endif /* __HW_DAC_REGISTERS_H__ */
/* EOF */

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/*
** ###################################################################
** Compilers: Keil ARM C/C++ Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
** Version: rev. 2.5, 2014-05-06
** Build: b140604
**
** Abstract:
** Extension to the CMSIS register access layer header.
**
** Copyright (c) 2014 Freescale Semiconductor, Inc.
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** Revisions:
** - rev. 1.0 (2013-07-23)
** Initial version.
** - rev. 1.1 (2013-09-17)
** RM rev. 0.4 update.
** - rev. 2.0 (2013-10-29)
** Register accessor macros added to the memory map.
** Symbols for Processor Expert memory map compatibility added to the memory map.
** Startup file for gcc has been updated according to CMSIS 3.2.
** System initialization updated.
** - rev. 2.1 (2013-10-30)
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
** - rev. 2.2 (2013-12-20)
** Update according to reference manual rev. 0.6,
** - rev. 2.3 (2014-01-13)
** Update according to reference manual rev. 0.61,
** - rev. 2.4 (2014-02-10)
** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
** - rev. 2.5 (2014-05-06)
** Update according to reference manual rev. 1.0,
** Update of system and startup files.
** Module access macro module_BASES replaced by module_BASE_PTRS.
**
** ###################################################################
*/
/*
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
*
* This file was generated automatically and any changes may be lost.
*/
#ifndef __HW_DMAMUX_REGISTERS_H__
#define __HW_DMAMUX_REGISTERS_H__
#include "MK22F51212.h"
#include "fsl_bitaccess.h"
/*
* MK22F51212 DMAMUX
*
* DMA channel multiplexor
*
* Registers defined in this header file:
* - HW_DMAMUX_CHCFGn - Channel Configuration register
*
* - hw_dmamux_t - Struct containing all module registers.
*/
#define HW_DMAMUX_INSTANCE_COUNT (1U) /*!< Number of instances of the DMAMUX module. */
/*******************************************************************************
* HW_DMAMUX_CHCFGn - Channel Configuration register
******************************************************************************/
/*!
* @brief HW_DMAMUX_CHCFGn - Channel Configuration register (RW)
*
* Reset value: 0x00U
*
* Each of the DMA channels can be independently enabled/disabled and associated
* with one of the DMA slots (peripheral slots or always-on slots) in the
* system. Setting multiple CHCFG registers with the same source value will result in
* unpredictable behavior. Before changing the trigger or source settings, a DMA
* channel must be disabled via CHCFGn[ENBL].
*/
typedef union _hw_dmamux_chcfgn
{
uint8_t U;
struct _hw_dmamux_chcfgn_bitfields
{
uint8_t SOURCE : 6; /*!< [5:0] DMA Channel Source (Slot) */
uint8_t TRIG : 1; /*!< [6] DMA Channel Trigger Enable */
uint8_t ENBL : 1; /*!< [7] DMA Channel Enable */
} B;
} hw_dmamux_chcfgn_t;
/*!
* @name Constants and macros for entire DMAMUX_CHCFGn register
*/
/*@{*/
#define HW_DMAMUX_CHCFGn_COUNT (16U)
#define HW_DMAMUX_CHCFGn_ADDR(x, n) ((x) + 0x0U + (0x1U * (n)))
#define HW_DMAMUX_CHCFGn(x, n) (*(__IO hw_dmamux_chcfgn_t *) HW_DMAMUX_CHCFGn_ADDR(x, n))
#define HW_DMAMUX_CHCFGn_RD(x, n) (HW_DMAMUX_CHCFGn(x, n).U)
#define HW_DMAMUX_CHCFGn_WR(x, n, v) (HW_DMAMUX_CHCFGn(x, n).U = (v))
#define HW_DMAMUX_CHCFGn_SET(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, HW_DMAMUX_CHCFGn_RD(x, n) | (v)))
#define HW_DMAMUX_CHCFGn_CLR(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, HW_DMAMUX_CHCFGn_RD(x, n) & ~(v)))
#define HW_DMAMUX_CHCFGn_TOG(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, HW_DMAMUX_CHCFGn_RD(x, n) ^ (v)))
/*@}*/
/*
* Constants & macros for individual DMAMUX_CHCFGn bitfields
*/
/*!
* @name Register DMAMUX_CHCFGn, field SOURCE[5:0] (RW)
*
* Specifies which DMA source, if any, is routed to a particular DMA channel.
* See your device's chip configuration details for information about the
* peripherals and their slot numbers.
*/
/*@{*/
#define BP_DMAMUX_CHCFGn_SOURCE (0U) /*!< Bit position for DMAMUX_CHCFGn_SOURCE. */
#define BM_DMAMUX_CHCFGn_SOURCE (0x3FU) /*!< Bit mask for DMAMUX_CHCFGn_SOURCE. */
#define BS_DMAMUX_CHCFGn_SOURCE (6U) /*!< Bit field size in bits for DMAMUX_CHCFGn_SOURCE. */
/*! @brief Read current value of the DMAMUX_CHCFGn_SOURCE field. */
#define BR_DMAMUX_CHCFGn_SOURCE(x, n) (HW_DMAMUX_CHCFGn(x, n).B.SOURCE)
/*! @brief Format value for bitfield DMAMUX_CHCFGn_SOURCE. */
#define BF_DMAMUX_CHCFGn_SOURCE(v) ((uint8_t)((uint8_t)(v) << BP_DMAMUX_CHCFGn_SOURCE) & BM_DMAMUX_CHCFGn_SOURCE)
/*! @brief Set the SOURCE field to a new value. */
#define BW_DMAMUX_CHCFGn_SOURCE(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, (HW_DMAMUX_CHCFGn_RD(x, n) & ~BM_DMAMUX_CHCFGn_SOURCE) | BF_DMAMUX_CHCFGn_SOURCE(v)))
/*@}*/
/*!
* @name Register DMAMUX_CHCFGn, field TRIG[6] (RW)
*
* Enables the periodic trigger capability for the triggered DMA channel.
*
* Values:
* - 0 - Triggering is disabled. If triggering is disabled and ENBL is set, the
* DMA Channel will simply route the specified source to the DMA channel.
* (Normal mode)
* - 1 - Triggering is enabled. If triggering is enabled and ENBL is set, the
* DMAMUX is in Periodic Trigger mode.
*/
/*@{*/
#define BP_DMAMUX_CHCFGn_TRIG (6U) /*!< Bit position for DMAMUX_CHCFGn_TRIG. */
#define BM_DMAMUX_CHCFGn_TRIG (0x40U) /*!< Bit mask for DMAMUX_CHCFGn_TRIG. */
#define BS_DMAMUX_CHCFGn_TRIG (1U) /*!< Bit field size in bits for DMAMUX_CHCFGn_TRIG. */
/*! @brief Read current value of the DMAMUX_CHCFGn_TRIG field. */
#define BR_DMAMUX_CHCFGn_TRIG(x, n) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_TRIG))
/*! @brief Format value for bitfield DMAMUX_CHCFGn_TRIG. */
#define BF_DMAMUX_CHCFGn_TRIG(v) ((uint8_t)((uint8_t)(v) << BP_DMAMUX_CHCFGn_TRIG) & BM_DMAMUX_CHCFGn_TRIG)
/*! @brief Set the TRIG field to a new value. */
#define BW_DMAMUX_CHCFGn_TRIG(x, n, v) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_TRIG) = (v))
/*@}*/
/*!
* @name Register DMAMUX_CHCFGn, field ENBL[7] (RW)
*
* Enables the DMA channel.
*
* Values:
* - 0 - DMA channel is disabled. This mode is primarily used during
* configuration of the DMAMux. The DMA has separate channel enables/disables, which
* should be used to disable or reconfigure a DMA channel.
* - 1 - DMA channel is enabled
*/
/*@{*/
#define BP_DMAMUX_CHCFGn_ENBL (7U) /*!< Bit position for DMAMUX_CHCFGn_ENBL. */
#define BM_DMAMUX_CHCFGn_ENBL (0x80U) /*!< Bit mask for DMAMUX_CHCFGn_ENBL. */
#define BS_DMAMUX_CHCFGn_ENBL (1U) /*!< Bit field size in bits for DMAMUX_CHCFGn_ENBL. */
/*! @brief Read current value of the DMAMUX_CHCFGn_ENBL field. */
#define BR_DMAMUX_CHCFGn_ENBL(x, n) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_ENBL))
/*! @brief Format value for bitfield DMAMUX_CHCFGn_ENBL. */
#define BF_DMAMUX_CHCFGn_ENBL(v) ((uint8_t)((uint8_t)(v) << BP_DMAMUX_CHCFGn_ENBL) & BM_DMAMUX_CHCFGn_ENBL)
/*! @brief Set the ENBL field to a new value. */
#define BW_DMAMUX_CHCFGn_ENBL(x, n, v) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_ENBL) = (v))
/*@}*/
/*******************************************************************************
* hw_dmamux_t - module struct
******************************************************************************/
/*!
* @brief All DMAMUX module registers.
*/
#pragma pack(1)
typedef struct _hw_dmamux
{
__IO hw_dmamux_chcfgn_t CHCFGn[16]; /*!< [0x0] Channel Configuration register */
} hw_dmamux_t;
#pragma pack()
/*! @brief Macro to access all DMAMUX registers. */
/*! @param x DMAMUX module instance base address. */
/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
* use the '&' operator, like <code>&HW_DMAMUX(DMAMUX_BASE)</code>. */
#define HW_DMAMUX(x) (*(hw_dmamux_t *)(x))
#endif /* __HW_DMAMUX_REGISTERS_H__ */
/* EOF */

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/*
** ###################################################################
** Compilers: Keil ARM C/C++ Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
** Version: rev. 2.5, 2014-05-06
** Build: b140604
**
** Abstract:
** Extension to the CMSIS register access layer header.
**
** Copyright (c) 2014 Freescale Semiconductor, Inc.
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** Revisions:
** - rev. 1.0 (2013-07-23)
** Initial version.
** - rev. 1.1 (2013-09-17)
** RM rev. 0.4 update.
** - rev. 2.0 (2013-10-29)
** Register accessor macros added to the memory map.
** Symbols for Processor Expert memory map compatibility added to the memory map.
** Startup file for gcc has been updated according to CMSIS 3.2.
** System initialization updated.
** - rev. 2.1 (2013-10-30)
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
** - rev. 2.2 (2013-12-20)
** Update according to reference manual rev. 0.6,
** - rev. 2.3 (2014-01-13)
** Update according to reference manual rev. 0.61,
** - rev. 2.4 (2014-02-10)
** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
** - rev. 2.5 (2014-05-06)
** Update according to reference manual rev. 1.0,
** Update of system and startup files.
** Module access macro module_BASES replaced by module_BASE_PTRS.
**
** ###################################################################
*/
/*
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
*
* This file was generated automatically and any changes may be lost.
*/
#ifndef __HW_EWM_REGISTERS_H__
#define __HW_EWM_REGISTERS_H__
#include "MK22F51212.h"
#include "fsl_bitaccess.h"
/*
* MK22F51212 EWM
*
* External Watchdog Monitor
*
* Registers defined in this header file:
* - HW_EWM_CTRL - Control Register
* - HW_EWM_SERV - Service Register
* - HW_EWM_CMPL - Compare Low Register
* - HW_EWM_CMPH - Compare High Register
* - HW_EWM_CLKPRESCALER - Clock Prescaler Register
*
* - hw_ewm_t - Struct containing all module registers.
*/
#define HW_EWM_INSTANCE_COUNT (1U) /*!< Number of instances of the EWM module. */
/*******************************************************************************
* HW_EWM_CTRL - Control Register
******************************************************************************/
/*!
* @brief HW_EWM_CTRL - Control Register (RW)
*
* Reset value: 0x00U
*
* The CTRL register is cleared by any reset. INEN, ASSIN and EWMEN bits can be
* written once after a CPU reset. Modifying these bits more than once, generates
* a bus transfer error.
*/
typedef union _hw_ewm_ctrl
{
uint8_t U;
struct _hw_ewm_ctrl_bitfields
{
uint8_t EWMEN : 1; /*!< [0] EWM enable. */
uint8_t ASSIN : 1; /*!< [1] EWM_in's Assertion State Select. */
uint8_t INEN : 1; /*!< [2] Input Enable. */
uint8_t INTEN : 1; /*!< [3] Interrupt Enable. */
uint8_t RESERVED0 : 4; /*!< [7:4] */
} B;
} hw_ewm_ctrl_t;
/*!
* @name Constants and macros for entire EWM_CTRL register
*/
/*@{*/
#define HW_EWM_CTRL_ADDR(x) ((x) + 0x0U)
#define HW_EWM_CTRL(x) (*(__IO hw_ewm_ctrl_t *) HW_EWM_CTRL_ADDR(x))
#define HW_EWM_CTRL_RD(x) (HW_EWM_CTRL(x).U)
#define HW_EWM_CTRL_WR(x, v) (HW_EWM_CTRL(x).U = (v))
#define HW_EWM_CTRL_SET(x, v) (HW_EWM_CTRL_WR(x, HW_EWM_CTRL_RD(x) | (v)))
#define HW_EWM_CTRL_CLR(x, v) (HW_EWM_CTRL_WR(x, HW_EWM_CTRL_RD(x) & ~(v)))
#define HW_EWM_CTRL_TOG(x, v) (HW_EWM_CTRL_WR(x, HW_EWM_CTRL_RD(x) ^ (v)))
/*@}*/
/*
* Constants & macros for individual EWM_CTRL bitfields
*/
/*!
* @name Register EWM_CTRL, field EWMEN[0] (RW)
*
* This bit when set, enables the EWM module. This resets the EWM counter to
* zero and deasserts the EWM_out signal. Clearing EWMEN bit disables the EWM, and
* therefore it cannot be enabled until a reset occurs, due to the write-once
* nature of this bit.
*/
/*@{*/
#define BP_EWM_CTRL_EWMEN (0U) /*!< Bit position for EWM_CTRL_EWMEN. */
#define BM_EWM_CTRL_EWMEN (0x01U) /*!< Bit mask for EWM_CTRL_EWMEN. */
#define BS_EWM_CTRL_EWMEN (1U) /*!< Bit field size in bits for EWM_CTRL_EWMEN. */
/*! @brief Read current value of the EWM_CTRL_EWMEN field. */
#define BR_EWM_CTRL_EWMEN(x) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_EWMEN))
/*! @brief Format value for bitfield EWM_CTRL_EWMEN. */
#define BF_EWM_CTRL_EWMEN(v) ((uint8_t)((uint8_t)(v) << BP_EWM_CTRL_EWMEN) & BM_EWM_CTRL_EWMEN)
/*! @brief Set the EWMEN field to a new value. */
#define BW_EWM_CTRL_EWMEN(x, v) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_EWMEN) = (v))
/*@}*/
/*!
* @name Register EWM_CTRL, field ASSIN[1] (RW)
*
* Default assert state of the EWM_in signal is logic zero. Setting ASSIN bit
* inverts the assert state to a logic one.
*/
/*@{*/
#define BP_EWM_CTRL_ASSIN (1U) /*!< Bit position for EWM_CTRL_ASSIN. */
#define BM_EWM_CTRL_ASSIN (0x02U) /*!< Bit mask for EWM_CTRL_ASSIN. */
#define BS_EWM_CTRL_ASSIN (1U) /*!< Bit field size in bits for EWM_CTRL_ASSIN. */
/*! @brief Read current value of the EWM_CTRL_ASSIN field. */
#define BR_EWM_CTRL_ASSIN(x) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_ASSIN))
/*! @brief Format value for bitfield EWM_CTRL_ASSIN. */
#define BF_EWM_CTRL_ASSIN(v) ((uint8_t)((uint8_t)(v) << BP_EWM_CTRL_ASSIN) & BM_EWM_CTRL_ASSIN)
/*! @brief Set the ASSIN field to a new value. */
#define BW_EWM_CTRL_ASSIN(x, v) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_ASSIN) = (v))
/*@}*/
/*!
* @name Register EWM_CTRL, field INEN[2] (RW)
*
* This bit when set, enables the EWM_in port.
*/
/*@{*/
#define BP_EWM_CTRL_INEN (2U) /*!< Bit position for EWM_CTRL_INEN. */
#define BM_EWM_CTRL_INEN (0x04U) /*!< Bit mask for EWM_CTRL_INEN. */
#define BS_EWM_CTRL_INEN (1U) /*!< Bit field size in bits for EWM_CTRL_INEN. */
/*! @brief Read current value of the EWM_CTRL_INEN field. */
#define BR_EWM_CTRL_INEN(x) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_INEN))
/*! @brief Format value for bitfield EWM_CTRL_INEN. */
#define BF_EWM_CTRL_INEN(v) ((uint8_t)((uint8_t)(v) << BP_EWM_CTRL_INEN) & BM_EWM_CTRL_INEN)
/*! @brief Set the INEN field to a new value. */
#define BW_EWM_CTRL_INEN(x, v) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_INEN) = (v))
/*@}*/
/*!
* @name Register EWM_CTRL, field INTEN[3] (RW)
*
* This bit when set and EWM_out is asserted, an interrupt request is generated.
* To de-assert interrupt request, user should clear this bit by writing 0.
*/
/*@{*/
#define BP_EWM_CTRL_INTEN (3U) /*!< Bit position for EWM_CTRL_INTEN. */
#define BM_EWM_CTRL_INTEN (0x08U) /*!< Bit mask for EWM_CTRL_INTEN. */
#define BS_EWM_CTRL_INTEN (1U) /*!< Bit field size in bits for EWM_CTRL_INTEN. */
/*! @brief Read current value of the EWM_CTRL_INTEN field. */
#define BR_EWM_CTRL_INTEN(x) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_INTEN))
/*! @brief Format value for bitfield EWM_CTRL_INTEN. */
#define BF_EWM_CTRL_INTEN(v) ((uint8_t)((uint8_t)(v) << BP_EWM_CTRL_INTEN) & BM_EWM_CTRL_INTEN)
/*! @brief Set the INTEN field to a new value. */
#define BW_EWM_CTRL_INTEN(x, v) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_INTEN) = (v))
/*@}*/
/*******************************************************************************
* HW_EWM_SERV - Service Register
******************************************************************************/
/*!
* @brief HW_EWM_SERV - Service Register (WORZ)
*
* Reset value: 0x00U
*
* The SERV register provides the interface from the CPU to the EWM module. It
* is write-only and reads of this register return zero.
*/
typedef union _hw_ewm_serv
{
uint8_t U;
struct _hw_ewm_serv_bitfields
{
uint8_t SERVICE : 8; /*!< [7:0] */
} B;
} hw_ewm_serv_t;
/*!
* @name Constants and macros for entire EWM_SERV register
*/
/*@{*/
#define HW_EWM_SERV_ADDR(x) ((x) + 0x1U)
#define HW_EWM_SERV(x) (*(__O hw_ewm_serv_t *) HW_EWM_SERV_ADDR(x))
#define HW_EWM_SERV_RD(x) (HW_EWM_SERV(x).U)
#define HW_EWM_SERV_WR(x, v) (HW_EWM_SERV(x).U = (v))
/*@}*/
/*
* Constants & macros for individual EWM_SERV bitfields
*/
/*!
* @name Register EWM_SERV, field SERVICE[7:0] (WORZ)
*
* The EWM service mechanism requires the CPU to write two values to the SERV
* register: a first data byte of 0xB4, followed by a second data byte of 0x2C. The
* EWM service is illegal if either of the following conditions is true. The
* first or second data byte is not written correctly. The second data byte is not
* written within a fixed number of peripheral bus cycles of the first data byte.
* This fixed number of cycles is called EWM_service_time.
*/
/*@{*/
#define BP_EWM_SERV_SERVICE (0U) /*!< Bit position for EWM_SERV_SERVICE. */
#define BM_EWM_SERV_SERVICE (0xFFU) /*!< Bit mask for EWM_SERV_SERVICE. */
#define BS_EWM_SERV_SERVICE (8U) /*!< Bit field size in bits for EWM_SERV_SERVICE. */
/*! @brief Format value for bitfield EWM_SERV_SERVICE. */
#define BF_EWM_SERV_SERVICE(v) ((uint8_t)((uint8_t)(v) << BP_EWM_SERV_SERVICE) & BM_EWM_SERV_SERVICE)
/*! @brief Set the SERVICE field to a new value. */
#define BW_EWM_SERV_SERVICE(x, v) (HW_EWM_SERV_WR(x, v))
/*@}*/
/*******************************************************************************
* HW_EWM_CMPL - Compare Low Register
******************************************************************************/
/*!
* @brief HW_EWM_CMPL - Compare Low Register (RW)
*
* Reset value: 0x00U
*
* The CMPL register is reset to zero after a CPU reset. This provides no
* minimum time for the CPU to service the EWM counter. This register can be written
* only once after a CPU reset. Writing this register more than once generates a
* bus transfer error.
*/
typedef union _hw_ewm_cmpl
{
uint8_t U;
struct _hw_ewm_cmpl_bitfields
{
uint8_t COMPAREL : 8; /*!< [7:0] */
} B;
} hw_ewm_cmpl_t;
/*!
* @name Constants and macros for entire EWM_CMPL register
*/
/*@{*/
#define HW_EWM_CMPL_ADDR(x) ((x) + 0x2U)
#define HW_EWM_CMPL(x) (*(__IO hw_ewm_cmpl_t *) HW_EWM_CMPL_ADDR(x))
#define HW_EWM_CMPL_RD(x) (HW_EWM_CMPL(x).U)
#define HW_EWM_CMPL_WR(x, v) (HW_EWM_CMPL(x).U = (v))
#define HW_EWM_CMPL_SET(x, v) (HW_EWM_CMPL_WR(x, HW_EWM_CMPL_RD(x) | (v)))
#define HW_EWM_CMPL_CLR(x, v) (HW_EWM_CMPL_WR(x, HW_EWM_CMPL_RD(x) & ~(v)))
#define HW_EWM_CMPL_TOG(x, v) (HW_EWM_CMPL_WR(x, HW_EWM_CMPL_RD(x) ^ (v)))
/*@}*/
/*
* Constants & macros for individual EWM_CMPL bitfields
*/
/*!
* @name Register EWM_CMPL, field COMPAREL[7:0] (RW)
*
* To prevent runaway code from changing this field, software should write to
* this field after a CPU reset even if the (default) minimum service time is
* required.
*/
/*@{*/
#define BP_EWM_CMPL_COMPAREL (0U) /*!< Bit position for EWM_CMPL_COMPAREL. */
#define BM_EWM_CMPL_COMPAREL (0xFFU) /*!< Bit mask for EWM_CMPL_COMPAREL. */
#define BS_EWM_CMPL_COMPAREL (8U) /*!< Bit field size in bits for EWM_CMPL_COMPAREL. */
/*! @brief Read current value of the EWM_CMPL_COMPAREL field. */
#define BR_EWM_CMPL_COMPAREL(x) (HW_EWM_CMPL(x).U)
/*! @brief Format value for bitfield EWM_CMPL_COMPAREL. */
#define BF_EWM_CMPL_COMPAREL(v) ((uint8_t)((uint8_t)(v) << BP_EWM_CMPL_COMPAREL) & BM_EWM_CMPL_COMPAREL)
/*! @brief Set the COMPAREL field to a new value. */
#define BW_EWM_CMPL_COMPAREL(x, v) (HW_EWM_CMPL_WR(x, v))
/*@}*/
/*******************************************************************************
* HW_EWM_CMPH - Compare High Register
******************************************************************************/
/*!
* @brief HW_EWM_CMPH - Compare High Register (RW)
*
* Reset value: 0xFFU
*
* The CMPH register is reset to 0xFF after a CPU reset. This provides a maximum
* of 256 clocks time, for the CPU to service the EWM counter. This register can
* be written only once after a CPU reset. Writing this register more than once
* generates a bus transfer error. The valid values for CMPH are up to 0xFE
* because the EWM counter never expires when CMPH = 0xFF. The expiration happens only
* if EWM counter is greater than CMPH.
*/
typedef union _hw_ewm_cmph
{
uint8_t U;
struct _hw_ewm_cmph_bitfields
{
uint8_t COMPAREH : 8; /*!< [7:0] */
} B;
} hw_ewm_cmph_t;
/*!
* @name Constants and macros for entire EWM_CMPH register
*/
/*@{*/
#define HW_EWM_CMPH_ADDR(x) ((x) + 0x3U)
#define HW_EWM_CMPH(x) (*(__IO hw_ewm_cmph_t *) HW_EWM_CMPH_ADDR(x))
#define HW_EWM_CMPH_RD(x) (HW_EWM_CMPH(x).U)
#define HW_EWM_CMPH_WR(x, v) (HW_EWM_CMPH(x).U = (v))
#define HW_EWM_CMPH_SET(x, v) (HW_EWM_CMPH_WR(x, HW_EWM_CMPH_RD(x) | (v)))
#define HW_EWM_CMPH_CLR(x, v) (HW_EWM_CMPH_WR(x, HW_EWM_CMPH_RD(x) & ~(v)))
#define HW_EWM_CMPH_TOG(x, v) (HW_EWM_CMPH_WR(x, HW_EWM_CMPH_RD(x) ^ (v)))
/*@}*/
/*
* Constants & macros for individual EWM_CMPH bitfields
*/
/*!
* @name Register EWM_CMPH, field COMPAREH[7:0] (RW)
*
* To prevent runaway code from changing this field, software should write to
* this field after a CPU reset even if the (default) maximum service time is
* required.
*/
/*@{*/
#define BP_EWM_CMPH_COMPAREH (0U) /*!< Bit position for EWM_CMPH_COMPAREH. */
#define BM_EWM_CMPH_COMPAREH (0xFFU) /*!< Bit mask for EWM_CMPH_COMPAREH. */
#define BS_EWM_CMPH_COMPAREH (8U) /*!< Bit field size in bits for EWM_CMPH_COMPAREH. */
/*! @brief Read current value of the EWM_CMPH_COMPAREH field. */
#define BR_EWM_CMPH_COMPAREH(x) (HW_EWM_CMPH(x).U)
/*! @brief Format value for bitfield EWM_CMPH_COMPAREH. */
#define BF_EWM_CMPH_COMPAREH(v) ((uint8_t)((uint8_t)(v) << BP_EWM_CMPH_COMPAREH) & BM_EWM_CMPH_COMPAREH)
/*! @brief Set the COMPAREH field to a new value. */
#define BW_EWM_CMPH_COMPAREH(x, v) (HW_EWM_CMPH_WR(x, v))
/*@}*/
/*******************************************************************************
* HW_EWM_CLKPRESCALER - Clock Prescaler Register
******************************************************************************/
/*!
* @brief HW_EWM_CLKPRESCALER - Clock Prescaler Register (RW)
*
* Reset value: 0x00U
*
* This CLKPRESCALER register is reset to 0x00 after a CPU reset. This register
* can be written only once after a CPU reset. Writing this register more than
* once generates a bus transfer error. Write the required prescaler value before
* enabling the EWM. The implementation of this register is chip-specific. See the
* Chip Configuration details.
*/
typedef union _hw_ewm_clkprescaler
{
uint8_t U;
struct _hw_ewm_clkprescaler_bitfields
{
uint8_t CLK_DIV : 8; /*!< [7:0] */
} B;
} hw_ewm_clkprescaler_t;
/*!
* @name Constants and macros for entire EWM_CLKPRESCALER register
*/
/*@{*/
#define HW_EWM_CLKPRESCALER_ADDR(x) ((x) + 0x5U)
#define HW_EWM_CLKPRESCALER(x) (*(__IO hw_ewm_clkprescaler_t *) HW_EWM_CLKPRESCALER_ADDR(x))
#define HW_EWM_CLKPRESCALER_RD(x) (HW_EWM_CLKPRESCALER(x).U)
#define HW_EWM_CLKPRESCALER_WR(x, v) (HW_EWM_CLKPRESCALER(x).U = (v))
#define HW_EWM_CLKPRESCALER_SET(x, v) (HW_EWM_CLKPRESCALER_WR(x, HW_EWM_CLKPRESCALER_RD(x) | (v)))
#define HW_EWM_CLKPRESCALER_CLR(x, v) (HW_EWM_CLKPRESCALER_WR(x, HW_EWM_CLKPRESCALER_RD(x) & ~(v)))
#define HW_EWM_CLKPRESCALER_TOG(x, v) (HW_EWM_CLKPRESCALER_WR(x, HW_EWM_CLKPRESCALER_RD(x) ^ (v)))
/*@}*/
/*
* Constants & macros for individual EWM_CLKPRESCALER bitfields
*/
/*!
* @name Register EWM_CLKPRESCALER, field CLK_DIV[7:0] (RW)
*
* Selected low power source for running the EWM counter can be prescaled as
* below. Prescaled clock frequency = low power clock source frequency/ ( 1+ CLK_DIV
* )
*/
/*@{*/
#define BP_EWM_CLKPRESCALER_CLK_DIV (0U) /*!< Bit position for EWM_CLKPRESCALER_CLK_DIV. */
#define BM_EWM_CLKPRESCALER_CLK_DIV (0xFFU) /*!< Bit mask for EWM_CLKPRESCALER_CLK_DIV. */
#define BS_EWM_CLKPRESCALER_CLK_DIV (8U) /*!< Bit field size in bits for EWM_CLKPRESCALER_CLK_DIV. */
/*! @brief Read current value of the EWM_CLKPRESCALER_CLK_DIV field. */
#define BR_EWM_CLKPRESCALER_CLK_DIV(x) (HW_EWM_CLKPRESCALER(x).U)
/*! @brief Format value for bitfield EWM_CLKPRESCALER_CLK_DIV. */
#define BF_EWM_CLKPRESCALER_CLK_DIV(v) ((uint8_t)((uint8_t)(v) << BP_EWM_CLKPRESCALER_CLK_DIV) & BM_EWM_CLKPRESCALER_CLK_DIV)
/*! @brief Set the CLK_DIV field to a new value. */
#define BW_EWM_CLKPRESCALER_CLK_DIV(x, v) (HW_EWM_CLKPRESCALER_WR(x, v))
/*@}*/
/*******************************************************************************
* hw_ewm_t - module struct
******************************************************************************/
/*!
* @brief All EWM module registers.
*/
#pragma pack(1)
typedef struct _hw_ewm
{
__IO hw_ewm_ctrl_t CTRL; /*!< [0x0] Control Register */
__O hw_ewm_serv_t SERV; /*!< [0x1] Service Register */
__IO hw_ewm_cmpl_t CMPL; /*!< [0x2] Compare Low Register */
__IO hw_ewm_cmph_t CMPH; /*!< [0x3] Compare High Register */
uint8_t _reserved0[1];
__IO hw_ewm_clkprescaler_t CLKPRESCALER; /*!< [0x5] Clock Prescaler Register */
} hw_ewm_t;
#pragma pack()
/*! @brief Macro to access all EWM registers. */
/*! @param x EWM module instance base address. */
/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
* use the '&' operator, like <code>&HW_EWM(EWM_BASE)</code>. */
#define HW_EWM(x) (*(hw_ewm_t *)(x))
#endif /* __HW_EWM_REGISTERS_H__ */
/* EOF */

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libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_fb.h Normal file
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@ -0,0 +1,904 @@
/*
** ###################################################################
** Compilers: Keil ARM C/C++ Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
** Version: rev. 2.5, 2014-05-06
** Build: b140604
**
** Abstract:
** Extension to the CMSIS register access layer header.
**
** Copyright (c) 2014 Freescale Semiconductor, Inc.
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** Revisions:
** - rev. 1.0 (2013-07-23)
** Initial version.
** - rev. 1.1 (2013-09-17)
** RM rev. 0.4 update.
** - rev. 2.0 (2013-10-29)
** Register accessor macros added to the memory map.
** Symbols for Processor Expert memory map compatibility added to the memory map.
** Startup file for gcc has been updated according to CMSIS 3.2.
** System initialization updated.
** - rev. 2.1 (2013-10-30)
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
** - rev. 2.2 (2013-12-20)
** Update according to reference manual rev. 0.6,
** - rev. 2.3 (2014-01-13)
** Update according to reference manual rev. 0.61,
** - rev. 2.4 (2014-02-10)
** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
** - rev. 2.5 (2014-05-06)
** Update according to reference manual rev. 1.0,
** Update of system and startup files.
** Module access macro module_BASES replaced by module_BASE_PTRS.
**
** ###################################################################
*/
/*
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
*
* This file was generated automatically and any changes may be lost.
*/
#ifndef __HW_FB_REGISTERS_H__
#define __HW_FB_REGISTERS_H__
#include "MK22F51212.h"
#include "fsl_bitaccess.h"
/*
* MK22F51212 FB
*
* FlexBus external bus interface
*
* Registers defined in this header file:
* - HW_FB_CSARn - Chip Select Address Register
* - HW_FB_CSMRn - Chip Select Mask Register
* - HW_FB_CSCRn - Chip Select Control Register
* - HW_FB_CSPMCR - Chip Select port Multiplexing Control Register
*
* - hw_fb_t - Struct containing all module registers.
*/
#define HW_FB_INSTANCE_COUNT (1U) /*!< Number of instances of the FB module. */
/*******************************************************************************
* HW_FB_CSARn - Chip Select Address Register
******************************************************************************/
/*!
* @brief HW_FB_CSARn - Chip Select Address Register (RW)
*
* Reset value: 0x00000000U
*
* Specifies the associated chip-select's base address.
*/
typedef union _hw_fb_csarn
{
uint32_t U;
struct _hw_fb_csarn_bitfields
{
uint32_t RESERVED0 : 16; /*!< [15:0] */
uint32_t BA : 16; /*!< [31:16] Base Address */
} B;
} hw_fb_csarn_t;
/*!
* @name Constants and macros for entire FB_CSARn register
*/
/*@{*/
#define HW_FB_CSARn_COUNT (6U)
#define HW_FB_CSARn_ADDR(x, n) ((x) + 0x0U + (0xCU * (n)))
#define HW_FB_CSARn(x, n) (*(__IO hw_fb_csarn_t *) HW_FB_CSARn_ADDR(x, n))
#define HW_FB_CSARn_RD(x, n) (HW_FB_CSARn(x, n).U)
#define HW_FB_CSARn_WR(x, n, v) (HW_FB_CSARn(x, n).U = (v))
#define HW_FB_CSARn_SET(x, n, v) (HW_FB_CSARn_WR(x, n, HW_FB_CSARn_RD(x, n) | (v)))
#define HW_FB_CSARn_CLR(x, n, v) (HW_FB_CSARn_WR(x, n, HW_FB_CSARn_RD(x, n) & ~(v)))
#define HW_FB_CSARn_TOG(x, n, v) (HW_FB_CSARn_WR(x, n, HW_FB_CSARn_RD(x, n) ^ (v)))
/*@}*/
/*
* Constants & macros for individual FB_CSARn bitfields
*/
/*!
* @name Register FB_CSARn, field BA[31:16] (RW)
*
* Defines the base address for memory dedicated to the associated chip-select.
* BA is compared to bits 31-16 on the internal address bus to determine if the
* associated chip-select's memory is being accessed. Because the FlexBus module
* is one of the slaves connected to the crossbar switch, it is only accessible
* within a certain memory range. See the chip memory map for the applicable
* FlexBus "expansion" address range for which the chip-selects can be active. Set the
* CSARn and CSMRn registers appropriately before accessing this region.
*/
/*@{*/
#define BP_FB_CSARn_BA (16U) /*!< Bit position for FB_CSARn_BA. */
#define BM_FB_CSARn_BA (0xFFFF0000U) /*!< Bit mask for FB_CSARn_BA. */
#define BS_FB_CSARn_BA (16U) /*!< Bit field size in bits for FB_CSARn_BA. */
/*! @brief Read current value of the FB_CSARn_BA field. */
#define BR_FB_CSARn_BA(x, n) (HW_FB_CSARn(x, n).B.BA)
/*! @brief Format value for bitfield FB_CSARn_BA. */
#define BF_FB_CSARn_BA(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSARn_BA) & BM_FB_CSARn_BA)
/*! @brief Set the BA field to a new value. */
#define BW_FB_CSARn_BA(x, n, v) (HW_FB_CSARn_WR(x, n, (HW_FB_CSARn_RD(x, n) & ~BM_FB_CSARn_BA) | BF_FB_CSARn_BA(v)))
/*@}*/
/*******************************************************************************
* HW_FB_CSMRn - Chip Select Mask Register
******************************************************************************/
/*!
* @brief HW_FB_CSMRn - Chip Select Mask Register (RW)
*
* Reset value: 0x00000000U
*
* Specifies the address mask and allowable access types for the associated
* chip-select.
*/
typedef union _hw_fb_csmrn
{
uint32_t U;
struct _hw_fb_csmrn_bitfields
{
uint32_t V : 1; /*!< [0] Valid */
uint32_t RESERVED0 : 7; /*!< [7:1] */
uint32_t WP : 1; /*!< [8] Write Protect */
uint32_t RESERVED1 : 7; /*!< [15:9] */
uint32_t BAM : 16; /*!< [31:16] Base Address Mask */
} B;
} hw_fb_csmrn_t;
/*!
* @name Constants and macros for entire FB_CSMRn register
*/
/*@{*/
#define HW_FB_CSMRn_COUNT (6U)
#define HW_FB_CSMRn_ADDR(x, n) ((x) + 0x4U + (0xCU * (n)))
#define HW_FB_CSMRn(x, n) (*(__IO hw_fb_csmrn_t *) HW_FB_CSMRn_ADDR(x, n))
#define HW_FB_CSMRn_RD(x, n) (HW_FB_CSMRn(x, n).U)
#define HW_FB_CSMRn_WR(x, n, v) (HW_FB_CSMRn(x, n).U = (v))
#define HW_FB_CSMRn_SET(x, n, v) (HW_FB_CSMRn_WR(x, n, HW_FB_CSMRn_RD(x, n) | (v)))
#define HW_FB_CSMRn_CLR(x, n, v) (HW_FB_CSMRn_WR(x, n, HW_FB_CSMRn_RD(x, n) & ~(v)))
#define HW_FB_CSMRn_TOG(x, n, v) (HW_FB_CSMRn_WR(x, n, HW_FB_CSMRn_RD(x, n) ^ (v)))
/*@}*/
/*
* Constants & macros for individual FB_CSMRn bitfields
*/
/*!
* @name Register FB_CSMRn, field V[0] (RW)
*
* Specifies whether the corresponding CSAR, CSMR, and CSCR contents are valid.
* Programmed chip-selects do not assert until the V bit is 1b (except for
* FB_CS0, which acts as the global chip-select). At reset, FB_CS0 will fire for any
* access to the FlexBus memory region. CSMR0[V] must be set as part of the chip
* select initialization sequence to allow other chip selects to function as
* programmed.
*
* Values:
* - 0 - Chip-select is invalid.
* - 1 - Chip-select is valid.
*/
/*@{*/
#define BP_FB_CSMRn_V (0U) /*!< Bit position for FB_CSMRn_V. */
#define BM_FB_CSMRn_V (0x00000001U) /*!< Bit mask for FB_CSMRn_V. */
#define BS_FB_CSMRn_V (1U) /*!< Bit field size in bits for FB_CSMRn_V. */
/*! @brief Read current value of the FB_CSMRn_V field. */
#define BR_FB_CSMRn_V(x, n) (BITBAND_ACCESS32(HW_FB_CSMRn_ADDR(x, n), BP_FB_CSMRn_V))
/*! @brief Format value for bitfield FB_CSMRn_V. */
#define BF_FB_CSMRn_V(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSMRn_V) & BM_FB_CSMRn_V)
/*! @brief Set the V field to a new value. */
#define BW_FB_CSMRn_V(x, n, v) (BITBAND_ACCESS32(HW_FB_CSMRn_ADDR(x, n), BP_FB_CSMRn_V) = (v))
/*@}*/
/*!
* @name Register FB_CSMRn, field WP[8] (RW)
*
* Controls write accesses to the address range in the corresponding CSAR.
*
* Values:
* - 0 - Write accesses are allowed.
* - 1 - Write accesses are not allowed. Attempting to write to the range of
* addresses for which the WP bit is set results in a bus error termination of
* the internal cycle and no external cycle.
*/
/*@{*/
#define BP_FB_CSMRn_WP (8U) /*!< Bit position for FB_CSMRn_WP. */
#define BM_FB_CSMRn_WP (0x00000100U) /*!< Bit mask for FB_CSMRn_WP. */
#define BS_FB_CSMRn_WP (1U) /*!< Bit field size in bits for FB_CSMRn_WP. */
/*! @brief Read current value of the FB_CSMRn_WP field. */
#define BR_FB_CSMRn_WP(x, n) (BITBAND_ACCESS32(HW_FB_CSMRn_ADDR(x, n), BP_FB_CSMRn_WP))
/*! @brief Format value for bitfield FB_CSMRn_WP. */
#define BF_FB_CSMRn_WP(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSMRn_WP) & BM_FB_CSMRn_WP)
/*! @brief Set the WP field to a new value. */
#define BW_FB_CSMRn_WP(x, n, v) (BITBAND_ACCESS32(HW_FB_CSMRn_ADDR(x, n), BP_FB_CSMRn_WP) = (v))
/*@}*/
/*!
* @name Register FB_CSMRn, field BAM[31:16] (RW)
*
* Defines the associated chip-select's block size by masking address bits.
*
* Values:
* - 0 - The corresponding address bit in CSAR is used in the chip-select decode.
* - 1 - The corresponding address bit in CSAR is a don't care in the
* chip-select decode.
*/
/*@{*/
#define BP_FB_CSMRn_BAM (16U) /*!< Bit position for FB_CSMRn_BAM. */
#define BM_FB_CSMRn_BAM (0xFFFF0000U) /*!< Bit mask for FB_CSMRn_BAM. */
#define BS_FB_CSMRn_BAM (16U) /*!< Bit field size in bits for FB_CSMRn_BAM. */
/*! @brief Read current value of the FB_CSMRn_BAM field. */
#define BR_FB_CSMRn_BAM(x, n) (HW_FB_CSMRn(x, n).B.BAM)
/*! @brief Format value for bitfield FB_CSMRn_BAM. */
#define BF_FB_CSMRn_BAM(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSMRn_BAM) & BM_FB_CSMRn_BAM)
/*! @brief Set the BAM field to a new value. */
#define BW_FB_CSMRn_BAM(x, n, v) (HW_FB_CSMRn_WR(x, n, (HW_FB_CSMRn_RD(x, n) & ~BM_FB_CSMRn_BAM) | BF_FB_CSMRn_BAM(v)))
/*@}*/
/*******************************************************************************
* HW_FB_CSCRn - Chip Select Control Register
******************************************************************************/
/*!
* @brief HW_FB_CSCRn - Chip Select Control Register (RW)
*
* Reset value: 0x003FFC00U
*
* Controls the auto-acknowledge, address setup and hold times, port size, burst
* capability, and number of wait states for the associated chip select. To
* support the global chip-select (FB_CS0), the CSCR0 reset values differ from the
* other CSCRs. The reset value of CSCR0 is as follows: Bits 31-24 are 0b Bit 23-3
* are chip-dependent Bits 3-0 are 0b See the chip configuration details for your
* particular chip for information on the exact CSCR0 reset value.
*/
typedef union _hw_fb_cscrn
{
uint32_t U;
struct _hw_fb_cscrn_bitfields
{
uint32_t RESERVED0 : 3; /*!< [2:0] */
uint32_t BSTW : 1; /*!< [3] Burst-Write Enable */
uint32_t BSTR : 1; /*!< [4] Burst-Read Enable */
uint32_t BEM : 1; /*!< [5] Byte-Enable Mode */
uint32_t PS : 2; /*!< [7:6] Port Size */
uint32_t AA : 1; /*!< [8] Auto-Acknowledge Enable */
uint32_t BLS : 1; /*!< [9] Byte-Lane Shift */
uint32_t WS : 6; /*!< [15:10] Wait States */
uint32_t WRAH : 2; /*!< [17:16] Write Address Hold or Deselect */
uint32_t RDAH : 2; /*!< [19:18] Read Address Hold or Deselect */
uint32_t ASET : 2; /*!< [21:20] Address Setup */
uint32_t EXTS : 1; /*!< [22] */
uint32_t SWSEN : 1; /*!< [23] Secondary Wait State Enable */
uint32_t RESERVED1 : 2; /*!< [25:24] */
uint32_t SWS : 6; /*!< [31:26] Secondary Wait States */
} B;
} hw_fb_cscrn_t;
/*!
* @name Constants and macros for entire FB_CSCRn register
*/
/*@{*/
#define HW_FB_CSCRn_COUNT (6U)
#define HW_FB_CSCRn_ADDR(x, n) ((x) + 0x8U + (0xCU * (n)))
#define HW_FB_CSCRn(x, n) (*(__IO hw_fb_cscrn_t *) HW_FB_CSCRn_ADDR(x, n))
#define HW_FB_CSCRn_RD(x, n) (HW_FB_CSCRn(x, n).U)
#define HW_FB_CSCRn_WR(x, n, v) (HW_FB_CSCRn(x, n).U = (v))
#define HW_FB_CSCRn_SET(x, n, v) (HW_FB_CSCRn_WR(x, n, HW_FB_CSCRn_RD(x, n) | (v)))
#define HW_FB_CSCRn_CLR(x, n, v) (HW_FB_CSCRn_WR(x, n, HW_FB_CSCRn_RD(x, n) & ~(v)))
#define HW_FB_CSCRn_TOG(x, n, v) (HW_FB_CSCRn_WR(x, n, HW_FB_CSCRn_RD(x, n) ^ (v)))
/*@}*/
/*
* Constants & macros for individual FB_CSCRn bitfields
*/
/*!
* @name Register FB_CSCRn, field BSTW[3] (RW)
*
* Specifies whether burst writes are enabled for memory associated with each
* chip select.
*
* Values:
* - 0 - Disabled. Data exceeding the specified port size is broken into
* individual, port-sized, non-burst writes. For example, a 32-bit write to an 8-bit
* port takes four byte writes.
* - 1 - Enabled. Enables burst write of data larger than the specified port
* size, including 32-bit writes to 8- and 16-bit ports, 16-bit writes to 8-bit
* ports, and line writes to 8-, 16-, and 32-bit ports.
*/
/*@{*/
#define BP_FB_CSCRn_BSTW (3U) /*!< Bit position for FB_CSCRn_BSTW. */
#define BM_FB_CSCRn_BSTW (0x00000008U) /*!< Bit mask for FB_CSCRn_BSTW. */
#define BS_FB_CSCRn_BSTW (1U) /*!< Bit field size in bits for FB_CSCRn_BSTW. */
/*! @brief Read current value of the FB_CSCRn_BSTW field. */
#define BR_FB_CSCRn_BSTW(x, n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BSTW))
/*! @brief Format value for bitfield FB_CSCRn_BSTW. */
#define BF_FB_CSCRn_BSTW(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_BSTW) & BM_FB_CSCRn_BSTW)
/*! @brief Set the BSTW field to a new value. */
#define BW_FB_CSCRn_BSTW(x, n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BSTW) = (v))
/*@}*/
/*!
* @name Register FB_CSCRn, field BSTR[4] (RW)
*
* Specifies whether burst reads are enabled for memory associated with each
* chip select.
*
* Values:
* - 0 - Disabled. Data exceeding the specified port size is broken into
* individual, port-sized, non-burst reads. For example, a 32-bit read from an 8-bit
* port is broken into four 8-bit reads.
* - 1 - Enabled. Enables data burst reads larger than the specified port size,
* including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit
* ports, and line reads from 8-, 16-, and 32-bit ports.
*/
/*@{*/
#define BP_FB_CSCRn_BSTR (4U) /*!< Bit position for FB_CSCRn_BSTR. */
#define BM_FB_CSCRn_BSTR (0x00000010U) /*!< Bit mask for FB_CSCRn_BSTR. */
#define BS_FB_CSCRn_BSTR (1U) /*!< Bit field size in bits for FB_CSCRn_BSTR. */
/*! @brief Read current value of the FB_CSCRn_BSTR field. */
#define BR_FB_CSCRn_BSTR(x, n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BSTR))
/*! @brief Format value for bitfield FB_CSCRn_BSTR. */
#define BF_FB_CSCRn_BSTR(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_BSTR) & BM_FB_CSCRn_BSTR)
/*! @brief Set the BSTR field to a new value. */
#define BW_FB_CSCRn_BSTR(x, n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BSTR) = (v))
/*@}*/
/*!
* @name Register FB_CSCRn, field BEM[5] (RW)
*
* Specifies whether the corresponding FB_BE is asserted for read accesses.
* Certain memories have byte enables that must be asserted during reads and writes.
* Write 1b to the BEM bit in the relevant CSCR to provide the appropriate mode
* of byte enable support for these SRAMs.
*
* Values:
* - 0 - FB_BE is asserted for data write only.
* - 1 - FB_BE is asserted for data read and write accesses.
*/
/*@{*/
#define BP_FB_CSCRn_BEM (5U) /*!< Bit position for FB_CSCRn_BEM. */
#define BM_FB_CSCRn_BEM (0x00000020U) /*!< Bit mask for FB_CSCRn_BEM. */
#define BS_FB_CSCRn_BEM (1U) /*!< Bit field size in bits for FB_CSCRn_BEM. */
/*! @brief Read current value of the FB_CSCRn_BEM field. */
#define BR_FB_CSCRn_BEM(x, n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BEM))
/*! @brief Format value for bitfield FB_CSCRn_BEM. */
#define BF_FB_CSCRn_BEM(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_BEM) & BM_FB_CSCRn_BEM)
/*! @brief Set the BEM field to a new value. */
#define BW_FB_CSCRn_BEM(x, n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BEM) = (v))
/*@}*/
/*!
* @name Register FB_CSCRn, field PS[7:6] (RW)
*
* Specifies the data port width of the associated chip-select, and determines
* where data is driven during write cycles and where data is sampled during read
* cycles.
*
* Values:
* - 00 - 32-bit port size. Valid data is sampled and driven on FB_D[31:0].
* - 01 - 8-bit port size. Valid data is sampled and driven on FB_D[31:24] when
* BLS is 0b, or FB_D[7:0] when BLS is 1b.
*/
/*@{*/
#define BP_FB_CSCRn_PS (6U) /*!< Bit position for FB_CSCRn_PS. */
#define BM_FB_CSCRn_PS (0x000000C0U) /*!< Bit mask for FB_CSCRn_PS. */
#define BS_FB_CSCRn_PS (2U) /*!< Bit field size in bits for FB_CSCRn_PS. */
/*! @brief Read current value of the FB_CSCRn_PS field. */
#define BR_FB_CSCRn_PS(x, n) (HW_FB_CSCRn(x, n).B.PS)
/*! @brief Format value for bitfield FB_CSCRn_PS. */
#define BF_FB_CSCRn_PS(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_PS) & BM_FB_CSCRn_PS)
/*! @brief Set the PS field to a new value. */
#define BW_FB_CSCRn_PS(x, n, v) (HW_FB_CSCRn_WR(x, n, (HW_FB_CSCRn_RD(x, n) & ~BM_FB_CSCRn_PS) | BF_FB_CSCRn_PS(v)))
/*@}*/
/*!
* @name Register FB_CSCRn, field AA[8] (RW)
*
* Asserts the internal transfer acknowledge for accesses specified by the
* chip-select address. If AA is 1b for a corresponding FB_CSn and the external system
* asserts an external FB_TA before the wait-state countdown asserts the
* internal FB_TA, the cycle is terminated. Burst cycles increment the address bus
* between each internal termination. This field must be 1b if CSPMCR disables FB_TA.
*
* Values:
* - 0 - Disabled. No internal transfer acknowledge is asserted and the cycle is
* terminated externally.
* - 1 - Enabled. Internal transfer acknowledge is asserted as specified by WS.
*/
/*@{*/
#define BP_FB_CSCRn_AA (8U) /*!< Bit position for FB_CSCRn_AA. */
#define BM_FB_CSCRn_AA (0x00000100U) /*!< Bit mask for FB_CSCRn_AA. */
#define BS_FB_CSCRn_AA (1U) /*!< Bit field size in bits for FB_CSCRn_AA. */
/*! @brief Read current value of the FB_CSCRn_AA field. */
#define BR_FB_CSCRn_AA(x, n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_AA))
/*! @brief Format value for bitfield FB_CSCRn_AA. */
#define BF_FB_CSCRn_AA(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_AA) & BM_FB_CSCRn_AA)
/*! @brief Set the AA field to a new value. */
#define BW_FB_CSCRn_AA(x, n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_AA) = (v))
/*@}*/
/*!
* @name Register FB_CSCRn, field BLS[9] (RW)
*
* Specifies if data on FB_AD appears left-aligned or right-aligned during the
* data phase of a FlexBus access.
*
* Values:
* - 0 - Not shifted. Data is left-aligned on FB_AD.
* - 1 - Shifted. Data is right-aligned on FB_AD.
*/
/*@{*/
#define BP_FB_CSCRn_BLS (9U) /*!< Bit position for FB_CSCRn_BLS. */
#define BM_FB_CSCRn_BLS (0x00000200U) /*!< Bit mask for FB_CSCRn_BLS. */
#define BS_FB_CSCRn_BLS (1U) /*!< Bit field size in bits for FB_CSCRn_BLS. */
/*! @brief Read current value of the FB_CSCRn_BLS field. */
#define BR_FB_CSCRn_BLS(x, n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BLS))
/*! @brief Format value for bitfield FB_CSCRn_BLS. */
#define BF_FB_CSCRn_BLS(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_BLS) & BM_FB_CSCRn_BLS)
/*! @brief Set the BLS field to a new value. */
#define BW_FB_CSCRn_BLS(x, n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BLS) = (v))
/*@}*/
/*!
* @name Register FB_CSCRn, field WS[15:10] (RW)
*
* Specifies the number of wait states inserted after FlexBus asserts the
* associated chip-select and before an internal transfer acknowledge is generated (WS
* = 00h inserts 0 wait states, ..., WS = 3Fh inserts 63 wait states).
*/
/*@{*/
#define BP_FB_CSCRn_WS (10U) /*!< Bit position for FB_CSCRn_WS. */
#define BM_FB_CSCRn_WS (0x0000FC00U) /*!< Bit mask for FB_CSCRn_WS. */
#define BS_FB_CSCRn_WS (6U) /*!< Bit field size in bits for FB_CSCRn_WS. */
/*! @brief Read current value of the FB_CSCRn_WS field. */
#define BR_FB_CSCRn_WS(x, n) (HW_FB_CSCRn(x, n).B.WS)
/*! @brief Format value for bitfield FB_CSCRn_WS. */
#define BF_FB_CSCRn_WS(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_WS) & BM_FB_CSCRn_WS)
/*! @brief Set the WS field to a new value. */
#define BW_FB_CSCRn_WS(x, n, v) (HW_FB_CSCRn_WR(x, n, (HW_FB_CSCRn_RD(x, n) & ~BM_FB_CSCRn_WS) | BF_FB_CSCRn_WS(v)))
/*@}*/
/*!
* @name Register FB_CSCRn, field WRAH[17:16] (RW)
*
* Controls the address, data, and attribute hold time after the termination of
* a write cycle that hits in the associated chip-select's address space. The
* hold time applies only at the end of a transfer. Therefore, during a burst
* transfer or a transfer to a port size smaller than the transfer size, the hold time
* is only added after the last bus cycle.
*
* Values:
* - 00 - 1 cycle (default for all but FB_CS0 )
* - 01 - 2 cycles
* - 10 - 3 cycles
* - 11 - 4 cycles (default for FB_CS0 )
*/
/*@{*/
#define BP_FB_CSCRn_WRAH (16U) /*!< Bit position for FB_CSCRn_WRAH. */
#define BM_FB_CSCRn_WRAH (0x00030000U) /*!< Bit mask for FB_CSCRn_WRAH. */
#define BS_FB_CSCRn_WRAH (2U) /*!< Bit field size in bits for FB_CSCRn_WRAH. */
/*! @brief Read current value of the FB_CSCRn_WRAH field. */
#define BR_FB_CSCRn_WRAH(x, n) (HW_FB_CSCRn(x, n).B.WRAH)
/*! @brief Format value for bitfield FB_CSCRn_WRAH. */
#define BF_FB_CSCRn_WRAH(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_WRAH) & BM_FB_CSCRn_WRAH)
/*! @brief Set the WRAH field to a new value. */
#define BW_FB_CSCRn_WRAH(x, n, v) (HW_FB_CSCRn_WR(x, n, (HW_FB_CSCRn_RD(x, n) & ~BM_FB_CSCRn_WRAH) | BF_FB_CSCRn_WRAH(v)))
/*@}*/
/*!
* @name Register FB_CSCRn, field RDAH[19:18] (RW)
*
* Controls the address and attribute hold time after the termination during a
* read cycle that hits in the associated chip-select's address space. The hold
* time applies only at the end of a transfer. Therefore, during a burst transfer
* or a transfer to a port size smaller than the transfer size, the hold time is
* only added after the last bus cycle. The number of cycles the address and
* attributes are held after FB_CSn deassertion depends on the value of the AA bit.
*
* Values:
* - 00 - When AA is 0b, 1 cycle. When AA is 1b, 0 cycles.
* - 01 - When AA is 0b, 2 cycles. When AA is 1b, 1 cycle.
* - 10 - When AA is 0b, 3 cycles. When AA is 1b, 2 cycles.
* - 11 - When AA is 0b, 4 cycles. When AA is 1b, 3 cycles.
*/
/*@{*/
#define BP_FB_CSCRn_RDAH (18U) /*!< Bit position for FB_CSCRn_RDAH. */
#define BM_FB_CSCRn_RDAH (0x000C0000U) /*!< Bit mask for FB_CSCRn_RDAH. */
#define BS_FB_CSCRn_RDAH (2U) /*!< Bit field size in bits for FB_CSCRn_RDAH. */
/*! @brief Read current value of the FB_CSCRn_RDAH field. */
#define BR_FB_CSCRn_RDAH(x, n) (HW_FB_CSCRn(x, n).B.RDAH)
/*! @brief Format value for bitfield FB_CSCRn_RDAH. */
#define BF_FB_CSCRn_RDAH(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_RDAH) & BM_FB_CSCRn_RDAH)
/*! @brief Set the RDAH field to a new value. */
#define BW_FB_CSCRn_RDAH(x, n, v) (HW_FB_CSCRn_WR(x, n, (HW_FB_CSCRn_RD(x, n) & ~BM_FB_CSCRn_RDAH) | BF_FB_CSCRn_RDAH(v)))
/*@}*/
/*!
* @name Register FB_CSCRn, field ASET[21:20] (RW)
*
* Controls when the chip-select is asserted with respect to assertion of a
* valid address and attributes.
*
* Values:
* - 00 - Assert FB_CSn on the first rising clock edge after the address is
* asserted (default for all but FB_CS0 ).
* - 01 - Assert FB_CSn on the second rising clock edge after the address is
* asserted.
* - 10 - Assert FB_CSn on the third rising clock edge after the address is
* asserted.
* - 11 - Assert FB_CSn on the fourth rising clock edge after the address is
* asserted (default for FB_CS0 ).
*/
/*@{*/
#define BP_FB_CSCRn_ASET (20U) /*!< Bit position for FB_CSCRn_ASET. */
#define BM_FB_CSCRn_ASET (0x00300000U) /*!< Bit mask for FB_CSCRn_ASET. */
#define BS_FB_CSCRn_ASET (2U) /*!< Bit field size in bits for FB_CSCRn_ASET. */
/*! @brief Read current value of the FB_CSCRn_ASET field. */
#define BR_FB_CSCRn_ASET(x, n) (HW_FB_CSCRn(x, n).B.ASET)
/*! @brief Format value for bitfield FB_CSCRn_ASET. */
#define BF_FB_CSCRn_ASET(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_ASET) & BM_FB_CSCRn_ASET)
/*! @brief Set the ASET field to a new value. */
#define BW_FB_CSCRn_ASET(x, n, v) (HW_FB_CSCRn_WR(x, n, (HW_FB_CSCRn_RD(x, n) & ~BM_FB_CSCRn_ASET) | BF_FB_CSCRn_ASET(v)))
/*@}*/
/*!
* @name Register FB_CSCRn, field EXTS[22] (RW)
*
* Extended Transfer Start/Extended Address Latch Enable Controls how long FB_TS
* /FB_ALE is asserted.
*
* Values:
* - 0 - Disabled. FB_TS /FB_ALE asserts for one bus clock cycle.
* - 1 - Enabled. FB_TS /FB_ALE remains asserted until the first positive clock
* edge after FB_CSn asserts.
*/
/*@{*/
#define BP_FB_CSCRn_EXTS (22U) /*!< Bit position for FB_CSCRn_EXTS. */
#define BM_FB_CSCRn_EXTS (0x00400000U) /*!< Bit mask for FB_CSCRn_EXTS. */
#define BS_FB_CSCRn_EXTS (1U) /*!< Bit field size in bits for FB_CSCRn_EXTS. */
/*! @brief Read current value of the FB_CSCRn_EXTS field. */
#define BR_FB_CSCRn_EXTS(x, n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_EXTS))
/*! @brief Format value for bitfield FB_CSCRn_EXTS. */
#define BF_FB_CSCRn_EXTS(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_EXTS) & BM_FB_CSCRn_EXTS)
/*! @brief Set the EXTS field to a new value. */
#define BW_FB_CSCRn_EXTS(x, n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_EXTS) = (v))
/*@}*/
/*!
* @name Register FB_CSCRn, field SWSEN[23] (RW)
*
* Values:
* - 0 - Disabled. A number of wait states (specified by WS) are inserted before
* an internal transfer acknowledge is generated for all transfers.
* - 1 - Enabled. A number of wait states (specified by SWS) are inserted before
* an internal transfer acknowledge is generated for burst transfer
* secondary terminations.
*/
/*@{*/
#define BP_FB_CSCRn_SWSEN (23U) /*!< Bit position for FB_CSCRn_SWSEN. */
#define BM_FB_CSCRn_SWSEN (0x00800000U) /*!< Bit mask for FB_CSCRn_SWSEN. */
#define BS_FB_CSCRn_SWSEN (1U) /*!< Bit field size in bits for FB_CSCRn_SWSEN. */
/*! @brief Read current value of the FB_CSCRn_SWSEN field. */
#define BR_FB_CSCRn_SWSEN(x, n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_SWSEN))
/*! @brief Format value for bitfield FB_CSCRn_SWSEN. */
#define BF_FB_CSCRn_SWSEN(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_SWSEN) & BM_FB_CSCRn_SWSEN)
/*! @brief Set the SWSEN field to a new value. */
#define BW_FB_CSCRn_SWSEN(x, n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_SWSEN) = (v))
/*@}*/
/*!
* @name Register FB_CSCRn, field SWS[31:26] (RW)
*
* Used only when the SWSEN bit is 1b. Specifies the number of wait states
* inserted before an internal transfer acknowledge is generated for a burst transfer
* (except for the first termination, which is controlled by WS).
*/
/*@{*/
#define BP_FB_CSCRn_SWS (26U) /*!< Bit position for FB_CSCRn_SWS. */
#define BM_FB_CSCRn_SWS (0xFC000000U) /*!< Bit mask for FB_CSCRn_SWS. */
#define BS_FB_CSCRn_SWS (6U) /*!< Bit field size in bits for FB_CSCRn_SWS. */
/*! @brief Read current value of the FB_CSCRn_SWS field. */
#define BR_FB_CSCRn_SWS(x, n) (HW_FB_CSCRn(x, n).B.SWS)
/*! @brief Format value for bitfield FB_CSCRn_SWS. */
#define BF_FB_CSCRn_SWS(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_SWS) & BM_FB_CSCRn_SWS)
/*! @brief Set the SWS field to a new value. */
#define BW_FB_CSCRn_SWS(x, n, v) (HW_FB_CSCRn_WR(x, n, (HW_FB_CSCRn_RD(x, n) & ~BM_FB_CSCRn_SWS) | BF_FB_CSCRn_SWS(v)))
/*@}*/
/*******************************************************************************
* HW_FB_CSPMCR - Chip Select port Multiplexing Control Register
******************************************************************************/
/*!
* @brief HW_FB_CSPMCR - Chip Select port Multiplexing Control Register (RW)
*
* Reset value: 0x00000000U
*
* Controls the multiplexing of the FlexBus signals. A bus error occurs when you
* do any of the following: Write to a reserved address Write to a reserved
* field in this register, or Access this register using a size other than 32 bits.
*/
typedef union _hw_fb_cspmcr
{
uint32_t U;
struct _hw_fb_cspmcr_bitfields
{
uint32_t RESERVED0 : 12; /*!< [11:0] */
uint32_t GROUP5 : 4; /*!< [15:12] FlexBus Signal Group 5 Multiplex
* control */
uint32_t GROUP4 : 4; /*!< [19:16] FlexBus Signal Group 4 Multiplex
* control */
uint32_t GROUP3 : 4; /*!< [23:20] FlexBus Signal Group 3 Multiplex
* control */
uint32_t GROUP2 : 4; /*!< [27:24] FlexBus Signal Group 2 Multiplex
* control */
uint32_t GROUP1 : 4; /*!< [31:28] FlexBus Signal Group 1 Multiplex
* control */
} B;
} hw_fb_cspmcr_t;
/*!
* @name Constants and macros for entire FB_CSPMCR register
*/
/*@{*/
#define HW_FB_CSPMCR_ADDR(x) ((x) + 0x60U)
#define HW_FB_CSPMCR(x) (*(__IO hw_fb_cspmcr_t *) HW_FB_CSPMCR_ADDR(x))
#define HW_FB_CSPMCR_RD(x) (HW_FB_CSPMCR(x).U)
#define HW_FB_CSPMCR_WR(x, v) (HW_FB_CSPMCR(x).U = (v))
#define HW_FB_CSPMCR_SET(x, v) (HW_FB_CSPMCR_WR(x, HW_FB_CSPMCR_RD(x) | (v)))
#define HW_FB_CSPMCR_CLR(x, v) (HW_FB_CSPMCR_WR(x, HW_FB_CSPMCR_RD(x) & ~(v)))
#define HW_FB_CSPMCR_TOG(x, v) (HW_FB_CSPMCR_WR(x, HW_FB_CSPMCR_RD(x) ^ (v)))
/*@}*/
/*
* Constants & macros for individual FB_CSPMCR bitfields
*/
/*!
* @name Register FB_CSPMCR, field GROUP5[15:12] (RW)
*
* Controls the multiplexing of the FB_TA , FB_CS3 , and FB_BE_7_0 signals. When
* GROUP5 is not 0000b, you must write 1b to the CSCR[AA] bit. Otherwise, the
* bus hangs during a transfer.
*
* Values:
* - 0000 - FB_TA
* - 0001 - FB_CS3 . You must also write 1b to CSCR[AA].
* - 0010 - FB_BE_7_0 . You must also write 1b to CSCR[AA].
*/
/*@{*/
#define BP_FB_CSPMCR_GROUP5 (12U) /*!< Bit position for FB_CSPMCR_GROUP5. */
#define BM_FB_CSPMCR_GROUP5 (0x0000F000U) /*!< Bit mask for FB_CSPMCR_GROUP5. */
#define BS_FB_CSPMCR_GROUP5 (4U) /*!< Bit field size in bits for FB_CSPMCR_GROUP5. */
/*! @brief Read current value of the FB_CSPMCR_GROUP5 field. */
#define BR_FB_CSPMCR_GROUP5(x) (HW_FB_CSPMCR(x).B.GROUP5)
/*! @brief Format value for bitfield FB_CSPMCR_GROUP5. */
#define BF_FB_CSPMCR_GROUP5(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSPMCR_GROUP5) & BM_FB_CSPMCR_GROUP5)
/*! @brief Set the GROUP5 field to a new value. */
#define BW_FB_CSPMCR_GROUP5(x, v) (HW_FB_CSPMCR_WR(x, (HW_FB_CSPMCR_RD(x) & ~BM_FB_CSPMCR_GROUP5) | BF_FB_CSPMCR_GROUP5(v)))
/*@}*/
/*!
* @name Register FB_CSPMCR, field GROUP4[19:16] (RW)
*
* Controls the multiplexing of the FB_TBST , FB_CS2 , and FB_BE_15_8 signals.
*
* Values:
* - 0000 - FB_TBST
* - 0001 - FB_CS2
* - 0010 - FB_BE_15_8
*/
/*@{*/
#define BP_FB_CSPMCR_GROUP4 (16U) /*!< Bit position for FB_CSPMCR_GROUP4. */
#define BM_FB_CSPMCR_GROUP4 (0x000F0000U) /*!< Bit mask for FB_CSPMCR_GROUP4. */
#define BS_FB_CSPMCR_GROUP4 (4U) /*!< Bit field size in bits for FB_CSPMCR_GROUP4. */
/*! @brief Read current value of the FB_CSPMCR_GROUP4 field. */
#define BR_FB_CSPMCR_GROUP4(x) (HW_FB_CSPMCR(x).B.GROUP4)
/*! @brief Format value for bitfield FB_CSPMCR_GROUP4. */
#define BF_FB_CSPMCR_GROUP4(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSPMCR_GROUP4) & BM_FB_CSPMCR_GROUP4)
/*! @brief Set the GROUP4 field to a new value. */
#define BW_FB_CSPMCR_GROUP4(x, v) (HW_FB_CSPMCR_WR(x, (HW_FB_CSPMCR_RD(x) & ~BM_FB_CSPMCR_GROUP4) | BF_FB_CSPMCR_GROUP4(v)))
/*@}*/
/*!
* @name Register FB_CSPMCR, field GROUP3[23:20] (RW)
*
* Controls the multiplexing of the FB_CS5 , FB_TSIZ1, and FB_BE_23_16 signals.
*
* Values:
* - 0000 - FB_CS5
* - 0001 - FB_TSIZ1
* - 0010 - FB_BE_23_16
*/
/*@{*/
#define BP_FB_CSPMCR_GROUP3 (20U) /*!< Bit position for FB_CSPMCR_GROUP3. */
#define BM_FB_CSPMCR_GROUP3 (0x00F00000U) /*!< Bit mask for FB_CSPMCR_GROUP3. */
#define BS_FB_CSPMCR_GROUP3 (4U) /*!< Bit field size in bits for FB_CSPMCR_GROUP3. */
/*! @brief Read current value of the FB_CSPMCR_GROUP3 field. */
#define BR_FB_CSPMCR_GROUP3(x) (HW_FB_CSPMCR(x).B.GROUP3)
/*! @brief Format value for bitfield FB_CSPMCR_GROUP3. */
#define BF_FB_CSPMCR_GROUP3(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSPMCR_GROUP3) & BM_FB_CSPMCR_GROUP3)
/*! @brief Set the GROUP3 field to a new value. */
#define BW_FB_CSPMCR_GROUP3(x, v) (HW_FB_CSPMCR_WR(x, (HW_FB_CSPMCR_RD(x) & ~BM_FB_CSPMCR_GROUP3) | BF_FB_CSPMCR_GROUP3(v)))
/*@}*/
/*!
* @name Register FB_CSPMCR, field GROUP2[27:24] (RW)
*
* Controls the multiplexing of the FB_CS4 , FB_TSIZ0, and FB_BE_31_24 signals.
*
* Values:
* - 0000 - FB_CS4
* - 0001 - FB_TSIZ0
* - 0010 - FB_BE_31_24
*/
/*@{*/
#define BP_FB_CSPMCR_GROUP2 (24U) /*!< Bit position for FB_CSPMCR_GROUP2. */
#define BM_FB_CSPMCR_GROUP2 (0x0F000000U) /*!< Bit mask for FB_CSPMCR_GROUP2. */
#define BS_FB_CSPMCR_GROUP2 (4U) /*!< Bit field size in bits for FB_CSPMCR_GROUP2. */
/*! @brief Read current value of the FB_CSPMCR_GROUP2 field. */
#define BR_FB_CSPMCR_GROUP2(x) (HW_FB_CSPMCR(x).B.GROUP2)
/*! @brief Format value for bitfield FB_CSPMCR_GROUP2. */
#define BF_FB_CSPMCR_GROUP2(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSPMCR_GROUP2) & BM_FB_CSPMCR_GROUP2)
/*! @brief Set the GROUP2 field to a new value. */
#define BW_FB_CSPMCR_GROUP2(x, v) (HW_FB_CSPMCR_WR(x, (HW_FB_CSPMCR_RD(x) & ~BM_FB_CSPMCR_GROUP2) | BF_FB_CSPMCR_GROUP2(v)))
/*@}*/
/*!
* @name Register FB_CSPMCR, field GROUP1[31:28] (RW)
*
* Controls the multiplexing of the FB_ALE, FB_CS1 , and FB_TS signals.
*
* Values:
* - 0000 - FB_ALE
* - 0001 - FB_CS1
* - 0010 - FB_TS
*/
/*@{*/
#define BP_FB_CSPMCR_GROUP1 (28U) /*!< Bit position for FB_CSPMCR_GROUP1. */
#define BM_FB_CSPMCR_GROUP1 (0xF0000000U) /*!< Bit mask for FB_CSPMCR_GROUP1. */
#define BS_FB_CSPMCR_GROUP1 (4U) /*!< Bit field size in bits for FB_CSPMCR_GROUP1. */
/*! @brief Read current value of the FB_CSPMCR_GROUP1 field. */
#define BR_FB_CSPMCR_GROUP1(x) (HW_FB_CSPMCR(x).B.GROUP1)
/*! @brief Format value for bitfield FB_CSPMCR_GROUP1. */
#define BF_FB_CSPMCR_GROUP1(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSPMCR_GROUP1) & BM_FB_CSPMCR_GROUP1)
/*! @brief Set the GROUP1 field to a new value. */
#define BW_FB_CSPMCR_GROUP1(x, v) (HW_FB_CSPMCR_WR(x, (HW_FB_CSPMCR_RD(x) & ~BM_FB_CSPMCR_GROUP1) | BF_FB_CSPMCR_GROUP1(v)))
/*@}*/
/*******************************************************************************
* hw_fb_t - module struct
******************************************************************************/
/*!
* @brief All FB module registers.
*/
#pragma pack(1)
typedef struct _hw_fb
{
struct {
__IO hw_fb_csarn_t CSARn; /*!< [0x0] Chip Select Address Register */
__IO hw_fb_csmrn_t CSMRn; /*!< [0x4] Chip Select Mask Register */
__IO hw_fb_cscrn_t CSCRn; /*!< [0x8] Chip Select Control Register */
} CS[6];
uint8_t _reserved0[24];
__IO hw_fb_cspmcr_t CSPMCR; /*!< [0x60] Chip Select port Multiplexing Control Register */
} hw_fb_t;
#pragma pack()
/*! @brief Macro to access all FB registers. */
/*! @param x FB module instance base address. */
/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
* use the '&' operator, like <code>&HW_FB(FB_BASE)</code>. */
#define HW_FB(x) (*(hw_fb_t *)(x))
#endif /* __HW_FB_REGISTERS_H__ */
/* EOF */

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/*
** ###################################################################
** Compilers: Keil ARM C/C++ Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
** Version: rev. 2.5, 2014-05-06
** Build: b140604
**
** Abstract:
** Extension to the CMSIS register access layer header.
**
** Copyright (c) 2014 Freescale Semiconductor, Inc.
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** Revisions:
** - rev. 1.0 (2013-07-23)
** Initial version.
** - rev. 1.1 (2013-09-17)
** RM rev. 0.4 update.
** - rev. 2.0 (2013-10-29)
** Register accessor macros added to the memory map.
** Symbols for Processor Expert memory map compatibility added to the memory map.
** Startup file for gcc has been updated according to CMSIS 3.2.
** System initialization updated.
** - rev. 2.1 (2013-10-30)
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
** - rev. 2.2 (2013-12-20)
** Update according to reference manual rev. 0.6,
** - rev. 2.3 (2014-01-13)
** Update according to reference manual rev. 0.61,
** - rev. 2.4 (2014-02-10)
** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
** - rev. 2.5 (2014-05-06)
** Update according to reference manual rev. 1.0,
** Update of system and startup files.
** Module access macro module_BASES replaced by module_BASE_PTRS.
**
** ###################################################################
*/
/*
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
*
* This file was generated automatically and any changes may be lost.
*/
#ifndef __HW_GPIO_REGISTERS_H__
#define __HW_GPIO_REGISTERS_H__
#include "MK22F51212.h"
#include "fsl_bitaccess.h"
/*
* MK22F51212 GPIO
*
* General Purpose Input/Output
*
* Registers defined in this header file:
* - HW_GPIO_PDOR - Port Data Output Register
* - HW_GPIO_PSOR - Port Set Output Register
* - HW_GPIO_PCOR - Port Clear Output Register
* - HW_GPIO_PTOR - Port Toggle Output Register
* - HW_GPIO_PDIR - Port Data Input Register
* - HW_GPIO_PDDR - Port Data Direction Register
*
* - hw_gpio_t - Struct containing all module registers.
*/
#define HW_GPIO_INSTANCE_COUNT (5U) /*!< Number of instances of the GPIO module. */
#define HW_GPIOA (0U) /*!< Instance number for GPIOA. */
#define HW_GPIOB (1U) /*!< Instance number for GPIOB. */
#define HW_GPIOC (2U) /*!< Instance number for GPIOC. */
#define HW_GPIOD (3U) /*!< Instance number for GPIOD. */
#define HW_GPIOE (4U) /*!< Instance number for GPIOE. */
/*******************************************************************************
* HW_GPIO_PDOR - Port Data Output Register
******************************************************************************/
/*!
* @brief HW_GPIO_PDOR - Port Data Output Register (RW)
*
* Reset value: 0x00000000U
*
* This register configures the logic levels that are driven on each
* general-purpose output pins. Do not modify pin configuration registers associated with
* pins not available in your selected package. All unbonded pins not available in
* your package will default to DISABLE state for lowest power consumption.
*/
typedef union _hw_gpio_pdor
{
uint32_t U;
struct _hw_gpio_pdor_bitfields
{
uint32_t PDO : 32; /*!< [31:0] Port Data Output */
} B;
} hw_gpio_pdor_t;
/*!
* @name Constants and macros for entire GPIO_PDOR register
*/
/*@{*/
#define HW_GPIO_PDOR_ADDR(x) ((x) + 0x0U)
#define HW_GPIO_PDOR(x) (*(__IO hw_gpio_pdor_t *) HW_GPIO_PDOR_ADDR(x))
#define HW_GPIO_PDOR_RD(x) (HW_GPIO_PDOR(x).U)
#define HW_GPIO_PDOR_WR(x, v) (HW_GPIO_PDOR(x).U = (v))
#define HW_GPIO_PDOR_SET(x, v) (HW_GPIO_PDOR_WR(x, HW_GPIO_PDOR_RD(x) | (v)))
#define HW_GPIO_PDOR_CLR(x, v) (HW_GPIO_PDOR_WR(x, HW_GPIO_PDOR_RD(x) & ~(v)))
#define HW_GPIO_PDOR_TOG(x, v) (HW_GPIO_PDOR_WR(x, HW_GPIO_PDOR_RD(x) ^ (v)))
/*@}*/
/*
* Constants & macros for individual GPIO_PDOR bitfields
*/
/*!
* @name Register GPIO_PDOR, field PDO[31:0] (RW)
*
* Register bits for unbonded pins return a undefined value when read.
*
* Values:
* - 0 - Logic level 0 is driven on pin, provided pin is configured for
* general-purpose output.
* - 1 - Logic level 1 is driven on pin, provided pin is configured for
* general-purpose output.
*/
/*@{*/
#define BP_GPIO_PDOR_PDO (0U) /*!< Bit position for GPIO_PDOR_PDO. */
#define BM_GPIO_PDOR_PDO (0xFFFFFFFFU) /*!< Bit mask for GPIO_PDOR_PDO. */
#define BS_GPIO_PDOR_PDO (32U) /*!< Bit field size in bits for GPIO_PDOR_PDO. */
/*! @brief Read current value of the GPIO_PDOR_PDO field. */
#define BR_GPIO_PDOR_PDO(x) (HW_GPIO_PDOR(x).U)
/*! @brief Format value for bitfield GPIO_PDOR_PDO. */
#define BF_GPIO_PDOR_PDO(v) ((uint32_t)((uint32_t)(v) << BP_GPIO_PDOR_PDO) & BM_GPIO_PDOR_PDO)
/*! @brief Set the PDO field to a new value. */
#define BW_GPIO_PDOR_PDO(x, v) (HW_GPIO_PDOR_WR(x, v))
/*@}*/
/*******************************************************************************
* HW_GPIO_PSOR - Port Set Output Register
******************************************************************************/
/*!
* @brief HW_GPIO_PSOR - Port Set Output Register (WORZ)
*
* Reset value: 0x00000000U
*
* This register configures whether to set the fields of the PDOR.
*/
typedef union _hw_gpio_psor
{
uint32_t U;
struct _hw_gpio_psor_bitfields
{
uint32_t PTSO : 32; /*!< [31:0] Port Set Output */
} B;
} hw_gpio_psor_t;
/*!
* @name Constants and macros for entire GPIO_PSOR register
*/
/*@{*/
#define HW_GPIO_PSOR_ADDR(x) ((x) + 0x4U)
#define HW_GPIO_PSOR(x) (*(__O hw_gpio_psor_t *) HW_GPIO_PSOR_ADDR(x))
#define HW_GPIO_PSOR_RD(x) (HW_GPIO_PSOR(x).U)
#define HW_GPIO_PSOR_WR(x, v) (HW_GPIO_PSOR(x).U = (v))
/*@}*/
/*
* Constants & macros for individual GPIO_PSOR bitfields
*/
/*!
* @name Register GPIO_PSOR, field PTSO[31:0] (WORZ)
*
* Writing to this register will update the contents of the corresponding bit in
* the PDOR as follows:
*
* Values:
* - 0 - Corresponding bit in PDORn does not change.
* - 1 - Corresponding bit in PDORn is set to logic 1.
*/
/*@{*/
#define BP_GPIO_PSOR_PTSO (0U) /*!< Bit position for GPIO_PSOR_PTSO. */
#define BM_GPIO_PSOR_PTSO (0xFFFFFFFFU) /*!< Bit mask for GPIO_PSOR_PTSO. */
#define BS_GPIO_PSOR_PTSO (32U) /*!< Bit field size in bits for GPIO_PSOR_PTSO. */
/*! @brief Format value for bitfield GPIO_PSOR_PTSO. */
#define BF_GPIO_PSOR_PTSO(v) ((uint32_t)((uint32_t)(v) << BP_GPIO_PSOR_PTSO) & BM_GPIO_PSOR_PTSO)
/*! @brief Set the PTSO field to a new value. */
#define BW_GPIO_PSOR_PTSO(x, v) (HW_GPIO_PSOR_WR(x, v))
/*@}*/
/*******************************************************************************
* HW_GPIO_PCOR - Port Clear Output Register
******************************************************************************/
/*!
* @brief HW_GPIO_PCOR - Port Clear Output Register (WORZ)
*
* Reset value: 0x00000000U
*
* This register configures whether to clear the fields of PDOR.
*/
typedef union _hw_gpio_pcor
{
uint32_t U;
struct _hw_gpio_pcor_bitfields
{
uint32_t PTCO : 32; /*!< [31:0] Port Clear Output */
} B;
} hw_gpio_pcor_t;
/*!
* @name Constants and macros for entire GPIO_PCOR register
*/
/*@{*/
#define HW_GPIO_PCOR_ADDR(x) ((x) + 0x8U)
#define HW_GPIO_PCOR(x) (*(__O hw_gpio_pcor_t *) HW_GPIO_PCOR_ADDR(x))
#define HW_GPIO_PCOR_RD(x) (HW_GPIO_PCOR(x).U)
#define HW_GPIO_PCOR_WR(x, v) (HW_GPIO_PCOR(x).U = (v))
/*@}*/
/*
* Constants & macros for individual GPIO_PCOR bitfields
*/
/*!
* @name Register GPIO_PCOR, field PTCO[31:0] (WORZ)
*
* Writing to this register will update the contents of the corresponding bit in
* the Port Data Output Register (PDOR) as follows:
*
* Values:
* - 0 - Corresponding bit in PDORn does not change.
* - 1 - Corresponding bit in PDORn is cleared to logic 0.
*/
/*@{*/
#define BP_GPIO_PCOR_PTCO (0U) /*!< Bit position for GPIO_PCOR_PTCO. */
#define BM_GPIO_PCOR_PTCO (0xFFFFFFFFU) /*!< Bit mask for GPIO_PCOR_PTCO. */
#define BS_GPIO_PCOR_PTCO (32U) /*!< Bit field size in bits for GPIO_PCOR_PTCO. */
/*! @brief Format value for bitfield GPIO_PCOR_PTCO. */
#define BF_GPIO_PCOR_PTCO(v) ((uint32_t)((uint32_t)(v) << BP_GPIO_PCOR_PTCO) & BM_GPIO_PCOR_PTCO)
/*! @brief Set the PTCO field to a new value. */
#define BW_GPIO_PCOR_PTCO(x, v) (HW_GPIO_PCOR_WR(x, v))
/*@}*/
/*******************************************************************************
* HW_GPIO_PTOR - Port Toggle Output Register
******************************************************************************/
/*!
* @brief HW_GPIO_PTOR - Port Toggle Output Register (WORZ)
*
* Reset value: 0x00000000U
*/
typedef union _hw_gpio_ptor
{
uint32_t U;
struct _hw_gpio_ptor_bitfields
{
uint32_t PTTO : 32; /*!< [31:0] Port Toggle Output */
} B;
} hw_gpio_ptor_t;
/*!
* @name Constants and macros for entire GPIO_PTOR register
*/
/*@{*/
#define HW_GPIO_PTOR_ADDR(x) ((x) + 0xCU)
#define HW_GPIO_PTOR(x) (*(__O hw_gpio_ptor_t *) HW_GPIO_PTOR_ADDR(x))
#define HW_GPIO_PTOR_RD(x) (HW_GPIO_PTOR(x).U)
#define HW_GPIO_PTOR_WR(x, v) (HW_GPIO_PTOR(x).U = (v))
/*@}*/
/*
* Constants & macros for individual GPIO_PTOR bitfields
*/
/*!
* @name Register GPIO_PTOR, field PTTO[31:0] (WORZ)
*
* Writing to this register will update the contents of the corresponding bit in
* the PDOR as follows:
*
* Values:
* - 0 - Corresponding bit in PDORn does not change.
* - 1 - Corresponding bit in PDORn is set to the inverse of its existing logic
* state.
*/
/*@{*/
#define BP_GPIO_PTOR_PTTO (0U) /*!< Bit position for GPIO_PTOR_PTTO. */
#define BM_GPIO_PTOR_PTTO (0xFFFFFFFFU) /*!< Bit mask for GPIO_PTOR_PTTO. */
#define BS_GPIO_PTOR_PTTO (32U) /*!< Bit field size in bits for GPIO_PTOR_PTTO. */
/*! @brief Format value for bitfield GPIO_PTOR_PTTO. */
#define BF_GPIO_PTOR_PTTO(v) ((uint32_t)((uint32_t)(v) << BP_GPIO_PTOR_PTTO) & BM_GPIO_PTOR_PTTO)
/*! @brief Set the PTTO field to a new value. */
#define BW_GPIO_PTOR_PTTO(x, v) (HW_GPIO_PTOR_WR(x, v))
/*@}*/
/*******************************************************************************
* HW_GPIO_PDIR - Port Data Input Register
******************************************************************************/
/*!
* @brief HW_GPIO_PDIR - Port Data Input Register (RO)
*
* Reset value: 0x00000000U
*
* Do not modify pin configuration registers associated with pins not available
* in your selected package. All unbonded pins not available in your package will
* default to DISABLE state for lowest power consumption.
*/
typedef union _hw_gpio_pdir
{
uint32_t U;
struct _hw_gpio_pdir_bitfields
{
uint32_t PDI : 32; /*!< [31:0] Port Data Input */
} B;
} hw_gpio_pdir_t;
/*!
* @name Constants and macros for entire GPIO_PDIR register
*/
/*@{*/
#define HW_GPIO_PDIR_ADDR(x) ((x) + 0x10U)
#define HW_GPIO_PDIR(x) (*(__I hw_gpio_pdir_t *) HW_GPIO_PDIR_ADDR(x))
#define HW_GPIO_PDIR_RD(x) (HW_GPIO_PDIR(x).U)
/*@}*/
/*
* Constants & macros for individual GPIO_PDIR bitfields
*/
/*!
* @name Register GPIO_PDIR, field PDI[31:0] (RO)
*
* Reads 0 at the unimplemented pins for a particular device. Pins that are not
* configured for a digital function read 0. If the Port Control and Interrupt
* module is disabled, then the corresponding bit in PDIR does not update.
*
* Values:
* - 0 - Pin logic level is logic 0, or is not configured for use by digital
* function.
* - 1 - Pin logic level is logic 1.
*/
/*@{*/
#define BP_GPIO_PDIR_PDI (0U) /*!< Bit position for GPIO_PDIR_PDI. */
#define BM_GPIO_PDIR_PDI (0xFFFFFFFFU) /*!< Bit mask for GPIO_PDIR_PDI. */
#define BS_GPIO_PDIR_PDI (32U) /*!< Bit field size in bits for GPIO_PDIR_PDI. */
/*! @brief Read current value of the GPIO_PDIR_PDI field. */
#define BR_GPIO_PDIR_PDI(x) (HW_GPIO_PDIR(x).U)
/*@}*/
/*******************************************************************************
* HW_GPIO_PDDR - Port Data Direction Register
******************************************************************************/
/*!
* @brief HW_GPIO_PDDR - Port Data Direction Register (RW)
*
* Reset value: 0x00000000U
*
* The PDDR configures the individual port pins for input or output.
*/
typedef union _hw_gpio_pddr
{
uint32_t U;
struct _hw_gpio_pddr_bitfields
{
uint32_t PDD : 32; /*!< [31:0] Port Data Direction */
} B;
} hw_gpio_pddr_t;
/*!
* @name Constants and macros for entire GPIO_PDDR register
*/
/*@{*/
#define HW_GPIO_PDDR_ADDR(x) ((x) + 0x14U)
#define HW_GPIO_PDDR(x) (*(__IO hw_gpio_pddr_t *) HW_GPIO_PDDR_ADDR(x))
#define HW_GPIO_PDDR_RD(x) (HW_GPIO_PDDR(x).U)
#define HW_GPIO_PDDR_WR(x, v) (HW_GPIO_PDDR(x).U = (v))
#define HW_GPIO_PDDR_SET(x, v) (HW_GPIO_PDDR_WR(x, HW_GPIO_PDDR_RD(x) | (v)))
#define HW_GPIO_PDDR_CLR(x, v) (HW_GPIO_PDDR_WR(x, HW_GPIO_PDDR_RD(x) & ~(v)))
#define HW_GPIO_PDDR_TOG(x, v) (HW_GPIO_PDDR_WR(x, HW_GPIO_PDDR_RD(x) ^ (v)))
/*@}*/
/*
* Constants & macros for individual GPIO_PDDR bitfields
*/
/*!
* @name Register GPIO_PDDR, field PDD[31:0] (RW)
*
* Configures individual port pins for input or output.
*
* Values:
* - 0 - Pin is configured as general-purpose input, for the GPIO function.
* - 1 - Pin is configured as general-purpose output, for the GPIO function.
*/
/*@{*/
#define BP_GPIO_PDDR_PDD (0U) /*!< Bit position for GPIO_PDDR_PDD. */
#define BM_GPIO_PDDR_PDD (0xFFFFFFFFU) /*!< Bit mask for GPIO_PDDR_PDD. */
#define BS_GPIO_PDDR_PDD (32U) /*!< Bit field size in bits for GPIO_PDDR_PDD. */
/*! @brief Read current value of the GPIO_PDDR_PDD field. */
#define BR_GPIO_PDDR_PDD(x) (HW_GPIO_PDDR(x).U)
/*! @brief Format value for bitfield GPIO_PDDR_PDD. */
#define BF_GPIO_PDDR_PDD(v) ((uint32_t)((uint32_t)(v) << BP_GPIO_PDDR_PDD) & BM_GPIO_PDDR_PDD)
/*! @brief Set the PDD field to a new value. */
#define BW_GPIO_PDDR_PDD(x, v) (HW_GPIO_PDDR_WR(x, v))
/*@}*/
/*******************************************************************************
* hw_gpio_t - module struct
******************************************************************************/
/*!
* @brief All GPIO module registers.
*/
#pragma pack(1)
typedef struct _hw_gpio
{
__IO hw_gpio_pdor_t PDOR; /*!< [0x0] Port Data Output Register */
__O hw_gpio_psor_t PSOR; /*!< [0x4] Port Set Output Register */
__O hw_gpio_pcor_t PCOR; /*!< [0x8] Port Clear Output Register */
__O hw_gpio_ptor_t PTOR; /*!< [0xC] Port Toggle Output Register */
__I hw_gpio_pdir_t PDIR; /*!< [0x10] Port Data Input Register */
__IO hw_gpio_pddr_t PDDR; /*!< [0x14] Port Data Direction Register */
} hw_gpio_t;
#pragma pack()
/*! @brief Macro to access all GPIO registers. */
/*! @param x GPIO module instance base address. */
/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
* use the '&' operator, like <code>&HW_GPIO(GPIOA_BASE)</code>. */
#define HW_GPIO(x) (*(hw_gpio_t *)(x))
#endif /* __HW_GPIO_REGISTERS_H__ */
/* EOF */

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/*
** ###################################################################
** Compilers: Keil ARM C/C++ Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
** Version: rev. 2.5, 2014-05-06
** Build: b140604
**
** Abstract:
** Extension to the CMSIS register access layer header.
**
** Copyright (c) 2014 Freescale Semiconductor, Inc.
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** Revisions:
** - rev. 1.0 (2013-07-23)
** Initial version.
** - rev. 1.1 (2013-09-17)
** RM rev. 0.4 update.
** - rev. 2.0 (2013-10-29)
** Register accessor macros added to the memory map.
** Symbols for Processor Expert memory map compatibility added to the memory map.
** Startup file for gcc has been updated according to CMSIS 3.2.
** System initialization updated.
** - rev. 2.1 (2013-10-30)
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
** - rev. 2.2 (2013-12-20)
** Update according to reference manual rev. 0.6,
** - rev. 2.3 (2014-01-13)
** Update according to reference manual rev. 0.61,
** - rev. 2.4 (2014-02-10)
** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
** - rev. 2.5 (2014-05-06)
** Update according to reference manual rev. 1.0,
** Update of system and startup files.
** Module access macro module_BASES replaced by module_BASE_PTRS.
**
** ###################################################################
*/
/*
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
*
* This file was generated automatically and any changes may be lost.
*/
#ifndef __HW_LPTMR_REGISTERS_H__
#define __HW_LPTMR_REGISTERS_H__
#include "MK22F51212.h"
#include "fsl_bitaccess.h"
/*
* MK22F51212 LPTMR
*
* Low Power Timer
*
* Registers defined in this header file:
* - HW_LPTMR_CSR - Low Power Timer Control Status Register
* - HW_LPTMR_PSR - Low Power Timer Prescale Register
* - HW_LPTMR_CMR - Low Power Timer Compare Register
* - HW_LPTMR_CNR - Low Power Timer Counter Register
*
* - hw_lptmr_t - Struct containing all module registers.
*/
#define HW_LPTMR_INSTANCE_COUNT (1U) /*!< Number of instances of the LPTMR module. */
/*******************************************************************************
* HW_LPTMR_CSR - Low Power Timer Control Status Register
******************************************************************************/
/*!
* @brief HW_LPTMR_CSR - Low Power Timer Control Status Register (RW)
*
* Reset value: 0x00000000U
*/
typedef union _hw_lptmr_csr
{
uint32_t U;
struct _hw_lptmr_csr_bitfields
{
uint32_t TEN : 1; /*!< [0] Timer Enable */
uint32_t TMS : 1; /*!< [1] Timer Mode Select */
uint32_t TFC : 1; /*!< [2] Timer Free-Running Counter */
uint32_t TPP : 1; /*!< [3] Timer Pin Polarity */
uint32_t TPS : 2; /*!< [5:4] Timer Pin Select */
uint32_t TIE : 1; /*!< [6] Timer Interrupt Enable */
uint32_t TCF : 1; /*!< [7] Timer Compare Flag */
uint32_t RESERVED0 : 24; /*!< [31:8] */
} B;
} hw_lptmr_csr_t;
/*!
* @name Constants and macros for entire LPTMR_CSR register
*/
/*@{*/
#define HW_LPTMR_CSR_ADDR(x) ((x) + 0x0U)
#define HW_LPTMR_CSR(x) (*(__IO hw_lptmr_csr_t *) HW_LPTMR_CSR_ADDR(x))
#define HW_LPTMR_CSR_RD(x) (HW_LPTMR_CSR(x).U)
#define HW_LPTMR_CSR_WR(x, v) (HW_LPTMR_CSR(x).U = (v))
#define HW_LPTMR_CSR_SET(x, v) (HW_LPTMR_CSR_WR(x, HW_LPTMR_CSR_RD(x) | (v)))
#define HW_LPTMR_CSR_CLR(x, v) (HW_LPTMR_CSR_WR(x, HW_LPTMR_CSR_RD(x) & ~(v)))
#define HW_LPTMR_CSR_TOG(x, v) (HW_LPTMR_CSR_WR(x, HW_LPTMR_CSR_RD(x) ^ (v)))
/*@}*/
/*
* Constants & macros for individual LPTMR_CSR bitfields
*/
/*!
* @name Register LPTMR_CSR, field TEN[0] (RW)
*
* When TEN is clear, it resets the LPTMR internal logic, including the CNR and
* TCF. When TEN is set, the LPTMR is enabled. While writing 1 to this field,
* CSR[5:1] must not be altered.
*
* Values:
* - 0 - LPTMR is disabled and internal logic is reset.
* - 1 - LPTMR is enabled.
*/
/*@{*/
#define BP_LPTMR_CSR_TEN (0U) /*!< Bit position for LPTMR_CSR_TEN. */
#define BM_LPTMR_CSR_TEN (0x00000001U) /*!< Bit mask for LPTMR_CSR_TEN. */
#define BS_LPTMR_CSR_TEN (1U) /*!< Bit field size in bits for LPTMR_CSR_TEN. */
/*! @brief Read current value of the LPTMR_CSR_TEN field. */
#define BR_LPTMR_CSR_TEN(x) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TEN))
/*! @brief Format value for bitfield LPTMR_CSR_TEN. */
#define BF_LPTMR_CSR_TEN(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_CSR_TEN) & BM_LPTMR_CSR_TEN)
/*! @brief Set the TEN field to a new value. */
#define BW_LPTMR_CSR_TEN(x, v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TEN) = (v))
/*@}*/
/*!
* @name Register LPTMR_CSR, field TMS[1] (RW)
*
* Configures the mode of the LPTMR. TMS must be altered only when the LPTMR is
* disabled.
*
* Values:
* - 0 - Time Counter mode.
* - 1 - Pulse Counter mode.
*/
/*@{*/
#define BP_LPTMR_CSR_TMS (1U) /*!< Bit position for LPTMR_CSR_TMS. */
#define BM_LPTMR_CSR_TMS (0x00000002U) /*!< Bit mask for LPTMR_CSR_TMS. */
#define BS_LPTMR_CSR_TMS (1U) /*!< Bit field size in bits for LPTMR_CSR_TMS. */
/*! @brief Read current value of the LPTMR_CSR_TMS field. */
#define BR_LPTMR_CSR_TMS(x) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TMS))
/*! @brief Format value for bitfield LPTMR_CSR_TMS. */
#define BF_LPTMR_CSR_TMS(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_CSR_TMS) & BM_LPTMR_CSR_TMS)
/*! @brief Set the TMS field to a new value. */
#define BW_LPTMR_CSR_TMS(x, v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TMS) = (v))
/*@}*/
/*!
* @name Register LPTMR_CSR, field TFC[2] (RW)
*
* When clear, TFC configures the CNR to reset whenever TCF is set. When set,
* TFC configures the CNR to reset on overflow. TFC must be altered only when the
* LPTMR is disabled.
*
* Values:
* - 0 - CNR is reset whenever TCF is set.
* - 1 - CNR is reset on overflow.
*/
/*@{*/
#define BP_LPTMR_CSR_TFC (2U) /*!< Bit position for LPTMR_CSR_TFC. */
#define BM_LPTMR_CSR_TFC (0x00000004U) /*!< Bit mask for LPTMR_CSR_TFC. */
#define BS_LPTMR_CSR_TFC (1U) /*!< Bit field size in bits for LPTMR_CSR_TFC. */
/*! @brief Read current value of the LPTMR_CSR_TFC field. */
#define BR_LPTMR_CSR_TFC(x) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TFC))
/*! @brief Format value for bitfield LPTMR_CSR_TFC. */
#define BF_LPTMR_CSR_TFC(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_CSR_TFC) & BM_LPTMR_CSR_TFC)
/*! @brief Set the TFC field to a new value. */
#define BW_LPTMR_CSR_TFC(x, v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TFC) = (v))
/*@}*/
/*!
* @name Register LPTMR_CSR, field TPP[3] (RW)
*
* Configures the polarity of the input source in Pulse Counter mode. TPP must
* be changed only when the LPTMR is disabled.
*
* Values:
* - 0 - Pulse Counter input source is active-high, and the CNR will increment
* on the rising-edge.
* - 1 - Pulse Counter input source is active-low, and the CNR will increment on
* the falling-edge.
*/
/*@{*/
#define BP_LPTMR_CSR_TPP (3U) /*!< Bit position for LPTMR_CSR_TPP. */
#define BM_LPTMR_CSR_TPP (0x00000008U) /*!< Bit mask for LPTMR_CSR_TPP. */
#define BS_LPTMR_CSR_TPP (1U) /*!< Bit field size in bits for LPTMR_CSR_TPP. */
/*! @brief Read current value of the LPTMR_CSR_TPP field. */
#define BR_LPTMR_CSR_TPP(x) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TPP))
/*! @brief Format value for bitfield LPTMR_CSR_TPP. */
#define BF_LPTMR_CSR_TPP(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_CSR_TPP) & BM_LPTMR_CSR_TPP)
/*! @brief Set the TPP field to a new value. */
#define BW_LPTMR_CSR_TPP(x, v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TPP) = (v))
/*@}*/
/*!
* @name Register LPTMR_CSR, field TPS[5:4] (RW)
*
* Configures the input source to be used in Pulse Counter mode. TPS must be
* altered only when the LPTMR is disabled. The input connections vary by device.
* See the chip configuration details for information on the connections to these
* inputs.
*
* Values:
* - 00 - Pulse counter input 0 is selected.
* - 01 - Pulse counter input 1 is selected.
* - 10 - Pulse counter input 2 is selected.
* - 11 - Pulse counter input 3 is selected.
*/
/*@{*/
#define BP_LPTMR_CSR_TPS (4U) /*!< Bit position for LPTMR_CSR_TPS. */
#define BM_LPTMR_CSR_TPS (0x00000030U) /*!< Bit mask for LPTMR_CSR_TPS. */
#define BS_LPTMR_CSR_TPS (2U) /*!< Bit field size in bits for LPTMR_CSR_TPS. */
/*! @brief Read current value of the LPTMR_CSR_TPS field. */
#define BR_LPTMR_CSR_TPS(x) (HW_LPTMR_CSR(x).B.TPS)
/*! @brief Format value for bitfield LPTMR_CSR_TPS. */
#define BF_LPTMR_CSR_TPS(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_CSR_TPS) & BM_LPTMR_CSR_TPS)
/*! @brief Set the TPS field to a new value. */
#define BW_LPTMR_CSR_TPS(x, v) (HW_LPTMR_CSR_WR(x, (HW_LPTMR_CSR_RD(x) & ~BM_LPTMR_CSR_TPS) | BF_LPTMR_CSR_TPS(v)))
/*@}*/
/*!
* @name Register LPTMR_CSR, field TIE[6] (RW)
*
* When TIE is set, the LPTMR Interrupt is generated whenever TCF is also set.
*
* Values:
* - 0 - Timer interrupt disabled.
* - 1 - Timer interrupt enabled.
*/
/*@{*/
#define BP_LPTMR_CSR_TIE (6U) /*!< Bit position for LPTMR_CSR_TIE. */
#define BM_LPTMR_CSR_TIE (0x00000040U) /*!< Bit mask for LPTMR_CSR_TIE. */
#define BS_LPTMR_CSR_TIE (1U) /*!< Bit field size in bits for LPTMR_CSR_TIE. */
/*! @brief Read current value of the LPTMR_CSR_TIE field. */
#define BR_LPTMR_CSR_TIE(x) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TIE))
/*! @brief Format value for bitfield LPTMR_CSR_TIE. */
#define BF_LPTMR_CSR_TIE(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_CSR_TIE) & BM_LPTMR_CSR_TIE)
/*! @brief Set the TIE field to a new value. */
#define BW_LPTMR_CSR_TIE(x, v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TIE) = (v))
/*@}*/
/*!
* @name Register LPTMR_CSR, field TCF[7] (W1C)
*
* TCF is set when the LPTMR is enabled and the CNR equals the CMR and
* increments. TCF is cleared when the LPTMR is disabled or a logic 1 is written to it.
*
* Values:
* - 0 - The value of CNR is not equal to CMR and increments.
* - 1 - The value of CNR is equal to CMR and increments.
*/
/*@{*/
#define BP_LPTMR_CSR_TCF (7U) /*!< Bit position for LPTMR_CSR_TCF. */
#define BM_LPTMR_CSR_TCF (0x00000080U) /*!< Bit mask for LPTMR_CSR_TCF. */
#define BS_LPTMR_CSR_TCF (1U) /*!< Bit field size in bits for LPTMR_CSR_TCF. */
/*! @brief Read current value of the LPTMR_CSR_TCF field. */
#define BR_LPTMR_CSR_TCF(x) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TCF))
/*! @brief Format value for bitfield LPTMR_CSR_TCF. */
#define BF_LPTMR_CSR_TCF(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_CSR_TCF) & BM_LPTMR_CSR_TCF)
/*! @brief Set the TCF field to a new value. */
#define BW_LPTMR_CSR_TCF(x, v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TCF) = (v))
/*@}*/
/*******************************************************************************
* HW_LPTMR_PSR - Low Power Timer Prescale Register
******************************************************************************/
/*!
* @brief HW_LPTMR_PSR - Low Power Timer Prescale Register (RW)
*
* Reset value: 0x00000000U
*/
typedef union _hw_lptmr_psr
{
uint32_t U;
struct _hw_lptmr_psr_bitfields
{
uint32_t PCS : 2; /*!< [1:0] Prescaler Clock Select */
uint32_t PBYP : 1; /*!< [2] Prescaler Bypass */
uint32_t PRESCALE : 4; /*!< [6:3] Prescale Value */
uint32_t RESERVED0 : 25; /*!< [31:7] */
} B;
} hw_lptmr_psr_t;
/*!
* @name Constants and macros for entire LPTMR_PSR register
*/
/*@{*/
#define HW_LPTMR_PSR_ADDR(x) ((x) + 0x4U)
#define HW_LPTMR_PSR(x) (*(__IO hw_lptmr_psr_t *) HW_LPTMR_PSR_ADDR(x))
#define HW_LPTMR_PSR_RD(x) (HW_LPTMR_PSR(x).U)
#define HW_LPTMR_PSR_WR(x, v) (HW_LPTMR_PSR(x).U = (v))
#define HW_LPTMR_PSR_SET(x, v) (HW_LPTMR_PSR_WR(x, HW_LPTMR_PSR_RD(x) | (v)))
#define HW_LPTMR_PSR_CLR(x, v) (HW_LPTMR_PSR_WR(x, HW_LPTMR_PSR_RD(x) & ~(v)))
#define HW_LPTMR_PSR_TOG(x, v) (HW_LPTMR_PSR_WR(x, HW_LPTMR_PSR_RD(x) ^ (v)))
/*@}*/
/*
* Constants & macros for individual LPTMR_PSR bitfields
*/
/*!
* @name Register LPTMR_PSR, field PCS[1:0] (RW)
*
* Selects the clock to be used by the LPTMR prescaler/glitch filter. PCS must
* be altered only when the LPTMR is disabled. The clock connections vary by
* device. See the chip configuration details for information on the connections to
* these inputs.
*
* Values:
* - 00 - Prescaler/glitch filter clock 0 selected.
* - 01 - Prescaler/glitch filter clock 1 selected.
* - 10 - Prescaler/glitch filter clock 2 selected.
* - 11 - Prescaler/glitch filter clock 3 selected.
*/
/*@{*/
#define BP_LPTMR_PSR_PCS (0U) /*!< Bit position for LPTMR_PSR_PCS. */
#define BM_LPTMR_PSR_PCS (0x00000003U) /*!< Bit mask for LPTMR_PSR_PCS. */
#define BS_LPTMR_PSR_PCS (2U) /*!< Bit field size in bits for LPTMR_PSR_PCS. */
/*! @brief Read current value of the LPTMR_PSR_PCS field. */
#define BR_LPTMR_PSR_PCS(x) (HW_LPTMR_PSR(x).B.PCS)
/*! @brief Format value for bitfield LPTMR_PSR_PCS. */
#define BF_LPTMR_PSR_PCS(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_PSR_PCS) & BM_LPTMR_PSR_PCS)
/*! @brief Set the PCS field to a new value. */
#define BW_LPTMR_PSR_PCS(x, v) (HW_LPTMR_PSR_WR(x, (HW_LPTMR_PSR_RD(x) & ~BM_LPTMR_PSR_PCS) | BF_LPTMR_PSR_PCS(v)))
/*@}*/
/*!
* @name Register LPTMR_PSR, field PBYP[2] (RW)
*
* When PBYP is set, the selected prescaler clock in Time Counter mode or
* selected input source in Pulse Counter mode directly clocks the CNR. When PBYP is
* clear, the CNR is clocked by the output of the prescaler/glitch filter. PBYP
* must be altered only when the LPTMR is disabled.
*
* Values:
* - 0 - Prescaler/glitch filter is enabled.
* - 1 - Prescaler/glitch filter is bypassed.
*/
/*@{*/
#define BP_LPTMR_PSR_PBYP (2U) /*!< Bit position for LPTMR_PSR_PBYP. */
#define BM_LPTMR_PSR_PBYP (0x00000004U) /*!< Bit mask for LPTMR_PSR_PBYP. */
#define BS_LPTMR_PSR_PBYP (1U) /*!< Bit field size in bits for LPTMR_PSR_PBYP. */
/*! @brief Read current value of the LPTMR_PSR_PBYP field. */
#define BR_LPTMR_PSR_PBYP(x) (BITBAND_ACCESS32(HW_LPTMR_PSR_ADDR(x), BP_LPTMR_PSR_PBYP))
/*! @brief Format value for bitfield LPTMR_PSR_PBYP. */
#define BF_LPTMR_PSR_PBYP(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_PSR_PBYP) & BM_LPTMR_PSR_PBYP)
/*! @brief Set the PBYP field to a new value. */
#define BW_LPTMR_PSR_PBYP(x, v) (BITBAND_ACCESS32(HW_LPTMR_PSR_ADDR(x), BP_LPTMR_PSR_PBYP) = (v))
/*@}*/
/*!
* @name Register LPTMR_PSR, field PRESCALE[6:3] (RW)
*
* Configures the size of the Prescaler in Time Counter mode or width of the
* glitch filter in Pulse Counter mode. PRESCALE must be altered only when the LPTMR
* is disabled.
*
* Values:
* - 0000 - Prescaler divides the prescaler clock by 2; glitch filter does not
* support this configuration.
* - 0001 - Prescaler divides the prescaler clock by 4; glitch filter recognizes
* change on input pin after 2 rising clock edges.
* - 0010 - Prescaler divides the prescaler clock by 8; glitch filter recognizes
* change on input pin after 4 rising clock edges.
* - 0011 - Prescaler divides the prescaler clock by 16; glitch filter
* recognizes change on input pin after 8 rising clock edges.
* - 0100 - Prescaler divides the prescaler clock by 32; glitch filter
* recognizes change on input pin after 16 rising clock edges.
* - 0101 - Prescaler divides the prescaler clock by 64; glitch filter
* recognizes change on input pin after 32 rising clock edges.
* - 0110 - Prescaler divides the prescaler clock by 128; glitch filter
* recognizes change on input pin after 64 rising clock edges.
* - 0111 - Prescaler divides the prescaler clock by 256; glitch filter
* recognizes change on input pin after 128 rising clock edges.
* - 1000 - Prescaler divides the prescaler clock by 512; glitch filter
* recognizes change on input pin after 256 rising clock edges.
* - 1001 - Prescaler divides the prescaler clock by 1024; glitch filter
* recognizes change on input pin after 512 rising clock edges.
* - 1010 - Prescaler divides the prescaler clock by 2048; glitch filter
* recognizes change on input pin after 1024 rising clock edges.
* - 1011 - Prescaler divides the prescaler clock by 4096; glitch filter
* recognizes change on input pin after 2048 rising clock edges.
* - 1100 - Prescaler divides the prescaler clock by 8192; glitch filter
* recognizes change on input pin after 4096 rising clock edges.
* - 1101 - Prescaler divides the prescaler clock by 16,384; glitch filter
* recognizes change on input pin after 8192 rising clock edges.
* - 1110 - Prescaler divides the prescaler clock by 32,768; glitch filter
* recognizes change on input pin after 16,384 rising clock edges.
* - 1111 - Prescaler divides the prescaler clock by 65,536; glitch filter
* recognizes change on input pin after 32,768 rising clock edges.
*/
/*@{*/
#define BP_LPTMR_PSR_PRESCALE (3U) /*!< Bit position for LPTMR_PSR_PRESCALE. */
#define BM_LPTMR_PSR_PRESCALE (0x00000078U) /*!< Bit mask for LPTMR_PSR_PRESCALE. */
#define BS_LPTMR_PSR_PRESCALE (4U) /*!< Bit field size in bits for LPTMR_PSR_PRESCALE. */
/*! @brief Read current value of the LPTMR_PSR_PRESCALE field. */
#define BR_LPTMR_PSR_PRESCALE(x) (HW_LPTMR_PSR(x).B.PRESCALE)
/*! @brief Format value for bitfield LPTMR_PSR_PRESCALE. */
#define BF_LPTMR_PSR_PRESCALE(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_PSR_PRESCALE) & BM_LPTMR_PSR_PRESCALE)
/*! @brief Set the PRESCALE field to a new value. */
#define BW_LPTMR_PSR_PRESCALE(x, v) (HW_LPTMR_PSR_WR(x, (HW_LPTMR_PSR_RD(x) & ~BM_LPTMR_PSR_PRESCALE) | BF_LPTMR_PSR_PRESCALE(v)))
/*@}*/
/*******************************************************************************
* HW_LPTMR_CMR - Low Power Timer Compare Register
******************************************************************************/
/*!
* @brief HW_LPTMR_CMR - Low Power Timer Compare Register (RW)
*
* Reset value: 0x00000000U
*/
typedef union _hw_lptmr_cmr
{
uint32_t U;
struct _hw_lptmr_cmr_bitfields
{
uint32_t COMPARE : 16; /*!< [15:0] Compare Value */
uint32_t RESERVED0 : 16; /*!< [31:16] */
} B;
} hw_lptmr_cmr_t;
/*!
* @name Constants and macros for entire LPTMR_CMR register
*/
/*@{*/
#define HW_LPTMR_CMR_ADDR(x) ((x) + 0x8U)
#define HW_LPTMR_CMR(x) (*(__IO hw_lptmr_cmr_t *) HW_LPTMR_CMR_ADDR(x))
#define HW_LPTMR_CMR_RD(x) (HW_LPTMR_CMR(x).U)
#define HW_LPTMR_CMR_WR(x, v) (HW_LPTMR_CMR(x).U = (v))
#define HW_LPTMR_CMR_SET(x, v) (HW_LPTMR_CMR_WR(x, HW_LPTMR_CMR_RD(x) | (v)))
#define HW_LPTMR_CMR_CLR(x, v) (HW_LPTMR_CMR_WR(x, HW_LPTMR_CMR_RD(x) & ~(v)))
#define HW_LPTMR_CMR_TOG(x, v) (HW_LPTMR_CMR_WR(x, HW_LPTMR_CMR_RD(x) ^ (v)))
/*@}*/
/*
* Constants & macros for individual LPTMR_CMR bitfields
*/
/*!
* @name Register LPTMR_CMR, field COMPARE[15:0] (RW)
*
* When the LPTMR is enabled and the CNR equals the value in the CMR and
* increments, TCF is set and the hardware trigger asserts until the next time the CNR
* increments. If the CMR is 0, the hardware trigger will remain asserted until
* the LPTMR is disabled. If the LPTMR is enabled, the CMR must be altered only
* when TCF is set.
*/
/*@{*/
#define BP_LPTMR_CMR_COMPARE (0U) /*!< Bit position for LPTMR_CMR_COMPARE. */
#define BM_LPTMR_CMR_COMPARE (0x0000FFFFU) /*!< Bit mask for LPTMR_CMR_COMPARE. */
#define BS_LPTMR_CMR_COMPARE (16U) /*!< Bit field size in bits for LPTMR_CMR_COMPARE. */
/*! @brief Read current value of the LPTMR_CMR_COMPARE field. */
#define BR_LPTMR_CMR_COMPARE(x) (HW_LPTMR_CMR(x).B.COMPARE)
/*! @brief Format value for bitfield LPTMR_CMR_COMPARE. */
#define BF_LPTMR_CMR_COMPARE(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_CMR_COMPARE) & BM_LPTMR_CMR_COMPARE)
/*! @brief Set the COMPARE field to a new value. */
#define BW_LPTMR_CMR_COMPARE(x, v) (HW_LPTMR_CMR_WR(x, (HW_LPTMR_CMR_RD(x) & ~BM_LPTMR_CMR_COMPARE) | BF_LPTMR_CMR_COMPARE(v)))
/*@}*/
/*******************************************************************************
* HW_LPTMR_CNR - Low Power Timer Counter Register
******************************************************************************/
/*!
* @brief HW_LPTMR_CNR - Low Power Timer Counter Register (RW)
*
* Reset value: 0x00000000U
*/
typedef union _hw_lptmr_cnr
{
uint32_t U;
struct _hw_lptmr_cnr_bitfields
{
uint32_t COUNTER : 16; /*!< [15:0] Counter Value */
uint32_t RESERVED0 : 16; /*!< [31:16] */
} B;
} hw_lptmr_cnr_t;
/*!
* @name Constants and macros for entire LPTMR_CNR register
*/
/*@{*/
#define HW_LPTMR_CNR_ADDR(x) ((x) + 0xCU)
#define HW_LPTMR_CNR(x) (*(__IO hw_lptmr_cnr_t *) HW_LPTMR_CNR_ADDR(x))
#define HW_LPTMR_CNR_RD(x) (HW_LPTMR_CNR(x).U)
#define HW_LPTMR_CNR_WR(x, v) (HW_LPTMR_CNR(x).U = (v))
#define HW_LPTMR_CNR_SET(x, v) (HW_LPTMR_CNR_WR(x, HW_LPTMR_CNR_RD(x) | (v)))
#define HW_LPTMR_CNR_CLR(x, v) (HW_LPTMR_CNR_WR(x, HW_LPTMR_CNR_RD(x) & ~(v)))
#define HW_LPTMR_CNR_TOG(x, v) (HW_LPTMR_CNR_WR(x, HW_LPTMR_CNR_RD(x) ^ (v)))
/*@}*/
/*
* Constants & macros for individual LPTMR_CNR bitfields
*/
/*!
* @name Register LPTMR_CNR, field COUNTER[15:0] (RW)
*/
/*@{*/
#define BP_LPTMR_CNR_COUNTER (0U) /*!< Bit position for LPTMR_CNR_COUNTER. */
#define BM_LPTMR_CNR_COUNTER (0x0000FFFFU) /*!< Bit mask for LPTMR_CNR_COUNTER. */
#define BS_LPTMR_CNR_COUNTER (16U) /*!< Bit field size in bits for LPTMR_CNR_COUNTER. */
/*! @brief Read current value of the LPTMR_CNR_COUNTER field. */
#define BR_LPTMR_CNR_COUNTER(x) (HW_LPTMR_CNR(x).B.COUNTER)
/*! @brief Format value for bitfield LPTMR_CNR_COUNTER. */
#define BF_LPTMR_CNR_COUNTER(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_CNR_COUNTER) & BM_LPTMR_CNR_COUNTER)
/*! @brief Set the COUNTER field to a new value. */
#define BW_LPTMR_CNR_COUNTER(x, v) (HW_LPTMR_CNR_WR(x, (HW_LPTMR_CNR_RD(x) & ~BM_LPTMR_CNR_COUNTER) | BF_LPTMR_CNR_COUNTER(v)))
/*@}*/
/*******************************************************************************
* hw_lptmr_t - module struct
******************************************************************************/
/*!
* @brief All LPTMR module registers.
*/
#pragma pack(1)
typedef struct _hw_lptmr
{
__IO hw_lptmr_csr_t CSR; /*!< [0x0] Low Power Timer Control Status Register */
__IO hw_lptmr_psr_t PSR; /*!< [0x4] Low Power Timer Prescale Register */
__IO hw_lptmr_cmr_t CMR; /*!< [0x8] Low Power Timer Compare Register */
__IO hw_lptmr_cnr_t CNR; /*!< [0xC] Low Power Timer Counter Register */
} hw_lptmr_t;
#pragma pack()
/*! @brief Macro to access all LPTMR registers. */
/*! @param x LPTMR module instance base address. */
/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
* use the '&' operator, like <code>&HW_LPTMR(LPTMR0_BASE)</code>. */
#define HW_LPTMR(x) (*(hw_lptmr_t *)(x))
#endif /* __HW_LPTMR_REGISTERS_H__ */
/* EOF */

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/*
** ###################################################################
** Compilers: Keil ARM C/C++ Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
** Version: rev. 2.5, 2014-05-06
** Build: b140604
**
** Abstract:
** Extension to the CMSIS register access layer header.
**
** Copyright (c) 2014 Freescale Semiconductor, Inc.
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** Revisions:
** - rev. 1.0 (2013-07-23)
** Initial version.
** - rev. 1.1 (2013-09-17)
** RM rev. 0.4 update.
** - rev. 2.0 (2013-10-29)
** Register accessor macros added to the memory map.
** Symbols for Processor Expert memory map compatibility added to the memory map.
** Startup file for gcc has been updated according to CMSIS 3.2.
** System initialization updated.
** - rev. 2.1 (2013-10-30)
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
** - rev. 2.2 (2013-12-20)
** Update according to reference manual rev. 0.6,
** - rev. 2.3 (2014-01-13)
** Update according to reference manual rev. 0.61,
** - rev. 2.4 (2014-02-10)
** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
** - rev. 2.5 (2014-05-06)
** Update according to reference manual rev. 1.0,
** Update of system and startup files.
** Module access macro module_BASES replaced by module_BASE_PTRS.
**
** ###################################################################
*/
/*
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
*
* This file was generated automatically and any changes may be lost.
*/
#ifndef __HW_MCM_REGISTERS_H__
#define __HW_MCM_REGISTERS_H__
#include "MK22F51212.h"
#include "fsl_bitaccess.h"
/*
* MK22F51212 MCM
*
* Core Platform Miscellaneous Control Module
*
* Registers defined in this header file:
* - HW_MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration
* - HW_MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration
* - HW_MCM_PLACR - Crossbar Switch (AXBS) Control Register
* - HW_MCM_ISCR - Interrupt Status and Control Register
* - HW_MCM_CPO - Compute Operation Control Register
*
* - hw_mcm_t - Struct containing all module registers.
*/
#define HW_MCM_INSTANCE_COUNT (1U) /*!< Number of instances of the MCM module. */
/*******************************************************************************
* HW_MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration
******************************************************************************/
/*!
* @brief HW_MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration (RO)
*
* Reset value: 0x001FU
*
* PLASC is a 16-bit read-only register identifying the presence/absence of bus
* slave connections to the device's crossbar switch.
*/
typedef union _hw_mcm_plasc
{
uint16_t U;
struct _hw_mcm_plasc_bitfields
{
uint16_t ASC : 8; /*!< [7:0] Each bit in the ASC field indicates
* whether there is a corresponding connection to the crossbar switch's slave
* input port. */
uint16_t RESERVED0 : 8; /*!< [15:8] */
} B;
} hw_mcm_plasc_t;
/*!
* @name Constants and macros for entire MCM_PLASC register
*/
/*@{*/
#define HW_MCM_PLASC_ADDR(x) ((x) + 0x8U)
#define HW_MCM_PLASC(x) (*(__I hw_mcm_plasc_t *) HW_MCM_PLASC_ADDR(x))
#define HW_MCM_PLASC_RD(x) (HW_MCM_PLASC(x).U)
/*@}*/
/*
* Constants & macros for individual MCM_PLASC bitfields
*/
/*!
* @name Register MCM_PLASC, field ASC[7:0] (RO)
*
* Values:
* - 0 - A bus slave connection to AXBS input port n is absent
* - 1 - A bus slave connection to AXBS input port n is present
*/
/*@{*/
#define BP_MCM_PLASC_ASC (0U) /*!< Bit position for MCM_PLASC_ASC. */
#define BM_MCM_PLASC_ASC (0x00FFU) /*!< Bit mask for MCM_PLASC_ASC. */
#define BS_MCM_PLASC_ASC (8U) /*!< Bit field size in bits for MCM_PLASC_ASC. */
/*! @brief Read current value of the MCM_PLASC_ASC field. */
#define BR_MCM_PLASC_ASC(x) (HW_MCM_PLASC(x).B.ASC)
/*@}*/
/*******************************************************************************
* HW_MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration
******************************************************************************/
/*!
* @brief HW_MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration (RO)
*
* Reset value: 0x0017U
*
* PLAMC is a 16-bit read-only register identifying the presence/absence of bus
* master connections to the device's crossbar switch.
*/
typedef union _hw_mcm_plamc
{
uint16_t U;
struct _hw_mcm_plamc_bitfields
{
uint16_t AMC : 8; /*!< [7:0] Each bit in the AMC field indicates
* whether there is a corresponding connection to the AXBS master input port. */
uint16_t RESERVED0 : 8; /*!< [15:8] */
} B;
} hw_mcm_plamc_t;
/*!
* @name Constants and macros for entire MCM_PLAMC register
*/
/*@{*/
#define HW_MCM_PLAMC_ADDR(x) ((x) + 0xAU)
#define HW_MCM_PLAMC(x) (*(__I hw_mcm_plamc_t *) HW_MCM_PLAMC_ADDR(x))
#define HW_MCM_PLAMC_RD(x) (HW_MCM_PLAMC(x).U)
/*@}*/
/*
* Constants & macros for individual MCM_PLAMC bitfields
*/
/*!
* @name Register MCM_PLAMC, field AMC[7:0] (RO)
*
* Values:
* - 0 - A bus master connection to AXBS input port n is absent
* - 1 - A bus master connection to AXBS input port n is present
*/
/*@{*/
#define BP_MCM_PLAMC_AMC (0U) /*!< Bit position for MCM_PLAMC_AMC. */
#define BM_MCM_PLAMC_AMC (0x00FFU) /*!< Bit mask for MCM_PLAMC_AMC. */
#define BS_MCM_PLAMC_AMC (8U) /*!< Bit field size in bits for MCM_PLAMC_AMC. */
/*! @brief Read current value of the MCM_PLAMC_AMC field. */
#define BR_MCM_PLAMC_AMC(x) (HW_MCM_PLAMC(x).B.AMC)
/*@}*/
/*******************************************************************************
* HW_MCM_PLACR - Crossbar Switch (AXBS) Control Register
******************************************************************************/
/*!
* @brief HW_MCM_PLACR - Crossbar Switch (AXBS) Control Register (RW)
*
* Reset value: 0x00000000U
*
* The PLACR register selects the arbitration policy for the crossbar masters.
*/
typedef union _hw_mcm_placr
{
uint32_t U;
struct _hw_mcm_placr_bitfields
{
uint32_t RESERVED0 : 9; /*!< [8:0] */
uint32_t ARB : 1; /*!< [9] Arbitration select */
uint32_t RESERVED1 : 22; /*!< [31:10] */
} B;
} hw_mcm_placr_t;
/*!
* @name Constants and macros for entire MCM_PLACR register
*/
/*@{*/
#define HW_MCM_PLACR_ADDR(x) ((x) + 0xCU)
#define HW_MCM_PLACR(x) (*(__IO hw_mcm_placr_t *) HW_MCM_PLACR_ADDR(x))
#define HW_MCM_PLACR_RD(x) (HW_MCM_PLACR(x).U)
#define HW_MCM_PLACR_WR(x, v) (HW_MCM_PLACR(x).U = (v))
#define HW_MCM_PLACR_SET(x, v) (HW_MCM_PLACR_WR(x, HW_MCM_PLACR_RD(x) | (v)))
#define HW_MCM_PLACR_CLR(x, v) (HW_MCM_PLACR_WR(x, HW_MCM_PLACR_RD(x) & ~(v)))
#define HW_MCM_PLACR_TOG(x, v) (HW_MCM_PLACR_WR(x, HW_MCM_PLACR_RD(x) ^ (v)))
/*@}*/
/*
* Constants & macros for individual MCM_PLACR bitfields
*/
/*!
* @name Register MCM_PLACR, field ARB[9] (RW)
*
* Values:
* - 0 - Fixed-priority arbitration for the crossbar masters
* - 1 - Round-robin arbitration for the crossbar masters
*/
/*@{*/
#define BP_MCM_PLACR_ARB (9U) /*!< Bit position for MCM_PLACR_ARB. */
#define BM_MCM_PLACR_ARB (0x00000200U) /*!< Bit mask for MCM_PLACR_ARB. */
#define BS_MCM_PLACR_ARB (1U) /*!< Bit field size in bits for MCM_PLACR_ARB. */
/*! @brief Read current value of the MCM_PLACR_ARB field. */
#define BR_MCM_PLACR_ARB(x) (HW_MCM_PLACR(x).B.ARB)
/*! @brief Format value for bitfield MCM_PLACR_ARB. */
#define BF_MCM_PLACR_ARB(v) ((uint32_t)((uint32_t)(v) << BP_MCM_PLACR_ARB) & BM_MCM_PLACR_ARB)
/*! @brief Set the ARB field to a new value. */
#define BW_MCM_PLACR_ARB(x, v) (HW_MCM_PLACR_WR(x, (HW_MCM_PLACR_RD(x) & ~BM_MCM_PLACR_ARB) | BF_MCM_PLACR_ARB(v)))
/*@}*/
/*******************************************************************************
* HW_MCM_ISCR - Interrupt Status and Control Register
******************************************************************************/
/*!
* @brief HW_MCM_ISCR - Interrupt Status and Control Register (RW)
*
* Reset value: 0x00020000U
*
* The MCM_ISCR register includes the enable and status bits associated with the
* core's floating-point exceptions. The individual event indicators are first
* qualified with their exception enables and then logically summed to form an
* interrupt request sent to the core's NVIC. Bits 15-8 are read-only indicator
* flags based on the processor's FPSCR register. Attempted writes to these bits are
* ignored. Once set, the flags remain asserted until software clears the
* corresponding FPSCR bit.
*/
typedef union _hw_mcm_iscr
{
uint32_t U;
struct _hw_mcm_iscr_bitfields
{
uint32_t RESERVED0 : 8; /*!< [7:0] */
uint32_t FIOC : 1; /*!< [8] FPU invalid operation interrupt status */
uint32_t FDZC : 1; /*!< [9] FPU divide-by-zero interrupt status */
uint32_t FOFC : 1; /*!< [10] FPU overflow interrupt status */
uint32_t FUFC : 1; /*!< [11] FPU underflow interrupt status */
uint32_t FIXC : 1; /*!< [12] FPU inexact interrupt status */
uint32_t RESERVED1 : 2; /*!< [14:13] */
uint32_t FIDC : 1; /*!< [15] FPU input denormal interrupt status */
uint32_t RESERVED2 : 8; /*!< [23:16] */
uint32_t FIOCE : 1; /*!< [24] FPU invalid operation interrupt enable
* */
uint32_t FDZCE : 1; /*!< [25] FPU divide-by-zero interrupt enable */
uint32_t FOFCE : 1; /*!< [26] FPU overflow interrupt enable */
uint32_t FUFCE : 1; /*!< [27] FPU underflow interrupt enable */
uint32_t FIXCE : 1; /*!< [28] FPU inexact interrupt enable */
uint32_t RESERVED3 : 2; /*!< [30:29] */
uint32_t FIDCE : 1; /*!< [31] FPU input denormal interrupt enable */
} B;
} hw_mcm_iscr_t;
/*!
* @name Constants and macros for entire MCM_ISCR register
*/
/*@{*/
#define HW_MCM_ISCR_ADDR(x) ((x) + 0x10U)
#define HW_MCM_ISCR(x) (*(__IO hw_mcm_iscr_t *) HW_MCM_ISCR_ADDR(x))
#define HW_MCM_ISCR_RD(x) (HW_MCM_ISCR(x).U)
#define HW_MCM_ISCR_WR(x, v) (HW_MCM_ISCR(x).U = (v))
#define HW_MCM_ISCR_SET(x, v) (HW_MCM_ISCR_WR(x, HW_MCM_ISCR_RD(x) | (v)))
#define HW_MCM_ISCR_CLR(x, v) (HW_MCM_ISCR_WR(x, HW_MCM_ISCR_RD(x) & ~(v)))
#define HW_MCM_ISCR_TOG(x, v) (HW_MCM_ISCR_WR(x, HW_MCM_ISCR_RD(x) ^ (v)))
/*@}*/
/*
* Constants & macros for individual MCM_ISCR bitfields
*/
/*!
* @name Register MCM_ISCR, field FIOC[8] (RO)
*
* This read-only bit is a copy of the core's FPSCR[IOC] bit and signals an
* illegal operation has been detected in the processor's FPU. Once set, this bit
* remains set until software clears the FPSCR[IOC] bit.
*
* Values:
* - 0 - No interrupt
* - 1 - Interrupt occurred
*/
/*@{*/
#define BP_MCM_ISCR_FIOC (8U) /*!< Bit position for MCM_ISCR_FIOC. */
#define BM_MCM_ISCR_FIOC (0x00000100U) /*!< Bit mask for MCM_ISCR_FIOC. */
#define BS_MCM_ISCR_FIOC (1U) /*!< Bit field size in bits for MCM_ISCR_FIOC. */
/*! @brief Read current value of the MCM_ISCR_FIOC field. */
#define BR_MCM_ISCR_FIOC(x) (HW_MCM_ISCR(x).B.FIOC)
/*@}*/
/*!
* @name Register MCM_ISCR, field FDZC[9] (RO)
*
* This read-only bit is a copy of the core's FPSCR[DZC] bit and signals a
* divide by zero has been detected in the processor's FPU. Once set, this bit remains
* set until software clears the FPSCR[DZC] bit.
*
* Values:
* - 0 - No interrupt
* - 1 - Interrupt occurred
*/
/*@{*/
#define BP_MCM_ISCR_FDZC (9U) /*!< Bit position for MCM_ISCR_FDZC. */
#define BM_MCM_ISCR_FDZC (0x00000200U) /*!< Bit mask for MCM_ISCR_FDZC. */
#define BS_MCM_ISCR_FDZC (1U) /*!< Bit field size in bits for MCM_ISCR_FDZC. */
/*! @brief Read current value of the MCM_ISCR_FDZC field. */
#define BR_MCM_ISCR_FDZC(x) (HW_MCM_ISCR(x).B.FDZC)
/*@}*/
/*!
* @name Register MCM_ISCR, field FOFC[10] (RO)
*
* This read-only bit is a copy of the core's FPSCR[OFC] bit and signals an
* overflow has been detected in the processor's FPU. Once set, this bit remains set
* until software clears the FPSCR[OFC] bit.
*
* Values:
* - 0 - No interrupt
* - 1 - Interrupt occurred
*/
/*@{*/
#define BP_MCM_ISCR_FOFC (10U) /*!< Bit position for MCM_ISCR_FOFC. */
#define BM_MCM_ISCR_FOFC (0x00000400U) /*!< Bit mask for MCM_ISCR_FOFC. */
#define BS_MCM_ISCR_FOFC (1U) /*!< Bit field size in bits for MCM_ISCR_FOFC. */
/*! @brief Read current value of the MCM_ISCR_FOFC field. */
#define BR_MCM_ISCR_FOFC(x) (HW_MCM_ISCR(x).B.FOFC)
/*@}*/
/*!
* @name Register MCM_ISCR, field FUFC[11] (RO)
*
* This read-only bit is a copy of the core's FPSCR[UFC] bit and signals an
* underflow has been detected in the processor's FPU. Once set, this bit remains set
* until software clears the FPSCR[UFC] bit.
*
* Values:
* - 0 - No interrupt
* - 1 - Interrupt occurred
*/
/*@{*/
#define BP_MCM_ISCR_FUFC (11U) /*!< Bit position for MCM_ISCR_FUFC. */
#define BM_MCM_ISCR_FUFC (0x00000800U) /*!< Bit mask for MCM_ISCR_FUFC. */
#define BS_MCM_ISCR_FUFC (1U) /*!< Bit field size in bits for MCM_ISCR_FUFC. */
/*! @brief Read current value of the MCM_ISCR_FUFC field. */
#define BR_MCM_ISCR_FUFC(x) (HW_MCM_ISCR(x).B.FUFC)
/*@}*/
/*!
* @name Register MCM_ISCR, field FIXC[12] (RO)
*
* This read-only bit is a copy of the core's FPSCR[IXC] bit and signals an
* inexact number has been detected in the processor's FPU. Once set, this bit
* remains set until software clears the FPSCR[IXC] bit.
*
* Values:
* - 0 - No interrupt
* - 1 - Interrupt occurred
*/
/*@{*/
#define BP_MCM_ISCR_FIXC (12U) /*!< Bit position for MCM_ISCR_FIXC. */
#define BM_MCM_ISCR_FIXC (0x00001000U) /*!< Bit mask for MCM_ISCR_FIXC. */
#define BS_MCM_ISCR_FIXC (1U) /*!< Bit field size in bits for MCM_ISCR_FIXC. */
/*! @brief Read current value of the MCM_ISCR_FIXC field. */
#define BR_MCM_ISCR_FIXC(x) (HW_MCM_ISCR(x).B.FIXC)
/*@}*/
/*!
* @name Register MCM_ISCR, field FIDC[15] (RO)
*
* This read-only bit is a copy of the core's FPSCR[IDC] bit and signals input
* denormalized number has been detected in the processor's FPU. Once set, this
* bit remains set until software clears the FPSCR[IDC] bit.
*
* Values:
* - 0 - No interrupt
* - 1 - Interrupt occurred
*/
/*@{*/
#define BP_MCM_ISCR_FIDC (15U) /*!< Bit position for MCM_ISCR_FIDC. */
#define BM_MCM_ISCR_FIDC (0x00008000U) /*!< Bit mask for MCM_ISCR_FIDC. */
#define BS_MCM_ISCR_FIDC (1U) /*!< Bit field size in bits for MCM_ISCR_FIDC. */
/*! @brief Read current value of the MCM_ISCR_FIDC field. */
#define BR_MCM_ISCR_FIDC(x) (HW_MCM_ISCR(x).B.FIDC)
/*@}*/
/*!
* @name Register MCM_ISCR, field FIOCE[24] (RW)
*
* Values:
* - 0 - Disable interrupt
* - 1 - Enable interrupt
*/
/*@{*/
#define BP_MCM_ISCR_FIOCE (24U) /*!< Bit position for MCM_ISCR_FIOCE. */
#define BM_MCM_ISCR_FIOCE (0x01000000U) /*!< Bit mask for MCM_ISCR_FIOCE. */
#define BS_MCM_ISCR_FIOCE (1U) /*!< Bit field size in bits for MCM_ISCR_FIOCE. */
/*! @brief Read current value of the MCM_ISCR_FIOCE field. */
#define BR_MCM_ISCR_FIOCE(x) (HW_MCM_ISCR(x).B.FIOCE)
/*! @brief Format value for bitfield MCM_ISCR_FIOCE. */
#define BF_MCM_ISCR_FIOCE(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_FIOCE) & BM_MCM_ISCR_FIOCE)
/*! @brief Set the FIOCE field to a new value. */
#define BW_MCM_ISCR_FIOCE(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_FIOCE) | BF_MCM_ISCR_FIOCE(v)))
/*@}*/
/*!
* @name Register MCM_ISCR, field FDZCE[25] (RW)
*
* Values:
* - 0 - Disable interrupt
* - 1 - Enable interrupt
*/
/*@{*/
#define BP_MCM_ISCR_FDZCE (25U) /*!< Bit position for MCM_ISCR_FDZCE. */
#define BM_MCM_ISCR_FDZCE (0x02000000U) /*!< Bit mask for MCM_ISCR_FDZCE. */
#define BS_MCM_ISCR_FDZCE (1U) /*!< Bit field size in bits for MCM_ISCR_FDZCE. */
/*! @brief Read current value of the MCM_ISCR_FDZCE field. */
#define BR_MCM_ISCR_FDZCE(x) (HW_MCM_ISCR(x).B.FDZCE)
/*! @brief Format value for bitfield MCM_ISCR_FDZCE. */
#define BF_MCM_ISCR_FDZCE(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_FDZCE) & BM_MCM_ISCR_FDZCE)
/*! @brief Set the FDZCE field to a new value. */
#define BW_MCM_ISCR_FDZCE(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_FDZCE) | BF_MCM_ISCR_FDZCE(v)))
/*@}*/
/*!
* @name Register MCM_ISCR, field FOFCE[26] (RW)
*
* Values:
* - 0 - Disable interrupt
* - 1 - Enable interrupt
*/
/*@{*/
#define BP_MCM_ISCR_FOFCE (26U) /*!< Bit position for MCM_ISCR_FOFCE. */
#define BM_MCM_ISCR_FOFCE (0x04000000U) /*!< Bit mask for MCM_ISCR_FOFCE. */
#define BS_MCM_ISCR_FOFCE (1U) /*!< Bit field size in bits for MCM_ISCR_FOFCE. */
/*! @brief Read current value of the MCM_ISCR_FOFCE field. */
#define BR_MCM_ISCR_FOFCE(x) (HW_MCM_ISCR(x).B.FOFCE)
/*! @brief Format value for bitfield MCM_ISCR_FOFCE. */
#define BF_MCM_ISCR_FOFCE(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_FOFCE) & BM_MCM_ISCR_FOFCE)
/*! @brief Set the FOFCE field to a new value. */
#define BW_MCM_ISCR_FOFCE(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_FOFCE) | BF_MCM_ISCR_FOFCE(v)))
/*@}*/
/*!
* @name Register MCM_ISCR, field FUFCE[27] (RW)
*
* Values:
* - 0 - Disable interrupt
* - 1 - Enable interrupt
*/
/*@{*/
#define BP_MCM_ISCR_FUFCE (27U) /*!< Bit position for MCM_ISCR_FUFCE. */
#define BM_MCM_ISCR_FUFCE (0x08000000U) /*!< Bit mask for MCM_ISCR_FUFCE. */
#define BS_MCM_ISCR_FUFCE (1U) /*!< Bit field size in bits for MCM_ISCR_FUFCE. */
/*! @brief Read current value of the MCM_ISCR_FUFCE field. */
#define BR_MCM_ISCR_FUFCE(x) (HW_MCM_ISCR(x).B.FUFCE)
/*! @brief Format value for bitfield MCM_ISCR_FUFCE. */
#define BF_MCM_ISCR_FUFCE(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_FUFCE) & BM_MCM_ISCR_FUFCE)
/*! @brief Set the FUFCE field to a new value. */
#define BW_MCM_ISCR_FUFCE(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_FUFCE) | BF_MCM_ISCR_FUFCE(v)))
/*@}*/
/*!
* @name Register MCM_ISCR, field FIXCE[28] (RW)
*
* Values:
* - 0 - Disable interrupt
* - 1 - Enable interrupt
*/
/*@{*/
#define BP_MCM_ISCR_FIXCE (28U) /*!< Bit position for MCM_ISCR_FIXCE. */
#define BM_MCM_ISCR_FIXCE (0x10000000U) /*!< Bit mask for MCM_ISCR_FIXCE. */
#define BS_MCM_ISCR_FIXCE (1U) /*!< Bit field size in bits for MCM_ISCR_FIXCE. */
/*! @brief Read current value of the MCM_ISCR_FIXCE field. */
#define BR_MCM_ISCR_FIXCE(x) (HW_MCM_ISCR(x).B.FIXCE)
/*! @brief Format value for bitfield MCM_ISCR_FIXCE. */
#define BF_MCM_ISCR_FIXCE(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_FIXCE) & BM_MCM_ISCR_FIXCE)
/*! @brief Set the FIXCE field to a new value. */
#define BW_MCM_ISCR_FIXCE(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_FIXCE) | BF_MCM_ISCR_FIXCE(v)))
/*@}*/
/*!
* @name Register MCM_ISCR, field FIDCE[31] (RW)
*
* Values:
* - 0 - Disable interrupt
* - 1 - Enable interrupt
*/
/*@{*/
#define BP_MCM_ISCR_FIDCE (31U) /*!< Bit position for MCM_ISCR_FIDCE. */
#define BM_MCM_ISCR_FIDCE (0x80000000U) /*!< Bit mask for MCM_ISCR_FIDCE. */
#define BS_MCM_ISCR_FIDCE (1U) /*!< Bit field size in bits for MCM_ISCR_FIDCE. */
/*! @brief Read current value of the MCM_ISCR_FIDCE field. */
#define BR_MCM_ISCR_FIDCE(x) (HW_MCM_ISCR(x).B.FIDCE)
/*! @brief Format value for bitfield MCM_ISCR_FIDCE. */
#define BF_MCM_ISCR_FIDCE(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_FIDCE) & BM_MCM_ISCR_FIDCE)
/*! @brief Set the FIDCE field to a new value. */
#define BW_MCM_ISCR_FIDCE(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_FIDCE) | BF_MCM_ISCR_FIDCE(v)))
/*@}*/
/*******************************************************************************
* HW_MCM_CPO - Compute Operation Control Register
******************************************************************************/
/*!
* @brief HW_MCM_CPO - Compute Operation Control Register (RW)
*
* Reset value: 0x00000000U
*
* This register controls the Compute Operation.
*/
typedef union _hw_mcm_cpo
{
uint32_t U;
struct _hw_mcm_cpo_bitfields
{
uint32_t CPOREQ : 1; /*!< [0] Compute Operation request */
uint32_t CPOACK : 1; /*!< [1] Compute Operation acknowledge */
uint32_t CPOWOI : 1; /*!< [2] Compute Operation wakeup on interrupt */
uint32_t RESERVED0 : 29; /*!< [31:3] */
} B;
} hw_mcm_cpo_t;
/*!
* @name Constants and macros for entire MCM_CPO register
*/
/*@{*/
#define HW_MCM_CPO_ADDR(x) ((x) + 0x40U)
#define HW_MCM_CPO(x) (*(__IO hw_mcm_cpo_t *) HW_MCM_CPO_ADDR(x))
#define HW_MCM_CPO_RD(x) (HW_MCM_CPO(x).U)
#define HW_MCM_CPO_WR(x, v) (HW_MCM_CPO(x).U = (v))
#define HW_MCM_CPO_SET(x, v) (HW_MCM_CPO_WR(x, HW_MCM_CPO_RD(x) | (v)))
#define HW_MCM_CPO_CLR(x, v) (HW_MCM_CPO_WR(x, HW_MCM_CPO_RD(x) & ~(v)))
#define HW_MCM_CPO_TOG(x, v) (HW_MCM_CPO_WR(x, HW_MCM_CPO_RD(x) ^ (v)))
/*@}*/
/*
* Constants & macros for individual MCM_CPO bitfields
*/
/*!
* @name Register MCM_CPO, field CPOREQ[0] (RW)
*
* This bit is auto-cleared by vector fetching if CPOWOI = 1.
*
* Values:
* - 0 - Request is cleared.
* - 1 - Request Compute Operation.
*/
/*@{*/
#define BP_MCM_CPO_CPOREQ (0U) /*!< Bit position for MCM_CPO_CPOREQ. */
#define BM_MCM_CPO_CPOREQ (0x00000001U) /*!< Bit mask for MCM_CPO_CPOREQ. */
#define BS_MCM_CPO_CPOREQ (1U) /*!< Bit field size in bits for MCM_CPO_CPOREQ. */
/*! @brief Read current value of the MCM_CPO_CPOREQ field. */
#define BR_MCM_CPO_CPOREQ(x) (HW_MCM_CPO(x).B.CPOREQ)
/*! @brief Format value for bitfield MCM_CPO_CPOREQ. */
#define BF_MCM_CPO_CPOREQ(v) ((uint32_t)((uint32_t)(v) << BP_MCM_CPO_CPOREQ) & BM_MCM_CPO_CPOREQ)
/*! @brief Set the CPOREQ field to a new value. */
#define BW_MCM_CPO_CPOREQ(x, v) (HW_MCM_CPO_WR(x, (HW_MCM_CPO_RD(x) & ~BM_MCM_CPO_CPOREQ) | BF_MCM_CPO_CPOREQ(v)))
/*@}*/
/*!
* @name Register MCM_CPO, field CPOACK[1] (RO)
*
* Values:
* - 0 - Compute operation entry has not completed or compute operation exit has
* completed.
* - 1 - Compute operation entry has completed or compute operation exit has not
* completed.
*/
/*@{*/
#define BP_MCM_CPO_CPOACK (1U) /*!< Bit position for MCM_CPO_CPOACK. */
#define BM_MCM_CPO_CPOACK (0x00000002U) /*!< Bit mask for MCM_CPO_CPOACK. */
#define BS_MCM_CPO_CPOACK (1U) /*!< Bit field size in bits for MCM_CPO_CPOACK. */
/*! @brief Read current value of the MCM_CPO_CPOACK field. */
#define BR_MCM_CPO_CPOACK(x) (HW_MCM_CPO(x).B.CPOACK)
/*@}*/
/*!
* @name Register MCM_CPO, field CPOWOI[2] (RW)
*
* Values:
* - 0 - No effect.
* - 1 - When set, the CPOREQ is cleared on any interrupt or exception vector
* fetch.
*/
/*@{*/
#define BP_MCM_CPO_CPOWOI (2U) /*!< Bit position for MCM_CPO_CPOWOI. */
#define BM_MCM_CPO_CPOWOI (0x00000004U) /*!< Bit mask for MCM_CPO_CPOWOI. */
#define BS_MCM_CPO_CPOWOI (1U) /*!< Bit field size in bits for MCM_CPO_CPOWOI. */
/*! @brief Read current value of the MCM_CPO_CPOWOI field. */
#define BR_MCM_CPO_CPOWOI(x) (HW_MCM_CPO(x).B.CPOWOI)
/*! @brief Format value for bitfield MCM_CPO_CPOWOI. */
#define BF_MCM_CPO_CPOWOI(v) ((uint32_t)((uint32_t)(v) << BP_MCM_CPO_CPOWOI) & BM_MCM_CPO_CPOWOI)
/*! @brief Set the CPOWOI field to a new value. */
#define BW_MCM_CPO_CPOWOI(x, v) (HW_MCM_CPO_WR(x, (HW_MCM_CPO_RD(x) & ~BM_MCM_CPO_CPOWOI) | BF_MCM_CPO_CPOWOI(v)))
/*@}*/
/*******************************************************************************
* hw_mcm_t - module struct
******************************************************************************/
/*!
* @brief All MCM module registers.
*/
#pragma pack(1)
typedef struct _hw_mcm
{
uint8_t _reserved0[8];
__I hw_mcm_plasc_t PLASC; /*!< [0x8] Crossbar Switch (AXBS) Slave Configuration */
__I hw_mcm_plamc_t PLAMC; /*!< [0xA] Crossbar Switch (AXBS) Master Configuration */
__IO hw_mcm_placr_t PLACR; /*!< [0xC] Crossbar Switch (AXBS) Control Register */
__IO hw_mcm_iscr_t ISCR; /*!< [0x10] Interrupt Status and Control Register */
uint8_t _reserved1[44];
__IO hw_mcm_cpo_t CPO; /*!< [0x40] Compute Operation Control Register */
} hw_mcm_t;
#pragma pack()
/*! @brief Macro to access all MCM registers. */
/*! @param x MCM module instance base address. */
/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
* use the '&' operator, like <code>&HW_MCM(MCM_BASE)</code>. */
#define HW_MCM(x) (*(hw_mcm_t *)(x))
#endif /* __HW_MCM_REGISTERS_H__ */
/* EOF */

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@ -0,0 +1,869 @@
/*
** ###################################################################
** Compilers: Keil ARM C/C++ Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
** Version: rev. 2.5, 2014-05-06
** Build: b140604
**
** Abstract:
** Extension to the CMSIS register access layer header.
**
** Copyright (c) 2014 Freescale Semiconductor, Inc.
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** Revisions:
** - rev. 1.0 (2013-07-23)
** Initial version.
** - rev. 1.1 (2013-09-17)
** RM rev. 0.4 update.
** - rev. 2.0 (2013-10-29)
** Register accessor macros added to the memory map.
** Symbols for Processor Expert memory map compatibility added to the memory map.
** Startup file for gcc has been updated according to CMSIS 3.2.
** System initialization updated.
** - rev. 2.1 (2013-10-30)
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
** - rev. 2.2 (2013-12-20)
** Update according to reference manual rev. 0.6,
** - rev. 2.3 (2014-01-13)
** Update according to reference manual rev. 0.61,
** - rev. 2.4 (2014-02-10)
** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
** - rev. 2.5 (2014-05-06)
** Update according to reference manual rev. 1.0,
** Update of system and startup files.
** Module access macro module_BASES replaced by module_BASE_PTRS.
**
** ###################################################################
*/
/*
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
*
* This file was generated automatically and any changes may be lost.
*/
#ifndef __HW_NV_REGISTERS_H__
#define __HW_NV_REGISTERS_H__
#include "MK22F51212.h"
#include "fsl_bitaccess.h"
/*
* MK22F51212 NV
*
* Flash configuration field
*
* Registers defined in this header file:
* - HW_NV_BACKKEY3 - Backdoor Comparison Key 3.
* - HW_NV_BACKKEY2 - Backdoor Comparison Key 2.
* - HW_NV_BACKKEY1 - Backdoor Comparison Key 1.
* - HW_NV_BACKKEY0 - Backdoor Comparison Key 0.
* - HW_NV_BACKKEY7 - Backdoor Comparison Key 7.
* - HW_NV_BACKKEY6 - Backdoor Comparison Key 6.
* - HW_NV_BACKKEY5 - Backdoor Comparison Key 5.
* - HW_NV_BACKKEY4 - Backdoor Comparison Key 4.
* - HW_NV_FPROT3 - Non-volatile P-Flash Protection 1 - Low Register
* - HW_NV_FPROT2 - Non-volatile P-Flash Protection 1 - High Register
* - HW_NV_FPROT1 - Non-volatile P-Flash Protection 0 - Low Register
* - HW_NV_FPROT0 - Non-volatile P-Flash Protection 0 - High Register
* - HW_NV_FSEC - Non-volatile Flash Security Register
* - HW_NV_FOPT - Non-volatile Flash Option Register
*
* - hw_nv_t - Struct containing all module registers.
*/
#define HW_NV_INSTANCE_COUNT (1U) /*!< Number of instances of the NV module. */
/*******************************************************************************
* HW_NV_BACKKEY3 - Backdoor Comparison Key 3.
******************************************************************************/
/*!
* @brief HW_NV_BACKKEY3 - Backdoor Comparison Key 3. (RO)
*
* Reset value: 0xFFU
*/
typedef union _hw_nv_backkey3
{
uint8_t U;
struct _hw_nv_backkey3_bitfields
{
uint8_t KEY : 8; /*!< [7:0] Backdoor Comparison Key. */
} B;
} hw_nv_backkey3_t;
/*!
* @name Constants and macros for entire NV_BACKKEY3 register
*/
/*@{*/
#define HW_NV_BACKKEY3_ADDR(x) ((x) + 0x0U)
#define HW_NV_BACKKEY3(x) (*(__I hw_nv_backkey3_t *) HW_NV_BACKKEY3_ADDR(x))
#define HW_NV_BACKKEY3_RD(x) (HW_NV_BACKKEY3(x).U)
/*@}*/
/*
* Constants & macros for individual NV_BACKKEY3 bitfields
*/
/*!
* @name Register NV_BACKKEY3, field KEY[7:0] (RO)
*/
/*@{*/
#define BP_NV_BACKKEY3_KEY (0U) /*!< Bit position for NV_BACKKEY3_KEY. */
#define BM_NV_BACKKEY3_KEY (0xFFU) /*!< Bit mask for NV_BACKKEY3_KEY. */
#define BS_NV_BACKKEY3_KEY (8U) /*!< Bit field size in bits for NV_BACKKEY3_KEY. */
/*! @brief Read current value of the NV_BACKKEY3_KEY field. */
#define BR_NV_BACKKEY3_KEY(x) (HW_NV_BACKKEY3(x).U)
/*@}*/
/*******************************************************************************
* HW_NV_BACKKEY2 - Backdoor Comparison Key 2.
******************************************************************************/
/*!
* @brief HW_NV_BACKKEY2 - Backdoor Comparison Key 2. (RO)
*
* Reset value: 0xFFU
*/
typedef union _hw_nv_backkey2
{
uint8_t U;
struct _hw_nv_backkey2_bitfields
{
uint8_t KEY : 8; /*!< [7:0] Backdoor Comparison Key. */
} B;
} hw_nv_backkey2_t;
/*!
* @name Constants and macros for entire NV_BACKKEY2 register
*/
/*@{*/
#define HW_NV_BACKKEY2_ADDR(x) ((x) + 0x1U)
#define HW_NV_BACKKEY2(x) (*(__I hw_nv_backkey2_t *) HW_NV_BACKKEY2_ADDR(x))
#define HW_NV_BACKKEY2_RD(x) (HW_NV_BACKKEY2(x).U)
/*@}*/
/*
* Constants & macros for individual NV_BACKKEY2 bitfields
*/
/*!
* @name Register NV_BACKKEY2, field KEY[7:0] (RO)
*/
/*@{*/
#define BP_NV_BACKKEY2_KEY (0U) /*!< Bit position for NV_BACKKEY2_KEY. */
#define BM_NV_BACKKEY2_KEY (0xFFU) /*!< Bit mask for NV_BACKKEY2_KEY. */
#define BS_NV_BACKKEY2_KEY (8U) /*!< Bit field size in bits for NV_BACKKEY2_KEY. */
/*! @brief Read current value of the NV_BACKKEY2_KEY field. */
#define BR_NV_BACKKEY2_KEY(x) (HW_NV_BACKKEY2(x).U)
/*@}*/
/*******************************************************************************
* HW_NV_BACKKEY1 - Backdoor Comparison Key 1.
******************************************************************************/
/*!
* @brief HW_NV_BACKKEY1 - Backdoor Comparison Key 1. (RO)
*
* Reset value: 0xFFU
*/
typedef union _hw_nv_backkey1
{
uint8_t U;
struct _hw_nv_backkey1_bitfields
{
uint8_t KEY : 8; /*!< [7:0] Backdoor Comparison Key. */
} B;
} hw_nv_backkey1_t;
/*!
* @name Constants and macros for entire NV_BACKKEY1 register
*/
/*@{*/
#define HW_NV_BACKKEY1_ADDR(x) ((x) + 0x2U)
#define HW_NV_BACKKEY1(x) (*(__I hw_nv_backkey1_t *) HW_NV_BACKKEY1_ADDR(x))
#define HW_NV_BACKKEY1_RD(x) (HW_NV_BACKKEY1(x).U)
/*@}*/
/*
* Constants & macros for individual NV_BACKKEY1 bitfields
*/
/*!
* @name Register NV_BACKKEY1, field KEY[7:0] (RO)
*/
/*@{*/
#define BP_NV_BACKKEY1_KEY (0U) /*!< Bit position for NV_BACKKEY1_KEY. */
#define BM_NV_BACKKEY1_KEY (0xFFU) /*!< Bit mask for NV_BACKKEY1_KEY. */
#define BS_NV_BACKKEY1_KEY (8U) /*!< Bit field size in bits for NV_BACKKEY1_KEY. */
/*! @brief Read current value of the NV_BACKKEY1_KEY field. */
#define BR_NV_BACKKEY1_KEY(x) (HW_NV_BACKKEY1(x).U)
/*@}*/
/*******************************************************************************
* HW_NV_BACKKEY0 - Backdoor Comparison Key 0.
******************************************************************************/
/*!
* @brief HW_NV_BACKKEY0 - Backdoor Comparison Key 0. (RO)
*
* Reset value: 0xFFU
*/
typedef union _hw_nv_backkey0
{
uint8_t U;
struct _hw_nv_backkey0_bitfields
{
uint8_t KEY : 8; /*!< [7:0] Backdoor Comparison Key. */
} B;
} hw_nv_backkey0_t;
/*!
* @name Constants and macros for entire NV_BACKKEY0 register
*/
/*@{*/
#define HW_NV_BACKKEY0_ADDR(x) ((x) + 0x3U)
#define HW_NV_BACKKEY0(x) (*(__I hw_nv_backkey0_t *) HW_NV_BACKKEY0_ADDR(x))
#define HW_NV_BACKKEY0_RD(x) (HW_NV_BACKKEY0(x).U)
/*@}*/
/*
* Constants & macros for individual NV_BACKKEY0 bitfields
*/
/*!
* @name Register NV_BACKKEY0, field KEY[7:0] (RO)
*/
/*@{*/
#define BP_NV_BACKKEY0_KEY (0U) /*!< Bit position for NV_BACKKEY0_KEY. */
#define BM_NV_BACKKEY0_KEY (0xFFU) /*!< Bit mask for NV_BACKKEY0_KEY. */
#define BS_NV_BACKKEY0_KEY (8U) /*!< Bit field size in bits for NV_BACKKEY0_KEY. */
/*! @brief Read current value of the NV_BACKKEY0_KEY field. */
#define BR_NV_BACKKEY0_KEY(x) (HW_NV_BACKKEY0(x).U)
/*@}*/
/*******************************************************************************
* HW_NV_BACKKEY7 - Backdoor Comparison Key 7.
******************************************************************************/
/*!
* @brief HW_NV_BACKKEY7 - Backdoor Comparison Key 7. (RO)
*
* Reset value: 0xFFU
*/
typedef union _hw_nv_backkey7
{
uint8_t U;
struct _hw_nv_backkey7_bitfields
{
uint8_t KEY : 8; /*!< [7:0] Backdoor Comparison Key. */
} B;
} hw_nv_backkey7_t;
/*!
* @name Constants and macros for entire NV_BACKKEY7 register
*/
/*@{*/
#define HW_NV_BACKKEY7_ADDR(x) ((x) + 0x4U)
#define HW_NV_BACKKEY7(x) (*(__I hw_nv_backkey7_t *) HW_NV_BACKKEY7_ADDR(x))
#define HW_NV_BACKKEY7_RD(x) (HW_NV_BACKKEY7(x).U)
/*@}*/
/*
* Constants & macros for individual NV_BACKKEY7 bitfields
*/
/*!
* @name Register NV_BACKKEY7, field KEY[7:0] (RO)
*/
/*@{*/
#define BP_NV_BACKKEY7_KEY (0U) /*!< Bit position for NV_BACKKEY7_KEY. */
#define BM_NV_BACKKEY7_KEY (0xFFU) /*!< Bit mask for NV_BACKKEY7_KEY. */
#define BS_NV_BACKKEY7_KEY (8U) /*!< Bit field size in bits for NV_BACKKEY7_KEY. */
/*! @brief Read current value of the NV_BACKKEY7_KEY field. */
#define BR_NV_BACKKEY7_KEY(x) (HW_NV_BACKKEY7(x).U)
/*@}*/
/*******************************************************************************
* HW_NV_BACKKEY6 - Backdoor Comparison Key 6.
******************************************************************************/
/*!
* @brief HW_NV_BACKKEY6 - Backdoor Comparison Key 6. (RO)
*
* Reset value: 0xFFU
*/
typedef union _hw_nv_backkey6
{
uint8_t U;
struct _hw_nv_backkey6_bitfields
{
uint8_t KEY : 8; /*!< [7:0] Backdoor Comparison Key. */
} B;
} hw_nv_backkey6_t;
/*!
* @name Constants and macros for entire NV_BACKKEY6 register
*/
/*@{*/
#define HW_NV_BACKKEY6_ADDR(x) ((x) + 0x5U)
#define HW_NV_BACKKEY6(x) (*(__I hw_nv_backkey6_t *) HW_NV_BACKKEY6_ADDR(x))
#define HW_NV_BACKKEY6_RD(x) (HW_NV_BACKKEY6(x).U)
/*@}*/
/*
* Constants & macros for individual NV_BACKKEY6 bitfields
*/
/*!
* @name Register NV_BACKKEY6, field KEY[7:0] (RO)
*/
/*@{*/
#define BP_NV_BACKKEY6_KEY (0U) /*!< Bit position for NV_BACKKEY6_KEY. */
#define BM_NV_BACKKEY6_KEY (0xFFU) /*!< Bit mask for NV_BACKKEY6_KEY. */
#define BS_NV_BACKKEY6_KEY (8U) /*!< Bit field size in bits for NV_BACKKEY6_KEY. */
/*! @brief Read current value of the NV_BACKKEY6_KEY field. */
#define BR_NV_BACKKEY6_KEY(x) (HW_NV_BACKKEY6(x).U)
/*@}*/
/*******************************************************************************
* HW_NV_BACKKEY5 - Backdoor Comparison Key 5.
******************************************************************************/
/*!
* @brief HW_NV_BACKKEY5 - Backdoor Comparison Key 5. (RO)
*
* Reset value: 0xFFU
*/
typedef union _hw_nv_backkey5
{
uint8_t U;
struct _hw_nv_backkey5_bitfields
{
uint8_t KEY : 8; /*!< [7:0] Backdoor Comparison Key. */
} B;
} hw_nv_backkey5_t;
/*!
* @name Constants and macros for entire NV_BACKKEY5 register
*/
/*@{*/
#define HW_NV_BACKKEY5_ADDR(x) ((x) + 0x6U)
#define HW_NV_BACKKEY5(x) (*(__I hw_nv_backkey5_t *) HW_NV_BACKKEY5_ADDR(x))
#define HW_NV_BACKKEY5_RD(x) (HW_NV_BACKKEY5(x).U)
/*@}*/
/*
* Constants & macros for individual NV_BACKKEY5 bitfields
*/
/*!
* @name Register NV_BACKKEY5, field KEY[7:0] (RO)
*/
/*@{*/
#define BP_NV_BACKKEY5_KEY (0U) /*!< Bit position for NV_BACKKEY5_KEY. */
#define BM_NV_BACKKEY5_KEY (0xFFU) /*!< Bit mask for NV_BACKKEY5_KEY. */
#define BS_NV_BACKKEY5_KEY (8U) /*!< Bit field size in bits for NV_BACKKEY5_KEY. */
/*! @brief Read current value of the NV_BACKKEY5_KEY field. */
#define BR_NV_BACKKEY5_KEY(x) (HW_NV_BACKKEY5(x).U)
/*@}*/
/*******************************************************************************
* HW_NV_BACKKEY4 - Backdoor Comparison Key 4.
******************************************************************************/
/*!
* @brief HW_NV_BACKKEY4 - Backdoor Comparison Key 4. (RO)
*
* Reset value: 0xFFU
*/
typedef union _hw_nv_backkey4
{
uint8_t U;
struct _hw_nv_backkey4_bitfields
{
uint8_t KEY : 8; /*!< [7:0] Backdoor Comparison Key. */
} B;
} hw_nv_backkey4_t;
/*!
* @name Constants and macros for entire NV_BACKKEY4 register
*/
/*@{*/
#define HW_NV_BACKKEY4_ADDR(x) ((x) + 0x7U)
#define HW_NV_BACKKEY4(x) (*(__I hw_nv_backkey4_t *) HW_NV_BACKKEY4_ADDR(x))
#define HW_NV_BACKKEY4_RD(x) (HW_NV_BACKKEY4(x).U)
/*@}*/
/*
* Constants & macros for individual NV_BACKKEY4 bitfields
*/
/*!
* @name Register NV_BACKKEY4, field KEY[7:0] (RO)
*/
/*@{*/
#define BP_NV_BACKKEY4_KEY (0U) /*!< Bit position for NV_BACKKEY4_KEY. */
#define BM_NV_BACKKEY4_KEY (0xFFU) /*!< Bit mask for NV_BACKKEY4_KEY. */
#define BS_NV_BACKKEY4_KEY (8U) /*!< Bit field size in bits for NV_BACKKEY4_KEY. */
/*! @brief Read current value of the NV_BACKKEY4_KEY field. */
#define BR_NV_BACKKEY4_KEY(x) (HW_NV_BACKKEY4(x).U)
/*@}*/
/*******************************************************************************
* HW_NV_FPROT3 - Non-volatile P-Flash Protection 1 - Low Register
******************************************************************************/
/*!
* @brief HW_NV_FPROT3 - Non-volatile P-Flash Protection 1 - Low Register (RO)
*
* Reset value: 0xFFU
*/
typedef union _hw_nv_fprot3
{
uint8_t U;
struct _hw_nv_fprot3_bitfields
{
uint8_t PROT : 8; /*!< [7:0] P-Flash Region Protect */
} B;
} hw_nv_fprot3_t;
/*!
* @name Constants and macros for entire NV_FPROT3 register
*/
/*@{*/
#define HW_NV_FPROT3_ADDR(x) ((x) + 0x8U)
#define HW_NV_FPROT3(x) (*(__I hw_nv_fprot3_t *) HW_NV_FPROT3_ADDR(x))
#define HW_NV_FPROT3_RD(x) (HW_NV_FPROT3(x).U)
/*@}*/
/*
* Constants & macros for individual NV_FPROT3 bitfields
*/
/*!
* @name Register NV_FPROT3, field PROT[7:0] (RO)
*/
/*@{*/
#define BP_NV_FPROT3_PROT (0U) /*!< Bit position for NV_FPROT3_PROT. */
#define BM_NV_FPROT3_PROT (0xFFU) /*!< Bit mask for NV_FPROT3_PROT. */
#define BS_NV_FPROT3_PROT (8U) /*!< Bit field size in bits for NV_FPROT3_PROT. */
/*! @brief Read current value of the NV_FPROT3_PROT field. */
#define BR_NV_FPROT3_PROT(x) (HW_NV_FPROT3(x).U)
/*@}*/
/*******************************************************************************
* HW_NV_FPROT2 - Non-volatile P-Flash Protection 1 - High Register
******************************************************************************/
/*!
* @brief HW_NV_FPROT2 - Non-volatile P-Flash Protection 1 - High Register (RO)
*
* Reset value: 0xFFU
*/
typedef union _hw_nv_fprot2
{
uint8_t U;
struct _hw_nv_fprot2_bitfields
{
uint8_t PROT : 8; /*!< [7:0] P-Flash Region Protect */
} B;
} hw_nv_fprot2_t;
/*!
* @name Constants and macros for entire NV_FPROT2 register
*/
/*@{*/
#define HW_NV_FPROT2_ADDR(x) ((x) + 0x9U)
#define HW_NV_FPROT2(x) (*(__I hw_nv_fprot2_t *) HW_NV_FPROT2_ADDR(x))
#define HW_NV_FPROT2_RD(x) (HW_NV_FPROT2(x).U)
/*@}*/
/*
* Constants & macros for individual NV_FPROT2 bitfields
*/
/*!
* @name Register NV_FPROT2, field PROT[7:0] (RO)
*/
/*@{*/
#define BP_NV_FPROT2_PROT (0U) /*!< Bit position for NV_FPROT2_PROT. */
#define BM_NV_FPROT2_PROT (0xFFU) /*!< Bit mask for NV_FPROT2_PROT. */
#define BS_NV_FPROT2_PROT (8U) /*!< Bit field size in bits for NV_FPROT2_PROT. */
/*! @brief Read current value of the NV_FPROT2_PROT field. */
#define BR_NV_FPROT2_PROT(x) (HW_NV_FPROT2(x).U)
/*@}*/
/*******************************************************************************
* HW_NV_FPROT1 - Non-volatile P-Flash Protection 0 - Low Register
******************************************************************************/
/*!
* @brief HW_NV_FPROT1 - Non-volatile P-Flash Protection 0 - Low Register (RO)
*
* Reset value: 0xFFU
*/
typedef union _hw_nv_fprot1
{
uint8_t U;
struct _hw_nv_fprot1_bitfields
{
uint8_t PROT : 8; /*!< [7:0] P-Flash Region Protect */
} B;
} hw_nv_fprot1_t;
/*!
* @name Constants and macros for entire NV_FPROT1 register
*/
/*@{*/
#define HW_NV_FPROT1_ADDR(x) ((x) + 0xAU)
#define HW_NV_FPROT1(x) (*(__I hw_nv_fprot1_t *) HW_NV_FPROT1_ADDR(x))
#define HW_NV_FPROT1_RD(x) (HW_NV_FPROT1(x).U)
/*@}*/
/*
* Constants & macros for individual NV_FPROT1 bitfields
*/
/*!
* @name Register NV_FPROT1, field PROT[7:0] (RO)
*/
/*@{*/
#define BP_NV_FPROT1_PROT (0U) /*!< Bit position for NV_FPROT1_PROT. */
#define BM_NV_FPROT1_PROT (0xFFU) /*!< Bit mask for NV_FPROT1_PROT. */
#define BS_NV_FPROT1_PROT (8U) /*!< Bit field size in bits for NV_FPROT1_PROT. */
/*! @brief Read current value of the NV_FPROT1_PROT field. */
#define BR_NV_FPROT1_PROT(x) (HW_NV_FPROT1(x).U)
/*@}*/
/*******************************************************************************
* HW_NV_FPROT0 - Non-volatile P-Flash Protection 0 - High Register
******************************************************************************/
/*!
* @brief HW_NV_FPROT0 - Non-volatile P-Flash Protection 0 - High Register (RO)
*
* Reset value: 0xFFU
*/
typedef union _hw_nv_fprot0
{
uint8_t U;
struct _hw_nv_fprot0_bitfields
{
uint8_t PROT : 8; /*!< [7:0] P-Flash Region Protect */
} B;
} hw_nv_fprot0_t;
/*!
* @name Constants and macros for entire NV_FPROT0 register
*/
/*@{*/
#define HW_NV_FPROT0_ADDR(x) ((x) + 0xBU)
#define HW_NV_FPROT0(x) (*(__I hw_nv_fprot0_t *) HW_NV_FPROT0_ADDR(x))
#define HW_NV_FPROT0_RD(x) (HW_NV_FPROT0(x).U)
/*@}*/
/*
* Constants & macros for individual NV_FPROT0 bitfields
*/
/*!
* @name Register NV_FPROT0, field PROT[7:0] (RO)
*/
/*@{*/
#define BP_NV_FPROT0_PROT (0U) /*!< Bit position for NV_FPROT0_PROT. */
#define BM_NV_FPROT0_PROT (0xFFU) /*!< Bit mask for NV_FPROT0_PROT. */
#define BS_NV_FPROT0_PROT (8U) /*!< Bit field size in bits for NV_FPROT0_PROT. */
/*! @brief Read current value of the NV_FPROT0_PROT field. */
#define BR_NV_FPROT0_PROT(x) (HW_NV_FPROT0(x).U)
/*@}*/
/*******************************************************************************
* HW_NV_FSEC - Non-volatile Flash Security Register
******************************************************************************/
/*!
* @brief HW_NV_FSEC - Non-volatile Flash Security Register (RO)
*
* Reset value: 0xFFU
*
* Allows the user to customize the operation of the MCU at boot time
*/
typedef union _hw_nv_fsec
{
uint8_t U;
struct _hw_nv_fsec_bitfields
{
uint8_t SEC : 2; /*!< [1:0] Flash Security */
uint8_t FSLACC : 2; /*!< [3:2] Freescale Failure Analysis Access Code
* */
uint8_t MEEN : 2; /*!< [5:4] */
uint8_t KEYEN : 2; /*!< [7:6] Backdoor Key Security Enable */
} B;
} hw_nv_fsec_t;
/*!
* @name Constants and macros for entire NV_FSEC register
*/
/*@{*/
#define HW_NV_FSEC_ADDR(x) ((x) + 0xCU)
#define HW_NV_FSEC(x) (*(__I hw_nv_fsec_t *) HW_NV_FSEC_ADDR(x))
#define HW_NV_FSEC_RD(x) (HW_NV_FSEC(x).U)
/*@}*/
/*
* Constants & macros for individual NV_FSEC bitfields
*/
/*!
* @name Register NV_FSEC, field SEC[1:0] (RO)
*
* Values:
* - 10 - MCU security status is unsecure
* - 11 - MCU security status is secure
*/
/*@{*/
#define BP_NV_FSEC_SEC (0U) /*!< Bit position for NV_FSEC_SEC. */
#define BM_NV_FSEC_SEC (0x03U) /*!< Bit mask for NV_FSEC_SEC. */
#define BS_NV_FSEC_SEC (2U) /*!< Bit field size in bits for NV_FSEC_SEC. */
/*! @brief Read current value of the NV_FSEC_SEC field. */
#define BR_NV_FSEC_SEC(x) (HW_NV_FSEC(x).B.SEC)
/*@}*/
/*!
* @name Register NV_FSEC, field FSLACC[3:2] (RO)
*
* Values:
* - 10 - Freescale factory access denied
* - 11 - Freescale factory access granted
*/
/*@{*/
#define BP_NV_FSEC_FSLACC (2U) /*!< Bit position for NV_FSEC_FSLACC. */
#define BM_NV_FSEC_FSLACC (0x0CU) /*!< Bit mask for NV_FSEC_FSLACC. */
#define BS_NV_FSEC_FSLACC (2U) /*!< Bit field size in bits for NV_FSEC_FSLACC. */
/*! @brief Read current value of the NV_FSEC_FSLACC field. */
#define BR_NV_FSEC_FSLACC(x) (HW_NV_FSEC(x).B.FSLACC)
/*@}*/
/*!
* @name Register NV_FSEC, field MEEN[5:4] (RO)
*
* Values:
* - 10 - Mass erase is disabled
* - 11 - Mass erase is enabled
*/
/*@{*/
#define BP_NV_FSEC_MEEN (4U) /*!< Bit position for NV_FSEC_MEEN. */
#define BM_NV_FSEC_MEEN (0x30U) /*!< Bit mask for NV_FSEC_MEEN. */
#define BS_NV_FSEC_MEEN (2U) /*!< Bit field size in bits for NV_FSEC_MEEN. */
/*! @brief Read current value of the NV_FSEC_MEEN field. */
#define BR_NV_FSEC_MEEN(x) (HW_NV_FSEC(x).B.MEEN)
/*@}*/
/*!
* @name Register NV_FSEC, field KEYEN[7:6] (RO)
*
* Values:
* - 10 - Backdoor key access enabled
* - 11 - Backdoor key access disabled
*/
/*@{*/
#define BP_NV_FSEC_KEYEN (6U) /*!< Bit position for NV_FSEC_KEYEN. */
#define BM_NV_FSEC_KEYEN (0xC0U) /*!< Bit mask for NV_FSEC_KEYEN. */
#define BS_NV_FSEC_KEYEN (2U) /*!< Bit field size in bits for NV_FSEC_KEYEN. */
/*! @brief Read current value of the NV_FSEC_KEYEN field. */
#define BR_NV_FSEC_KEYEN(x) (HW_NV_FSEC(x).B.KEYEN)
/*@}*/
/*******************************************************************************
* HW_NV_FOPT - Non-volatile Flash Option Register
******************************************************************************/
/*!
* @brief HW_NV_FOPT - Non-volatile Flash Option Register (RO)
*
* Reset value: 0xFFU
*/
typedef union _hw_nv_fopt
{
uint8_t U;
struct _hw_nv_fopt_bitfields
{
uint8_t LPBOOT : 1; /*!< [0] */
uint8_t EZPORT_DIS : 1; /*!< [1] */
uint8_t NMI_DIS : 1; /*!< [2] */
uint8_t RESERVED0 : 2; /*!< [4:3] */
uint8_t FAST_INIT : 1; /*!< [5] */
uint8_t RESERVED1 : 2; /*!< [7:6] */
} B;
} hw_nv_fopt_t;
/*!
* @name Constants and macros for entire NV_FOPT register
*/
/*@{*/
#define HW_NV_FOPT_ADDR(x) ((x) + 0xDU)
#define HW_NV_FOPT(x) (*(__I hw_nv_fopt_t *) HW_NV_FOPT_ADDR(x))
#define HW_NV_FOPT_RD(x) (HW_NV_FOPT(x).U)
/*@}*/
/*
* Constants & macros for individual NV_FOPT bitfields
*/
/*!
* @name Register NV_FOPT, field LPBOOT[0] (RO)
*
* Values:
* - 00 - Low-power boot
* - 01 - Normal boot
*/
/*@{*/
#define BP_NV_FOPT_LPBOOT (0U) /*!< Bit position for NV_FOPT_LPBOOT. */
#define BM_NV_FOPT_LPBOOT (0x01U) /*!< Bit mask for NV_FOPT_LPBOOT. */
#define BS_NV_FOPT_LPBOOT (1U) /*!< Bit field size in bits for NV_FOPT_LPBOOT. */
/*! @brief Read current value of the NV_FOPT_LPBOOT field. */
#define BR_NV_FOPT_LPBOOT(x) (BITBAND_ACCESS8(HW_NV_FOPT_ADDR(x), BP_NV_FOPT_LPBOOT))
/*@}*/
/*!
* @name Register NV_FOPT, field EZPORT_DIS[1] (RO)
*/
/*@{*/
#define BP_NV_FOPT_EZPORT_DIS (1U) /*!< Bit position for NV_FOPT_EZPORT_DIS. */
#define BM_NV_FOPT_EZPORT_DIS (0x02U) /*!< Bit mask for NV_FOPT_EZPORT_DIS. */
#define BS_NV_FOPT_EZPORT_DIS (1U) /*!< Bit field size in bits for NV_FOPT_EZPORT_DIS. */
/*! @brief Read current value of the NV_FOPT_EZPORT_DIS field. */
#define BR_NV_FOPT_EZPORT_DIS(x) (BITBAND_ACCESS8(HW_NV_FOPT_ADDR(x), BP_NV_FOPT_EZPORT_DIS))
/*@}*/
/*!
* @name Register NV_FOPT, field NMI_DIS[2] (RO)
*
* Values:
* - 00 - NMI interrupts are always blocked
* - 01 - NMI_b pin/interrupts reset default to enabled
*/
/*@{*/
#define BP_NV_FOPT_NMI_DIS (2U) /*!< Bit position for NV_FOPT_NMI_DIS. */
#define BM_NV_FOPT_NMI_DIS (0x04U) /*!< Bit mask for NV_FOPT_NMI_DIS. */
#define BS_NV_FOPT_NMI_DIS (1U) /*!< Bit field size in bits for NV_FOPT_NMI_DIS. */
/*! @brief Read current value of the NV_FOPT_NMI_DIS field. */
#define BR_NV_FOPT_NMI_DIS(x) (BITBAND_ACCESS8(HW_NV_FOPT_ADDR(x), BP_NV_FOPT_NMI_DIS))
/*@}*/
/*!
* @name Register NV_FOPT, field FAST_INIT[5] (RO)
*
* Values:
* - 00 - Slower initialization
* - 01 - Fast Initialization
*/
/*@{*/
#define BP_NV_FOPT_FAST_INIT (5U) /*!< Bit position for NV_FOPT_FAST_INIT. */
#define BM_NV_FOPT_FAST_INIT (0x20U) /*!< Bit mask for NV_FOPT_FAST_INIT. */
#define BS_NV_FOPT_FAST_INIT (1U) /*!< Bit field size in bits for NV_FOPT_FAST_INIT. */
/*! @brief Read current value of the NV_FOPT_FAST_INIT field. */
#define BR_NV_FOPT_FAST_INIT(x) (BITBAND_ACCESS8(HW_NV_FOPT_ADDR(x), BP_NV_FOPT_FAST_INIT))
/*@}*/
/*******************************************************************************
* hw_nv_t - module struct
******************************************************************************/
/*!
* @brief All NV module registers.
*/
#pragma pack(1)
typedef struct _hw_nv
{
__I hw_nv_backkey3_t BACKKEY3; /*!< [0x0] Backdoor Comparison Key 3. */
__I hw_nv_backkey2_t BACKKEY2; /*!< [0x1] Backdoor Comparison Key 2. */
__I hw_nv_backkey1_t BACKKEY1; /*!< [0x2] Backdoor Comparison Key 1. */
__I hw_nv_backkey0_t BACKKEY0; /*!< [0x3] Backdoor Comparison Key 0. */
__I hw_nv_backkey7_t BACKKEY7; /*!< [0x4] Backdoor Comparison Key 7. */
__I hw_nv_backkey6_t BACKKEY6; /*!< [0x5] Backdoor Comparison Key 6. */
__I hw_nv_backkey5_t BACKKEY5; /*!< [0x6] Backdoor Comparison Key 5. */
__I hw_nv_backkey4_t BACKKEY4; /*!< [0x7] Backdoor Comparison Key 4. */
__I hw_nv_fprot3_t FPROT3; /*!< [0x8] Non-volatile P-Flash Protection 1 - Low Register */
__I hw_nv_fprot2_t FPROT2; /*!< [0x9] Non-volatile P-Flash Protection 1 - High Register */
__I hw_nv_fprot1_t FPROT1; /*!< [0xA] Non-volatile P-Flash Protection 0 - Low Register */
__I hw_nv_fprot0_t FPROT0; /*!< [0xB] Non-volatile P-Flash Protection 0 - High Register */
__I hw_nv_fsec_t FSEC; /*!< [0xC] Non-volatile Flash Security Register */
__I hw_nv_fopt_t FOPT; /*!< [0xD] Non-volatile Flash Option Register */
} hw_nv_t;
#pragma pack()
/*! @brief Macro to access all NV registers. */
/*! @param x NV module instance base address. */
/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
* use the '&' operator, like <code>&HW_NV(FTFA_FlashConfig_BASE)</code>. */
#define HW_NV(x) (*(hw_nv_t *)(x))
#endif /* __HW_NV_REGISTERS_H__ */
/* EOF */

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/*
** ###################################################################
** Compilers: Keil ARM C/C++ Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
** Version: rev. 2.5, 2014-05-06
** Build: b140604
**
** Abstract:
** Extension to the CMSIS register access layer header.
**
** Copyright (c) 2014 Freescale Semiconductor, Inc.
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** Revisions:
** - rev. 1.0 (2013-07-23)
** Initial version.
** - rev. 1.1 (2013-09-17)
** RM rev. 0.4 update.
** - rev. 2.0 (2013-10-29)
** Register accessor macros added to the memory map.
** Symbols for Processor Expert memory map compatibility added to the memory map.
** Startup file for gcc has been updated according to CMSIS 3.2.
** System initialization updated.
** - rev. 2.1 (2013-10-30)
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
** - rev. 2.2 (2013-12-20)
** Update according to reference manual rev. 0.6,
** - rev. 2.3 (2014-01-13)
** Update according to reference manual rev. 0.61,
** - rev. 2.4 (2014-02-10)
** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
** - rev. 2.5 (2014-05-06)
** Update according to reference manual rev. 1.0,
** Update of system and startup files.
** Module access macro module_BASES replaced by module_BASE_PTRS.
**
** ###################################################################
*/
/*
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
*
* This file was generated automatically and any changes may be lost.
*/
#ifndef __HW_OSC_REGISTERS_H__
#define __HW_OSC_REGISTERS_H__
#include "MK22F51212.h"
#include "fsl_bitaccess.h"
/*
* MK22F51212 OSC
*
* Oscillator
*
* Registers defined in this header file:
* - HW_OSC_CR - OSC Control Register
* - HW_OSC_DIV - OSC_DIV
*
* - hw_osc_t - Struct containing all module registers.
*/
#define HW_OSC_INSTANCE_COUNT (1U) /*!< Number of instances of the OSC module. */
/*******************************************************************************
* HW_OSC_CR - OSC Control Register
******************************************************************************/
/*!
* @brief HW_OSC_CR - OSC Control Register (RW)
*
* Reset value: 0x00U
*
* After OSC is enabled and starts generating the clocks, the configurations
* such as low power and frequency range, must not be changed.
*/
typedef union _hw_osc_cr
{
uint8_t U;
struct _hw_osc_cr_bitfields
{
uint8_t SC16P : 1; /*!< [0] Oscillator 16 pF Capacitor Load Configure
* */
uint8_t SC8P : 1; /*!< [1] Oscillator 8 pF Capacitor Load Configure */
uint8_t SC4P : 1; /*!< [2] Oscillator 4 pF Capacitor Load Configure */
uint8_t SC2P : 1; /*!< [3] Oscillator 2 pF Capacitor Load Configure */
uint8_t RESERVED0 : 1; /*!< [4] */
uint8_t EREFSTEN : 1; /*!< [5] External Reference Stop Enable */
uint8_t RESERVED1 : 1; /*!< [6] */
uint8_t ERCLKEN : 1; /*!< [7] External Reference Enable */
} B;
} hw_osc_cr_t;
/*!
* @name Constants and macros for entire OSC_CR register
*/
/*@{*/
#define HW_OSC_CR_ADDR(x) ((x) + 0x0U)
#define HW_OSC_CR(x) (*(__IO hw_osc_cr_t *) HW_OSC_CR_ADDR(x))
#define HW_OSC_CR_RD(x) (HW_OSC_CR(x).U)
#define HW_OSC_CR_WR(x, v) (HW_OSC_CR(x).U = (v))
#define HW_OSC_CR_SET(x, v) (HW_OSC_CR_WR(x, HW_OSC_CR_RD(x) | (v)))
#define HW_OSC_CR_CLR(x, v) (HW_OSC_CR_WR(x, HW_OSC_CR_RD(x) & ~(v)))
#define HW_OSC_CR_TOG(x, v) (HW_OSC_CR_WR(x, HW_OSC_CR_RD(x) ^ (v)))
/*@}*/
/*
* Constants & macros for individual OSC_CR bitfields
*/
/*!
* @name Register OSC_CR, field SC16P[0] (RW)
*
* Configures the oscillator load.
*
* Values:
* - 0 - Disable the selection.
* - 1 - Add 16 pF capacitor to the oscillator load.
*/
/*@{*/
#define BP_OSC_CR_SC16P (0U) /*!< Bit position for OSC_CR_SC16P. */
#define BM_OSC_CR_SC16P (0x01U) /*!< Bit mask for OSC_CR_SC16P. */
#define BS_OSC_CR_SC16P (1U) /*!< Bit field size in bits for OSC_CR_SC16P. */
/*! @brief Read current value of the OSC_CR_SC16P field. */
#define BR_OSC_CR_SC16P(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC16P))
/*! @brief Format value for bitfield OSC_CR_SC16P. */
#define BF_OSC_CR_SC16P(v) ((uint8_t)((uint8_t)(v) << BP_OSC_CR_SC16P) & BM_OSC_CR_SC16P)
/*! @brief Set the SC16P field to a new value. */
#define BW_OSC_CR_SC16P(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC16P) = (v))
/*@}*/
/*!
* @name Register OSC_CR, field SC8P[1] (RW)
*
* Configures the oscillator load.
*
* Values:
* - 0 - Disable the selection.
* - 1 - Add 8 pF capacitor to the oscillator load.
*/
/*@{*/
#define BP_OSC_CR_SC8P (1U) /*!< Bit position for OSC_CR_SC8P. */
#define BM_OSC_CR_SC8P (0x02U) /*!< Bit mask for OSC_CR_SC8P. */
#define BS_OSC_CR_SC8P (1U) /*!< Bit field size in bits for OSC_CR_SC8P. */
/*! @brief Read current value of the OSC_CR_SC8P field. */
#define BR_OSC_CR_SC8P(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC8P))
/*! @brief Format value for bitfield OSC_CR_SC8P. */
#define BF_OSC_CR_SC8P(v) ((uint8_t)((uint8_t)(v) << BP_OSC_CR_SC8P) & BM_OSC_CR_SC8P)
/*! @brief Set the SC8P field to a new value. */
#define BW_OSC_CR_SC8P(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC8P) = (v))
/*@}*/
/*!
* @name Register OSC_CR, field SC4P[2] (RW)
*
* Configures the oscillator load.
*
* Values:
* - 0 - Disable the selection.
* - 1 - Add 4 pF capacitor to the oscillator load.
*/
/*@{*/
#define BP_OSC_CR_SC4P (2U) /*!< Bit position for OSC_CR_SC4P. */
#define BM_OSC_CR_SC4P (0x04U) /*!< Bit mask for OSC_CR_SC4P. */
#define BS_OSC_CR_SC4P (1U) /*!< Bit field size in bits for OSC_CR_SC4P. */
/*! @brief Read current value of the OSC_CR_SC4P field. */
#define BR_OSC_CR_SC4P(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC4P))
/*! @brief Format value for bitfield OSC_CR_SC4P. */
#define BF_OSC_CR_SC4P(v) ((uint8_t)((uint8_t)(v) << BP_OSC_CR_SC4P) & BM_OSC_CR_SC4P)
/*! @brief Set the SC4P field to a new value. */
#define BW_OSC_CR_SC4P(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC4P) = (v))
/*@}*/
/*!
* @name Register OSC_CR, field SC2P[3] (RW)
*
* Configures the oscillator load.
*
* Values:
* - 0 - Disable the selection.
* - 1 - Add 2 pF capacitor to the oscillator load.
*/
/*@{*/
#define BP_OSC_CR_SC2P (3U) /*!< Bit position for OSC_CR_SC2P. */
#define BM_OSC_CR_SC2P (0x08U) /*!< Bit mask for OSC_CR_SC2P. */
#define BS_OSC_CR_SC2P (1U) /*!< Bit field size in bits for OSC_CR_SC2P. */
/*! @brief Read current value of the OSC_CR_SC2P field. */
#define BR_OSC_CR_SC2P(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC2P))
/*! @brief Format value for bitfield OSC_CR_SC2P. */
#define BF_OSC_CR_SC2P(v) ((uint8_t)((uint8_t)(v) << BP_OSC_CR_SC2P) & BM_OSC_CR_SC2P)
/*! @brief Set the SC2P field to a new value. */
#define BW_OSC_CR_SC2P(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC2P) = (v))
/*@}*/
/*!
* @name Register OSC_CR, field EREFSTEN[5] (RW)
*
* Controls whether or not the external reference clock (OSCERCLK) remains
* enabled when MCU enters Stop mode.
*
* Values:
* - 0 - External reference clock is disabled in Stop mode.
* - 1 - External reference clock stays enabled in Stop mode if ERCLKEN is set
* before entering Stop mode.
*/
/*@{*/
#define BP_OSC_CR_EREFSTEN (5U) /*!< Bit position for OSC_CR_EREFSTEN. */
#define BM_OSC_CR_EREFSTEN (0x20U) /*!< Bit mask for OSC_CR_EREFSTEN. */
#define BS_OSC_CR_EREFSTEN (1U) /*!< Bit field size in bits for OSC_CR_EREFSTEN. */
/*! @brief Read current value of the OSC_CR_EREFSTEN field. */
#define BR_OSC_CR_EREFSTEN(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_EREFSTEN))
/*! @brief Format value for bitfield OSC_CR_EREFSTEN. */
#define BF_OSC_CR_EREFSTEN(v) ((uint8_t)((uint8_t)(v) << BP_OSC_CR_EREFSTEN) & BM_OSC_CR_EREFSTEN)
/*! @brief Set the EREFSTEN field to a new value. */
#define BW_OSC_CR_EREFSTEN(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_EREFSTEN) = (v))
/*@}*/
/*!
* @name Register OSC_CR, field ERCLKEN[7] (RW)
*
* Enables external reference clock (OSCERCLK).
*
* Values:
* - 0 - External reference clock is inactive.
* - 1 - External reference clock is enabled.
*/
/*@{*/
#define BP_OSC_CR_ERCLKEN (7U) /*!< Bit position for OSC_CR_ERCLKEN. */
#define BM_OSC_CR_ERCLKEN (0x80U) /*!< Bit mask for OSC_CR_ERCLKEN. */
#define BS_OSC_CR_ERCLKEN (1U) /*!< Bit field size in bits for OSC_CR_ERCLKEN. */
/*! @brief Read current value of the OSC_CR_ERCLKEN field. */
#define BR_OSC_CR_ERCLKEN(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_ERCLKEN))
/*! @brief Format value for bitfield OSC_CR_ERCLKEN. */
#define BF_OSC_CR_ERCLKEN(v) ((uint8_t)((uint8_t)(v) << BP_OSC_CR_ERCLKEN) & BM_OSC_CR_ERCLKEN)
/*! @brief Set the ERCLKEN field to a new value. */
#define BW_OSC_CR_ERCLKEN(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_ERCLKEN) = (v))
/*@}*/
/*******************************************************************************
* HW_OSC_DIV - OSC_DIV
******************************************************************************/
/*!
* @brief HW_OSC_DIV - OSC_DIV (RW)
*
* Reset value: 0x00U
*
* OSC CLock divider register.
*/
typedef union _hw_osc_div
{
uint8_t U;
struct _hw_osc_div_bitfields
{
uint8_t RESERVED0 : 6; /*!< [5:0] */
uint8_t ERPS : 2; /*!< [7:6] */
} B;
} hw_osc_div_t;
/*!
* @name Constants and macros for entire OSC_DIV register
*/
/*@{*/
#define HW_OSC_DIV_ADDR(x) ((x) + 0x2U)
#define HW_OSC_DIV(x) (*(__IO hw_osc_div_t *) HW_OSC_DIV_ADDR(x))
#define HW_OSC_DIV_RD(x) (HW_OSC_DIV(x).U)
#define HW_OSC_DIV_WR(x, v) (HW_OSC_DIV(x).U = (v))
#define HW_OSC_DIV_SET(x, v) (HW_OSC_DIV_WR(x, HW_OSC_DIV_RD(x) | (v)))
#define HW_OSC_DIV_CLR(x, v) (HW_OSC_DIV_WR(x, HW_OSC_DIV_RD(x) & ~(v)))
#define HW_OSC_DIV_TOG(x, v) (HW_OSC_DIV_WR(x, HW_OSC_DIV_RD(x) ^ (v)))
/*@}*/
/*
* Constants & macros for individual OSC_DIV bitfields
*/
/*!
* @name Register OSC_DIV, field ERPS[7:6] (RW)
*
* ERCLK prescaler. These two bits are used to divide the ERCLK output. The
* un-divided ERCLK output is not affected by these two bits.
*
* Values:
* - 00 - The divisor ratio is 1.
* - 01 - The divisor ratio is 2.
* - 10 - The divisor ratio is 4.
* - 11 - The divisor ratio is 8.
*/
/*@{*/
#define BP_OSC_DIV_ERPS (6U) /*!< Bit position for OSC_DIV_ERPS. */
#define BM_OSC_DIV_ERPS (0xC0U) /*!< Bit mask for OSC_DIV_ERPS. */
#define BS_OSC_DIV_ERPS (2U) /*!< Bit field size in bits for OSC_DIV_ERPS. */
/*! @brief Read current value of the OSC_DIV_ERPS field. */
#define BR_OSC_DIV_ERPS(x) (HW_OSC_DIV(x).B.ERPS)
/*! @brief Format value for bitfield OSC_DIV_ERPS. */
#define BF_OSC_DIV_ERPS(v) ((uint8_t)((uint8_t)(v) << BP_OSC_DIV_ERPS) & BM_OSC_DIV_ERPS)
/*! @brief Set the ERPS field to a new value. */
#define BW_OSC_DIV_ERPS(x, v) (HW_OSC_DIV_WR(x, (HW_OSC_DIV_RD(x) & ~BM_OSC_DIV_ERPS) | BF_OSC_DIV_ERPS(v)))
/*@}*/
/*******************************************************************************
* hw_osc_t - module struct
******************************************************************************/
/*!
* @brief All OSC module registers.
*/
#pragma pack(1)
typedef struct _hw_osc
{
__IO hw_osc_cr_t CR; /*!< [0x0] OSC Control Register */
uint8_t _reserved0[1];
__IO hw_osc_div_t DIV; /*!< [0x2] OSC_DIV */
} hw_osc_t;
#pragma pack()
/*! @brief Macro to access all OSC registers. */
/*! @param x OSC module instance base address. */
/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
* use the '&' operator, like <code>&HW_OSC(OSC_BASE)</code>. */
#define HW_OSC(x) (*(hw_osc_t *)(x))
#endif /* __HW_OSC_REGISTERS_H__ */
/* EOF */

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/*
** ###################################################################
** Compilers: Keil ARM C/C++ Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
** Version: rev. 2.5, 2014-05-06
** Build: b140604
**
** Abstract:
** Extension to the CMSIS register access layer header.
**
** Copyright (c) 2014 Freescale Semiconductor, Inc.
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** Revisions:
** - rev. 1.0 (2013-07-23)
** Initial version.
** - rev. 1.1 (2013-09-17)
** RM rev. 0.4 update.
** - rev. 2.0 (2013-10-29)
** Register accessor macros added to the memory map.
** Symbols for Processor Expert memory map compatibility added to the memory map.
** Startup file for gcc has been updated according to CMSIS 3.2.
** System initialization updated.
** - rev. 2.1 (2013-10-30)
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
** - rev. 2.2 (2013-12-20)
** Update according to reference manual rev. 0.6,
** - rev. 2.3 (2014-01-13)
** Update according to reference manual rev. 0.61,
** - rev. 2.4 (2014-02-10)
** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
** - rev. 2.5 (2014-05-06)
** Update according to reference manual rev. 1.0,
** Update of system and startup files.
** Module access macro module_BASES replaced by module_BASE_PTRS.
**
** ###################################################################
*/
/*
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
*
* This file was generated automatically and any changes may be lost.
*/
#ifndef __HW_PIT_REGISTERS_H__
#define __HW_PIT_REGISTERS_H__
#include "MK22F51212.h"
#include "fsl_bitaccess.h"
/*
* MK22F51212 PIT
*
* Periodic Interrupt Timer
*
* Registers defined in this header file:
* - HW_PIT_MCR - PIT Module Control Register
* - HW_PIT_LDVALn - Timer Load Value Register
* - HW_PIT_CVALn - Current Timer Value Register
* - HW_PIT_TCTRLn - Timer Control Register
* - HW_PIT_TFLGn - Timer Flag Register
*
* - hw_pit_t - Struct containing all module registers.
*/
#define HW_PIT_INSTANCE_COUNT (1U) /*!< Number of instances of the PIT module. */
/*******************************************************************************
* HW_PIT_MCR - PIT Module Control Register
******************************************************************************/
/*!
* @brief HW_PIT_MCR - PIT Module Control Register (RW)
*
* Reset value: 0x00000006U
*
* This register enables or disables the PIT timer clocks and controls the
* timers when the PIT enters the Debug mode.
*/
typedef union _hw_pit_mcr
{
uint32_t U;
struct _hw_pit_mcr_bitfields
{
uint32_t FRZ : 1; /*!< [0] Freeze */
uint32_t MDIS : 1; /*!< [1] Module Disable - (PIT section) */
uint32_t RESERVED0 : 30; /*!< [31:2] */
} B;
} hw_pit_mcr_t;
/*!
* @name Constants and macros for entire PIT_MCR register
*/
/*@{*/
#define HW_PIT_MCR_ADDR(x) ((x) + 0x0U)
#define HW_PIT_MCR(x) (*(__IO hw_pit_mcr_t *) HW_PIT_MCR_ADDR(x))
#define HW_PIT_MCR_RD(x) (HW_PIT_MCR(x).U)
#define HW_PIT_MCR_WR(x, v) (HW_PIT_MCR(x).U = (v))
#define HW_PIT_MCR_SET(x, v) (HW_PIT_MCR_WR(x, HW_PIT_MCR_RD(x) | (v)))
#define HW_PIT_MCR_CLR(x, v) (HW_PIT_MCR_WR(x, HW_PIT_MCR_RD(x) & ~(v)))
#define HW_PIT_MCR_TOG(x, v) (HW_PIT_MCR_WR(x, HW_PIT_MCR_RD(x) ^ (v)))
/*@}*/
/*
* Constants & macros for individual PIT_MCR bitfields
*/
/*!
* @name Register PIT_MCR, field FRZ[0] (RW)
*
* Allows the timers to be stopped when the device enters the Debug mode.
*
* Values:
* - 0 - Timers continue to run in Debug mode.
* - 1 - Timers are stopped in Debug mode.
*/
/*@{*/
#define BP_PIT_MCR_FRZ (0U) /*!< Bit position for PIT_MCR_FRZ. */
#define BM_PIT_MCR_FRZ (0x00000001U) /*!< Bit mask for PIT_MCR_FRZ. */
#define BS_PIT_MCR_FRZ (1U) /*!< Bit field size in bits for PIT_MCR_FRZ. */
/*! @brief Read current value of the PIT_MCR_FRZ field. */
#define BR_PIT_MCR_FRZ(x) (BITBAND_ACCESS32(HW_PIT_MCR_ADDR(x), BP_PIT_MCR_FRZ))
/*! @brief Format value for bitfield PIT_MCR_FRZ. */
#define BF_PIT_MCR_FRZ(v) ((uint32_t)((uint32_t)(v) << BP_PIT_MCR_FRZ) & BM_PIT_MCR_FRZ)
/*! @brief Set the FRZ field to a new value. */
#define BW_PIT_MCR_FRZ(x, v) (BITBAND_ACCESS32(HW_PIT_MCR_ADDR(x), BP_PIT_MCR_FRZ) = (v))
/*@}*/
/*!
* @name Register PIT_MCR, field MDIS[1] (RW)
*
* Disables the standard timers. This field must be enabled before any other
* setup is done.
*
* Values:
* - 0 - Clock for standard PIT timers is enabled.
* - 1 - Clock for standard PIT timers is disabled.
*/
/*@{*/
#define BP_PIT_MCR_MDIS (1U) /*!< Bit position for PIT_MCR_MDIS. */
#define BM_PIT_MCR_MDIS (0x00000002U) /*!< Bit mask for PIT_MCR_MDIS. */
#define BS_PIT_MCR_MDIS (1U) /*!< Bit field size in bits for PIT_MCR_MDIS. */
/*! @brief Read current value of the PIT_MCR_MDIS field. */
#define BR_PIT_MCR_MDIS(x) (BITBAND_ACCESS32(HW_PIT_MCR_ADDR(x), BP_PIT_MCR_MDIS))
/*! @brief Format value for bitfield PIT_MCR_MDIS. */
#define BF_PIT_MCR_MDIS(v) ((uint32_t)((uint32_t)(v) << BP_PIT_MCR_MDIS) & BM_PIT_MCR_MDIS)
/*! @brief Set the MDIS field to a new value. */
#define BW_PIT_MCR_MDIS(x, v) (BITBAND_ACCESS32(HW_PIT_MCR_ADDR(x), BP_PIT_MCR_MDIS) = (v))
/*@}*/
/*******************************************************************************
* HW_PIT_LDVALn - Timer Load Value Register
******************************************************************************/
/*!
* @brief HW_PIT_LDVALn - Timer Load Value Register (RW)
*
* Reset value: 0x00000000U
*
* These registers select the timeout period for the timer interrupts.
*/
typedef union _hw_pit_ldvaln
{
uint32_t U;
struct _hw_pit_ldvaln_bitfields
{
uint32_t TSV : 32; /*!< [31:0] Timer Start Value */
} B;
} hw_pit_ldvaln_t;
/*!
* @name Constants and macros for entire PIT_LDVALn register
*/
/*@{*/
#define HW_PIT_LDVALn_COUNT (4U)
#define HW_PIT_LDVALn_ADDR(x, n) ((x) + 0x100U + (0x10U * (n)))
#define HW_PIT_LDVALn(x, n) (*(__IO hw_pit_ldvaln_t *) HW_PIT_LDVALn_ADDR(x, n))
#define HW_PIT_LDVALn_RD(x, n) (HW_PIT_LDVALn(x, n).U)
#define HW_PIT_LDVALn_WR(x, n, v) (HW_PIT_LDVALn(x, n).U = (v))
#define HW_PIT_LDVALn_SET(x, n, v) (HW_PIT_LDVALn_WR(x, n, HW_PIT_LDVALn_RD(x, n) | (v)))
#define HW_PIT_LDVALn_CLR(x, n, v) (HW_PIT_LDVALn_WR(x, n, HW_PIT_LDVALn_RD(x, n) & ~(v)))
#define HW_PIT_LDVALn_TOG(x, n, v) (HW_PIT_LDVALn_WR(x, n, HW_PIT_LDVALn_RD(x, n) ^ (v)))
/*@}*/
/*
* Constants & macros for individual PIT_LDVALn bitfields
*/
/*!
* @name Register PIT_LDVALn, field TSV[31:0] (RW)
*
* Sets the timer start value. The timer will count down until it reaches 0,
* then it will generate an interrupt and load this register value again. Writing a
* new value to this register will not restart the timer; instead the value will
* be loaded after the timer expires. To abort the current cycle and start a
* timer period with the new value, the timer must be disabled and enabled again.
*/
/*@{*/
#define BP_PIT_LDVALn_TSV (0U) /*!< Bit position for PIT_LDVALn_TSV. */
#define BM_PIT_LDVALn_TSV (0xFFFFFFFFU) /*!< Bit mask for PIT_LDVALn_TSV. */
#define BS_PIT_LDVALn_TSV (32U) /*!< Bit field size in bits for PIT_LDVALn_TSV. */
/*! @brief Read current value of the PIT_LDVALn_TSV field. */
#define BR_PIT_LDVALn_TSV(x, n) (HW_PIT_LDVALn(x, n).U)
/*! @brief Format value for bitfield PIT_LDVALn_TSV. */
#define BF_PIT_LDVALn_TSV(v) ((uint32_t)((uint32_t)(v) << BP_PIT_LDVALn_TSV) & BM_PIT_LDVALn_TSV)
/*! @brief Set the TSV field to a new value. */
#define BW_PIT_LDVALn_TSV(x, n, v) (HW_PIT_LDVALn_WR(x, n, v))
/*@}*/
/*******************************************************************************
* HW_PIT_CVALn - Current Timer Value Register
******************************************************************************/
/*!
* @brief HW_PIT_CVALn - Current Timer Value Register (RO)
*
* Reset value: 0x00000000U
*
* These registers indicate the current timer position.
*/
typedef union _hw_pit_cvaln
{
uint32_t U;
struct _hw_pit_cvaln_bitfields
{
uint32_t TVL : 32; /*!< [31:0] Current Timer Value */
} B;
} hw_pit_cvaln_t;
/*!
* @name Constants and macros for entire PIT_CVALn register
*/
/*@{*/
#define HW_PIT_CVALn_COUNT (4U)
#define HW_PIT_CVALn_ADDR(x, n) ((x) + 0x104U + (0x10U * (n)))
#define HW_PIT_CVALn(x, n) (*(__I hw_pit_cvaln_t *) HW_PIT_CVALn_ADDR(x, n))
#define HW_PIT_CVALn_RD(x, n) (HW_PIT_CVALn(x, n).U)
/*@}*/
/*
* Constants & macros for individual PIT_CVALn bitfields
*/
/*!
* @name Register PIT_CVALn, field TVL[31:0] (RO)
*
* Represents the current timer value, if the timer is enabled. If the timer is
* disabled, do not use this field as its value is unreliable. The timer uses a
* downcounter. The timer values are frozen in Debug mode if MCR[FRZ] is set.
*/
/*@{*/
#define BP_PIT_CVALn_TVL (0U) /*!< Bit position for PIT_CVALn_TVL. */
#define BM_PIT_CVALn_TVL (0xFFFFFFFFU) /*!< Bit mask for PIT_CVALn_TVL. */
#define BS_PIT_CVALn_TVL (32U) /*!< Bit field size in bits for PIT_CVALn_TVL. */
/*! @brief Read current value of the PIT_CVALn_TVL field. */
#define BR_PIT_CVALn_TVL(x, n) (HW_PIT_CVALn(x, n).U)
/*@}*/
/*******************************************************************************
* HW_PIT_TCTRLn - Timer Control Register
******************************************************************************/
/*!
* @brief HW_PIT_TCTRLn - Timer Control Register (RW)
*
* Reset value: 0x00000000U
*
* These registers contain the control bits for each timer.
*/
typedef union _hw_pit_tctrln
{
uint32_t U;
struct _hw_pit_tctrln_bitfields
{
uint32_t TEN : 1; /*!< [0] Timer Enable */
uint32_t TIE : 1; /*!< [1] Timer Interrupt Enable */
uint32_t CHN : 1; /*!< [2] Chain Mode */
uint32_t RESERVED0 : 29; /*!< [31:3] */
} B;
} hw_pit_tctrln_t;
/*!
* @name Constants and macros for entire PIT_TCTRLn register
*/
/*@{*/
#define HW_PIT_TCTRLn_COUNT (4U)
#define HW_PIT_TCTRLn_ADDR(x, n) ((x) + 0x108U + (0x10U * (n)))
#define HW_PIT_TCTRLn(x, n) (*(__IO hw_pit_tctrln_t *) HW_PIT_TCTRLn_ADDR(x, n))
#define HW_PIT_TCTRLn_RD(x, n) (HW_PIT_TCTRLn(x, n).U)
#define HW_PIT_TCTRLn_WR(x, n, v) (HW_PIT_TCTRLn(x, n).U = (v))
#define HW_PIT_TCTRLn_SET(x, n, v) (HW_PIT_TCTRLn_WR(x, n, HW_PIT_TCTRLn_RD(x, n) | (v)))
#define HW_PIT_TCTRLn_CLR(x, n, v) (HW_PIT_TCTRLn_WR(x, n, HW_PIT_TCTRLn_RD(x, n) & ~(v)))
#define HW_PIT_TCTRLn_TOG(x, n, v) (HW_PIT_TCTRLn_WR(x, n, HW_PIT_TCTRLn_RD(x, n) ^ (v)))
/*@}*/
/*
* Constants & macros for individual PIT_TCTRLn bitfields
*/
/*!
* @name Register PIT_TCTRLn, field TEN[0] (RW)
*
* Enables or disables the timer.
*
* Values:
* - 0 - Timer n is disabled.
* - 1 - Timer n is enabled.
*/
/*@{*/
#define BP_PIT_TCTRLn_TEN (0U) /*!< Bit position for PIT_TCTRLn_TEN. */
#define BM_PIT_TCTRLn_TEN (0x00000001U) /*!< Bit mask for PIT_TCTRLn_TEN. */
#define BS_PIT_TCTRLn_TEN (1U) /*!< Bit field size in bits for PIT_TCTRLn_TEN. */
/*! @brief Read current value of the PIT_TCTRLn_TEN field. */
#define BR_PIT_TCTRLn_TEN(x, n) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(x, n), BP_PIT_TCTRLn_TEN))
/*! @brief Format value for bitfield PIT_TCTRLn_TEN. */
#define BF_PIT_TCTRLn_TEN(v) ((uint32_t)((uint32_t)(v) << BP_PIT_TCTRLn_TEN) & BM_PIT_TCTRLn_TEN)
/*! @brief Set the TEN field to a new value. */
#define BW_PIT_TCTRLn_TEN(x, n, v) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(x, n), BP_PIT_TCTRLn_TEN) = (v))
/*@}*/
/*!
* @name Register PIT_TCTRLn, field TIE[1] (RW)
*
* When an interrupt is pending, or, TFLGn[TIF] is set, enabling the interrupt
* will immediately cause an interrupt event. To avoid this, the associated
* TFLGn[TIF] must be cleared first.
*
* Values:
* - 0 - Interrupt requests from Timer n are disabled.
* - 1 - Interrupt will be requested whenever TIF is set.
*/
/*@{*/
#define BP_PIT_TCTRLn_TIE (1U) /*!< Bit position for PIT_TCTRLn_TIE. */
#define BM_PIT_TCTRLn_TIE (0x00000002U) /*!< Bit mask for PIT_TCTRLn_TIE. */
#define BS_PIT_TCTRLn_TIE (1U) /*!< Bit field size in bits for PIT_TCTRLn_TIE. */
/*! @brief Read current value of the PIT_TCTRLn_TIE field. */
#define BR_PIT_TCTRLn_TIE(x, n) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(x, n), BP_PIT_TCTRLn_TIE))
/*! @brief Format value for bitfield PIT_TCTRLn_TIE. */
#define BF_PIT_TCTRLn_TIE(v) ((uint32_t)((uint32_t)(v) << BP_PIT_TCTRLn_TIE) & BM_PIT_TCTRLn_TIE)
/*! @brief Set the TIE field to a new value. */
#define BW_PIT_TCTRLn_TIE(x, n, v) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(x, n), BP_PIT_TCTRLn_TIE) = (v))
/*@}*/
/*!
* @name Register PIT_TCTRLn, field CHN[2] (RW)
*
* When activated, Timer n-1 needs to expire before timer n can decrement by 1.
* Timer 0 cannot be chained.
*
* Values:
* - 0 - Timer is not chained.
* - 1 - Timer is chained to previous timer. For example, for Channel 2, if this
* field is set, Timer 2 is chained to Timer 1.
*/
/*@{*/
#define BP_PIT_TCTRLn_CHN (2U) /*!< Bit position for PIT_TCTRLn_CHN. */
#define BM_PIT_TCTRLn_CHN (0x00000004U) /*!< Bit mask for PIT_TCTRLn_CHN. */
#define BS_PIT_TCTRLn_CHN (1U) /*!< Bit field size in bits for PIT_TCTRLn_CHN. */
/*! @brief Read current value of the PIT_TCTRLn_CHN field. */
#define BR_PIT_TCTRLn_CHN(x, n) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(x, n), BP_PIT_TCTRLn_CHN))
/*! @brief Format value for bitfield PIT_TCTRLn_CHN. */
#define BF_PIT_TCTRLn_CHN(v) ((uint32_t)((uint32_t)(v) << BP_PIT_TCTRLn_CHN) & BM_PIT_TCTRLn_CHN)
/*! @brief Set the CHN field to a new value. */
#define BW_PIT_TCTRLn_CHN(x, n, v) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(x, n), BP_PIT_TCTRLn_CHN) = (v))
/*@}*/
/*******************************************************************************
* HW_PIT_TFLGn - Timer Flag Register
******************************************************************************/
/*!
* @brief HW_PIT_TFLGn - Timer Flag Register (RW)
*
* Reset value: 0x00000000U
*
* These registers hold the PIT interrupt flags.
*/
typedef union _hw_pit_tflgn
{
uint32_t U;
struct _hw_pit_tflgn_bitfields
{
uint32_t TIF : 1; /*!< [0] Timer Interrupt Flag */
uint32_t RESERVED0 : 31; /*!< [31:1] */
} B;
} hw_pit_tflgn_t;
/*!
* @name Constants and macros for entire PIT_TFLGn register
*/
/*@{*/
#define HW_PIT_TFLGn_COUNT (4U)
#define HW_PIT_TFLGn_ADDR(x, n) ((x) + 0x10CU + (0x10U * (n)))
#define HW_PIT_TFLGn(x, n) (*(__IO hw_pit_tflgn_t *) HW_PIT_TFLGn_ADDR(x, n))
#define HW_PIT_TFLGn_RD(x, n) (HW_PIT_TFLGn(x, n).U)
#define HW_PIT_TFLGn_WR(x, n, v) (HW_PIT_TFLGn(x, n).U = (v))
#define HW_PIT_TFLGn_SET(x, n, v) (HW_PIT_TFLGn_WR(x, n, HW_PIT_TFLGn_RD(x, n) | (v)))
#define HW_PIT_TFLGn_CLR(x, n, v) (HW_PIT_TFLGn_WR(x, n, HW_PIT_TFLGn_RD(x, n) & ~(v)))
#define HW_PIT_TFLGn_TOG(x, n, v) (HW_PIT_TFLGn_WR(x, n, HW_PIT_TFLGn_RD(x, n) ^ (v)))
/*@}*/
/*
* Constants & macros for individual PIT_TFLGn bitfields
*/
/*!
* @name Register PIT_TFLGn, field TIF[0] (W1C)
*
* Sets to 1 at the end of the timer period. Writing 1 to this flag clears it.
* Writing 0 has no effect. If enabled, or, when TCTRLn[TIE] = 1, TIF causes an
* interrupt request.
*
* Values:
* - 0 - Timeout has not yet occurred.
* - 1 - Timeout has occurred.
*/
/*@{*/
#define BP_PIT_TFLGn_TIF (0U) /*!< Bit position for PIT_TFLGn_TIF. */
#define BM_PIT_TFLGn_TIF (0x00000001U) /*!< Bit mask for PIT_TFLGn_TIF. */
#define BS_PIT_TFLGn_TIF (1U) /*!< Bit field size in bits for PIT_TFLGn_TIF. */
/*! @brief Read current value of the PIT_TFLGn_TIF field. */
#define BR_PIT_TFLGn_TIF(x, n) (BITBAND_ACCESS32(HW_PIT_TFLGn_ADDR(x, n), BP_PIT_TFLGn_TIF))
/*! @brief Format value for bitfield PIT_TFLGn_TIF. */
#define BF_PIT_TFLGn_TIF(v) ((uint32_t)((uint32_t)(v) << BP_PIT_TFLGn_TIF) & BM_PIT_TFLGn_TIF)
/*! @brief Set the TIF field to a new value. */
#define BW_PIT_TFLGn_TIF(x, n, v) (BITBAND_ACCESS32(HW_PIT_TFLGn_ADDR(x, n), BP_PIT_TFLGn_TIF) = (v))
/*@}*/
/*******************************************************************************
* hw_pit_t - module struct
******************************************************************************/
/*!
* @brief All PIT module registers.
*/
#pragma pack(1)
typedef struct _hw_pit
{
__IO hw_pit_mcr_t MCR; /*!< [0x0] PIT Module Control Register */
uint8_t _reserved0[252];
struct {
__IO hw_pit_ldvaln_t LDVALn; /*!< [0x100] Timer Load Value Register */
__I hw_pit_cvaln_t CVALn; /*!< [0x104] Current Timer Value Register */
__IO hw_pit_tctrln_t TCTRLn; /*!< [0x108] Timer Control Register */
__IO hw_pit_tflgn_t TFLGn; /*!< [0x10C] Timer Flag Register */
} CHANNEL[4];
} hw_pit_t;
#pragma pack()
/*! @brief Macro to access all PIT registers. */
/*! @param x PIT module instance base address. */
/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
* use the '&' operator, like <code>&HW_PIT(PIT_BASE)</code>. */
#define HW_PIT(x) (*(hw_pit_t *)(x))
#endif /* __HW_PIT_REGISTERS_H__ */
/* EOF */

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libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_pmc.h Normal file
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@ -0,0 +1,572 @@
/*
** ###################################################################
** Compilers: Keil ARM C/C++ Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
** Version: rev. 2.5, 2014-05-06
** Build: b140604
**
** Abstract:
** Extension to the CMSIS register access layer header.
**
** Copyright (c) 2014 Freescale Semiconductor, Inc.
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** Revisions:
** - rev. 1.0 (2013-07-23)
** Initial version.
** - rev. 1.1 (2013-09-17)
** RM rev. 0.4 update.
** - rev. 2.0 (2013-10-29)
** Register accessor macros added to the memory map.
** Symbols for Processor Expert memory map compatibility added to the memory map.
** Startup file for gcc has been updated according to CMSIS 3.2.
** System initialization updated.
** - rev. 2.1 (2013-10-30)
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
** - rev. 2.2 (2013-12-20)
** Update according to reference manual rev. 0.6,
** - rev. 2.3 (2014-01-13)
** Update according to reference manual rev. 0.61,
** - rev. 2.4 (2014-02-10)
** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
** - rev. 2.5 (2014-05-06)
** Update according to reference manual rev. 1.0,
** Update of system and startup files.
** Module access macro module_BASES replaced by module_BASE_PTRS.
**
** ###################################################################
*/
/*
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
*
* This file was generated automatically and any changes may be lost.
*/
#ifndef __HW_PMC_REGISTERS_H__
#define __HW_PMC_REGISTERS_H__
#include "MK22F51212.h"
#include "fsl_bitaccess.h"
/*
* MK22F51212 PMC
*
* Power Management Controller
*
* Registers defined in this header file:
* - HW_PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register
* - HW_PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register
* - HW_PMC_REGSC - Regulator Status And Control register
*
* - hw_pmc_t - Struct containing all module registers.
*/
#define HW_PMC_INSTANCE_COUNT (1U) /*!< Number of instances of the PMC module. */
/*******************************************************************************
* HW_PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register
******************************************************************************/
/*!
* @brief HW_PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register (RW)
*
* Reset value: 0x10U
*
* This register contains status and control bits to support the low voltage
* detect function. This register should be written during the reset initialization
* program to set the desired controls even if the desired settings are the same
* as the reset settings. While the device is in the very low power or low
* leakage modes, the LVD system is disabled regardless of LVDSC1 settings. To protect
* systems that must have LVD always on, configure the Power Mode Protection
* (PMPROT) register of the SMC module (SMC_PMPROT) to disallow any very low power or
* low leakage modes from being enabled. See the device's data sheet for the
* exact LVD trip voltages. The LVDV bits are reset solely on a POR Only event. The
* register's other bits are reset on Chip Reset Not VLLS. For more information
* about these reset types, refer to the Reset section details.
*/
typedef union _hw_pmc_lvdsc1
{
uint8_t U;
struct _hw_pmc_lvdsc1_bitfields
{
uint8_t LVDV : 2; /*!< [1:0] Low-Voltage Detect Voltage Select */
uint8_t RESERVED0 : 2; /*!< [3:2] */
uint8_t LVDRE : 1; /*!< [4] Low-Voltage Detect Reset Enable */
uint8_t LVDIE : 1; /*!< [5] Low-Voltage Detect Interrupt Enable */
uint8_t LVDACK : 1; /*!< [6] Low-Voltage Detect Acknowledge */
uint8_t LVDF : 1; /*!< [7] Low-Voltage Detect Flag */
} B;
} hw_pmc_lvdsc1_t;
/*!
* @name Constants and macros for entire PMC_LVDSC1 register
*/
/*@{*/
#define HW_PMC_LVDSC1_ADDR(x) ((x) + 0x0U)
#define HW_PMC_LVDSC1(x) (*(__IO hw_pmc_lvdsc1_t *) HW_PMC_LVDSC1_ADDR(x))
#define HW_PMC_LVDSC1_RD(x) (HW_PMC_LVDSC1(x).U)
#define HW_PMC_LVDSC1_WR(x, v) (HW_PMC_LVDSC1(x).U = (v))
#define HW_PMC_LVDSC1_SET(x, v) (HW_PMC_LVDSC1_WR(x, HW_PMC_LVDSC1_RD(x) | (v)))
#define HW_PMC_LVDSC1_CLR(x, v) (HW_PMC_LVDSC1_WR(x, HW_PMC_LVDSC1_RD(x) & ~(v)))
#define HW_PMC_LVDSC1_TOG(x, v) (HW_PMC_LVDSC1_WR(x, HW_PMC_LVDSC1_RD(x) ^ (v)))
/*@}*/
/*
* Constants & macros for individual PMC_LVDSC1 bitfields
*/
/*!
* @name Register PMC_LVDSC1, field LVDV[1:0] (RW)
*
* Selects the LVD trip point voltage (V LVD ).
*
* Values:
* - 00 - Low trip point selected (V LVD = V LVDL )
* - 01 - High trip point selected (V LVD = V LVDH )
* - 10 - Reserved
* - 11 - Reserved
*/
/*@{*/
#define BP_PMC_LVDSC1_LVDV (0U) /*!< Bit position for PMC_LVDSC1_LVDV. */
#define BM_PMC_LVDSC1_LVDV (0x03U) /*!< Bit mask for PMC_LVDSC1_LVDV. */
#define BS_PMC_LVDSC1_LVDV (2U) /*!< Bit field size in bits for PMC_LVDSC1_LVDV. */
/*! @brief Read current value of the PMC_LVDSC1_LVDV field. */
#define BR_PMC_LVDSC1_LVDV(x) (HW_PMC_LVDSC1(x).B.LVDV)
/*! @brief Format value for bitfield PMC_LVDSC1_LVDV. */
#define BF_PMC_LVDSC1_LVDV(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC1_LVDV) & BM_PMC_LVDSC1_LVDV)
/*! @brief Set the LVDV field to a new value. */
#define BW_PMC_LVDSC1_LVDV(x, v) (HW_PMC_LVDSC1_WR(x, (HW_PMC_LVDSC1_RD(x) & ~BM_PMC_LVDSC1_LVDV) | BF_PMC_LVDSC1_LVDV(v)))
/*@}*/
/*!
* @name Register PMC_LVDSC1, field LVDRE[4] (RW)
*
* This write-once bit enables LVDF events to generate a hardware reset.
* Additional writes are ignored.
*
* Values:
* - 0 - LVDF does not generate hardware resets
* - 1 - Force an MCU reset when LVDF = 1
*/
/*@{*/
#define BP_PMC_LVDSC1_LVDRE (4U) /*!< Bit position for PMC_LVDSC1_LVDRE. */
#define BM_PMC_LVDSC1_LVDRE (0x10U) /*!< Bit mask for PMC_LVDSC1_LVDRE. */
#define BS_PMC_LVDSC1_LVDRE (1U) /*!< Bit field size in bits for PMC_LVDSC1_LVDRE. */
/*! @brief Read current value of the PMC_LVDSC1_LVDRE field. */
#define BR_PMC_LVDSC1_LVDRE(x) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDRE))
/*! @brief Format value for bitfield PMC_LVDSC1_LVDRE. */
#define BF_PMC_LVDSC1_LVDRE(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC1_LVDRE) & BM_PMC_LVDSC1_LVDRE)
/*! @brief Set the LVDRE field to a new value. */
#define BW_PMC_LVDSC1_LVDRE(x, v) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDRE) = (v))
/*@}*/
/*!
* @name Register PMC_LVDSC1, field LVDIE[5] (RW)
*
* Enables hardware interrupt requests for LVDF.
*
* Values:
* - 0 - Hardware interrupt disabled (use polling)
* - 1 - Request a hardware interrupt when LVDF = 1
*/
/*@{*/
#define BP_PMC_LVDSC1_LVDIE (5U) /*!< Bit position for PMC_LVDSC1_LVDIE. */
#define BM_PMC_LVDSC1_LVDIE (0x20U) /*!< Bit mask for PMC_LVDSC1_LVDIE. */
#define BS_PMC_LVDSC1_LVDIE (1U) /*!< Bit field size in bits for PMC_LVDSC1_LVDIE. */
/*! @brief Read current value of the PMC_LVDSC1_LVDIE field. */
#define BR_PMC_LVDSC1_LVDIE(x) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDIE))
/*! @brief Format value for bitfield PMC_LVDSC1_LVDIE. */
#define BF_PMC_LVDSC1_LVDIE(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC1_LVDIE) & BM_PMC_LVDSC1_LVDIE)
/*! @brief Set the LVDIE field to a new value. */
#define BW_PMC_LVDSC1_LVDIE(x, v) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDIE) = (v))
/*@}*/
/*!
* @name Register PMC_LVDSC1, field LVDACK[6] (WORZ)
*
* This write-only field is used to acknowledge low voltage detection errors.
* Write 1 to clear LVDF. Reads always return 0.
*/
/*@{*/
#define BP_PMC_LVDSC1_LVDACK (6U) /*!< Bit position for PMC_LVDSC1_LVDACK. */
#define BM_PMC_LVDSC1_LVDACK (0x40U) /*!< Bit mask for PMC_LVDSC1_LVDACK. */
#define BS_PMC_LVDSC1_LVDACK (1U) /*!< Bit field size in bits for PMC_LVDSC1_LVDACK. */
/*! @brief Format value for bitfield PMC_LVDSC1_LVDACK. */
#define BF_PMC_LVDSC1_LVDACK(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC1_LVDACK) & BM_PMC_LVDSC1_LVDACK)
/*! @brief Set the LVDACK field to a new value. */
#define BW_PMC_LVDSC1_LVDACK(x, v) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDACK) = (v))
/*@}*/
/*!
* @name Register PMC_LVDSC1, field LVDF[7] (RO)
*
* This read-only status field indicates a low-voltage detect event.
*
* Values:
* - 0 - Low-voltage event not detected
* - 1 - Low-voltage event detected
*/
/*@{*/
#define BP_PMC_LVDSC1_LVDF (7U) /*!< Bit position for PMC_LVDSC1_LVDF. */
#define BM_PMC_LVDSC1_LVDF (0x80U) /*!< Bit mask for PMC_LVDSC1_LVDF. */
#define BS_PMC_LVDSC1_LVDF (1U) /*!< Bit field size in bits for PMC_LVDSC1_LVDF. */
/*! @brief Read current value of the PMC_LVDSC1_LVDF field. */
#define BR_PMC_LVDSC1_LVDF(x) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDF))
/*@}*/
/*******************************************************************************
* HW_PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register
******************************************************************************/
/*!
* @brief HW_PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register (RW)
*
* Reset value: 0x00U
*
* This register contains status and control bits to support the low voltage
* warning function. While the device is in the very low power or low leakage modes,
* the LVD system is disabled regardless of LVDSC2 settings. See the device's
* data sheet for the exact LVD trip voltages. The LVW trip voltages depend on LVWV
* and LVDV. LVWV is reset solely on a POR Only event. The other fields of the
* register are reset on Chip Reset Not VLLS. For more information about these
* reset types, refer to the Reset section details.
*/
typedef union _hw_pmc_lvdsc2
{
uint8_t U;
struct _hw_pmc_lvdsc2_bitfields
{
uint8_t LVWV : 2; /*!< [1:0] Low-Voltage Warning Voltage Select */
uint8_t RESERVED0 : 3; /*!< [4:2] */
uint8_t LVWIE : 1; /*!< [5] Low-Voltage Warning Interrupt Enable */
uint8_t LVWACK : 1; /*!< [6] Low-Voltage Warning Acknowledge */
uint8_t LVWF : 1; /*!< [7] Low-Voltage Warning Flag */
} B;
} hw_pmc_lvdsc2_t;
/*!
* @name Constants and macros for entire PMC_LVDSC2 register
*/
/*@{*/
#define HW_PMC_LVDSC2_ADDR(x) ((x) + 0x1U)
#define HW_PMC_LVDSC2(x) (*(__IO hw_pmc_lvdsc2_t *) HW_PMC_LVDSC2_ADDR(x))
#define HW_PMC_LVDSC2_RD(x) (HW_PMC_LVDSC2(x).U)
#define HW_PMC_LVDSC2_WR(x, v) (HW_PMC_LVDSC2(x).U = (v))
#define HW_PMC_LVDSC2_SET(x, v) (HW_PMC_LVDSC2_WR(x, HW_PMC_LVDSC2_RD(x) | (v)))
#define HW_PMC_LVDSC2_CLR(x, v) (HW_PMC_LVDSC2_WR(x, HW_PMC_LVDSC2_RD(x) & ~(v)))
#define HW_PMC_LVDSC2_TOG(x, v) (HW_PMC_LVDSC2_WR(x, HW_PMC_LVDSC2_RD(x) ^ (v)))
/*@}*/
/*
* Constants & macros for individual PMC_LVDSC2 bitfields
*/
/*!
* @name Register PMC_LVDSC2, field LVWV[1:0] (RW)
*
* Selects the LVW trip point voltage (VLVW). The actual voltage for the warning
* depends on LVDSC1[LVDV].
*
* Values:
* - 00 - Low trip point selected (VLVW = VLVW1)
* - 01 - Mid 1 trip point selected (VLVW = VLVW2)
* - 10 - Mid 2 trip point selected (VLVW = VLVW3)
* - 11 - High trip point selected (VLVW = VLVW4)
*/
/*@{*/
#define BP_PMC_LVDSC2_LVWV (0U) /*!< Bit position for PMC_LVDSC2_LVWV. */
#define BM_PMC_LVDSC2_LVWV (0x03U) /*!< Bit mask for PMC_LVDSC2_LVWV. */
#define BS_PMC_LVDSC2_LVWV (2U) /*!< Bit field size in bits for PMC_LVDSC2_LVWV. */
/*! @brief Read current value of the PMC_LVDSC2_LVWV field. */
#define BR_PMC_LVDSC2_LVWV(x) (HW_PMC_LVDSC2(x).B.LVWV)
/*! @brief Format value for bitfield PMC_LVDSC2_LVWV. */
#define BF_PMC_LVDSC2_LVWV(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC2_LVWV) & BM_PMC_LVDSC2_LVWV)
/*! @brief Set the LVWV field to a new value. */
#define BW_PMC_LVDSC2_LVWV(x, v) (HW_PMC_LVDSC2_WR(x, (HW_PMC_LVDSC2_RD(x) & ~BM_PMC_LVDSC2_LVWV) | BF_PMC_LVDSC2_LVWV(v)))
/*@}*/
/*!
* @name Register PMC_LVDSC2, field LVWIE[5] (RW)
*
* Enables hardware interrupt requests for LVWF.
*
* Values:
* - 0 - Hardware interrupt disabled (use polling)
* - 1 - Request a hardware interrupt when LVWF = 1
*/
/*@{*/
#define BP_PMC_LVDSC2_LVWIE (5U) /*!< Bit position for PMC_LVDSC2_LVWIE. */
#define BM_PMC_LVDSC2_LVWIE (0x20U) /*!< Bit mask for PMC_LVDSC2_LVWIE. */
#define BS_PMC_LVDSC2_LVWIE (1U) /*!< Bit field size in bits for PMC_LVDSC2_LVWIE. */
/*! @brief Read current value of the PMC_LVDSC2_LVWIE field. */
#define BR_PMC_LVDSC2_LVWIE(x) (BITBAND_ACCESS8(HW_PMC_LVDSC2_ADDR(x), BP_PMC_LVDSC2_LVWIE))
/*! @brief Format value for bitfield PMC_LVDSC2_LVWIE. */
#define BF_PMC_LVDSC2_LVWIE(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC2_LVWIE) & BM_PMC_LVDSC2_LVWIE)
/*! @brief Set the LVWIE field to a new value. */
#define BW_PMC_LVDSC2_LVWIE(x, v) (BITBAND_ACCESS8(HW_PMC_LVDSC2_ADDR(x), BP_PMC_LVDSC2_LVWIE) = (v))
/*@}*/
/*!
* @name Register PMC_LVDSC2, field LVWACK[6] (WORZ)
*
* This write-only field is used to acknowledge low voltage warning errors.
* Write 1 to clear LVWF. Reads always return 0.
*/
/*@{*/
#define BP_PMC_LVDSC2_LVWACK (6U) /*!< Bit position for PMC_LVDSC2_LVWACK. */
#define BM_PMC_LVDSC2_LVWACK (0x40U) /*!< Bit mask for PMC_LVDSC2_LVWACK. */
#define BS_PMC_LVDSC2_LVWACK (1U) /*!< Bit field size in bits for PMC_LVDSC2_LVWACK. */
/*! @brief Format value for bitfield PMC_LVDSC2_LVWACK. */
#define BF_PMC_LVDSC2_LVWACK(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC2_LVWACK) & BM_PMC_LVDSC2_LVWACK)
/*! @brief Set the LVWACK field to a new value. */
#define BW_PMC_LVDSC2_LVWACK(x, v) (BITBAND_ACCESS8(HW_PMC_LVDSC2_ADDR(x), BP_PMC_LVDSC2_LVWACK) = (v))
/*@}*/
/*!
* @name Register PMC_LVDSC2, field LVWF[7] (RO)
*
* This read-only status field indicates a low-voltage warning event. LVWF is
* set when VSupply transitions below the trip point, or after reset and VSupply is
* already below VLVW. LVWF may be 1 after power-on reset, therefore, to use LVW
* interrupt function, before enabling LVWIE, LVWF must be cleared by writing
* LVWACK first.
*
* Values:
* - 0 - Low-voltage warning event not detected
* - 1 - Low-voltage warning event detected
*/
/*@{*/
#define BP_PMC_LVDSC2_LVWF (7U) /*!< Bit position for PMC_LVDSC2_LVWF. */
#define BM_PMC_LVDSC2_LVWF (0x80U) /*!< Bit mask for PMC_LVDSC2_LVWF. */
#define BS_PMC_LVDSC2_LVWF (1U) /*!< Bit field size in bits for PMC_LVDSC2_LVWF. */
/*! @brief Read current value of the PMC_LVDSC2_LVWF field. */
#define BR_PMC_LVDSC2_LVWF(x) (BITBAND_ACCESS8(HW_PMC_LVDSC2_ADDR(x), BP_PMC_LVDSC2_LVWF))
/*@}*/
/*******************************************************************************
* HW_PMC_REGSC - Regulator Status And Control register
******************************************************************************/
/*!
* @brief HW_PMC_REGSC - Regulator Status And Control register (RW)
*
* Reset value: 0x04U
*
* The PMC contains an internal voltage regulator. The voltage regulator design
* uses a bandgap reference that is also available through a buffer as input to
* certain internal peripherals, such as the CMP and ADC. The internal regulator
* provides a status bit (REGONS) indicating the regulator is in run regulation.
* This register is reset on Chip Reset Not VLLS and by reset types that trigger
* Chip Reset not VLLS. See the Reset section details for more information.
*/
typedef union _hw_pmc_regsc
{
uint8_t U;
struct _hw_pmc_regsc_bitfields
{
uint8_t BGBE : 1; /*!< [0] Bandgap Buffer Enable */
uint8_t RESERVED0 : 1; /*!< [1] */
uint8_t REGONS : 1; /*!< [2] Regulator In Run Regulation Status */
uint8_t ACKISO : 1; /*!< [3] Acknowledge Isolation */
uint8_t BGEN : 1; /*!< [4] Bandgap Enable In VLPx Operation */
uint8_t RESERVED1 : 3; /*!< [7:5] */
} B;
} hw_pmc_regsc_t;
/*!
* @name Constants and macros for entire PMC_REGSC register
*/
/*@{*/
#define HW_PMC_REGSC_ADDR(x) ((x) + 0x2U)
#define HW_PMC_REGSC(x) (*(__IO hw_pmc_regsc_t *) HW_PMC_REGSC_ADDR(x))
#define HW_PMC_REGSC_RD(x) (HW_PMC_REGSC(x).U)
#define HW_PMC_REGSC_WR(x, v) (HW_PMC_REGSC(x).U = (v))
#define HW_PMC_REGSC_SET(x, v) (HW_PMC_REGSC_WR(x, HW_PMC_REGSC_RD(x) | (v)))
#define HW_PMC_REGSC_CLR(x, v) (HW_PMC_REGSC_WR(x, HW_PMC_REGSC_RD(x) & ~(v)))
#define HW_PMC_REGSC_TOG(x, v) (HW_PMC_REGSC_WR(x, HW_PMC_REGSC_RD(x) ^ (v)))
/*@}*/
/*
* Constants & macros for individual PMC_REGSC bitfields
*/
/*!
* @name Register PMC_REGSC, field BGBE[0] (RW)
*
* Enables the bandgap buffer.
*
* Values:
* - 0 - Bandgap buffer not enabled
* - 1 - Bandgap buffer enabled
*/
/*@{*/
#define BP_PMC_REGSC_BGBE (0U) /*!< Bit position for PMC_REGSC_BGBE. */
#define BM_PMC_REGSC_BGBE (0x01U) /*!< Bit mask for PMC_REGSC_BGBE. */
#define BS_PMC_REGSC_BGBE (1U) /*!< Bit field size in bits for PMC_REGSC_BGBE. */
/*! @brief Read current value of the PMC_REGSC_BGBE field. */
#define BR_PMC_REGSC_BGBE(x) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_BGBE))
/*! @brief Format value for bitfield PMC_REGSC_BGBE. */
#define BF_PMC_REGSC_BGBE(v) ((uint8_t)((uint8_t)(v) << BP_PMC_REGSC_BGBE) & BM_PMC_REGSC_BGBE)
/*! @brief Set the BGBE field to a new value. */
#define BW_PMC_REGSC_BGBE(x, v) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_BGBE) = (v))
/*@}*/
/*!
* @name Register PMC_REGSC, field REGONS[2] (RO)
*
* This read-only field provides the current status of the internal voltage
* regulator.
*
* Values:
* - 0 - Regulator is in stop regulation or in transition to/from it
* - 1 - Regulator is in run regulation
*/
/*@{*/
#define BP_PMC_REGSC_REGONS (2U) /*!< Bit position for PMC_REGSC_REGONS. */
#define BM_PMC_REGSC_REGONS (0x04U) /*!< Bit mask for PMC_REGSC_REGONS. */
#define BS_PMC_REGSC_REGONS (1U) /*!< Bit field size in bits for PMC_REGSC_REGONS. */
/*! @brief Read current value of the PMC_REGSC_REGONS field. */
#define BR_PMC_REGSC_REGONS(x) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_REGONS))
/*@}*/
/*!
* @name Register PMC_REGSC, field ACKISO[3] (W1C)
*
* Reading this field indicates whether certain peripherals and the I/O pads are
* in a latched state as a result of having been in a VLLS mode. Writing 1 to
* this field when it is set releases the I/O pads and certain peripherals to their
* normal run mode state. After recovering from a VLLS mode, user should restore
* chip configuration before clearing ACKISO. In particular, pin configuration
* for enabled LLWU wakeup pins should be restored to avoid any LLWU flag from
* being falsely set when ACKISO is cleared.
*
* Values:
* - 0 - Peripherals and I/O pads are in normal run state.
* - 1 - Certain peripherals and I/O pads are in an isolated and latched state.
*/
/*@{*/
#define BP_PMC_REGSC_ACKISO (3U) /*!< Bit position for PMC_REGSC_ACKISO. */
#define BM_PMC_REGSC_ACKISO (0x08U) /*!< Bit mask for PMC_REGSC_ACKISO. */
#define BS_PMC_REGSC_ACKISO (1U) /*!< Bit field size in bits for PMC_REGSC_ACKISO. */
/*! @brief Read current value of the PMC_REGSC_ACKISO field. */
#define BR_PMC_REGSC_ACKISO(x) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_ACKISO))
/*! @brief Format value for bitfield PMC_REGSC_ACKISO. */
#define BF_PMC_REGSC_ACKISO(v) ((uint8_t)((uint8_t)(v) << BP_PMC_REGSC_ACKISO) & BM_PMC_REGSC_ACKISO)
/*! @brief Set the ACKISO field to a new value. */
#define BW_PMC_REGSC_ACKISO(x, v) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_ACKISO) = (v))
/*@}*/
/*!
* @name Register PMC_REGSC, field BGEN[4] (RW)
*
* BGEN controls whether the bandgap is enabled in lower power modes of
* operation (VLPx, LLS, and VLLSx). When on-chip peripherals require the bandgap voltage
* reference in low power modes of operation, set BGEN to continue to enable the
* bandgap operation. When the bandgap voltage reference is not needed in low
* power modes, clear BGEN to avoid excess power consumption.
*
* Values:
* - 0 - Bandgap voltage reference is disabled in VLPx , LLS , and VLLSx modes.
* - 1 - Bandgap voltage reference is enabled in VLPx , LLS , and VLLSx modes.
*/
/*@{*/
#define BP_PMC_REGSC_BGEN (4U) /*!< Bit position for PMC_REGSC_BGEN. */
#define BM_PMC_REGSC_BGEN (0x10U) /*!< Bit mask for PMC_REGSC_BGEN. */
#define BS_PMC_REGSC_BGEN (1U) /*!< Bit field size in bits for PMC_REGSC_BGEN. */
/*! @brief Read current value of the PMC_REGSC_BGEN field. */
#define BR_PMC_REGSC_BGEN(x) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_BGEN))
/*! @brief Format value for bitfield PMC_REGSC_BGEN. */
#define BF_PMC_REGSC_BGEN(v) ((uint8_t)((uint8_t)(v) << BP_PMC_REGSC_BGEN) & BM_PMC_REGSC_BGEN)
/*! @brief Set the BGEN field to a new value. */
#define BW_PMC_REGSC_BGEN(x, v) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_BGEN) = (v))
/*@}*/
/*******************************************************************************
* hw_pmc_t - module struct
******************************************************************************/
/*!
* @brief All PMC module registers.
*/
#pragma pack(1)
typedef struct _hw_pmc
{
__IO hw_pmc_lvdsc1_t LVDSC1; /*!< [0x0] Low Voltage Detect Status And Control 1 register */
__IO hw_pmc_lvdsc2_t LVDSC2; /*!< [0x1] Low Voltage Detect Status And Control 2 register */
__IO hw_pmc_regsc_t REGSC; /*!< [0x2] Regulator Status And Control register */
} hw_pmc_t;
#pragma pack()
/*! @brief Macro to access all PMC registers. */
/*! @param x PMC module instance base address. */
/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
* use the '&' operator, like <code>&HW_PMC(PMC_BASE)</code>. */
#define HW_PMC(x) (*(hw_pmc_t *)(x))
#endif /* __HW_PMC_REGISTERS_H__ */
/* EOF */

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@ -0,0 +1,892 @@
/*
** ###################################################################
** Compilers: Keil ARM C/C++ Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
** Version: rev. 2.5, 2014-05-06
** Build: b140604
**
** Abstract:
** Extension to the CMSIS register access layer header.
**
** Copyright (c) 2014 Freescale Semiconductor, Inc.
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** Revisions:
** - rev. 1.0 (2013-07-23)
** Initial version.
** - rev. 1.1 (2013-09-17)
** RM rev. 0.4 update.
** - rev. 2.0 (2013-10-29)
** Register accessor macros added to the memory map.
** Symbols for Processor Expert memory map compatibility added to the memory map.
** Startup file for gcc has been updated according to CMSIS 3.2.
** System initialization updated.
** - rev. 2.1 (2013-10-30)
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
** - rev. 2.2 (2013-12-20)
** Update according to reference manual rev. 0.6,
** - rev. 2.3 (2014-01-13)
** Update according to reference manual rev. 0.61,
** - rev. 2.4 (2014-02-10)
** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
** - rev. 2.5 (2014-05-06)
** Update according to reference manual rev. 1.0,
** Update of system and startup files.
** Module access macro module_BASES replaced by module_BASE_PTRS.
**
** ###################################################################
*/
/*
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
*
* This file was generated automatically and any changes may be lost.
*/
#ifndef __HW_PORT_REGISTERS_H__
#define __HW_PORT_REGISTERS_H__
#include "MK22F51212.h"
#include "fsl_bitaccess.h"
/*
* MK22F51212 PORT
*
* Pin Control and Interrupts
*
* Registers defined in this header file:
* - HW_PORT_PCRn - Pin Control Register n
* - HW_PORT_GPCLR - Global Pin Control Low Register
* - HW_PORT_GPCHR - Global Pin Control High Register
* - HW_PORT_ISFR - Interrupt Status Flag Register
* - HW_PORT_DFER - Digital Filter Enable Register
* - HW_PORT_DFCR - Digital Filter Clock Register
* - HW_PORT_DFWR - Digital Filter Width Register
*
* - hw_port_t - Struct containing all module registers.
*/
#define HW_PORT_INSTANCE_COUNT (5U) /*!< Number of instances of the PORT module. */
#define HW_PORTA (0U) /*!< Instance number for PORTA. */
#define HW_PORTB (1U) /*!< Instance number for PORTB. */
#define HW_PORTC (2U) /*!< Instance number for PORTC. */
#define HW_PORTD (3U) /*!< Instance number for PORTD. */
#define HW_PORTE (4U) /*!< Instance number for PORTE. */
/*******************************************************************************
* HW_PORT_PCRn - Pin Control Register n
******************************************************************************/
/*!
* @brief HW_PORT_PCRn - Pin Control Register n (RW)
*
* Reset value: 0x00000700U
*
* See the Signal Multiplexing and Pin Assignment chapter for the reset value of
* this device. See the GPIO Configuration section for details on the available
* functions for each pin. Do not modify pin configuration registers associated
* with pins not available in your selected package. All unbonded pins not
* available in your package will default to DISABLE state for lowest power consumption.
*/
typedef union _hw_port_pcrn
{
uint32_t U;
struct _hw_port_pcrn_bitfields
{
uint32_t PS : 1; /*!< [0] Pull Select */
uint32_t PE : 1; /*!< [1] Pull Enable */
uint32_t SRE : 1; /*!< [2] Slew Rate Enable */
uint32_t RESERVED0 : 1; /*!< [3] */
uint32_t PFE : 1; /*!< [4] Passive Filter Enable */
uint32_t ODE : 1; /*!< [5] Open Drain Enable */
uint32_t DSE : 1; /*!< [6] Drive Strength Enable */
uint32_t RESERVED1 : 1; /*!< [7] */
uint32_t MUX : 3; /*!< [10:8] Pin Mux Control */
uint32_t RESERVED2 : 4; /*!< [14:11] */
uint32_t LK : 1; /*!< [15] Lock Register */
uint32_t IRQC : 4; /*!< [19:16] Interrupt Configuration */
uint32_t RESERVED3 : 4; /*!< [23:20] */
uint32_t ISF : 1; /*!< [24] Interrupt Status Flag */
uint32_t RESERVED4 : 7; /*!< [31:25] */
} B;
} hw_port_pcrn_t;
/*!
* @name Constants and macros for entire PORT_PCRn register
*/
/*@{*/
#define HW_PORT_PCRn_COUNT (32U)
#define HW_PORT_PCRn_ADDR(x, n) ((x) + 0x0U + (0x4U * (n)))
#define HW_PORT_PCRn(x, n) (*(__IO hw_port_pcrn_t *) HW_PORT_PCRn_ADDR(x, n))
#define HW_PORT_PCRn_RD(x, n) (HW_PORT_PCRn(x, n).U)
#define HW_PORT_PCRn_WR(x, n, v) (HW_PORT_PCRn(x, n).U = (v))
#define HW_PORT_PCRn_SET(x, n, v) (HW_PORT_PCRn_WR(x, n, HW_PORT_PCRn_RD(x, n) | (v)))
#define HW_PORT_PCRn_CLR(x, n, v) (HW_PORT_PCRn_WR(x, n, HW_PORT_PCRn_RD(x, n) & ~(v)))
#define HW_PORT_PCRn_TOG(x, n, v) (HW_PORT_PCRn_WR(x, n, HW_PORT_PCRn_RD(x, n) ^ (v)))
/*@}*/
/*
* Constants & macros for individual PORT_PCRn bitfields
*/
/*!
* @name Register PORT_PCRn, field PS[0] (RW)
*
* Pull configuration is valid in all digital pin muxing modes.
*
* Values:
* - 0 - Internal pulldown resistor is enabled on the corresponding pin, if the
* corresponding PE field is set.
* - 1 - Internal pullup resistor is enabled on the corresponding pin, if the
* corresponding PE field is set.
*/
/*@{*/
#define BP_PORT_PCRn_PS (0U) /*!< Bit position for PORT_PCRn_PS. */
#define BM_PORT_PCRn_PS (0x00000001U) /*!< Bit mask for PORT_PCRn_PS. */
#define BS_PORT_PCRn_PS (1U) /*!< Bit field size in bits for PORT_PCRn_PS. */
/*! @brief Read current value of the PORT_PCRn_PS field. */
#define BR_PORT_PCRn_PS(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PS))
/*! @brief Format value for bitfield PORT_PCRn_PS. */
#define BF_PORT_PCRn_PS(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_PS) & BM_PORT_PCRn_PS)
/*! @brief Set the PS field to a new value. */
#define BW_PORT_PCRn_PS(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PS) = (v))
/*@}*/
/*!
* @name Register PORT_PCRn, field PE[1] (RW)
*
* Pull configuration is valid in all digital pin muxing modes.
*
* Values:
* - 0 - Internal pullup or pulldown resistor is not enabled on the
* corresponding pin.
* - 1 - Internal pullup or pulldown resistor is enabled on the corresponding
* pin, if the pin is configured as a digital input.
*/
/*@{*/
#define BP_PORT_PCRn_PE (1U) /*!< Bit position for PORT_PCRn_PE. */
#define BM_PORT_PCRn_PE (0x00000002U) /*!< Bit mask for PORT_PCRn_PE. */
#define BS_PORT_PCRn_PE (1U) /*!< Bit field size in bits for PORT_PCRn_PE. */
/*! @brief Read current value of the PORT_PCRn_PE field. */
#define BR_PORT_PCRn_PE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PE))
/*! @brief Format value for bitfield PORT_PCRn_PE. */
#define BF_PORT_PCRn_PE(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_PE) & BM_PORT_PCRn_PE)
/*! @brief Set the PE field to a new value. */
#define BW_PORT_PCRn_PE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PE) = (v))
/*@}*/
/*!
* @name Register PORT_PCRn, field SRE[2] (RW)
*
* Slew rate configuration is valid in all digital pin muxing modes.
*
* Values:
* - 0 - Fast slew rate is configured on the corresponding pin, if the pin is
* configured as a digital output.
* - 1 - Slow slew rate is configured on the corresponding pin, if the pin is
* configured as a digital output.
*/
/*@{*/
#define BP_PORT_PCRn_SRE (2U) /*!< Bit position for PORT_PCRn_SRE. */
#define BM_PORT_PCRn_SRE (0x00000004U) /*!< Bit mask for PORT_PCRn_SRE. */
#define BS_PORT_PCRn_SRE (1U) /*!< Bit field size in bits for PORT_PCRn_SRE. */
/*! @brief Read current value of the PORT_PCRn_SRE field. */
#define BR_PORT_PCRn_SRE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_SRE))
/*! @brief Format value for bitfield PORT_PCRn_SRE. */
#define BF_PORT_PCRn_SRE(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_SRE) & BM_PORT_PCRn_SRE)
/*! @brief Set the SRE field to a new value. */
#define BW_PORT_PCRn_SRE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_SRE) = (v))
/*@}*/
/*!
* @name Register PORT_PCRn, field PFE[4] (RW)
*
* Passive filter configuration is valid in all digital pin muxing modes.
*
* Values:
* - 0 - Passive input filter is disabled on the corresponding pin.
* - 1 - Passive input filter is enabled on the corresponding pin, if the pin is
* configured as a digital input. Refer to the device data sheet for filter
* characteristics.
*/
/*@{*/
#define BP_PORT_PCRn_PFE (4U) /*!< Bit position for PORT_PCRn_PFE. */
#define BM_PORT_PCRn_PFE (0x00000010U) /*!< Bit mask for PORT_PCRn_PFE. */
#define BS_PORT_PCRn_PFE (1U) /*!< Bit field size in bits for PORT_PCRn_PFE. */
/*! @brief Read current value of the PORT_PCRn_PFE field. */
#define BR_PORT_PCRn_PFE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PFE))
/*! @brief Format value for bitfield PORT_PCRn_PFE. */
#define BF_PORT_PCRn_PFE(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_PFE) & BM_PORT_PCRn_PFE)
/*! @brief Set the PFE field to a new value. */
#define BW_PORT_PCRn_PFE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PFE) = (v))
/*@}*/
/*!
* @name Register PORT_PCRn, field ODE[5] (RW)
*
* Open drain configuration is valid in all digital pin muxing modes.
*
* Values:
* - 0 - Open drain output is disabled on the corresponding pin.
* - 1 - Open drain output is enabled on the corresponding pin, if the pin is
* configured as a digital output.
*/
/*@{*/
#define BP_PORT_PCRn_ODE (5U) /*!< Bit position for PORT_PCRn_ODE. */
#define BM_PORT_PCRn_ODE (0x00000020U) /*!< Bit mask for PORT_PCRn_ODE. */
#define BS_PORT_PCRn_ODE (1U) /*!< Bit field size in bits for PORT_PCRn_ODE. */
/*! @brief Read current value of the PORT_PCRn_ODE field. */
#define BR_PORT_PCRn_ODE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ODE))
/*! @brief Format value for bitfield PORT_PCRn_ODE. */
#define BF_PORT_PCRn_ODE(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_ODE) & BM_PORT_PCRn_ODE)
/*! @brief Set the ODE field to a new value. */
#define BW_PORT_PCRn_ODE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ODE) = (v))
/*@}*/
/*!
* @name Register PORT_PCRn, field DSE[6] (RW)
*
* Drive strength configuration is valid in all digital pin muxing modes.
*
* Values:
* - 0 - Low drive strength is configured on the corresponding pin, if pin is
* configured as a digital output.
* - 1 - High drive strength is configured on the corresponding pin, if pin is
* configured as a digital output.
*/
/*@{*/
#define BP_PORT_PCRn_DSE (6U) /*!< Bit position for PORT_PCRn_DSE. */
#define BM_PORT_PCRn_DSE (0x00000040U) /*!< Bit mask for PORT_PCRn_DSE. */
#define BS_PORT_PCRn_DSE (1U) /*!< Bit field size in bits for PORT_PCRn_DSE. */
/*! @brief Read current value of the PORT_PCRn_DSE field. */
#define BR_PORT_PCRn_DSE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_DSE))
/*! @brief Format value for bitfield PORT_PCRn_DSE. */
#define BF_PORT_PCRn_DSE(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_DSE) & BM_PORT_PCRn_DSE)
/*! @brief Set the DSE field to a new value. */
#define BW_PORT_PCRn_DSE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_DSE) = (v))
/*@}*/
/*!
* @name Register PORT_PCRn, field MUX[10:8] (RW)
*
* Not all pins support all pin muxing slots. Unimplemented pin muxing slots are
* reserved and may result in configuring the pin for a different pin muxing
* slot. The corresponding pin is configured in the following pin muxing slot as
* follows:
*
* Values:
* - 000 - Pin disabled (analog).
* - 001 - Alternative 1 (GPIO).
* - 010 - Alternative 2 (chip-specific).
* - 011 - Alternative 3 (chip-specific).
* - 100 - Alternative 4 (chip-specific).
* - 101 - Alternative 5 (chip-specific).
* - 110 - Alternative 6 (chip-specific).
* - 111 - Alternative 7 (chip-specific).
*/
/*@{*/
#define BP_PORT_PCRn_MUX (8U) /*!< Bit position for PORT_PCRn_MUX. */
#define BM_PORT_PCRn_MUX (0x00000700U) /*!< Bit mask for PORT_PCRn_MUX. */
#define BS_PORT_PCRn_MUX (3U) /*!< Bit field size in bits for PORT_PCRn_MUX. */
/*! @brief Read current value of the PORT_PCRn_MUX field. */
#define BR_PORT_PCRn_MUX(x, n) (HW_PORT_PCRn(x, n).B.MUX)
/*! @brief Format value for bitfield PORT_PCRn_MUX. */
#define BF_PORT_PCRn_MUX(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_MUX) & BM_PORT_PCRn_MUX)
/*! @brief Set the MUX field to a new value. */
#define BW_PORT_PCRn_MUX(x, n, v) (HW_PORT_PCRn_WR(x, n, (HW_PORT_PCRn_RD(x, n) & ~BM_PORT_PCRn_MUX) | BF_PORT_PCRn_MUX(v)))
/*@}*/
/*!
* @name Register PORT_PCRn, field LK[15] (RW)
*
* Values:
* - 0 - Pin Control Register fields [15:0] are not locked.
* - 1 - Pin Control Register fields [15:0] are locked and cannot be updated
* until the next system reset.
*/
/*@{*/
#define BP_PORT_PCRn_LK (15U) /*!< Bit position for PORT_PCRn_LK. */
#define BM_PORT_PCRn_LK (0x00008000U) /*!< Bit mask for PORT_PCRn_LK. */
#define BS_PORT_PCRn_LK (1U) /*!< Bit field size in bits for PORT_PCRn_LK. */
/*! @brief Read current value of the PORT_PCRn_LK field. */
#define BR_PORT_PCRn_LK(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_LK))
/*! @brief Format value for bitfield PORT_PCRn_LK. */
#define BF_PORT_PCRn_LK(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_LK) & BM_PORT_PCRn_LK)
/*! @brief Set the LK field to a new value. */
#define BW_PORT_PCRn_LK(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_LK) = (v))
/*@}*/
/*!
* @name Register PORT_PCRn, field IRQC[19:16] (RW)
*
* The pin interrupt configuration is valid in all digital pin muxing modes. The
* corresponding pin is configured to generate interrupt/DMA request as follows:
*
* Values:
* - 0000 - Interrupt/DMA request disabled.
* - 0001 - DMA request on rising edge.
* - 0010 - DMA request on falling edge.
* - 0011 - DMA request on either edge.
* - 1000 - Interrupt when logic 0.
* - 1001 - Interrupt on rising-edge.
* - 1010 - Interrupt on falling-edge.
* - 1011 - Interrupt on either edge.
* - 1100 - Interrupt when logic 1.
*/
/*@{*/
#define BP_PORT_PCRn_IRQC (16U) /*!< Bit position for PORT_PCRn_IRQC. */
#define BM_PORT_PCRn_IRQC (0x000F0000U) /*!< Bit mask for PORT_PCRn_IRQC. */
#define BS_PORT_PCRn_IRQC (4U) /*!< Bit field size in bits for PORT_PCRn_IRQC. */
/*! @brief Read current value of the PORT_PCRn_IRQC field. */
#define BR_PORT_PCRn_IRQC(x, n) (HW_PORT_PCRn(x, n).B.IRQC)
/*! @brief Format value for bitfield PORT_PCRn_IRQC. */
#define BF_PORT_PCRn_IRQC(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_IRQC) & BM_PORT_PCRn_IRQC)
/*! @brief Set the IRQC field to a new value. */
#define BW_PORT_PCRn_IRQC(x, n, v) (HW_PORT_PCRn_WR(x, n, (HW_PORT_PCRn_RD(x, n) & ~BM_PORT_PCRn_IRQC) | BF_PORT_PCRn_IRQC(v)))
/*@}*/
/*!
* @name Register PORT_PCRn, field ISF[24] (W1C)
*
* The pin interrupt configuration is valid in all digital pin muxing modes.
*
* Values:
* - 0 - Configured interrupt is not detected.
* - 1 - Configured interrupt is detected. If the pin is configured to generate
* a DMA request, then the corresponding flag will be cleared automatically
* at the completion of the requested DMA transfer. Otherwise, the flag
* remains set until a logic 1 is written to the flag. If the pin is configured for
* a level sensitive interrupt and the pin remains asserted, then the flag
* is set again immediately after it is cleared.
*/
/*@{*/
#define BP_PORT_PCRn_ISF (24U) /*!< Bit position for PORT_PCRn_ISF. */
#define BM_PORT_PCRn_ISF (0x01000000U) /*!< Bit mask for PORT_PCRn_ISF. */
#define BS_PORT_PCRn_ISF (1U) /*!< Bit field size in bits for PORT_PCRn_ISF. */
/*! @brief Read current value of the PORT_PCRn_ISF field. */
#define BR_PORT_PCRn_ISF(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ISF))
/*! @brief Format value for bitfield PORT_PCRn_ISF. */
#define BF_PORT_PCRn_ISF(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_ISF) & BM_PORT_PCRn_ISF)
/*! @brief Set the ISF field to a new value. */
#define BW_PORT_PCRn_ISF(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ISF) = (v))
/*@}*/
/*******************************************************************************
* HW_PORT_GPCLR - Global Pin Control Low Register
******************************************************************************/
/*!
* @brief HW_PORT_GPCLR - Global Pin Control Low Register (WORZ)
*
* Reset value: 0x00000000U
*
* Only 32-bit writes are supported to this register.
*/
typedef union _hw_port_gpclr
{
uint32_t U;
struct _hw_port_gpclr_bitfields
{
uint32_t GPWD : 16; /*!< [15:0] Global Pin Write Data */
uint32_t GPWE : 16; /*!< [31:16] Global Pin Write Enable */
} B;
} hw_port_gpclr_t;
/*!
* @name Constants and macros for entire PORT_GPCLR register
*/
/*@{*/
#define HW_PORT_GPCLR_ADDR(x) ((x) + 0x80U)
#define HW_PORT_GPCLR(x) (*(__O hw_port_gpclr_t *) HW_PORT_GPCLR_ADDR(x))
#define HW_PORT_GPCLR_RD(x) (HW_PORT_GPCLR(x).U)
#define HW_PORT_GPCLR_WR(x, v) (HW_PORT_GPCLR(x).U = (v))
/*@}*/
/*
* Constants & macros for individual PORT_GPCLR bitfields
*/
/*!
* @name Register PORT_GPCLR, field GPWD[15:0] (WORZ)
*
* Write value that is written to all Pin Control Registers bits [15:0] that are
* selected by GPWE.
*/
/*@{*/
#define BP_PORT_GPCLR_GPWD (0U) /*!< Bit position for PORT_GPCLR_GPWD. */
#define BM_PORT_GPCLR_GPWD (0x0000FFFFU) /*!< Bit mask for PORT_GPCLR_GPWD. */
#define BS_PORT_GPCLR_GPWD (16U) /*!< Bit field size in bits for PORT_GPCLR_GPWD. */
/*! @brief Format value for bitfield PORT_GPCLR_GPWD. */
#define BF_PORT_GPCLR_GPWD(v) ((uint32_t)((uint32_t)(v) << BP_PORT_GPCLR_GPWD) & BM_PORT_GPCLR_GPWD)
/*! @brief Set the GPWD field to a new value. */
#define BW_PORT_GPCLR_GPWD(x, v) (HW_PORT_GPCLR_WR(x, (HW_PORT_GPCLR_RD(x) & ~BM_PORT_GPCLR_GPWD) | BF_PORT_GPCLR_GPWD(v)))
/*@}*/
/*!
* @name Register PORT_GPCLR, field GPWE[31:16] (WORZ)
*
* Selects which Pin Control Registers (15 through 0) bits [15:0] update with
* the value in GPWD. If a selected Pin Control Register is locked then the write
* to that register is ignored.
*
* Values:
* - 0 - Corresponding Pin Control Register is not updated with the value in
* GPWD.
* - 1 - Corresponding Pin Control Register is updated with the value in GPWD.
*/
/*@{*/
#define BP_PORT_GPCLR_GPWE (16U) /*!< Bit position for PORT_GPCLR_GPWE. */
#define BM_PORT_GPCLR_GPWE (0xFFFF0000U) /*!< Bit mask for PORT_GPCLR_GPWE. */
#define BS_PORT_GPCLR_GPWE (16U) /*!< Bit field size in bits for PORT_GPCLR_GPWE. */
/*! @brief Format value for bitfield PORT_GPCLR_GPWE. */
#define BF_PORT_GPCLR_GPWE(v) ((uint32_t)((uint32_t)(v) << BP_PORT_GPCLR_GPWE) & BM_PORT_GPCLR_GPWE)
/*! @brief Set the GPWE field to a new value. */
#define BW_PORT_GPCLR_GPWE(x, v) (HW_PORT_GPCLR_WR(x, (HW_PORT_GPCLR_RD(x) & ~BM_PORT_GPCLR_GPWE) | BF_PORT_GPCLR_GPWE(v)))
/*@}*/
/*******************************************************************************
* HW_PORT_GPCHR - Global Pin Control High Register
******************************************************************************/
/*!
* @brief HW_PORT_GPCHR - Global Pin Control High Register (WORZ)
*
* Reset value: 0x00000000U
*
* Only 32-bit writes are supported to this register.
*/
typedef union _hw_port_gpchr
{
uint32_t U;
struct _hw_port_gpchr_bitfields
{
uint32_t GPWD : 16; /*!< [15:0] Global Pin Write Data */
uint32_t GPWE : 16; /*!< [31:16] Global Pin Write Enable */
} B;
} hw_port_gpchr_t;
/*!
* @name Constants and macros for entire PORT_GPCHR register
*/
/*@{*/
#define HW_PORT_GPCHR_ADDR(x) ((x) + 0x84U)
#define HW_PORT_GPCHR(x) (*(__O hw_port_gpchr_t *) HW_PORT_GPCHR_ADDR(x))
#define HW_PORT_GPCHR_RD(x) (HW_PORT_GPCHR(x).U)
#define HW_PORT_GPCHR_WR(x, v) (HW_PORT_GPCHR(x).U = (v))
/*@}*/
/*
* Constants & macros for individual PORT_GPCHR bitfields
*/
/*!
* @name Register PORT_GPCHR, field GPWD[15:0] (WORZ)
*
* Write value that is written to all Pin Control Registers bits [15:0] that are
* selected by GPWE.
*/
/*@{*/
#define BP_PORT_GPCHR_GPWD (0U) /*!< Bit position for PORT_GPCHR_GPWD. */
#define BM_PORT_GPCHR_GPWD (0x0000FFFFU) /*!< Bit mask for PORT_GPCHR_GPWD. */
#define BS_PORT_GPCHR_GPWD (16U) /*!< Bit field size in bits for PORT_GPCHR_GPWD. */
/*! @brief Format value for bitfield PORT_GPCHR_GPWD. */
#define BF_PORT_GPCHR_GPWD(v) ((uint32_t)((uint32_t)(v) << BP_PORT_GPCHR_GPWD) & BM_PORT_GPCHR_GPWD)
/*! @brief Set the GPWD field to a new value. */
#define BW_PORT_GPCHR_GPWD(x, v) (HW_PORT_GPCHR_WR(x, (HW_PORT_GPCHR_RD(x) & ~BM_PORT_GPCHR_GPWD) | BF_PORT_GPCHR_GPWD(v)))
/*@}*/
/*!
* @name Register PORT_GPCHR, field GPWE[31:16] (WORZ)
*
* Selects which Pin Control Registers (31 through 16) bits [15:0] update with
* the value in GPWD. If a selected Pin Control Register is locked then the write
* to that register is ignored.
*
* Values:
* - 0 - Corresponding Pin Control Register is not updated with the value in
* GPWD.
* - 1 - Corresponding Pin Control Register is updated with the value in GPWD.
*/
/*@{*/
#define BP_PORT_GPCHR_GPWE (16U) /*!< Bit position for PORT_GPCHR_GPWE. */
#define BM_PORT_GPCHR_GPWE (0xFFFF0000U) /*!< Bit mask for PORT_GPCHR_GPWE. */
#define BS_PORT_GPCHR_GPWE (16U) /*!< Bit field size in bits for PORT_GPCHR_GPWE. */
/*! @brief Format value for bitfield PORT_GPCHR_GPWE. */
#define BF_PORT_GPCHR_GPWE(v) ((uint32_t)((uint32_t)(v) << BP_PORT_GPCHR_GPWE) & BM_PORT_GPCHR_GPWE)
/*! @brief Set the GPWE field to a new value. */
#define BW_PORT_GPCHR_GPWE(x, v) (HW_PORT_GPCHR_WR(x, (HW_PORT_GPCHR_RD(x) & ~BM_PORT_GPCHR_GPWE) | BF_PORT_GPCHR_GPWE(v)))
/*@}*/
/*******************************************************************************
* HW_PORT_ISFR - Interrupt Status Flag Register
******************************************************************************/
/*!
* @brief HW_PORT_ISFR - Interrupt Status Flag Register (W1C)
*
* Reset value: 0x00000000U
*
* The pin interrupt configuration is valid in all digital pin muxing modes. The
* Interrupt Status Flag for each pin is also visible in the corresponding Pin
* Control Register, and each flag can be cleared in either location.
*/
typedef union _hw_port_isfr
{
uint32_t U;
struct _hw_port_isfr_bitfields
{
uint32_t ISF : 32; /*!< [31:0] Interrupt Status Flag */
} B;
} hw_port_isfr_t;
/*!
* @name Constants and macros for entire PORT_ISFR register
*/
/*@{*/
#define HW_PORT_ISFR_ADDR(x) ((x) + 0xA0U)
#define HW_PORT_ISFR(x) (*(__IO hw_port_isfr_t *) HW_PORT_ISFR_ADDR(x))
#define HW_PORT_ISFR_RD(x) (HW_PORT_ISFR(x).U)
#define HW_PORT_ISFR_WR(x, v) (HW_PORT_ISFR(x).U = (v))
#define HW_PORT_ISFR_SET(x, v) (HW_PORT_ISFR_WR(x, HW_PORT_ISFR_RD(x) | (v)))
#define HW_PORT_ISFR_CLR(x, v) (HW_PORT_ISFR_WR(x, HW_PORT_ISFR_RD(x) & ~(v)))
#define HW_PORT_ISFR_TOG(x, v) (HW_PORT_ISFR_WR(x, HW_PORT_ISFR_RD(x) ^ (v)))
/*@}*/
/*
* Constants & macros for individual PORT_ISFR bitfields
*/
/*!
* @name Register PORT_ISFR, field ISF[31:0] (W1C)
*
* Each bit in the field indicates the detection of the configured interrupt of
* the same number as the field.
*
* Values:
* - 0 - Configured interrupt is not detected.
* - 1 - Configured interrupt is detected. If the pin is configured to generate
* a DMA request, then the corresponding flag will be cleared automatically
* at the completion of the requested DMA transfer. Otherwise, the flag
* remains set until a logic 1 is written to the flag. If the pin is configured for
* a level sensitive interrupt and the pin remains asserted, then the flag
* is set again immediately after it is cleared.
*/
/*@{*/
#define BP_PORT_ISFR_ISF (0U) /*!< Bit position for PORT_ISFR_ISF. */
#define BM_PORT_ISFR_ISF (0xFFFFFFFFU) /*!< Bit mask for PORT_ISFR_ISF. */
#define BS_PORT_ISFR_ISF (32U) /*!< Bit field size in bits for PORT_ISFR_ISF. */
/*! @brief Read current value of the PORT_ISFR_ISF field. */
#define BR_PORT_ISFR_ISF(x) (HW_PORT_ISFR(x).U)
/*! @brief Format value for bitfield PORT_ISFR_ISF. */
#define BF_PORT_ISFR_ISF(v) ((uint32_t)((uint32_t)(v) << BP_PORT_ISFR_ISF) & BM_PORT_ISFR_ISF)
/*! @brief Set the ISF field to a new value. */
#define BW_PORT_ISFR_ISF(x, v) (HW_PORT_ISFR_WR(x, v))
/*@}*/
/*******************************************************************************
* HW_PORT_DFER - Digital Filter Enable Register
******************************************************************************/
/*!
* @brief HW_PORT_DFER - Digital Filter Enable Register (RW)
*
* Reset value: 0x00000000U
*
* The corresponding bit is read only for pins that do not support a digital
* filter. Refer to the Chapter of Signal Multiplexing and Signal Descriptions for
* the pins that support digital filter. The digital filter configuration is valid
* in all digital pin muxing modes.
*/
typedef union _hw_port_dfer
{
uint32_t U;
struct _hw_port_dfer_bitfields
{
uint32_t DFE : 32; /*!< [31:0] Digital Filter Enable */
} B;
} hw_port_dfer_t;
/*!
* @name Constants and macros for entire PORT_DFER register
*/
/*@{*/
#define HW_PORT_DFER_ADDR(x) ((x) + 0xC0U)
#define HW_PORT_DFER(x) (*(__IO hw_port_dfer_t *) HW_PORT_DFER_ADDR(x))
#define HW_PORT_DFER_RD(x) (HW_PORT_DFER(x).U)
#define HW_PORT_DFER_WR(x, v) (HW_PORT_DFER(x).U = (v))
#define HW_PORT_DFER_SET(x, v) (HW_PORT_DFER_WR(x, HW_PORT_DFER_RD(x) | (v)))
#define HW_PORT_DFER_CLR(x, v) (HW_PORT_DFER_WR(x, HW_PORT_DFER_RD(x) & ~(v)))
#define HW_PORT_DFER_TOG(x, v) (HW_PORT_DFER_WR(x, HW_PORT_DFER_RD(x) ^ (v)))
/*@}*/
/*
* Constants & macros for individual PORT_DFER bitfields
*/
/*!
* @name Register PORT_DFER, field DFE[31:0] (RW)
*
* The digital filter configuration is valid in all digital pin muxing modes.
* The output of each digital filter is reset to zero at system reset and whenever
* the digital filter is disabled. Each bit in the field enables the digital
* filter of the same number as the field.
*
* Values:
* - 0 - Digital filter is disabled on the corresponding pin and output of the
* digital filter is reset to zero.
* - 1 - Digital filter is enabled on the corresponding pin, if the pin is
* configured as a digital input.
*/
/*@{*/
#define BP_PORT_DFER_DFE (0U) /*!< Bit position for PORT_DFER_DFE. */
#define BM_PORT_DFER_DFE (0xFFFFFFFFU) /*!< Bit mask for PORT_DFER_DFE. */
#define BS_PORT_DFER_DFE (32U) /*!< Bit field size in bits for PORT_DFER_DFE. */
/*! @brief Read current value of the PORT_DFER_DFE field. */
#define BR_PORT_DFER_DFE(x) (HW_PORT_DFER(x).U)
/*! @brief Format value for bitfield PORT_DFER_DFE. */
#define BF_PORT_DFER_DFE(v) ((uint32_t)((uint32_t)(v) << BP_PORT_DFER_DFE) & BM_PORT_DFER_DFE)
/*! @brief Set the DFE field to a new value. */
#define BW_PORT_DFER_DFE(x, v) (HW_PORT_DFER_WR(x, v))
/*@}*/
/*******************************************************************************
* HW_PORT_DFCR - Digital Filter Clock Register
******************************************************************************/
/*!
* @brief HW_PORT_DFCR - Digital Filter Clock Register (RW)
*
* Reset value: 0x00000000U
*
* This register is read only for ports that do not support a digital filter.
* The digital filter configuration is valid in all digital pin muxing modes.
*/
typedef union _hw_port_dfcr
{
uint32_t U;
struct _hw_port_dfcr_bitfields
{
uint32_t CS : 1; /*!< [0] Clock Source */
uint32_t RESERVED0 : 31; /*!< [31:1] */
} B;
} hw_port_dfcr_t;
/*!
* @name Constants and macros for entire PORT_DFCR register
*/
/*@{*/
#define HW_PORT_DFCR_ADDR(x) ((x) + 0xC4U)
#define HW_PORT_DFCR(x) (*(__IO hw_port_dfcr_t *) HW_PORT_DFCR_ADDR(x))
#define HW_PORT_DFCR_RD(x) (HW_PORT_DFCR(x).U)
#define HW_PORT_DFCR_WR(x, v) (HW_PORT_DFCR(x).U = (v))
#define HW_PORT_DFCR_SET(x, v) (HW_PORT_DFCR_WR(x, HW_PORT_DFCR_RD(x) | (v)))
#define HW_PORT_DFCR_CLR(x, v) (HW_PORT_DFCR_WR(x, HW_PORT_DFCR_RD(x) & ~(v)))
#define HW_PORT_DFCR_TOG(x, v) (HW_PORT_DFCR_WR(x, HW_PORT_DFCR_RD(x) ^ (v)))
/*@}*/
/*
* Constants & macros for individual PORT_DFCR bitfields
*/
/*!
* @name Register PORT_DFCR, field CS[0] (RW)
*
* The digital filter configuration is valid in all digital pin muxing modes.
* Configures the clock source for the digital input filters. Changing the filter
* clock source must be done only when all digital filters are disabled.
*
* Values:
* - 0 - Digital filters are clocked by the bus clock.
* - 1 - Digital filters are clocked by the 1 kHz LPO clock.
*/
/*@{*/
#define BP_PORT_DFCR_CS (0U) /*!< Bit position for PORT_DFCR_CS. */
#define BM_PORT_DFCR_CS (0x00000001U) /*!< Bit mask for PORT_DFCR_CS. */
#define BS_PORT_DFCR_CS (1U) /*!< Bit field size in bits for PORT_DFCR_CS. */
/*! @brief Read current value of the PORT_DFCR_CS field. */
#define BR_PORT_DFCR_CS(x) (BITBAND_ACCESS32(HW_PORT_DFCR_ADDR(x), BP_PORT_DFCR_CS))
/*! @brief Format value for bitfield PORT_DFCR_CS. */
#define BF_PORT_DFCR_CS(v) ((uint32_t)((uint32_t)(v) << BP_PORT_DFCR_CS) & BM_PORT_DFCR_CS)
/*! @brief Set the CS field to a new value. */
#define BW_PORT_DFCR_CS(x, v) (BITBAND_ACCESS32(HW_PORT_DFCR_ADDR(x), BP_PORT_DFCR_CS) = (v))
/*@}*/
/*******************************************************************************
* HW_PORT_DFWR - Digital Filter Width Register
******************************************************************************/
/*!
* @brief HW_PORT_DFWR - Digital Filter Width Register (RW)
*
* Reset value: 0x00000000U
*
* This register is read only for ports that do not support a digital filter.
* The digital filter configuration is valid in all digital pin muxing modes.
*/
typedef union _hw_port_dfwr
{
uint32_t U;
struct _hw_port_dfwr_bitfields
{
uint32_t FILT : 5; /*!< [4:0] Filter Length */
uint32_t RESERVED0 : 27; /*!< [31:5] */
} B;
} hw_port_dfwr_t;
/*!
* @name Constants and macros for entire PORT_DFWR register
*/
/*@{*/
#define HW_PORT_DFWR_ADDR(x) ((x) + 0xC8U)
#define HW_PORT_DFWR(x) (*(__IO hw_port_dfwr_t *) HW_PORT_DFWR_ADDR(x))
#define HW_PORT_DFWR_RD(x) (HW_PORT_DFWR(x).U)
#define HW_PORT_DFWR_WR(x, v) (HW_PORT_DFWR(x).U = (v))
#define HW_PORT_DFWR_SET(x, v) (HW_PORT_DFWR_WR(x, HW_PORT_DFWR_RD(x) | (v)))
#define HW_PORT_DFWR_CLR(x, v) (HW_PORT_DFWR_WR(x, HW_PORT_DFWR_RD(x) & ~(v)))
#define HW_PORT_DFWR_TOG(x, v) (HW_PORT_DFWR_WR(x, HW_PORT_DFWR_RD(x) ^ (v)))
/*@}*/
/*
* Constants & macros for individual PORT_DFWR bitfields
*/
/*!
* @name Register PORT_DFWR, field FILT[4:0] (RW)
*
* The digital filter configuration is valid in all digital pin muxing modes.
* Configures the maximum size of the glitches, in clock cycles, that the digital
* filter absorbs for the enabled digital filters. Glitches that are longer than
* this register setting will pass through the digital filter, and glitches that
* are equal to or less than this register setting are filtered. Changing the
* filter length must be done only after all filters are disabled.
*/
/*@{*/
#define BP_PORT_DFWR_FILT (0U) /*!< Bit position for PORT_DFWR_FILT. */
#define BM_PORT_DFWR_FILT (0x0000001FU) /*!< Bit mask for PORT_DFWR_FILT. */
#define BS_PORT_DFWR_FILT (5U) /*!< Bit field size in bits for PORT_DFWR_FILT. */
/*! @brief Read current value of the PORT_DFWR_FILT field. */
#define BR_PORT_DFWR_FILT(x) (HW_PORT_DFWR(x).B.FILT)
/*! @brief Format value for bitfield PORT_DFWR_FILT. */
#define BF_PORT_DFWR_FILT(v) ((uint32_t)((uint32_t)(v) << BP_PORT_DFWR_FILT) & BM_PORT_DFWR_FILT)
/*! @brief Set the FILT field to a new value. */
#define BW_PORT_DFWR_FILT(x, v) (HW_PORT_DFWR_WR(x, (HW_PORT_DFWR_RD(x) & ~BM_PORT_DFWR_FILT) | BF_PORT_DFWR_FILT(v)))
/*@}*/
/*******************************************************************************
* hw_port_t - module struct
******************************************************************************/
/*!
* @brief All PORT module registers.
*/
#pragma pack(1)
typedef struct _hw_port
{
__IO hw_port_pcrn_t PCRn[32]; /*!< [0x0] Pin Control Register n */
__O hw_port_gpclr_t GPCLR; /*!< [0x80] Global Pin Control Low Register */
__O hw_port_gpchr_t GPCHR; /*!< [0x84] Global Pin Control High Register */
uint8_t _reserved0[24];
__IO hw_port_isfr_t ISFR; /*!< [0xA0] Interrupt Status Flag Register */
uint8_t _reserved1[28];
__IO hw_port_dfer_t DFER; /*!< [0xC0] Digital Filter Enable Register */
__IO hw_port_dfcr_t DFCR; /*!< [0xC4] Digital Filter Clock Register */
__IO hw_port_dfwr_t DFWR; /*!< [0xC8] Digital Filter Width Register */
} hw_port_t;
#pragma pack()
/*! @brief Macro to access all PORT registers. */
/*! @param x PORT module instance base address. */
/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
* use the '&' operator, like <code>&HW_PORT(PORTA_BASE)</code>. */
#define HW_PORT(x) (*(hw_port_t *)(x))
#endif /* __HW_PORT_REGISTERS_H__ */
/* EOF */

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/*
** ###################################################################
** Compilers: Keil ARM C/C++ Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
** Version: rev. 2.5, 2014-05-06
** Build: b140604
**
** Abstract:
** Extension to the CMSIS register access layer header.
**
** Copyright (c) 2014 Freescale Semiconductor, Inc.
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** Revisions:
** - rev. 1.0 (2013-07-23)
** Initial version.
** - rev. 1.1 (2013-09-17)
** RM rev. 0.4 update.
** - rev. 2.0 (2013-10-29)
** Register accessor macros added to the memory map.
** Symbols for Processor Expert memory map compatibility added to the memory map.
** Startup file for gcc has been updated according to CMSIS 3.2.
** System initialization updated.
** - rev. 2.1 (2013-10-30)
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
** - rev. 2.2 (2013-12-20)
** Update according to reference manual rev. 0.6,
** - rev. 2.3 (2014-01-13)
** Update according to reference manual rev. 0.61,
** - rev. 2.4 (2014-02-10)
** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
** - rev. 2.5 (2014-05-06)
** Update according to reference manual rev. 1.0,
** Update of system and startup files.
** Module access macro module_BASES replaced by module_BASE_PTRS.
**
** ###################################################################
*/
/*
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
*
* This file was generated automatically and any changes may be lost.
*/
#ifndef __HW_RFSYS_REGISTERS_H__
#define __HW_RFSYS_REGISTERS_H__
#include "MK22F51212.h"
#include "fsl_bitaccess.h"
/*
* MK22F51212 RFSYS
*
* System register file
*
* Registers defined in this header file:
* - HW_RFSYS_REGn - Register file register
*
* - hw_rfsys_t - Struct containing all module registers.
*/
#define HW_RFSYS_INSTANCE_COUNT (1U) /*!< Number of instances of the RFSYS module. */
/*******************************************************************************
* HW_RFSYS_REGn - Register file register
******************************************************************************/
/*!
* @brief HW_RFSYS_REGn - Register file register (RW)
*
* Reset value: 0x00000000U
*
* Each register can be accessed as 8-, 16-, or 32-bits.
*/
typedef union _hw_rfsys_regn
{
uint32_t U;
struct _hw_rfsys_regn_bitfields
{
uint32_t LL : 8; /*!< [7:0] */
uint32_t LH : 8; /*!< [15:8] */
uint32_t HL : 8; /*!< [23:16] */
uint32_t HH : 8; /*!< [31:24] */
} B;
} hw_rfsys_regn_t;
/*!
* @name Constants and macros for entire RFSYS_REGn register
*/
/*@{*/
#define HW_RFSYS_REGn_COUNT (8U)
#define HW_RFSYS_REGn_ADDR(x, n) ((x) + 0x0U + (0x4U * (n)))
#define HW_RFSYS_REGn(x, n) (*(__IO hw_rfsys_regn_t *) HW_RFSYS_REGn_ADDR(x, n))
#define HW_RFSYS_REGn_RD(x, n) (HW_RFSYS_REGn(x, n).U)
#define HW_RFSYS_REGn_WR(x, n, v) (HW_RFSYS_REGn(x, n).U = (v))
#define HW_RFSYS_REGn_SET(x, n, v) (HW_RFSYS_REGn_WR(x, n, HW_RFSYS_REGn_RD(x, n) | (v)))
#define HW_RFSYS_REGn_CLR(x, n, v) (HW_RFSYS_REGn_WR(x, n, HW_RFSYS_REGn_RD(x, n) & ~(v)))
#define HW_RFSYS_REGn_TOG(x, n, v) (HW_RFSYS_REGn_WR(x, n, HW_RFSYS_REGn_RD(x, n) ^ (v)))
/*@}*/
/*
* Constants & macros for individual RFSYS_REGn bitfields
*/
/*!
* @name Register RFSYS_REGn, field LL[7:0] (RW)
*
* Low lower byte
*/
/*@{*/
#define BP_RFSYS_REGn_LL (0U) /*!< Bit position for RFSYS_REGn_LL. */
#define BM_RFSYS_REGn_LL (0x000000FFU) /*!< Bit mask for RFSYS_REGn_LL. */
#define BS_RFSYS_REGn_LL (8U) /*!< Bit field size in bits for RFSYS_REGn_LL. */
/*! @brief Read current value of the RFSYS_REGn_LL field. */
#define BR_RFSYS_REGn_LL(x, n) (HW_RFSYS_REGn(x, n).B.LL)
/*! @brief Format value for bitfield RFSYS_REGn_LL. */
#define BF_RFSYS_REGn_LL(v) ((uint32_t)((uint32_t)(v) << BP_RFSYS_REGn_LL) & BM_RFSYS_REGn_LL)
/*! @brief Set the LL field to a new value. */
#define BW_RFSYS_REGn_LL(x, n, v) (HW_RFSYS_REGn_WR(x, n, (HW_RFSYS_REGn_RD(x, n) & ~BM_RFSYS_REGn_LL) | BF_RFSYS_REGn_LL(v)))
/*@}*/
/*!
* @name Register RFSYS_REGn, field LH[15:8] (RW)
*
* Low higher byte
*/
/*@{*/
#define BP_RFSYS_REGn_LH (8U) /*!< Bit position for RFSYS_REGn_LH. */
#define BM_RFSYS_REGn_LH (0x0000FF00U) /*!< Bit mask for RFSYS_REGn_LH. */
#define BS_RFSYS_REGn_LH (8U) /*!< Bit field size in bits for RFSYS_REGn_LH. */
/*! @brief Read current value of the RFSYS_REGn_LH field. */
#define BR_RFSYS_REGn_LH(x, n) (HW_RFSYS_REGn(x, n).B.LH)
/*! @brief Format value for bitfield RFSYS_REGn_LH. */
#define BF_RFSYS_REGn_LH(v) ((uint32_t)((uint32_t)(v) << BP_RFSYS_REGn_LH) & BM_RFSYS_REGn_LH)
/*! @brief Set the LH field to a new value. */
#define BW_RFSYS_REGn_LH(x, n, v) (HW_RFSYS_REGn_WR(x, n, (HW_RFSYS_REGn_RD(x, n) & ~BM_RFSYS_REGn_LH) | BF_RFSYS_REGn_LH(v)))
/*@}*/
/*!
* @name Register RFSYS_REGn, field HL[23:16] (RW)
*
* High lower byte
*/
/*@{*/
#define BP_RFSYS_REGn_HL (16U) /*!< Bit position for RFSYS_REGn_HL. */
#define BM_RFSYS_REGn_HL (0x00FF0000U) /*!< Bit mask for RFSYS_REGn_HL. */
#define BS_RFSYS_REGn_HL (8U) /*!< Bit field size in bits for RFSYS_REGn_HL. */
/*! @brief Read current value of the RFSYS_REGn_HL field. */
#define BR_RFSYS_REGn_HL(x, n) (HW_RFSYS_REGn(x, n).B.HL)
/*! @brief Format value for bitfield RFSYS_REGn_HL. */
#define BF_RFSYS_REGn_HL(v) ((uint32_t)((uint32_t)(v) << BP_RFSYS_REGn_HL) & BM_RFSYS_REGn_HL)
/*! @brief Set the HL field to a new value. */
#define BW_RFSYS_REGn_HL(x, n, v) (HW_RFSYS_REGn_WR(x, n, (HW_RFSYS_REGn_RD(x, n) & ~BM_RFSYS_REGn_HL) | BF_RFSYS_REGn_HL(v)))
/*@}*/
/*!
* @name Register RFSYS_REGn, field HH[31:24] (RW)
*
* High higher byte
*/
/*@{*/
#define BP_RFSYS_REGn_HH (24U) /*!< Bit position for RFSYS_REGn_HH. */
#define BM_RFSYS_REGn_HH (0xFF000000U) /*!< Bit mask for RFSYS_REGn_HH. */
#define BS_RFSYS_REGn_HH (8U) /*!< Bit field size in bits for RFSYS_REGn_HH. */
/*! @brief Read current value of the RFSYS_REGn_HH field. */
#define BR_RFSYS_REGn_HH(x, n) (HW_RFSYS_REGn(x, n).B.HH)
/*! @brief Format value for bitfield RFSYS_REGn_HH. */
#define BF_RFSYS_REGn_HH(v) ((uint32_t)((uint32_t)(v) << BP_RFSYS_REGn_HH) & BM_RFSYS_REGn_HH)
/*! @brief Set the HH field to a new value. */
#define BW_RFSYS_REGn_HH(x, n, v) (HW_RFSYS_REGn_WR(x, n, (HW_RFSYS_REGn_RD(x, n) & ~BM_RFSYS_REGn_HH) | BF_RFSYS_REGn_HH(v)))
/*@}*/
/*******************************************************************************
* hw_rfsys_t - module struct
******************************************************************************/
/*!
* @brief All RFSYS module registers.
*/
#pragma pack(1)
typedef struct _hw_rfsys
{
__IO hw_rfsys_regn_t REGn[8]; /*!< [0x0] Register file register */
} hw_rfsys_t;
#pragma pack()
/*! @brief Macro to access all RFSYS registers. */
/*! @param x RFSYS module instance base address. */
/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
* use the '&' operator, like <code>&HW_RFSYS(RFSYS_BASE)</code>. */
#define HW_RFSYS(x) (*(hw_rfsys_t *)(x))
#endif /* __HW_RFSYS_REGISTERS_H__ */
/* EOF */

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/*
** ###################################################################
** Compilers: Keil ARM C/C++ Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
** Version: rev. 2.5, 2014-05-06
** Build: b140604
**
** Abstract:
** Extension to the CMSIS register access layer header.
**
** Copyright (c) 2014 Freescale Semiconductor, Inc.
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** Revisions:
** - rev. 1.0 (2013-07-23)
** Initial version.
** - rev. 1.1 (2013-09-17)
** RM rev. 0.4 update.
** - rev. 2.0 (2013-10-29)
** Register accessor macros added to the memory map.
** Symbols for Processor Expert memory map compatibility added to the memory map.
** Startup file for gcc has been updated according to CMSIS 3.2.
** System initialization updated.
** - rev. 2.1 (2013-10-30)
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
** - rev. 2.2 (2013-12-20)
** Update according to reference manual rev. 0.6,
** - rev. 2.3 (2014-01-13)
** Update according to reference manual rev. 0.61,
** - rev. 2.4 (2014-02-10)
** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
** - rev. 2.5 (2014-05-06)
** Update according to reference manual rev. 1.0,
** Update of system and startup files.
** Module access macro module_BASES replaced by module_BASE_PTRS.
**
** ###################################################################
*/
/*
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
*
* This file was generated automatically and any changes may be lost.
*/
#ifndef __HW_RFVBAT_REGISTERS_H__
#define __HW_RFVBAT_REGISTERS_H__
#include "MK22F51212.h"
#include "fsl_bitaccess.h"
/*
* MK22F51212 RFVBAT
*
* VBAT register file
*
* Registers defined in this header file:
* - HW_RFVBAT_REGn - VBAT register file register
*
* - hw_rfvbat_t - Struct containing all module registers.
*/
#define HW_RFVBAT_INSTANCE_COUNT (1U) /*!< Number of instances of the RFVBAT module. */
/*******************************************************************************
* HW_RFVBAT_REGn - VBAT register file register
******************************************************************************/
/*!
* @brief HW_RFVBAT_REGn - VBAT register file register (RW)
*
* Reset value: 0x00000000U
*
* Each register can be accessed as 8-, 16-, or 32-bits.
*/
typedef union _hw_rfvbat_regn
{
uint32_t U;
struct _hw_rfvbat_regn_bitfields
{
uint32_t LL : 8; /*!< [7:0] */
uint32_t LH : 8; /*!< [15:8] */
uint32_t HL : 8; /*!< [23:16] */
uint32_t HH : 8; /*!< [31:24] */
} B;
} hw_rfvbat_regn_t;
/*!
* @name Constants and macros for entire RFVBAT_REGn register
*/
/*@{*/
#define HW_RFVBAT_REGn_COUNT (8U)
#define HW_RFVBAT_REGn_ADDR(x, n) ((x) + 0x0U + (0x4U * (n)))
#define HW_RFVBAT_REGn(x, n) (*(__IO hw_rfvbat_regn_t *) HW_RFVBAT_REGn_ADDR(x, n))
#define HW_RFVBAT_REGn_RD(x, n) (HW_RFVBAT_REGn(x, n).U)
#define HW_RFVBAT_REGn_WR(x, n, v) (HW_RFVBAT_REGn(x, n).U = (v))
#define HW_RFVBAT_REGn_SET(x, n, v) (HW_RFVBAT_REGn_WR(x, n, HW_RFVBAT_REGn_RD(x, n) | (v)))
#define HW_RFVBAT_REGn_CLR(x, n, v) (HW_RFVBAT_REGn_WR(x, n, HW_RFVBAT_REGn_RD(x, n) & ~(v)))
#define HW_RFVBAT_REGn_TOG(x, n, v) (HW_RFVBAT_REGn_WR(x, n, HW_RFVBAT_REGn_RD(x, n) ^ (v)))
/*@}*/
/*
* Constants & macros for individual RFVBAT_REGn bitfields
*/
/*!
* @name Register RFVBAT_REGn, field LL[7:0] (RW)
*
* Low lower byte
*/
/*@{*/
#define BP_RFVBAT_REGn_LL (0U) /*!< Bit position for RFVBAT_REGn_LL. */
#define BM_RFVBAT_REGn_LL (0x000000FFU) /*!< Bit mask for RFVBAT_REGn_LL. */
#define BS_RFVBAT_REGn_LL (8U) /*!< Bit field size in bits for RFVBAT_REGn_LL. */
/*! @brief Read current value of the RFVBAT_REGn_LL field. */
#define BR_RFVBAT_REGn_LL(x, n) (HW_RFVBAT_REGn(x, n).B.LL)
/*! @brief Format value for bitfield RFVBAT_REGn_LL. */
#define BF_RFVBAT_REGn_LL(v) ((uint32_t)((uint32_t)(v) << BP_RFVBAT_REGn_LL) & BM_RFVBAT_REGn_LL)
/*! @brief Set the LL field to a new value. */
#define BW_RFVBAT_REGn_LL(x, n, v) (HW_RFVBAT_REGn_WR(x, n, (HW_RFVBAT_REGn_RD(x, n) & ~BM_RFVBAT_REGn_LL) | BF_RFVBAT_REGn_LL(v)))
/*@}*/
/*!
* @name Register RFVBAT_REGn, field LH[15:8] (RW)
*
* Low higher byte
*/
/*@{*/
#define BP_RFVBAT_REGn_LH (8U) /*!< Bit position for RFVBAT_REGn_LH. */
#define BM_RFVBAT_REGn_LH (0x0000FF00U) /*!< Bit mask for RFVBAT_REGn_LH. */
#define BS_RFVBAT_REGn_LH (8U) /*!< Bit field size in bits for RFVBAT_REGn_LH. */
/*! @brief Read current value of the RFVBAT_REGn_LH field. */
#define BR_RFVBAT_REGn_LH(x, n) (HW_RFVBAT_REGn(x, n).B.LH)
/*! @brief Format value for bitfield RFVBAT_REGn_LH. */
#define BF_RFVBAT_REGn_LH(v) ((uint32_t)((uint32_t)(v) << BP_RFVBAT_REGn_LH) & BM_RFVBAT_REGn_LH)
/*! @brief Set the LH field to a new value. */
#define BW_RFVBAT_REGn_LH(x, n, v) (HW_RFVBAT_REGn_WR(x, n, (HW_RFVBAT_REGn_RD(x, n) & ~BM_RFVBAT_REGn_LH) | BF_RFVBAT_REGn_LH(v)))
/*@}*/
/*!
* @name Register RFVBAT_REGn, field HL[23:16] (RW)
*
* High lower byte
*/
/*@{*/
#define BP_RFVBAT_REGn_HL (16U) /*!< Bit position for RFVBAT_REGn_HL. */
#define BM_RFVBAT_REGn_HL (0x00FF0000U) /*!< Bit mask for RFVBAT_REGn_HL. */
#define BS_RFVBAT_REGn_HL (8U) /*!< Bit field size in bits for RFVBAT_REGn_HL. */
/*! @brief Read current value of the RFVBAT_REGn_HL field. */
#define BR_RFVBAT_REGn_HL(x, n) (HW_RFVBAT_REGn(x, n).B.HL)
/*! @brief Format value for bitfield RFVBAT_REGn_HL. */
#define BF_RFVBAT_REGn_HL(v) ((uint32_t)((uint32_t)(v) << BP_RFVBAT_REGn_HL) & BM_RFVBAT_REGn_HL)
/*! @brief Set the HL field to a new value. */
#define BW_RFVBAT_REGn_HL(x, n, v) (HW_RFVBAT_REGn_WR(x, n, (HW_RFVBAT_REGn_RD(x, n) & ~BM_RFVBAT_REGn_HL) | BF_RFVBAT_REGn_HL(v)))
/*@}*/
/*!
* @name Register RFVBAT_REGn, field HH[31:24] (RW)
*
* High higher byte
*/
/*@{*/
#define BP_RFVBAT_REGn_HH (24U) /*!< Bit position for RFVBAT_REGn_HH. */
#define BM_RFVBAT_REGn_HH (0xFF000000U) /*!< Bit mask for RFVBAT_REGn_HH. */
#define BS_RFVBAT_REGn_HH (8U) /*!< Bit field size in bits for RFVBAT_REGn_HH. */
/*! @brief Read current value of the RFVBAT_REGn_HH field. */
#define BR_RFVBAT_REGn_HH(x, n) (HW_RFVBAT_REGn(x, n).B.HH)
/*! @brief Format value for bitfield RFVBAT_REGn_HH. */
#define BF_RFVBAT_REGn_HH(v) ((uint32_t)((uint32_t)(v) << BP_RFVBAT_REGn_HH) & BM_RFVBAT_REGn_HH)
/*! @brief Set the HH field to a new value. */
#define BW_RFVBAT_REGn_HH(x, n, v) (HW_RFVBAT_REGn_WR(x, n, (HW_RFVBAT_REGn_RD(x, n) & ~BM_RFVBAT_REGn_HH) | BF_RFVBAT_REGn_HH(v)))
/*@}*/
/*******************************************************************************
* hw_rfvbat_t - module struct
******************************************************************************/
/*!
* @brief All RFVBAT module registers.
*/
#pragma pack(1)
typedef struct _hw_rfvbat
{
__IO hw_rfvbat_regn_t REGn[8]; /*!< [0x0] VBAT register file register */
} hw_rfvbat_t;
#pragma pack()
/*! @brief Macro to access all RFVBAT registers. */
/*! @param x RFVBAT module instance base address. */
/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
* use the '&' operator, like <code>&HW_RFVBAT(RFVBAT_BASE)</code>. */
#define HW_RFVBAT(x) (*(hw_rfvbat_t *)(x))
#endif /* __HW_RFVBAT_REGISTERS_H__ */
/* EOF */

587
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@ -0,0 +1,587 @@
/*
** ###################################################################
** Compilers: Keil ARM C/C++ Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
** Version: rev. 2.5, 2014-05-06
** Build: b140604
**
** Abstract:
** Extension to the CMSIS register access layer header.
**
** Copyright (c) 2014 Freescale Semiconductor, Inc.
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** Revisions:
** - rev. 1.0 (2013-07-23)
** Initial version.
** - rev. 1.1 (2013-09-17)
** RM rev. 0.4 update.
** - rev. 2.0 (2013-10-29)
** Register accessor macros added to the memory map.
** Symbols for Processor Expert memory map compatibility added to the memory map.
** Startup file for gcc has been updated according to CMSIS 3.2.
** System initialization updated.
** - rev. 2.1 (2013-10-30)
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
** - rev. 2.2 (2013-12-20)
** Update according to reference manual rev. 0.6,
** - rev. 2.3 (2014-01-13)
** Update according to reference manual rev. 0.61,
** - rev. 2.4 (2014-02-10)
** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
** - rev. 2.5 (2014-05-06)
** Update according to reference manual rev. 1.0,
** Update of system and startup files.
** Module access macro module_BASES replaced by module_BASE_PTRS.
**
** ###################################################################
*/
/*
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
*
* This file was generated automatically and any changes may be lost.
*/
#ifndef __HW_RNG_REGISTERS_H__
#define __HW_RNG_REGISTERS_H__
#include "MK22F51212.h"
#include "fsl_bitaccess.h"
/*
* MK22F51212 RNG
*
* Random Number Generator Accelerator
*
* Registers defined in this header file:
* - HW_RNG_CR - RNGA Control Register
* - HW_RNG_SR - RNGA Status Register
* - HW_RNG_ER - RNGA Entropy Register
* - HW_RNG_OR - RNGA Output Register
*
* - hw_rng_t - Struct containing all module registers.
*/
#define HW_RNG_INSTANCE_COUNT (1U) /*!< Number of instances of the RNG module. */
/*******************************************************************************
* HW_RNG_CR - RNGA Control Register
******************************************************************************/
/*!
* @brief HW_RNG_CR - RNGA Control Register (RW)
*
* Reset value: 0x00000000U
*
* Controls the operation of RNGA.
*/
typedef union _hw_rng_cr
{
uint32_t U;
struct _hw_rng_cr_bitfields
{
uint32_t GO : 1; /*!< [0] Go */
uint32_t HA : 1; /*!< [1] High Assurance */
uint32_t INTM : 1; /*!< [2] Interrupt Mask */
uint32_t CLRI : 1; /*!< [3] Clear Interrupt */
uint32_t SLP : 1; /*!< [4] Sleep */
uint32_t RESERVED0 : 27; /*!< [31:5] */
} B;
} hw_rng_cr_t;
/*!
* @name Constants and macros for entire RNG_CR register
*/
/*@{*/
#define HW_RNG_CR_ADDR(x) ((x) + 0x0U)
#define HW_RNG_CR(x) (*(__IO hw_rng_cr_t *) HW_RNG_CR_ADDR(x))
#define HW_RNG_CR_RD(x) (HW_RNG_CR(x).U)
#define HW_RNG_CR_WR(x, v) (HW_RNG_CR(x).U = (v))
#define HW_RNG_CR_SET(x, v) (HW_RNG_CR_WR(x, HW_RNG_CR_RD(x) | (v)))
#define HW_RNG_CR_CLR(x, v) (HW_RNG_CR_WR(x, HW_RNG_CR_RD(x) & ~(v)))
#define HW_RNG_CR_TOG(x, v) (HW_RNG_CR_WR(x, HW_RNG_CR_RD(x) ^ (v)))
/*@}*/
/*
* Constants & macros for individual RNG_CR bitfields
*/
/*!
* @name Register RNG_CR, field GO[0] (RW)
*
* Specifies whether random-data generation and loading (into OR[RANDOUT]) is
* enabled.This field is sticky. You must reset RNGA to stop RNGA from loading
* OR[RANDOUT] with data.
*
* Values:
* - 0 - Disabled
* - 1 - Enabled
*/
/*@{*/
#define BP_RNG_CR_GO (0U) /*!< Bit position for RNG_CR_GO. */
#define BM_RNG_CR_GO (0x00000001U) /*!< Bit mask for RNG_CR_GO. */
#define BS_RNG_CR_GO (1U) /*!< Bit field size in bits for RNG_CR_GO. */
/*! @brief Read current value of the RNG_CR_GO field. */
#define BR_RNG_CR_GO(x) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_GO))
/*! @brief Format value for bitfield RNG_CR_GO. */
#define BF_RNG_CR_GO(v) ((uint32_t)((uint32_t)(v) << BP_RNG_CR_GO) & BM_RNG_CR_GO)
/*! @brief Set the GO field to a new value. */
#define BW_RNG_CR_GO(x, v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_GO) = (v))
/*@}*/
/*!
* @name Register RNG_CR, field HA[1] (RW)
*
* Enables notification of security violations (via SR[SECV]). A security
* violation occurs when you read OR[RANDOUT] and SR[OREG_LVL]=0. This field is sticky.
* After enabling notification of security violations, you must reset RNGA to
* disable them again.
*
* Values:
* - 0 - Disabled
* - 1 - Enabled
*/
/*@{*/
#define BP_RNG_CR_HA (1U) /*!< Bit position for RNG_CR_HA. */
#define BM_RNG_CR_HA (0x00000002U) /*!< Bit mask for RNG_CR_HA. */
#define BS_RNG_CR_HA (1U) /*!< Bit field size in bits for RNG_CR_HA. */
/*! @brief Read current value of the RNG_CR_HA field. */
#define BR_RNG_CR_HA(x) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_HA))
/*! @brief Format value for bitfield RNG_CR_HA. */
#define BF_RNG_CR_HA(v) ((uint32_t)((uint32_t)(v) << BP_RNG_CR_HA) & BM_RNG_CR_HA)
/*! @brief Set the HA field to a new value. */
#define BW_RNG_CR_HA(x, v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_HA) = (v))
/*@}*/
/*!
* @name Register RNG_CR, field INTM[2] (RW)
*
* Masks the triggering of an error interrupt to the interrupt controller when
* an OR underflow condition occurs. An OR underflow condition occurs when you
* read OR[RANDOUT] and SR[OREG_LVL]=0. See the Output Register (OR) description.
*
* Values:
* - 0 - Not masked
* - 1 - Masked
*/
/*@{*/
#define BP_RNG_CR_INTM (2U) /*!< Bit position for RNG_CR_INTM. */
#define BM_RNG_CR_INTM (0x00000004U) /*!< Bit mask for RNG_CR_INTM. */
#define BS_RNG_CR_INTM (1U) /*!< Bit field size in bits for RNG_CR_INTM. */
/*! @brief Read current value of the RNG_CR_INTM field. */
#define BR_RNG_CR_INTM(x) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_INTM))
/*! @brief Format value for bitfield RNG_CR_INTM. */
#define BF_RNG_CR_INTM(v) ((uint32_t)((uint32_t)(v) << BP_RNG_CR_INTM) & BM_RNG_CR_INTM)
/*! @brief Set the INTM field to a new value. */
#define BW_RNG_CR_INTM(x, v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_INTM) = (v))
/*@}*/
/*!
* @name Register RNG_CR, field CLRI[3] (WORZ)
*
* Clears the interrupt by resetting the error-interrupt indicator (SR[ERRI]).
*
* Values:
* - 0 - Do not clear the interrupt.
* - 1 - Clear the interrupt. When you write 1 to this field, RNGA then resets
* the error-interrupt indicator (SR[ERRI]). This bit always reads as 0.
*/
/*@{*/
#define BP_RNG_CR_CLRI (3U) /*!< Bit position for RNG_CR_CLRI. */
#define BM_RNG_CR_CLRI (0x00000008U) /*!< Bit mask for RNG_CR_CLRI. */
#define BS_RNG_CR_CLRI (1U) /*!< Bit field size in bits for RNG_CR_CLRI. */
/*! @brief Format value for bitfield RNG_CR_CLRI. */
#define BF_RNG_CR_CLRI(v) ((uint32_t)((uint32_t)(v) << BP_RNG_CR_CLRI) & BM_RNG_CR_CLRI)
/*! @brief Set the CLRI field to a new value. */
#define BW_RNG_CR_CLRI(x, v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_CLRI) = (v))
/*@}*/
/*!
* @name Register RNG_CR, field SLP[4] (RW)
*
* Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep
* mode by asserting the DOZE signal.
*
* Values:
* - 0 - Normal mode
* - 1 - Sleep (low-power) mode
*/
/*@{*/
#define BP_RNG_CR_SLP (4U) /*!< Bit position for RNG_CR_SLP. */
#define BM_RNG_CR_SLP (0x00000010U) /*!< Bit mask for RNG_CR_SLP. */
#define BS_RNG_CR_SLP (1U) /*!< Bit field size in bits for RNG_CR_SLP. */
/*! @brief Read current value of the RNG_CR_SLP field. */
#define BR_RNG_CR_SLP(x) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_SLP))
/*! @brief Format value for bitfield RNG_CR_SLP. */
#define BF_RNG_CR_SLP(v) ((uint32_t)((uint32_t)(v) << BP_RNG_CR_SLP) & BM_RNG_CR_SLP)
/*! @brief Set the SLP field to a new value. */
#define BW_RNG_CR_SLP(x, v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_SLP) = (v))
/*@}*/
/*******************************************************************************
* HW_RNG_SR - RNGA Status Register
******************************************************************************/
/*!
* @brief HW_RNG_SR - RNGA Status Register (RO)
*
* Reset value: 0x00010000U
*
* Indicates the status of RNGA. This register is read-only.
*/
typedef union _hw_rng_sr
{
uint32_t U;
struct _hw_rng_sr_bitfields
{
uint32_t SECV : 1; /*!< [0] Security Violation */
uint32_t LRS : 1; /*!< [1] Last Read Status */
uint32_t ORU : 1; /*!< [2] Output Register Underflow */
uint32_t ERRI : 1; /*!< [3] Error Interrupt */
uint32_t SLP : 1; /*!< [4] Sleep */
uint32_t RESERVED0 : 3; /*!< [7:5] */
uint32_t OREG_LVL : 8; /*!< [15:8] Output Register Level */
uint32_t OREG_SIZE : 8; /*!< [23:16] Output Register Size */
uint32_t RESERVED1 : 8; /*!< [31:24] */
} B;
} hw_rng_sr_t;
/*!
* @name Constants and macros for entire RNG_SR register
*/
/*@{*/
#define HW_RNG_SR_ADDR(x) ((x) + 0x4U)
#define HW_RNG_SR(x) (*(__I hw_rng_sr_t *) HW_RNG_SR_ADDR(x))
#define HW_RNG_SR_RD(x) (HW_RNG_SR(x).U)
/*@}*/
/*
* Constants & macros for individual RNG_SR bitfields
*/
/*!
* @name Register RNG_SR, field SECV[0] (RO)
*
* Used only when high assurance is enabled (CR[HA]). Indicates that a security
* violation has occurred.This field is sticky. To clear SR[SECV], you must reset
* RNGA.
*
* Values:
* - 0 - No security violation
* - 1 - Security violation
*/
/*@{*/
#define BP_RNG_SR_SECV (0U) /*!< Bit position for RNG_SR_SECV. */
#define BM_RNG_SR_SECV (0x00000001U) /*!< Bit mask for RNG_SR_SECV. */
#define BS_RNG_SR_SECV (1U) /*!< Bit field size in bits for RNG_SR_SECV. */
/*! @brief Read current value of the RNG_SR_SECV field. */
#define BR_RNG_SR_SECV(x) (BITBAND_ACCESS32(HW_RNG_SR_ADDR(x), BP_RNG_SR_SECV))
/*@}*/
/*!
* @name Register RNG_SR, field LRS[1] (RO)
*
* Indicates whether the most recent read of OR[RANDOUT] caused an OR underflow
* condition, regardless of whether the error interrupt is masked (CR[INTM]). An
* OR underflow condition occurs when you read OR[RANDOUT] and SR[OREG_LVL]=0.
* After you read this register, RNGA writes 0 to this field.
*
* Values:
* - 0 - No underflow
* - 1 - Underflow
*/
/*@{*/
#define BP_RNG_SR_LRS (1U) /*!< Bit position for RNG_SR_LRS. */
#define BM_RNG_SR_LRS (0x00000002U) /*!< Bit mask for RNG_SR_LRS. */
#define BS_RNG_SR_LRS (1U) /*!< Bit field size in bits for RNG_SR_LRS. */
/*! @brief Read current value of the RNG_SR_LRS field. */
#define BR_RNG_SR_LRS(x) (BITBAND_ACCESS32(HW_RNG_SR_ADDR(x), BP_RNG_SR_LRS))
/*@}*/
/*!
* @name Register RNG_SR, field ORU[2] (RO)
*
* Indicates whether an OR underflow condition has occurred since you last read
* this register (SR) or RNGA was reset, regardless of whether the error
* interrupt is masked (CR[INTM]). An OR underflow condition occurs when you read
* OR[RANDOUT] and SR[OREG_LVL]=0. After you read this register, RNGA writes 0 to this
* field.
*
* Values:
* - 0 - No underflow
* - 1 - Underflow
*/
/*@{*/
#define BP_RNG_SR_ORU (2U) /*!< Bit position for RNG_SR_ORU. */
#define BM_RNG_SR_ORU (0x00000004U) /*!< Bit mask for RNG_SR_ORU. */
#define BS_RNG_SR_ORU (1U) /*!< Bit field size in bits for RNG_SR_ORU. */
/*! @brief Read current value of the RNG_SR_ORU field. */
#define BR_RNG_SR_ORU(x) (BITBAND_ACCESS32(HW_RNG_SR_ADDR(x), BP_RNG_SR_ORU))
/*@}*/
/*!
* @name Register RNG_SR, field ERRI[3] (RO)
*
* Indicates whether an OR underflow condition has occurred since you last
* cleared the error interrupt (CR[CLRI]) or RNGA was reset, regardless of whether the
* error interrupt is masked (CR[INTM]). An OR underflow condition occurs when
* you read OR[RANDOUT] and SR[OREG_LVL]=0. After you reset the error-interrupt
* indicator (via CR[CLRI]), RNGA writes 0 to this field.
*
* Values:
* - 0 - No underflow
* - 1 - Underflow
*/
/*@{*/
#define BP_RNG_SR_ERRI (3U) /*!< Bit position for RNG_SR_ERRI. */
#define BM_RNG_SR_ERRI (0x00000008U) /*!< Bit mask for RNG_SR_ERRI. */
#define BS_RNG_SR_ERRI (1U) /*!< Bit field size in bits for RNG_SR_ERRI. */
/*! @brief Read current value of the RNG_SR_ERRI field. */
#define BR_RNG_SR_ERRI(x) (BITBAND_ACCESS32(HW_RNG_SR_ADDR(x), BP_RNG_SR_ERRI))
/*@}*/
/*!
* @name Register RNG_SR, field SLP[4] (RO)
*
* Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep
* mode by asserting the DOZE signal.
*
* Values:
* - 0 - Normal mode
* - 1 - Sleep (low-power) mode
*/
/*@{*/
#define BP_RNG_SR_SLP (4U) /*!< Bit position for RNG_SR_SLP. */
#define BM_RNG_SR_SLP (0x00000010U) /*!< Bit mask for RNG_SR_SLP. */
#define BS_RNG_SR_SLP (1U) /*!< Bit field size in bits for RNG_SR_SLP. */
/*! @brief Read current value of the RNG_SR_SLP field. */
#define BR_RNG_SR_SLP(x) (BITBAND_ACCESS32(HW_RNG_SR_ADDR(x), BP_RNG_SR_SLP))
/*@}*/
/*!
* @name Register RNG_SR, field OREG_LVL[15:8] (RO)
*
* Indicates the number of random-data words that are in OR[RANDOUT], which
* indicates whether OR[RANDOUT] is valid.If you read OR[RANDOUT] when SR[OREG_LVL]
* is not 0, then the contents of a random number contained in OR[RANDOUT] are
* returned, and RNGA writes 0 to both OR[RANDOUT] and SR[OREG_LVL].
*
* Values:
* - 0 - No words (empty)
* - 1 - One word (valid)
*/
/*@{*/
#define BP_RNG_SR_OREG_LVL (8U) /*!< Bit position for RNG_SR_OREG_LVL. */
#define BM_RNG_SR_OREG_LVL (0x0000FF00U) /*!< Bit mask for RNG_SR_OREG_LVL. */
#define BS_RNG_SR_OREG_LVL (8U) /*!< Bit field size in bits for RNG_SR_OREG_LVL. */
/*! @brief Read current value of the RNG_SR_OREG_LVL field. */
#define BR_RNG_SR_OREG_LVL(x) (HW_RNG_SR(x).B.OREG_LVL)
/*@}*/
/*!
* @name Register RNG_SR, field OREG_SIZE[23:16] (RO)
*
* Indicates the size of the Output (OR) register in terms of the number of
* 32-bit random-data words it can hold.
*
* Values:
* - 1 - One word (this value is fixed)
*/
/*@{*/
#define BP_RNG_SR_OREG_SIZE (16U) /*!< Bit position for RNG_SR_OREG_SIZE. */
#define BM_RNG_SR_OREG_SIZE (0x00FF0000U) /*!< Bit mask for RNG_SR_OREG_SIZE. */
#define BS_RNG_SR_OREG_SIZE (8U) /*!< Bit field size in bits for RNG_SR_OREG_SIZE. */
/*! @brief Read current value of the RNG_SR_OREG_SIZE field. */
#define BR_RNG_SR_OREG_SIZE(x) (HW_RNG_SR(x).B.OREG_SIZE)
/*@}*/
/*******************************************************************************
* HW_RNG_ER - RNGA Entropy Register
******************************************************************************/
/*!
* @brief HW_RNG_ER - RNGA Entropy Register (WORZ)
*
* Reset value: 0x00000000U
*
* Specifies an entropy value that RNGA uses in addition to its ring oscillators
* to seed its pseudorandom algorithm. This is a write-only register; reads
* return all zeros.
*/
typedef union _hw_rng_er
{
uint32_t U;
struct _hw_rng_er_bitfields
{
uint32_t EXT_ENT : 32; /*!< [31:0] External Entropy */
} B;
} hw_rng_er_t;
/*!
* @name Constants and macros for entire RNG_ER register
*/
/*@{*/
#define HW_RNG_ER_ADDR(x) ((x) + 0x8U)
#define HW_RNG_ER(x) (*(__O hw_rng_er_t *) HW_RNG_ER_ADDR(x))
#define HW_RNG_ER_RD(x) (HW_RNG_ER(x).U)
#define HW_RNG_ER_WR(x, v) (HW_RNG_ER(x).U = (v))
/*@}*/
/*
* Constants & macros for individual RNG_ER bitfields
*/
/*!
* @name Register RNG_ER, field EXT_ENT[31:0] (WORZ)
*
* Specifies an entropy value that RNGA uses in addition to its ring oscillators
* to seed its pseudorandom algorithm.Specifying a value for this field is
* optional but recommended. You can write to this field at any time during operation.
*/
/*@{*/
#define BP_RNG_ER_EXT_ENT (0U) /*!< Bit position for RNG_ER_EXT_ENT. */
#define BM_RNG_ER_EXT_ENT (0xFFFFFFFFU) /*!< Bit mask for RNG_ER_EXT_ENT. */
#define BS_RNG_ER_EXT_ENT (32U) /*!< Bit field size in bits for RNG_ER_EXT_ENT. */
/*! @brief Format value for bitfield RNG_ER_EXT_ENT. */
#define BF_RNG_ER_EXT_ENT(v) ((uint32_t)((uint32_t)(v) << BP_RNG_ER_EXT_ENT) & BM_RNG_ER_EXT_ENT)
/*! @brief Set the EXT_ENT field to a new value. */
#define BW_RNG_ER_EXT_ENT(x, v) (HW_RNG_ER_WR(x, v))
/*@}*/
/*******************************************************************************
* HW_RNG_OR - RNGA Output Register
******************************************************************************/
/*!
* @brief HW_RNG_OR - RNGA Output Register (RO)
*
* Reset value: 0x00000000U
*
* Stores a random-data word generated by RNGA.
*/
typedef union _hw_rng_or
{
uint32_t U;
struct _hw_rng_or_bitfields
{
uint32_t RANDOUT : 32; /*!< [31:0] Random Output */
} B;
} hw_rng_or_t;
/*!
* @name Constants and macros for entire RNG_OR register
*/
/*@{*/
#define HW_RNG_OR_ADDR(x) ((x) + 0xCU)
#define HW_RNG_OR(x) (*(__I hw_rng_or_t *) HW_RNG_OR_ADDR(x))
#define HW_RNG_OR_RD(x) (HW_RNG_OR(x).U)
/*@}*/
/*
* Constants & macros for individual RNG_OR bitfields
*/
/*!
* @name Register RNG_OR, field RANDOUT[31:0] (RO)
*
* Stores a random-data word generated by RNGA. This is a read-only field.Before
* reading RANDOUT, be sure it is valid (SR[OREG_LVL]=1).
*
* Values:
* - 0 - Invalid data (if you read this field when it is 0 and SR[OREG_LVL] is
* 0, RNGA then writes 1 to SR[ERRI], SR[ORU], and SR[LRS]; when the error
* interrupt is not masked (CR[INTM]=0), RNGA also asserts an error interrupt
* request to the interrupt controller).
*/
/*@{*/
#define BP_RNG_OR_RANDOUT (0U) /*!< Bit position for RNG_OR_RANDOUT. */
#define BM_RNG_OR_RANDOUT (0xFFFFFFFFU) /*!< Bit mask for RNG_OR_RANDOUT. */
#define BS_RNG_OR_RANDOUT (32U) /*!< Bit field size in bits for RNG_OR_RANDOUT. */
/*! @brief Read current value of the RNG_OR_RANDOUT field. */
#define BR_RNG_OR_RANDOUT(x) (HW_RNG_OR(x).U)
/*@}*/
/*******************************************************************************
* hw_rng_t - module struct
******************************************************************************/
/*!
* @brief All RNG module registers.
*/
#pragma pack(1)
typedef struct _hw_rng
{
__IO hw_rng_cr_t CR; /*!< [0x0] RNGA Control Register */
__I hw_rng_sr_t SR; /*!< [0x4] RNGA Status Register */
__O hw_rng_er_t ER; /*!< [0x8] RNGA Entropy Register */
__I hw_rng_or_t OR; /*!< [0xC] RNGA Output Register */
} hw_rng_t;
#pragma pack()
/*! @brief Macro to access all RNG registers. */
/*! @param x RNG module instance base address. */
/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
* use the '&' operator, like <code>&HW_RNG(RNG_BASE)</code>. */
#define HW_RNG(x) (*(hw_rng_t *)(x))
#endif /* __HW_RNG_REGISTERS_H__ */
/* EOF */

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/*
** ###################################################################
** Compilers: Keil ARM C/C++ Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
** Version: rev. 2.5, 2014-05-06
** Build: b140604
**
** Abstract:
** Extension to the CMSIS register access layer header.
**
** Copyright (c) 2014 Freescale Semiconductor, Inc.
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** Revisions:
** - rev. 1.0 (2013-07-23)
** Initial version.
** - rev. 1.1 (2013-09-17)
** RM rev. 0.4 update.
** - rev. 2.0 (2013-10-29)
** Register accessor macros added to the memory map.
** Symbols for Processor Expert memory map compatibility added to the memory map.
** Startup file for gcc has been updated according to CMSIS 3.2.
** System initialization updated.
** - rev. 2.1 (2013-10-30)
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
** - rev. 2.2 (2013-12-20)
** Update according to reference manual rev. 0.6,
** - rev. 2.3 (2014-01-13)
** Update according to reference manual rev. 0.61,
** - rev. 2.4 (2014-02-10)
** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
** - rev. 2.5 (2014-05-06)
** Update according to reference manual rev. 1.0,
** Update of system and startup files.
** Module access macro module_BASES replaced by module_BASE_PTRS.
**
** ###################################################################
*/
/*
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
*
* This file was generated automatically and any changes may be lost.
*/
#ifndef __HW_SMC_REGISTERS_H__
#define __HW_SMC_REGISTERS_H__
#include "MK22F51212.h"
#include "fsl_bitaccess.h"
/*
* MK22F51212 SMC
*
* System Mode Controller
*
* Registers defined in this header file:
* - HW_SMC_PMPROT - Power Mode Protection register
* - HW_SMC_PMCTRL - Power Mode Control register
* - HW_SMC_STOPCTRL - Stop Control Register
* - HW_SMC_PMSTAT - Power Mode Status register
*
* - hw_smc_t - Struct containing all module registers.
*/
#define HW_SMC_INSTANCE_COUNT (1U) /*!< Number of instances of the SMC module. */
/*******************************************************************************
* HW_SMC_PMPROT - Power Mode Protection register
******************************************************************************/
/*!
* @brief HW_SMC_PMPROT - Power Mode Protection register (RW)
*
* Reset value: 0x00U
*
* This register provides protection for entry into any low-power run or stop
* mode. The enabling of the low-power run or stop mode occurs by configuring the
* Power Mode Control register (PMCTRL). The PMPROT register can be written only
* once after any system reset. If the MCU is configured for a disallowed or
* reserved power mode, the MCU remains in its current power mode. For example, if the
* MCU is in normal RUN mode and AVLP is 0, an attempt to enter VLPR mode using
* PMCTRL[RUNM] is blocked and PMCTRL[RUNM] remains 00b, indicating the MCU is
* still in Normal Run mode. This register is reset on Chip Reset not VLLS and by
* reset types that trigger Chip Reset not VLLS. It is unaffected by reset types
* that do not trigger Chip Reset not VLLS. See the Reset section details for more
* information.
*/
typedef union _hw_smc_pmprot
{
uint8_t U;
struct _hw_smc_pmprot_bitfields
{
uint8_t RESERVED0 : 1; /*!< [0] */
uint8_t AVLLS : 1; /*!< [1] Allow Very-Low-Leakage Stop Mode */
uint8_t RESERVED1 : 1; /*!< [2] */
uint8_t ALLS : 1; /*!< [3] Allow Low-Leakage Stop Mode */
uint8_t RESERVED2 : 1; /*!< [4] */
uint8_t AVLP : 1; /*!< [5] Allow Very-Low-Power Modes */
uint8_t RESERVED3 : 1; /*!< [6] */
uint8_t AHSRUN : 1; /*!< [7] Allow High Speed Run mode */
} B;
} hw_smc_pmprot_t;
/*!
* @name Constants and macros for entire SMC_PMPROT register
*/
/*@{*/
#define HW_SMC_PMPROT_ADDR(x) ((x) + 0x0U)
#define HW_SMC_PMPROT(x) (*(__IO hw_smc_pmprot_t *) HW_SMC_PMPROT_ADDR(x))
#define HW_SMC_PMPROT_RD(x) (HW_SMC_PMPROT(x).U)
#define HW_SMC_PMPROT_WR(x, v) (HW_SMC_PMPROT(x).U = (v))
#define HW_SMC_PMPROT_SET(x, v) (HW_SMC_PMPROT_WR(x, HW_SMC_PMPROT_RD(x) | (v)))
#define HW_SMC_PMPROT_CLR(x, v) (HW_SMC_PMPROT_WR(x, HW_SMC_PMPROT_RD(x) & ~(v)))
#define HW_SMC_PMPROT_TOG(x, v) (HW_SMC_PMPROT_WR(x, HW_SMC_PMPROT_RD(x) ^ (v)))
/*@}*/
/*
* Constants & macros for individual SMC_PMPROT bitfields
*/
/*!
* @name Register SMC_PMPROT, field AVLLS[1] (RW)
*
* Provided the appropriate control bits are set up in PMCTRL, this write once
* bit allows the MCU to enter any very-low-leakage stop mode (VLLSx).
*
* Values:
* - 0 - Any VLLSx mode is not allowed
* - 1 - Any VLLSx mode is allowed
*/
/*@{*/
#define BP_SMC_PMPROT_AVLLS (1U) /*!< Bit position for SMC_PMPROT_AVLLS. */
#define BM_SMC_PMPROT_AVLLS (0x02U) /*!< Bit mask for SMC_PMPROT_AVLLS. */
#define BS_SMC_PMPROT_AVLLS (1U) /*!< Bit field size in bits for SMC_PMPROT_AVLLS. */
/*! @brief Read current value of the SMC_PMPROT_AVLLS field. */
#define BR_SMC_PMPROT_AVLLS(x) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_AVLLS))
/*! @brief Format value for bitfield SMC_PMPROT_AVLLS. */
#define BF_SMC_PMPROT_AVLLS(v) ((uint8_t)((uint8_t)(v) << BP_SMC_PMPROT_AVLLS) & BM_SMC_PMPROT_AVLLS)
/*! @brief Set the AVLLS field to a new value. */
#define BW_SMC_PMPROT_AVLLS(x, v) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_AVLLS) = (v))
/*@}*/
/*!
* @name Register SMC_PMPROT, field ALLS[3] (RW)
*
* Provided the appropriate control bits are set up in PMCTRL, this write-once
* field allows the MCU to enter any low-leakage stop mode (LLS).
*
* Values:
* - 0 - Any LLSx mode is not allowed
* - 1 - Any LLSx mode is allowed
*/
/*@{*/
#define BP_SMC_PMPROT_ALLS (3U) /*!< Bit position for SMC_PMPROT_ALLS. */
#define BM_SMC_PMPROT_ALLS (0x08U) /*!< Bit mask for SMC_PMPROT_ALLS. */
#define BS_SMC_PMPROT_ALLS (1U) /*!< Bit field size in bits for SMC_PMPROT_ALLS. */
/*! @brief Read current value of the SMC_PMPROT_ALLS field. */
#define BR_SMC_PMPROT_ALLS(x) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_ALLS))
/*! @brief Format value for bitfield SMC_PMPROT_ALLS. */
#define BF_SMC_PMPROT_ALLS(v) ((uint8_t)((uint8_t)(v) << BP_SMC_PMPROT_ALLS) & BM_SMC_PMPROT_ALLS)
/*! @brief Set the ALLS field to a new value. */
#define BW_SMC_PMPROT_ALLS(x, v) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_ALLS) = (v))
/*@}*/
/*!
* @name Register SMC_PMPROT, field AVLP[5] (RW)
*
* Provided the appropriate control bits are set up in PMCTRL, this write-once
* field allows the MCU to enter any very-low-power mode (VLPR, VLPW, and VLPS).
*
* Values:
* - 0 - VLPR, VLPW, and VLPS are not allowed.
* - 1 - VLPR, VLPW, and VLPS are allowed.
*/
/*@{*/
#define BP_SMC_PMPROT_AVLP (5U) /*!< Bit position for SMC_PMPROT_AVLP. */
#define BM_SMC_PMPROT_AVLP (0x20U) /*!< Bit mask for SMC_PMPROT_AVLP. */
#define BS_SMC_PMPROT_AVLP (1U) /*!< Bit field size in bits for SMC_PMPROT_AVLP. */
/*! @brief Read current value of the SMC_PMPROT_AVLP field. */
#define BR_SMC_PMPROT_AVLP(x) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_AVLP))
/*! @brief Format value for bitfield SMC_PMPROT_AVLP. */
#define BF_SMC_PMPROT_AVLP(v) ((uint8_t)((uint8_t)(v) << BP_SMC_PMPROT_AVLP) & BM_SMC_PMPROT_AVLP)
/*! @brief Set the AVLP field to a new value. */
#define BW_SMC_PMPROT_AVLP(x, v) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_AVLP) = (v))
/*@}*/
/*!
* @name Register SMC_PMPROT, field AHSRUN[7] (RW)
*
* Provided the appropriate control bits are set up in PMCTRL, this write-once
* field allows the MCU to enter High Speed Run mode (HSRUN).
*
* Values:
* - 0 - HSRUN is not allowed
* - 1 - HSRUN is allowed
*/
/*@{*/
#define BP_SMC_PMPROT_AHSRUN (7U) /*!< Bit position for SMC_PMPROT_AHSRUN. */
#define BM_SMC_PMPROT_AHSRUN (0x80U) /*!< Bit mask for SMC_PMPROT_AHSRUN. */
#define BS_SMC_PMPROT_AHSRUN (1U) /*!< Bit field size in bits for SMC_PMPROT_AHSRUN. */
/*! @brief Read current value of the SMC_PMPROT_AHSRUN field. */
#define BR_SMC_PMPROT_AHSRUN(x) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_AHSRUN))
/*! @brief Format value for bitfield SMC_PMPROT_AHSRUN. */
#define BF_SMC_PMPROT_AHSRUN(v) ((uint8_t)((uint8_t)(v) << BP_SMC_PMPROT_AHSRUN) & BM_SMC_PMPROT_AHSRUN)
/*! @brief Set the AHSRUN field to a new value. */
#define BW_SMC_PMPROT_AHSRUN(x, v) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_AHSRUN) = (v))
/*@}*/
/*******************************************************************************
* HW_SMC_PMCTRL - Power Mode Control register
******************************************************************************/
/*!
* @brief HW_SMC_PMCTRL - Power Mode Control register (RW)
*
* Reset value: 0x00U
*
* The PMCTRL register controls entry into low-power Run and Stop modes,
* provided that the selected power mode is allowed via an appropriate setting of the
* protection (PMPROT) register. This register is reset on Chip POR not VLLS and by
* reset types that trigger Chip POR not VLLS. It is unaffected by reset types
* that do not trigger Chip POR not VLLS. See the Reset section details for more
* information.
*/
typedef union _hw_smc_pmctrl
{
uint8_t U;
struct _hw_smc_pmctrl_bitfields
{
uint8_t STOPM : 3; /*!< [2:0] Stop Mode Control */
uint8_t STOPA : 1; /*!< [3] Stop Aborted */
uint8_t RESERVED0 : 1; /*!< [4] */
uint8_t RUNM : 2; /*!< [6:5] Run Mode Control */
uint8_t RESERVED1 : 1; /*!< [7] */
} B;
} hw_smc_pmctrl_t;
/*!
* @name Constants and macros for entire SMC_PMCTRL register
*/
/*@{*/
#define HW_SMC_PMCTRL_ADDR(x) ((x) + 0x1U)
#define HW_SMC_PMCTRL(x) (*(__IO hw_smc_pmctrl_t *) HW_SMC_PMCTRL_ADDR(x))
#define HW_SMC_PMCTRL_RD(x) (HW_SMC_PMCTRL(x).U)
#define HW_SMC_PMCTRL_WR(x, v) (HW_SMC_PMCTRL(x).U = (v))
#define HW_SMC_PMCTRL_SET(x, v) (HW_SMC_PMCTRL_WR(x, HW_SMC_PMCTRL_RD(x) | (v)))
#define HW_SMC_PMCTRL_CLR(x, v) (HW_SMC_PMCTRL_WR(x, HW_SMC_PMCTRL_RD(x) & ~(v)))
#define HW_SMC_PMCTRL_TOG(x, v) (HW_SMC_PMCTRL_WR(x, HW_SMC_PMCTRL_RD(x) ^ (v)))
/*@}*/
/*
* Constants & macros for individual SMC_PMCTRL bitfields
*/
/*!
* @name Register SMC_PMCTRL, field STOPM[2:0] (RW)
*
* When written, controls entry into the selected stop mode when Sleep-Now or
* Sleep-On-Exit mode is entered with SLEEPDEEP=1 . Writes to this field are
* blocked if the protection level has not been enabled using the PMPROT register.
* After any system reset, this field is cleared by hardware on any successful write
* to the PMPROT register. When set to VLLSxor LLSx, the LLSM in the STOPCTRL
* register is used to further select the particular VLLSor LLS submode which will
* be entered. When set to STOP, the PSTOPO bits in the STOPCTRL register can be
* used to select a Partial Stop mode if desired.
*
* Values:
* - 000 - Normal Stop (STOP)
* - 001 - Reserved
* - 010 - Very-Low-Power Stop (VLPS)
* - 011 - Low-Leakage Stop (LLSx)
* - 100 - Very-Low-Leakage Stop (VLLSx)
* - 101 - Reserved
* - 110 - Reseved
* - 111 - Reserved
*/
/*@{*/
#define BP_SMC_PMCTRL_STOPM (0U) /*!< Bit position for SMC_PMCTRL_STOPM. */
#define BM_SMC_PMCTRL_STOPM (0x07U) /*!< Bit mask for SMC_PMCTRL_STOPM. */
#define BS_SMC_PMCTRL_STOPM (3U) /*!< Bit field size in bits for SMC_PMCTRL_STOPM. */
/*! @brief Read current value of the SMC_PMCTRL_STOPM field. */
#define BR_SMC_PMCTRL_STOPM(x) (HW_SMC_PMCTRL(x).B.STOPM)
/*! @brief Format value for bitfield SMC_PMCTRL_STOPM. */
#define BF_SMC_PMCTRL_STOPM(v) ((uint8_t)((uint8_t)(v) << BP_SMC_PMCTRL_STOPM) & BM_SMC_PMCTRL_STOPM)
/*! @brief Set the STOPM field to a new value. */
#define BW_SMC_PMCTRL_STOPM(x, v) (HW_SMC_PMCTRL_WR(x, (HW_SMC_PMCTRL_RD(x) & ~BM_SMC_PMCTRL_STOPM) | BF_SMC_PMCTRL_STOPM(v)))
/*@}*/
/*!
* @name Register SMC_PMCTRL, field STOPA[3] (RO)
*
* When set, this read-only status bit indicates an interrupt occured during the
* previous stop mode entry sequence, preventing the system from entering that
* mode. This field is cleared by reset or by hardware at the beginning of any
* stop mode entry sequence and is set if the sequence was aborted.
*
* Values:
* - 0 - The previous stop mode entry was successsful.
* - 1 - The previous stop mode entry was aborted.
*/
/*@{*/
#define BP_SMC_PMCTRL_STOPA (3U) /*!< Bit position for SMC_PMCTRL_STOPA. */
#define BM_SMC_PMCTRL_STOPA (0x08U) /*!< Bit mask for SMC_PMCTRL_STOPA. */
#define BS_SMC_PMCTRL_STOPA (1U) /*!< Bit field size in bits for SMC_PMCTRL_STOPA. */
/*! @brief Read current value of the SMC_PMCTRL_STOPA field. */
#define BR_SMC_PMCTRL_STOPA(x) (BITBAND_ACCESS8(HW_SMC_PMCTRL_ADDR(x), BP_SMC_PMCTRL_STOPA))
/*@}*/
/*!
* @name Register SMC_PMCTRL, field RUNM[6:5] (RW)
*
* When written, causes entry into the selected run mode. Writes to this field
* are blocked if the protection level has not been enabled using the PMPROT
* register. RUNM may be set to VLPR only when PMSTAT=RUN. After being written to
* VLPR, RUNM should not be written back to RUN until PMSTAT=VLPR. RUNM may be set to
* HSRUN only when PMSTAT=RUN. After being programmed to HSRUN, RUNM should not
* be programmed back to RUN until PMSTAT=HSRUN. Also, stop mode entry should not
* be attempted while RUNM=HSRUN or PMSTAT=HSRUN.
*
* Values:
* - 00 - Normal Run mode (RUN)
* - 01 - Reserved
* - 10 - Very-Low-Power Run mode (VLPR)
* - 11 - High Speed Run mode (HSRUN)
*/
/*@{*/
#define BP_SMC_PMCTRL_RUNM (5U) /*!< Bit position for SMC_PMCTRL_RUNM. */
#define BM_SMC_PMCTRL_RUNM (0x60U) /*!< Bit mask for SMC_PMCTRL_RUNM. */
#define BS_SMC_PMCTRL_RUNM (2U) /*!< Bit field size in bits for SMC_PMCTRL_RUNM. */
/*! @brief Read current value of the SMC_PMCTRL_RUNM field. */
#define BR_SMC_PMCTRL_RUNM(x) (HW_SMC_PMCTRL(x).B.RUNM)
/*! @brief Format value for bitfield SMC_PMCTRL_RUNM. */
#define BF_SMC_PMCTRL_RUNM(v) ((uint8_t)((uint8_t)(v) << BP_SMC_PMCTRL_RUNM) & BM_SMC_PMCTRL_RUNM)
/*! @brief Set the RUNM field to a new value. */
#define BW_SMC_PMCTRL_RUNM(x, v) (HW_SMC_PMCTRL_WR(x, (HW_SMC_PMCTRL_RD(x) & ~BM_SMC_PMCTRL_RUNM) | BF_SMC_PMCTRL_RUNM(v)))
/*@}*/
/*******************************************************************************
* HW_SMC_STOPCTRL - Stop Control Register
******************************************************************************/
/*!
* @brief HW_SMC_STOPCTRL - Stop Control Register (RW)
*
* Reset value: 0x03U
*
* The STOPCTRL register provides various control bits allowing the user to fine
* tune power consumption during the stop mode selected by the STOPM field. This
* register is reset on Chip POR not VLLS and by reset types that trigger Chip
* POR not VLLS. It is unaffected by reset types that do not trigger Chip POR not
* VLLS. See the Reset section details for more information.
*/
typedef union _hw_smc_stopctrl
{
uint8_t U;
struct _hw_smc_stopctrl_bitfields
{
uint8_t LLSM : 3; /*!< [2:0] LLS or VLLS Mode Control */
uint8_t RESERVED0 : 2; /*!< [4:3] */
uint8_t PORPO : 1; /*!< [5] POR Power Option */
uint8_t PSTOPO : 2; /*!< [7:6] Partial Stop Option */
} B;
} hw_smc_stopctrl_t;
/*!
* @name Constants and macros for entire SMC_STOPCTRL register
*/
/*@{*/
#define HW_SMC_STOPCTRL_ADDR(x) ((x) + 0x2U)
#define HW_SMC_STOPCTRL(x) (*(__IO hw_smc_stopctrl_t *) HW_SMC_STOPCTRL_ADDR(x))
#define HW_SMC_STOPCTRL_RD(x) (HW_SMC_STOPCTRL(x).U)
#define HW_SMC_STOPCTRL_WR(x, v) (HW_SMC_STOPCTRL(x).U = (v))
#define HW_SMC_STOPCTRL_SET(x, v) (HW_SMC_STOPCTRL_WR(x, HW_SMC_STOPCTRL_RD(x) | (v)))
#define HW_SMC_STOPCTRL_CLR(x, v) (HW_SMC_STOPCTRL_WR(x, HW_SMC_STOPCTRL_RD(x) & ~(v)))
#define HW_SMC_STOPCTRL_TOG(x, v) (HW_SMC_STOPCTRL_WR(x, HW_SMC_STOPCTRL_RD(x) ^ (v)))
/*@}*/
/*
* Constants & macros for individual SMC_STOPCTRL bitfields
*/
/*!
* @name Register SMC_STOPCTRL, field LLSM[2:0] (RW)
*
* This field controls which LLS or VLLS sub-mode to enter if STOPM=LLSx or
* VLLSx.
*
* Values:
* - 000 - VLLS0 if PMCTRL[STOPM]=VLLSx, LLS2 if PMCTRL[STOPM]=LLSx
* - 001 - VLLS1 if PMCTRL[STOPM]=VLLSx, LLS2 if PMCTRL[STOPM]=LLSx
* - 010 - VLLS2 if PMCTRL[STOPM]=VLLSx, LLS2 if PMCTRL[STOPM]=LLSx
* - 011 - VLLS3 if PMCTRL[STOPM]=VLLSx, LLS3 if PMCTRL[STOPM]=LLSx
* - 100 - Reserved
* - 101 - Reserved
* - 110 - Reserved
* - 111 - Reserved
*/
/*@{*/
#define BP_SMC_STOPCTRL_LLSM (0U) /*!< Bit position for SMC_STOPCTRL_LLSM. */
#define BM_SMC_STOPCTRL_LLSM (0x07U) /*!< Bit mask for SMC_STOPCTRL_LLSM. */
#define BS_SMC_STOPCTRL_LLSM (3U) /*!< Bit field size in bits for SMC_STOPCTRL_LLSM. */
/*! @brief Read current value of the SMC_STOPCTRL_LLSM field. */
#define BR_SMC_STOPCTRL_LLSM(x) (HW_SMC_STOPCTRL(x).B.LLSM)
/*! @brief Format value for bitfield SMC_STOPCTRL_LLSM. */
#define BF_SMC_STOPCTRL_LLSM(v) ((uint8_t)((uint8_t)(v) << BP_SMC_STOPCTRL_LLSM) & BM_SMC_STOPCTRL_LLSM)
/*! @brief Set the LLSM field to a new value. */
#define BW_SMC_STOPCTRL_LLSM(x, v) (HW_SMC_STOPCTRL_WR(x, (HW_SMC_STOPCTRL_RD(x) & ~BM_SMC_STOPCTRL_LLSM) | BF_SMC_STOPCTRL_LLSM(v)))
/*@}*/
/*!
* @name Register SMC_STOPCTRL, field PORPO[5] (RW)
*
* This bit controls whether the POR detect circuit is enabled in VLLS0 mode.
*
* Values:
* - 0 - POR detect circuit is enabled in VLLS0
* - 1 - POR detect circuit is disabled in VLLS0
*/
/*@{*/
#define BP_SMC_STOPCTRL_PORPO (5U) /*!< Bit position for SMC_STOPCTRL_PORPO. */
#define BM_SMC_STOPCTRL_PORPO (0x20U) /*!< Bit mask for SMC_STOPCTRL_PORPO. */
#define BS_SMC_STOPCTRL_PORPO (1U) /*!< Bit field size in bits for SMC_STOPCTRL_PORPO. */
/*! @brief Read current value of the SMC_STOPCTRL_PORPO field. */
#define BR_SMC_STOPCTRL_PORPO(x) (BITBAND_ACCESS8(HW_SMC_STOPCTRL_ADDR(x), BP_SMC_STOPCTRL_PORPO))
/*! @brief Format value for bitfield SMC_STOPCTRL_PORPO. */
#define BF_SMC_STOPCTRL_PORPO(v) ((uint8_t)((uint8_t)(v) << BP_SMC_STOPCTRL_PORPO) & BM_SMC_STOPCTRL_PORPO)
/*! @brief Set the PORPO field to a new value. */
#define BW_SMC_STOPCTRL_PORPO(x, v) (BITBAND_ACCESS8(HW_SMC_STOPCTRL_ADDR(x), BP_SMC_STOPCTRL_PORPO) = (v))
/*@}*/
/*!
* @name Register SMC_STOPCTRL, field PSTOPO[7:6] (RW)
*
* These bits control whether a Partial Stop mode is entered when STOPM=STOP.
* When entering a Partial Stop mode from RUN mode, the PMC, MCG and flash remain
* fully powered, allowing the device to wakeup almost instantaneously at the
* expense of higher power consumption. In PSTOP2, only system clocks are gated
* allowing peripherals running on bus clock to remain fully functional. In PSTOP1,
* both system and bus clocks are gated.
*
* Values:
* - 00 - STOP - Normal Stop mode
* - 01 - PSTOP1 - Partial Stop with both system and bus clocks disabled
* - 10 - PSTOP2 - Partial Stop with system clock disabled and bus clock enabled
* - 11 - Reserved
*/
/*@{*/
#define BP_SMC_STOPCTRL_PSTOPO (6U) /*!< Bit position for SMC_STOPCTRL_PSTOPO. */
#define BM_SMC_STOPCTRL_PSTOPO (0xC0U) /*!< Bit mask for SMC_STOPCTRL_PSTOPO. */
#define BS_SMC_STOPCTRL_PSTOPO (2U) /*!< Bit field size in bits for SMC_STOPCTRL_PSTOPO. */
/*! @brief Read current value of the SMC_STOPCTRL_PSTOPO field. */
#define BR_SMC_STOPCTRL_PSTOPO(x) (HW_SMC_STOPCTRL(x).B.PSTOPO)
/*! @brief Format value for bitfield SMC_STOPCTRL_PSTOPO. */
#define BF_SMC_STOPCTRL_PSTOPO(v) ((uint8_t)((uint8_t)(v) << BP_SMC_STOPCTRL_PSTOPO) & BM_SMC_STOPCTRL_PSTOPO)
/*! @brief Set the PSTOPO field to a new value. */
#define BW_SMC_STOPCTRL_PSTOPO(x, v) (HW_SMC_STOPCTRL_WR(x, (HW_SMC_STOPCTRL_RD(x) & ~BM_SMC_STOPCTRL_PSTOPO) | BF_SMC_STOPCTRL_PSTOPO(v)))
/*@}*/
/*******************************************************************************
* HW_SMC_PMSTAT - Power Mode Status register
******************************************************************************/
/*!
* @brief HW_SMC_PMSTAT - Power Mode Status register (RO)
*
* Reset value: 0x01U
*
* PMSTAT is a read-only, one-hot register which indicates the current power
* mode of the system. This register is reset on Chip POR not VLLS and by reset
* types that trigger Chip POR not VLLS. It is unaffected by reset types that do not
* trigger Chip POR not VLLS. See the Reset section details for more information.
*/
typedef union _hw_smc_pmstat
{
uint8_t U;
struct _hw_smc_pmstat_bitfields
{
uint8_t PMSTAT : 8; /*!< [7:0] */
} B;
} hw_smc_pmstat_t;
/*!
* @name Constants and macros for entire SMC_PMSTAT register
*/
/*@{*/
#define HW_SMC_PMSTAT_ADDR(x) ((x) + 0x3U)
#define HW_SMC_PMSTAT(x) (*(__I hw_smc_pmstat_t *) HW_SMC_PMSTAT_ADDR(x))
#define HW_SMC_PMSTAT_RD(x) (HW_SMC_PMSTAT(x).U)
/*@}*/
/*
* Constants & macros for individual SMC_PMSTAT bitfields
*/
/*!
* @name Register SMC_PMSTAT, field PMSTAT[7:0] (RO)
*
* When debug is enabled, the PMSTAT will not update to STOP or VLPS When a
* PSTOP mode is enabled, the PMSTAT will not update to STOP or VLPS
*/
/*@{*/
#define BP_SMC_PMSTAT_PMSTAT (0U) /*!< Bit position for SMC_PMSTAT_PMSTAT. */
#define BM_SMC_PMSTAT_PMSTAT (0xFFU) /*!< Bit mask for SMC_PMSTAT_PMSTAT. */
#define BS_SMC_PMSTAT_PMSTAT (8U) /*!< Bit field size in bits for SMC_PMSTAT_PMSTAT. */
/*! @brief Read current value of the SMC_PMSTAT_PMSTAT field. */
#define BR_SMC_PMSTAT_PMSTAT(x) (HW_SMC_PMSTAT(x).U)
/*@}*/
/*******************************************************************************
* hw_smc_t - module struct
******************************************************************************/
/*!
* @brief All SMC module registers.
*/
#pragma pack(1)
typedef struct _hw_smc
{
__IO hw_smc_pmprot_t PMPROT; /*!< [0x0] Power Mode Protection register */
__IO hw_smc_pmctrl_t PMCTRL; /*!< [0x1] Power Mode Control register */
__IO hw_smc_stopctrl_t STOPCTRL; /*!< [0x2] Stop Control Register */
__I hw_smc_pmstat_t PMSTAT; /*!< [0x3] Power Mode Status register */
} hw_smc_t;
#pragma pack()
/*! @brief Macro to access all SMC registers. */
/*! @param x SMC module instance base address. */
/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
* use the '&' operator, like <code>&HW_SMC(SMC_BASE)</code>. */
#define HW_SMC(x) (*(hw_smc_t *)(x))
#endif /* __HW_SMC_REGISTERS_H__ */
/* EOF */

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/*
** ###################################################################
** Compilers: Keil ARM C/C++ Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
** Version: rev. 2.5, 2014-05-06
** Build: b140604
**
** Abstract:
** Extension to the CMSIS register access layer header.
**
** Copyright (c) 2014 Freescale Semiconductor, Inc.
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** Revisions:
** - rev. 1.0 (2013-07-23)
** Initial version.
** - rev. 1.1 (2013-09-17)
** RM rev. 0.4 update.
** - rev. 2.0 (2013-10-29)
** Register accessor macros added to the memory map.
** Symbols for Processor Expert memory map compatibility added to the memory map.
** Startup file for gcc has been updated according to CMSIS 3.2.
** System initialization updated.
** - rev. 2.1 (2013-10-30)
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
** - rev. 2.2 (2013-12-20)
** Update according to reference manual rev. 0.6,
** - rev. 2.3 (2014-01-13)
** Update according to reference manual rev. 0.61,
** - rev. 2.4 (2014-02-10)
** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
** - rev. 2.5 (2014-05-06)
** Update according to reference manual rev. 1.0,
** Update of system and startup files.
** Module access macro module_BASES replaced by module_BASE_PTRS.
**
** ###################################################################
*/
/*
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
*
* This file was generated automatically and any changes may be lost.
*/
#ifndef __HW_VREF_REGISTERS_H__
#define __HW_VREF_REGISTERS_H__
#include "MK22F51212.h"
#include "fsl_bitaccess.h"
/*
* MK22F51212 VREF
*
* Voltage Reference
*
* Registers defined in this header file:
* - HW_VREF_TRM - VREF Trim Register
* - HW_VREF_SC - VREF Status and Control Register
*
* - hw_vref_t - Struct containing all module registers.
*/
#define HW_VREF_INSTANCE_COUNT (1U) /*!< Number of instances of the VREF module. */
/*******************************************************************************
* HW_VREF_TRM - VREF Trim Register
******************************************************************************/
/*!
* @brief HW_VREF_TRM - VREF Trim Register (RW)
*
* Reset value: 0x00U
*
* This register contains bits that contain the trim data for the Voltage
* Reference.
*/
typedef union _hw_vref_trm
{
uint8_t U;
struct _hw_vref_trm_bitfields
{
uint8_t TRIM : 6; /*!< [5:0] Trim bits */
uint8_t CHOPEN : 1; /*!< [6] Chop oscillator enable. When set,
* internal chopping operation is enabled and the internal analog offset will be
* minimized. */
uint8_t RESERVED0 : 1; /*!< [7] */
} B;
} hw_vref_trm_t;
/*!
* @name Constants and macros for entire VREF_TRM register
*/
/*@{*/
#define HW_VREF_TRM_ADDR(x) ((x) + 0x0U)
#define HW_VREF_TRM(x) (*(__IO hw_vref_trm_t *) HW_VREF_TRM_ADDR(x))
#define HW_VREF_TRM_RD(x) (HW_VREF_TRM(x).U)
#define HW_VREF_TRM_WR(x, v) (HW_VREF_TRM(x).U = (v))
#define HW_VREF_TRM_SET(x, v) (HW_VREF_TRM_WR(x, HW_VREF_TRM_RD(x) | (v)))
#define HW_VREF_TRM_CLR(x, v) (HW_VREF_TRM_WR(x, HW_VREF_TRM_RD(x) & ~(v)))
#define HW_VREF_TRM_TOG(x, v) (HW_VREF_TRM_WR(x, HW_VREF_TRM_RD(x) ^ (v)))
/*@}*/
/*
* Constants & macros for individual VREF_TRM bitfields
*/
/*!
* @name Register VREF_TRM, field TRIM[5:0] (RW)
*
* These bits change the resulting VREF by approximately +/- 0.5 mV for each
* step. Min = minimum and max = maximum voltage reference output. For minimum and
* maximum voltage reference output values, refer to the Data Sheet for this chip.
*
* Values:
* - 000000 - Min
* - 111111 - Max
*/
/*@{*/
#define BP_VREF_TRM_TRIM (0U) /*!< Bit position for VREF_TRM_TRIM. */
#define BM_VREF_TRM_TRIM (0x3FU) /*!< Bit mask for VREF_TRM_TRIM. */
#define BS_VREF_TRM_TRIM (6U) /*!< Bit field size in bits for VREF_TRM_TRIM. */
/*! @brief Read current value of the VREF_TRM_TRIM field. */
#define BR_VREF_TRM_TRIM(x) (HW_VREF_TRM(x).B.TRIM)
/*! @brief Format value for bitfield VREF_TRM_TRIM. */
#define BF_VREF_TRM_TRIM(v) ((uint8_t)((uint8_t)(v) << BP_VREF_TRM_TRIM) & BM_VREF_TRM_TRIM)
/*! @brief Set the TRIM field to a new value. */
#define BW_VREF_TRM_TRIM(x, v) (HW_VREF_TRM_WR(x, (HW_VREF_TRM_RD(x) & ~BM_VREF_TRM_TRIM) | BF_VREF_TRM_TRIM(v)))
/*@}*/
/*!
* @name Register VREF_TRM, field CHOPEN[6] (RW)
*
* This bit is set during factory trimming of the VREF voltage. This bit should
* be written to 1 to achieve the performance stated in the data sheet.
*
* Values:
* - 0 - Chop oscillator is disabled.
* - 1 - Chop oscillator is enabled.
*/
/*@{*/
#define BP_VREF_TRM_CHOPEN (6U) /*!< Bit position for VREF_TRM_CHOPEN. */
#define BM_VREF_TRM_CHOPEN (0x40U) /*!< Bit mask for VREF_TRM_CHOPEN. */
#define BS_VREF_TRM_CHOPEN (1U) /*!< Bit field size in bits for VREF_TRM_CHOPEN. */
/*! @brief Read current value of the VREF_TRM_CHOPEN field. */
#define BR_VREF_TRM_CHOPEN(x) (BITBAND_ACCESS8(HW_VREF_TRM_ADDR(x), BP_VREF_TRM_CHOPEN))
/*! @brief Format value for bitfield VREF_TRM_CHOPEN. */
#define BF_VREF_TRM_CHOPEN(v) ((uint8_t)((uint8_t)(v) << BP_VREF_TRM_CHOPEN) & BM_VREF_TRM_CHOPEN)
/*! @brief Set the CHOPEN field to a new value. */
#define BW_VREF_TRM_CHOPEN(x, v) (BITBAND_ACCESS8(HW_VREF_TRM_ADDR(x), BP_VREF_TRM_CHOPEN) = (v))
/*@}*/
/*******************************************************************************
* HW_VREF_SC - VREF Status and Control Register
******************************************************************************/
/*!
* @brief HW_VREF_SC - VREF Status and Control Register (RW)
*
* Reset value: 0x00U
*
* This register contains the control bits used to enable the internal voltage
* reference and to select the buffer mode to be used.
*/
typedef union _hw_vref_sc
{
uint8_t U;
struct _hw_vref_sc_bitfields
{
uint8_t MODE_LV : 2; /*!< [1:0] Buffer Mode selection */
uint8_t VREFST : 1; /*!< [2] Internal Voltage Reference stable */
uint8_t RESERVED0 : 2; /*!< [4:3] */
uint8_t ICOMPEN : 1; /*!< [5] Second order curvature compensation
* enable */
uint8_t REGEN : 1; /*!< [6] Regulator enable */
uint8_t VREFEN : 1; /*!< [7] Internal Voltage Reference enable */
} B;
} hw_vref_sc_t;
/*!
* @name Constants and macros for entire VREF_SC register
*/
/*@{*/
#define HW_VREF_SC_ADDR(x) ((x) + 0x1U)
#define HW_VREF_SC(x) (*(__IO hw_vref_sc_t *) HW_VREF_SC_ADDR(x))
#define HW_VREF_SC_RD(x) (HW_VREF_SC(x).U)
#define HW_VREF_SC_WR(x, v) (HW_VREF_SC(x).U = (v))
#define HW_VREF_SC_SET(x, v) (HW_VREF_SC_WR(x, HW_VREF_SC_RD(x) | (v)))
#define HW_VREF_SC_CLR(x, v) (HW_VREF_SC_WR(x, HW_VREF_SC_RD(x) & ~(v)))
#define HW_VREF_SC_TOG(x, v) (HW_VREF_SC_WR(x, HW_VREF_SC_RD(x) ^ (v)))
/*@}*/
/*
* Constants & macros for individual VREF_SC bitfields
*/
/*!
* @name Register VREF_SC, field MODE_LV[1:0] (RW)
*
* These bits select the buffer modes for the Voltage Reference module.
*
* Values:
* - 00 - Bandgap on only, for stabilization and startup
* - 01 - High power buffer mode enabled
* - 10 - Low-power buffer mode enabled
* - 11 - Reserved
*/
/*@{*/
#define BP_VREF_SC_MODE_LV (0U) /*!< Bit position for VREF_SC_MODE_LV. */
#define BM_VREF_SC_MODE_LV (0x03U) /*!< Bit mask for VREF_SC_MODE_LV. */
#define BS_VREF_SC_MODE_LV (2U) /*!< Bit field size in bits for VREF_SC_MODE_LV. */
/*! @brief Read current value of the VREF_SC_MODE_LV field. */
#define BR_VREF_SC_MODE_LV(x) (HW_VREF_SC(x).B.MODE_LV)
/*! @brief Format value for bitfield VREF_SC_MODE_LV. */
#define BF_VREF_SC_MODE_LV(v) ((uint8_t)((uint8_t)(v) << BP_VREF_SC_MODE_LV) & BM_VREF_SC_MODE_LV)
/*! @brief Set the MODE_LV field to a new value. */
#define BW_VREF_SC_MODE_LV(x, v) (HW_VREF_SC_WR(x, (HW_VREF_SC_RD(x) & ~BM_VREF_SC_MODE_LV) | BF_VREF_SC_MODE_LV(v)))
/*@}*/
/*!
* @name Register VREF_SC, field VREFST[2] (RO)
*
* This bit indicates that the bandgap reference within the Voltage Reference
* module has completed its startup and stabilization.
*
* Values:
* - 0 - The module is disabled or not stable.
* - 1 - The module is stable.
*/
/*@{*/
#define BP_VREF_SC_VREFST (2U) /*!< Bit position for VREF_SC_VREFST. */
#define BM_VREF_SC_VREFST (0x04U) /*!< Bit mask for VREF_SC_VREFST. */
#define BS_VREF_SC_VREFST (1U) /*!< Bit field size in bits for VREF_SC_VREFST. */
/*! @brief Read current value of the VREF_SC_VREFST field. */
#define BR_VREF_SC_VREFST(x) (BITBAND_ACCESS8(HW_VREF_SC_ADDR(x), BP_VREF_SC_VREFST))
/*@}*/
/*!
* @name Register VREF_SC, field ICOMPEN[5] (RW)
*
* This bit is set during factory trimming of the VREF voltage. This bit should
* be written to 1 to achieve the performance stated in the data sheet.
*
* Values:
* - 0 - Disabled
* - 1 - Enabled
*/
/*@{*/
#define BP_VREF_SC_ICOMPEN (5U) /*!< Bit position for VREF_SC_ICOMPEN. */
#define BM_VREF_SC_ICOMPEN (0x20U) /*!< Bit mask for VREF_SC_ICOMPEN. */
#define BS_VREF_SC_ICOMPEN (1U) /*!< Bit field size in bits for VREF_SC_ICOMPEN. */
/*! @brief Read current value of the VREF_SC_ICOMPEN field. */
#define BR_VREF_SC_ICOMPEN(x) (BITBAND_ACCESS8(HW_VREF_SC_ADDR(x), BP_VREF_SC_ICOMPEN))
/*! @brief Format value for bitfield VREF_SC_ICOMPEN. */
#define BF_VREF_SC_ICOMPEN(v) ((uint8_t)((uint8_t)(v) << BP_VREF_SC_ICOMPEN) & BM_VREF_SC_ICOMPEN)
/*! @brief Set the ICOMPEN field to a new value. */
#define BW_VREF_SC_ICOMPEN(x, v) (BITBAND_ACCESS8(HW_VREF_SC_ADDR(x), BP_VREF_SC_ICOMPEN) = (v))
/*@}*/
/*!
* @name Register VREF_SC, field REGEN[6] (RW)
*
* This bit is used to enable the internal 1.75 V regulator to produce a
* constant internal voltage supply in order to reduce the sensitivity to external
* supply noise and variation. If it is desired to keep the regulator enabled in very
* low power modes, refer to the Chip Configuration details for a description on
* how this can be achieved. This bit is set during factory trimming of the VREF
* voltage. This bit should be written to 1 to achieve the performance stated in
* the data sheet.
*
* Values:
* - 0 - Internal 1.75 V regulator is disabled.
* - 1 - Internal 1.75 V regulator is enabled.
*/
/*@{*/
#define BP_VREF_SC_REGEN (6U) /*!< Bit position for VREF_SC_REGEN. */
#define BM_VREF_SC_REGEN (0x40U) /*!< Bit mask for VREF_SC_REGEN. */
#define BS_VREF_SC_REGEN (1U) /*!< Bit field size in bits for VREF_SC_REGEN. */
/*! @brief Read current value of the VREF_SC_REGEN field. */
#define BR_VREF_SC_REGEN(x) (BITBAND_ACCESS8(HW_VREF_SC_ADDR(x), BP_VREF_SC_REGEN))
/*! @brief Format value for bitfield VREF_SC_REGEN. */
#define BF_VREF_SC_REGEN(v) ((uint8_t)((uint8_t)(v) << BP_VREF_SC_REGEN) & BM_VREF_SC_REGEN)
/*! @brief Set the REGEN field to a new value. */
#define BW_VREF_SC_REGEN(x, v) (BITBAND_ACCESS8(HW_VREF_SC_ADDR(x), BP_VREF_SC_REGEN) = (v))
/*@}*/
/*!
* @name Register VREF_SC, field VREFEN[7] (RW)
*
* This bit is used to enable the bandgap reference within the Voltage Reference
* module. After the VREF is enabled, turning off the clock to the VREF module
* via the corresponding clock gate register will not disable the VREF. VREF must
* be disabled via this VREFEN bit.
*
* Values:
* - 0 - The module is disabled.
* - 1 - The module is enabled.
*/
/*@{*/
#define BP_VREF_SC_VREFEN (7U) /*!< Bit position for VREF_SC_VREFEN. */
#define BM_VREF_SC_VREFEN (0x80U) /*!< Bit mask for VREF_SC_VREFEN. */
#define BS_VREF_SC_VREFEN (1U) /*!< Bit field size in bits for VREF_SC_VREFEN. */
/*! @brief Read current value of the VREF_SC_VREFEN field. */
#define BR_VREF_SC_VREFEN(x) (BITBAND_ACCESS8(HW_VREF_SC_ADDR(x), BP_VREF_SC_VREFEN))
/*! @brief Format value for bitfield VREF_SC_VREFEN. */
#define BF_VREF_SC_VREFEN(v) ((uint8_t)((uint8_t)(v) << BP_VREF_SC_VREFEN) & BM_VREF_SC_VREFEN)
/*! @brief Set the VREFEN field to a new value. */
#define BW_VREF_SC_VREFEN(x, v) (BITBAND_ACCESS8(HW_VREF_SC_ADDR(x), BP_VREF_SC_VREFEN) = (v))
/*@}*/
/*******************************************************************************
* hw_vref_t - module struct
******************************************************************************/
/*!
* @brief All VREF module registers.
*/
#pragma pack(1)
typedef struct _hw_vref
{
__IO hw_vref_trm_t TRM; /*!< [0x0] VREF Trim Register */
__IO hw_vref_sc_t SC; /*!< [0x1] VREF Status and Control Register */
} hw_vref_t;
#pragma pack()
/*! @brief Macro to access all VREF registers. */
/*! @param x VREF module instance base address. */
/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
* use the '&' operator, like <code>&HW_VREF(VREF_BASE)</code>. */
#define HW_VREF(x) (*(hw_vref_t *)(x))
#endif /* __HW_VREF_REGISTERS_H__ */
/* EOF */

1153
libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_wdog.h Normal file
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159
libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/regs.h → libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/fsl_bitaccess.h
View File

@ -1,62 +1,75 @@
/*
* Copyright (c) 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*/
** ###################################################################
** Version: rev. 2.5, 2014-05-06
** Build: b140604
**
** Abstract:
** Register bit field access macros.
**
** Copyright (c) 2014 Freescale Semiconductor, Inc.
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** Revisions:
** - rev. 1.0 (2013-07-23)
** Initial version.
** - rev. 1.1 (2013-09-17)
** RM rev. 0.4 update.
** - rev. 2.0 (2013-10-29)
** Register accessor macros added to the memory map.
** Symbols for Processor Expert memory map compatibility added to the memory map.
** Startup file for gcc has been updated according to CMSIS 3.2.
** System initialization updated.
** - rev. 2.1 (2013-10-30)
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
** - rev. 2.2 (2013-12-20)
** Update according to reference manual rev. 0.6,
** - rev. 2.3 (2014-01-13)
** Update according to reference manual rev. 0.61,
** - rev. 2.4 (2014-02-10)
** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
** - rev. 2.5 (2014-05-06)
** Update according to reference manual rev. 1.0,
** Update of system and startup files.
** Module access macro module_BASES replaced by module_BASE_PTRS.
**
** ###################################################################
*/
#ifndef _REGS_H
#define _REGS_H 1
#ifndef _FSL_BITACCESS_H
#define _FSL_BITACCESS_H 1
#include <stdint.h>
#include <stdlib.h>
//
// define base address of the register block only if it is not already
// defined, which allows the compiler to override at build time for
// users who've mapped their registers to locations other than the
// physical location
//
#include <stdint.h>
#ifndef REGS_BASE
#define REGS_BASE 0x00000000
#endif
//
// common register types
//
#ifndef __LANGUAGE_ASM__
typedef unsigned char reg8_t;
typedef unsigned short reg16_t;
typedef unsigned int reg32_t;
#endif
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
#define BME_AND_MASK (1<<26)
#define BME_OR_MASK (1<<27)
#define BME_XOR_MASK (3<<26)
#define BME_BFI_MASK(BIT,WIDTH) (1<<28) | (BIT<<23) | ((WIDTH-1)<<19)
#define BME_UBFX_MASK(BIT,WIDTH) (1<<28) | (BIT<<23) | ((WIDTH-1)<<19)
/**
* @brief Macro to access a single bit of a 32-bit peripheral register (bit band region
* 0x40000000 to 0x400FFFFF) using the bit-band alias region access.
@ -84,21 +97,9 @@ typedef unsigned int reg32_t;
*/
#define BITBAND_ACCESS8(Reg,Bit) (*((uint8_t volatile*)(0x42000000u + (32u*((uint32_t)(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))))
//
// Typecast macro for C or asm. In C, the cast is applied, while in asm it is excluded. This is
// used to simplify macro definitions in the module register headers.
//
#ifndef __REG_VALUE_TYPE
#ifndef __LANGUAGE_ASM__
#define __REG_VALUE_TYPE(v, t) ((t)(v))
#else
#define __REG_VALUE_TYPE(v, t) (v)
#endif
#endif
//
// macros for single instance registers
//
/*
* Macros for single instance registers
*/
#define BF_SET(reg, field) HW_##reg##_SET(BM_##reg##_##field)
#define BF_CLR(reg, field) HW_##reg##_CLR(BM_##reg##_##field)
@ -202,9 +203,9 @@ typedef unsigned int reg32_t;
BF_##reg##_##f7(v7) | \
BF_##reg##_##f8(v8)))
//
// macros for multiple instance registers
//
/*
* Macros for multiple instance registers
*/
#define BF_SETn(reg, n, field) HW_##reg##_SET(n, BM_##reg##_##field)
#define BF_CLRn(reg, n, field) HW_##reg##_CLR(n, BM_##reg##_##field)
@ -308,9 +309,9 @@ typedef unsigned int reg32_t;
BF_##reg##_##f7(v7) | \
BF_##reg##_##f8(v8))))
//
// macros for single instance MULTI-BLOCK registers
//
/*
* Macros for single instance MULTI-BLOCK registers
*/
#define BFn_SET(reg, blk, field) HW_##reg##_SET(blk, BM_##reg##_##field)
#define BFn_CLR(reg, blk, field) HW_##reg##_CLR(blk, BM_##reg##_##field)
@ -414,9 +415,9 @@ typedef unsigned int reg32_t;
BF_##reg##_##f7(v7) | \
BF_##reg##_##f8(v8)))
//
// macros for MULTI-BLOCK multiple instance registers
//
/*
* Macros for MULTI-BLOCK multiple instance registers
*/
#define BFn_SETn(reg, blk, n, field) HW_##reg##_SET(blk, n, BM_##reg##_##field)
#define BFn_CLRn(reg, blk, n, field) HW_##reg##_CLR(blk, n, BM_##reg##_##field)
@ -520,6 +521,6 @@ typedef unsigned int reg32_t;
BF_##reg##_##f7(v7) | \
BF_##reg##_##f8(v8))))
#endif // _REGS_H
#endif /* _FSL_BITACCESS_H */
////////////////////////////////////////////////////////////////////////////////
/******************************************************************************/

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33
libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/mbed_overrides.c Normal file
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@ -0,0 +1,33 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "gpio_api.h"
#include "pinmap.h"
// called before main - implement here if board needs it otherwise, let
// the application override this if necessary
void mbed_sdk_init()
{
pin_function(PTA2, 1); //By default the GREEN LED is enabled. This disables it
}
// Change the NMI pin to an input. This allows NMI pin to
// be used as a low power mode wakeup. The application will
// need to change the pin back to NMI_b or wakeup only occurs once!
void NMI_Handler(void)
{
gpio_t gpio;
gpio_init_in(&gpio, PTA4);
}

3
libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/common/phyksz8081/fsl_phy_driver.c
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@ -30,6 +30,8 @@
#include "fsl_phy_driver.h"
#ifndef MBED_NO_ENET
/*******************************************************************************
* Variables
******************************************************************************/
@ -257,6 +259,7 @@ uint32_t phy_get_link_duplex(enet_dev_if_t * enetIfPtr, enet_phy_duplex_t *statu
return result;
}
#endif
/*******************************************************************************
* EOF

7
libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/common/phyksz8081/fsl_phy_driver.h
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@ -33,7 +33,10 @@
#include <stdint.h>
#include <stdbool.h>
#include "fsl_enet_driver.h"
/*!
#ifndef MBED_NO_ENET
/*!
* @addtogroup phy_driver
* @{
*/
@ -181,6 +184,8 @@ uint32_t phy_get_link_duplex(enet_dev_if_t * enetIfPtr, enet_phy_duplex_t *statu
extern }
#endif
#endif
/*! @}*/
#endif /* __FSL_PHY_DRIVER_H__ */

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@ -1,228 +0,0 @@
/*
* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#if !defined(__FSL_CLOCK_CONFIGS_H__)
#define __FSL_CLOCK_CONFIGS_H__
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @addtogroup clock_manager*/
/*! @{*/
#if defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FN1M0VMJ15)
#define CLOCK_SETUP 1
/*! @brief Predefined clock setups for K70*/
/*
0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
Reference clock source for MCG module is the slow internal clock source 32.768kHz
Core clock = 41.94MHz, BusClock = 41.94MHz
1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
Reference clock source for MCG module is an external reference clock source 50MHz
Core clock = 120MHz, BusClock = 60MHz
2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode
Core clock/Bus clock derived directly from an external reference clock source 50MHz with no multiplication
Core clock = 50MHz, BusClock = 50MHz
*/
/*! @brief Define clock source values for K70*/
#if (CLOCK_SETUP == 0)
#define CPU_XTAL0_CLK_HZ 50000000u /* external crystal or osc clock frequency in Hz connected to System Oscillator 0*/
#define CPU_XTAL1_CLK_HZ 8000000u /* external crystal or osc clock frequency in Hz connected to System Oscillator 1*/
#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz*/
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz*/
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz*/
#define DEFAULT_SYSTEM_CLOCK 41943040u /* Default System clock value*/
#elif (CLOCK_SETUP == 1)
#define CPU_XTAL0_CLK_HZ 50000000u /* external crystal or osc clock frequency in Hz connected to System Oscillator 0*/
#define CPU_XTAL1_CLK_HZ 8000000u /* external crystal or osc clock frequency in Hz connected to System Oscillator 1*/
#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz*/
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz*/
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz*/
#define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value*/
#elif (CLOCK_SETUP == 2)
#define CPU_XTAL0_CLK_HZ 50000000u /* external crystal or osc clock frequency in Hz connected to System Oscillator 0*/
#define CPU_XTAL1_CLK_HZ 8000000u /* external crystal or osc clock frequency in Hz connected to System Oscillator 1*/
#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz*/
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz*/
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz*/
#define DEFAULT_SYSTEM_CLOCK 50000000u /* Default System clock value*/
#endif /* (CLOCK_SETUP == 2)*/
#elif defined(CPU_MKL25Z128VLK4)
#define CLOCK_SETUP 1
/*! @brief Predefined clock setups for KL25*/
/*
0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
Reference clock source for MCG module is the slow internal clock source 32.768kHz
Core clock = 41.94MHz, BusClock = 13.98MHz
1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
Reference clock source for MCG module is an external crystal 8MHz
Core clock = 48MHz, BusClock = 24MHz
2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode
Core clock/Bus clock derived directly from an external crystal 8MHz with no multiplication
Core clock = 8MHz, BusClock = 8MHz
*/
/*! @brief Define clock source values for KL25*/
#if (CLOCK_SETUP == 0)
#define CPU_XTAL_CLK_HZ 8000000u /* external crystal or oscillator clock frequency in Hz*/
#define CPU_INT_SLOW_CLK_HZ 32768u /* slow internal oscillator clock frequency in Hz*/
#define CPU_INT_FAST_CLK_HZ 4000000u /* fast internal oscillator clock frequency in Hz*/
#define DEFAULT_SYSTEM_CLOCK 41943040u /* Default System clock value*/
#elif (CLOCK_SETUP == 1)
#define CPU_XTAL_CLK_HZ 8000000u /* external crystal or oscillator clock frequency in Hz*/
#define CPU_INT_SLOW_CLK_HZ 32768u /* slow internal oscillator clock frequency in Hz*/
#define CPU_INT_FAST_CLK_HZ 4000000u /* fast internal oscillator clock frequency in Hz*/
#define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value*/
#elif (CLOCK_SETUP == 2)
#define CPU_XTAL_CLK_HZ 8000000u /* external crystal or oscillator clock frequency in Hz*/
#define CPU_INT_SLOW_CLK_HZ 32768u /* slow internal oscillator clock frequency in Hz*/
#define CPU_INT_FAST_CLK_HZ 4000000u /* fast internal oscillator clock frequency in Hz*/
#define DEFAULT_SYSTEM_CLOCK 8000000u /* Default System clock value*/
#endif /*(CLOCK_SETUP == 2)*/
#elif defined(CPU_MK64FN1M0VMD12)
#define DISABLE_WDOG 1
#define CLOCK_SETUP 1
/* Predefined clock setups
0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
Reference clock source for MCG module is the slow internal clock source 32.768kHz
Core clock = 20.97MHz, BusClock = 20.97MHz
1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
Reference clock source for MCG module is an external clock source 50MHz
USB clock divider is set for USB to receive 48MHz input clock.
Core clock = 120MHz, BusClock = 60MHz
3 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power Internal (BLPI) mode
Core clock/Bus clock derived directly from an fast internal clock 4MHz with no multiplication
The clock settings is ready for Very Low Power Run mode.
Core clock = 4MHz, BusClock = 4MHz
*/
/*----------------------------------------------------------------------------
Define clock source values
*----------------------------------------------------------------------------*/
#if (CLOCK_SETUP == 0)
#define CPU_XTAL_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */
#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
#define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */
#define DEFAULT_SYSTEM_CLOCK 20485760u /* Default System clock value */
#elif (CLOCK_SETUP == 1)
#define CPU_XTAL_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */
#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
#define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */
#define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value */
#elif (CLOCK_SETUP == 3)
#define CPU_XTAL_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */
#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
#define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */
#define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */
#endif /* (CLOCK_SETUP == 3) */
#elif defined(CPU_MK22FN512VDC12)
#define DISABLE_WDOG 1
#define CLOCK_SETUP 1
/* Predefined clock setups
0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
Reference clock source for MCG module is the slow internal clock source 32.768kHz
Core clock = 41.94MHz, BusClock = 41.94MHz
1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
Reference clock source for MCG module is an external crystal 8MHz
Core clock = 100MHz, BusClock = 50MHz
2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode
Core clock/Bus clock derived directly from an external crystal 8MHz with no multiplication
Core clock = 8MHz, BusClock = 8MHz
3 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
Reference clock source for MCG module is an external crystal 8MHz
Core clock = 120MHz, BusClock = 60MHz
*/
/*----------------------------------------------------------------------------
Define clock source values
*----------------------------------------------------------------------------*/
#if (CLOCK_SETUP == 0)
#define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
#define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */
#define DEFAULT_SYSTEM_CLOCK 41943040u /* Default System clock value */
#elif (CLOCK_SETUP == 1)
#define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
#define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */
#define DEFAULT_SYSTEM_CLOCK 100000000u /* Default System clock value */
#elif (CLOCK_SETUP == 2)
#define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
#define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */
#define DEFAULT_SYSTEM_CLOCK 8000000u /* Default System clock value */
#elif (CLOCK_SETUP == 3)
#define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
#define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */
#define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value */
#endif /* (CLOCK_SETUP == 3) */
#endif /* CPU types*/
/*! @}*/
#endif /* __FSL_CLOCK_CONFIGS_H__*/
/*******************************************************************************
* EOF
******************************************************************************/

299
libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/clock/fsl_clock_manager.c Normal file
View File

@ -0,0 +1,299 @@
/*
* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fsl_device_registers.h"
#include "fsl_clock_manager.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/* Table of base addresses for instances. */
const uint32_t g_simBaseAddr[] = SIM_BASE_ADDRS;
const uint32_t g_mcgBaseAddr[] = MCG_BASE_ADDRS;
/*******************************************************************************
* Code
******************************************************************************/
/*FUNCTION**********************************************************************
*
* Function Name : CLOCK_SYS_GetSysClkFreq
* Description : Internal function to get the system clock frequency
* This function will check the clock name configuration table for specific
* chip family and find out the supported clock name for that chip family
* then it will call the mcg hal function to get the basic system clock,
* calculate the clock frequency for specified clock name.
*
*END**************************************************************************/
clock_manager_error_code_t CLOCK_SYS_GetSysClkFreq(clock_names_t clockName,
uint32_t *frequency)
{
/* system clock out divider*/
uint32_t divider;
const clock_name_config_t *table = &kClockNameConfigTable[clockName];
/* check if we need to use a reference clock*/
if (table->useOtherRefClock)
{
/* get other specified ref clock*/
if ( kClockManagerSuccess != CLOCK_SYS_GetFreq(table->otherRefClockName,
frequency) )
{
return kClockManagerNoSuchClockName;
}
}
else
{
/* get default ref clock */
*frequency = CLOCK_HAL_GetOutClk(g_mcgBaseAddr[0]);
}
/* get system clock divider*/
if ( CLOCK_HAL_GetDivider(g_simBaseAddr[0], table->dividerName, &divider) == kSimHalSuccess)
{
/* get the frequency for the specified clock*/
*frequency = (*frequency) / (divider + 1);
return kClockManagerSuccess;
}
else
{
return kClockManagerNoSuchDivider;
}
}
/*FUNCTION**********************************************************************
*
* Function Name : CLOCK_SYS_GetFreq
* Description : Internal function to get the frequency by clock name
* This function will get/calculate the clock frequency based on clock name
* and current configuration of clock generator.
*
*END**************************************************************************/
clock_manager_error_code_t CLOCK_SYS_GetFreq(clock_names_t clockName,
uint32_t *frequency)
{
clock_manager_error_code_t returnCode = kClockManagerSuccess;
/* branch according to clock name */
switch(clockName)
{
/* osc clock*/
case kOsc32kClock:
*frequency = CPU_XTAL32k_CLK_HZ;
break;
case kOsc0ErClock:
#if FSL_FEATURE_MCG_HAS_OSC1
/* System oscillator 0 drives MCG clock */
*frequency = CPU_XTAL0_CLK_HZ;
#else
/* System oscillator 0 drives MCG clock */
*frequency = CPU_XTAL_CLK_HZ;
#endif
break;
#if FSL_FEATURE_MCG_HAS_OSC1
case kOsc1ErClock:
*frequency = CPU_XTAL1_CLK_HZ;
break;
#endif
#if FSL_FEATURE_MCG_HAS_IRC_48M
/* irc clock*/
case kIrc48mClock:
*frequency = CPU_INT_IRC_CLK_HZ;
break;
#endif
/* rtc clock*/
case kRtc32kClock:
*frequency = CPU_XTAL32k_CLK_HZ;
break;
case kRtc1hzClock:
*frequency = CPU_XTAL1hz_CLK_HZ; // defined in fsl_clock_manager.h for now
break;
/* lpo clcok*/
case kLpoClock:
*frequency = CPU_LPO_CLK_HZ; // defined in fsl_clock_manager.h for now
break;
/* mcg clocks, calling mcg clock functions */
case kMcgFfClock:
*frequency = CLOCK_HAL_GetFllRefClk(g_mcgBaseAddr[0]);
break;
case kMcgFllClock:
*frequency = CLOCK_HAL_GetFllClk(g_mcgBaseAddr[0]);
break;
#if FSL_FEATURE_MCG_HAS_PLL
case kMcgPll0Clock:
*frequency = CLOCK_HAL_GetPll0Clk(g_mcgBaseAddr[0]);
break;
#endif
case kMcgOutClock:
*frequency = CLOCK_HAL_GetOutClk(g_mcgBaseAddr[0]);
break;
case kMcgIrClock:
*frequency = CLOCK_HAL_GetInternalRefClk(g_mcgBaseAddr[0]);
break;
case kSDHC0_CLKIN:
*frequency = SDHC0_CLKIN; // defined in fsl_clock_manager.h for now
break;
case kENET_1588_CLKIN:
*frequency = ENET_1588_CLKIN; // defined in fsl_clock_manager.h for now
break;
case kEXTAL_Clock:
*frequency = EXTAL_Clock; // defined in fsl_clock_manager.h for now
break;
case kEXTAL1_Clock:
*frequency = EXTAL1_Clock; // defined in fsl_clock_manager.h for now
break;
case kUSB_CLKIN:
*frequency = USB_CLKIN; // defined in fsl_clock_manager.h for now
break;
/* system clocks */
case kCoreClock:
case kSystemClock:
case kPlatformClock:
case kBusClock:
case kFlexBusClock:
case kFlashClock:
returnCode = CLOCK_SYS_GetSysClkFreq(clockName, frequency);
break;
/* reserved value*/
case kReserved:
default:
*frequency = 55555; /* for testing use purpose*/
returnCode = kClockManagerNoSuchClockName;
break;
}
return returnCode;
}
/*FUNCTION**********************************************************************
*
* Function Name : CLOCK_SYS_SetSource
* Description : Set clock source setting
* This function will set the settings for specified clock source. Each clock
* source has its clock selection settings. Refer to reference manual for
* details of settings for each clock source. Refer to clock_source_names_t
* for clock sources.
*
*END**************************************************************************/
clock_manager_error_code_t CLOCK_SYS_SetSource(clock_source_names_t clockSource,
uint8_t setting)
{
clock_manager_error_code_t returnCode = kClockManagerSuccess;
if (CLOCK_HAL_SetSource(g_simBaseAddr[0], clockSource, setting) != kSimHalSuccess)
{
returnCode = kClockManagerNoSuchClockSource;
}
return returnCode;
}
/*FUNCTION**********************************************************************
*
* Function Name : CLOCK_SYS_GetSource
* Description : Get clock source setting
* This function will get the settings for specified clock source. Each clock
* source has its clock selection settings. Refer to reference manual for
* details of settings for each clock source. Refer to clock_source_names_t
* for clock sources.
*
*END**************************************************************************/
clock_manager_error_code_t CLOCK_SYS_GetSource(clock_source_names_t clockSource,
uint8_t *setting)
{
clock_manager_error_code_t returnCode = kClockManagerSuccess;
if (CLOCK_HAL_GetSource(g_simBaseAddr[0], clockSource, setting) != kSimHalSuccess)
{
returnCode = kClockManagerNoSuchClockSource;
}
return returnCode;
}
/*FUNCTION**********************************************************************
*
* Function Name : CLOCK_SYS_SetDivider
* Description : Set clock divider setting
* This function will set the setting for specified clock divider. Refer to
* reference manual for supported clock divider and value range. Refer to
* clock_divider_names_t for dividers.
*
*END**************************************************************************/
clock_manager_error_code_t CLOCK_SYS_SetDivider(clock_divider_names_t clockDivider,
uint32_t setting)
{
clock_manager_error_code_t returnCode = kClockManagerSuccess;
if (CLOCK_HAL_SetDivider(g_simBaseAddr[0], clockDivider, setting) != kSimHalSuccess)
{
returnCode = kClockManagerNoSuchDivider;
}
return returnCode;
}
/*FUNCTION**********************************************************************
*
* Function Name : CLOCK_SYS_GetDivider
* Description : Get clock divider setting
* This function will get the setting for specified clock divider. Refer to
* reference manual for supported clock divider and value range. Refer to
* clock_divider_names_t for dividers.
*
*END**************************************************************************/
clock_manager_error_code_t CLOCK_SYS_GetDivider(clock_divider_names_t clockDivider,
uint32_t *setting)
{
clock_manager_error_code_t returnCode = kClockManagerSuccess;
if (CLOCK_HAL_GetDivider(g_simBaseAddr[0], clockDivider, setting) != kSimHalSuccess)
{
returnCode = kClockManagerNoSuchDivider;
}
return returnCode;
}
/*******************************************************************************
* EOF
******************************************************************************/

510
libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/clock/fsl_clock_manager.h
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@ -34,6 +34,8 @@
#include <stdint.h>
#include <stdbool.h>
#include <assert.h>
#include "fsl_mcg_hal.h"
#include "fsl_sim_hal.h"
/*! @addtogroup clock_manager*/
/*! @{*/
@ -44,140 +46,21 @@
* Definitions
******************************************************************************/
/*! @brief Clock names */
typedef enum _clock_names {
/* default system clocks*/
kCoreClock, /**/
kSystemClock, /**/
kPlatformClock, /**/
kBusClock, /**/
kFlexBusClock, /**/
kFlashClock, /**/
/* other internal clocks used by peripherals*/
/* system clocks definition (should be moved to other proper place) */
#define CPU_XTAL1hz_CLK_HZ 1
#define CPU_LPO_CLK_HZ 1000
/* osc clock*/
kOsc32kClock,
kOsc0ErClock,
kOsc1ErClock,
/* irc 48Mhz clock */
kIrc48mClock,
/* external clock definition (should be moved to other proper place) */
/* rtc clock*/
kRtc32kClock,
kRtc1hzClock,
#define SDHC0_CLKIN 0 /* kSimSDHC0_CLKIN */
#define ENET_1588_CLKIN 0 /* kSimENET_1588_CLKIN */
#define EXTAL_Clock 0 /* kSimEXTAL_Clock */
#define EXTAL1_Clock 0 /* kSimEXTAL1_Clock */
#define USB_CLKIN 0 /* kSimUSB_CLKIN */
/* lpo clcok*/
kLpoClock,
/* mcg clocks*/
kMcgFllClock,
kMcgPll0Clock,
kMcgPll1Clock,
kMcgOutClock,
kMcgIrClock,
/* constant clocks (provided in other header files?)*/
kSDHC0_CLKIN,
kENET_1588_CLKIN,
kEXTAL_Clock,
kEXTAL1_Clock,
kUSB_CLKIN,
/* reserved value*/
kReserved,
/* clock name max */
kClockNameCount
} clock_names_t;
/*! @brief Clock gate module names */
typedef enum _clock_gate_module_names {
/* System modules*/
kClockModuleDMA, /**/
kClockModuleDMAMUX, /* instance 0, 1*/
kClockModulePORT, /* instance 0 - 5 (A - F)*/
kClockModuleMPU, /**/
kClockModuleLLWU, /**/
kClockModuleEWM, /**/
/* Clocks*/
kClockModuleOSC1, /**/
/* Memory and memory interfaces*/
kClockModuleFTF, /* Flash memory control clock*/
kClockModuleNFC, /* NAND flash control clock*/
kClockModuleFLEXBUS, /**/
kClockModuleDDR, /**/
/* Security*/
kClockModuleCRC, /**/
kClockModuleRNGA, /**/
kClockModuleREGFILE, /**/
kClockModuleDRYICESECREG, /**/
kClockModuleDRYICE, /**/
/* Analog*/
kClockModuleADC, /* instance 0 - 3*/
kClockModuleCMP, /* */
kClockModuleDAC, /* instance 0, 1*/
kClockModuleVREF, /* */
kClockModuleSAI, /* instance 0, 1*/
/* Timers*/
kClockModuleTPM, /* TPM timers 0 - 2*/
kClockModulePDB, /* */
kClockModuleFTM, /* instance 0 - 3*/
kClockModulePIT, /**/
kClockModuleLPTIMER, /**/
kClockModuleCMT, /**/
kClockModuleRTC, /**/
/* Communication Interfaces*/
kClockModuleENET, /**/
kClockModuleUSBHS, /**/
kClockModuleUSBFS, /**/
kClockModuleUSBDCD, /**/
kClockModuleFLEXCAN, /* instance 0, 1*/
kClockModuleSPI, /* instance 0 - 2*/
kClockModuleI2C, /* instance 0, 1*/
kClockModuleUART, /* instance 0 - 5*/
kClockModuleESDHC, /**/
kClockModuleLPUART, /**/
/* Human-machine Interfaces*/
kClockModuleTSI, /**/
kClockModuleLCDC, /**/
kClockModuleMax
} clock_gate_module_names_t;
/*! @brief Clock source and SEL names */
typedef enum _clock_source_names {
kClockNfcSrc, /* NFCSRC*/
kClockEsdhcSrc, /* ESDHCSRC K70*/
kClockSdhcSrc, /* SDHCSRC K64*/
kClockLcdcSrc, /* LCDCSRC*/
kClockTimeSrc, /* TIMESRC*/
kClockRmiiSrc, /* RMIISRC*/
kClockUsbfSrc, /* USBFSRC K70*/
kClockUsbSrc, /* USBSRC K64, KL25, KV31, and K22*/
kClockUsbhSrc, /* USBHSRC*/
kClockUart0Src, /* UART0SRC*/
kClockTpmSrc, /* TPMSRC*/
kClockOsc32kSel, /* OSC32KSEL*/
kClockUsbfSel, /* USBF_CLKSEL*/
kClockPllfllSel, /* PLLFLLSEL*/
kClockNfcSel, /* NFC_CLKSEL*/
kClockLcdcSel, /* LCDC_CLKSEL*/
kClockTraceSel, /* TRACE_CLKSEL*/
kClockClkoutSel, /* CLKOUTSEL*/
kClockRtcClkoutSel, /* RTCCLKOUTSEL */
kClockSourceMax
} clock_source_names_t;
/* Table of base addresses for instances. */
extern const uint32_t g_simBaseAddr[];
extern const uint32_t g_mcgBaseAddr[];
/*!
* @brief Error code definition for the clock manager APIs
@ -200,49 +83,6 @@ typedef enum _clock_manager_error_code {
extern "C" {
#endif /* __cplusplus*/
/*! @name Clock Gating*/
/*@{*/
/*!
* @brief Enables or disables the clock for a specific clock module.
*
* This function enables/disables the clock for a specified clock module and
* instance. See the clock_gate_module_names_t for supported clock module names
* for a specific function and see the Reference Manual for supported clock module
* name for a specific chip family. Most module drivers call this function
* to gate(disable)/ungate(enable) the clock for a module. However, the application
* can also call this function as needed. Disabling the clock causes the module
* to stop working. See the Reference Manual to properly enable
* and disable the clock for a device module.
*
* @param moduleName Gate control module name defined in clock_gate_module_names_t
* @param instance Instance of the module
* @param enable Enable or disable the clock for the module
* - true: Enable
* - false: Disable
* @return status Error code defined in clock_manager_error_code_t
*/
clock_manager_error_code_t clock_manager_set_gate(clock_gate_module_names_t moduleName,
uint8_t instance, bool enable);
/*!
* @brief Gets the current clock gate status for a specific clock module.
*
* This function returns the current clock gate status for a specific clock
* module. See clock_gate_module_names_t for supported clock module name.
*
* @param moduleName Gate control module name defined in clock_gate_module_names_t
* @param instance Instance of the module
* @param isEnabled Status of the module clock
* - true: Enabled
* - false: Disabled
* @return status Error code defined in clock_manager_error_code_t
*/
clock_manager_error_code_t clock_manager_get_gate(clock_gate_module_names_t moduleName,
uint8_t instance, bool *isEnabled);
/*@}*/
/*! @name Clock Frequencies*/
/*@{*/
@ -252,7 +92,7 @@ clock_manager_error_code_t clock_manager_get_gate(clock_gate_module_names_t modu
* This function checks the current clock configurations and then calculates
* the clock frequency for a specific clock name defined in clock_names_t.
* The MCG must be properly configured before using this function. See
* the Reference Manual for supported clock names for different chip families.
* the reference manual for supported clock names for different chip families.
* The returned value is in Hertz. If it cannot find the clock name
* or the name is not supported for a specific chip family, it returns an
* error.
@ -261,26 +101,84 @@ clock_manager_error_code_t clock_manager_get_gate(clock_gate_module_names_t modu
* @param frequency Returned clock frequency value in Hertz
* @return status Error code defined in clock_manager_error_code_t
*/
clock_manager_error_code_t clock_manager_get_frequency(clock_names_t clockName,
clock_manager_error_code_t CLOCK_SYS_GetFreq(clock_names_t clockName,
uint32_t *frequency);
/*!
* @brief Gets the clock frequency for a specified clock source.
* @brief Sets the clock source setting.
*
* This function gets the specified clock source setting and converts it
* into a clock name. It calls the internal function to get the value
* for that clock name. The returned value is in Hertz.
* If it cannot find the clock source or the source is not supported for the
* specific chip family, it returns an error.
* This function sets the settings for a specified clock source. Each clock
* source has its own clock selection settings. See the chip reference manual for
* clock source detailed settings and the sim_clock_source_names_t
* for clock sources.
*
* @param clockSource Clock source names defined in clock_source_names_t
* @param frequency Returned clock frequency value in Hertz
* @return status Error code defined in clock_manager_error_code_t
* @param clockSource Clock source name defined in sim_clock_source_names_t
* @param setting Setting value
* @return status If the clock source doesn't exist, it returns an error.
*/
clock_manager_error_code_t clock_manager_get_frequency_by_source(
clock_source_names_t clockSource, uint32_t *frequency);
clock_manager_error_code_t CLOCK_SYS_SetSource(clock_source_names_t clockSource,
uint8_t setting);
/*@}*/
/*!
* @brief Gets the clock source setting.
*
* This function gets the settings for a specified clock source. Each clock
* source has its own clock selection settings. See the reference manual for
* clock source detailed settings and the sim_clock_source_names_t
* for clock sources.
*
* @param clockSource Clock source name
* @param setting Current setting for the clock source
* @return status If the clock source doesn't exist, it returns an error.
*/
clock_manager_error_code_t CLOCK_SYS_GetSource(clock_source_names_t clockSource,
uint8_t *setting);
/*!
* @brief Sets the clock divider setting.
*
* This function sets the setting for a specified clock divider. See the
* reference manual for a supported clock divider and value range and the
* sim_clock_divider_names_t for dividers.
*
* @param clockDivider Clock divider name
* @param divider Divider setting
* @return status If the clock divider doesn't exist, it returns an error.
*/
clock_manager_error_code_t CLOCK_SYS_SetDivider(clock_divider_names_t clockDivider,
uint32_t setting);
/*!
* @brief Gets the clock divider setting.
*
* This function gets the setting for a specified clock divider. See the
* reference manual for a supported clock divider and value range and the
* clock_divider_names_t for dividers.
*
* @param clockDivider Clock divider name
* @param divider Divider value pointer
* @return status If the clock divider doesn't exist, it returns an error.
*/
clock_manager_error_code_t CLOCK_SYS_GetDivider(clock_divider_names_t clockDivider,
uint32_t *setting);
/*!
* @brief Sets the clock out dividers setting.
*
* This function sets the setting for all clock out dividers at the same time.
* See the reference manual for a supported clock divider and value range and the
* clock_divider_names_t for clock out dividers.
*
* @param outdiv1 Outdivider1 setting
* @param outdiv2 Outdivider2 setting
* @param outdiv3 Outdivider3 setting
* @param outdiv4 Outdivider4 setting
*/
static inline void CLOCK_SYS_SetOutDividers(uint32_t outdiv1, uint32_t outdiv2,
uint32_t outdiv3, uint32_t outdiv4)
{
CLOCK_HAL_SetOutDividers(g_simBaseAddr[0], outdiv1, outdiv2, outdiv3, outdiv4);
}
#if defined(__cplusplus)
}
@ -288,6 +186,242 @@ clock_manager_error_code_t clock_manager_get_frequency_by_source(
/*! @}*/
/*
* Include the cpu specific clock API header files.
*/
#if (defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || \
defined(CPU_MK02FN64VLF10) || defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10))
#define K02F12810_SERIES
#elif (defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || \
defined(CPU_MK20DN64VMP5) || defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || \
defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || defined(CPU_MK20DX64VLH5) || \
defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \
defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || \
defined(CPU_MK20DN64VFM5) || defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || \
defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || defined(CPU_MK20DX64VFT5) || \
defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \
defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || \
defined(CPU_MK20DN64VLF5) || defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5))
#define K20D5_SERIES
#elif (defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VLL10) || \
defined(CPU_MK22FN128VMP10))
#define K22F12810_SERIES
/* Clock System Level API header file */
#include "MK22F12810/fsl_clock_K22F12810.h"
#elif (defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || \
defined(CPU_MK22FN256VMP12))
#define K22F25612_SERIES
/* Clock System Level API header file */
#include "MK22F25612/fsl_clock_K22F25612.h"
#elif (defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12))
#define K22F51212_SERIES
/* Clock System Level API header file */
#include "MK22F51212/fsl_clock_K22F51212.h"
#elif (defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLQ12))
#define K24F12_SERIES
/* Clock System Level API header file */
#include "MK24F12/fsl_clock_K24F12.h"
#elif (defined(CPU_MK24FN256VDC12))
#define K24F25612_SERIES
#elif (defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12))
#define K63F12_SERIES
/* Clock System Level API header file */
#include "MK63F12/fsl_clock_K63F12.h"
#elif (defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || \
defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || \
defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12))
#define K64F12_SERIES
/* Clock System Level API header file */
#include "MK64F12/fsl_clock_K64F12.h"
#elif (defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || \
defined(CPU_MK65FX1M0VMI18))
#define K65F18_SERIES
#elif (defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || \
defined(CPU_MK66FX1M0VMD18))
#define K66F18_SERIES
#elif (defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || \
defined(CPU_MK70FX512VMF15) || defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || \
defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15))
#define K70F12_SERIES
#elif (defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || \
defined(CPU_MK70FX512VMF15) || defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || \
defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15))
#define K70F15_SERIES
#elif (defined(CPU_MKL02Z32CAF4) || defined(CPU_MKL02Z8VFG4) || defined(CPU_MKL02Z16VFG4) || \
defined(CPU_MKL02Z32VFG4) || defined(CPU_MKL02Z16VFK4) || defined(CPU_MKL02Z32VFK4) || \
defined(CPU_MKL02Z16VFM4) || defined(CPU_MKL02Z32VFM4))
#define KL02Z4_SERIES
#elif (defined(CPU_MKL03Z32CAF4) || defined(CPU_MKL03Z8VFG4) || defined(CPU_MKL03Z16VFG4) || \
defined(CPU_MKL03Z32VFG4) || defined(CPU_MKL03Z8VFK4) || defined(CPU_MKL03Z16VFK4) || \
defined(CPU_MKL03Z32VFK4))
#define KL03Z4_SERIES
#elif (defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || \
defined(CPU_MKL05Z8VLC4) || defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || \
defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || defined(CPU_MKL05Z32VFM4) || \
defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4))
#define KL05Z4_SERIES
#elif (defined(CPU_MKL13Z64VFM4) || defined(CPU_MKL13Z128VFM4) || defined(CPU_MKL13Z256VFM4) || \
defined(CPU_MKL13Z64VFT4) || defined(CPU_MKL13Z128VFT4) || defined(CPU_MKL13Z256VFT4) || \
defined(CPU_MKL13Z64VLH4) || defined(CPU_MKL13Z128VLH4) || defined(CPU_MKL13Z256VLH4) || \
defined(CPU_MKL13Z64VMP4) || defined(CPU_MKL13Z128VMP4) || defined(CPU_MKL13Z256VMP4))
#define KL13Z4_SERIES
#elif (defined(CPU_MKL23Z64VFM4) || defined(CPU_MKL23Z128VFM4) || defined(CPU_MKL23Z256VFM4) || \
defined(CPU_MKL23Z64VFT4) || defined(CPU_MKL23Z128VFT4) || defined(CPU_MKL23Z256VFT4) || \
defined(CPU_MKL23Z64VLH4) || defined(CPU_MKL23Z128VLH4) || defined(CPU_MKL23Z256VLH4) || \
defined(CPU_MKL23Z64VMP4) || defined(CPU_MKL23Z128VMP4) || defined(CPU_MKL23Z256VMP4))
#define KL23Z4_SERIES
#elif (defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || \
defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z128VFT4) || \
defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || \
defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4))
#define KL25Z4_SERIES
/* Clock System Level API header file */
#include "MKL25Z4/fsl_clock_KL25Z4.h"
#elif (defined(CPU_MKL26Z32VFM4) || defined(CPU_MKL26Z64VFM4) || defined(CPU_MKL26Z128VFM4) || \
defined(CPU_MKL26Z32VFT4) || defined(CPU_MKL26Z64VFT4) || defined(CPU_MKL26Z128VFT4) || \
defined(CPU_MKL26Z32VLH4) || defined(CPU_MKL26Z64VLH4) || defined(CPU_MKL26Z128VLH4) || \
defined(CPU_MKL26Z256VLH4) || defined(CPU_MKL26Z256VLK4) || defined(CPU_MKL26Z128VLL4) || \
defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || defined(CPU_MKL26Z256VMC4))
#define KL26Z4_SERIES
#elif (defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || \
defined(CPU_MKL33Z256VMP4))
#define KL33Z4_SERIES
#elif (defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || \
defined(CPU_MKL43Z64VMP4) || defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4))
#define KL43Z4_SERIES
#elif (defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || \
defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4))
#define KL46Z4_SERIES
#elif (defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || defined(CPU_MKV30F128VLF10) || \
defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10))
#define KV30F12810_SERIES
#elif (defined(CPU_MKV31F128VLH10) || defined(CPU_MKV31F128VLL10))
#define KV31F12810_SERIES
/* Clock System Level API header file */
#include "MKV31F12810/fsl_clock_KV31F12810.h"
#elif (defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12))
#define KV31F25612_SERIES
/* Clock System Level API header file */
#include "MKV31F25612/fsl_clock_KV31F25612.h"
#elif (defined(CPU_MKV31F512VLH12) || defined(CPU_MKV31F512VLL12))
#define KV31F51212_SERIES
/* Clock System Level API header file */
#include "MKV31F51212/fsl_clock_KV31F51212.h"
#elif (defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLH15) || \
defined(CPU_MKV40F256VLL15) || defined(CPU_MKV40F64VLH15))
#define KV40F15_SERIES
#elif (defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || defined(CPU_MKV43F64VLH15))
#define KV43F15_SERIES
#elif (defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15))
#define KV44F15_SERIES
#elif (defined(CPU_MKV45F128VLH15) || defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLH15) || \
defined(CPU_MKV45F256VLL15))
#define KV45F15_SERIES
#elif (defined(CPU_MKV46F128VLH15) || defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLH15) || \
defined(CPU_MKV46F256VLL15))
#define KV46F15_SERIES
#else
#error "No valid CPU defined!"
#endif
#endif /* __FSL_CLOCK_MANAGER_H__*/
/*******************************************************************************
* EOF

476
libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/clock/src/fsl_clock_manager.c
View File

@ -1,476 +0,0 @@
/*
* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fsl_device_registers.h"
#include "fsl_sim_hal.h"
#include "fsl_clock_manager.h"
#include "fsl_clock_manager_private.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/* internal function for clock manager. see function header for details */
static clock_manager_error_code_t clock_manager_get_frequency_by_name(sim_clock_names_t clockName,
uint32_t *frequency);
/*******************************************************************************
* Code
******************************************************************************/
/*FUNCTION**********************************************************************
*
* Function Name : clock_manager_get_system_clock
* Description : Internal function to get the system clock frequency
* This function will check the clock name configuration table for specific
* chip family and find out the supported clock name for that chip family
* then it will call the mcg hal function to get the basic system clock,
* calculate the clock frequency for specified clock name.
*
*END**************************************************************************/
clock_manager_error_code_t clock_manager_get_system_clock(sim_clock_names_t clockName,
uint32_t *frequency)
{
/* system clock out divider*/
uint32_t divider;
uint32_t i = 0;
const sim_clock_name_config_t *table = NULL;
/* search through whole name table*/
while (kSimClockNameConfigTable[i].clockName != kSimClockNameCount)
{
/* find only the match with name*/
if (kSimClockNameConfigTable[i].clockName == clockName)
{
/* return the table pointer*/
table = &kSimClockNameConfigTable[i];
break;
}
i++;
}
/* if the configuration table doesn't exist, return error */
if (table == NULL)
{
return kClockManagerNoSuchClockName;
}
/* check if we need to use a reference clock*/
if (table->useOtherRefClock)
{
/* get other specified ref clock*/
if ( kClockManagerSuccess != clock_manager_get_frequency_by_name(table->otherRefClockName,
frequency) )
{
return kClockManagerNoSuchClockName;
}
}
else
{
/* get default ref clock */
*frequency = clock_hal_get_outclk();
}
/* get system clock divider*/
if ( clock_hal_get_clock_divider(table->dividerName, &divider) == kSimHalSuccess)
{
/* get the frequency for the specified clock*/
*frequency = (*frequency) / (divider + 1);
return kClockManagerSuccess;
}
else
{
return kClockManagerNoSuchDivider;
}
}
/*FUNCTION**********************************************************************
*
* Function Name : clock_manager_set_gate
* Description : Enable or disable the clock for specified clock module
* This function will enable/disable the clock for specified clock module and
* instance. Refer to clock_gate_module_names_t for supported clock module name
* by this function and refer to reference manual for supported clock moulde
* name for a specified chip family. Most module driver will call this function
* to gate(disable)/ungate(enable) the clock for that module, but application
* can also call this function as needed. Disable the clock will make the module
* stop working. Refer to the reference maunal for proper procedure of enalbing
* and disabling the clock for the device module.
*
*END**************************************************************************/
clock_manager_error_code_t clock_manager_set_gate(clock_gate_module_names_t moduleName,
uint8_t instance, bool enable)
{
/* calling hal api, to set(Enable/Disable) the clock module gate */
if (clock_hal_set_gate(kClockModuleNameSimMap[moduleName], instance, enable) == kSimHalSuccess)
{
return kClockManagerSuccess;
}
else
{
return kClockManagerNoSuchClockModule;
}
}
/*FUNCTION**********************************************************************
*
* Function Name : clock_manager_get_gate
* Description : Get the current clock gate status for specified clock module
* This function will return the current clock gate status for specified clock
* module. Refer to clock_gate_module_names_t for supported clock module name.
*
*END**************************************************************************/
clock_manager_error_code_t clock_manager_get_gate(clock_gate_module_names_t moduleName,
uint8_t instance, bool *isEnabled)
{
/* calling the hal function to get the clock module gate status */
if (clock_hal_get_gate(kClockModuleNameSimMap[moduleName], instance, isEnabled)
== kSimHalSuccess)
{
return kClockManagerSuccess;
}
else
{
return kClockManagerNoSuchClockModule;
}
}
/*FUNCTION**********************************************************************
*
* Function Name : clock_manager_get_frequency
* Description : Get the clock frequency for specified clock name
* This function will check the current clock configurations and then calculate
* the clock frequency for specified clock name defined in clock_names_t.
* The MCG must be properly configured before using this function. Also check
* the reference manual for supported clock names on different chip falmily.
* The returned value will be in herz. And if it cannot find the clock name
* or the name is not supported on specific chip family, it will return an
* error.
*
*END**************************************************************************/
clock_manager_error_code_t clock_manager_get_frequency(clock_names_t clockName,
uint32_t *frequency)
{
/* convert clock manager clock name to sim clock name */
sim_clock_names_t simClockName = kClockNameSimMap[clockName];
/* calling internal get frequency by name function */
return clock_manager_get_frequency_by_name(simClockName, frequency);
}
/*FUNCTION**********************************************************************
*
* Function Name : clock_manager_get_frequency_by_name
* Description : Internal function to get the frequency by clock name
* This function will get/calculate the clock frequency based on clock name
* and current configuration of clock generator.
*
*END**************************************************************************/
clock_manager_error_code_t static clock_manager_get_frequency_by_name(sim_clock_names_t clockName,
uint32_t *frequency)
{
/* branch according to clock name */
switch(clockName)
{
/* osc clock*/
case kSimOsc32kClock:
/* *frequency = CPU_XTAL32k_CLK_HZ; // or should provided by osc module??*/
*frequency = 32768;
break;
case kSimOsc0ErClock:
/* *frequency = CPU_XTAL_CLK_HZ; // or should provided by osc module??*/
*frequency = 80000; /* for testing purpose only*/
break;
case kSimOsc1ErClock:
/* *frequency = CPU_XTAL_CLK_HZ; // or should provided by osc module??*/
*frequency = 80001; /* for testing purpose only*/
break;
/* irc clock*/
case kSimIrc48mClock:
/* *frequency = CPU_INT_IRC_CLK_HZ; // or should provided by irc module??*/
*frequency = 48000;
break;
/* rtc clock*/
case kSimRtc32kClock:
/* *frequency = CPU_XTAL32k_CLK_HZ; // or should provided by rtc module??*/
*frequency = 32768;
break;
case kSimRtc1hzClock:
/* *frequency = CPU_XTAL1hz_CLK_HZ; // or should provided by rtc module??*/
*frequency = 1;
break;
/* lpo clcok*/
case kSimLpoClock:
/* *frequency = 1000; // where should we define this constant??*/
*frequency = 1000;
break;
/* mcg clocks, calling mcg clock functions */
case kSimMcgFllClock:
*frequency = clock_hal_get_fllclk();
break;
case kSimMcgPll0Clock:
*frequency = clock_hal_get_pll0clk();
break;
case kSimMcgOutClock:
*frequency = clock_hal_get_outclk();
break;
case kSimMcgIrClock:
*frequency = clock_hal_get_irclk();
break;
/* constant clocks (provided in other header files - TBD)*/
case kSimSDHC0_CLKIN:
*frequency = 11111; /* for testing use purpose*/
break;
case kSimENET_1588_CLKIN:
*frequency = 22222; /* for testing use purpose*/
break;
case kSimEXTAL_Clock:
/* *frequency = CPU_XTAL_CLK_HZ; // is this correct??*/
*frequency = 33333; /* for testing use purpose*/
break;
case kSimEXTAL1_Clock:
/* *frequency = CPU_XTAL_CLK_HZ; // is this correct??*/
*frequency = 33334; /* for testing use purpose*/
break;
case kSimUSB_CLKIN:
*frequency = 44444; /* for testing use purpose*/
break;
/* system clocks */
case kSimCoreClock:
case kSimSystemClock:
case kSimPlatformClock:
case kSimBusClock:
case kSimFlexBusClock:
case kSimFlashClock:
return clock_manager_get_system_clock(clockName, frequency);
/* reserved value*/
case kSimReserved:
default:
*frequency = 55555; /* for testing use purpose*/
return kClockManagerNoSuchClockName;
}
return kClockManagerSuccess;
}
/*FUNCTION**********************************************************************
*
* Function Name : clock_manager_get_frequency_by_source
* Description : Get the clock frequency for specified clock source
* This function will get the specified clock source setting and convert it
* into a clock name, then calling the internal function to find out the value
* for that clock name. Also the returned value is in herz.
* If it cannot find the clock source or the source is not supported on the
* specific chip family, it will return an error.
*
*END**************************************************************************/
clock_manager_error_code_t clock_manager_get_frequency_by_source(clock_source_names_t clockSource,
uint32_t *frequency)
{
uint8_t setting;
uint8_t subsetting1;
uint8_t subsetting2;
uint32_t frac = 0;
uint32_t divider = 0;
sim_clock_names_t simClockName;
sim_clock_source_names_t simClockSource;
sim_clock_divider_names_t dividerName;
const sim_clock_source_value_t *valueTable = NULL;
const sim_clock_source_value_t *subValueTable1 = NULL;
const sim_clock_source_value_t *subValueTable2 = NULL;
assert (clockSource < kClockSourceMax);
/* convert clock manager clock source to sim clock source*/
simClockSource = kClockSourceNameSimMap[clockSource];
/* check to see if we need to use clock sel for specified clock source (see if CLKSEL exists)*/
switch (simClockSource)
{
case kSimClockNfcSrc: /* NFCSRC*/
simClockSource = kSimClockNfcSel;
break;
case kSimClockLcdcSrc: /* LCDCSRC*/
simClockSource = kSimClockLcdcSel;
break;
case kSimClockUsbfSrc: /* USBFSRC K70*/
simClockSource = kSimClockUsbfSel;
break;
default:
break;
}
/* get the sim clock source setting*/
if (clock_hal_get_clock_source(simClockSource, &setting) != kSimHalSuccess)
{
return kClockManagerNoSuchClockSource;
}
/* get the value index table for the clock source*/
valueTable = kSimClockSourceValueTable[simClockSource];
/* if the source exists*/
if (valueTable == NULL)
{
return kClockManagerNoSuchClockSource;
}
/* check if it is a clock name or selection*/
if (valueTable[setting].isSel)
{
/* if it is a selection, then convert the selection into a clock name*/
/* get the config table for the clock source*/
if (clock_hal_get_clock_source(valueTable[setting].clockSelName, &subsetting1)
!= kSimHalSuccess)
{
return kClockManagerNoSuchClockSource;
}
/* get the value index table for the clock source*/
subValueTable1 = kSimClockSourceValueTable[valueTable[setting].clockSelName];
/* check if there's bad data*/
if (subValueTable1 == NULL)
{
return kClockManagerNoSuchClockSource;
}
/* check if there's further clock select*/
if (subValueTable1[subsetting1].isSel)
{
/* if it is a selection, then convert the selection into a clock name*/
/* get the config table for the clock source*/
if (clock_hal_get_clock_source(subValueTable1[subsetting1].clockSelName, &subsetting2)
!= kSimHalSuccess)
{
return kClockManagerNoSuchClockSource;
}
/* get the value index table for the clock source*/
subValueTable2 = kSimClockSourceValueTable[subValueTable1[subsetting1].clockSelName];
/* check if there's bad data*/
if (subValueTable2 == NULL)
{
return kClockManagerNoSuchClockSource;
}
/* further convert the subvalue to clock name */
simClockName = subValueTable2[subsetting2].clockName;
}
else
{
/* further convert the subvalue to clock name */
simClockName = subValueTable1[subsetting1].clockName;
}
}
else
{
/* convert the value to clock name */
simClockName = valueTable[setting].clockName;
}
/* get/calculate the frequency for the specified clock name*/
if ( clock_manager_get_frequency_by_name(simClockName, frequency) != kClockManagerSuccess)
{
return kClockManagerNoSuchClockName;
}
/* find the first available divider*/
if (valueTable[setting].hasDivider)
{
/* get the diviver name */
dividerName = valueTable[setting].dividerName;
}
else if ((subValueTable1 != NULL) && (subValueTable1[subsetting1].hasDivider))
{
/* get the diviver name */
dividerName = subValueTable1[subsetting1].dividerName;
}
else if ((subValueTable2 != NULL) && (subValueTable2[subsetting2].hasDivider))
{
/* get the diviver name */
dividerName = subValueTable2[subsetting2].dividerName;
}
else
{
return kClockManagerSuccess;
}
/* get the divider value*/
switch (dividerName)
{
case kSimClockDividerNfcDiv: /* NFCSRC*/
clock_hal_get_clock_divider(kSimClockDividerNfcDiv, &divider);
clock_hal_get_clock_divider(kSimClockDividerNfcFrac, &frac);
break;
case kSimClockDividerLcdcDiv: /* LCDCSRC*/
clock_hal_get_clock_divider(kSimClockDividerLcdcDiv, &divider);
clock_hal_get_clock_divider(kSimClockDividerLcdcFrac, &frac);
break;
case kSimClockDividerUsbfsDiv: /* USBFSRC K70*/
clock_hal_get_clock_divider(kSimClockDividerUsbfsDiv, &divider);
clock_hal_get_clock_divider(kSimClockDividerUsbfsFrac, &frac);
break;
case kSimClockDividerUsbDiv: /* USBSRC K64, KL25, KV31, and K22*/
clock_hal_get_clock_divider(kSimClockDividerUsbDiv, &divider);
clock_hal_get_clock_divider(kSimClockDividerUsbFrac, &frac);
break;
case kSimClockDividerUsbhsDiv: /* USBHSRC K70*/
clock_hal_get_clock_divider(kSimClockDividerUsbhsDiv, &divider);
clock_hal_get_clock_divider(kSimClockDividerUsbhsFrac, &frac);
break;
case kSimClockDividerSpecial1: /* Special KL25 divider 2*/
clock_hal_get_clock_divider(kSimClockDividerSpecial1, &divider);
break;
default:
break;
}
/* Divider output clock = Divider input clock × [ (USBFRAC+1) / (USBDIV+1) ]*/
*frequency = (*frequency) * (frac + 1) / (divider + 1);
return kClockManagerSuccess;
}
/*******************************************************************************
* EOF
******************************************************************************/

234
libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/clock/src/fsl_clock_manager_private.h
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@ -1,234 +0,0 @@
/*
* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#if !defined(__FSL_CLOCK_MANAGER_PRIVATE_H__)
#define __FSL_CLOCK_MANAGER_PRIVATE_H__
#include <stdint.h>
#include <stdbool.h>
#include <assert.h>
/*! @addtogroup clock_manager*/
/*! @{*/
/*! @file*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @brief Clock manager clock names mapping into the SIM clock name*/
sim_clock_names_t kClockNameSimMap[kClockNameCount] = {
/* default clocks*/
kSimCoreClock, /**/
kSimSystemClock, /**/
kSimPlatformClock, /**/
kSimBusClock, /**/
kSimFlexBusClock, /**/
kSimFlashClock, /**/
/* other internal clocks used by peripherals*/
/* osc clock*/
kSimOsc32kClock,
kSimOsc0ErClock,
kSimOsc1ErClock,
/* irc 48Mhz clock */
kSimIrc48mClock,
/* rtc clock*/
kSimRtc32kClock,
kSimRtc1hzClock,
/* lpo clcok*/
kSimLpoClock,
/* mcg clocks*/
kSimMcgFllClock,
kSimMcgPll0Clock,
kSimMcgPll1Clock,
kSimMcgOutClock,
kSimMcgIrClock,
/* constant clocks (provided in other header files?)*/
kSimSDHC0_CLKIN,
kSimENET_1588_CLKIN,
kSimEXTAL_Clock,
kSimEXTAL1_Clock,
kSimUSB_CLKIN,
/* reserved value*/
kSimReserved
};
/*! @brief Clock manager clock source names mapping into the SIM clock source name*/
sim_clock_source_names_t kClockSourceNameSimMap[kClockSourceMax] = {
kSimClockNfcSrc, /* NFCSRC*/
kSimClockEsdhcSrc, /* ESDHCSRC K70*/
kSimClockSdhcSrc, /* SDHCSRC K64*/
kSimClockLcdcSrc, /* LCDCSRC*/
kSimClockTimeSrc, /* TIMESRC*/
kSimClockRmiiSrc, /* RMIISRC*/
kSimClockUsbfSrc, /* USBFSRC K70*/
kSimClockUsbSrc, /* USBSRC K64, KL25, KV31, and K22*/
kSimClockUsbhSrc, /* USBHSRC*/
kSimClockUart0Src, /* UART0SRC*/
kSimClockTpmSrc, /* TPMSRC*/
kSimClockOsc32kSel, /* OSC32KSEL*/
kSimClockUsbfSel, /* USBF_CLKSEL*/
kSimClockPllfllSel, /* PLLFLLSEL*/
kSimClockNfcSel, /* NFC_CLKSEL*/
kSimClockLcdcSel, /* LCDC_CLKSEL*/
kSimClockTraceSel, /* TRACE_CLKSEL*/
kSimClockClkoutSel, /* CLKOUTSEL*/
kSimClockRtcClkoutSel /* RTCCLKOUTSEL */
};
/*! @brief Clock manager clock module names mapping into the SIM clock module name*/
sim_clock_gate_module_names_t kClockModuleNameSimMap[kClockModuleMax] = {
/* System modules*/
kSimClockModuleDMA, /**/
kSimClockModuleDMAMUX, /* instance 0, 1*/
kSimClockModulePORT, /* instance 0 - 5 (A - F)*/
kSimClockModuleMPU, /**/
kSimClockModuleLLWU, /**/
kSimClockModuleEWM, /**/
/* Clocks*/
kSimClockModuleOSC1, /**/
/* Memory and memory interfaces*/
kSimClockModuleFTF, /* Flash memory control clock*/
kSimClockModuleNFC, /* NAND flash control clock*/
kSimClockModuleFLEXBUS, /**/
kSimClockModuleDDR, /**/
/* Security*/
kSimClockModuleCRC, /**/
kSimClockModuleRNGA, /**/
kSimClockModuleREGFILE, /**/
kSimClockModuleDRYICESECREG, /**/
kSimClockModuleDRYICE, /**/
/* Analog*/
kSimClockModuleADC, /* instance 0 - 3*/
kSimClockModuleCMP, /* */
kSimClockModuleDAC, /* instance 0, 1*/
kSimClockModuleVREF, /* */
kSimClockModuleSAI, /* instance 0, 1*/
/* Timers*/
kSimClockModuleTPM, /* TPM timers 0 - 2*/
kSimClockModulePDB, /* */
kSimClockModuleFTM, /* instance 0 - 3*/
kSimClockModulePIT, /**/
kSimClockModuleLPTIMER, /**/
kSimClockModuleCMT, /**/
kSimClockModuleRTC, /**/
/* Communication Interfaces*/
kSimClockModuleENET, /**/
kSimClockModuleUSBHS, /**/
kSimClockModuleUSBFS, /**/
kSimClockModuleUSBDCD, /**/
kSimClockModuleFLEXCAN, /* instance 0, 1*/
kSimClockModuleSPI, /* instance 0 - 2*/
kSimClockModuleI2C, /* instance 0, 1*/
kSimClockModuleUART, /* instance 0 - 5*/
kSimClockModuleESDHC, /**/
kSimClockModuleLPUART, /**/
/* Human-machine Interfaces*/
kSimClockModuleTSI, /**/
kSimClockModuleLCDC /**/
};
extern const sim_clock_source_value_t *kSimClockSourceValueTable[];
/*******************************************************************************
* API
******************************************************************************/
/*! @name System out clock access API*/
/*@{*/
/*!
* @brief Gets the current out clock.
*
* @param none
*
* @return frequency Out clock frequency for the clock system
*/
extern uint32_t clock_hal_get_outclk(void);
/*!
* @brief Gets the current FLL clock.
*
* @param none
*
* @return frequency FLL clock frequency for the clock system
*/
extern uint32_t clock_hal_get_fllclk(void);
/*!
* @brief Gets the current PLL0 clock.
*
* @param none
*
* @return frequency PLL0 clock frequency for the clock system
*/
extern uint32_t clock_hal_get_pll0clk(void);
/*!
* @brief Gets the current PLL1 clock.
*
* @param none
*
* @return frequency PLL1 clock frequency for the clock system
*/
extern uint32_t clock_hal_get_pll1clk(void);
/*!
* @brief Get the current IR (internal reference) clock.
*
* @param none
*
* @return frequency IR clock frequency for the clock system
*/
extern uint32_t clock_hal_get_irclk(void);
/*@}*/
/*! @}*/
#endif /* __FSL_CLOCK_MANAGER_PRIVATE_H__*/
/*******************************************************************************
* EOF
******************************************************************************/

7
libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/enet/fsl_enet_driver.h
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@ -34,7 +34,10 @@
#include <stdbool.h>
#include "fsl_enet_hal.h"
#include "fsl_os_abstraction.h"
/*!
#ifndef MBED_NO_ENET
/*!
* @addtogroup enet_driver
* @{
*/
@ -938,6 +941,8 @@ void *enet_mac_dequeue_buffer( void **queue);
extern }
#endif
#endif
/*! @}*/
#endif /* __FSL_ENET_DRIVER_H__ */

69
libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/enet/fsl_enet_irq.c Normal file
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@ -0,0 +1,69 @@
/*
* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fsl_enet_driver.h"
#include "fsl_clock_manager.h"
#ifndef MBED_NO_ENET
/*******************************************************************************
* Variables
******************************************************************************/
#define ENET_INSTANCE 0U
/*******************************************************************************
* Code
******************************************************************************/
#if defined (K64F12_SERIES) || defined (K70F12_SERIES) || defined (K63F12_SERIES)
void ENET_Transmit_IRQHandler(void)
{
ENET_DRV_TxIRQHandler(ENET_INSTANCE);
}
void ENET_Receive_IRQHandler(void)
{
ENET_DRV_RxIRQHandler(ENET_INSTANCE);
}
#if FSL_FEATURE_ENET_SUPPORT_PTP
void ENET_1588_Timer_IRQHandler(void)
{
ENET_DRV_TsIRQHandler(ENET_INSTANCE);
}
#endif
#endif
#endif /* MBED_NO_ENET */
/*******************************************************************************
* EOF
******************************************************************************/

513
libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/enet/fsl_enet_rtcs_adapter.h Normal file
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@ -0,0 +1,513 @@
/*
* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __FSL_ENET_RTCS_ADAPTOR_H__
#define __FSL_ENET_RTCS_ADAPTOR_H__
#include "fsl_enet_hal.h"
#ifndef MBED_NO_ENET
#ifdef FSL_RTOS_MQX
#include "rtcs.h"
#include "pcb.h"
#endif
/*!
* @addtogroup enet_rtcs_adaptor
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @brief Definitions of the task parameter*/
#ifndef FSL_RTOS_MQX
extern unsigned long _RTCSTASK_priority;
#endif
#define ENET_RECEIVE_TASK_PRIO (1)
#define ENET_TASK_STACK_SIZE (800)
#define ENET_PCB_NUM (16)
/*! @brief Definitions of the configuration parameter*/
#define ENET_RXBD_NUM (8)
#define ENET_TXBD_NUM (4)
#define ENET_EXTRXBD_NUM (4)
#define ENET_RXBuff_SIZE (kEnetMaxFrameSize)
#define ENET_TXBuff_SIZE (kEnetMaxFrameSize)
#define ENET_RXRTCSBUFF_NUM (8)
#define ENET_RX_BUFFER_ALIGNMENT (16)
#define ENET_TX_BUFFER_ALIGNMENT (16)
#define ENET_BD_ALIGNMENT (16)
#define ENET_RXBuffSizeAlign(n) ENET_ALIGN(n, ENET_RX_BUFFER_ALIGNMENT)
#define ENET_TXBuffSizeAlign(n) ENET_ALIGN(n, ENET_TX_BUFFER_ALIGNMENT)
#define ENET_MII_CLOCK (2500000L)
#if FSL_FEATURE_ENET_SUPPORT_PTP
#define ENET_PTP_TXTS_RING_LEN (25)
#define ENET_PTP_RXTS_RING_LEN (25)
#endif
/*! @brief Definitions of the error codes */
#define ENET_OK (0)
#define ENET_ERROR (0xff) /* General ENET error */
#define ENETERR_INVALID_DEVICE (kStatus_ENET_InvalidDevice) /* Device number out of range */
#define ENETERR_INIT_DEVICE (kStatus_ENET_Initialized) /* Device already initialized */
/*! @brief Definitions of the ENET protocol parameter*/
#define ENETPROT_IP 0x0800
#define ENETPROT_ARP 0x0806
#define ENETPROT_8021Q 0x8100
#define ENETPROT_IP6 0x86DD
#define ENETPROT_ETHERNET 0x88F7
#define ENET_OPT_8023 0x0001
#define ENET_OPT_8021QTAG 0x0002
#define ENET_SETOPT_8021QPRIO(p) (ENET_OPT_8021QTAG | (((uint_32)(p) & 0x7) << 2))
#define ENET_GETOPT_8021QPRIO(f) ((((unsigned int)f) >> 2) & 0x7)
/*! @brief Definitions of the ENET option macro*/
#define ENET_OPTION_HW_TX_IP_CHECKSUM 0x00001000
#define ENET_OPTION_HW_TX_PROTOCOL_CHECKSUM 0x00002000
#define ENET_OPTION_HW_RX_IP_CHECKSUM 0x00004000
#define ENET_OPTION_HW_RX_PROTOCOL_CHECKSUM 0x00008000
#define ENET_OPTION_HW_RX_MAC_ERR 0x00010000
/*! @brief Definitions of the ENET default Mac*/
#define ENET_DEFAULT_MAC_ADD { 0x00, 0x00, 0x5E, 0, 0, 0 }
#define PCB_MINIMUM_SIZE (sizeof(PCB2))
#define PCB_free(pcb_ptr) ((pcb_ptr)->FREE(pcb_ptr))
/*! @brief Definitions of the macro for byte-swap*/
#if SYSTEM_LITTLE_ENDIAN
#define RTCS_HTONS(n) BSWAP_16(n)
#define RTCS_HTONL(n) BSWAP_32(n)
#define RTCS_NTOHS(n) BSWAP_16(n)
#define RTCS_NTOHL(n) BSWAP_32(n)
#else
#define RTCS_HTONS(n) (n)
#define RTCS_HTONL(n) (n)
#define RTCS_NTOHS(n) (n)
#define RTCS_NTOHL(n) (n)
#endif
#ifndef FSL_RTOS_MQX
#define htonl(p,x) (((uint_8_ptr)(p))[0] = ((x) >> 24) & 0xFF, \
((uint_8_ptr)(p))[1] = ((x) >> 16) & 0xFF, \
((uint_8_ptr)(p))[2] = ((x) >> 8) & 0xFF, \
((uint_8_ptr)(p))[3] = (x) & 0xFF, \
(x))
#define htons(p,x) (((uint_8_ptr)(p))[0] = ((x) >> 8) & 0xFF, \
((uint_8_ptr)(p))[1] = (x) & 0xFF, \
(x))
#define htonc(p,x) (((uint_8_ptr)(p))[0] = (x) & 0xFF, \
(x))
#define ntohl(p) (\
(((uint_32)(((uint_8_ptr)(p))[0])) << 24) | \
(((uint_32)(((uint_8_ptr)(p))[1])) << 16) | \
(((uint_32)(((uint_8_ptr)(p))[2])) << 8) | \
( (uint_32)(((uint_8_ptr)(p))[3])) \
)
#define ntohs(p) (\
(((uint_16)(((uint_8_ptr)(p))[0])) << 8) | \
( (uint_16)(((uint_8_ptr)(p))[1])) \
)
#define ntohc(p) ((uint_8)(((uint_8_ptr)(p))[0]))
#endif
#define htone(p,x) ((p)[0] = (x)[0], \
(p)[1] = (x)[1], \
(p)[2] = (x)[2], \
(p)[3] = (x)[3], \
(p)[4] = (x)[4], \
(p)[5] = (x)[5] \
)
#define ntohe(p,x) ((x)[0] = (p)[0] & 0xFF, \
(x)[1] = (p)[1] & 0xFF, \
(x)[2] = (p)[2] & 0xFF, \
(x)[3] = (p)[3] & 0xFF, \
(x)[4] = (p)[4] & 0xFF, \
(x)[5] = (p)[5] & 0xFF \
)
/*! @brief Definitions of the add to queue*/
#define QUEUEADD(head,tail,pcb) \
if ((head) == NULL) { \
(head) = (pcb); \
} else { \
(tail)->PRIVATE = (pcb); \
} \
(tail) = (pcb); \
(pcb)->PRIVATE = NULL
/*! @brief Definitions of the get from queue*/
#define QUEUEGET(head,tail,pcb) \
(pcb) = (head); \
if (head) { \
(head) = (head)->PRIVATE; \
if ((head) == NULL) { \
(tail) = NULL; \
} \
}
/*! @brief Definition for ENET six-byte Mac type*/
typedef unsigned char _enet_address[6];
/*! @brief Definition of the IPCFG structure*/
typedef void * _enet_handle;
#ifndef FSL_RTOS_MQX
struct pcb;
typedef void (* PCB_FREE_FPTR)(struct pcb *);
#endif
/*! @brief Definition of the Ethernet packet header structure*/
typedef struct enet_header
{
_enet_address DEST; /*!< destination Mac address*/
_enet_address SOURCE; /*!< source Mac address*/
unsigned char TYPE[2]; /*!< protocol type*/
} ENET_HEADER, * ENET_HEADER_PTR;
#ifndef FSL_RTOS_MQX
/*! @brief Definition of the fragment PCB structure*/
typedef struct pcb_fragment
{
uint32_t LENGTH; /*!< Packet fragment length*/
unsigned char *FRAGMENT; /*!< brief Pointer to fragment*/
} PCB_FRAGMENT, * PCB_FRAGMENT_PTR;
/*! @brief Definition of the PCB structure for the RTCS adaptor*/
typedef struct pcb
{
PCB_FREE_FPTR FREE; /*!< Function that frees PCB*/
void *PRIVATE; /*!< Private PCB information*/
PCB_FRAGMENT FRAG[1]; /*!< Pointer to PCB fragment*/
} PCB, * PCB_PTR;
/*! @brief Definition of the two fragment PCB structure*/
typedef struct pcb2
{
PCB_FREE_FPTR FREE; /*!< Function that frees PCB*/
void *PRIVATE; /*!< Private PCB information*/
PCB_FRAGMENT FRAG[2]; /*!< Pointers to two PCB fragments*/
} PCB2, *PCB2_PTR;
#endif
/*! @brief Definition of the two fragment PCB structure*/
typedef struct pcb_queue
{
PCB *pcbHead; /*!< PCB buffer head*/
PCB *pcbTail; /*!< PCB buffer tail*/
}pcb_queue;
/*! @brief Definition of the ECB structure, which contains the protocol type and it's related service function*/
typedef struct ENETEcbStruct
{
uint16_t TYPE;
void (* SERVICE)(PCB_PTR, void *);
void *PRIVATE;
struct ENETEcbStruct *NEXT;
} enet_ecb_struct_t;
/*! @brief Definition of the 8022 header*/
typedef struct enet_8022_header
{
uint8_t dsap[1]; /*!< DSAP region*/
uint8_t ssap[1]; /*!< SSAP region*/
uint8_t command[1]; /*!< Command region*/
uint8_t oui[3]; /*!< OUI region*/
uint16_t type; /*!< type region*/
}enet_8022_header_t, *enet_8022_header_ptr;
/*! @brief Definition of the common status structure*/
typedef struct enet_commom_stats_struct {
uint32_t ST_RX_TOTAL; /*!< Total number of received packets*/
uint32_t ST_RX_MISSED; /*!< Number of missed packets*/
uint32_t ST_RX_DISCARDED; /*!< Discarded a protocol that was not recognized*/
uint32_t ST_RX_ERRORS; /*!< Discarded error during reception*/
uint32_t ST_TX_TOTAL; /*!< Total number of transmitted packets*/
uint32_t ST_TX_MISSED; /*!< Discarded transmit ring full*/
uint32_t ST_TX_DISCARDED; /*!< Discarded bad packet*/
uint32_t ST_TX_ERRORS; /*!< Error during transmission*/
} ENET_COMMON_STATS_STRUCT, * ENET_COMMON_STATS_STRUCT_PTR;
typedef struct enet_stats {
ENET_COMMON_STATS_STRUCT COMMON; /*!< Common status structure*/
uint32_t ST_RX_ALIGN; /*!< Frame Alignment error*/
uint32_t ST_RX_FCS; /*!< CRC error */
uint32_t ST_RX_RUNT; /*!< Runt packet received */
uint32_t ST_RX_GIANT; /*!< Giant packet received*/
uint32_t ST_RX_LATECOLL; /*!< Late collision */
uint32_t ST_RX_OVERRUN; /*!< DMA overrun*/
uint32_t ST_TX_SQE; /*!< Heartbeat lost*/
uint32_t ST_TX_DEFERRED; /*!< Transmission deferred*/
uint32_t ST_TX_LATECOLL; /*!< Late collision*/
uint32_t ST_TX_EXCESSCOLL; /*!< Excessive collisions*/
uint32_t ST_TX_CARRIER; /*!< Carrier sense lost*/
uint32_t ST_TX_UNDERRUN; /*!< DMA underrun*/
/* Following stats are collected by the Ethernet driver */
uint32_t ST_RX_COPY_SMALL; /*!< Driver had to copy packet */
uint32_t ST_RX_COPY_LARGE; /*!< Driver had to copy packet */
uint32_t ST_TX_COPY_SMALL; /*!< Driver had to copy packet */
uint32_t ST_TX_COPY_LARGE; /*!< Driver had to copy packet */
uint32_t RX_FRAGS_EXCEEDED;
uint32_t RX_PCBS_EXHAUSTED;
uint32_t RX_LARGE_BUFFERS_EXHAUSTED;
uint32_t TX_ALIGNED;
uint32_t TX_ALL_ALIGNED;
#if BSPCFG_ENABLE_ENET_HISTOGRAM
uint32_t RX_HISTOGRAM[ENET_HISTOGRAM_ENTRIES];
uint32_t TX_HISTOGRAM[ENET_HISTOGRAM_ENTRIES];
#endif
} ENET_STATS, * ENET_STATS_PTR;
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @name ENET RTCS ADAPTOR
* @{
*/
/*!
* @brief Initializes the ENET device.
*
* @param device The ENET device number.
* @param address The hardware address.
* @param flag The flag for upper layer.
* @param handle The address pointer for ENET device structure.
* @return The execution status.
*/
uint32_t ENET_initialize(uint32_t device, _enet_address address,uint32_t flag, _enet_handle *handle);
/*!
* @brief Opens the ENET device.
*
* @param handle The address pointer for ENET device structure.
* @param type The ENET protocol type.
* @param service The service function for type.
* @param private The private data for ENET device.
* @return The execution status.
*/
uint32_t ENET_open(_enet_handle handle, uint16_t type, void (* service)(PCB_PTR, void *), void *private);
/*!
* @brief Shuts down the ENET device.
*
* @param handle The address pointer for ENET device structure.
* @return The execution status.
*/
uint32_t ENET_shutdown(_enet_handle handle);
#if !ENET_RECEIVE_ALL_INTERRUPT
/*!
* @brief ENET frame receive.
*
* @param enetIfPtr The address pointer for ENET device structure.
*/
static void ENET_receive(task_param_t param);
#endif
/*!
* @brief ENET frame transmit.
*
* @param handle The address pointer for ENET device structure.
* @param packet The ENET packet buffer.
* @param type The ENET protocol type.
* @param dest The destination hardware address.
* @param flag The flag for upper layer.
* @return The execution status.
*/
uint32_t ENET_send(_enet_handle handle, PCB_PTR packet, uint32_t type, _enet_address dest, uint32_t flags) ;
/*!
* @brief The ENET gets the address with the initialized device.
*
* @param handle The address pointer for ENET device structure.
* @param address The destination hardware address.
* @return The execution status.
*/
uint32_t ENET_get_address(_enet_handle handle, _enet_address address);
/*!
* @brief The ENET gets the address with an uninitialized device.
*
* @param handle The address pointer for ENET device structure.
* @param value The value to change the last three bytes of hardware.
* @param address The destination hardware address.
* @return True if the execution status is success else false.
*/
uint32_t ENET_get_mac_address(uint32_t device, uint32_t value, _enet_address address);
/*!
* @brief The ENET joins a multicast group address.
*
* @param handle The address pointer for ENET device structure.
* @param type The ENET protocol type.
* @param address The destination hardware address.
* @return The execution status.
*/
uint32_t ENET_join(_enet_handle handle, uint16_t type, _enet_address address);
/*!
* @brief The ENET leaves a multicast group address.
*
* @param handle The address pointer for ENET device structure.
* @param type The ENET protocol type.
* @param address The destination hardware address.
* @return The execution status.
*/
uint32_t ENET_leave(_enet_handle handle, uint16_t type, _enet_address address);
#if BSPCFG_ENABLE_ENET_STATS
/*!
* @brief The ENET gets the packet statistic.
*
* @param handle The address pointer for ENET device structure.
* @return The statistic.
*/
ENET_STATS_PTR ENET_get_stats(_enet_handle handle);
#endif
/*!
* @brief The ENET gets the link status.
*
* @param handle The address pointer for ENET device structure.
* @return The link status.
*/
bool ENET_link_status(_enet_handle handle);
/*!
* @brief The ENET gets the link speed.
*
* @param handle The address pointer for ENET device structure.
* @return The link speed.
*/
uint32_t ENET_get_speed(_enet_handle handle);
/*!
* @brief The ENET gets the MTU.
*
* @param handle The address pointer for ENET device structure.
* @return The link MTU
*/
uint32_t ENET_get_MTU(_enet_handle handle);
/*!
* @brief Gets the ENET PHY registers.
*
* @param handle The address pointer for ENET device structure.
* @param numRegs The number of registers.
* @param regPtr The buffer for data read from PHY registers.
* @return True if all numRegs registers are read succeed else false.
*/
bool ENET_phy_registers(_enet_handle handle, uint32_t numRegs, uint32_t *regPtr);
/*!
* @brief Gets ENET options.
*
* @param handle The address pointer for ENET device structure.
* @return ENET options.
*/
uint32_t ENET_get_options(_enet_handle handle);
/*!
* @brief Unregisters a protocol type on an Ethernet channel.
*
* @param handle The address pointer for ENET device structure.
* @return ENET options.
*/
uint32_t ENET_close(_enet_handle handle, uint16_t type);
/*!
* @brief ENET mediactl.
*
* @param handle The address pointer for ENET device structure.
* @param The command ID.
* @param The buffer for input or output parameters.
* @return ENET options.
*/
uint32_t ENET_mediactl(_enet_handle handle, uint32_t commandId, void *inOutParam);
/*!
* @brief Gets the next ENET device handle address.
*
* @param handle The address pointer for ENET device structure.
* @return The address of next ENET device handle.
*/
_enet_handle ENET_get_next_device_handle(_enet_handle handle);
/*!
* @brief ENET free.
*
* @param packet The buffer address.
*/
void ENET_free(PCB_PTR packet);
/*!
* @brief ENET error description.
*
* @param error The ENET error code.
* @return The error string.
*/
const char * ENET_strerror(uint32_t error);
/* @} */
#if defined(__cplusplus)
}
#endif
/*! @}*/
#endif /* MBED_NO_ENET */
#endif /* __FSL_ENET_RTCS_ADAPTOR_H__ */
/*******************************************************************************
* EOF
******************************************************************************/

155
libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/interrupt/fsl_interrupt_features.h
View File

@ -1,59 +1,126 @@
/*
* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __FSL_INTERRUPT_FEATURES_H__
** ###################################################################
** Version: rev. 1.0, 2014-05-14
** Build: b140526
**
** Abstract:
** Chip specific module features.
**
** Copyright: 2014 Freescale Semiconductor, Inc.
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** Revisions:
** - rev. 1.0 (2014-05-14)
** Customer release.
**
** ###################################################################
*/
#if !defined(__FSL_INTERRUPT_FEATURES_H__)
#define __FSL_INTERRUPT_FEATURES_H__
#if (defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || \
defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z128VFT4) || \
defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || \
defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4))
#define FSL_FEATURE_INTERRUPT_IRQ_MAX (31)
#if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \
defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || \
defined(CPU_MKV30F128VLF10) || defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10)
/* @brief Lowest interrupt request number. */
#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
#elif (defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || \
defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15))
/* @brief Highest interrupt request number. */
#define FSL_FEATURE_INTERRUPT_IRQ_MAX (73)
#elif defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \
defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \
defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \
defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \
defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || \
defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \
defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || \
defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) || defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || \
defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || \
defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15)
/* @brief Lowest interrupt request number. */
#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
/* @brief Highest interrupt request number. */
#define FSL_FEATURE_INTERRUPT_IRQ_MAX (105)
#elif defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || \
defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || \
defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12) || defined(CPU_MK24FN1M0VDC12) || \
defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK24FN256VDC12) || defined(CPU_MK63FN1M0VLQ12) || \
defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || \
defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VMD12) || \
defined(CPU_MK64FN1M0VMD12) || defined(CPU_MKV31F128VLH10) || defined(CPU_MKV31F128VLL10) || defined(CPU_MKV31F256VLH12) || \
defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31F512VLH12) || defined(CPU_MKV31F512VLL12)
/* @brief Lowest interrupt request number. */
#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
#elif (defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || \
defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || \
defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12))
/* @brief Highest interrupt request number. */
#define FSL_FEATURE_INTERRUPT_IRQ_MAX (85)
#elif defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || \
defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18) || \
defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLL15) || defined(CPU_MKV43F128VLL15) || defined(CPU_MKV45F128VLL15) || \
defined(CPU_MKV45F256VLL15) || defined(CPU_MKV46F128VLH15) || defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLH15) || \
defined(CPU_MKV46F256VLL15)
/* @brief Lowest interrupt request number. */
#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
#elif (defined(CPU_MK22FN512VDC12))
#define FSL_FEATURE_INTERRUPT_IRQ_MAX (85)
/* @brief Highest interrupt request number. */
#define FSL_FEATURE_INTERRUPT_IRQ_MAX (99)
#elif defined(CPU_MKL03Z32CAF4) || defined(CPU_MKL03Z8VFG4) || defined(CPU_MKL03Z16VFG4) || defined(CPU_MKL03Z32VFG4) || \
defined(CPU_MKL03Z8VFK4) || defined(CPU_MKL03Z16VFK4) || defined(CPU_MKL03Z32VFK4) || defined(CPU_MKL05Z8VFK4) || \
defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || defined(CPU_MKL05Z16VLC4) || \
defined(CPU_MKL05Z32VLC4) || defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || defined(CPU_MKL05Z32VFM4) || \
defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4) || defined(CPU_MKL17Z128VFM4) || defined(CPU_MKL17Z256VFM4) || \
defined(CPU_MKL17Z128VFT4) || defined(CPU_MKL17Z256VFT4) || defined(CPU_MKL17Z128VMP4) || defined(CPU_MKL17Z256VMP4) || \
defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z32VFT4) || \
defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || \
defined(CPU_MKL25Z128VLH4) || defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4) || \
defined(CPU_MKL26Z256VLK4) || defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || \
defined(CPU_MKL26Z256VMC4) || defined(CPU_MKL27Z128VFM4) || defined(CPU_MKL27Z256VFM4) || defined(CPU_MKL33Z128VLH4) || \
defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || defined(CPU_MKL33Z256VMP4) || defined(CPU_MKL43Z64VLH4) || \
defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z64VMP4) || defined(CPU_MKL43Z128VMP4) || \
defined(CPU_MKL43Z256VMP4) || defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || \
defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4)
/* @brief Lowest interrupt request number. */
#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
/* @brief Highest interrupt request number. */
#define FSL_FEATURE_INTERRUPT_IRQ_MAX (31)
#elif defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F256VLH15) || defined(CPU_MKV40F64VLH15) || defined(CPU_MKV43F128VLH15) || \
defined(CPU_MKV43F64VLH15) || defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15) || \
defined(CPU_MKV45F128VLH15) || defined(CPU_MKV45F256VLH15)
/* @brief Lowest interrupt request number. */
#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
/* @brief Highest interrupt request number. */
#define FSL_FEATURE_INTERRUPT_IRQ_MAX (92)
#else
#error "No valid CPU defined"
#error "No valid CPU defined!"
#endif
#endif /* __FSL_INTERRUPT_FEATURES_H__*/
#endif /* __FSL_INTERRUPT_FEATURES_H__ */
/*******************************************************************************
* EOF
******************************************************************************/

10
libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/interrupt/fsl_interrupt_manager.h
View File

@ -70,7 +70,7 @@ extern "C" {
* @param irqNumber IRQ number
* @param handler Interrupt handler routine address pointer
*/
void interrupt_register_handler(IRQn_Type irqNumber, void (*handler)(void));
void INT_SYS_InstallHandler(IRQn_Type irqNumber, void (*handler)(void));
/*!
* @brief Enables an interrupt for a given IRQ number.
@ -82,7 +82,7 @@ void interrupt_register_handler(IRQn_Type irqNumber, void (*handler)(void));
*
* @param irqNumber IRQ number
*/
static inline void interrupt_enable(IRQn_Type irqNumber)
static inline void INT_SYS_EnableIRQ(IRQn_Type irqNumber)
{
/* check IRQ number */
assert(0 <= irqNumber);
@ -101,7 +101,7 @@ static inline void interrupt_enable(IRQn_Type irqNumber)
*
* @param irqNumber IRQ number
*/
static inline void interrupt_disable(IRQn_Type irqNumber)
static inline void INT_SYS_DisableIRQ(IRQn_Type irqNumber)
{
/* check IRQ number */
assert(0 <= irqNumber);
@ -117,7 +117,7 @@ static inline void interrupt_disable(IRQn_Type irqNumber)
* This function enables the global interrupt by calling the core API.
*
*/
void interrupt_enable_global(void);
void INT_SYS_EnableIRQGlobal(void);
/*!
* @brief Disable system interrupt.
@ -125,7 +125,7 @@ void interrupt_enable_global(void);
* This function disables the global interrupt by calling the core API.
*
*/
void interrupt_disable_global(void);
void INT_SYS_DisableIRQGlobal(void);
/*@}*/

37
libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/interrupt/src/fsl_interrupt_manager.c
View File

@ -30,7 +30,6 @@
#include <assert.h>
#include "fsl_interrupt_manager.h"
#include "cmsis_nvic.h"
/*******************************************************************************
* Definitions
@ -39,7 +38,7 @@
/*!
* @brief Counter to manage the nested callings of global disable/enable interrupt.
*/
uint32_t g_interrupt_disable_count = 0;
uint32_t g_interruptDisableCount = 0;
/*******************************************************************************
* Code
@ -47,7 +46,7 @@ uint32_t g_interrupt_disable_count = 0;
/*FUNCTION**********************************************************************
*
* Function Name : interrupt_register_handler
* Function Name : INT_SYS_InstallHandler
* Description : Install an interrupt handler routine for a given IRQ number
* This function will let application to register/replace the interrupt
* handler for specified IRQ number. IRQ number is different with Vector
@ -58,26 +57,38 @@ uint32_t g_interrupt_disable_count = 0;
* it.
*
*END**************************************************************************/
void interrupt_register_handler(IRQn_Type irqNumber, void (*handler)(void))
void INT_SYS_InstallHandler(IRQn_Type irqNumber, void (*handler)(void))
{
NVIC_SetVector(irqNumber, (uint32_t)handler);
#if (defined(KEIL))
extern uint32_t Image$$VECTOR_RAM$$Base[];
#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
#else
extern uint32_t __VECTOR_RAM[];
#endif
/* check IRQ number */
assert(FSL_FEATURE_INTERRUPT_IRQ_MIN <= irqNumber);
assert(irqNumber <= FSL_FEATURE_INTERRUPT_IRQ_MAX);
/* set handler into vector table*/
__VECTOR_RAM[irqNumber + 16] = (uint32_t)handler;
}
/*FUNCTION**********************************************************************
*
* Function Name : interrupt_enable_global
* Function Name : INT_SYS_EnableIRQGlobal
* Description : Enable system interrupt
* This function will enable the global interrupt by calling the core API
*
*END**************************************************************************/
void interrupt_enable_global(void)
void INT_SYS_EnableIRQGlobal(void)
{
/* check and update */
if (g_interrupt_disable_count > 0)
if (g_interruptDisableCount > 0)
{
g_interrupt_disable_count--;
g_interruptDisableCount--;
if (g_interrupt_disable_count > 0)
if (g_interruptDisableCount > 0)
{
return;
}
@ -89,18 +100,18 @@ void interrupt_enable_global(void)
/*FUNCTION**********************************************************************
*
* Function Name : interrupt_disable_global
* Function Name : INT_SYS_DisableIRQGlobal
* Description : Disnable system interrupt
* This function will disable the global interrupt by calling the core API
*
*END**************************************************************************/
void interrupt_disable_global(void)
void INT_SYS_DisableIRQGlobal(void)
{
/* call core API to disable the global interrupt*/
__disable_irq();
/* update counter*/
g_interrupt_disable_count++;
g_interruptDisableCount++;
}
/*******************************************************************************

4
libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/interrupt/subdir.mk
View File

@ -1,4 +0,0 @@
INTERRUPT_DRIVER_DIR := $(SDK_ROOT)/platform/drivers/interrupt
SOURCES += $(INTERRUPT_DRIVER_DIR)/src/fsl_interrupt_manager.c
INCLUDES += $(INTERRUPT_DRIVER_DIR)

47
libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/pit/common/fsl_pit_common.c Normal file
View File

@ -0,0 +1,47 @@
/*
* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fsl_pit_features.h"
#include "fsl_device_registers.h"
/*******************************************************************************
* Variables
******************************************************************************/
/* Table of base addresses for pit instances. */
const uint32_t g_pitBaseAddr[] = PIT_BASE_ADDRS;
/* Table to save PIT IRQ enum numbers defined in CMSIS files. */
const IRQn_Type g_pitIrqId[] = PIT_IRQS;
/*******************************************************************************
* EOF
******************************************************************************/

49
libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/pit/common/fsl_pit_common.h Normal file
View File

@ -0,0 +1,49 @@
/*
* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#if !defined(__FSL_PIT_COMMON_H__)
#define __FSL_PIT_COMMON_H__
#include <stdint.h>
#include "fsl_device_registers.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @brief Table of base addresses for pit instances. */
extern const uint32_t g_pitBaseAddr[];
/*! @brief Table to save pit IRQ enum numbers defined in CMSIS header file. */
extern const IRQn_Type g_pitIrqId[];
#endif /* __FSL_PIT_COMMON_H__*/
/*******************************************************************************
* EOF
******************************************************************************/

121
libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/pit/fsl_pit_driver.h
View File

@ -46,12 +46,12 @@
/*!
* @brief PIT timer configuration structure
*
* Define structure PitConfig and use pit_init_channel() to make necessary
* initializations. You may also use remaining functions for PIT configuration.
* Define structure PitConfig and use the PIT_DRV_InitChannel() function to make necessary
* initializations. You may also use the remaining functions for PIT configuration.
*
* @note the timer chain feature is not valid in all devices, please check
* fsl_pit_features.h for accurate setting. If it's not valid, the value set here
* will be bypassed inside function pit_init_channel().
* @note The timer chain feature is not valid in all devices. Check the
* fsl_pit_features.h for accurate settings. If it's not valid, the value set here
* will be bypassed inside the PIT_DRV_InitChannel() function.
*/
typedef struct PitUserConfig {
bool isInterruptEnabled; /*!< Timer interrupt 0-disable/1-enable*/
@ -76,27 +76,38 @@ extern "C" {
*/
/*!
* @brief Initialize PIT module.
* @brief Initializes the PIT module.
*
* This function must be called before calling all the other PIT driver functions.
* This function un-gates the PIT clock and enables the PIT module. The isRunInDebug
* passed into function will affect all timer channels.
* passed into function affects all timer channels.
*
* @param instance PIT module instance number.
* @param isRunInDebug Timers run or stop in debug mode.
* - true: Timers continue to run in debug mode.
* - false: Timers stop in debug mode.
*/
void pit_init_module(bool isRunInDebug);
void PIT_DRV_Init(uint32_t instance, bool isRunInDebug);
/*!
* @brief Initialize PIT channel.
*
* This function initialize PIT timers by channel. Pass in timer number and its
* config structure. Timers do not start counting by default after calling this
* function. Function pit_timer_start must be called to start timer counting.
* Call pit_set_timer_period_us to re-set the period.
* @brief Disables the PIT module and gate control.
*
* Here is an example demonstrating how to define a PIT channel config structure:
* This function disables all PIT interrupts and PIT clock. It then gates the
* PIT clock control. PIT_DRV_Init must be called if you want to use PIT again.
*
* @param instance PIT module instance number.
*/
void PIT_DRV_Deinit(uint32_t instance);
/*!
* @brief Initializes the PIT channel.
*
* This function initializes the PIT timers by using a channel. Pass in the timer number and its
* configuration structure. Timers do not start counting by default after calling this
* function. The function PIT_DRV_StartTimer must be called to start the timer counting.
* Call the PIT_DRV_SetTimerPeriodByUs to re-set the period.
*
* This is an example demonstrating how to define a PIT channel configuration structure:
@code
pit_user_config_t pitTestInit = {
.isInterruptEnabled = true,
@ -108,18 +119,11 @@ void pit_init_module(bool isRunInDebug);
};
@endcode
*
* @param timer Timer channel number.
* @param instance PIT module instance number.
* @param channel Timer channel number.
* @param config PIT channel configuration structure.
*/
void pit_init_channel(uint32_t timer, const pit_user_config_t * config);
/*!
* @brief Disable PIT module and gate control.
*
* This function disables all PIT interrupts and PIT clock. It then gates the
* PIT clock control. pit_init_module must be called if you want to use PIT again.
*/
void pit_shutdown(void);
void PIT_DRV_InitChannel(uint32_t instance, uint32_t channel, const pit_user_config_t * config);
/* @} */
@ -129,25 +133,27 @@ void pit_shutdown(void);
*/
/*!
* @brief Start timer counting.
* @brief Starts the timer counting.
*
* After calling this function, timers load period value, count down to 0 and
* then load the respective start value again. Each time a timer reaches 0,
* it generates a trigger pulse and sets the timeout interrupt flag.
*
* @param timer Timer channel number.
* @param instance PIT module instance number.
* @param channel Timer channel number.
*/
void pit_timer_start(uint32_t timer);
void PIT_DRV_StartTimer(uint32_t instance, uint32_t channel);
/*!
* @brief Stop timer counting.
* @brief Stops the timer counting.
*
* This function stops every timer counting. Timers reload their periods
* respectively after the next time they call pit_timer_start.
* respectively after the next time they call the PIT_DRV_StartTimer.
*
* @param timer Timer channel number.
* @param instance PIT module instance number.
* @param channel Timer channel number.
*/
void pit_timer_stop(uint32_t timer);
void PIT_DRV_StopTimer(uint32_t instance, uint32_t channel);
/* @} */
@ -157,52 +163,56 @@ void pit_timer_stop(uint32_t timer);
*/
/*!
* @brief Set timer period in microsecond units.
* @brief Sets the timer period in microseconds.
*
* The period range depends on the frequency of PIT source clock. If the required period
* is out of range, use the lifetime timer, if applicable.
* The period range depends on the frequency of the PIT source clock. If the required period
* is out of range, use the lifetime timer.
*
* @param timer Timer channel number.
* @param instance PIT module instance number.
* @param channel Timer channel number.
* @param us Timer period in microseconds.
*/
void pit_set_timer_period_us(uint32_t timer, uint32_t us);
void PIT_DRV_SetTimerPeriodByUs(uint32_t instance, uint32_t channel, uint32_t us);
/*!
* @brief Read current timer value in microsecond units.
* @brief Reads the current timer value in microseconds.
*
* This function returns an absolute time stamp in microsecond units.
* This function returns an absolute time stamp in microseconds.
* One common use of this function is to measure the running time of a part of
* code. Call this function at both the beginning and end of code; the time
* difference between these two time stamps is the running time (Make sure the
* running time will not exceed the timer period). The time stamp returned is
* code. Call this function at both the beginning and end of code. The time
* difference between these two time stamps is the running time. Make sure the
* running time does not exceed the timer period. The time stamp returned is
* up-counting.
*
* @param timer Timer channel number.
* @param instance PIT module instance number.
* @param channel Timer channel number.
* @return Current timer value in microseconds.
*/
uint32_t pit_read_timer_us(uint32_t timer);
uint32_t PIT_DRV_ReadTimerUs(uint32_t instance, uint32_t channel);
#if FSL_FEATURE_PIT_HAS_LIFETIME_TIMER
/*!
* @brief Set lifetime timer period.
* @brief Sets the lifetime timer period.
*
* Timer 1 must be chained with timer 0 before using the lifetime timer. The period
* range is restricted by "period * pitSourceClock < max of an uint64_t integer",
* or it may cause an overflow and be unable to set the correct period.
*
* @param instance PIT module instance number.
* @param period Lifetime timer period in microseconds.
*/
void pit_set_lifetime_timer_period_us(uint64_t us);
void PIT_DRV_SetLifetimeTimerPeriodByUs(uint32_t instance, uint64_t us);
/*!
* @brief Read current lifetime value in microseconds.
* @brief Reads the current lifetime value in microseconds.
*
* This feature returns an absolute time stamp in microsecond units. The time stamp
* value will not exceed the timer period. The timer is up-counting.
* This feature returns an absolute time stamp in microseconds. The time stamp
* value does not exceed the timer period. The timer is up-counting.
*
* @param instance PIT module instance number.
* @return Current lifetime timer value in microseconds.
*/
uint64_t pit_read_lifetime_timer_us(void);
uint64_t PIT_DRV_ReadLifetimeTimerUs(uint32_t instance);
#endif /*FSL_FEATURE_PIT_HAS_LIFETIME_TIMER*/
/* @} */
@ -213,17 +223,18 @@ uint64_t pit_read_lifetime_timer_us(void);
*/
/*!
* @brief Register pit isr callback function.
* @brief Registers the PIT ISR callback function.
*
* System default ISR interfaces are already defined in fsl_pit_irq.c. Users
* System default ISR interfaces are already defined in the fsl_pit_irq.c. Users
* can either edit these ISRs or use this function to register a callback
* function. The default ISR runs the callback function if there is one
* installed.
*
* @param timer Timer channel number.
* @param function Pointer to pit isr callback function.
* @param instance PIT module instance number.
* @param channel Timer channel number.
* @param function Pointer to pit ISR callback function.
*/
void pit_register_isr_callback_function(uint32_t timer, pit_isr_callback_t function);
void PIT_DRV_InstallCallback(uint32_t instance, uint32_t channel, pit_isr_callback_t function);
/* @} */

116
libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/pit/src/fsl_pit_driver.c
View File

@ -28,6 +28,7 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fsl_pit_common.h"
#include "fsl_pit_driver.h"
#include "fsl_clock_manager.h"
#include "fsl_interrupt_manager.h"
@ -36,146 +37,158 @@
* Variables
******************************************************************************/
/* pit source clock variable which will be updated in pit_init_module. */
/* pit source clock variable which will be updated in PIT_DRV_Init. */
uint64_t pitSourceClock;
/* Table to save PIT IRQ enum numbers defined in CMSIS files. This table is
* defined in fsl_pit_irq.c */
extern IRQn_Type pit_irq_ids[FSL_FEATURE_PIT_TIMER_COUNT];
/*******************************************************************************
* Code
******************************************************************************/
/*FUNCTION**********************************************************************
*
* Function Name : pit_init_module
* Function Name : PIT_DRV_Init
* Description : Initialize PIT module.
* This function must be called before calling all the other PIT driver functions.
* This function un-gates the PIT clock and enables the PIT module. The isRunInDebug
* passed into function will affect all timer channels.
*
*END**************************************************************************/
void pit_init_module(bool isRunInDebug)
void PIT_DRV_Init(uint32_t instance, bool isRunInDebug)
{
uint32_t busClock;
assert(instance < HW_PIT_INSTANCE_COUNT);
uint32_t baseAddr = g_pitBaseAddr[instance];
/* Un-gate pit clock*/
clock_manager_set_gate(kClockModulePIT, 0U, true);
CLOCK_SYS_EnablePitClock( 0U);
/* Enable PIT module clock*/
pit_hal_enable();
PIT_HAL_Enable(baseAddr);
/* Set timer run or stop in debug mode*/
pit_hal_configure_timer_run_in_debug(isRunInDebug);
PIT_HAL_SetTimerRunInDebugCmd(baseAddr, isRunInDebug);
/* Finally, update pit source clock frequency.*/
clock_manager_get_frequency(kBusClock, &busClock);
pitSourceClock = (uint64_t)busClock;
pitSourceClock = CLOCK_SYS_GetPitFreq(0);
}
/*FUNCTION**********************************************************************
*
* Function Name : pit_init_channel
* Function Name : PIT_DRV_InitChannel
* Description : Initialize PIT channel.
* This function initialize PIT timers by channel. Pass in timer number and its
* config structure. Timers do not start counting by default after calling this
* function. Function pit_timer_start must be called to start timer counting.
* Call pit_set_timer_period_us to re-set the period.
* function. Function PIT_DRV_StartTimer must be called to start timer counting.
* Call PIT_DRV_SetTimerPeriodByUs to re-set the period.
*
*END**************************************************************************/
void pit_init_channel(uint32_t timer, const pit_user_config_t * config)
void PIT_DRV_InitChannel(uint32_t instance, uint32_t channel, const pit_user_config_t * config)
{
assert(instance < HW_PIT_INSTANCE_COUNT);
uint32_t baseAddr = g_pitBaseAddr[instance];
/* Set timer period.*/
pit_set_timer_period_us(timer, config->periodUs);
PIT_DRV_SetTimerPeriodByUs(instance, channel, config->periodUs);
#if FSL_FEATURE_PIT_HAS_CHAIN_MODE
/* Configure timer chained or not.*/
pit_hal_configure_timer_chain(timer, config->isTimerChained);
PIT_HAL_SetTimerChainCmd(baseAddr, channel, config->isTimerChained);
#endif
/* Enable or disable interrupt.*/
pit_hal_configure_interrupt(timer, config->isInterruptEnabled);
PIT_HAL_SetIntCmd(baseAddr, channel, config->isInterruptEnabled);
/* Configure NVIC*/
if (config->isInterruptEnabled)
{
/* Enable PIT interrupt.*/
interrupt_enable(pit_irq_ids[timer]);
INT_SYS_EnableIRQ(g_pitIrqId[channel]);
}
}
/*FUNCTION**********************************************************************
*
* Function Name : pit_shutdown
* Function Name : PIT_DRV_Deinit
* Description : Disable PIT module and gate control
* This function will disable all PIT interrupts and PIT clock. Then gate the
* PIT clock control. pit_init must be called in order to use PIT again.
*
*END**************************************************************************/
void pit_shutdown(void)
void PIT_DRV_Deinit(uint32_t instance)
{
assert(instance < HW_PIT_INSTANCE_COUNT);
uint32_t baseAddr = g_pitBaseAddr[instance];
uint32_t i;
/* Disable all PIT interrupts. */
for (i=0; i < FSL_FEATURE_PIT_TIMER_COUNT; i++)
{
pit_hal_configure_interrupt(i, false);
interrupt_disable(pit_irq_ids[i]);
PIT_HAL_SetIntCmd(baseAddr, i, false);
INT_SYS_DisableIRQ(g_pitIrqId[i]);
}
/* Disable PIT module clock*/
pit_hal_disable();
PIT_HAL_Disable(baseAddr);
/* Gate PIT clock control*/
clock_manager_set_gate(kClockModulePIT, 0U, false);
CLOCK_SYS_DisablePitClock( 0U);
}
/*FUNCTION**********************************************************************
*
* Function Name : pit_timer_start
* Function Name : PIT_DRV_StartTimer
* Description : Start timer counting.
* After calling this function, timers load period value, count down to 0 and
* then load the respective start value again. Each time a timer reaches 0,
* it will generate a trigger pulse and set the timeout interrupt flag.
*
*END**************************************************************************/
void pit_timer_start(uint32_t timer)
void PIT_DRV_StartTimer(uint32_t instance, uint32_t channel)
{
pit_hal_timer_start(timer);
assert(instance < HW_PIT_INSTANCE_COUNT);
uint32_t baseAddr = g_pitBaseAddr[instance];
PIT_HAL_StartTimer(baseAddr, channel);
}
/*FUNCTION**********************************************************************
*
* Function Name : pit_timer_stop
* Function Name : PIT_DRV_StopTimer
* Description : Stop timer counting.
* This function will stop every timer counting. Timers will reload their periods
* respectively after calling pit_timer_start next time.
* respectively after calling PIT_DRV_StartTimer next time.
*
*END**************************************************************************/
void pit_timer_stop(uint32_t timer)
void PIT_DRV_StopTimer(uint32_t instance, uint32_t channel)
{
pit_hal_timer_stop(timer);
assert(instance < HW_PIT_INSTANCE_COUNT);
uint32_t baseAddr = g_pitBaseAddr[instance];
PIT_HAL_StopTimer(baseAddr, channel);
}
/*FUNCTION**********************************************************************
*
* Function Name : pit_set_timer_period_us
* Function Name : PIT_DRV_SetTimerPeriodByUs
* Description : Set timer period in microseconds unit.
* The period range depends on the frequency of PIT source clock. If required
* period is out the range, try to use lifetime timer if applicable.
*
*END**************************************************************************/
void pit_set_timer_period_us(uint32_t timer, uint32_t us)
void PIT_DRV_SetTimerPeriodByUs(uint32_t instance, uint32_t channel, uint32_t us)
{
assert(instance < HW_PIT_INSTANCE_COUNT);
uint32_t baseAddr = g_pitBaseAddr[instance];
/* Calculate the count value, assign it to timer counter register.*/
uint32_t count = (uint32_t)(us * pitSourceClock / 1000000U - 1U);
pit_hal_set_timer_period_count(timer, count);
PIT_HAL_SetTimerPeriodByCount(baseAddr, channel, count);
}
/*FUNCTION**********************************************************************
*
* Function Name : pit_read_timer_us
* Function Name : PIT_DRV_ReadTimerUs
* Description : Read current timer value in microseconds unit.
* This function will return an absolute time stamp in the unit of microseconds.
* One common use of this function is to measure the running time of part of
@ -185,10 +198,13 @@ void pit_set_timer_period_us(uint32_t timer, uint32_t us)
* stamp returned is up-counting.
*
*END**************************************************************************/
uint32_t pit_read_timer_us(uint32_t timer)
uint32_t PIT_DRV_ReadTimerUs(uint32_t instance, uint32_t channel)
{
assert(instance < HW_PIT_INSTANCE_COUNT);
uint32_t baseAddr = g_pitBaseAddr[instance];
/* Get current timer count, and reverse it to up-counting.*/
uint64_t currentTime = (~pit_hal_read_timer_count(timer));
uint64_t currentTime = (~PIT_HAL_ReadTimerCount(baseAddr, channel));
/* Convert count numbers to microseconds unit.*/
currentTime = (currentTime * 1000000U) / pitSourceClock;
@ -198,37 +214,43 @@ uint32_t pit_read_timer_us(uint32_t timer)
#if FSL_FEATURE_PIT_HAS_LIFETIME_TIMER
/*FUNCTION**********************************************************************
*
* Function Name : pit_set_lifetime_timer_period_us
* Function Name : PIT_DRV_SetLifetimeTimerPeriodByUs
* Description : Set lifetime timer period (Timers must be chained).
* Timer 1 must be chained with timer 0 before using lifetime timer. The period
* range is restricted by "period * pitSourceClock < max of an uint64_t integer",
* or it may cause a overflow and is not able to set correct period.
*
*END**************************************************************************/
void pit_set_lifetime_timer_period_us(uint64_t us)
void PIT_DRV_SetLifetimeTimerPeriodByUs(uint32_t instance, uint64_t us)
{
assert(instance < HW_PIT_INSTANCE_COUNT);
uint32_t baseAddr = g_pitBaseAddr[instance];
uint64_t lifeTimeCount;
/* Calculate the counter value.*/
lifeTimeCount = us * pitSourceClock / 1000000U - 1U;
/* Assign to timers.*/
pit_hal_set_timer_period_count(0U, (uint32_t)lifeTimeCount);
pit_hal_set_timer_period_count(1U, (uint32_t)(lifeTimeCount >> 32U));
PIT_HAL_SetTimerPeriodByCount(baseAddr, 0U, (uint32_t)lifeTimeCount);
PIT_HAL_SetTimerPeriodByCount(baseAddr, 1U, (uint32_t)(lifeTimeCount >> 32U));
}
/*FUNCTION**********************************************************************
*
* Function Name : pit_read_lifetime_timer_us
* Function Name : PIT_DRV_ReadLifetimeTimerUs
* Description : Read current lifetime value in microseconds unit.
* Return an absolute time stamp in the unit of microseconds. The time stamp
* value will not exceed the timer period. Also, the timer is up-counting.
*
*END**************************************************************************/
uint64_t pit_read_lifetime_timer_us(void)
uint64_t PIT_DRV_ReadLifetimeTimerUs(uint32_t instance)
{
assert(instance < HW_PIT_INSTANCE_COUNT);
uint32_t baseAddr = g_pitBaseAddr[instance];
/* Get current lifetime timer count, and reverse it to up-counting.*/
uint64_t currentTime = (~pit_hal_read_lifetime_timer_count());
uint64_t currentTime = (~PIT_HAL_ReadLifetimeTimerCount(baseAddr));
/* Convert count numbers to microseconds unit.*/
/* Note: using currentTime * 1000 rather than 1000000 to avoid short time overflow. */

117
libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/pit/src/fsl_pit_irq.c
View File

@ -27,9 +27,10 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <stdlib.h>
#include <assert.h>
#include "fsl_pit_common.h"
#include "fsl_pit_driver.h"
/*!
@ -40,106 +41,90 @@
/*******************************************************************************
* Variables
******************************************************************************/
#if defined (KL25Z4_SERIES)
/*!
* @brief Table to save PIT IRQ enum numbers defined in CMSIS files.
*
* They are used by pit_init_channel to enable or disable PIT interrupts. This table is
* indexed by channel number which could return PIT IRQ numbers.
*/
const IRQn_Type pit_irq_ids[FSL_FEATURE_PIT_TIMER_COUNT] =
{
PIT_IRQn, PIT_IRQn
};
#elif defined (K64F12_SERIES) || defined (K70F12_SERIES) || defined (K22F51212_SERIES)
const IRQn_Type pit_irq_ids[FSL_FEATURE_PIT_TIMER_COUNT] =
{
PIT0_IRQn, PIT1_IRQn, PIT2_IRQn, PIT3_IRQn
};
#endif
/*!
* @brief Function table to save PIT isr callback function pointers.
*
* Call pit_register_isr_callback_function to install isr callback functions.
* Call PIT_DRV_InstallCallback to install isr callback functions.
*/
pit_isr_callback_t pit_isr_callback_table[FSL_FEATURE_PIT_TIMER_COUNT] = {NULL};
static pit_isr_callback_t pitIsrCallbackTable[HW_PIT_INSTANCE_COUNT][FSL_FEATURE_PIT_TIMER_COUNT] = {{NULL}};
/*******************************************************************************
* Code
******************************************************************************/
#if defined (KL25Z4_SERIES)
/*!
/*!
* @brief System default IRQ handler defined in startup code.
*
* Users can either edit this handler or define a callback function. Furthermore,
* interrupt manager could be used to re-map the IRQ handler to another function.
* interrupt manager could be used to re-map the IRQ handler to another function.
*/
void PIT_IRQHandler(void)
{
uint32_t i;
for(i=0; i < FSL_FEATURE_PIT_TIMER_COUNT; i++)
{
/* Run callback function if it exists.*/
if (pit_isr_callback_table[i])
{
(*pit_isr_callback_table[i])();
}
/* Clear interrupt flag.*/
pit_hal_clear_interrupt_flag(i);
PIT_HAL_ClearIntFlag(g_pitBaseAddr[0], i);
/* Run callback function if it exists.*/
if (pitIsrCallbackTable[0][i])
{
(*pitIsrCallbackTable[0][i])();
}
}
}
#elif defined (K64F12_SERIES) || defined (K70F12_SERIES) || defined (K22F51212_SERIES)
#elif defined (K64F12_SERIES) || defined (K24F12_SERIES) || defined (K63F12_SERIES) || \
defined (K22F12810_SERIES) || defined (K22F25612_SERIES) || defined (K22F51212_SERIES) || \
defined (KV31F12810_SERIES) || defined (KV31F25612_SERIES) || defined (KV31F51212_SERIES) || \
defined (K70F12_SERIES)
void PIT0_IRQHandler(void)
{
/* Run callback function if it exists.*/
if (pit_isr_callback_table[0])
{
(*pit_isr_callback_table[0])();
}
/* Clear interrupt flag.*/
pit_hal_clear_interrupt_flag(0);
PIT_HAL_ClearIntFlag(g_pitBaseAddr[0], 0U);
/* Run callback function if it exists.*/
if (pitIsrCallbackTable[0][0])
{
(*pitIsrCallbackTable[0][0])();
}
}
void PIT1_IRQHandler(void)
{
/* Run callback function if it exists.*/
if (pit_isr_callback_table[1])
{
(*pit_isr_callback_table[1])();
}
/* Clear interrupt flag.*/
pit_hal_clear_interrupt_flag(1);
PIT_HAL_ClearIntFlag(g_pitBaseAddr[0], 1U);
/* Run callback function if it exists.*/
if (pitIsrCallbackTable[0][1])
{
(*pitIsrCallbackTable[0][1])();
}
}
void PIT2_IRQHandler(void)
{
/* Run callback function if it exists.*/
if (pit_isr_callback_table[2])
{
(*pit_isr_callback_table[2])();
}
/* Clear interrupt flag.*/
pit_hal_clear_interrupt_flag(2);
PIT_HAL_ClearIntFlag(g_pitBaseAddr[0], 2U);
/* Run callback function if it exists.*/
if (pitIsrCallbackTable[0][2])
{
(*pitIsrCallbackTable[0][2])();
}
}
void PIT3_IRQHandler(void)
{
/* Run callback function if it exists.*/
if (pit_isr_callback_table[3])
{
(*pit_isr_callback_table[3])();
}
/* Clear interrupt flag.*/
pit_hal_clear_interrupt_flag(3);
PIT_HAL_ClearIntFlag(g_pitBaseAddr[0], 3U);
/* Run callback function if it exists.*/
if (pitIsrCallbackTable[0][3])
{
(*pitIsrCallbackTable[0][3])();
}
}
#endif
@ -147,20 +132,20 @@ void PIT3_IRQHandler(void)
/*FUNCTION**********************************************************************
*
* Function Name : pit_register_isr_callback_function
* Description : Register pit isr callback function.
* System default ISR interfaces are already defined in fsl_pit_irq.c. Users
* Function Name : PIT_DRV_InstallCallback
* Description : Register pit isr callback function.
* System default ISR interfaces are already defined in fsl_pit_irq.c. Users
* can either edit these ISRs or use this function to register a callback
* function. The default ISR will run the callback function it there is one
* installed here.
*END**************************************************************************/
void pit_register_isr_callback_function(uint32_t timer, pit_isr_callback_t function)
void PIT_DRV_InstallCallback(uint32_t instance, uint32_t channel, pit_isr_callback_t function)
{
assert(timer < FSL_FEATURE_PIT_TIMER_COUNT);
assert(channel < FSL_FEATURE_PIT_TIMER_COUNT);
assert(function != NULL);
pit_isr_callback_table[timer] = function;
pitIsrCallbackTable[instance][channel] = function;
}
/*******************************************************************************

3
libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/pit/subdir.mk
View File

@ -1,3 +0,0 @@
PIT_DRIVER_DIR := $(SDK_ROOT)/platform/drivers/pit
SOURCES += $(wildcard $(PIT_DRIVER_DIR)/src/*.c)
INCLUDES += $(PIT_DRIVER_DIR)

258
libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/adc/fsl_adc_features.h
View File

@ -1,138 +1,220 @@
/*
* Copyright (c) 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
** ###################################################################
** Version: rev. 1.0, 2014-05-14
** Build: b140515
**
** Abstract:
** Chip specific module features.
**
** Copyright: 2014 Freescale Semiconductor, Inc.
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** Revisions:
** - rev. 1.0 (2014-05-14)
** Customer release.
**
** ###################################################################
*/
#if !defined(__FSL_ADC_FEATURES_H__)
#define __FSL_ADC_FEATURES_H__
#if defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \
defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \
defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \
defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || \
defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || \
defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) || \
defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || \
defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12) || defined(CPU_MK24FN1M0VDC12) || \
defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FN1M0VDC12) || \
defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VMD12) || \
defined(CPU_MK64FX512VMD12) || defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || \
defined(CPU_MK65FX1M0VMI18) || defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || \
defined(CPU_MK66FX1M0VMD18) || defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || \
defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || \
defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || \
defined(CPU_MKL25Z128VLK4) || defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || \
defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4) || defined(CPU_MKV31F256VLH12) || \
defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31FN512VLH12) || defined(CPU_MKV31F512VLL12)
/* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA).*/
#if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \
defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || \
defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || \
defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || \
defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || \
defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \
defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || \
defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) || defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || \
defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || \
defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || \
defined(CPU_MK22FN512VLL12) || defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) || \
defined(CPU_MK24FN256VDC12) || defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || \
defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || \
defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK65FN2M0CAC18) || \
defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || defined(CPU_MK66FN2M0VLQ18) || \
defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18) || defined(CPU_MKL13Z64VFM4) || \
defined(CPU_MKL13Z128VFM4) || defined(CPU_MKL13Z256VFM4) || defined(CPU_MKL13Z64VFT4) || defined(CPU_MKL13Z128VFT4) || \
defined(CPU_MKL13Z256VFT4) || defined(CPU_MKL13Z64VLH4) || defined(CPU_MKL13Z128VLH4) || defined(CPU_MKL13Z256VLH4) || \
defined(CPU_MKL13Z64VMP4) || defined(CPU_MKL13Z128VMP4) || defined(CPU_MKL13Z256VMP4) || defined(CPU_MKL23Z64VFM4) || \
defined(CPU_MKL23Z128VFM4) || defined(CPU_MKL23Z256VFM4) || defined(CPU_MKL23Z64VFT4) || defined(CPU_MKL23Z128VFT4) || \
defined(CPU_MKL23Z256VFT4) || defined(CPU_MKL23Z64VLH4) || defined(CPU_MKL23Z128VLH4) || defined(CPU_MKL23Z256VLH4) || \
defined(CPU_MKL23Z64VMP4) || defined(CPU_MKL23Z128VMP4) || defined(CPU_MKL23Z256VMP4) || defined(CPU_MKL25Z32VFM4) || \
defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || \
defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || \
defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4) || defined(CPU_MKL26Z256VLK4) || \
defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || defined(CPU_MKL26Z256VMC4) || \
defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || defined(CPU_MKL33Z256VMP4) || \
defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z64VMP4) || \
defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4) || defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || \
defined(CPU_MKL46Z128VLL4) || defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4) || \
defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || defined(CPU_MKV30F128VLF10) || defined(CPU_MKV30F64VLF10) || \
defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10) || defined(CPU_MKV31F128VLH10) || defined(CPU_MKV31F128VLL10) || \
defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31F512VLH12) || defined(CPU_MKV31F512VLL12)
/* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */
#define FSL_FEATURE_ADC_HAS_PGA (0)
/* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]).*/
/* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */
#define FSL_FEATURE_ADC_HAS_DMA (1)
/* @brief Has differential mode (bitfield SC1x[DIFF]).*/
/* @brief Has differential mode (bitfield SC1x[DIFF]). */
#define FSL_FEATURE_ADC_HAS_DIFF_MODE (1)
/* @brief Has FIFO (bit SC4[AFDEP]).*/
/* @brief Has FIFO (bit SC4[AFDEP]). */
#define FSL_FEATURE_ADC_HAS_FIFO (0)
/* @brief FIFO size if available (bitfield SC4[AFDEP]).*/
/* @brief FIFO size if available (bitfield SC4[AFDEP]). */
#define FSL_FEATURE_ADC_FIFO_SIZE (0)
/* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]).*/
/* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */
#define FSL_FEATURE_ADC_HAS_MUX_SELECT (1)
/* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE].*/
/* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */
#define FSL_FEATURE_ADC_HAS_HW_TRIGGER_MASK (0)
/* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx).*/
/* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */
#define FSL_FEATURE_ADC_HAS_CALIBRATION (1)
/* @brief Has HW averaging (bit SC3[AVGE]).*/
/* @brief Has HW averaging (bit SC3[AVGE]). */
#define FSL_FEATURE_ADC_HAS_HW_AVERAGE (1)
/* @brief Has offset correction (register OFS).*/
/* @brief Has offset correction (register OFS). */
#define FSL_FEATURE_ADC_HAS_OFFSET_CORRECTION (1)
/* @brief Maximum ADC resolution.*/
/* @brief Maximum ADC resolution. */
#define FSL_FEATURE_ADC_MAX_RESOLUTION (16)
/* @brief Number of SC1x and Rx register pairs (conversion control and result registers).*/
/* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */
#define FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT (2)
#elif defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \
defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || \
defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || \
defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || defined(CPU_MKL05Z32VFM4) || defined(CPU_MKL05Z16VLF4) || \
defined(CPU_MKL05Z32VLF4)
/* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA).*/
defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5)
/* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */
#define FSL_FEATURE_ADC_HAS_PGA (0)
/* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]).*/
/* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */
#define FSL_FEATURE_ADC_HAS_DMA (1)
/* @brief Has differential mode (bitfield SC1x[DIFF]).*/
/* @brief Has differential mode (bitfield SC1x[DIFF]). */
#define FSL_FEATURE_ADC_HAS_DIFF_MODE (0)
/* @brief Has FIFO (bit SC4[AFDEP]).*/
/* @brief Has FIFO (bit SC4[AFDEP]). */
#define FSL_FEATURE_ADC_HAS_FIFO (0)
/* @brief FIFO size if available (bitfield SC4[AFDEP]).*/
/* @brief FIFO size if available (bitfield SC4[AFDEP]). */
#define FSL_FEATURE_ADC_FIFO_SIZE (0)
/* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]).*/
/* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */
#define FSL_FEATURE_ADC_HAS_MUX_SELECT (1)
/* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE].*/
/* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */
#define FSL_FEATURE_ADC_HAS_HW_TRIGGER_MASK (0)
/* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx).*/
/* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */
#define FSL_FEATURE_ADC_HAS_CALIBRATION (1)
/* @brief Has HW averaging (bit SC3[AVGE]).*/
/* @brief Has HW averaging (bit SC3[AVGE]). */
#define FSL_FEATURE_ADC_HAS_HW_AVERAGE (1)
/* @brief Has offset correction (register OFS).*/
/* @brief Has offset correction (register OFS). */
#define FSL_FEATURE_ADC_HAS_OFFSET_CORRECTION (1)
/* @brief Maximum ADC resolution.*/
/* @brief Maximum ADC resolution. */
#define FSL_FEATURE_ADC_MAX_RESOLUTION (16)
/* @brief Number of SC1x and Rx register pairs (conversion control and result registers).*/
/* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */
#define FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT (2)
#elif defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \
defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15)
/* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA).*/
/* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */
#define FSL_FEATURE_ADC_HAS_PGA (1)
/* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]).*/
/* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */
#define FSL_FEATURE_ADC_HAS_DMA (1)
/* @brief Has differential mode (bitfield SC1x[DIFF]).*/
/* @brief Has differential mode (bitfield SC1x[DIFF]). */
#define FSL_FEATURE_ADC_HAS_DIFF_MODE (1)
/* @brief Has FIFO (bit SC4[AFDEP]).*/
/* @brief Has FIFO (bit SC4[AFDEP]). */
#define FSL_FEATURE_ADC_HAS_FIFO (0)
/* @brief FIFO size if available (bitfield SC4[AFDEP]).*/
/* @brief FIFO size if available (bitfield SC4[AFDEP]). */
#define FSL_FEATURE_ADC_FIFO_SIZE (0)
/* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]).*/
/* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */
#define FSL_FEATURE_ADC_HAS_MUX_SELECT (1)
/* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE].*/
/* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */
#define FSL_FEATURE_ADC_HAS_HW_TRIGGER_MASK (0)
/* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx).*/
/* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */
#define FSL_FEATURE_ADC_HAS_CALIBRATION (1)
/* @brief Has HW averaging (bit SC3[AVGE]).*/
/* @brief Has HW averaging (bit SC3[AVGE]). */
#define FSL_FEATURE_ADC_HAS_HW_AVERAGE (1)
/* @brief Has offset correction (register OFS).*/
/* @brief Has offset correction (register OFS). */
#define FSL_FEATURE_ADC_HAS_OFFSET_CORRECTION (1)
/* @brief Maximum ADC resolution.*/
/* @brief Maximum ADC resolution. */
#define FSL_FEATURE_ADC_MAX_RESOLUTION (16)
/* @brief Number of SC1x and Rx register pairs (conversion control and result registers).*/
/* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */
#define FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT (2)
#elif defined(CPU_MKL03Z32CAF4) || defined(CPU_MKL03Z8VFG4) || defined(CPU_MKL03Z16VFG4) || defined(CPU_MKL03Z32VFG4) || \
defined(CPU_MKL03Z8VFK4) || defined(CPU_MKL03Z16VFK4) || defined(CPU_MKL03Z32VFK4)
/* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */
#define FSL_FEATURE_ADC_HAS_PGA (0)
/* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */
#define FSL_FEATURE_ADC_HAS_DMA (0)
/* @brief Has differential mode (bitfield SC1x[DIFF]). */
#define FSL_FEATURE_ADC_HAS_DIFF_MODE (0)
/* @brief Has FIFO (bit SC4[AFDEP]). */
#define FSL_FEATURE_ADC_HAS_FIFO (0)
/* @brief FIFO size if available (bitfield SC4[AFDEP]). */
#define FSL_FEATURE_ADC_FIFO_SIZE (0)
/* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */
#define FSL_FEATURE_ADC_HAS_MUX_SELECT (1)
/* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */
#define FSL_FEATURE_ADC_HAS_HW_TRIGGER_MASK (0)
/* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */
#define FSL_FEATURE_ADC_HAS_CALIBRATION (1)
/* @brief Has HW averaging (bit SC3[AVGE]). */
#define FSL_FEATURE_ADC_HAS_HW_AVERAGE (1)
/* @brief Has offset correction (register OFS). */
#define FSL_FEATURE_ADC_HAS_OFFSET_CORRECTION (1)
/* @brief Maximum ADC resolution. */
#define FSL_FEATURE_ADC_MAX_RESOLUTION (12)
/* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */
#define FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT (2)
#elif defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || \
defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || \
defined(CPU_MKL05Z32VFM4) || defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4)
/* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */
#define FSL_FEATURE_ADC_HAS_PGA (0)
/* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */
#define FSL_FEATURE_ADC_HAS_DMA (1)
/* @brief Has differential mode (bitfield SC1x[DIFF]). */
#define FSL_FEATURE_ADC_HAS_DIFF_MODE (0)
/* @brief Has FIFO (bit SC4[AFDEP]). */
#define FSL_FEATURE_ADC_HAS_FIFO (0)
/* @brief FIFO size if available (bitfield SC4[AFDEP]). */
#define FSL_FEATURE_ADC_FIFO_SIZE (0)
/* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */
#define FSL_FEATURE_ADC_HAS_MUX_SELECT (1)
/* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */
#define FSL_FEATURE_ADC_HAS_HW_TRIGGER_MASK (0)
/* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */
#define FSL_FEATURE_ADC_HAS_CALIBRATION (1)
/* @brief Has HW averaging (bit SC3[AVGE]). */
#define FSL_FEATURE_ADC_HAS_HW_AVERAGE (1)
/* @brief Has offset correction (register OFS). */
#define FSL_FEATURE_ADC_HAS_OFFSET_CORRECTION (1)
/* @brief Maximum ADC resolution. */
#define FSL_FEATURE_ADC_MAX_RESOLUTION (12)
/* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */
#define FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT (2)
#else
#error "No valid CPU defined!"
#endif
#endif /* __FSL_ADC_FEATURES_H__*/
#endif /* __FSL_ADC_FEATURES_H__ */
/*******************************************************************************
* EOF
******************************************************************************/

216
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View File

@ -1,114 +1,152 @@
/*
* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fsl_adc_hal.h"
#include "fsl_device_registers.h"
#include <assert.h>
/*******************************************************************************
* Code
******************************************************************************/
/*FUNCTION**********************************************************************
/*FUNCTION*********************************************************************
*
* Function Name : adc_hal_start_calibration
* Description : This function is to clear the calibrate flag bit and then set
* the enable bit to start the calibration.
*
*END**************************************************************************/
adc_status_t adc_hal_start_calibration(uint32_t instance)
* Function Name : ADC_HAL_Init
* Description :Reset all the registers into a known state for ADC
* module. This known state is the default value indicated by the Reference
* manual. It is strongly recommended to call this API before any operations
* when initializing the ADC module. Note registers for calibration would not
* be cleared in this function.
*
*END*************************************************************************/
void ADC_HAL_Init(uint32_t baseAddr)
{
assert(instance < HW_ADC_INSTANCE_COUNT);
/* Execute the calibration */
HW_ADC_SC3_SET(instance, BM_ADC_SC3_CALF); /* Clear the calibration's flag */
BW_ADC_SC3_CAL(instance, 1U); /* Enable the calibration */
while (!adc_hal_is_conversion_completed(instance, 0U))
{} /* Wait conversion is competed */
if (adc_hal_is_calibration_fail(instance))
{
return kStatus_ADC_Failed; /* Check for calibration fail error and return */
}
return kStatus_ADC_Success;
HW_ADC_CFG1_WR(baseAddr, 0U);
HW_ADC_CFG2_WR(baseAddr, 0U);
HW_ADC_CV1_WR(baseAddr, 0U);
HW_ADC_CV2_WR(baseAddr, 0U);
HW_ADC_SC2_WR(baseAddr, 0U);
HW_ADC_SC3_WR(baseAddr, 0U);
#if FSL_FEATURE_ADC_HAS_PGA
HW_ADC_PGA_WR(baseAddr, 0U);
#endif /* FSL_FEATURE_ADC_HAS_PGA */
}
/*FUNCTION**********************************************************************
/*FUNCTION*********************************************************************
*
* Function Name : adc_hal_get_calibration_PG
* Description : This function is to get the CLP0 - CLP4 and CLPS and
* accumulate them, and then return the value that can be set to PG directly.
*
*END**************************************************************************/
uint32_t adc_hal_get_calibration_PG(uint32_t instance)
* Function Name : ADC_HAL_SetHwCmpMode
* Description :Set the asserted compare range when enabling hardware
* compare function. About the selection of range mode, see to the description
* for "adc_hw_cmp_range_mode_t".
*
*END*************************************************************************/
void ADC_HAL_SetHwCmpMode(uint32_t baseAddr, adc_hw_cmp_range_mode_t mode)
{
assert(instance < HW_ADC_INSTANCE_COUNT);
uint32_t cal_var;
switch (mode)
{
case kAdcHwCmpRangeModeOf1:
ADC_HAL_SetHwCmpGreaterCmd(baseAddr, false);
ADC_HAL_SetHwCmpRangeCmd(baseAddr, false);
break;
case kAdcHwCmpRangeModeOf2:
ADC_HAL_SetHwCmpGreaterCmd(baseAddr, true);
ADC_HAL_SetHwCmpRangeCmd(baseAddr, false);
break;
case kAdcHwCmpRangeModeOf3:
ADC_HAL_SetHwCmpGreaterCmd(baseAddr, false);
ADC_HAL_SetHwCmpRangeCmd(baseAddr, true);
break;
case kAdcHwCmpRangeModeOf4:
ADC_HAL_SetHwCmpGreaterCmd(baseAddr, true);
ADC_HAL_SetHwCmpRangeCmd(baseAddr, true);
break;
default:
break;
}
}
#if FSL_FEATURE_ADC_HAS_CALIBRATION
/*FUNCTION*********************************************************************
*
* Function Name : ADC_HAL_GetAutoPlusSideGainValue
* Description : Get the values of CLP0 - CLP4 and CLPS internally,
* accumulate them, and return the value that can be used to be set in PG
* register directly. Note that this API should be called after the process of
* auto calibration has been done.
*
*END*************************************************************************/
uint16_t ADC_HAL_GetAutoPlusSideGainValue(uint32_t baseAddr)
{
uint16_t cal_var;
/* Calculate plus-side calibration */
cal_var = 0U;
cal_var += BR_ADC_CLP0_CLP0(instance);
cal_var += BR_ADC_CLP1_CLP1(instance);
cal_var += BR_ADC_CLP2_CLP2(instance);
cal_var += BR_ADC_CLP3_CLP3(instance);
cal_var += BR_ADC_CLP4_CLP4(instance);
cal_var += BR_ADC_CLPS_CLPS(instance);
cal_var += BR_ADC_CLP0_CLP0(baseAddr);
cal_var += BR_ADC_CLP1_CLP1(baseAddr);
cal_var += BR_ADC_CLP2_CLP2(baseAddr);
cal_var += BR_ADC_CLP3_CLP3(baseAddr);
cal_var += BR_ADC_CLP4_CLP4(baseAddr);
cal_var += BR_ADC_CLPS_CLPS(baseAddr);
cal_var = 0x8000U | (cal_var>>1U);
return cal_var;
}
/*FUNCTION**********************************************************************
#if FSL_FEATURE_ADC_HAS_DIFF_MODE
/*FUNCTION*********************************************************************
*
* Function Name : adc_hal_get_calibration_MG
* Description : This function is to get the CLM0 - CLM4 and CLMS and
* accumulate them, and then return the value that can be set to MG directly.
*
*END**************************************************************************/
uint32_t adc_hal_get_calibration_MG(uint32_t instance)
* Function Name : ADC_HAL_GetAutoMinusSideGainValue
* Description : Get the values of CLM0 - CLM4 and CLMS internally,
* accumulate them, and return the value that can be used to be set in MG
* register directly. Note that this API should be called after the process of
* auto calibration has been done.
*
*END*************************************************************************/
uint16_t ADC_HAL_GetAutoMinusSideGainValue(uint32_t baseAddr)
{
assert(instance < HW_ADC_INSTANCE_COUNT);
uint32_t cal_var;
uint16_t cal_var;
/* Calculate minus-side calibration */
cal_var = 0U;
cal_var += BR_ADC_CLM0_CLM0(instance);
cal_var += BR_ADC_CLM1_CLM1(instance);
cal_var += BR_ADC_CLM2_CLM2(instance);
cal_var += BR_ADC_CLM3_CLM3(instance);
cal_var += BR_ADC_CLM4_CLM4(instance);
cal_var += BR_ADC_CLMS_CLMS(instance);
cal_var += BR_ADC_CLM0_CLM0(baseAddr);
cal_var += BR_ADC_CLM1_CLM1(baseAddr);
cal_var += BR_ADC_CLM2_CLM2(baseAddr);
cal_var += BR_ADC_CLM3_CLM3(baseAddr);
cal_var += BR_ADC_CLM4_CLM4(baseAddr);
cal_var += BR_ADC_CLMS_CLMS(baseAddr);
cal_var = 0x8000U | (cal_var>>1U);
return cal_var;
}
/*******************************************************************************
#endif /* FSL_FEATURE_ADC_HAS_DIFF_MODE */
#endif /* FSL_FEATURE_ADC_HAS_CALIBRATION */
/******************************************************************************
* EOF
******************************************************************************/
*****************************************************************************/

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@ -1,68 +1,119 @@
/*
* Copyright (c) 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#if !defined(__FSL_CAN_FEATURES_H__)
#define __FSL_CAN_FEATURES_H__
** ###################################################################
** Version: rev. 1.0, 2014-05-14
** Build: b140516
**
** Abstract:
** Chip specific module features.
**
** Copyright: 2014 Freescale Semiconductor, Inc.
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** Revisions:
** - rev. 1.0 (2014-05-14)
** Customer release.
**
** ###################################################################
*/
#if defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12) || \
defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VLQ12) || \
defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK64FX512VMD12) || defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || \
defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || \
defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18)
/* @brief Message buffer size*/
#define FSL_FEATURE_CAN_HAS_MESSAGE_BUFFER_MAX_NUMBER (16)
/* @brief Has doze mode support (register bit field MCR[DOZE]).*/
#define FSL_FEATURE_CAN_HAS_DOZE_MODE_SUPPORT (0)
/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]).*/
#define FSL_FEATURE_CAN_HAS_GLITCH_FILTER (1)
/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2).*/
#define FSL_FEATURE_CAN_HAS_EXTENDED_FLAG_REGISTER (0)
/* @brief Has separate message buffer 0 interrupt flag (register bit field IFLAG1[BUF0I]).*/
#define FSL_FEATURE_CAN_HAS_SEPARATE_BUFFER_0_FLAG (1)
#if !defined(__FSL_FLEXCAN_FEATURES_H__)
#define __FSL_FLEXCAN_FEATURES_H__
#if defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK63FN1M0VLQ12) || \
defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || \
defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VMD12) || \
defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || \
defined(CPU_MK65FX1M0VMI18) || defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || \
defined(CPU_MK66FX1M0VMD18)
/* @brief Message buffer size */
#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBER (16)
/* @brief Has doze mode support (register bit field MCR[DOZE]). */
#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (0)
/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */
#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1)
/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */
#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (0)
/* @brief Has extended bit timing register (register CBT). */
#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_TIMING_REGISTER (0)
/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */
#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (0)
/* @brief Has separate message buffer 0 interrupt flag (register bit field IFLAG1[BUF0I]). */
#define FSL_FEATURE_FLEXCAN_HAS_SEPARATE_BUFFER_0_FLAG (1)
/* @brief Number of interrupt vectors. */
#define FSL_FEATURE_FLEXCAN_INTERRUPT_COUNT (6)
#elif defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \
defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15)
/* @brief Message buffer size*/
#define FSL_FEATURE_CAN_HAS_MESSAGE_BUFFER_MAX_NUMBER (16)
/* @brief Has doze mode support (register bit field MCR[DOZE]).*/
#define FSL_FEATURE_CAN_HAS_DOZE_MODE_SUPPORT (0)
/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]).*/
#define FSL_FEATURE_CAN_HAS_GLITCH_FILTER (0)
/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2).*/
#define FSL_FEATURE_CAN_HAS_EXTENDED_FLAG_REGISTER (1)
/* @brief Has separate message buffer 0 interrupt flag (register bit field IFLAG1[BUF0I]).*/
#define FSL_FEATURE_CAN_HAS_SEPARATE_BUFFER_0_FLAG (0)
/* @brief Message buffer size */
#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBER (16)
/* @brief Has doze mode support (register bit field MCR[DOZE]). */
#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (0)
/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */
#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (0)
/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */
#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (1)
/* @brief Has extended bit timing register (register CBT). */
#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_TIMING_REGISTER (0)
/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */
#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (0)
/* @brief Has separate message buffer 0 interrupt flag (register bit field IFLAG1[BUF0I]). */
#define FSL_FEATURE_FLEXCAN_HAS_SEPARATE_BUFFER_0_FLAG (0)
/* @brief Number of interrupt vectors. */
#define FSL_FEATURE_FLEXCAN_INTERRUPT_COUNT (6)
#elif defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLH15) || defined(CPU_MKV40F256VLL15) || \
defined(CPU_MKV40F64VLH15) || defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || defined(CPU_MKV43F64VLH15) || \
defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15) || defined(CPU_MKV45F128VLH15) || \
defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLH15) || defined(CPU_MKV45F256VLL15) || defined(CPU_MKV46F128VLH15) || \
defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLH15) || defined(CPU_MKV46F256VLL15)
/* @brief Message buffer size */
#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBER (16)
/* @brief Has doze mode support (register bit field MCR[DOZE]). */
#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (1)
/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */
#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1)
/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */
#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (0)
/* @brief Has extended bit timing register (register CBT). */
#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_TIMING_REGISTER (1)
/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */
#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (1)
/* @brief Has separate message buffer 0 interrupt flag (register bit field IFLAG1[BUF0I]). */
#define FSL_FEATURE_FLEXCAN_HAS_SEPARATE_BUFFER_0_FLAG (1)
/* @brief Number of interrupt vectors. */
#define FSL_FEATURE_FLEXCAN_INTERRUPT_COUNT (6)
#else
#error "No valid CPU defined!"
#define MBED_NO_FLEXCAN
#endif
#endif /* __FSL_CAN_FEATURES_H__*/
#endif /* __FSL_FLEXCAN_FEATURES_H__ */
/*******************************************************************************
* EOF
******************************************************************************/

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@ -36,6 +36,8 @@
#include "fsl_flexcan_features.h"
#include "fsl_device_registers.h"
#ifndef MBED_NO_FLEXCAN
/*!
* @addtogroup flexcan_hal
* @{
@ -190,40 +192,13 @@ typedef struct FLEXCANBerrCounter {
uint16_t rxerr; /*!< Receive error counter*/
} flexcan_berr_counter_t;
/*! @brief FlexCAN MB code and status for transmitting*/
typedef struct FLEXCANMbCodeStatusTx {
flexcan_mb_code_tx_t code; /*!< MB code for Tx buffers*/
flexcan_mb_id_type_t msg_id_type; /*!< Type of message ID (standard or extended)*/
uint32_t data_length; /*!< Length of Data in Bytes*/
uint32_t substitute_remote; /*!< Substitute remote request (used only in*/
/*! extended format)*/
uint32_t remote_transmission; /*!< Remote transmission request*/
bool local_priority_enable; /*!< 1 if enable it; 0 if disable it*/
uint32_t local_priority_val; /*!< Local priority value [0..2]*/
} flexcan_mb_code_status_tx_t;
/*! @brief FlexCAN MB code and status for receiving*/
typedef struct FLEXCANMbCodeStatusRx {
flexcan_mb_code_rx_t code; /*!< MB code for Rx buffers*/
flexcan_mb_id_type_t msg_id_type; /*!< Type of message ID (standard or extended)*/
uint32_t data_length; /*!< Length of Data in Bytes*/
uint32_t substitute_remote; /*!< Substitute remote request (used only in*/
/*! extended format)*/
uint32_t remote_transmission; /*!< Remote transmission request*/
bool local_priority_enable; /*!< 1 if enable it; 0 if disable it*/
uint32_t local_priority_val; /*!< Local priority value [0..2]*/
} flexcan_mb_code_status_rx_t;
/*! @brief FlexCAN Rx FIFO configuration*/
typedef struct FLEXCANRxFifoConfig {
flexcan_mb_id_type_t msg_id_type; /*!< Type of message ID*/
/*! (standard or extended)*/
uint32_t data_length; /*!< Length of Data in Bytes*/
uint32_t substitute_remote; /*!< Substitute remote request (used*/
/*! only in extended format)*/
uint32_t remote_transmission; /*!< Remote transmission request*/
flexcan_rx_fifo_id_element_format_t id_filter_number; /*!< The number of Rx FIFO ID filters*/
} flexcan_rx_fifo_config_t;
/*! @brief FlexCAN MB code and status for transmit and receive */
typedef struct FLEXCANMbCodeStatus {
uint32_t code; /*!< MB code for TX or RX buffers.
Defined by flexcan_mb_code_rx_t and flexcan_mb_code_tx_t */
flexcan_mb_id_type_t msg_id_type; /*!< Type of message ID (standard or extended)*/
uint32_t data_length; /*!< Length of Data in Bytes*/
} flexcan_mb_code_status_t;
/*! @brief FlexCAN message buffer structure*/
typedef struct FLEXCANMb {
@ -234,11 +209,9 @@ typedef struct FLEXCANMb {
/*! @brief FlexCAN configuration*/
typedef struct FLEXCANUserConfig {
uint32_t num_mb; /*!< The number of Message Buffers needed*/
uint32_t max_num_mb; /*!< The maximum number of Message Buffers*/
flexcan_rx_fifo_id_filter_num_t num_id_filters; /*!< The number of Rx FIFO ID filters needed*/
bool is_rx_fifo_needed; /*!< 1 if needed; 0 if not*/
bool is_rx_mb_needed; /*!< 1 if needed; 0 if not*/
} flexcan_user_config_t;
/*! @brief FlexCAN timing related structures*/
@ -267,111 +240,101 @@ extern "C" {
/*!
* @brief Enables FlexCAN controller.
*
* @param instance The FlexCAN instance number
* @param canBaseAddr The FlexCAN base address
* @return 0 if successful; non-zero failed
*/
flexcan_status_t flexcan_hal_enable(uint8_t instance);
flexcan_status_t FLEXCAN_HAL_Enable(uint32_t canBaseAddr);
/*!
* @brief Disables FlexCAN controller.
*
* @param instance The FlexCAN instance number
* @param canBaseAddr The FlexCAN base address
* @return 0 if successful; non-zero failed
*/
flexcan_status_t flexcan_hal_disable(uint8_t instance);
flexcan_status_t FLEXCAN_HAL_Disable(uint32_t canBaseAddr);
/*!
* @brief Checks whether the FlexCAN is enabled or disabled.
*
* @param instance The FlexCAN instance number
* @param canBaseAddr The FlexCAN base address
* @return State of FlexCAN enable(0)/disable(1)
*/
static inline bool flexcan_hal_is_enabled(uint8_t instance)
static inline bool FLEXCAN_HAL_IsEnabled(uint32_t canBaseAddr)
{
assert(instance < HW_CAN_INSTANCE_COUNT);
return BR_CAN_MCR_MDIS(instance);
return BR_CAN_MCR_MDIS(canBaseAddr);
}
/*!
* @brief Resets the FlexCAN controller.
*
* @param instance The FlexCAN instance number
* @return 0 if successful; non-zero failed
*/
flexcan_status_t flexcan_hal_sw_reset(uint8_t instance);
/*!
* @brief Selects the clock source for FlexCAN.
*
* @param instance The FlexCAN instance number
* @param canBaseAddr The FlexCAN base address
* @param clk The FlexCAN clock source
* @return 0 if successful; non-zero failed
*/
flexcan_status_t flexcan_hal_select_clk(uint8_t instance, flexcan_clk_source_t clk);
flexcan_status_t FLEXCAN_HAL_SelectClock(uint32_t canBaseAddr, flexcan_clk_source_t clk);
/*!
* @brief Initializes the FlexCAN controller.
*
* @param instance The FlexCAN instance number
* @param data The FlexCAN platform data.
* @param canBaseAddr The FlexCAN base address
* @param data The FlexCAN platform data.
* @return 0 if successful; non-zero failed
*/
flexcan_status_t flexcan_hal_init(uint8_t instance, const flexcan_user_config_t *data);
flexcan_status_t FLEXCAN_HAL_Init(uint32_t canBaseAddr, const flexcan_user_config_t *data);
/*!
* @brief Sets the FlexCAN time segments for setting up bit rate.
*
* @param instance The FlexCAN instance number
* @param canBaseAddr The FlexCAN base address
* @param time_seg FlexCAN time segments, which need to be set for the bit rate.
* @return 0 if successful; non-zero failed
*/
void flexcan_hal_set_time_segments(uint8_t instance, flexcan_time_segment_t *time_seg);
void FLEXCAN_HAL_SetTimeSegments(uint32_t canBaseAddr, flexcan_time_segment_t *time_seg);
/*!
* @brief Gets the FlexCAN time segments to calculate the bit rate.
*
* @param instance The FlexCAN instance number
* @param canBaseAddr The FlexCAN base address
* @param time_seg FlexCAN time segments read for bit rate
* @return 0 if successful; non-zero failed
*/
void flexcan_hal_get_time_segments(uint8_t instance, flexcan_time_segment_t *time_seg);
void FLEXCAN_HAL_GetTimeSegments(uint32_t canBaseAddr, flexcan_time_segment_t *time_seg);
/*!
* @brief Un freezes the FlexCAN module.
*
* @param instance The FlexCAN instance number
* @param canBaseAddr The FlexCAN base address
* @return 0 if successful; non-zero failed.
*/
void flexcan_hal_exit_freeze_mode(uint8_t instance);
void FLEXCAN_HAL_ExitFreezeMode(uint32_t canBaseAddr);
/*!
* @brief Freezes the FlexCAN module.
*
* @param instance The FlexCAN instance number
* @param canBaseAddr The FlexCAN base address
*/
void flexcan_hal_enter_freeze_mode(uint8_t instance);
void FLEXCAN_HAL_EnterFreezeMode(uint32_t canBaseAddr);
/*!
* @brief Enables operation mode.
*
* @param instance The FlexCAN instance number
* @param canBaseAddr The FlexCAN base address
* @param mode An operation mode to be enabled
* @return 0 if successful; non-zero failed.
*/
flexcan_status_t flexcan_hal_enable_operation_mode(
uint8_t instance,
flexcan_status_t FLEXCAN_HAL_EnableOperationMode(
uint32_t canBaseAddr,
flexcan_operation_modes_t mode);
/*!
* @brief Disables operation mode.
*
* @param instance The FlexCAN instance number
* @param canBaseAddr The FlexCAN base address
* @param mode An operation mode to be disabled
* @return 0 if successful; non-zero failed.
*/
flexcan_status_t flexcan_hal_disable_operation_mode(
uint8_t instance,
flexcan_status_t FLEXCAN_HAL_DisableOperationMode(
uint32_t canBaseAddr,
flexcan_operation_modes_t mode);
/*@}*/
@ -384,7 +347,7 @@ flexcan_status_t flexcan_hal_disable_operation_mode(
/*!
* @brief Sets the FlexCAN message buffer fields for transmitting.
*
* @param instance The FlexCAN instance number
* @param canBaseAddr The FlexCAN base address
* @param data The FlexCAN platform data
* @param mb_idx Index of the message buffer
* @param cs CODE/status values (TX)
@ -392,42 +355,42 @@ flexcan_status_t flexcan_hal_disable_operation_mode(
* @param mb_data Bytes of the FlexCAN message
* @return 0 if successful; non-zero failed
*/
flexcan_status_t flexcan_hal_set_mb_tx(
uint8_t instance,
flexcan_status_t FLEXCAN_HAL_SetMbTx(
uint32_t canBaseAddr,
const flexcan_user_config_t *data,
uint32_t mb_idx,
flexcan_mb_code_status_tx_t *cs,
flexcan_mb_code_status_t *cs,
uint32_t msg_id,
uint8_t *mb_data);
/*!
* @brief Set the FlexCAN message buffer fields for receiving.
* @brief Sets the FlexCAN message buffer fields for receiving.
*
* @param instance The FlexCAN instance number
* @param canBaseAddr The FlexCAN base address
* @param data The FlexCAN platform data
* @param mb_idx Index of the message buffer
* @param cs CODE/status values (RX)
* @param msg_id ID of the message to receive
* @return 0 if successful; non-zero failed
*/
flexcan_status_t flexcan_hal_set_mb_rx(
uint8_t instance,
flexcan_status_t FLEXCAN_HAL_SetMbRx(
uint32_t canBaseAddr,
const flexcan_user_config_t *data,
uint32_t mb_idx,
flexcan_mb_code_status_rx_t *cs,
flexcan_mb_code_status_t *cs,
uint32_t msg_id);
/*!
* @brief Gets the FlexCAN message buffer fields.
*
* @param instance The FlexCAN instance number
* @param canBaseAddr The FlexCAN base address
* @param data The FlexCAN platform data
* @param mb_idx Index of the message buffer
* @param mb The fields of the message buffer
* @return 0 if successful; non-zero failed
*/
flexcan_status_t flexcan_hal_get_mb(
uint8_t instance,
flexcan_status_t FLEXCAN_HAL_GetMb(
uint32_t canBaseAddr,
const flexcan_user_config_t *data,
uint32_t mb_idx,
flexcan_mb_t *mb);
@ -435,74 +398,72 @@ flexcan_status_t flexcan_hal_get_mb(
/*!
* @brief Locks the FlexCAN Rx message buffer.
*
* @param instance The FlexCAN instance number
* @param canBaseAddr The FlexCAN base address
* @param data The FlexCAN platform data
* @param mb_idx Index of the message buffer
* @return 0 if successful; non-zero failed
*/
flexcan_status_t flexcan_hal_lock_rx_mb(
uint8_t instance,
flexcan_status_t FLEXCAN_HAL_LockRxMb(
uint32_t canBaseAddr,
const flexcan_user_config_t *data,
uint32_t mb_idx);
/*!
* @brief Unlocks the FlexCAN Rx message buffer.
*
* @param instance The FlexCAN instance number
* @param canBaseAddr The FlexCAN base address
* @return 0 if successful; non-zero failed
*/
static inline void flexcan_hal_unlock_rx_mb(uint8_t instance)
static inline void FLEXCAN_HAL_UnlockRxMb(uint32_t canBaseAddr)
{
assert(instance < HW_CAN_INSTANCE_COUNT);
/* Unlock the mailbox */
HW_CAN_TIMER_RD(instance);
HW_CAN_TIMER_RD(canBaseAddr);
}
/*!
* @brief Enables the Rx FIFO.
*
* @param instance The FlexCAN instance number
* @param canBaseAddr The FlexCAN base address
*/
void flexcan_hal_enable_rx_fifo(uint8_t instance);
void FLEXCAN_HAL_EnableRxFifo(uint32_t canBaseAddr);
/*!
* @brief Disables the Rx FIFO.
*
* @param instance The FlexCAN instance number
* @param canBaseAddr The FlexCAN base address
*/
void flexcan_hal_disable_rx_fifo(uint8_t instance);
void FLEXCAN_HAL_DisableRxFifo(uint32_t canBaseAddr);
/*!
* @brief Sets the number of the Rx FIFO filters.
*
* @param instance The FlexCAN instance number
* @param canBaseAddr The FlexCAN base address
* @param number The number of Rx FIFO filters
*/
void flexcan_hal_set_rx_fifo_filters_number(uint8_t instance, uint32_t number);
void FLEXCAN_HAL_SetRxFifoFiltersNumber(uint32_t canBaseAddr, uint32_t number);
/*!
* @brief Sets the maximum number of Message Buffers.
*
* @param instance The FlexCAN instance number
* @param canBaseAddr The FlexCAN base address
* @param data The FlexCAN platform data
*/
void flexcan_hal_set_max_mb_number(
uint8_t instance,
void FLEXCAN_HAL_SetMaxMbNumber(
uint32_t canBaseAddr,
const flexcan_user_config_t *data);
/*!
* @brief Sets the Rx FIFO ID filter table elements.
*
* @param instance The FlexCAN instance number
* @param data The FlexCAN platform data
* @param id_format The format of the Rx FIFO ID Filter Table Elements
* @param id_filter_table The ID filter table elements which contain if RTR bit,
* IDE bit and RX message ID need to be set.
* @param canBaseAddr The FlexCAN base address
* @param data The FlexCAN platform data
* @param id_format The format of the Rx FIFO ID Filter Table Elements
* @param id_filter_table The ID filter table elements which contain if RTR bit,
* IDE bit and RX message ID need to be set.
* @return 0 if successful; non-zero failed.
*/
flexcan_status_t flexcan_hal_set_id_filter_table_elements(
uint8_t instance,
flexcan_status_t FLEXCAN_HAL_SetIdFilterTableElements(
uint32_t canBaseAddr,
const flexcan_user_config_t *data,
flexcan_rx_fifo_id_element_format_t id_format,
flexcan_id_table_t *id_filter_table);
@ -510,15 +471,15 @@ flexcan_status_t flexcan_hal_set_id_filter_table_elements(
/*!
* @brief Sets the FlexCAN Rx FIFO fields.
*
* @param instance The FlexCAN instance number
* @param canBaseAddr The FlexCAN base address
* @param data The FlexCAN platform data
* @param id_format The format of the Rx FIFO ID Filter Table Elements
* @param id_filter_table The ID filter table elements which contain RTR bit, IDE bit,
* and RX message ID.
* @return 0 if successful; non-zero failed.
*/
flexcan_status_t flexcan_hal_set_rx_fifo(
uint8_t instance,
flexcan_status_t FLEXCAN_HAL_SetRxFifo(
uint32_t canBaseAddr,
const flexcan_user_config_t *data,
flexcan_rx_fifo_id_element_format_t id_format,
flexcan_id_table_t *id_filter_table);
@ -526,12 +487,12 @@ flexcan_status_t flexcan_hal_set_rx_fifo(
/*!
* @brief Gets the FlexCAN Rx FIFO data.
*
* @param instance The FlexCAN instance number
* @param canBaseAddr The FlexCAN base address
* @param rx_fifo The FlexCAN receive FIFO data
* @return 0 if successful; non-zero failed.
*/
flexcan_status_t flexcan_hal_read_fifo(
uint8_t instance,
flexcan_status_t FLEXCAN_HAL_ReadFifo(
uint32_t canBaseAddr,
flexcan_mb_t *rx_fifo);
/*@}*/
@ -544,97 +505,97 @@ flexcan_status_t flexcan_hal_read_fifo(
/*!
* @brief Enables the FlexCAN Message Buffer interrupt.
*
* @param instance The FlexCAN instance number
* @param canBaseAddr The FlexCAN base address
* @param data The FlexCAN platform data
* @param mb_idx Index of the message buffer
* @return 0 if successful; non-zero failed
*/
flexcan_status_t flexcan_hal_enable_mb_interrupt(
uint8_t instance,
flexcan_status_t FLEXCAN_HAL_EnableMbInt(
uint32_t canBaseAddr,
const flexcan_user_config_t *data,
uint32_t mb_idx);
/*!
* @brief Disables the FlexCAN Message Buffer interrupt.
*
* @param instance The FlexCAN instance number
* @param canBaseAddr The FlexCAN base address
* @param data The FlexCAN platform data
* @param mb_idx Index of the message buffer
* @return 0 if successful; non-zero failed
*/
flexcan_status_t flexcan_hal_disable_mb_interrupt(
uint8_t instance,
flexcan_status_t FLEXCAN_HAL_DisableMbInt(
uint32_t canBaseAddr,
const flexcan_user_config_t *data,
uint32_t mb_idx);
/*!
* @brief Enables error interrupt of the FlexCAN module.
* @param instance The FlexCAN instance number
* @param canBaseAddr The FlexCAN base address
*/
void flexcan_hal_enable_error_interrupt(uint8_t instance);
void FLEXCAN_HAL_EnableErrInt(uint32_t canBaseAddr);
/*!
* @brief Disables error interrupt of the FlexCAN module.
*
* @param instance The FlexCAN instance number
* @param canBaseAddr The FlexCAN base address
*/
void flexcan_hal_disable_error_interrupt(uint8_t instance);
void FLEXCAN_HAL_DisableErrInt(uint32_t canBaseAddr);
/*!
* @brief Enables Bus off interrupt of the FlexCAN module.
*
* @param instance The FlexCAN instance number
* @param canBaseAddr The FlexCAN base address
*/
void flexcan_hal_enable_bus_off_interrupt(uint8_t instance);
void FLEXCAN_HAL_EnableBusOffInt(uint32_t canBaseAddr);
/*!
* @brief Disables Bus off interrupt of the FlexCAN module.
*
* @param instance The FlexCAN instance number
* @param canBaseAddr The FlexCAN base address
*/
void flexcan_hal_disable_bus_off_interrupt(uint8_t instance);
void FLEXCAN_HAL_DisableBusOffInt(uint32_t canBaseAddr);
/*!
* @brief Enables Wakeup interrupt of the FlexCAN module.
*
* @param instance The FlexCAN instance number
* @param canBaseAddr The FlexCAN base address
*/
void flexcan_hal_enable_wakeup_interrupt(uint8_t instance);
void FLEXCAN_HAL_EnableWakeupInt(uint32_t canBaseAddr);
/*!
* @brief Disables Wakeup interrupt of the FlexCAN module.
*
* @param instance The FlexCAN instance number
* @param canBaseAddr The FlexCAN base address
*/
void flexcan_hal_disable_wakeup_interrupt(uint8_t instance);
void FLEXCAN_HAL_DisableWakeupInt(uint32_t canBaseAddr);
/*!
* @brief Enables TX warning interrupt of the FlexCAN module
*
* @param instance The FlexCAN instance number
* @param canBaseAddr The FlexCAN base address
*/
void flexcan_hal_enable_tx_warning_interrupt(uint8_t instance);
void FLEXCAN_HAL_EnableTxWarningInt(uint32_t canBaseAddr);
/*!
* @brief Disables TX warning interrupt of the FlexCAN module.
*
* @param instance The FlexCAN instance number
* @param canBaseAddr The FlexCAN base address
*/
void flexcan_hal_disable_tx_warning_interrupt(uint8_t instance);
void FLEXCAN_HAL_DisableTxWarningInt(uint32_t canBaseAddr);
/*!
* @brief Enables RX warning interrupt of the FlexCAN module.
*
* @param instance The FlexCAN instance number
* @param canBaseAddr The FlexCAN base address
*/
void flexcan_hal_enable_rx_warning_interrupt(uint8_t instance);
void FLEXCAN_HAL_EnableRxWarningInt(uint32_t canBaseAddr);
/*!
* @brief Disables RX warning interrupt of the FlexCAN module.
*
* @param instance The FlexCAN instance number
* @param canBaseAddr The FlexCAN base address
*/
void flexcan_hal_disable_rx_warning_interrupt(uint8_t instance);
void FLEXCAN_HAL_DisableRxWarningInt(uint32_t canBaseAddr);
/*@}*/
@ -646,85 +607,80 @@ void flexcan_hal_disable_rx_warning_interrupt(uint8_t instance);
/*!
* @brief Gets the value of FlexCAN freeze ACK.
*
* @param instance The FlexCAN instance number
* @param canBaseAddr The FlexCAN base address
* @return freeze ACK state (1-freeze mode, 0-not in freeze mode).
*/
static inline uint32_t flexcan_hal_get_freeze_ack(uint8_t instance)
static inline uint32_t FLEXCAN_HAL_GetFreezeAck(uint32_t canBaseAddr)
{
assert(instance < HW_CAN_INSTANCE_COUNT);
return HW_CAN_MCR(instance).B.FRZACK;
return HW_CAN_MCR(canBaseAddr).B.FRZACK;
}
/*!
* @brief Gets the individual FlexCAN MB interrupt flag.
*
* @param instance The FlexCAN instance number
* @param canBaseAddr The FlexCAN base address
* @param data The FlexCAN platform data
* @param mb_idx Index of the message buffer
* @return the individual MB interrupt flag (0 and 1 are the flag value)
*/
uint8_t flexcan_hal_get_mb_int_flag(
uint8_t instance,
uint8_t FLEXCAN_HAL_GetMbIntFlag(
uint32_t canBaseAddr,
const flexcan_user_config_t *data,
uint32_t mb_idx);
/*!
* @brief Gets all FlexCAN MB interrupt flags.
*
* @param instance The FlexCAN instance number
* @param canBaseAddr The FlexCAN base address
* @return all MB interrupt flags
*/
static inline uint32_t flexcan_hal_get_all_mb_int_flags(uint8_t instance)
static inline uint32_t FLEXCAN_HAL_GetAllMbIntFlags(uint32_t canBaseAddr)
{
assert(instance < HW_CAN_INSTANCE_COUNT);
return HW_CAN_IFLAG1_RD(instance);
return HW_CAN_IFLAG1_RD(canBaseAddr);
}
/*!
* @brief Clears the interrupt flag of the message buffers.
*
* @param instance The FlexCAN instance number
* @param canBaseAddr The FlexCAN base address
* @param reg_val The value to be written to the interrupt flag1 register.
*/
/* See fsl_flexcan_hal.h for documentation of this function.*/
static inline void flexcan_hal_clear_mb_int_flag(
uint8_t instance,
static inline void FLEXCAN_HAL_ClearMbIntFlag(
uint32_t canBaseAddr,
uint32_t reg_val)
{
assert(instance < HW_CAN_INSTANCE_COUNT);
/* Clear the corresponding message buffer interrupt flag*/
HW_CAN_IFLAG1_SET(instance, reg_val);
HW_CAN_IFLAG1_SET(canBaseAddr, reg_val);
}
/*!
* @brief Gets the transmit error counter and receives the error counter.
*
* @param instance The FlexCAN instance number
* @param canBaseAddr The FlexCAN base address
* @param err_cnt Transmit error counter and receive error counter
*/
void flexcan_hal_get_err_counter(
uint8_t instance,
void FLEXCAN_HAL_GetErrCounter(
uint32_t canBaseAddr,
flexcan_berr_counter_t *err_cnt);
/*!
* @brief Gets error and status.
*
* @param instance The FlexCAN instance number
* @param canBaseAddr The FlexCAN base address
* @return The current error and status
*/
static inline uint32_t flexcan_hal_get_err_status(uint8_t instance)
static inline uint32_t FLEXCAN_HAL_GetErrStatus(uint32_t canBaseAddr)
{
assert(instance < HW_CAN_INSTANCE_COUNT);
return HW_CAN_ESR1_RD(instance);
return HW_CAN_ESR1_RD(canBaseAddr);
}
/*!
* @brief Clears all other interrupts in ERRSTAT register (Error, Busoff, Wakeup).
*
* @param instance The FlexCAN instance number
* @param canBaseAddr The FlexCAN base address
*/
void flexcan_hal_clear_err_interrupt_status(uint8_t instance);
void FLEXCAN_HAL_ClearErrIntStatus(uint32_t canBaseAddr);
/*@}*/
@ -736,42 +692,42 @@ void flexcan_hal_clear_err_interrupt_status(uint8_t instance);
/*!
* @brief Sets the Rx masking type.
*
* @param instance The FlexCAN instance number
* @param canBaseAddr The FlexCAN base address
* @param type The FlexCAN Rx mask type
*/
void flexcan_hal_set_mask_type(uint8_t instance, flexcan_rx_mask_type_t type);
void FLEXCAN_HAL_SetMaskType(uint32_t canBaseAddr, flexcan_rx_mask_type_t type);
/*!
* @brief Sets the FlexCAN RX FIFO global standard mask.
*
* @param instance The FlexCAN instance number
* @param canBaseAddr The FlexCAN base address
* @param std_mask Standard mask
*/
void flexcan_hal_set_rx_fifo_global_std_mask(
uint8_t instance,
void FLEXCAN_HAL_SetRxFifoGlobalStdMask(
uint32_t canBaseAddr,
uint32_t std_mask);
/*!
* @brief Sets the FlexCAN Rx FIFO global extended mask.
*
* @param instance The FlexCAN instance number
* @param canBaseAddr The FlexCAN base address
* @param ext_mask Extended mask
*/
void flexcan_hal_set_rx_fifo_global_ext_mask(
uint8_t instance,
void FLEXCAN_HAL_SetRxFifoGlobalExtMask(
uint32_t canBaseAddr,
uint32_t ext_mask);
/*!
* @brief Sets the FlexCAN Rx individual standard mask for ID filtering in the Rx MBs and the Rx FIFO.
*
* @param instance The FlexCAN instance number
* @param canBaseAddr The FlexCAN base address
* @param data The FlexCAN platform data
* @param mb_idx Index of the message buffer
* @param std_mask Individual standard mask
* @return 0 if successful; non-zero failed
*/
flexcan_status_t flexcan_hal_set_rx_individual_std_mask(
uint8_t instance,
flexcan_status_t FLEXCAN_HAL_SetRxIndividualStdMask(
uint32_t canBaseAddr,
const flexcan_user_config_t * data,
uint32_t mb_idx,
uint32_t std_mask);
@ -779,14 +735,14 @@ flexcan_status_t flexcan_hal_set_rx_individual_std_mask(
/*!
* @brief Sets the FlexCAN Rx individual extended mask for ID filtering in the Rx MBs and the Rx FIFO.
*
* @param instance The FlexCAN instance number
* @param canBaseAddr The FlexCAN base address
* @param data The FlexCAN platform data
* @param mb_idx Index of the message buffer
* @param ext_mask Individual extended mask
* @return 0 if successful; non-zero failed
*/
flexcan_status_t flexcan_hal_set_rx_individual_ext_mask(
uint8_t instance,
flexcan_status_t FLEXCAN_HAL_SetRxIndividualExtMask(
uint32_t canBaseAddr,
const flexcan_user_config_t * data,
uint32_t mb_idx,
uint32_t ext_mask);
@ -794,74 +750,73 @@ flexcan_status_t flexcan_hal_set_rx_individual_ext_mask(
/*!
* @brief Sets the FlexCAN Rx MB global standard mask.
*
* @param instance The FlexCAN instance number
* @param canBaseAddr The FlexCAN base address
* @param std_mask Standard mask
*/
void flexcan_hal_set_rx_mb_global_std_mask(
uint8_t instance,
void FLEXCAN_HAL_SetRxMbGlobalStdMask(
uint32_t canBaseAddr,
uint32_t std_mask);
/*!
* @brief Sets the FlexCAN RX MB BUF14 standard mask.
*
* @param instance The FlexCAN instance number
* @param canBaseAddr The FlexCAN base address
* @param std_mask Standard mask
*/
void flexcan_hal_set_rx_mb_buf14_std_mask(
uint8_t instance,
void FLEXCAN_HAL_SetRxMbBuf14StdMask(
uint32_t canBaseAddr,
uint32_t std_mask);
/*!
* @brief Sets the FlexCAN Rx MB BUF15 standard mask.
*
* @param instance The FlexCAN instance number
* @param canBaseAddr The FlexCAN base address
* @param std_mask Standard mask
* @return 0 if successful; non-zero failed
*/
void flexcan_hal_set_rx_mb_buf15_std_mask(
uint8_t instance,
void FLEXCAN_HAL_SetRxMbBuf15StdMask(
uint32_t canBaseAddr,
uint32_t std_mask);
/*!
* @brief Sets the FlexCAN RX MB global extended mask.
*
* @param instance The FlexCAN instance number
* @param canBaseAddr The FlexCAN base address
* @param ext_mask Extended mask
*/
void flexcan_hal_set_rx_mb_global_ext_mask(
uint8_t instance,
void FLEXCAN_HAL_SetRxMbGlobalExtMask(
uint32_t canBaseAddr,
uint32_t ext_mask);
/*!
* @brief Sets the FlexCAN RX MB BUF14 extended mask.
*
* @param instance The FlexCAN instance number
* @param canBaseAddr The FlexCAN base address
* @param ext_mask Extended mask
*/
void flexcan_hal_set_rx_mb_buf14_ext_mask(
uint8_t instance,
void FLEXCAN_HAL_SetRxMbBuf14ExtMask(
uint32_t canBaseAddr,
uint32_t ext_mask);
/*!
* @brief Sets the FlexCAN RX MB BUF15 extended mask.
*
* @param instance The FlexCAN instance number
* @param canBaseAddr The FlexCAN base address
* @param ext_mask Extended mask
*/
void flexcan_hal_set_rx_mb_buf15_ext_mask(
uint8_t instance,
void FLEXCAN_HAL_SetRxMbBuf15ExtMask(
uint32_t canBaseAddr,
uint32_t ext_mask);
/*!
* @brief Gets the FlexCAN ID acceptance filter hit indicator on Rx FIFO.
*
* @param instance The FlexCAN instance number
* @param canBaseAddr The FlexCAN base address
* @return RX FIFO information
*/
static inline uint32_t flexcan_hal_get_rx_fifo_id_acceptance_filter(uint8_t instance)
static inline uint32_t FLEXCAN_HAL_GetIdAcceptanceFilterRxFifo(uint32_t canBaseAddr)
{
assert(instance < HW_CAN_INSTANCE_COUNT);
return BR_CAN_RXFIR_IDHIT(instance);
return BR_CAN_RXFIR_IDHIT(canBaseAddr);
}
/*@}*/
@ -872,6 +827,8 @@ static inline uint32_t flexcan_hal_get_rx_fifo_id_acceptance_filter(uint8_t ins
/*! @}*/
#endif /* MBED_NO_FLEXCAN */
#endif /* __FSL_FLEXCAN_HAL_H__*/
/*******************************************************************************

100
libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/dac/fsl_dac_features.h Normal file
View File

@ -0,0 +1,100 @@
/*
** ###################################################################
** Version: rev. 1.0, 2014-05-14
** Build: b140515
**
** Abstract:
** Chip specific module features.
**
** Copyright: 2014 Freescale Semiconductor, Inc.
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** Revisions:
** - rev. 1.0 (2014-05-14)
** Customer release.
**
** ###################################################################
*/
#if !defined(__FSL_DAC_FEATURES_H__)
#define __FSL_DAC_FEATURES_H__
#if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \
defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || \
defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || \
defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || \
defined(CPU_MK22FN512VLL12) || defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) || \
defined(CPU_MK24FN256VDC12) || defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || \
defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || \
defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK65FN2M0CAC18) || \
defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || defined(CPU_MK66FN2M0VLQ18) || \
defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18) || defined(CPU_MK70FN1M0VMF12) || \
defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || defined(CPU_MK70FN1M0VMJ12) || \
defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15) || defined(CPU_MKV30F128VFM10) || \
defined(CPU_MKV30F64VFM10) || defined(CPU_MKV30F128VLF10) || defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || \
defined(CPU_MKV30F64VLH10) || defined(CPU_MKV31F128VLH10) || defined(CPU_MKV31F128VLL10) || defined(CPU_MKV31F256VLH12) || \
defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31F512VLH12) || defined(CPU_MKV31F512VLL12) || defined(CPU_MKV44F128VLH15) || \
defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15) || defined(CPU_MKV46F128VLH15) || defined(CPU_MKV46F128VLL15) || \
defined(CPU_MKV46F256VLH15) || defined(CPU_MKV46F256VLL15)
/* @brief Define the size of hardware buffer */
#define FSL_FEATURE_DAC_BUFFER_SIZE (16)
/* @brief Define has watermark event detection or not. */
#define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (1)
#elif defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || \
defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || \
defined(CPU_MKL05Z32VFM4) || defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4) || defined(CPU_MKL13Z64VFM4) || \
defined(CPU_MKL13Z128VFM4) || defined(CPU_MKL13Z256VFM4) || defined(CPU_MKL13Z64VFT4) || defined(CPU_MKL13Z128VFT4) || \
defined(CPU_MKL13Z256VFT4) || defined(CPU_MKL13Z64VLH4) || defined(CPU_MKL13Z128VLH4) || defined(CPU_MKL13Z256VLH4) || \
defined(CPU_MKL13Z64VMP4) || defined(CPU_MKL13Z128VMP4) || defined(CPU_MKL13Z256VMP4) || defined(CPU_MKL23Z64VFM4) || \
defined(CPU_MKL23Z128VFM4) || defined(CPU_MKL23Z256VFM4) || defined(CPU_MKL23Z64VFT4) || defined(CPU_MKL23Z128VFT4) || \
defined(CPU_MKL23Z256VFT4) || defined(CPU_MKL23Z64VLH4) || defined(CPU_MKL23Z128VLH4) || defined(CPU_MKL23Z256VLH4) || \
defined(CPU_MKL23Z64VMP4) || defined(CPU_MKL23Z128VMP4) || defined(CPU_MKL23Z256VMP4) || defined(CPU_MKL25Z32VFM4) || \
defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || \
defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || \
defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4) || defined(CPU_MKL26Z256VLK4) || \
defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || defined(CPU_MKL26Z256VMC4) || \
defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || defined(CPU_MKL33Z256VMP4) || \
defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z64VMP4) || \
defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4) || defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || \
defined(CPU_MKL46Z128VLL4) || defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4)
/* @brief Define the size of hardware buffer */
#define FSL_FEATURE_DAC_BUFFER_SIZE (2)
/* @brief Define has watermark event detection or not. */
#define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (0)
#else
#error "No valid CPU defined!"
#endif
#endif /* __FSL_DAC_FEATURES_H__ */
/*******************************************************************************
* EOF
******************************************************************************/

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/*
* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fsl_dac_hal.h"
/*FUNCTION*********************************************************************
*
* Function Name : DAC_HAL_Init
* Description : Reset all the configurable registers to be reset state for DAC.
* It should be called before configuring the DAC module.
*
*END*************************************************************************/
void DAC_HAL_Init(uint32_t baseAddr)
{
/* DACx_DATL and DACx_DATH */
HW_DAC_DATnL_WR(baseAddr, 0U, 0U); HW_DAC_DATnH_WR(baseAddr, 0U, 0U);
HW_DAC_DATnL_WR(baseAddr, 1U, 0U); HW_DAC_DATnH_WR(baseAddr, 1U, 0U);
#if (HW_DAC_DATnL_COUNT > 2U)
HW_DAC_DATnL_WR(baseAddr, 2U, 0U); HW_DAC_DATnH_WR(baseAddr, 2U, 0U);
HW_DAC_DATnL_WR(baseAddr, 3U, 0U); HW_DAC_DATnH_WR(baseAddr, 3U, 0U);
HW_DAC_DATnL_WR(baseAddr, 4U, 0U); HW_DAC_DATnH_WR(baseAddr, 4U, 0U);
HW_DAC_DATnL_WR(baseAddr, 5U, 0U); HW_DAC_DATnH_WR(baseAddr, 5U, 0U);
HW_DAC_DATnL_WR(baseAddr, 6U, 0U); HW_DAC_DATnH_WR(baseAddr, 6U, 0U);
HW_DAC_DATnL_WR(baseAddr, 7U, 0U); HW_DAC_DATnH_WR(baseAddr, 7U, 0U);
HW_DAC_DATnL_WR(baseAddr, 8U, 0U); HW_DAC_DATnH_WR(baseAddr, 8U, 0U);
HW_DAC_DATnL_WR(baseAddr, 9U, 0U); HW_DAC_DATnH_WR(baseAddr, 9U, 0U);
HW_DAC_DATnL_WR(baseAddr, 10U, 0U); HW_DAC_DATnH_WR(baseAddr, 10U, 0U);
HW_DAC_DATnL_WR(baseAddr, 11U, 0U); HW_DAC_DATnH_WR(baseAddr, 11U, 0U);
HW_DAC_DATnL_WR(baseAddr, 12U, 0U); HW_DAC_DATnH_WR(baseAddr, 12U, 0U);
HW_DAC_DATnL_WR(baseAddr, 13U, 0U); HW_DAC_DATnH_WR(baseAddr, 13U, 0U);
HW_DAC_DATnL_WR(baseAddr, 14U, 0U); HW_DAC_DATnH_WR(baseAddr, 14U, 0U);
HW_DAC_DATnL_WR(baseAddr, 15U, 0U); HW_DAC_DATnH_WR(baseAddr, 15U, 0U);
#endif /* HW_DAC_DATnL_COUNT */
/* DACx_SR. */
HW_DAC_SR_WR(baseAddr, 0U); /* Clear all flags. */
/* DACx_C0. */
HW_DAC_C0_WR(baseAddr, 0U);
/* DACx_C1. */
HW_DAC_C1_WR(baseAddr, 0U);
/* DACx_C2. */
HW_DAC_C2_WR(baseAddr, 15U);
}
/*FUNCTION*********************************************************************
*
* Function Name : DAC_HAL_SetBuffValue
* Description : Set the value assembled by the low 8 bits and high 4
* bits of 12-bit DAC item in buffer.
*
*END*************************************************************************/
void DAC_HAL_SetBuffValue(uint32_t baseAddr, uint8_t index, uint16_t value)
{
assert(index < HW_DAC_DATnL_COUNT);
BW_DAC_DATnL_DATA0(baseAddr, index, (uint8_t)(0xFFU & value) );
BW_DAC_DATnH_DATA1(baseAddr, index, (uint8_t)((0xF00U & value)>>8U) );
}
/*FUNCTION*********************************************************************
*
* Function Name : DAC_HAL_GetBuffValue
* Description : Get the value assembled by the low 8 bits and high 4
* bits of 12-bit DAC item in buffer.
*
*END*************************************************************************/
uint16_t DAC_HAL_GetBuffValue(uint32_t baseAddr, uint8_t index)
{
assert(index < HW_DAC_DATnL_COUNT);
uint16_t ret16;
ret16 = BR_DAC_DATnH_DATA1(baseAddr, index);
ret16 <<= 8U;
ret16 |= BR_DAC_DATnL_DATA0(baseAddr, index);
return ret16;
}
/******************************************************************************
* EOF
*****************************************************************************/

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/*
* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __FSL_DAC_HAL_H__
#define __FSL_DAC_HAL_H__
#include <stdint.h>
#include <stdbool.h>
#include <assert.h>
#include "fsl_device_registers.h"
#include "fsl_dac_features.h"
/*!
* @addtogroup dac_hal
* @{
*/
/******************************************************************************
* Definitions
*****************************************************************************/
/*!
* @brief DAC status return codes.
*/
typedef enum _dac_status
{
kStatus_DAC_Success = 0U, /*!< Success. */
kStatus_DAC_InvalidArgument = 1U, /*!< Invalid argument existed. */
kStatus_DAC_Failed = 2U /*!< Execution failed. */
} dac_status_t;
/*!
* @brief Defines the type of selection for DAC module's reference voltage source.
*
* See the appropriate SoC Reference Manual for actual connections.
*/
typedef enum _dac_ref_volt_src_mode
{
kDacRefVoltSrcOfVref1 = 0U, /*!< Select DACREF_1 as the reference voltage. */
kDacRefVoltSrcOfVref2 = 1U, /*!< Select DACREF_2 as the reference voltage. */
} dac_ref_volt_src_mode_t;
/*!
* @brief Defines the type of selection for DAC module trigger mode.
*/
typedef enum _dac_trigger_mode
{
kDacTriggerByHardware = 0U, /*!< Select hardware trigger. */
kDacTriggerBySoftware = 1U /*!< Select software trigger. */
} dac_trigger_mode_t;
/*!
* @brief Defines the type of selection for buffer watermark mode.
*
* If the buffer feature for DAC module is enabled, a watermark event will
* occur when the buffer index hits the watermark.
*/
typedef enum _dac_buff_watermark_mode
{
kDacBuffWatermarkFromUpperAs1Word = 0U, /*!< Select 1 word away from the upper of buffer. */
kDacBuffWatermarkFromUpperAs2Word = 1U, /*!< Select 2 word away from the upper of buffer. */
kDacBuffWatermarkFromUpperAs3Word = 2U, /*!< Select 3 word away from the upper of buffer. */
kDacBuffWatermarkFromUpperAs4Word = 3U, /*!< Select 4 word away from the upper of buffer. */
} dac_buff_watermark_mode_t;
/*!
* @brief Defines the type of selection for buffer work mode.
*
* There are three kinds of work modes when the DAC buffer is enabled.
* Normal mode - When the buffer index hits the upper level, it
* starts (0) on the next trigger.
* Swing mode - When the buffer index hits the upper level, it goes backward to
* the start and is reduced one-by-one on the next trigger. When the buffer index
* hits the start, it goes backward to the upper level and increases one-by-one
* on the next trigger.
* One-Time-Scan mode - The buffer index can only be increased on the next trigger.
* When the buffer index hits the upper level, it is not updated by the trigger.
* FIFO mode
*/
typedef enum _dac_buff_work_mode
{
kDacBuffWorkAsNormalMode = 0U, /*!< Buffer works as Normal. */
kDacBuffWorkAsSwingMode = 1U, /*!< Buffer works as swing. */
kDacBuffWorkAsOneTimeScanMode = 2U, /*!< Buffer works as one time scan.*/
kDacBuffWorkAsFIFOMode = 3U /*!< Buffer works as FIFO.*/
} dac_buff_work_mode_t;
#if defined(__cplusplus)
extern "C" {
#endif
/*******************************************************************************
* API
******************************************************************************/
/*!
* @brief Resets all configurable registers to be in the reset state for DAC.
*
* This function resets all configurable registers to be in the reset state for DAC.
* It should be called before configuring the DAC module.
*
* @param baseAddr The DAC peripheral base address.
*/
void DAC_HAL_Init(uint32_t baseAddr);
/*!
* @brief Sets the 12-bit value for the DAC items in the buffer.
*
* This function sets the value assembled by the low 8 bits and high 4
* bits of 12-bit DAC item in the buffer.
*
* @param baseAddr The DAC peripheral base address.
* @param index Buffer index.
* @param value Setting value.
*/
void DAC_HAL_SetBuffValue(uint32_t baseAddr, uint8_t index, uint16_t value);
/*!
* @brief Gets the 12-bit value from the DAC item in the buffer.
*
* This function gets the value assembled by the low 8 bits and high 4
* bits of 12-bit DAC item in the buffer.
*
* @param baseAddr The DAC peripheral base address.
* @param index Buffer index.
* @return Current setting value.
*/
uint16_t DAC_HAL_GetBuffValue(uint32_t baseAddr, uint8_t index);
/*!
* @brief Clears the flag of the DAC buffer read pointer.
*
* This function clears the flag of the DAC buffer read pointer when it hits the
* bottom position.
*
* @param baseAddr The DAC peripheral base address.
*/
static inline void DAC_HAL_ClearBuffIndexUpperFlag(uint32_t baseAddr)
{
BW_DAC_SR_DACBFRPBF(baseAddr, 0U);
}
/*!
* @brief Gets the flag of DAC buffer read pointer when it hits the bottom position.
*
* This function gets the flag of DAC buffer read pointer when it hits the
* bottom position.
*
* @param baseAddr The DAC peripheral base address.
* @return Assertion of indicated event.
*/
static inline bool DAC_HAL_GetBuffIndexUpperFlag(uint32_t baseAddr)
{
return ( 1U == BR_DAC_SR_DACBFRPBF(baseAddr) );
}
/*!
* @brief Clears the flag of the DAC buffer read pointer when it hits the top position.
*
* This function clears the flag of the DAC buffer read pointer when it hits the
* top position.
*
* @param baseAddr The DAC peripheral base address.
*/
static inline void DAC_HAL_ClearBuffIndexStartFlag(uint32_t baseAddr)
{
BW_DAC_SR_DACBFRPTF(baseAddr, 0U);
}
/*!
* @brief Gets the flag of the DAC buffer read pointer when it hits the top position.
*
* This function gets the flag of the DAC buffer read pointer when it hits the
* top position.
*
* @param baseAddr The DAC peripheral base address.
* @return Assertion of indicated event.
*/
static inline bool DAC_HAL_GetBuffIndexStartFlag(uint32_t baseAddr)
{
return ( 1U == BR_DAC_SR_DACBFRPTF(baseAddr) );
}
#if FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION
/*!
* @brief Gets the flag of the DAC buffer read pointer when it hits the watermark position.
*
* This function gets the flag of the DAC buffer read pointer when it hits the
* watermark position.
*
* @param baseAddr The DAC peripheral base address.
* @return Assertion of indicated event.
*/
static inline bool DAC_HAL_GetBuffIndexWatermarkFlag(uint32_t baseAddr)
{
return ( 1U == BR_DAC_SR_DACBFWMF(baseAddr) );
}
/*!
* @brief Clears the flag of the DAC buffer read pointer when it hits the watermark position.
*
* This function clears the flag of the DAC buffer read pointer when it hits the
* watermark position.
*
* @param baseAddr The DAC peripheral base address.
* @return Assertion of indicated event.
*/
static inline void DAC_HAL_ClearBuffIndexWatermarkFlag(uint32_t baseAddr)
{
BW_DAC_SR_DACBFWMF(baseAddr, 0U);
}
#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION */
/*!
* @brief Enables the Programmable Reference Generator.
*
* This function enables the Programmable Reference Generator. Then the
* DAC system is enabled.
*
* @param baseAddr The DAC peripheral base address.
*/
static inline void DAC_HAL_Enable(uint32_t baseAddr)
{
BW_DAC_C0_DACEN(baseAddr, 1U);
}
/*!
* @brief Disables the Programmable Reference Generator.
*
* This function disables the Programmable Reference Generator. Then the
* DAC system is disabled.
*
* @param baseAddr The DAC peripheral base address.
*/
static inline void DAC_HAL_Disable(uint32_t baseAddr)
{
BW_DAC_C0_DACEN(baseAddr, 0U);
}
/*!
* @brief Sets the reference voltage source mode for the DAC module.
*
* This function sets the reference voltage source mode for the DAC module.
*
* @param baseAddr The DAC peripheral base address.
* @param mode Selection of enumeration mode. See to "dac_ref_volt_src_mode_t".
*/
static inline void DAC_HAL_SetRefVoltSrcMode(uint32_t baseAddr, dac_ref_volt_src_mode_t mode)
{
BW_DAC_C0_DACRFS(baseAddr, ((kDacRefVoltSrcOfVref1==mode)?0U:1U) );
}
/*!
* @brief Sets the trigger mode for the DAC module.
*
* This function sets the trigger mode for the DAC module.
*
* @param baseAddr The DAC peripheral base address.
* @param mode Selection of enumeration mode. See to "dac_trigger_mode_t".
*/
static inline void DAC_HAL_SetTriggerMode(uint32_t baseAddr, dac_trigger_mode_t mode)
{
BW_DAC_C0_DACTRGSEL(baseAddr, ((kDacTriggerByHardware==mode)?0U:1U) );
}
/*!
* @brief Triggers the converter with software.
*
* This function triggers the converter with software. If the DAC software
* trigger is selected and buffer enabled, calling this API advances the
* buffer read pointer once.
*
* @param baseAddr The DAC peripheral base address.
*/
static inline void DAC_HAL_SetSoftTriggerCmd(uint32_t baseAddr)
{
BW_DAC_C0_DACSWTRG(baseAddr, 1U);
}
/*!
* @brief Switches to enable working in low power mode for the DAC module.
*
* This function switches to enable working in low power mode for the DAC module.
*
* @param baseAddr The DAC peripheral base address.
* @param enable Switcher to assert the feature.
*/
static inline void DAC_HAL_SetLowPowerCmd(uint32_t baseAddr, bool enable)
{
BW_DAC_C0_LPEN(baseAddr, (enable?1U:0U) );
}
#if FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION
/*!
* @brief Switches to enable the interrupt when buffer read pointer hits the watermark position.
*
* This function switches to enable the interrupt when the buffer read pointer hits
* the watermark position.
*
* @param baseAddr The DAC peripheral base address.
* @param enable Switcher to assert the feature.
*/
static inline void DAC_HAL_SetBuffIndexWatermarkIntCmd(uint32_t baseAddr, bool enable)
{
BW_DAC_C0_DACBWIEN(baseAddr, (enable?1U:0U) );
}
#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION */
/*!
* @brief Switches to enable the interrupt when the buffer read pointer hits the top position.
*
* This function switches to enable the interrupt when the buffer read pointer hits
* the top position.
*
* @param baseAddr The DAC peripheral base address.
* @param enable Switcher to assert the feature.
*/
static inline void DAC_HAL_SetBuffIndexStartIntCmd(uint32_t baseAddr, bool enable)
{
BW_DAC_C0_DACBTIEN(baseAddr, (enable?1U:0U) );
}
/*!
* @brief Switches to enable the interrupt when the buffer read pointer hits the bottom position.
*
* This function switches to enable the interrupt when the buffer read pointer hits
* the bottom position.
*
* @param baseAddr The DAC peripheral base address.
* @param enable Switcher to assert the feature.
*/
static inline void DAC_HAL_SetBuffIndexUpperIntCmd(uint32_t baseAddr, bool enable)
{
BW_DAC_C0_DACBBIEN(baseAddr, (enable?1U:0U) );
}
/*!
* @brief Switches to enable the DMA for DAC.
*
* This function switches to enable the DMA for the DAC module. When the DMA is enabled,
* DMA request is generated by the original interrupts, which are
* not presented on this module at the same time.
*
* @param baseAddr The DAC peripheral base address.
* @param enable Switcher to assert the feature.
*/
static inline void DAC_HAL_SetDmaCmd(uint32_t baseAddr, bool enable)
{
BW_DAC_C1_DMAEN(baseAddr, (enable?1U:0U) );
}
#if FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION
/*!
* @brief Sets the watermark mode of the buffer for the DAC module.
*
* This function sets the watermark mode of the buffer for the DAC module.
*
* @param baseAddr The DAC peripheral base address.
* @param mode Selection of enumeration mode. See to "dac_buff_watermark_mode_t".
*/
static inline void DAC_HAL_SetBuffWatermarkMode(uint32_t baseAddr, dac_buff_watermark_mode_t mode)
{
BW_DAC_C1_DACBFWM(baseAddr, (uint8_t)mode);
}
#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION */
/*!
* @brief Sets the work mode of the buffer for the DAC module.
*
* This function sets the work mode of the buffer for the DAC module.
*
* @param baseAddr The DAC peripheral base address.
* @param mode Selection of enumeration mode. See to "dac_buff_work_mode_t".
*/
static inline void DAC_HAL_SetBuffWorkMode(uint32_t baseAddr, dac_buff_work_mode_t mode)
{
BW_DAC_C1_DACBFMD(baseAddr, (uint8_t)mode );
}
/*!
* @brief Switches to enable the buffer for the DAC module.
*
* This function switches to enable the buffer for the DAC module.
*
* @param baseAddr The DAC peripheral base address.
* @param enable Switcher to assert the feature.
*/
static inline void DAC_HAL_SetBuffCmd(uint32_t baseAddr, bool enable)
{
BW_DAC_C1_DACBFEN(baseAddr, (enable?1U:0U) );
}
/*!
* @brief Gets the buffer index upper limitation for the DAC module.
*
* This function gets the upper buffer index upper limitation for the DAC module.
*
* @param baseAddr The DAC peripheral base address.
* @return Value of buffer index upper limitation.
*/
static inline uint8_t DAC_HAL_GetBuffUpperIndex(uint32_t baseAddr)
{
return BR_DAC_C2_DACBFUP(baseAddr);
}
/*!
* @brief Sets the buffer index upper limitation for the DAC module.
*
* This function sets the upper buffer index upper limitation for the DAC module.
*
* @param baseAddr The DAC peripheral base address.
* @param index Setting value of upper limitation for buffer index.
*/
static inline void DAC_HAL_SetBuffUpperIndex(uint32_t baseAddr, uint8_t index)
{
assert(index < HW_DAC_DATnL_COUNT);
BW_DAC_C2_DACBFUP(baseAddr , index);
}
/*!
* @brief Gets the current buffer index upper limitation for the DAC module.
*
* This function gets the current buffer index for the DAC module.
*
* @param baseAddr The DAC peripheral base address.
* @return Value of current buffer index.
*/
static inline uint8_t DAC_HAL_GetBuffCurrentIndex(uint32_t baseAddr)
{
return BR_DAC_C2_DACBFRP(baseAddr);
}
/*!
* @brief Sets the buffer index for the DAC module.
*
* This function sets the upper buffer index for the DAC module.
*
* @param baseAddr the DAC peripheral base address.
* @param index Setting value for buffer index.
*/
static inline void DAC_HAL_SetBuffCurrentIndex(uint32_t baseAddr, uint8_t index)
{
assert(index < HW_DAC_DATnL_COUNT);
BW_DAC_C2_DACBFRP(baseAddr, index);
}
#if defined(__cplusplus)
extern }
#endif
/*!
* @}
*/
#endif /* __FSL_DAC_HAL_H__ */
/******************************************************************************
* EOF
*****************************************************************************/

150
libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/dmamux/fsl_dmamux_features.h
View File

@ -1,78 +1,114 @@
/*
* Copyright (c) 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
** ###################################################################
** Version: rev. 1.0, 2014-05-14
** Build: b140515
**
** Abstract:
** Chip specific module features.
**
** Copyright: 2014 Freescale Semiconductor, Inc.
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** Revisions:
** - rev. 1.0 (2014-05-14)
** Customer release.
**
** ###################################################################
*/
#if !defined(__FSL_DMAMUX_FEATURES_H__)
#define __FSL_DMAMUX_FEATURES_H__
#if defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \
defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \
defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \
defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \
defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || \
defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \
defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || \
defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) || defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || \
defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || \
defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || defined(CPU_MKL05Z32VFM4) || defined(CPU_MKL05Z16VLF4) || \
defined(CPU_MKL05Z32VLF4) || defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || \
defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || \
defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || \
defined(CPU_MKL25Z128VLK4) || defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || \
defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4)
/* @brief Number of DMA channels (related to number of register CHCFGn).*/
#if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \
defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || \
defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || \
defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || \
defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || \
defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || \
defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || \
defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || \
defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) || \
defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || \
defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || \
defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || \
defined(CPU_MKL05Z32VFM4) || defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4) || defined(CPU_MKL13Z64VFM4) || \
defined(CPU_MKL13Z128VFM4) || defined(CPU_MKL13Z256VFM4) || defined(CPU_MKL13Z64VFT4) || defined(CPU_MKL13Z128VFT4) || \
defined(CPU_MKL13Z256VFT4) || defined(CPU_MKL13Z64VLH4) || defined(CPU_MKL13Z128VLH4) || defined(CPU_MKL13Z256VLH4) || \
defined(CPU_MKL13Z64VMP4) || defined(CPU_MKL13Z128VMP4) || defined(CPU_MKL13Z256VMP4) || defined(CPU_MKL23Z64VFM4) || \
defined(CPU_MKL23Z128VFM4) || defined(CPU_MKL23Z256VFM4) || defined(CPU_MKL23Z64VFT4) || defined(CPU_MKL23Z128VFT4) || \
defined(CPU_MKL23Z256VFT4) || defined(CPU_MKL23Z64VLH4) || defined(CPU_MKL23Z128VLH4) || defined(CPU_MKL23Z256VLH4) || \
defined(CPU_MKL23Z64VMP4) || defined(CPU_MKL23Z128VMP4) || defined(CPU_MKL23Z256VMP4) || defined(CPU_MKL25Z32VFM4) || \
defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || \
defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || \
defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4) || defined(CPU_MKL26Z256VLK4) || \
defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || defined(CPU_MKL26Z256VMC4) || \
defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || defined(CPU_MKL33Z256VMP4) || \
defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z64VMP4) || \
defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4) || defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || \
defined(CPU_MKL46Z128VLL4) || defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4) || \
defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || defined(CPU_MKV30F128VLF10) || defined(CPU_MKV30F64VLF10) || \
defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10) || defined(CPU_MKV31F128VLH10) || defined(CPU_MKV31F128VLL10)
/* @brief Number of DMA channels (related to number of register CHCFGn). */
#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (4)
/* @brief Total number of DMA channels on all modules.*/
/* @brief Total number of DMA channels on all modules. */
#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (HW_DMAMUX_INSTANCE_COUNT * 4)
#elif defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || \
defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12) || defined(CPU_MK24FN1M0VDC12) || \
defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FN1M0VDC12) || \
defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VMD12) || \
defined(CPU_MK64FX512VMD12) || defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31FN512VLH12) || \
defined(CPU_MKV31F512VLL12) || defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || \
defined(CPU_MK70FX512VMF15) || defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || \
defined(CPU_MK70FX512VMJ15) || defined(CPU_MK70FN1M0VMJ12WS) || defined(CPU_MK70FX512VMJ12WS) || defined(CPU_MK70FN1M0VMJ15WS)
/* @brief Number of DMA channels (related to number of register CHCFGn).*/
defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK24FN256VDC12) || defined(CPU_MK63FN1M0VLQ12) || \
defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || \
defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VMD12) || \
defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || \
defined(CPU_MK70FX512VMF15) || defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || \
defined(CPU_MK70FX512VMJ15) || defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31F512VLH12) || \
defined(CPU_MKV31F512VLL12) || defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLH15) || \
defined(CPU_MKV40F256VLL15) || defined(CPU_MKV40F64VLH15) || defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || \
defined(CPU_MKV43F64VLH15) || defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15) || \
defined(CPU_MKV45F128VLH15) || defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLH15) || defined(CPU_MKV45F256VLL15) || \
defined(CPU_MKV46F128VLH15) || defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLH15) || defined(CPU_MKV46F256VLL15)
/* @brief Number of DMA channels (related to number of register CHCFGn). */
#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (16)
/* @brief Total number of DMA channels on all modules.*/
/* @brief Total number of DMA channels on all modules. */
#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (HW_DMAMUX_INSTANCE_COUNT * 16)
#elif defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || \
defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18)
/* @brief Number of DMA channels (related to number of register CHCFGn).*/
/* @brief Number of DMA channels (related to number of register CHCFGn). */
#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (32)
/* @brief Total number of DMA channels on all modules.*/
/* @brief Total number of DMA channels on all modules. */
#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (HW_DMAMUX_INSTANCE_COUNT * 32)
#else
#error "No valid CPU defined!"
#endif
#endif /* __FSL_DMAMUX_FEATURES_H__*/
#endif /* __FSL_DMAMUX_FEATURES_H__ */
/*******************************************************************************
* EOF
******************************************************************************/

7
libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/dmamux/fsl_dmamux_hal.c
View File

@ -39,15 +39,14 @@
* Description : Initialize the dmamux module to the reset state.
*
*END**************************************************************************/
void dmamux_hal_init(uint8_t module)
void DMAMUX_HAL_Init(uint32_t baseAddr)
{
assert(module < HW_DMAMUX_INSTANCE_COUNT);
int i;
for (i = 0; i < FSL_FEATURE_DMAMUX_MODULE_CHANNEL; i++)
{
BW_DMAMUX_CHCFGn_ENBL(module, i, 0U);
BW_DMAMUX_CHCFGn_SOURCE(module, i, 0U);
BW_DMAMUX_CHCFGn_ENBL(baseAddr, i, 0U);
BW_DMAMUX_CHCFGn_SOURCE(baseAddr, i, 0U);
}
}

64
libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/dmamux/fsl_dmamux_hal.h
View File

@ -70,67 +70,40 @@ extern "C" {
*
* Initializes the DMAMUX module to the reset state.
*
* @param module DMAMUX module index
* @param baseAddr Register base address for DMAMUX module.
*/
void dmamux_hal_init(uint8_t module);
void DMAMUX_HAL_Init(uint32_t baseAddr);
/*!
* @brief Enables the DMAMUX channel.
* @brief Enables/Disables the DMAMUX channel.
*
* Enables the hardware request. If enabled, the hardware request is sent to
* the corresponding DMA channel.
*
* @param module DMAMUX module.
* @param channel DMAMUX channel.
* @param baseAddr Register base address for DMAMUX module.
* @param channel DMAMUX channel number.
* @param enable Enables (true) or Disables (false) DMAMUX channel.
*/
static inline void dmamux_hal_enable_channel(uint8_t module, uint8_t channel)
static inline void DMAMUX_HAL_SetChannelCmd(uint32_t baseAddr, uint32_t channel, bool enable)
{
assert(module < HW_DMAMUX_INSTANCE_COUNT);
assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
BW_DMAMUX_CHCFGn_ENBL(module, channel, 1U);
BW_DMAMUX_CHCFGn_ENBL(baseAddr, channel, enable);
}
/*!
* @brief Disables the DMAMUX channel.
*
* Disable hardware request. If disabled, the hardware request is not sent to
* the corresponding DMA channel.
*
* @param module DMAMUX module.
* @param channel DMAMUX channel.
*/
static inline void dmamux_hal_disable_channel(uint8_t module, uint8_t channel)
{
assert(module < HW_DMAMUX_INSTANCE_COUNT);
assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
BW_DMAMUX_CHCFGn_ENBL(module, channel, 0U);
}
/*!
* @brief Enables the period trigger.
* @brief Enables/Disables the period trigger.
*
* @param module DMAMUX module.
* @param channel DMAMUX channel.
* @param baseAddr Register base address for DMAMUX module.
* @param channel DMAMUX channel number.
* @param enable Enables (true) or Disables (false) period trigger.
*/
static inline void dmamux_hal_enable_period_trigger(uint8_t module, uint8_t channel)
static inline void DMAMUX_HAL_SetPeriodTriggerCmd(uint32_t baseAddr, uint32_t channel, bool enable)
{
assert(module < HW_DMAMUX_INSTANCE_COUNT);
assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
BW_DMAMUX_CHCFGn_TRIG(module, channel, 1U);
BW_DMAMUX_CHCFGn_TRIG(baseAddr, channel, enable);
}
/*!
* @brief Disables the period trigger.
*
* @param module DMAMUX module.
* @param channel DMAMUX channel.
*/
static inline void dmamux_hal_disable_period_trigger(uint8_t module, uint8_t channel)
{
assert(module < HW_DMAMUX_INSTANCE_COUNT);
assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
BW_DMAMUX_CHCFGn_TRIG(module, channel, 0U);
}
/*!
* @brief Configures the DMA request for the DMAMUX channel.
@ -138,15 +111,14 @@ static inline void dmamux_hal_disable_period_trigger(uint8_t module, uint8_t cha
* Sets the trigger source for the DMA channel. The trigger source is in the file
* fsl_dma_request.h.
*
* @param module DMAMUX module.
* @param channel DMAMUX channel.
* @param baseAddr Register base address for DMAMUX module.
* @param channel DMAMUX channel number.
* @param source DMA request source.
*/
static inline void dmamux_hal_set_trigger_source(uint8_t module, uint8_t channel, uint8_t source)
static inline void DMAMUX_HAL_SetTriggerSource(uint32_t baseAddr, uint32_t channel, uint8_t source)
{
assert(module < HW_DMAMUX_INSTANCE_COUNT);
assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
BW_DMAMUX_CHCFGn_SOURCE(module, channel, source);
BW_DMAMUX_CHCFGn_SOURCE(baseAddr, channel, source);
}
/* @} */

572
libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/dspi/fsl_dspi_features.h
View File

@ -1,365 +1,247 @@
/*
* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
** ###################################################################
** Version: rev. 1.0, 2014-05-14
** Build: b140515
**
** Abstract:
** Chip specific module features.
**
** Copyright: 2014 Freescale Semiconductor, Inc.
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** Revisions:
** - rev. 1.0 (2014-05-14)
** Customer release.
**
** ###################################################################
*/
#if !defined(__FSL_DSPI_FEATURES_H__)
#define __FSL_DSPI_FEATURES_H__
#if defined(CPU_MK10DN512VLK10) || defined(CPU_MK10DN512VMB10) || defined(CPU_MK10DX128VMP5) || defined(CPU_MK10DN128VMP5) || \
defined(CPU_MK10DX64VMP5) || defined(CPU_MK10DN64VMP5) || defined(CPU_MK10DX32VMP5) || defined(CPU_MK10DN32VMP5) || \
defined(CPU_MK10DX128VLH5) || defined(CPU_MK10DN128VLH5) || defined(CPU_MK10DX64VLH5) || defined(CPU_MK10DN64VLH5) || \
defined(CPU_MK10DX32VLH5) || defined(CPU_MK10DN32VLH5) || defined(CPU_MK10DX128VFT5) || defined(CPU_MK10DN128VFT5) || \
defined(CPU_MK10DX64VFT5) || defined(CPU_MK10DN64VFT5) || defined(CPU_MK10DX32VFT5) || defined(CPU_MK10DN32VFT5) || \
defined(CPU_MK10DX128VLF5) || defined(CPU_MK10DN128VLF5) || defined(CPU_MK10DX64VLF5) || defined(CPU_MK10DN64VLF5) || \
defined(CPU_MK10DX32VLF5) || defined(CPU_MK10DN32VLF5) || defined(CPU_MK10DX64VLH7) || defined(CPU_MK10DX128VLH7) || \
defined(CPU_MK10DX256VLH7) || defined(CPU_MK10DX64VLK7) || defined(CPU_MK10DX128VLK7) || defined(CPU_MK10DX256VLK7) || \
defined(CPU_MK10DX64VMB7) || defined(CPU_MK10DX128VMB7) || defined(CPU_MK10DX256VMB7) || defined(CPU_MK10DN512ZVLK10) || \
defined(CPU_MK10DN512ZVMB10) || defined(CPU_MK20DN512VLK10) || defined(CPU_MK20DN512VMB10) || defined(CPU_MK20DX128VMP5) || \
defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || defined(CPU_MK20DX32VMP5) || \
defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || defined(CPU_MK20DX64VLH5) || \
defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || defined(CPU_MK20DX128VFT5) || \
defined(CPU_MK20DN128VFT5) || defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || \
defined(CPU_MK20DN32VFT5) || defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || \
defined(CPU_MK20DN64VLF5) || defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) || defined(CPU_MK20DX64VLH7) || \
defined(CPU_MK20DX128VLH7) || defined(CPU_MK20DX256VLH7) || defined(CPU_MK20DX64VLK7) || defined(CPU_MK20DX128VLK7) || \
defined(CPU_MK20DX256VLK7) || defined(CPU_MK20DX64VMB7) || defined(CPU_MK20DX128VMB7) || defined(CPU_MK20DX256VMB7) || \
defined(CPU_MK20DN512ZVLK10) || defined(CPU_MK20DX256ZVLK10) || defined(CPU_MK20DN512ZVMB10) || defined(CPU_MK20DX256ZVMB10) || \
defined(CPU_MK22FX512VLH12) || defined(CPU_MK22FN1M0VLH12) || defined(CPU_MK22FX512VLK12) || defined(CPU_MK22FN1M0VLK12) || \
defined(CPU_MK30DN512VLK10) || defined(CPU_MK30DN512VMB10) || defined(CPU_MK30DX64VLH7) || defined(CPU_MK30DX128VLH7) || \
defined(CPU_MK30DX256VLH7) || defined(CPU_MK30DX64VLK7) || defined(CPU_MK30DX128VLK7) || defined(CPU_MK30DX256VLK7) || \
defined(CPU_MK30DX64VMB7) || defined(CPU_MK30DX128VMB7) || defined(CPU_MK30DX256VMB7) || defined(CPU_MK30DN512ZVLK10) || \
defined(CPU_MK30DN512ZVMB10) || defined(CPU_MK40DN512VLK10) || defined(CPU_MK40DN512VMB10) || defined(CPU_MK40DX64VLH7) || \
defined(CPU_MK40DX128VLH7) || defined(CPU_MK40DX256VLH7) || defined(CPU_MK40DX64VLK7) || defined(CPU_MK40DX128VLK7) || \
defined(CPU_MK40DX256VLK7) || defined(CPU_MK40DX64VMB7) || defined(CPU_MK40DX128VMB7) || defined(CPU_MK40DX256VMB7) || \
defined(CPU_MK40DN512ZVLK10) || defined(CPU_MK40DN512ZVMB10) || defined(CPU_MK50DX128CLH7) || defined(CPU_MK50DX256CLK10) || \
defined(CPU_MK50DX128CLK7) || defined(CPU_MK50DX256CLK7) || defined(CPU_MK50DX256CMB10) || defined(CPU_MK50DX128CMB7) || \
defined(CPU_MK50DX256CMB7) || defined(CPU_MK50DX256ZCLK10) || defined(CPU_MK50DX256ZCMB10) || defined(CPU_MK51DX128CLH7) || \
defined(CPU_MK51DX256CLK10) || defined(CPU_MK51DX128CLK7) || defined(CPU_MK51DX256CLK7) || defined(CPU_MK51DX256CMB10) || \
defined(CPU_MK51DX128CMB7) || defined(CPU_MK51DX256CMB7) || defined(CPU_MK51DX256ZCLK10) || defined(CPU_MK51DX256ZCMB10)
/* @brief Deserial serial peripheral interface (registers MCR, TCR, CTARn, CTARn_SLAVE, SR, RSER, PUSHR, PUSHR_SLAVE, POPR, TXFRn, RXFRn if non-zero, otherwise C1, S, C2, BR, D, M).*/
#define FSL_FEATURE_SPI_IS_DSPI (1)
/* @brief Has DMA support (register bit fields C2[RXDMAE] and C2[TXDMAE]). (Only valid for non-DSPI modules.)*/
#define FSL_FEATURE_SPI_HAS_DMA_SUPPORT (1)
/* @brief Receive/transmit FIFO size in number of items.*/
#define FSL_FEATURE_SPI_FIFO_SIZE (4)
/* @brief Maximum transfer data width in bits.*/
#define FSL_FEATURE_SPI_MAX_DATA_WIDTH (16)
/* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS] on DSPI modules.)*/
#define FSL_FEATURE_SPI_MAX_CHIP_SELECT_COUNT (6)
/* @brief Number of chip select pins. (Only valid for DSPI modules.)*/
#define FSL_FEATURE_SPI_CHIP_SELECT_COUNTn(x) \
#if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || \
defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || \
defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10)
/* @brief Receive/transmit FIFO size in number of items. */
#define FSL_FEATURE_DSPI_FIFO_SIZE (4)
#define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \
((x) == 0 ? (4) : (-1))
/* @brief Maximum transfer data width in bits. */
#define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16)
/* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */
#define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6)
/* @brief Number of chip select pins. */
#define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (4)
#define FSL_FEATURE_DSPI_CHIP_SELECT_COUNTn(x) \
((x) == 0 ? (4) : (-1))
/* @brief Has chip select strobe capability on the PCS5 pin. */
#define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1)
/* @brief Has 16-bit data transfer support. */
#define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1)
#elif defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || \
defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \
defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \
defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \
defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || \
defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || \
defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) || \
defined(CPU_MKV30F128VLF10) || defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10)
/* @brief Receive/transmit FIFO size in number of items. */
#define FSL_FEATURE_DSPI_FIFO_SIZE (4)
#define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \
((x) == 0 ? (4) : (-1))
/* @brief Maximum transfer data width in bits. */
#define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16)
/* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */
#define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6)
/* @brief Number of chip select pins. */
#define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (5)
#define FSL_FEATURE_DSPI_CHIP_SELECT_COUNTn(x) \
((x) == 0 ? (5) : (-1))
/* @brief Has chip select strobe capability on the PCS5 pin. */
#define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1)
/* @brief Has 16-bit data transfer support. */
#define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1)
#elif defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLL12) || \
defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLL12) || defined(CPU_MKV31F128VLL10) || defined(CPU_MKV31F256VLL12) || \
defined(CPU_MKV31F512VLL12)
/* @brief Receive/transmit FIFO size in number of items. */
#define FSL_FEATURE_DSPI_FIFO_SIZE (4)
#define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \
((x) == 0 ? (4) : \
((x) == 1 ? (1) : (-1)))
/* @brief Maximum transfer data width in bits. */
#define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16)
/* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */
#define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6)
/* @brief Number of chip select pins. */
#define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (6)
#define FSL_FEATURE_DSPI_CHIP_SELECT_COUNTn(x) \
((x) == 0 ? (6) : \
((x) == 1 ? (4) : (-1)))
/* @brief Has chip select strobe capability on the PCS5 pin. */
#define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1)
/* @brief Has 16-bit data transfer support. */
#define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1)
#elif defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VMP10) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VMP12) || \
defined(CPU_MK22FN512VLH12) || defined(CPU_MKV31F128VLH10) || defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F512VLH12)
/* @brief Receive/transmit FIFO size in number of items. */
#define FSL_FEATURE_DSPI_FIFO_SIZE (4)
#define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \
((x) == 0 ? (4) : \
((x) == 1 ? (1) : (-1)))
/* @brief Maximum transfer data width in bits. */
#define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16)
/* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */
#define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6)
/* @brief Number of chip select pins. */
#define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (5)
#define FSL_FEATURE_DSPI_CHIP_SELECT_COUNTn(x) \
((x) == 0 ? (5) : \
((x) == 1 ? (3) : (-1)))
/* @brief Has chip select strobe capability on the PCS5 pin. (Only valid for DSPI modules.)*/
#define FSL_FEATURE_SPI_HAS_CHIP_SELECT_STROBE (1)
/* @brief The data register name has postfix (L as low and H as high). (Only valid for non-DSPI modules.)*/
#define FSL_FEATURE_SPI_DATA_REGISTER_HAS_POSTFIX (0)
/* @brief Has 16-bit data transfer support.*/
#define FSL_FEATURE_SPI_FEATURE_16BIT_TRANSFERS (1)
#elif defined(CPU_MK10DN512VLL10) || defined(CPU_MK10DX128VLQ10) || defined(CPU_MK10DX256VLQ10) || defined(CPU_MK10DN512VLQ10) || \
defined(CPU_MK10DN512VMC10) || defined(CPU_MK10DX128VMD10) || defined(CPU_MK10DX256VMD10) || defined(CPU_MK10DN512VMD10) || \
defined(CPU_MK10DX128VLL7) || defined(CPU_MK10DX256VLL7) || defined(CPU_MK10DX128VML7) || defined(CPU_MK10DX256VML7) || \
defined(CPU_MK10FN1M0VLQ12) || defined(CPU_MK10FX512VLQ12) || defined(CPU_MK10FN1M0VMD12) || defined(CPU_MK10FX512VMD12) || \
defined(CPU_MK10DN512ZVLL10) || defined(CPU_MK10DN512ZVLQ10) || defined(CPU_MK10DX256ZVLQ10) || defined(CPU_MK10DX128ZVLQ10) || \
defined(CPU_MK10DN512ZVMC10) || defined(CPU_MK10DN512ZVMD10) || defined(CPU_MK10DX256ZVMD10) || defined(CPU_MK10DX128ZVMD10) || \
defined(CPU_MK20DN512VLL10) || defined(CPU_MK20DX128VLQ10) || defined(CPU_MK20DX256VLQ10) || defined(CPU_MK20DN512VLQ10) || \
defined(CPU_MK20DX256VMC10) || defined(CPU_MK20DN512VMC10) || defined(CPU_MK20DX128VMD10) || defined(CPU_MK20DX256VMD10) || \
defined(CPU_MK20DN512VMD10) || defined(CPU_MK20DX128VLL7) || defined(CPU_MK20DX256VLL7) || defined(CPU_MK20DX128VML7) || \
defined(CPU_MK20DX256VML7) || defined(CPU_MK20FN1M0VLQ12) || defined(CPU_MK20FX512VLQ12) || defined(CPU_MK20FN1M0VMD12) || \
defined(CPU_MK20FX512VMD12) || defined(CPU_MK20DN512ZVLL10) || defined(CPU_MK20DX256ZVLL10) || defined(CPU_MK20DN512ZVLQ10) || \
defined(CPU_MK20DX256ZVLQ10) || defined(CPU_MK20DX128ZVLQ10) || defined(CPU_MK20DN512ZVMC10) || defined(CPU_MK20DX256ZVMC10) || \
defined(CPU_MK20DN512ZVMD10) || defined(CPU_MK20DX256ZVMD10) || defined(CPU_MK20DX128ZVMD10) || defined(CPU_MK21FX512VLQ12) || \
defined(CPU_MK21FN1M0VLQ12) || defined(CPU_MK21FX512VLQ12WS) || defined(CPU_MK21FN1M0VLQ12WS) || defined(CPU_MK21FX512VMC12) || \
defined(CPU_MK21FN1M0VMC12) || defined(CPU_MK21FX512VMC12WS) || defined(CPU_MK21FN1M0VMC12WS) || defined(CPU_MK21FX512VMD12) || \
defined(CPU_MK21FN1M0VMD12) || defined(CPU_MK21FX512VMD12WS) || defined(CPU_MK21FN1M0VMD12WS) || defined(CPU_MK22FX512VLL12) || \
defined(CPU_MK22FN1M0VLL12) || defined(CPU_MK22FX512VLQ12) || defined(CPU_MK22FN1M0VLQ12) || defined(CPU_MK22FX512VMC12) || \
defined(CPU_MK22FN1M0VMC12) || defined(CPU_MK22FX512VMD12) || defined(CPU_MK22FN1M0VMD12) || defined(CPU_MK30DN512VLL10) || \
defined(CPU_MK30DX128VLQ10) || defined(CPU_MK30DX256VLQ10) || defined(CPU_MK30DN512VLQ10) || defined(CPU_MK30DN512VMC10) || \
defined(CPU_MK30DX128VMD10) || defined(CPU_MK30DX256VMD10) || defined(CPU_MK30DN512VMD10) || defined(CPU_MK30DX128VLL7) || \
defined(CPU_MK30DX256VLL7) || defined(CPU_MK30DX128VML7) || defined(CPU_MK30DX256VML7) || defined(CPU_MK30DN512ZVLL10) || \
defined(CPU_MK30DN512ZVLQ10) || defined(CPU_MK30DX256ZVLQ10) || defined(CPU_MK30DX128ZVLQ10) || defined(CPU_MK30DN512ZVMC10) || \
defined(CPU_MK30DN512ZVMD10) || defined(CPU_MK30DX256ZVMD10) || defined(CPU_MK30DX128ZVMD10) || defined(CPU_MK40DN512VLL10) || \
defined(CPU_MK40DX128VLQ10) || defined(CPU_MK40DX256VLQ10) || defined(CPU_MK40DN512VLQ10) || defined(CPU_MK40DN512VMC10) || \
defined(CPU_MK40DX128VMD10) || defined(CPU_MK40DX256VMD10) || defined(CPU_MK40DN512VMD10) || defined(CPU_MK40DX128VLL7) || \
defined(CPU_MK40DX256VLL7) || defined(CPU_MK40DX128VML7) || defined(CPU_MK40DX256VML7) || defined(CPU_MK40DN512ZVLL10) || \
defined(CPU_MK40DN512ZVLQ10) || defined(CPU_MK40DX256ZVLQ10) || defined(CPU_MK40DX128ZVLQ10) || defined(CPU_MK40DN512ZVMC10) || \
defined(CPU_MK40DN512ZVMD10) || defined(CPU_MK40DX256ZVMD10) || defined(CPU_MK40DX128ZVMD10) || defined(CPU_MK50DX256CLL10) || \
defined(CPU_MK50DN512CLL10) || defined(CPU_MK50DN512CLQ10) || defined(CPU_MK50DX256CMC10) || defined(CPU_MK50DN512CMC10) || \
defined(CPU_MK50DN512CMD10) || defined(CPU_MK50DX256CMD10) || defined(CPU_MK50DX256CLL7) || defined(CPU_MK50DX256CML7) || \
defined(CPU_MK50DN512ZCLL10) || defined(CPU_MK50DX256ZCLL10) || defined(CPU_MK50DN512ZCLQ10) || defined(CPU_MK50DN512ZCMC10) || \
defined(CPU_MK50DX256ZCMC10) || defined(CPU_MK50DN512ZCMD10) || defined(CPU_MK51DX256CLL10) || defined(CPU_MK51DN512CLL10) || \
defined(CPU_MK51DN256CLQ10) || defined(CPU_MK51DN512CLQ10) || defined(CPU_MK51DX256CMC10) || defined(CPU_MK51DN512CMC10) || \
defined(CPU_MK51DN256CMD10) || defined(CPU_MK51DN512CMD10) || defined(CPU_MK51DX256CLL7) || defined(CPU_MK51DX256CML7) || \
defined(CPU_MK51DN512ZCLL10) || defined(CPU_MK51DX256ZCLL10) || defined(CPU_MK51DN512ZCLQ10) || defined(CPU_MK51DN256ZCLQ10) || \
defined(CPU_MK51DN512ZCMC10) || defined(CPU_MK51DX256ZCMC10) || defined(CPU_MK51DN512ZCMD10) || defined(CPU_MK51DN256ZCMD10) || \
defined(CPU_MK52DN512CLQ10) || defined(CPU_MK52DN512CMD10) || defined(CPU_MK52DN512ZCLQ10) || defined(CPU_MK52DN512ZCMD10) || \
defined(CPU_MK53DN512CLQ10) || defined(CPU_MK53DX256CLQ10) || defined(CPU_MK53DN512CMD10) || defined(CPU_MK53DX256CMD10) || \
defined(CPU_MK53DN512ZCLQ10) || defined(CPU_MK53DX256ZCLQ10) || defined(CPU_MK53DN512ZCMD10) || defined(CPU_MK53DX256ZCMD10) || \
defined(CPU_MK60DN256VLL10) || defined(CPU_MK60DX256VLL10) || defined(CPU_MK60DN512VLL10) || defined(CPU_MK60DN256VLQ10) || \
defined(CPU_MK60DX256VLQ10) || defined(CPU_MK60DN512VLQ10) || defined(CPU_MK60DN256VMC10) || defined(CPU_MK60DX256VMC10) || \
defined(CPU_MK60DN512VMC10) || defined(CPU_MK60DN256VMD10) || defined(CPU_MK60DX256VMD10) || defined(CPU_MK60DN512VMD10) || \
defined(CPU_MK60FN1M0VLQ12) || defined(CPU_MK60FX512VLQ12) || defined(CPU_MK60FN1M0VLQ15) || defined(CPU_MK60FX512VLQ15) || \
defined(CPU_MK60FN1M0VMD12) || defined(CPU_MK60FX512VMD12) || defined(CPU_MK60FN1M0VMD15) || defined(CPU_MK60FX512VMD15) || \
defined(CPU_MK60DN512ZVLL10) || defined(CPU_MK60DX256ZVLL10) || defined(CPU_MK60DN256ZVLL10) || defined(CPU_MK60DN512ZVLQ10) || \
defined(CPU_MK60DX256ZVLQ10) || defined(CPU_MK60DN256ZVLQ10) || defined(CPU_MK60DN512ZVMC10) || defined(CPU_MK60DX256ZVMC10) || \
defined(CPU_MK60DN256ZVMC10) || defined(CPU_MK60DN512ZVMD10) || defined(CPU_MK60DX256ZVMD10) || defined(CPU_MK60DN256ZVMD10) || \
defined(CPU_MK61FN1M0VMD12) || defined(CPU_MK61FX512VMD12) || defined(CPU_MK61FN1M0VMD15) || defined(CPU_MK61FX512VMD15) || \
defined(CPU_MK61FN1M0VMD12WS) || defined(CPU_MK61FX512VMD12WS) || defined(CPU_MK61FN1M0VMD15WS) || defined(CPU_MK61FX512VMD15WS) || \
defined(CPU_MK61FN1M0VMF12) || defined(CPU_MK61FX512VMF12) || defined(CPU_MK61FN1M0VMF15) || defined(CPU_MK61FX512VMF15) || \
defined(CPU_MK61FN1M0VMJ12) || defined(CPU_MK61FX512VMJ12) || defined(CPU_MK61FN1M0VMJ15) || defined(CPU_MK61FX512VMJ15) || \
defined(CPU_MK61FN1M0VMJ12WS) || defined(CPU_MK61FX512VMJ12WS) || defined(CPU_MK61FN1M0VMJ15WS) || defined(CPU_MK61FX512VMJ15WS) || \
defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK63FN1M0VMD12WS) || defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK64FX512VMD12) || \
defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \
defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15) || \
defined(CPU_MK70FN1M0VMJ12WS) || defined(CPU_MK70FX512VMJ12WS) || defined(CPU_MK70FN1M0VMJ15WS) || defined(CPU_MK70FX512VMJ15WS)
/* @brief Deserial serial peripheral interface (registers MCR, TCR, CTARn, CTARn_SLAVE, SR, RSER, PUSHR, PUSHR_SLAVE, POPR, TXFRn, RXFRn if non-zero, otherwise C1, S, C2, BR, D, M).*/
#define FSL_FEATURE_SPI_IS_DSPI (1)
/* @brief Has DMA support (register bit fields C2[RXDMAE] and C2[TXDMAE]). (Only valid for non-DSPI modules.)*/
#define FSL_FEATURE_SPI_HAS_DMA_SUPPORT (1)
/* @brief Receive/transmit FIFO size in number of items.*/
#if defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK64FX512VMD12)
#define FSL_FEATURE_SPI_FIFO_SIZEn(x) \
((x) == 1 ? (2) : (-1)))
/* @brief Has chip select strobe capability on the PCS5 pin. */
#define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1)
/* @brief Has 16-bit data transfer support. */
#define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1)
#elif defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK24FN256VDC12) || defined(CPU_MK63FN1M0VLQ12) || \
defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLQ12) || \
defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK65FN2M0CAC18) || \
defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || defined(CPU_MK66FN2M0VLQ18) || \
defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18)
/* @brief Receive/transmit FIFO size in number of items. */
#define FSL_FEATURE_DSPI_FIFO_SIZE (4)
#define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \
((x) == 0 ? (4) : \
((x) == 1 ? (1) : \
((x) == 2 ? (1) : (-1))))
#else
#define FSL_FEATURE_SPI_FIFO_SIZEn(x) \
((x) == 0 ? (4) : \
/* @brief Maximum transfer data width in bits. */
#define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16)
/* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */
#define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6)
/* @brief Number of chip select pins. */
#define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (6)
#define FSL_FEATURE_DSPI_CHIP_SELECT_COUNTn(x) \
((x) == 0 ? (6) : \
((x) == 1 ? (4) : \
((x) == 2 ? (4) : (-1))))
#endif
/* @brief Maximum transfer data width in bits.*/
#define FSL_FEATURE_SPI_MAX_DATA_WIDTH (16)
/* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS] on DSPI modules.)*/
#define FSL_FEATURE_SPI_MAX_CHIP_SELECT_COUNT (6)
/* @brief Number of chip select pins. (Only valid for DSPI modules.)*/
#define FSL_FEATURE_SPI_CHIP_SELECT_COUNTn(x) \
((x) == 2 ? (2) : (-1))))
/* @brief Has chip select strobe capability on the PCS5 pin. */
#define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1)
/* @brief Has 16-bit data transfer support. */
#define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1)
#elif defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12)
/* @brief Receive/transmit FIFO size in number of items. */
#define FSL_FEATURE_DSPI_FIFO_SIZE (4)
#define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \
((x) == 0 ? (4) : \
((x) == 1 ? (1) : \
((x) == 2 ? (1) : (-1))))
/* @brief Maximum transfer data width in bits. */
#define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16)
/* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */
#define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6)
/* @brief Number of chip select pins. */
#define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (6)
#define FSL_FEATURE_DSPI_CHIP_SELECT_COUNTn(x) \
((x) == 0 ? (6) : \
((x) == 1 ? (4) : \
((x) == 2 ? (1) : (-1))))
/* @brief Has chip select strobe capability on the PCS5 pin. (Only valid for DSPI modules.)*/
#define FSL_FEATURE_SPI_HAS_CHIP_SELECT_STROBE (1)
/* @brief The data register name has postfix (L as low and H as high). (Only valid for non-DSPI modules.)*/
#define FSL_FEATURE_SPI_DATA_REGISTER_HAS_POSTFIX (0)
/* @brief Has 16-bit data transfer support.*/
#define FSL_FEATURE_SPI_FEATURE_16BIT_TRANSFERS (1)
#elif defined(CPU_MK10DX128VFM5) || defined(CPU_MK10DN128VFM5) || defined(CPU_MK10DX64VFM5) || defined(CPU_MK10DN64VFM5) || \
defined(CPU_MK10DX32VFM5) || defined(CPU_MK10DN32VFM5) || defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || \
defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5)
/* @brief Deserial serial peripheral interface (registers MCR, TCR, CTARn, CTARn_SLAVE, SR, RSER, PUSHR, PUSHR_SLAVE, POPR, TXFRn, RXFRn if non-zero, otherwise C1, S, C2, BR, D, M).*/
#define FSL_FEATURE_SPI_IS_DSPI (1)
/* @brief Has DMA support (register bit fields C2[RXDMAE] and C2[TXDMAE]). (Only valid for non-DSPI modules.)*/
#define FSL_FEATURE_SPI_HAS_DMA_SUPPORT (1)
/* @brief Receive/transmit FIFO size in number of items.*/
#define FSL_FEATURE_SPI_FIFO_SIZE (4)
/* @brief Maximum transfer data width in bits.*/
#define FSL_FEATURE_SPI_MAX_DATA_WIDTH (16)
/* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS] on DSPI modules.)*/
#define FSL_FEATURE_SPI_MAX_CHIP_SELECT_COUNT (6)
/* @brief Number of chip select pins. (Only valid for DSPI modules.)*/
#define FSL_FEATURE_SPI_CHIP_SELECT_COUNT (4)
/* @brief Has chip select strobe capability on the PCS5 pin. (Only valid for DSPI modules.)*/
#define FSL_FEATURE_SPI_HAS_CHIP_SELECT_STROBE (1)
/* @brief The data register name has postfix (L as low and H as high). (Only valid for non-DSPI modules.)*/
#define FSL_FEATURE_SPI_DATA_REGISTER_HAS_POSTFIX (0)
/* @brief Has 16-bit data transfer support.*/
#define FSL_FEATURE_SPI_FEATURE_16BIT_TRANSFERS (1)
#elif defined(CPU_MK11DX128VLK5) || defined(CPU_MK11DX256VLK5) || defined(CPU_MK11DN512VLK5) || defined(CPU_MK11DX128VLK5WS) || \
defined(CPU_MK11DX256VLK5WS) || defined(CPU_MK11DN512VLK5WS) || defined(CPU_MK11DX128VMC5) || defined(CPU_MK11DX256VMC5) || \
defined(CPU_MK11DN512VMC5) || defined(CPU_MK11DX128VMC5WS) || defined(CPU_MK11DX256VMC5WS) || defined(CPU_MK11DN512VMC5WS) || \
defined(CPU_MK12DX128VLH5) || defined(CPU_MK12DX256VLH5) || defined(CPU_MK12DN512VLH5) || defined(CPU_MK12DX128VLK5) || \
defined(CPU_MK12DX256VLK5) || defined(CPU_MK12DN512VLK5) || defined(CPU_MK12DX128VMC5) || defined(CPU_MK12DX256VMC5) || \
defined(CPU_MK12DN512VMC5) || defined(CPU_MK12DX128VLF5) || defined(CPU_MK12DX256VLF5) || defined(CPU_MK21DX128VLK5) || \
defined(CPU_MK21DX256VLK5) || defined(CPU_MK21DN512VLK5) || defined(CPU_MK21DX128VLK5WS) || defined(CPU_MK21DX256VLK5WS) || \
defined(CPU_MK21DN512VLK5WS) || defined(CPU_MK21DX128VMC5) || defined(CPU_MK21DX256VMC5) || defined(CPU_MK21DN512VMC5) || \
defined(CPU_MK21DX128VMC5WS) || defined(CPU_MK21DX256VMC5WS) || defined(CPU_MK21DN512VMC5WS) || defined(CPU_MK22DX128VLH5) || \
defined(CPU_MK22DX256VLH5) || defined(CPU_MK22DN512VLH5) || defined(CPU_MK22DX128VLK5) || defined(CPU_MK22DX256VLK5) || \
defined(CPU_MK22DN512VLK5) || defined(CPU_MK22DX128VMC5) || defined(CPU_MK22DX256VMC5) || defined(CPU_MK22DN512VMC5) || \
defined(CPU_MK22DX128VLF5) || defined(CPU_MK22DX256VLF5)
/* @brief Deserial serial peripheral interface (registers MCR, TCR, CTARn, CTARn_SLAVE, SR, RSER, PUSHR, PUSHR_SLAVE, POPR, TXFRn, RXFRn if non-zero, otherwise C1, S, C2, BR, D, M).*/
#define FSL_FEATURE_SPI_IS_DSPI (1)
/* @brief Has DMA support (register bit fields C2[RXDMAE] and C2[TXDMAE]). (Only valid for non-DSPI modules.)*/
#define FSL_FEATURE_SPI_HAS_DMA_SUPPORT (1)
/* @brief Receive/transmit FIFO size in number of items.*/
#define FSL_FEATURE_SPI_FIFO_SIZE (4)
/* @brief Maximum transfer data width in bits.*/
#define FSL_FEATURE_SPI_MAX_DATA_WIDTH (16)
/* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS] on DSPI modules.)*/
#define FSL_FEATURE_SPI_MAX_CHIP_SELECT_COUNT (5)
/* @brief Number of chip select pins. (Only valid for DSPI modules.)*/
#define FSL_FEATURE_SPI_CHIP_SELECT_COUNTn(x) \
((x) == 0 ? (5) : \
((x) == 1 ? (3) : (-1)))
/* @brief Has chip select strobe capability on the PCS5 pin. (Only valid for DSPI modules.)*/
#define FSL_FEATURE_SPI_HAS_CHIP_SELECT_STROBE (0)
/* @brief The data register name has postfix (L as low and H as high). (Only valid for non-DSPI modules.)*/
#define FSL_FEATURE_SPI_DATA_REGISTER_HAS_POSTFIX (0)
/* @brief Has 16-bit data transfer support.*/
#define FSL_FEATURE_SPI_FEATURE_16BIT_TRANSFERS (1)
#elif defined(CPU_MK22FN512VDC12)
/* @brief Deserial serial peripheral interface (registers MCR, TCR, CTARn, CTARn_SLAVE, SR, RSER, PUSHR, PUSHR_SLAVE, POPR, TXFRn, RXFRn if non-zero, otherwise C1, S, C2, BR, D, M).*/
#define FSL_FEATURE_SPI_IS_DSPI (1)
/* @brief Has DMA support (register bit fields C2[RXDMAE] and C2[TXDMAE]). (Only valid for non-DSPI modules.)*/
#define FSL_FEATURE_SPI_HAS_DMA_SUPPORT (1)
/* @brief Receive/transmit FIFO size in number of items.*/
#define FSL_FEATURE_SPI_FIFO_SIZEn(x) \
/* @brief Has chip select strobe capability on the PCS5 pin. */
#define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1)
/* @brief Has 16-bit data transfer support. */
#define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1)
#elif defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \
defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15)
/* @brief Receive/transmit FIFO size in number of items. */
#define FSL_FEATURE_DSPI_FIFO_SIZE (4)
#define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \
((x) == 0 ? (4) : \
((x) == 1 ? (1) : (-1)))
/* @brief Maximum transfer data width in bits.*/
#define FSL_FEATURE_SPI_MAX_DATA_WIDTH (16)
/* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS] on DSPI modules.)*/
#define FSL_FEATURE_SPI_MAX_CHIP_SELECT_COUNT (6)
/* @brief Number of chip select pins. (Only valid for DSPI modules.)*/
#define FSL_FEATURE_SPI_CHIP_SELECT_COUNT (0)
/* @brief Has chip select strobe capability on the PCS5 pin. (Only valid for DSPI modules.)*/
#define FSL_FEATURE_SPI_HAS_CHIP_SELECT_STROBE (1)
/* @brief The data register name has postfix (L as low and H as high). (Only valid for non-DSPI modules.)*/
#define FSL_FEATURE_SPI_DATA_REGISTER_HAS_POSTFIX (0)
/* @brief Has 16-bit data transfer support.*/
#define FSL_FEATURE_SPI_FEATURE_16BIT_TRANSFERS (1)
#elif defined(CPU_MK22FN512VDC12)
/* @brief Deserial serial peripheral interface (registers MCR, TCR, CTARn, CTARn_SLAVE, SR, RSER, PUSHR, PUSHR_SLAVE, POPR, TXFRn, RXFRn if non-zero, otherwise C1, S, C2, BR, D, M).*/
#define FSL_FEATURE_SPI_IS_DSPI (1)
/* @brief Has DMA support (register bit fields C2[RXDMAE] and C2[TXDMAE]). (Only valid for non-DSPI modules.)*/
#define FSL_FEATURE_SPI_HAS_DMA_SUPPORT (1)
/* @brief Receive/transmit FIFO size in number of items.*/
#define FSL_FEATURE_SPI_FIFO_SIZEn(x) \
((x) == 0 ? (4) : \
((x) == 1 ? (1) : (-1)))
/* @brief Maximum transfer data width in bits.*/
#define FSL_FEATURE_SPI_MAX_DATA_WIDTH (16)
/* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS] on DSPI modules.)*/
#define FSL_FEATURE_SPI_MAX_CHIP_SELECT_COUNT (6)
/* @brief Number of chip select pins. (Only valid for DSPI modules.)*/
#define FSL_FEATURE_SPI_CHIP_SELECT_COUNTn(x) \
((x) == 0 ? (5) : \
((x) == 1 ? (3) : (-1)))
/* @brief Has chip select strobe capability on the PCS5 pin. (Only valid for DSPI modules.)*/
#define FSL_FEATURE_SPI_HAS_CHIP_SELECT_STROBE (1)
/* @brief The data register name has postfix (L as low and H as high). (Only valid for non-DSPI modules.)*/
#define FSL_FEATURE_SPI_DATA_REGISTER_HAS_POSTFIX (0)
/* @brief Has 16-bit data transfer support.*/
#define FSL_FEATURE_SPI_FEATURE_16BIT_TRANSFERS (1)
#elif defined(CPU_MKE02Z64VLC2) || defined(CPU_MKE02Z32VLC2) || defined(CPU_MKE02Z16VLC2) || defined(CPU_MKE02Z64VLD2) || \
defined(CPU_MKE02Z32VLD2) || defined(CPU_MKE02Z16VLD2) || defined(CPU_MKE02Z64VLH2) || defined(CPU_MKE02Z64VQH2) || \
defined(CPU_MKE02Z32VLH2) || defined(CPU_MKE02Z32VQH2) || defined(CPU_MKE04Z8VFK4) || defined(CPU_MKE04Z8VTG4) || \
defined(CPU_MKE04Z8VWJ4) || defined(CPU_MKL02Z32CAF4) || defined(CPU_MKL02Z8VFG4) || defined(CPU_MKL02Z16VFG4) || \
defined(CPU_MKL02Z32VFG4) || defined(CPU_MKL02Z16VFK4) || defined(CPU_MKL02Z32VFK4) || defined(CPU_MKL02Z16VFM4) || \
defined(CPU_MKL02Z32VFM4)
/* @brief Deserial serial peripheral interface (registers MCR, TCR, CTARn, CTARn_SLAVE, SR, RSER, PUSHR, PUSHR_SLAVE, POPR, TXFRn, RXFRn if non-zero, otherwise C1, S, C2, BR, D, M).*/
#define FSL_FEATURE_SPI_IS_DSPI (0)
/* @brief Has DMA support (register bit fields C2[RXDMAE] and C2[TXDMAE]). (Only valid for non-DSPI modules.)*/
#define FSL_FEATURE_SPI_HAS_DMA_SUPPORT (0)
/* @brief Receive/transmit FIFO size in number of items.*/
#define FSL_FEATURE_SPI_FIFO_SIZE (1)
/* @brief Maximum transfer data width in bits.*/
#define FSL_FEATURE_SPI_MAX_DATA_WIDTH (8)
/* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS] on DSPI modules.)*/
#define FSL_FEATURE_SPI_MAX_CHIP_SELECT_COUNT (1)
/* @brief Number of chip select pins. (Only valid for DSPI modules.)*/
#define FSL_FEATURE_SPI_CHIP_SELECT_COUNT (0)
/* @brief Has chip select strobe capability on the PCS5 pin. (Only valid for DSPI modules.)*/
#define FSL_FEATURE_SPI_HAS_CHIP_SELECT_STROBE (0)
/* @brief The data register name has postfix (L as low and H as high). (Only valid for non-DSPI modules.)*/
#define FSL_FEATURE_SPI_DATA_REGISTER_HAS_POSTFIX (1)
/* @brief Has 16-bit data transfer support.*/
#define FSL_FEATURE_SPI_16BIT_TRANSFERS (0)
#elif defined(CPU_MKL04Z8VFK4) || defined(CPU_MKL04Z16VFK4) || defined(CPU_MKL04Z32VFK4) || defined(CPU_MKL04Z8VLC4) || \
defined(CPU_MKL04Z16VLC4) || defined(CPU_MKL04Z32VLC4) || defined(CPU_MKL04Z8VFM4) || defined(CPU_MKL04Z16VFM4) || \
defined(CPU_MKL04Z32VFM4) || defined(CPU_MKL04Z16VLF4) || defined(CPU_MKL04Z32VLF4) || defined(CPU_MKL05Z8VFK4) || \
defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || defined(CPU_MKL05Z16VLC4) || \
defined(CPU_MKL05Z32VLC4) || defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || defined(CPU_MKL05Z32VFM4) || \
defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4) || defined(CPU_MKL14Z32VFM4) || defined(CPU_MKL14Z64VFM4) || \
defined(CPU_MKL14Z32VFT4) || defined(CPU_MKL14Z64VFT4) || defined(CPU_MKL14Z32VLH4) || defined(CPU_MKL14Z64VLH4) || \
defined(CPU_MKL14Z32VLK4) || defined(CPU_MKL14Z64VLK4) || defined(CPU_MKL15Z32VFM4) || defined(CPU_MKL15Z64VFM4) || \
defined(CPU_MKL15Z128VFM4) || defined(CPU_MKL15Z32VFT4) || defined(CPU_MKL15Z64VFT4) || defined(CPU_MKL15Z128VFT4) || \
defined(CPU_MKL15Z32VLH4) || defined(CPU_MKL15Z64VLH4) || defined(CPU_MKL15Z128VLH4) || defined(CPU_MKL15Z32VLK4) || \
defined(CPU_MKL15Z64VLK4) || defined(CPU_MKL15Z128VLK4) || defined(CPU_MKL24Z32VFM4) || defined(CPU_MKL24Z64VFM4) || \
defined(CPU_MKL24Z32VFT4) || defined(CPU_MKL24Z64VFT4) || defined(CPU_MKL24Z32VLH4) || defined(CPU_MKL24Z64VLH4) || \
defined(CPU_MKL24Z32VLK4) || defined(CPU_MKL24Z64VLK4) || defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z64VFM4) || \
defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z128VFT4) || \
defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || defined(CPU_MKL25Z32VLK4) || \
defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4)
/* @brief Deserial serial peripheral interface (registers MCR, TCR, CTARn, CTARn_SLAVE, SR, RSER, PUSHR, PUSHR_SLAVE, POPR, TXFRn, RXFRn if non-zero, otherwise C1, S, C2, BR, D, M).*/
#define FSL_FEATURE_SPI_IS_DSPI (0)
/* @brief Has DMA support (register bit fields C2[RXDMAE] and C2[TXDMAE]). (Only valid for non-DSPI modules.)*/
#define FSL_FEATURE_SPI_HAS_DMA_SUPPORT (1)
/* @brief Receive/transmit FIFO size in number of items.*/
#define FSL_FEATURE_SPI_FIFO_SIZE (1)
/* @brief Maximum transfer data width in bits.*/
#define FSL_FEATURE_SPI_MAX_DATA_WIDTH (8)
/* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS] on DSPI modules.)*/
#define FSL_FEATURE_SPI_MAX_CHIP_SELECT_COUNT (1)
/* @brief Number of chip select pins. (Only valid for DSPI modules.)*/
#define FSL_FEATURE_SPI_CHIP_SELECT_COUNT (0)
/* @brief Has chip select strobe capability on the PCS5 pin. (Only valid for DSPI modules.)*/
#define FSL_FEATURE_SPI_HAS_CHIP_SELECT_STROBE (0)
/* @brief The data register name has postfix (L as low and H as high). (Only valid for non-DSPI modules.)*/
#define FSL_FEATURE_SPI_DATA_REGISTER_HAS_POSTFIX (1)
/* @brief Has 16-bit data transfer support.*/
#define FSL_FEATURE_SPI_16BIT_TRANSFERS (0)
#elif defined(CPU_MKL16Z32VFM4) || defined(CPU_MKL16Z64VFM4) || defined(CPU_MKL16Z128VFM4) || defined(CPU_MKL16Z32VFT4) || \
defined(CPU_MKL16Z64VFT4) || defined(CPU_MKL16Z128VFT4) || defined(CPU_MKL16Z32VLH4) || defined(CPU_MKL16Z64VLH4) || \
defined(CPU_MKL16Z128VLH4) || defined(CPU_MKL16Z256VLH4) || defined(CPU_MKL16Z256VLK4) || defined(CPU_MKL26Z32VFM4) || \
defined(CPU_MKL26Z64VFM4) || defined(CPU_MKL26Z128VFM4) || defined(CPU_MKL26Z32VFT4) || defined(CPU_MKL26Z64VFT4) || \
defined(CPU_MKL26Z128VFT4) || defined(CPU_MKL26Z32VLH4) || defined(CPU_MKL26Z64VLH4) || defined(CPU_MKL26Z128VLH4) || \
defined(CPU_MKL26Z256VLH4) || defined(CPU_MKL26Z256VLK4) || defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z256VLL4) || \
defined(CPU_MKL26Z128VMC4) || defined(CPU_MKL26Z256VMC4) || defined(CPU_MKL34Z64VLH4) || defined(CPU_MKL34Z64VLL4) || \
defined(CPU_MKL36Z64VLH4) || defined(CPU_MKL36Z128VLH4) || defined(CPU_MKL36Z256VLH4) || defined(CPU_MKL36Z64VLL4) || \
defined(CPU_MKL36Z128VLL4) || defined(CPU_MKL36Z256VLL4) || defined(CPU_MKL36Z128VMC4) || defined(CPU_MKL36Z256VMC4) || \
defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || defined(CPU_MKL46Z256VLL4) || \
defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4)
/* @brief Deserial serial peripheral interface (registers MCR, TCR, CTARn, CTARn_SLAVE, SR, RSER, PUSHR, PUSHR_SLAVE, POPR, TXFRn, RXFRn if non-zero, otherwise C1, S, C2, BR, D, M).*/
#define FSL_FEATURE_SPI_IS_DSPI (0)
/* @brief Has DMA support (register bit fields C2[RXDMAE] and C2[TXDMAE]). (Only valid for non-DSPI modules.)*/
#define FSL_FEATURE_SPI_HAS_DMA_SUPPORT (1)
/* @brief Receive/transmit FIFO size in number of items.*/
#define FSL_FEATURE_SPI_FIFO_SIZEn(x) \
((x) == 0 ? (1) : \
((x) == 1 ? (8) : (-1)))
/* @brief Maximum transfer data width in bits.*/
#define FSL_FEATURE_SPI_MAX_DATA_WIDTH (16)
/* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS] on DSPI modules.)*/
#define FSL_FEATURE_SPI_MAX_CHIP_SELECT_COUNT (1)
/* @brief Number of chip select pins. (Only valid for DSPI modules.)*/
#define FSL_FEATURE_SPI_CHIP_SELECT_COUNT (0)
/* @brief Has chip select strobe capability on the PCS5 pin. (Only valid for DSPI modules.)*/
#define FSL_FEATURE_SPI_HAS_CHIP_SELECT_STROBE (0)
/* @brief The data register name has postfix (L as low and H as high). (Only valid for non-DSPI modules.)*/
#define FSL_FEATURE_SPI_DATA_REGISTER_HAS_POSTFIX (1)
/* @brief Has 16-bit data transfer support.*/
#define FSL_FEATURE_SPI_16BIT_TRANSFERS (1)
((x) == 1 ? (4) : \
((x) == 2 ? (4) : (-1))))
/* @brief Maximum transfer data width in bits. */
#define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16)
/* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */
#define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6)
/* @brief Number of chip select pins. */
#define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (6)
#define FSL_FEATURE_DSPI_CHIP_SELECT_COUNTn(x) \
((x) == 0 ? (6) : \
((x) == 1 ? (4) : \
((x) == 2 ? (2) : (-1))))
/* @brief Has chip select strobe capability on the PCS5 pin. */
#define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1)
/* @brief Has 16-bit data transfer support. */
#define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1)
#elif defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F256VLH15) || defined(CPU_MKV40F64VLH15) || defined(CPU_MKV43F128VLH15) || \
defined(CPU_MKV43F64VLH15) || defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F64VLH15) || defined(CPU_MKV45F128VLH15) || \
defined(CPU_MKV45F256VLH15) || defined(CPU_MKV46F128VLH15) || defined(CPU_MKV46F256VLH15)
/* @brief Receive/transmit FIFO size in number of items. */
#define FSL_FEATURE_DSPI_FIFO_SIZE (4)
#define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \
((x) == 0 ? (4) : (-1))
/* @brief Maximum transfer data width in bits. */
#define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16)
/* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */
#define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6)
/* @brief Number of chip select pins. */
#define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (5)
#define FSL_FEATURE_DSPI_CHIP_SELECT_COUNTn(x) \
((x) == 0 ? (5) : (-1))
/* @brief Has chip select strobe capability on the PCS5 pin. */
#define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1)
/* @brief Has 16-bit data transfer support. */
#define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1)
#elif defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLL15) || defined(CPU_MKV43F128VLL15) || defined(CPU_MKV44F128VLL15) || \
defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLL15) || defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLL15)
/* @brief Receive/transmit FIFO size in number of items. */
#define FSL_FEATURE_DSPI_FIFO_SIZE (4)
#define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \
((x) == 0 ? (4) : (-1))
/* @brief Maximum transfer data width in bits. */
#define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16)
/* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */
#define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6)
/* @brief Number of chip select pins. */
#define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (6)
#define FSL_FEATURE_DSPI_CHIP_SELECT_COUNTn(x) \
((x) == 0 ? (6) : (-1))
/* @brief Has chip select strobe capability on the PCS5 pin. */
#define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1)
/* @brief Has 16-bit data transfer support. */
#define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1)
#else
#error "No valid CPU defined!"
#endif
#endif /* __FSL_DSPI_FEATURES_H__*/
#endif /* __FSL_DSPI_FEATURES_H__ */
/*******************************************************************************
* EOF
******************************************************************************/

625
libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/dspi/fsl_dspi_hal.c
View File

@ -34,174 +34,54 @@
* Definitions
******************************************************************************/
/*******************************************************************************
* Variables
******************************************************************************/
/*******************************************************************************
* Code
******************************************************************************/
/*FUNCTION**********************************************************************
*
* Function Name : dspi_hal_master_init
* Description : Configure the DSPI peripheral in master mode.
* This function will initialize the module to user defined settings and default settings in master
* mode. Here is an example demonstrating how to define the dspi_master_config_t structure and call
* the dspi_hal_master_init function:
* dspi_master_config_t dspiConfig;
* dspiConfig.isEnabled = false;
* dspiConfig.whichCtar = kDspiCtar0;
* dspiConfig.bitsPerSec = 0;
* dspiConfig.sourceClockInHz = dspiSourceClock;
* dspiConfig.isSckContinuous = false;
* dspiConfig.whichPcs = kDspiPcs0;
* dspiConfig.pcsPolarity = kDspiPcs_ActiveLow;
* dspiConfig.masterInSample = kDspiSckToSin_0Clock;
* dspiConfig.isModifiedTimingFormatEnabled = false;
* dspiConfig.isTxFifoDisabled = false;
* dspiConfig.isRxFifoDisabled = false;
* dspiConfig.dataConfig.bitsPerFrame = 16;
* dspiConfig.dataConfig.clkPolarity = kDspiClockPolarity_ActiveHigh;
* dspiConfig.dataConfig.clkPhase = kDspiClockPhase_FirstEdge;
* dspiConfig.dataConfig.direction = kDspiMsbFirst;
* dspi_hal_master_init(instance, &dspiConfig, calculatedBaudRate);
*
*END**************************************************************************/
dspi_status_t dspi_hal_master_init(uint32_t instance, const dspi_master_config_t * config,
uint32_t * calculatedBaudRate)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
/* Enable or disable the module. */
/* Note, to enable the module, MDIS must be cleared. However, the member isEnabled*/
/* must be true (1) to enable module, hence we negate the value of isEnabled to properly*/
/* configure the MDIS bit*/
BW_SPI_MCR_MDIS(instance, ~(config->isEnabled == true));
/* Configure baud rate if a value is provided.*/
if (config->bitsPerSec != 0U)
{
*calculatedBaudRate = dspi_hal_set_baud(instance, config->whichCtar, config->bitsPerSec,
config->sourceClockInHz);
}
else
{
*calculatedBaudRate = 0;
}
/* Set master or slave mode.*/
dspi_hal_set_master_slave(instance, kDspiMaster);
/* Configure data format.*/
if (dspi_hal_configure_data_format(instance, config->whichCtar, &config->dataConfig)
!= kStatus_DSPI_Success)
{
return kStatus_DSPI_InvalidBitCount;
}
/* Configure for continuous SCK operation*/
dspi_hal_configure_continuous_sck(instance, config->isSckContinuous);
/* Configure for peripheral chip select polarity*/
dspi_hal_configure_pcs_polarity(instance, config->whichPcs,config->pcsPolarity);
/* Configure sample point for data in, master mode*/
dspi_hal_set_datain_samplepoint(instance, config->masterInSample);
/* Configure for modified timing format*/
dspi_hal_configure_modified_timing_format(instance, config->isModifiedTimingFormatEnabled);
/* Configure for fifo operation*/
dspi_hal_configure_fifos(instance, config->isTxFifoDisabled, config->isRxFifoDisabled);
/* finally, clear the DSPI CONFIGURATION (DCONF), even though this is cleared in some IPs*/
/* by default and other bit settings are reserved*/
HW_SPI_MCR_CLR(instance, BM_SPI_MCR_DCONF);
return kStatus_DSPI_Success;
}
/*FUNCTION**********************************************************************
*
* Function Name : dspi_hal_slave_init
* Description : Configure the DSPI peripheral in slave mode.
* This function initializes the DSPI module for slave mode. Here is an example demonstrating how
* to define the dspi_slave_config_t structure and call the dspi_hal_slave_init function:
* dspi_slave_config_t dspiConfig;
* dspiConfig.isEnabled = false;
* dspiConfig.isTxFifoDisabled = false;
* dspiConfig.isRxFifoDisabled = false;
* dspiConfig.dataConfig.bitsPerFrame = 16;
* dspiConfig.dataConfig.clkPolarity = kDspiClockPolarity_ActiveHigh;
* dspiConfig.dataConfig.clkPhase = kDspiClockPhase_FirstEdge;
* dspi_hal_slave_init(instance, &dspiConfig);
*
*END**************************************************************************/
dspi_status_t dspi_hal_slave_init(uint32_t instance, const dspi_slave_config_t * config)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
/* Enable or disable the module.
* Note, to enable the module, MDIS must be cleared. However, the member isEnabled
* must be true (1) to enable module, hence we negate the value of isEnabled to properly
* configure the MDIS bit
*/
BW_SPI_MCR_MDIS(instance, ~(config->isEnabled == true));
/* Set master or slave moe. */
dspi_hal_set_master_slave(instance, kDspiSlave);
/* Configure data format. For slave mode, only CTAR0 is available for use */
if (dspi_hal_configure_data_format(instance, kDspiCtar0, &config->dataConfig)
!= kStatus_DSPI_Success)
{
return kStatus_DSPI_InvalidBitCount;
}
/* Configure for fifo operation */
dspi_hal_configure_fifos(instance, config->isTxFifoDisabled, config->isRxFifoDisabled);
/* finally, clear the DSPI CONFIGURATION (DCONF), even though this is cleared in some IPs
* by default and other bit settings are reserved
*/
HW_SPI_MCR_CLR(instance, BM_SPI_MCR_DCONF);
return kStatus_DSPI_Success;
}
/*FUNCTION**********************************************************************
*
* Function Name : dspi_hal_reset
* Function Name : DSPI_HAL_Init
* Description : Restore DSPI to reset configuration.
* This function basically resets all of the DSPI registers to their default setting including
* disabling the module.
*
*END**************************************************************************/
void dspi_hal_reset(uint32_t instance)
void DSPI_HAL_Init(uint32_t baseAddr)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
/* first, make sure the module is enabled to allow writes to certain registers*/
dspi_hal_enable(instance);
DSPI_HAL_Enable(baseAddr);
/* Halt all transfers*/
HW_SPI_MCR_WR(instance, BM_SPI_MCR_HALT);
/* flush the fifos*/
dspi_hal_flush_fifos(instance, true, true);
DSPI_HAL_StopTransfer(baseAddr);
/* set the registers to their default states*/
/* clear the status bits (write-1-to-clear)*/
HW_SPI_SR_WR(instance, BM_SPI_SR_TCF | BM_SPI_SR_EOQF | BM_SPI_SR_TFUF | BM_SPI_SR_TFFF |
BM_SPI_SR_RFOF | BM_SPI_SR_RFDF);
HW_SPI_TCR_WR(instance, 0);
HW_SPI_CTARn_WR(instance, 0, 0); /* CTAR0*/
HW_SPI_CTARn_WR(instance, 1, 0); /* CTAR1*/
HW_SPI_RSER_WR(instance, 0);
/* disable the module*/
HW_SPI_MCR_WR(instance, BM_SPI_MCR_MDIS | BM_SPI_MCR_HALT);
HW_SPI_SR_WR(baseAddr, BM_SPI_SR_TCF | BM_SPI_SR_EOQF | BM_SPI_SR_TFUF |
BM_SPI_SR_TFFF | BM_SPI_SR_RFOF | BM_SPI_SR_RFDF);
HW_SPI_TCR_WR(baseAddr, 0);
HW_SPI_CTARn_WR(baseAddr, 0, 0x78000000); /* CTAR0*/
HW_SPI_CTARn_WR(baseAddr, 1, 0x78000000); /* CTAR1*/
HW_SPI_RSER_WR(baseAddr, 0);
/* Clear out PUSHR register. Since DSPI is halted, nothing should be transmitted. Be
* sure the flush the FIFOs afterwards
*/
HW_SPI_PUSHR_WR(baseAddr, 0);
/* flush the fifos*/
DSPI_HAL_SetFlushFifoCmd(baseAddr, true, true);
/* Now set MCR to default value, which disables module: set MDIS and HALT, clear other bits */
HW_SPI_MCR_WR(baseAddr, BM_SPI_MCR_MDIS | BM_SPI_MCR_HALT);
}
/*FUNCTION**********************************************************************
*
* Function Name : dspi_hal_set_baud
* Function Name : DSPI_HAL_SetBaudRate
* Description : Set the DSPI baud rate in bits per second.
* This function will take in the desired bitsPerSec (baud rate) and will calculate the nearest
* possible baud rate without exceeding the desired baud rate, and will return the calculated
@ -209,13 +89,11 @@ void dspi_hal_reset(uint32_t instance)
* module source clock (in Hz).
*
*END**************************************************************************/
uint32_t dspi_hal_set_baud(uint32_t instance, dspi_ctar_selection_t whichCtar, uint32_t bitsPerSec,
uint32_t sourceClockInHz)
uint32_t DSPI_HAL_SetBaudRate(uint32_t baseAddr, dspi_ctar_selection_t whichCtar,
uint32_t bitsPerSec, uint32_t sourceClockInHz)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
/* for master mode configuration, if slave mode detected, return 0*/
if (HW_SPI_MCR(instance).B.MSTR != 1)
if (!DSPI_HAL_IsMaster(baseAddr))
{
return 0;
}
@ -264,14 +142,10 @@ uint32_t dspi_hal_set_baud(uint32_t instance, dspi_ctar_selection_t whichCtar, u
}
}
uint32_t temp;
/* write the best dbr, prescalar, and baud rate scalar to the CTAR*/
temp = HW_SPI_CTARn_RD(instance, whichCtar); /* save register contents*/
temp &= ~(BM_SPI_CTARn_DBR| BM_SPI_CTARn_PBR | BM_SPI_CTARn_BR);
temp |= BF_SPI_CTARn_DBR(bestDbr - 1) |
BF_SPI_CTARn_PBR(bestPrescaler) |
BF_SPI_CTARn_BR(bestScaler);
HW_SPI_CTARn_WR(instance, whichCtar, temp);
BW_SPI_CTARn_DBR(baseAddr, whichCtar, (bestDbr - 1));
BW_SPI_CTARn_PBR(baseAddr, whichCtar, bestPrescaler);
BW_SPI_CTARn_BR(baseAddr, whichCtar, bestScaler);
/* return the actual calculated baud rate*/
return bestBaudrate;
@ -279,49 +153,40 @@ uint32_t dspi_hal_set_baud(uint32_t instance, dspi_ctar_selection_t whichCtar, u
/*FUNCTION**********************************************************************
*
* Function Name : dspi_hal_set_baud_divisors
* Function Name : DSPI_HAL_SetBaudDivisors
* Description : Configure the baud rate divisors manually.
* This function allows the caller to manually set the baud rate divisors in the event that
* these dividers are known and the caller does not wish to call the dspi_hal_set_baud function.
* these dividers are known and the caller does not wish to call the DSPI_HAL_SetBaudRate function.
*
*END**************************************************************************/
void dspi_hal_set_baud_divisors(uint32_t instance,
dspi_ctar_selection_t whichCtar,
const dspi_baud_rate_divisors_t * divisors)
void DSPI_HAL_SetBaudDivisors(uint32_t baseAddr,
dspi_ctar_selection_t whichCtar,
const dspi_baud_rate_divisors_t * divisors)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
uint32_t temp;
/* these settings are only relevant in master mode*/
if (HW_SPI_MCR(instance).B.MSTR == 1)
if (DSPI_HAL_IsMaster(baseAddr))
{
temp = HW_SPI_CTARn_RD(instance, whichCtar); /* save register contents*/
temp &= ~(BM_SPI_CTARn_DBR | BM_SPI_CTARn_PBR | BM_SPI_CTARn_BR); /* clear dividers*/
temp |= BF_SPI_CTARn_DBR(divisors->doubleBaudRate) |
BF_SPI_CTARn_PBR(divisors->prescaleDivisor) |
BF_SPI_CTARn_BR(divisors->baudRateDivisor);
HW_SPI_CTARn_WR(instance, whichCtar, temp);
BW_SPI_CTARn_DBR(baseAddr, whichCtar, divisors->doubleBaudRate);
BW_SPI_CTARn_PBR(baseAddr, whichCtar, divisors->prescaleDivisor);
BW_SPI_CTARn_BR(baseAddr, whichCtar, divisors->baudRateDivisor);
}
}
/*FUNCTION**********************************************************************
*
* Function Name : dspi_hal_configure_pcs_polarity
* Function Name : DSPI_HAL_SetPcsPolarityMode
* Description : Configure DSPI peripheral chip select polarity.
* This function will take in the desired peripheral chip select (PCS) and it's
* corresponding desired polarity and will configure the PCS signal to operate with the
* desired characteristic.
*
*END**************************************************************************/
void dspi_hal_configure_pcs_polarity(uint32_t instance, dspi_which_pcs_config_t pcs,
dspi_pcs_polarity_config_t activeLowOrHigh)
void DSPI_HAL_SetPcsPolarityMode(uint32_t baseAddr, dspi_which_pcs_config_t pcs,
dspi_pcs_polarity_config_t activeLowOrHigh)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
uint32_t temp;
temp = BR_SPI_MCR_PCSIS(instance);
temp = BR_SPI_MCR_PCSIS(baseAddr);
if (activeLowOrHigh == kDspiPcs_ActiveLow)
{
@ -332,60 +197,59 @@ void dspi_hal_configure_pcs_polarity(uint32_t instance, dspi_which_pcs_config_t
temp &= ~(unsigned)pcs;
}
BW_SPI_MCR_PCSIS(instance, temp);
BW_SPI_MCR_PCSIS(baseAddr, temp);
}
/*FUNCTION**********************************************************************
*
* Function Name : dspi_hal_configure_fifos
* Description : Configure DSPI fifos.
* Function Name : DSPI_HAL_SetFifoCmd
* Description : Enables (or disables) the DSPI FIFOs.
* This function with allow the caller to disable/enable the TX and RX FIFOs (independently).
* Note that to disable, the caller must pass in a logic 1 (true) for the particular FIFO
* configuration. To enable, the caller must pass in a logic 0 (false). For example, to enable
* both the TX and RX FIFOs, the caller will make this function call (where instance is the
* Note that to disable, the caller must pass in a logic 0 (false) for the particular FIFO
* configuration. To enable, the caller must pass in a logic 1 (true).
*
*END**************************************************************************/
void dspi_hal_configure_fifos(uint32_t instance, bool disableTxFifo, bool disableRxFifo)
void DSPI_HAL_SetFifoCmd(uint32_t baseAddr, bool enableTxFifo, bool enableRxFifo)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
/* first see if MDIS is set or cleared */
uint32_t isMdisSet = HW_SPI_MCR(instance).B.MDIS;
uint32_t isMdisSet = BR_SPI_MCR_MDIS(baseAddr);
if (isMdisSet)
{
/* clear the MDIS bit to allow us to write to the fifo disables */
HW_SPI_MCR_CLR(instance, BM_SPI_MCR_MDIS);
/* clear the MDIS bit (enable DSPI) to allow us to write to the fifo disables */
DSPI_HAL_Enable(baseAddr);
}
BW_SPI_MCR_DIS_TXF(instance, (disableTxFifo == true));
BW_SPI_MCR_DIS_RXF(instance, (disableRxFifo == true));
/* Note, the bit definition is "disable FIFO", so a "1" would disable. If user wants to enable
* the FIFOs, they pass in true, which we must logically negate (turn to false) to enable the
* FIFO
*/
BW_SPI_MCR_DIS_TXF(baseAddr, ~(enableTxFifo == true));
BW_SPI_MCR_DIS_RXF(baseAddr, ~(enableRxFifo == true));
/* set MDIS if it was set to begin with */
/* set MDIS (disable DSPI) if it was set to begin with */
if (isMdisSet)
{
HW_SPI_MCR_SET(instance, BM_SPI_MCR_MDIS);
DSPI_HAL_Disable(baseAddr);
}
}
/*FUNCTION**********************************************************************
*
* Function Name : dspi_hal_flush_fifos
* Function Name : DSPI_HAL_SetFlushFifoCmd
* Description : Flush DSPI fifos.
*
*END**************************************************************************/
void dspi_hal_flush_fifos(uint32_t instance, bool enableFlushTxFifo, bool enableFlushRxFifo)
void DSPI_HAL_SetFlushFifoCmd(uint32_t baseAddr, bool enableFlushTxFifo, bool enableFlushRxFifo)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
BW_SPI_MCR_CLR_TXF(instance, (enableFlushTxFifo == true));
BW_SPI_MCR_CLR_RXF(instance, (enableFlushRxFifo == true));
BW_SPI_MCR_CLR_TXF(baseAddr, (enableFlushTxFifo == true));
BW_SPI_MCR_CLR_RXF(baseAddr, (enableFlushRxFifo == true));
}
/*FUNCTION**********************************************************************
*
* Function Name : dspi_hal_configure_data_format
* Function Name : DSPI_HAL_SetDataFormat
* Description : Configure the data format for a particular CTAR.
* This function configures the bits-per-frame, polarity, phase, and shift direction for a
* particular CTAR. An example use case is as follows:
@ -394,169 +258,267 @@ void dspi_hal_flush_fifos(uint32_t instance, bool enableFlushTxFifo, bool enable
* dataFormat.clkPolarity = kDspiClockPolarity_ActiveLow;
* dataFormat.clkPhase = kDspiClockPhase_FirstEdge;
* dataFormat.direction = kDspiMsbFirst;
* dspi_hal_configure_data_format(instance, kDspiCtar0, &dataFormat);
* DSPI_HAL_SetDataFormat(baseAddr, kDspiCtar0, &dataFormat);
*
*END**************************************************************************/
dspi_status_t dspi_hal_configure_data_format(uint32_t instance,
dspi_ctar_selection_t whichCtar,
const dspi_data_format_config_t * config)
dspi_status_t DSPI_HAL_SetDataFormat(uint32_t baseAddr,
dspi_ctar_selection_t whichCtar,
const dspi_data_format_config_t * config)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
/* check bits-per-frame value to make sure it it within the proper range*/
/* in either master or slave mode*/
if ((config->bitsPerFrame < 4) ||
((config->bitsPerFrame > 16) && (HW_SPI_MCR(instance).B.MSTR == 1)) ||
((config->bitsPerFrame > 32) && (HW_SPI_MCR(instance).B.MSTR == 0)))
((config->bitsPerFrame > 16) && (HW_SPI_MCR(baseAddr).B.MSTR == 1)) ||
((config->bitsPerFrame > 32) && (HW_SPI_MCR(baseAddr).B.MSTR == 0)))
{
return kStatus_DSPI_InvalidBitCount;
}
uint32_t temp;
/* for master mode configuration*/
if (HW_SPI_MCR(instance).B.MSTR == 1)
if (DSPI_HAL_IsMaster(baseAddr))
{
temp = HW_SPI_CTARn_RD(instance, whichCtar); /* save register contents*/
temp &= ~(BM_SPI_CTARn_FMSZ| BM_SPI_CTARn_CPOL | BM_SPI_CTARn_CPHA | BM_SPI_CTARn_LSBFE);
temp |= BF_SPI_CTARn_FMSZ(config->bitsPerFrame - 1) |
BF_SPI_CTARn_CPOL(config->clkPolarity) |
BF_SPI_CTARn_CPHA(config->clkPhase) |
BF_SPI_CTARn_LSBFE(config->direction);
HW_SPI_CTARn_WR(instance, whichCtar, temp);
BW_SPI_CTARn_FMSZ(baseAddr, whichCtar, (config->bitsPerFrame - 1));
BW_SPI_CTARn_CPOL(baseAddr, whichCtar, config->clkPolarity);
BW_SPI_CTARn_CPHA(baseAddr, whichCtar, config->clkPhase);
BW_SPI_CTARn_LSBFE(baseAddr, whichCtar, config->direction);
}
else /* for slave mode configuration*/
{
temp = HW_SPI_CTARn_SLAVE_RD(instance, whichCtar); /* save register contents*/
temp &= ~(BM_SPI_CTARn_SLAVE_FMSZ| BM_SPI_CTARn_SLAVE_CPOL | BM_SPI_CTARn_SLAVE_CPHA);
temp |= BF_SPI_CTARn_SLAVE_FMSZ(config->bitsPerFrame - 1) |
BF_SPI_CTARn_SLAVE_CPOL(config->clkPolarity) |
BF_SPI_CTARn_SLAVE_CPHA(config->clkPhase);
HW_SPI_CTARn_SLAVE_WR(instance, whichCtar, temp);
BW_SPI_CTARn_SLAVE_FMSZ(baseAddr, whichCtar, (config->bitsPerFrame - 1));
BW_SPI_CTARn_SLAVE_CPOL(baseAddr, whichCtar, config->clkPolarity);
BW_SPI_CTARn_SLAVE_CPHA(baseAddr, whichCtar, config->clkPhase);
}
return kStatus_DSPI_Success;
}
/*FUNCTION**********************************************************************
*
* Function Name : dspi_hal_configure_delays
* Description : Configure the delays for a particular CTAR, master mode only.
* This function configures the PCS to SCK delay prescalar (PCSSCK),
* the PCS to SCK Delay scalar (CSSCK),
* the After SCK delay prescalar (PASC),
* the After SCK delay scalar (ASC),
* the Delay after transfer prescalar (PDT),
* and the Delay after transfer scalar (DT).
* The following is an example use case of this function:
* dspi_delay_settings_config_t delayConfig;
* delayConfig.pcsToSckPre = 0x3;
* delayConfig.pcsToSck = 0xF;
* delayConfig.afterSckPre = 0x2;
* delayConfig.afterSck = 0xA;
* delayConfig.afterTransferPre = 0x1;
* delayConfig.afterTransfer = 0x5;
* dspi_hal_configure_delays(instance, kDspiCtar0, &delayConfig);
* Function Name : DSPI_HAL_SetDelay
* Description : Manually configures the delay prescaler and scaler for a particular CTAR.
* This function configures the:
* PCS to SCK delay pre-scalar (PCSSCK) and scalar (CSSCK),
* After SCK delay pre-scalar (PASC) and scalar (ASC),
* Delay after transfer pre-scalar (PDT)and scalar (DT).
*
* These delay names are available in type dspi_delay_type_t.
*
* The user passes which delay they want to configure along with the prescaler and scaler value.
* This basically allows the user to directly set the prescaler/scaler values if they have
* pre-calculated them or if they simply wish to manually increment either value.
*END**************************************************************************/
void dspi_hal_configure_delays(uint32_t instance,
dspi_ctar_selection_t whichCtar,
const dspi_delay_settings_config_t * config)
void DSPI_HAL_SetDelay(uint32_t baseAddr, dspi_ctar_selection_t whichCtar, uint32_t prescaler,
uint32_t scaler, dspi_delay_type_t whichDelay)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
uint32_t temp;
/* these settings are only relevant in master mode*/
if (HW_SPI_MCR(instance).B.MSTR == 1)
if (DSPI_HAL_IsMaster(baseAddr))
{
temp = HW_SPI_CTARn_RD(instance, whichCtar); /* save register contents*/
temp &= ~(BM_SPI_CTARn_PCSSCK | BM_SPI_CTARn_PASC | BM_SPI_CTARn_PDT |
BM_SPI_CTARn_CSSCK| BM_SPI_CTARn_ASC | BM_SPI_CTARn_DT);
temp |= BF_SPI_CTARn_PCSSCK(config->pcsToSckPre) |
BF_SPI_CTARn_PASC(config->afterSckPre) |
BF_SPI_CTARn_PDT(config->afterTransferPre) |
BF_SPI_CTARn_CSSCK(config->pcsToSck) |
BF_SPI_CTARn_ASC(config->afterSck) |
BF_SPI_CTARn_DT(config->afterTransfer);
HW_SPI_CTARn_WR(instance, whichCtar, temp);
if (whichDelay == kDspiPcsToSck)
{
BW_SPI_CTARn_PCSSCK(baseAddr, whichCtar, prescaler);
BW_SPI_CTARn_CSSCK(baseAddr, whichCtar, scaler);
}
if (whichDelay == kDspiLastSckToPcs)
{
BW_SPI_CTARn_PASC(baseAddr, whichCtar, prescaler);
BW_SPI_CTARn_ASC(baseAddr, whichCtar, scaler);
}
if (whichDelay == kDspiAfterTransfer)
{
BW_SPI_CTARn_PDT(baseAddr, whichCtar, prescaler);
BW_SPI_CTARn_DT(baseAddr, whichCtar, scaler);
}
}
}
/*FUNCTION**********************************************************************
*
* Function Name : dspi_hal_configure_dma
* Description : Configure transmit and receive DMA requests.
* This function configures the FIFOs to generate a DMA or interrupt request. Note that the
* corresponding request enable must also be set. For the Transmit FIFO Fill, in order
* to generate a DMA request, the Transmit FIFO Fill Request Enable (TFFF_RE) must also be set.
* Similarly for the Receive FIFO Drain Request, to generate a DMA request, the Receive FIFO Drain
* Request Enable (RFDF_RE) must also be set. These request enables can be configured via
* the function dspi_hal_configure_interrupt(). So basically to enable DMA operation, first enable
* the desired request enable using the dspi_hal_configure_interrupt() function and then use
* the dspi_hal_configure_dma() to configure the request to generate a DMA reuqest.
* Function Name : DSPI_HAL_CalculateDelay
* Description : Calculates the delay prescaler and scaler based on desired delay input in
* nano-seconds.
*
* This function calculates the values for:
* PCS to SCK delay pre-scalar (PCSSCK) and scalar (CSSCK), or
* After SCK delay pre-scalar (PASC) and scalar (ASC), or
* Delay after transfer pre-scalar (PDT)and scalar (DT).
*
* These delay names are available in type dspi_delay_type_t.
*
* The user passes which delay they want to configure along with the desired delay value in
* nano-seconds. The function will calculate the values needed for the prescaler and scaler and
* will return the actual calculated delay as an exact delay match may not be acheivable. In this
* case, the closest match will be calculated without going below the desired delay value input.
* It is possible to input a very large delay value that exceeds the capability of the part, in
* which case the maximum supported delay will be returned. It will be up to the higher level
* peripheral driver to alert the user of an out of range delay input.
*END**************************************************************************/
uint32_t DSPI_HAL_CalculateDelay(uint32_t baseAddr, dspi_ctar_selection_t whichCtar,
dspi_delay_type_t whichDelay, uint32_t sourceClockInHz,
uint32_t delayInNanoSec)
{
/* for master mode configuration, if slave mode detected, return 0*/
if (!DSPI_HAL_IsMaster(baseAddr))
{
return 0;
}
uint32_t prescaler, bestPrescaler;
uint32_t scaler, bestScaler;
uint32_t realDelay, bestDelay;
uint32_t diff, min_diff;
uint32_t initialDelayNanoSec;
/* find combination of prescaler and scaler resulting in the delay closest to the
* requested value
*/
min_diff = 0xFFFFFFFFU;
/* Initialize prescaler and scaler to their max values to generate the max delay */
bestPrescaler = 0x3;
bestScaler = 0xF;
bestDelay = (1000000000/sourceClockInHz) * s_delayPrescaler[bestPrescaler] *
s_delayScaler[bestScaler];
/* First calculate the initial, default delay */
initialDelayNanoSec = 1000000000/sourceClockInHz * 2;
/* If the initial, default delay is already greater than the desired delay, then
* set the delays to their initial value (0) and return the delay. In other words,
* there is no way to decrease the delay value further.
*/
if (initialDelayNanoSec >= delayInNanoSec)
{
DSPI_HAL_SetDelay(baseAddr, whichCtar, 0, 0, whichDelay);
return initialDelayNanoSec;
}
/* In all for loops, if min_diff = 0, the exit for loop*/
for (prescaler = 0; (prescaler < 4) && min_diff; prescaler++)
{
for (scaler = 0; (scaler < 16) && min_diff; scaler++)
{
realDelay = (1000000000/sourceClockInHz) * s_delayPrescaler[prescaler] *
s_delayScaler[scaler];
/* calculate the delay difference based on the conditional statement
* that states that the calculated delay must not be less then the desired delay
*/
if (realDelay >= delayInNanoSec)
{
diff = realDelay-delayInNanoSec;
if (min_diff > diff)
{
/* a better match found */
min_diff = diff;
bestPrescaler = prescaler;
bestScaler = scaler;
bestDelay = realDelay;
}
}
}
}
/* write the best dbr, prescalar, and baud rate scalar to the CTAR*/
DSPI_HAL_SetDelay(baseAddr, whichCtar, bestPrescaler, bestScaler, whichDelay);
/* return the actual calculated baud rate*/
return bestDelay;
}
/*FUNCTION**********************************************************************
*
* Function Name : DSPI_HAL_SetTxFifoFillDmaIntMode
* Description : Configures the DSPI Tx FIFO Fill request to generate DMA or interrupt requests.
* This function configures the DSPI Tx FIFO Fill flag to generate either
* an interrupt or DMA request. The user passes in which request they'd like to generate
* of type dspi_dma_or_int_mode_t and whether or not they wish to enable this request.
* Note, when disabling the request, the request type is don't care.
*
* DSPI_HAL_SetTxFifoFillDmaIntMode(baseAddr, kDspiGenerateDmaReq, true); <- to enable DMA
* DSPI_HAL_SetTxFifoFillDmaIntMode(baseAddr, kDspiGenerateIntReq, true); <- to enable Interrupt
* DSPI_HAL_SetTxFifoFillDmaIntMode(baseAddr, kDspiGenerateIntReq, false); <- to disable
*
*END**************************************************************************/
void dspi_hal_configure_dma(uint32_t instance, bool enableTransmit, bool enableReceive)
void DSPI_HAL_SetTxFifoFillDmaIntMode(uint32_t baseAddr, dspi_dma_or_int_mode_t mode, bool enable)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
BW_SPI_RSER_TFFF_DIRS(instance, enableTransmit);
BW_SPI_RSER_RFDF_DIRS(instance, enableReceive);
BW_SPI_RSER_TFFF_DIRS(baseAddr, mode); /* Configure as DMA or interrupt */
BW_SPI_RSER_TFFF_RE(baseAddr, (enable == true)); /* Enable or disable the request */
}
/*FUNCTION**********************************************************************
*
* Function Name : dspi_hal_configure_interrupt
* Description : Configure DSPI interrupts.
* This function will configure the various interrupt sources of the DSPI. The parameters to pass
* in are instance, interrupt source, and enable/disable setting.
* The interrupt source will be of a typedef enum whose value will be the bit position of the
* interrupt source setting within the RSER register. In the DSPI, all of the interrupt
* configuration settings reside within the one register. The typedef enum will equate each
* interrupt source to the bit position defined in the device header file.
* The function will use these bit positions in its algorithm to enable/disable the
* interrupt source, where interrupt source is of type dspi_status_and_interrupt_request_t.
* temp = (HW_SPI_RSER_RD(instance) & ~interruptSrc) | (enable << interruptSrc);
* HW_SPI_RSER_WR(instance, temp);
* Function Name : DSPI_HAL_SetRxFifoDrainDmaIntMode
* Description : Configures the DSPI Rx FIFO Drain request to generate DMA or interrupt requests.
* This function configures the DSPI Rx FIFO Drain flag to generate either
* an interrupt or DMA request. The user passes in which request they'd like to generate
* of type dspi_dma_or_int_mode_t and whether or not they wish to enable this request.
* Note, when disabling the request, the request type is don't care.
*
* dspi_hal_configure_interrupt(instance, kDspiTxComplete, true); <- example use-case
* DSPI_HAL_SetRxFifoDrainDmaIntMode(baseAddr, kDspiGenerateDmaReq, true); <- to enable DMA
* DSPI_HAL_SetRxFifoDrainDmaIntMode(baseAddr, kDspiGenerateIntReq, true); <- to enable Interrupt
* DSPI_HAL_SetRxFifoDrainDmaIntMode(baseAddr, kDspiGenerateIntReq, false); <- to disable
*
*END**************************************************************************/
void dspi_hal_configure_interrupt(uint32_t instance,
void DSPI_HAL_SetRxFifoDrainDmaIntMode(uint32_t baseAddr, dspi_dma_or_int_mode_t mode, bool enable)
{
BW_SPI_RSER_RFDF_DIRS(baseAddr, mode); /* Configure as DMA or interrupt */
BW_SPI_RSER_RFDF_RE(baseAddr, (enable == true)); /* Enable or disable the request */
}
/*FUNCTION**********************************************************************
*
* Function Name : DSPI_HAL_SetIntMode
* Description : Configure DSPI interrupts.
* This function configures the various interrupt sources of the DSPI. The parameters are
* baseAddr, interrupt source, and enable/disable setting.
* The interrupt source is a typedef enum whose value is the bit position of the
* interrupt source setting within the RSER register. In the DSPI, all interrupt
* configuration settings are in one register. The typedef enum equates each
* interrupt source to the bit position defined in the device header file.
* The function uses these bit positions in its algorithm to enable/disable the
* interrupt source, where interrupt source is the dspi_status_and_interrupt_request_t type.
* Note, for Tx FIFO Fill and Rx FIFO Drain requests, use the functions:
* DSPI_HAL_SetTxFifoFillDmaIntMode and DSPI_HAL_SetRxFifoDrainDmaIntMode respectively as
* these requests can generate either an interrupt or DMA request.
*
* DSPI_HAL_SetIntMode(baseAddr, kDspiTxComplete, true); <- example use-case
*
*END**************************************************************************/
void DSPI_HAL_SetIntMode(uint32_t baseAddr,
dspi_status_and_interrupt_request_t interruptSrc,
bool enable)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
uint32_t temp;
temp = (HW_SPI_RSER_RD(instance) & ~(0x1U << interruptSrc)) | ((uint32_t)enable << interruptSrc);
HW_SPI_RSER_WR(instance, temp);
temp = (HW_SPI_RSER_RD(baseAddr) & ~(0x1U << interruptSrc)) |
((uint32_t)enable << interruptSrc);
HW_SPI_RSER_WR(baseAddr, temp);
}
/*FUNCTION**********************************************************************
*
* Function Name : dspi_hal_get_fifo_data
* Function Name : DSPI_HAL_GetFifoData
* Description : Read fifo registers for debug purposes.
*
*END**************************************************************************/
uint32_t dspi_hal_get_fifo_data(uint32_t instance, dspi_fifo_t whichFifo, uint32_t whichFifoEntry)
uint32_t DSPI_HAL_GetFifoData(uint32_t baseAddr, dspi_fifo_t whichFifo, uint32_t whichFifoEntry)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
if (whichFifo == kDspiTxFifo)
{
return HW_SPI_TXFRn_RD(instance, whichFifoEntry);
return HW_SPI_TXFRn_RD(baseAddr, whichFifoEntry);
}
else
{
return HW_SPI_RXFRn_RD(instance, whichFifoEntry);
return HW_SPI_RXFRn_RD(baseAddr, whichFifoEntry);
}
}
/*FUNCTION**********************************************************************
*
* Function Name : dspi_hal_write_data_master_mode
* Function Name : DSPI_HAL_WriteDataMastermode
* Description : Write data into the data buffer, master mode.
* In master mode, the 16-bit data is appended with the 16-bit command info. The command portion
* provides characteristics of the data being sent such as: optional continuous chip select
@ -570,17 +532,16 @@ uint32_t dspi_hal_get_fifo_data(uint32_t instance, dspi_fifo_t whichFifo, uint32
* commandConfig.whichPcs = kDspiPcs1;
* commandConfig.clearTransferCount = false;
* commandConfig.isEndOfQueue = false;
* dspi_hal_write_data_master_mode(instance, &commandConfig, dataWord);
* DSPI_HAL_WriteDataMastermode(baseAddr, &commandConfig, dataWord);
*
*END**************************************************************************/
void dspi_hal_write_data_master_mode(uint32_t instance,
dspi_command_config_t * command,
uint16_t data)
void DSPI_HAL_WriteDataMastermode(uint32_t baseAddr,
dspi_command_config_t * command,
uint16_t data)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
uint32_t temp;
/* First, build up the 32-bit word then write it to the PUSHR */
temp = BF_SPI_PUSHR_CONT(command->isChipSelectContinuous) |
BF_SPI_PUSHR_CTAS(command->whichCtar) |
BF_SPI_PUSHR_PCS(command->whichPcs) |
@ -588,7 +549,53 @@ void dspi_hal_write_data_master_mode(uint32_t instance,
BF_SPI_PUSHR_CTCNT(command->clearTransferCount) |
BF_SPI_PUSHR_TXDATA(data);
HW_SPI_PUSHR_WR(instance, temp);
HW_SPI_PUSHR_WR(baseAddr, temp);
}
/*FUNCTION**********************************************************************
*
* Function Name : DSPI_HAL_WriteDataMastermode
* Description : Write data into the data buffer, master mode and waits till complete to return.
* In master mode, the 16-bit data is appended with the 16-bit command info. The command portion
* provides characteristics of the data being sent such as: optional continuous chip select
* operation between transfers, the desired Clock and Transfer Attributes register to use for the
* associated SPI frame, the desired PCS signal to use for the data transfer, whether the current
* transfer is the last in the queue, and whether to clear the transfer count (normally needed when
* sending the first frame of a data packet). An example use case is as follows:
* dspi_command_config_t commandConfig;
* commandConfig.isChipSelectContinuous = true;
* commandConfig.whichCtar = kDspiCtar0;
* commandConfig.whichPcs = kDspiPcs1;
* commandConfig.clearTransferCount = false;
* commandConfig.isEndOfQueue = false;
* DSPI_HAL_WriteDataMastermode(baseAddr, &commandConfig, dataWord);
*
* Note that this function will not return until after the transmit is complete. Also note that
* the DSPI must be enabled and running in order to transmit data (MCR[MDIS] & [HALT] = 0).
* Since the SPI is a synchronous protocol, receive data will be available when transmit completes.
*
*END**************************************************************************/
void DSPI_HAL_WriteDataMastermodeBlocking(uint32_t baseAddr,
dspi_command_config_t * command,
uint16_t data)
{
uint32_t temp;
/* First, clear Transmit Complete Flag (TCF) */
BW_SPI_SR_TCF(baseAddr, 1);
/* First, build up the 32-bit word then write it to the PUSHR */
temp = BF_SPI_PUSHR_CONT(command->isChipSelectContinuous) |
BF_SPI_PUSHR_CTAS(command->whichCtar) |
BF_SPI_PUSHR_PCS(command->whichPcs) |
BF_SPI_PUSHR_EOQ(command->isEndOfQueue) |
BF_SPI_PUSHR_CTCNT(command->clearTransferCount) |
BF_SPI_PUSHR_TXDATA(data);
HW_SPI_PUSHR_WR(baseAddr, temp);
/* Wait till TCF sets */
while(BR_SPI_SR_TCF(baseAddr) == 0) { }
}
/*******************************************************************************

616
libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/dspi/fsl_dspi_hal.h
View File

@ -30,7 +30,6 @@
#if !defined(__FSL_DSPI_HAL_H__)
#define __FSL_DSPI_HAL_H__
#include <assert.h>
#include <stdint.h>
#include <stdbool.h>
#include "fsl_dspi_features.h"
@ -52,6 +51,11 @@ static const uint32_t s_baudratePrescaler[] = { 2, 3, 5, 7 };
static const uint32_t s_baudrateScaler[] = { 2, 4, 6, 8, 16, 32, 64, 128, 256, 512, 1024, 2048,
4096, 8192, 16384, 32768 };
static const uint32_t s_delayPrescaler[] = { 1, 3, 5, 7 };
static const uint32_t s_delayScaler[] = { 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048,
4096, 8192, 16384, 32768, 65536 };
/*! @brief Error codes for the DSPI driver.*/
typedef enum _dspi_status
{
@ -63,9 +67,9 @@ typedef enum _dspi_status
transfer.*/
kStatus_DSPI_NoTransferInProgress, /*!< Attempt to abort a transfer when no transfer
was in progress*/
kStatus_DSPI_InvalidBitCount, /*!< bits-per-frame value not valid*/
kStatus_DSPI_InvalidInstanceNumber, /*!< DSPI instance number does not match current count*/
kStatus_DSPI_OutOfRange /*< DSPI out-of-range error used in slave callback */
kStatus_DSPI_InvalidBitCount, /*!< bits-per-frame value not valid*/
kStatus_DSPI_InvalidInstanceNumber, /*!< DSPI instance number does not match current count*/
kStatus_DSPI_OutOfRange /*!< DSPI out-of-range error used in slave callback */
} dspi_status_t;
/*! @brief DSPI master or slave configuration*/
@ -132,6 +136,12 @@ typedef enum _dspi_fifo {
kDspiRxFifo = 1 /*!< DSPI Rx FIFO.*/
} dspi_fifo_t;
/*! @brief DSPI Tx FIFO Fill and Rx FIFO Drain DMA or Interrupt configuration */
typedef enum _dspi_dma_or_int_mode {
kDspiGenerateIntReq = 0, /*!< Desired flag generates an Interrupt request */
kDspiGenerateDmaReq = 1 /*!< Desired flag generates a DMA request */
} dspi_dma_or_int_mode_t;
/*! @brief DSPI status flags and interrupt request enable*/
typedef enum _dspi_status_and_interrupt_request {
kDspiTxComplete = BP_SPI_RSER_TCF_RE, /*!< TCF status/interrupt enable */
@ -141,7 +151,6 @@ typedef enum _dspi_status_and_interrupt_request {
kDspiTxFifoFillRequest = BP_SPI_RSER_TFFF_RE, /*!< TFFF status/interrupt enable*/
kDspiRxFifoOverflow = BP_SPI_RSER_RFOF_RE, /*!< RFOF status/interrupt enable*/
kDspiRxFifoDrainRequest = BP_SPI_RSER_RFDF_RE /*!< RFDF status/interrupt enable*/
} dspi_status_and_interrupt_request_t;
/*! @brief DSPI FIFO counter or pointer defines based on bit positions*/
@ -152,6 +161,13 @@ typedef enum _dspi_fifo_counter_pointer {
kDspiTxFifoCounter = BP_SPI_SR_TXCTR /*!< Tx FIFO counter*/
} dspi_fifo_counter_pointer_t;
/*! @brief DSPI delay type selection*/
typedef enum _dspi_delay_type {
kDspiPcsToSck = 1, /*!< PCS-to-SCK delay */
kDspiLastSckToPcs = 2, /*!< Last SCK edge to PCS delay */
kDspiAfterTransfer = 3, /*!< Delay between transfers */
} dspi_delay_type_t;
/*!
* @brief DSPI data format settings configuration structure
*
@ -167,48 +183,10 @@ typedef struct DspiDataFormatConfig {
can be ignored in slave mode */
} dspi_data_format_config_t;
/*!
* @brief DSPI hardware configuration settings for master mode
*
* Use an instance of this structure with the dspi_hal_master_init() to configure the
* most common settings of the DSPI peripheral in master mode with a single function call.
*
* The @c bitsPerSec member is handled in a special way. If this value is set to 0, then the baud is
* not set by the dspi_hal_master_init(), and must be set with a separate call to either the
* dspi_hal_set_baud() or the dspi_hal_set_baud_divisors(). This can be useful when you know the
* divisors in advance and don't want to spend the time to compute them for the provided rate
* in bits/sec.
*
* This structure also contains another structure template as a member:
* @c dspi_data_format_config_t @c dataConfig.
* An example usage for this is assuming declaration @c dspi_master_config_t
* @c dspiConfig:
@code
dspiConfig.dataConfig.bitsPerFrame = 16;
dspiConfig.dataConfig.clkPolarity = kDspiClockPolarity_ActiveHigh;
dspiConfig.dataConfig.clkPhase = kDspiClockPhase_FirstEdge;
dspiConfig.dataConfig.direction = kDspiMsbFirst;
@endcode
*/
typedef struct DspiMasterConfig {
bool isEnabled; /*!< Set to true to enable the DSPI peripheral.*/
dspi_ctar_selection_t whichCtar; /*!< Desired Clock and Transfer Attributes Register (CTAR)*/
uint32_t bitsPerSec; /*!< Baud rate in bits per second*/
uint32_t sourceClockInHz; /*!< Module source clock */
dspi_data_format_config_t dataConfig; /*!< Data format configuration structure*/
bool isSckContinuous; /*!< Disable(0) or Enable(1) continuous SCK operation*/
dspi_which_pcs_config_t whichPcs; /*!< Desired Peripheral Chip Select (PCS) */
dspi_pcs_polarity_config_t pcsPolarity; /*!< Peripheral Chip Select (PCS) polarity setting.*/
dspi_master_sample_point_t masterInSample; /*!< Master data-in (SIN) sample point setting.*/
bool isModifiedTimingFormatEnabled; /*!< Disable(0) or Enable(1) modified timing format.*/
bool isTxFifoDisabled; /*!< Disable(1) or Enable(0) Tx FIFO */
bool isRxFifoDisabled; /*!< Disable(1) or Enable(0) Rx FIFO */
} dspi_master_config_t;
/*!
* @brief DSPI hardware configuration settings for slave mode.
*
* Use an instance of this structure with the dspi_hal_slave_init() to configure the
* Use an instance of this structure with the DSPI_HAL_SlaveInit() to configure the
* most common settings of the DSPI peripheral in slave mode with a single function call.
*/
typedef struct DspiSlaveConfig {
@ -222,8 +200,8 @@ typedef struct DspiSlaveConfig {
* @brief DSPI baud rate divisors settings configuration structure.
*
* Note: These settings are relevant only in master mode.
* This structure contains the baud rate divisor settings, which provides the user with the option to
* explicitly set these baud rate divisors. In addition, the user must also set the
* This structure contains the baud rate divisor settings, which provides the user with the option
* to explicitly set these baud rate divisors. In addition, the user must also set the
* CTARn register with the divisor settings.
*/
typedef struct DspiBaudRateDivisors {
@ -232,22 +210,6 @@ typedef struct DspiBaudRateDivisors {
uint32_t baudRateDivisor; /*!< Baud Rate scaler parameter setting */
} dspi_baud_rate_divisors_t;
/*!
* @brief DSPI delay settings configuration structure
*
* Note: These settings are relevant only in master mode.
* This structure contains the various delay settings. These settings apply to a specific
* CTARn register, which the user must provide in this structure.
*/
typedef struct DspiDelaySettingsConfig {
uint32_t pcsToSckPre; /*!< PCS to SCK delay pre-scalar (PCSSCK) */
uint32_t pcsToSck; /*!< PCS to SCK Delay scalar (CSSCK) */
uint32_t afterSckPre; /*!< After SCK delay pre-scalar (PASC)*/
uint32_t afterSck; /*!< After SCK delay scalar (ASC)*/
uint32_t afterTransferPre; /*!< Delay after transfer pre-scalar (PDT)*/
uint32_t afterTransfer; /*!< Delay after transfer scalar (DT) */
} dspi_delay_settings_config_t;
/*!
* @brief DSPI command and data configuration structure
*
@ -269,6 +231,12 @@ typedef struct DspiCommandDataConfig {
bool clearTransferCount; /*!< Clears SPI_TCNT field; cleared before transmission starts*/
} dspi_command_config_t;
/*******************************************************************************
* Variables
******************************************************************************/
extern const uint32_t spi_base_addr[];
/*******************************************************************************
* API
******************************************************************************/
@ -282,93 +250,34 @@ extern "C" {
* @{
*/
/*!
* @brief Configure the DSPI peripheral in master mode
*
* This function initializes the module to the user defined settings and default settings in master
* mode. This is an example demonstrating how to define the dspi_master_config_t structure and call
* the dspi_hal_master_init function:
@code
dspi_master_config_t dspiConfig;
dspiConfig.isEnabled = false;
dspiConfig.whichCtar = kDspiCtar0;
dspiConfig.bitsPerSec = 0;
dspiConfig.sourceClockInHz = dspiSourceClock;
dspiConfig.isSckContinuous = false;
dspiConfig.whichPcs = kDspiPcs0;
dspiConfig.pcsPolarity = kDspiPcs_ActiveLow;
dspiConfig.masterInSample = kDspiSckToSin_0Clock;
dspiConfig.isModifiedTimingFormatEnabled = false;
dspiConfig.isTxFifoDisabled = false;
dspiConfig.isRxFifoDisabled = false;
dspiConfig.dataConfig.bitsPerFrame = 16;
dspiConfig.dataConfig.clkPolarity = kDspiClockPolarity_ActiveHigh;
dspiConfig.dataConfig.clkPhase = kDspiClockPhase_FirstEdge;
dspiConfig.dataConfig.direction = kDspiMsbFirst;
dspi_hal_master_init(instance, &dspiConfig, calculatedBaudRate);
@endcode
*
* @param instance Module instance number
* @param config Pointer to the master mode configuration data structure
* @param calculatedBaudRate The calculated baud rate passed back to the user for them to determine
* if the calculated baud rate is close enough to meet their needs.
* @return An error code or kStatus_DSPI_Success.
*/
dspi_status_t dspi_hal_master_init(uint32_t instance, const dspi_master_config_t * config,
uint32_t * calculatedBaudRate);
/*!
* @brief Configures the DSPI peripheral in slave mode.
*
* This function initializes the DSPI module for slave mode. This is an example demonstrating how
* to define the dspi_slave_config_t structure and call the dspi_hal_slave_init function:
@code
dspi_slave_config_t dspiConfig;
dspiConfig.isEnabled = false;
dspiConfig.isTxFifoDisabled = false;
dspiConfig.isRxFifoDisabled = false;
dspiConfig.dataConfig.bitsPerFrame = 16;
dspiConfig.dataConfig.clkPolarity = kDspiClockPolarity_ActiveHigh;
dspiConfig.dataConfig.clkPhase = kDspiClockPhase_FirstEdge;
dspi_hal_slave_init(instance, &dspiConfig);
@endcode
*
* @param instance Module instance number
* @param config Pointer to the slave mode configuration data structure
* @return An error code or kStatus_DSPI_Success.
*/
dspi_status_t dspi_hal_slave_init(uint32_t instance, const dspi_slave_config_t * config);
/*!
* @brief Restores the DSPI to reset the configuration.
*
* This function basically resets all of the DSPI registers to their default setting including
* disabling the module.
*
* @param instance Module instance number
* @param baseAddr Module base address
*/
void dspi_hal_reset(uint32_t instance);
void DSPI_HAL_Init(uint32_t baseAddr);
/*!
* @brief Enable the DSPI peripheral, set MCR MDIS to 0.
* @brief Enables the DSPI peripheral and sets the MCR MDIS to 0.
*
* @param instance Module instance number
* @param baseAddr Module base address
*/
static inline void dspi_hal_enable(uint32_t instance)
static inline void DSPI_HAL_Enable(uint32_t baseAddr)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
HW_SPI_MCR_CLR(instance, BM_SPI_MCR_MDIS);
BW_SPI_MCR_MDIS(baseAddr, 0);
}
/*!
* @brief Disables the DSPI peripheral, sets MCR MDIS to 1.
*
* @param instance Module instance number
* @param baseAddr Module base address
*/
static inline void dspi_hal_disable(uint32_t instance)
static inline void DSPI_HAL_Disable(uint32_t baseAddr)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
HW_SPI_MCR_SET(instance, BM_SPI_MCR_MDIS);
BW_SPI_MCR_MDIS(baseAddr, 1);
}
/*!
@ -379,65 +288,74 @@ static inline void dspi_hal_disable(uint32_t instance)
* baud rate in bits-per-second. It requires that the caller also provide the frequency of the
* module source clock (in Hertz).
*
* @param instance Module instance number
* @param baseAddr Module base address
* @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of the type
* dspi_ctar_selection_t
* @param bitsPerSec The desired baud rate in bits per second
* @param sourceClockInHz Module source input clock in Hertz
* @return The actual calculated baud rate
*/
uint32_t dspi_hal_set_baud(uint32_t instance, dspi_ctar_selection_t whichCtar, uint32_t bitsPerSec,
uint32_t sourceClockInHz);
uint32_t DSPI_HAL_SetBaudRate(uint32_t baseAddr, dspi_ctar_selection_t whichCtar,
uint32_t bitsPerSec, uint32_t sourceClockInHz);
/*!
* @brief Configures the baud rate divisors manually.
*
* This function allows the caller to manually set the baud rate divisors in the event that
* these dividers are known and the caller does not wish to call the dspi_hal_set_baud function.
* these dividers are known and the caller does not wish to call the DSPI_HAL_SetBaudRate function.
*
* @param instance Module instance number
* @param baseAddr Module base address
* @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of type
* dspi_ctar_selection_t
* @param divisors Pointer to a structure containing the user defined baud rate divisor settings
*/
void dspi_hal_set_baud_divisors(uint32_t instance,
dspi_ctar_selection_t whichCtar,
const dspi_baud_rate_divisors_t * divisors);
void DSPI_HAL_SetBaudDivisors(uint32_t baseAddr,
dspi_ctar_selection_t whichCtar,
const dspi_baud_rate_divisors_t * divisors);
/*!
* @brief Configures the DSPI for master or slave.
*
* @param instance Module instance number
* @param baseAddr Module base address
* @param mode Mode setting (master or slave) of type dspi_master_slave_mode_t
*/
static inline void dspi_hal_set_master_slave(uint32_t instance, dspi_master_slave_mode_t mode)
static inline void DSPI_HAL_SetMasterSlaveMode(uint32_t baseAddr, dspi_master_slave_mode_t mode)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
BW_SPI_MCR_MSTR(instance, (uint32_t)mode);
BW_SPI_MCR_MSTR(baseAddr, (uint32_t)mode);
}
/*!
* @brief Returns whether the DSPI module is in master mode.
*
* @param baseAddr Module base address
* @retval true The module is in master mode.
* @retval false The module is in slave mode.
*/
static inline bool DSPI_HAL_IsMaster(uint32_t baseAddr)
{
return (bool)BR_SPI_MCR_MSTR(baseAddr);
}
/*!
* @brief Configures the DSPI for the continuous SCK operation.
*
* @param instance Module instance number
* @param baseAddr Module base address
* @param enable Enables (true) or disables(false) continuous SCK operation.
*/
static inline void dspi_hal_configure_continuous_sck(uint32_t instance, bool enable)
static inline void DSPI_HAL_SetContinuousSckCmd(uint32_t baseAddr, bool enable)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
BW_SPI_MCR_CONT_SCKE(instance, (enable == true));
BW_SPI_MCR_CONT_SCKE(baseAddr, (enable == true));
}
/*!
* @brief Configures the DSPI to enable modified timing format.
*
* @param instance Module instance number
* @param baseAddr Module base address
* @param enable Enables (true) or disables(false) modified timing format.
*/
static inline void dspi_hal_configure_modified_timing_format(uint32_t instance, bool enable)
static inline void DSPI_HAL_SetModifiedTimingFormatCmd(uint32_t baseAddr, bool enable)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
BW_SPI_MCR_MTFE(instance, (enable == true));
BW_SPI_MCR_MTFE(baseAddr, (enable == true));
}
/*!
@ -448,14 +366,13 @@ static inline void dspi_hal_configure_modified_timing_format(uint32_t instance,
* Chip Select in master mode. When configured as a strobe, it provides a signal to an external
* demultiplexer to decode PCS[0] to PCS[4] signals into as many as 128 glitch-free PCS signals.
*
* @param instance Module instance number
* @param baseAddr Module base address
* @param enable Enable (true) PCS[5] to operate as the peripheral chip select (PCS) strobe
* If disable (false), PCS[5] operates as a peripheral chip select
*/
static inline void dspi_hal_configure_pcs_strobe(uint32_t instance, bool enable)
static inline void DSPI_HAL_SetPcsStrobeCmd(uint32_t baseAddr, bool enable)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
BW_SPI_MCR_PCSSE(instance, (enable == true));
BW_SPI_MCR_PCSSE(baseAddr, (enable == true));
}
/*!
@ -465,14 +382,13 @@ static inline void dspi_hal_configure_pcs_strobe(uint32_t instance, bool enable)
* receive shift register when the Rx FIFO is full. Otherwise when disabled, the incoming data
* is ignored when the RX FIFO is full.
*
* @param instance Module instance number.
* @param baseAddr Module base address.
* @param enable If enabled (true), allows incoming data to overwrite Rx FIFO contents when full,
* else incoming data is ignored.
*/
static inline void dspi_hal_configure_rx_fifo_overwrite(uint32_t instance, bool enable)
static inline void DSPI_HAL_SetRxFifoOverwriteCmd(uint32_t baseAddr, bool enable)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
BW_SPI_MCR_ROOE(instance, (enable == true));
BW_SPI_MCR_ROOE(baseAddr, (enable == true));
}
/*!
@ -482,60 +398,54 @@ static inline void dspi_hal_configure_rx_fifo_overwrite(uint32_t instance, bool
* corresponding desired polarity and configures the PCS signal to operate with the
* desired characteristic.
*
* @param instance Module instance number
* @param baseAddr Module base address
* @param pcs The particular peripheral chip select (parameter value is of type
* dspi_which_pcs_config_t) for which we wish to apply the active high or active
* low characteristic.
* @param activeLowOrHigh The setting for either "active high, inactive low (0)" or
* "active low, inactive high(1)" of type dspi_pcs_polarity_config_t.
*/
void dspi_hal_configure_pcs_polarity(uint32_t instance, dspi_which_pcs_config_t pcs,
dspi_pcs_polarity_config_t activeLowOrHigh);
void DSPI_HAL_SetPcsPolarityMode(uint32_t baseAddr, dspi_which_pcs_config_t pcs,
dspi_pcs_polarity_config_t activeLowOrHigh);
/*!
* @brief Configures the DSPI FIFOs.
* @brief Enables (or disables) the DSPI FIFOs.
*
* This function allows the caller to disable/enable the Tx and Rx FIFOs (independently).
* Note that to disable, the caller must pass in a logic 1 (true) for the particular FIFO
* configuration. To enable, the caller must pass in a logic 0 (false). For example, to enable
* both the Tx and Rx FIFOs, the caller makes this function call (where instance is the
* desired module instance number):
@code
dspi_hal_configure_fifos(instance, false, false);
@endcode
* Note that to disable, the caller must pass in a logic 0 (false) for the particular FIFO
* configuration. To enable, the caller must pass in a logic 1 (true).
*
* @param instance Module instance number
* @param disableTxFifo Disables (false) the TX FIFO, else enables (true) the TX FIFO
* @param disableRxFifo Disables (false) the RX FIFO, else enables (true) the RX FIFO
* @param baseAddr Module instance number
* @param enableTxFifo Disables (false) the TX FIFO, else enables (true) the TX FIFO
* @param enableRxFifo Disables (false) the RX FIFO, else enables (true) the RX FIFO
*/
void dspi_hal_configure_fifos(uint32_t instance, bool disableTxFifo, bool disableRxFifo);
void DSPI_HAL_SetFifoCmd(uint32_t baseAddr, bool enableTxFifo, bool enableRxFifo);
/*!
* @brief Flushes the DSPI FIFOs.
*
* @param instance Module instance number
* @param baseAddr Module base address
* @param enableFlushTxFifo Flushes (true) the Tx FIFO, else do not flush (false) the Tx FIFO
* @param enableFlushRxFifo Flushes (true) the Rx FIFO, else do not flush (false) the Rx FIFO
*/
void dspi_hal_flush_fifos(uint32_t instance, bool enableFlushTxFifo, bool enableFlushRxFifo);
void DSPI_HAL_SetFlushFifoCmd(uint32_t baseAddr, bool enableFlushTxFifo, bool enableFlushRxFifo);
/*!
* @brief Configures when the DSPI master samples SIN in the Modified Transfer Format
* @brief Configures the time when the DSPI master samples SIN in the Modified Transfer Format.
*
* This function controls when the DSPI master samples SIN (data in) in the Modified Transfer
* Format. Note that this is valid only when the CPHA bit in the CTAR register is 0.
*
* @param instance Module instance number
* @param baseAddr Module base address
* @param samplePnt selects when the data in (SIN) is sampled, of type dspi_master_sample_point_t.
* This value selects either 0, 1, or 2 system clocks between the SCK edge
* and the SIN (data in) sample.
*/
static inline void dspi_hal_set_datain_samplepoint(uint32_t instance,
static inline void DSPI_HAL_SetDatainSamplepointMode(uint32_t baseAddr,
dspi_master_sample_point_t samplePnt)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
BW_SPI_MCR_SMPL_PT(instance, samplePnt);
BW_SPI_MCR_SMPL_PT(baseAddr, samplePnt);
}
@ -545,12 +455,11 @@ static inline void dspi_hal_set_datain_samplepoint(uint32_t instance,
* This function call called whenever the module is ready to begin data transfers in either master
* or slave mode.
*
* @param instance Module instance number
* @param baseAddr Module base address
*/
static inline void dspi_hal_start_transfer(uint32_t instance)
static inline void DSPI_HAL_StartTransfer(uint32_t baseAddr)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
HW_SPI_MCR_CLR(instance, BM_SPI_MCR_HALT);
BW_SPI_MCR_HALT(baseAddr, 0);
}
/*!
@ -558,12 +467,11 @@ static inline void dspi_hal_start_transfer(uint32_t instance)
*
* This function call stops data transfers in either master or slave mode.
*
* @param instance Module instance number
* @param baseAddr Module base address
*/
static inline void dspi_hal_stop_transfer(uint32_t instance)
static inline void DSPI_HAL_StopTransfer(uint32_t baseAddr)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
HW_SPI_MCR_SET(instance, BM_SPI_MCR_HALT);
BW_SPI_MCR_HALT(baseAddr, 1);
}
/*!
@ -577,72 +485,72 @@ static inline void dspi_hal_stop_transfer(uint32_t instance)
dataFormat.clkPolarity = kDspiClockPolarity_ActiveLow;
dataFormat.clkPhase = kDspiClockPhase_FirstEdge;
dataFormat.direction = kDspiMsbFirst;
dspi_hal_configure_data_format(instance, kDspiCtar0, &dataFormat);
DSPI_HAL_SetDataFormat(instance, kDspiCtar0, &dataFormat);
@endcode
*
* @param instance Module instance number
* @param baseAddr Module base address
* @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of type
* dspi_ctar_selection_t.
* @param config Pointer to a structure containing the user defined data format configuration settings.
* @param config Pointer to structure containing user defined data format configuration settings.
* @return An error code or kStatus_DSPI_Success
*/
dspi_status_t dspi_hal_configure_data_format(uint32_t instance,
dspi_ctar_selection_t whichCtar,
const dspi_data_format_config_t * config);
dspi_status_t DSPI_HAL_SetDataFormat(uint32_t baseAddr,
dspi_ctar_selection_t whichCtar,
const dspi_data_format_config_t * config);
/*!
* @brief Configures the delays for a particular CTAR, master mode only.
* @brief Manually configures the delay prescaler and scaler for a particular CTAR.
*
* This function configures the PCS to SCK delay pre-scalar (PCSSCK),
* the PCS to SCK Delay scalar (CSSCK),
* the After SCK delay pre-scalar (PASC),
* the After SCK delay scalar (ASC),
* the Delay after transfer pre-scalar (PDT),
* and the Delay after transfer scalar (DT).
* The following is an example use case of this function:
* @code
dspi_delay_settings_config_t delayConfig;
delayConfig.pcsToSckPre = 0x3;
delayConfig.pcsToSck = 0xF;
delayConfig.afterSckPre = 0x2;
delayConfig.afterSck = 0xA;
delayConfig.afterTransferPre = 0x1;
delayConfig.afterTransfer = 0x5;
dspi_hal_configure_delays(instance, kDspiCtar0, &delayConfig);
* @endcode
* This function configures the PCS to SCK delay pre-scalar (PCSSCK) and scalar (CSSCK),
* after SCK delay pre-scalar (PASC) and scalar (ASC), and the delay
* after transfer pre-scalar (PDT)and scalar (DT).
*
* @param instance Module instance number
* These delay names are available in type dspi_delay_type_t.
*
* The user passes which delay they want to configure along with the prescaler and scaler value.
* This allows the user to directly set the prescaler/scaler values if they have
* pre-calculated them or if they simply wish to manually increment either value.
*
* @param baseAddr Module base address
* @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of type
* dspi_ctar_selection_t.
* @param config Pointer to a structure containing the user defined delay configuration settings.
* @param prescaler The prescaler delay value (can be an integer 0, 1, 2, or 3).
* @param prescaler The scaler delay value (can be any integer between 0 to 15).
* @param whichDelay The desired delay to configure, must be of type dspi_delay_type_t
*/
void dspi_hal_configure_delays(uint32_t instance,
dspi_ctar_selection_t whichCtar,
const dspi_delay_settings_config_t * config);
void DSPI_HAL_SetDelay(uint32_t baseAddr, dspi_ctar_selection_t whichCtar, uint32_t prescaler,
uint32_t scaler, dspi_delay_type_t whichDelay);
/*@}*/
/*!
* @name DMA
* @{
*/
/*!
* @brief Configures transmit and receive DMA requests.
* @brief Calculates the delay prescaler and scaler based on the desired delay input in nanoseconds.
*
* This function configures the FIFOs to generate a DMA or an interrupt request. Note that the
* corresponding request enable must also be set. For the Transmit FIFO Fill, in order
* to generate a DMA request, the Transmit FIFO Fill Request Enable (TFFF_RE) must also be set.
* Similarly for the Receive FIFO Drain Request, to generate a DMA request, the Receive FIFO Drain
* Request Enable (RFDF_RE) must also be set. These requests can be configured with
* the function dspi_hal_configure_interrupt(). To enable DMA operation, first enable
* the desired request enable by using the dspi_hal_configure_interrupt() function and then use
* the dspi_hal_configure_dma() to configure the request and generate a DMA request.
* This function calculates the values for:
* PCS to SCK delay pre-scalar (PCSSCK) and scalar (CSSCK), or
* After SCK delay pre-scalar (PASC) and scalar (ASC), or
* Delay after transfer pre-scalar (PDT)and scalar (DT).
*
* @param enableTransmit Configures Tx FIFO fill request to generate a DMA or interrupt request
* @param enableReceive Configures Rx FIFO fill request to generate a DMA or interrupt request
* These delay names are available in type dspi_delay_type_t.
*
* The user passes which delay they want to configure along with the desired delay value in
* nano-seconds. The function calculates the values needed for the prescaler and scaler and
* returning the actual calculated delay as an exact delay match may not be possible. In this
* case, the closest match is calculated without going below the desired delay value input.
* It is possible to input a very large delay value that exceeds the capability of the part, in
* which case the maximum supported delay will be returned. It is to the higher level
* peripheral driver to alert the user of an out of range delay input.
*
* @param baseAddr Module base address
* @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of type
* dspi_ctar_selection_t.
* @param whichDelay The desired delay to configure, must be of type dspi_delay_type_t
* @param sourceClockInHz Module source input clock in Hertz
* @param delayInNanoSec The desired delay value in nano-seconds.
* @return The actual calculated delay value.
*/
void dspi_hal_configure_dma(uint32_t instance, bool enableTransmit, bool enableReceive);
uint32_t DSPI_HAL_CalculateDelay(uint32_t baseAddr, dspi_ctar_selection_t whichCtar,
dspi_delay_type_t whichDelay, uint32_t sourceClockInHz,
uint32_t delayInNanoSec);
/*@}*/
@ -658,14 +566,13 @@ void dspi_hal_configure_dma(uint32_t instance, bool enableTransmit, bool enableR
* When disabled, the doze mode has no effect on the DSPI, and when enabled, the Doze mode
* disables the DSPI.
*
* @param instance Module instance number
* @param enable If disabled (false), the doze mode has no effect on the DSPI, if enabled (true), the doze mode
* disables the DSPI.
* @param baseAddr Module base address
* @param enable If disabled (false), the doze mode has no effect on the DSPI, if enabled (true),
* the doze mode disables the DSPI.
*/
static inline void dspi_hal_configure_doze_mode(uint32_t instance, bool enable)
static inline void DSPI_HAL_SetDozemodeCmd(uint32_t baseAddr, bool enable)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
BW_SPI_MCR_DOZE(instance, (enable == true));
BW_SPI_MCR_DOZE(baseAddr, (enable == true));
}
/*@}*/
@ -675,55 +582,93 @@ static inline void dspi_hal_configure_doze_mode(uint32_t instance, bool enable)
* @{
*/
/*!
* @brief Configures the DSPI Tx FIFO fill request to generate DMA or interrupt requests.
*
* This function configures the DSPI Tx FIFO Fill flag to generate either
* an interrupt or DMA request. The user passes in which request they'd like to generate
* of type dspi_dma_or_int_mode_t and whether or not they wish to enable this request.
* Note, when disabling the request, the request type is don't care.
@code
DSPI_HAL_SetTxFifoFillDmaIntMode(baseAddr, kDspiGenerateDmaReq, true); <- to enable DMA
DSPI_HAL_SetTxFifoFillDmaIntMode(baseAddr, kDspiGenerateIntReq, true); <- to enable Interrupt
DSPI_HAL_SetTxFifoFillDmaIntMode(baseAddr, kDspiGenerateIntReq, false); <- to disable
@endcode
* @param baseAddr Module base address
* @param mode Configures the DSPI Tx FIFO Fill to generate an interrupt or DMA request
* @param enable Enable (true) or disable (false) the DSPI Tx FIFO Fill flag to generate requests
*/
void DSPI_HAL_SetTxFifoFillDmaIntMode(uint32_t baseAddr, dspi_dma_or_int_mode_t mode, bool enable);
/*!
* @brief Configures the DSPI Rx FIFO Drain request to generate DMA or interrupt requests.
*
* This function configures the DSPI Rx FIFO Drain flag to generate either
* an interrupt or a DMA request. The user passes in which request they'd like to generate
* of type dspi_dma_or_int_mode_t and whether or not they wish to enable this request.
* Note, when disabling the request, the request type is don't care.
@code
DSPI_HAL_SetRxFifoDrainDmaIntMode(baseAddr, kDspiGenerateDmaReq, true); <- to enable DMA
DSPI_HAL_SetRxFifoDrainDmaIntMode(baseAddr, kDspiGenerateIntReq, true); <- to enable Interrupt
DSPI_HAL_SetRxFifoDrainDmaIntMode(baseAddr, kDspiGenerateIntReq, false); <- to disable
@endcode
* @param baseAddr Module base address
* @param mode Configures the Rx FIFO Drain to generate an interrupt or DMA request
* @param enable Enable (true) or disable (false) the Rx FIFO Drain flag to generate requests
*/
void DSPI_HAL_SetRxFifoDrainDmaIntMode(uint32_t baseAddr, dspi_dma_or_int_mode_t mode, bool enable);
/*!
* @brief Configures the DSPI interrupts.
*
* This function configures the various interrupt sources of the DSPI. The parameters are instance, interrupt source, and enable/disable setting.
* The interrupt source is a typedef enum whose value is the bit position of the
* This function configures the various interrupt sources of the DSPI. The parameters are
* baseAddr, interrupt source, and enable/disable setting.
* The interrupt source is a typedef enumeration whose value is the bit position of the
* interrupt source setting within the RSER register. In the DSPI, all interrupt
* configuration settings are in one register. The typedef enum equates each
* interrupt source to the bit position defined in the device header file.
* The function uses these bit positions in its algorithm to enable/disable the
* interrupt source, where interrupt source is the dspi_status_and_interrupt_request_t type.
* @code
temp = (HW_SPI_RSER_RD(instance) & ~interruptSrc) | (enable << interruptSrc);
HW_SPI_RSER_WR(instance, temp);
dspi_hal_configure_interrupt(instance, kDspiTxComplete, true); <- example use-case
* @endcode
* Note, for Tx FIFO Fill and Rx FIFO Drain requests, use the functions:
* DSPI_HAL_SetTxFifoFillDmaIntMode and DSPI_HAL_SetRxFifoDrainDmaIntMode respectively as
* these requests can generate either an interrupt or DMA request.
@code
DSPI_HAL_SetIntMode(baseAddr, kDspiTxComplete, true); <- example use-case
@endcode
*
* @param instance Module instance number
* @param baseAddr Module base address
* @param interruptSrc The interrupt source, of type dspi_status_and_interrupt_request_t
* @param enable Enable (true) or disable (false) the interrupt source to generate requests
*/
void dspi_hal_configure_interrupt(uint32_t instance,
void DSPI_HAL_SetIntMode(uint32_t baseAddr,
dspi_status_and_interrupt_request_t interruptSrc,
bool enable);
/*!
* @brief Gets the DSPI interrupt configuration, returns if interrupt request is enabled or disabled.
* @brief Gets DSPI interrupt configuration, returns if interrupt request is enabled or disabled.
*
* This function returns the requested interrupt source setting (enabled or disabled, of
* type bool). The parameters to pass in are instance and interrupt source. It utilizes the
* same enum definitions for the interrupt sources as described in the "interrupt configuration"
* type bool). The parameters to pass in are baseAddr and interrupt source. It utilizes the
* same enumeration definitions for the interrupt sources as described in the "interrupt configuration"
* function. The function uses these bit positions in its algorithm to obtain the desired
* interrupt source setting.
* @code
return ((HW_SPI_RSER_RD(instance) & interruptSrc) >> interruptSrc);
getInterruptSetting = dspi_hal_get_interrupt_config(instance, kDspiTxComplete);
* @endcode
* Note, for Tx FIFO Fill and Rx FIFO Drain requests, this returns whether or not their
* requests are enabled.
@code
getInterruptSetting = DSPI_HAL_GetIntMode(baseAddr, kDspiTxComplete);
@endcode
*
* @param instance Module instance number
* @param baseAddr Module base address
* @param interruptSrc The interrupt source, of type dspi_status_and_interrupt_request_t
* @return Configuration of interrupt request: enable (true) or disable (false).
*/
static inline bool dspi_hal_get_interrupt_config(uint32_t instance,
static inline bool DSPI_HAL_GetIntMode(uint32_t baseAddr,
dspi_status_and_interrupt_request_t interruptSrc)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
return ((HW_SPI_RSER_RD(instance) >> interruptSrc) & 0x1);
return ((HW_SPI_RSER_RD(baseAddr) >> interruptSrc) & 0x1);
}
/*@}*/
@ -736,48 +681,42 @@ static inline bool dspi_hal_get_interrupt_config(uint32_t instance,
/*!
* @brief Gets the DSPI status flag state.
*
* The status flag is defined in the same enum as the interrupt source enable because the bit
* The status flag is defined in the same enumeration as the interrupt source enable because the bit
* position of the interrupt source and corresponding status flag are the same in the RSER and
* SR registers. The function uses these bit positions in its algorithm to obtain the desired
* flag state, similar to the dspi_get_interrupt_config function.
* @code
return ((HW_SPI_SR_RD(instance) & statusFlag) >> statusFlag);
getStatus = dspi_hal_get_status_flag(instance, kDspiTxComplete);
* @endcode
@code
getStatus = DSPI_HAL_GetStatusFlag(baseAddr, kDspiTxComplete);
@endcode
*
* @param instance Module instance number
* @param baseAddr Module base address
* @param statusFlag The status flag, of type dspi_status_and_interrupt_request_t
* @return State of the status flag: asserted (true) or not-asserted (false)
*/
static inline bool dspi_hal_get_status_flag(uint32_t instance,
static inline bool DSPI_HAL_GetStatusFlag(uint32_t baseAddr,
dspi_status_and_interrupt_request_t statusFlag)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
return ((HW_SPI_SR_RD(instance) >> statusFlag) & 0x1);
return ((HW_SPI_SR_RD(baseAddr) >> statusFlag) & 0x1);
}
/*!
* @brief Clears the DSPI status flag.
*
* This function clears the desired status bit by using a write-1-to-clear. The user passes in
* the instance and the desired status bit to clear. The list of status bits is defined in the
* the baseAddr and the desired status bit to clear. The list of status bits is defined in the
* dspi_status_and_interrupt_request_t. The function uses these bit positions in its algorithm
* to clear the desired flag state. It uses this macro:
* @code
HW_SPI_SR_WR(instance, statusFlag);
dspi_hal_clear_status_flag(instance, kDspiTxComplete);
* @endcode
* to clear the desired flag state. Example usage:
@code
DSPI_HAL_ClearStatusFlag(baseAddr, kDspiTxComplete);
@endcode
*
* @param instance Module instance number
* @param baseAddr Module base address
* @param statusFlag The status flag, of type dspi_status_and_interrupt_request_t
*/
static inline void dspi_hal_clear_status_flag(uint32_t instance,
static inline void DSPI_HAL_ClearStatusFlag(uint32_t baseAddr,
dspi_status_and_interrupt_request_t statusFlag)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
HW_SPI_SR_SET(instance, (0x1U << statusFlag));
HW_SPI_SR_SET(baseAddr, (0x1U << statusFlag));
}
@ -785,23 +724,20 @@ static inline void dspi_hal_clear_status_flag(uint32_t instance,
* @brief Gets the DSPI FIFO counter or pointer.
*
* This function returns the number of entries or the next pointer in the Tx or Rx FIFO.
* The parameters to pass in are the instance and either the Tx or Rx FIFO counter or a
* pointer. The latter is an enum type defined as the bitmask of
* those particular bit fields found in the device header file. For example:
* @code
return ((HW_SPI_SR_RD(instance) >> desiredParamter) & 0xF);
dspi_hal_get_fifo_counter_or_pointer(instance, kDspiRxFifoCounter);
* @endcode
* The parameters to pass in are the baseAddr and either the Tx or Rx FIFO counter or a
* pointer. The latter is an enumeration type defined as the bitmask of
* those particular bit fields found in the device header file. Example usage:
@code
DSPI_HAL_GetFifoCountOrPtr(baseAddr, kDspiRxFifoCounter);
@endcode
*
* @param instance Module instance number
* @param baseAddr Module base address
* @param desiredParameter Desired parameter to obtain, of type dspi_fifo_counter_pointer_t
*/
static inline uint32_t dspi_hal_get_fifo_counter_or_pointer(uint32_t instance,
static inline uint32_t DSPI_HAL_GetFifoCountOrPtr(uint32_t baseAddr,
dspi_fifo_counter_pointer_t desiredParameter)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
return ((HW_SPI_SR_RD(instance) >> desiredParameter) & 0xFU);
return ((HW_SPI_SR_RD(baseAddr) >> desiredParameter) & 0xFU);
}
@ -815,12 +751,11 @@ static inline uint32_t dspi_hal_get_fifo_counter_or_pointer(uint32_t instance,
/*!
* @brief Reads data from the data buffer.
*
* @param instance Module instance number
* @param baseAddr Module base address
*/
static inline uint32_t dspi_hal_read_data(uint32_t instance)
static inline uint32_t DSPI_HAL_ReadData(uint32_t baseAddr)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
return HW_SPI_POPR_RD(instance);
return HW_SPI_POPR_RD(baseAddr);
}
/*!
@ -828,13 +763,12 @@ static inline uint32_t dspi_hal_read_data(uint32_t instance)
*
* In slave mode, up to 32-bit words may be written.
*
* @param instance Module instance number
* @param baseAddr Module base address
* @param data The data to send
*/
static inline void dspi_hal_write_data_slave_mode(uint32_t instance, uint32_t data)
static inline void DSPI_HAL_WriteDataSlavemode(uint32_t baseAddr, uint32_t data)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
HW_SPI_PUSHR_SLAVE_WR(instance, data);
HW_SPI_PUSHR_SLAVE_WR(baseAddr, data);
}
/*!
@ -846,36 +780,66 @@ static inline void dspi_hal_write_data_slave_mode(uint32_t instance, uint32_t da
* associated SPI frame, the desired PCS signal to use for the data transfer, whether the current
* transfer is the last in the queue, and whether to clear the transfer count (normally needed when
* sending the first frame of a data packet). This is an example:
* @code
@code
dspi_command_config_t commandConfig;
commandConfig.isChipSelectContinuous = true;
commandConfig.whichCtar = kDspiCtar0;
commandConfig.whichPcs = kDspiPcs1;
commandConfig.clearTransferCount = false;
commandConfig.isEndOfQueue = false;
dspi_hal_write_data_master_mode(instance, &commandConfig, dataWord);
* endcode
DSPI_HAL_WriteDataMastermode(baseAddr, &commandConfig, dataWord);
@endcode
*
* @param instance Module instance number
* @param baseAddr Module base address
* @param command Pointer to command structure
* @param data The data word to be sent
*/
void dspi_hal_write_data_master_mode(uint32_t instance,
dspi_command_config_t * command,
uint16_t data);
void DSPI_HAL_WriteDataMastermode(uint32_t baseAddr,
dspi_command_config_t * command,
uint16_t data);
/*!
* @brief Writes data into the data buffer, master mode and waits till complete to return.
*
* In master mode, the 16-bit data is appended to the 16-bit command info. The command portion
* provides characteristics of the data such as: optional continuous chip select
* operation between transfers, the desired Clock and Transfer Attributes register to use for the
* associated SPI frame, the desired PCS signal to use for the data transfer, whether the current
* transfer is the last in the queue, and whether to clear the transfer count (normally needed when
* sending the first frame of a data packet). This is an example:
@code
dspi_command_config_t commandConfig;
commandConfig.isChipSelectContinuous = true;
commandConfig.whichCtar = kDspiCtar0;
commandConfig.whichPcs = kDspiPcs1;
commandConfig.clearTransferCount = false;
commandConfig.isEndOfQueue = false;
DSPI_HAL_WriteDataMastermode(baseAddr, &commandConfig, dataWord);
@endcode
*
* Note that this function does not return until after the transmit is complete. Also note that
* the DSPI must be enabled and running in order to transmit data (MCR[MDIS] & [HALT] = 0).
* Since the SPI is a synchronous protocol, receive data is available when transmit completes.
*
* @param baseAddr Module base address
* @param command Pointer to command structure
* @param data The data word to be sent
*/
void DSPI_HAL_WriteDataMastermodeBlocking(uint32_t baseAddr,
dspi_command_config_t * command,
uint16_t data);
/*!
* @brief Gets the transfer count.
*
* This function returns the current value of the DSPI Transfer Count Register.
*
* @param instance Module instance number
* @param baseAddr Module base address
* @return The current transfer count
*/
static inline uint32_t dspi_hal_get_transfer_count(uint32_t instance)
static inline uint32_t DSPI_HAL_GetTransferCount(uint32_t baseAddr)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
return BR_SPI_TCR_SPI_TCNT(instance);
return BR_SPI_TCR_SPI_TCNT(baseAddr);
}
/*!
@ -884,13 +848,12 @@ static inline uint32_t dspi_hal_get_transfer_count(uint32_t instance)
* This function allows the caller to pre-set the DSI Transfer Count Register to a desired value up
* to 65535; Incrementing past this resets the counter back to 0.
*
* @param instance Module instance number
* @param baseAddr Module base address
* @param presetValue The desired pre-set value for the transfer counter
*/
static inline void dspi_hal_preset_transfer_count(uint32_t instance, uint16_t presetValue)
static inline void DSPI_HAL_PresetTransferCount(uint32_t baseAddr, uint16_t presetValue)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
BW_SPI_TCR_SPI_TCNT(instance, presetValue);
BW_SPI_TCR_SPI_TCNT(baseAddr, presetValue);
}
/*@}*/
@ -901,26 +864,25 @@ static inline void dspi_hal_preset_transfer_count(uint32_t instance, uint16_t pr
*/
/*!
* @brief Read FIFO registers for debug purposes.
* @brief Reads FIFO registers for debug purposes.
*
* @param instance Module instance number
* @param baseAddr Module base address
* @param whichFifo Selects Tx or Rx FIFO, of type dspi_fifo_t.
* @param whichFifoEntry Selects which FIFO entry to read: 0, 1, 2, or 3.
* @retrun The desired FIFO register contents
* @return The desired FIFO register contents
*/
uint32_t dspi_hal_get_fifo_data(uint32_t instance, dspi_fifo_t whichFifo, uint32_t whichFifoEntry);
uint32_t DSPI_HAL_GetFifoData(uint32_t baseAddr, dspi_fifo_t whichFifo, uint32_t whichFifoEntry);
/*!
* @brief Configures the DSPI to halt during debug mode.
*
* @param instance Module instance number
* @param baseAddr Module base address
* @param enable Enables (true) debug mode to halt transfers, else disable to not halt transfer
* in debug mode.
*/
static inline void dspi_hal_configure_halt_in_debug_mode(uint32_t instance, bool enable)
static inline void DSPI_HAL_SetHaltInDebugmodeCmd(uint32_t baseAddr, bool enable)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
BW_SPI_MCR_FRZ(instance, (enable == true));
BW_SPI_MCR_FRZ(baseAddr, (enable == true));
}
/* @}*/

221
libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/edma/fsl_edma_features.h
View File

@ -1,36 +1,66 @@
/*
* Copyright (c) 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#if !defined(__FSL_DMA_FEATURES_H__)
#define __FSL_DMA_FEATURES_H__
** ###################################################################
** Version: rev. 1.0, 2014-05-14
** Build: b140515
**
** Abstract:
** Chip specific module features.
**
** Copyright: 2014 Freescale Semiconductor, Inc.
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** Revisions:
** - rev. 1.0 (2014-05-14)
** Customer release.
**
** ###################################################################
*/
#if defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \
#if !defined(__FSL_EDMA_FEATURES_H__)
#define __FSL_EDMA_FEATURES_H__
#if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \
defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || \
defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || \
defined(CPU_MKV30F128VLF10) || defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10) || \
defined(CPU_MKV31F128VLH10) || defined(CPU_MKV31F128VLL10)
/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */
#define FSL_FEATURE_EDMA_MODULE_CHANNEL (4)
/* @brief Total number of DMA channels on all modules. */
#define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (HW_DMA_INSTANCE_COUNT * 4)
/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */
#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1)
/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */
#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (4)
#elif defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \
defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \
defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \
defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \
@ -38,89 +68,68 @@
defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \
defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || \
defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5)
/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.)*/
#define FSL_FEATURE_DMA_MODULE_CHANNEL (4)
/* @brief Total number of DMA channels on all modules.*/
#define FSL_FEATURE_DMA_DMAMUX_CHANNELS (HW_DMA_INSTANCE_COUNT * 4)
/* @brief Enhanced Direct Memory Access Controller (registers CR, ES, ERQ, EEI, CEEI, SEEI, CERQ, SERQ, CDNE, SSRT, CERR, CINT, INT, ERR, HRS, DCHPRIn, TCDn if non-zero, otherwise SARn, DARn, DSR_BCRn, DCRn).*/
#define FSL_FEATURE_DMA_IS_EDMA (1)
/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.)*/
#define FSL_FEATURE_DMA_CHANNEL_GROUP_COUNT (1)
/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.)*/
#define FSL_FEATURE_DMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (0)
/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */
#define FSL_FEATURE_EDMA_MODULE_CHANNEL (4)
/* @brief Total number of DMA channels on all modules. */
#define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (HW_DMA_INSTANCE_COUNT * 4)
/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */
#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1)
/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */
#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (0)
#elif defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || \
defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12) || defined(CPU_MKV31F256VLH12) || \
defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31FN512VLH12) || defined(CPU_MKV31F512VLL12)
/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.)*/
#define FSL_FEATURE_DMA_MODULE_CHANNEL (16)
/* @brief Total number of DMA channels on all modules.*/
#define FSL_FEATURE_DMA_DMAMUX_CHANNELS (HW_DMA_INSTANCE_COUNT * 16)
/* @brief Enhanced Direct Memory Access Controller (registers CR, ES, ERQ, EEI, CEEI, SEEI, CERQ, SERQ, CDNE, SSRT, CERR, CINT, INT, ERR, HRS, DCHPRIn, TCDn if non-zero, otherwise SARn, DARn, DSR_BCRn, DCRn).*/
#define FSL_FEATURE_DMA_IS_EDMA (1)
/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.)*/
#define FSL_FEATURE_DMA_CHANNEL_GROUP_COUNT (1)
/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.)*/
#define FSL_FEATURE_DMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (4)
#elif defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12) || \
defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VLQ12) || \
defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK64FX512VMD12)
/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.)*/
#define FSL_FEATURE_DMA_MODULE_CHANNEL (16)
/* @brief Total number of DMA channels on all modules.*/
#define FSL_FEATURE_DMA_DMAMUX_CHANNELS (HW_DMA_INSTANCE_COUNT * 16)
/* @brief Enhanced Direct Memory Access Controller (registers CR, ES, ERQ, EEI, CEEI, SEEI, CERQ, SERQ, CDNE, SSRT, CERR, CINT, INT, ERR, HRS, DCHPRIn, TCDn if non-zero, otherwise SARn, DARn, DSR_BCRn, DCRn).*/
#define FSL_FEATURE_DMA_IS_EDMA (1)
/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.)*/
#define FSL_FEATURE_DMA_CHANNEL_GROUP_COUNT (1)
/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.)*/
#define FSL_FEATURE_DMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (0)
#elif defined(CPU_MK65FN2M0VMF18) || defined(CPU_MK65FX1M0VMF18) || defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18)
/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.)*/
#define FSL_FEATURE_DMA_MODULE_CHANNEL (32)
/* @brief Total number of DMA channels on all modules.*/
#define FSL_FEATURE_DMA_DMAMUX_CHANNELS (HW_DMA_INSTANCE_COUNT * 32)
/* @brief Enhanced Direct Memory Access Controller (registers CR, ES, ERQ, EEI, CEEI, SEEI, CERQ, SERQ, CDNE, SSRT, CERR, CINT, INT, ERR, HRS, DCHPRIn, TCDn if non-zero, otherwise SARn, DARn, DSR_BCRn, DCRn).*/
#define FSL_FEATURE_DMA_IS_EDMA (1)
/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.)*/
#define FSL_FEATURE_DMA_CHANNEL_GROUP_COUNT (2)
/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.)*/
#define FSL_FEATURE_DMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (32)
defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31F512VLH12) || defined(CPU_MKV31F512VLL12) || defined(CPU_MKV40F128VLH15) || \
defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLH15) || defined(CPU_MKV40F256VLL15) || defined(CPU_MKV40F64VLH15) || \
defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || defined(CPU_MKV43F64VLH15) || defined(CPU_MKV44F128VLH15) || \
defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15) || defined(CPU_MKV45F128VLH15) || defined(CPU_MKV45F128VLL15) || \
defined(CPU_MKV45F256VLH15) || defined(CPU_MKV45F256VLL15) || defined(CPU_MKV46F128VLH15) || defined(CPU_MKV46F128VLL15) || \
defined(CPU_MKV46F256VLH15) || defined(CPU_MKV46F256VLL15)
/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */
#define FSL_FEATURE_EDMA_MODULE_CHANNEL (16)
/* @brief Total number of DMA channels on all modules. */
#define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (HW_DMA_INSTANCE_COUNT * 16)
/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */
#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1)
/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */
#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (16)
#elif defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK24FN256VDC12) || \
defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || \
defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || \
defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12)
/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */
#define FSL_FEATURE_EDMA_MODULE_CHANNEL (16)
/* @brief Total number of DMA channels on all modules. */
#define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (HW_DMA_INSTANCE_COUNT * 16)
/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */
#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1)
/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */
#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (0)
#elif defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || \
defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18)
/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */
#define FSL_FEATURE_EDMA_MODULE_CHANNEL (32)
/* @brief Total number of DMA channels on all modules. */
#define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (HW_DMA_INSTANCE_COUNT * 32)
/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */
#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (2)
/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */
#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (32)
#elif defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \
defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15)
/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.)*/
#define FSL_FEATURE_DMA_MODULE_CHANNEL (32)
/* @brief Total number of DMA channels on all modules.*/
#define FSL_FEATURE_DMA_DMAMUX_CHANNELS (HW_DMA_INSTANCE_COUNT * 32)
/* @brief Enhanced Direct Memory Access Controller (registers CR, ES, ERQ, EEI, CEEI, SEEI, CERQ, SERQ, CDNE, SSRT, CERR, CINT, INT, ERR, HRS, DCHPRIn, TCDn if non-zero, otherwise SARn, DARn, DSR_BCRn, DCRn).*/
#define FSL_FEATURE_DMA_IS_EDMA (1)
/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.)*/
#define FSL_FEATURE_DMA_CHANNEL_GROUP_COUNT (2)
/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.)*/
#define FSL_FEATURE_DMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (0)
#elif defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || \
defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || \
defined(CPU_MKL05Z32VFM4) || defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4) || defined(CPU_MKL25Z32VFM4) || \
defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || \
defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || \
defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4) || defined(CPU_MKL46Z128VLH4) || \
defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || \
defined(CPU_MKL46Z256VMC4)
/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.)*/
#define FSL_FEATURE_DMA_MODULE_CHANNEL (4)
/* @brief Total number of DMA channels on all modules.*/
#define FSL_FEATURE_DMA_DMAMUX_CHANNELS (HW_DMA_INSTANCE_COUNT * 4)
/* @brief Enhanced Direct Memory Access Controller (registers CR, ES, ERQ, EEI, CEEI, SEEI, CERQ, SERQ, CDNE, SSRT, CERR, CINT, INT, ERR, HRS, DCHPRIn, TCDn if non-zero, otherwise SARn, DARn, DSR_BCRn, DCRn).*/
#define FSL_FEATURE_DMA_IS_EDMA (0)
/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.)*/
#define FSL_FEATURE_DMA_CHANNEL_GROUP_COUNT (0)
/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.)*/
#define FSL_FEATURE_DMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (4)
/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */
#define FSL_FEATURE_EDMA_MODULE_CHANNEL (32)
/* @brief Total number of DMA channels on all modules. */
#define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (HW_DMA_INSTANCE_COUNT * 32)
/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */
#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (2)
/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */
#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (0)
#else
#error "No valid CPU defined!"
#endif
#endif /* __FSL_DMA_FEATURES_H__*/
#endif /* __FSL_EDMA_FEATURES_H__ */
/*******************************************************************************
* EOF
******************************************************************************/

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