From a72472f70a4ef7eedbf6a83582a8f123a9a9961c Mon Sep 17 00:00:00 2001 From: Volodymyr Medvid Date: Mon, 8 Jul 2019 13:01:09 +0300 Subject: [PATCH] PSOC6: update to latest psoc6pdl --- .../TARGET_PSOC6/psoc6pdl/LICENSE | 165 + .../TARGET_PSOC6/psoc6pdl/README.md | 40 + .../devices/include/cy8c6016bzi_f04.h | 4 +- .../devices/include/cy8c6036bzi_f04.h | 4 +- .../devices/include/cy8c6116bzi_f54.h | 4 +- .../devices/include/cy8c6117bzi_f34.h | 4 +- .../devices/include/cy8c6117fdi_f02.h | 4 +- .../psoc6pdl/devices/include/cy8c6117wi_f34.h | 6 +- .../devices/include/cy8c6136bzi_f14.h | 4 +- .../devices/include/cy8c6136bzi_f34.h | 4 +- .../devices/include/cy8c6136fdi_f42.h | 4 +- .../devices/include/cy8c6136fti_f42.h | 4 +- .../devices/include/cy8c6137bzi_f14.h | 4 +- .../devices/include/cy8c6137bzi_f34.h | 4 +- .../devices/include/cy8c6137bzi_f54.h | 4 +- .../devices/include/cy8c6137fdi_f02.h | 4 +- .../psoc6pdl/devices/include/cy8c6137wi_f54.h | 6 +- .../devices/include/cy8c6245azi_s3d02.h | 1180 +++++++ .../devices/include/cy8c6245azi_s3d12.h | 1180 +++++++ .../devices/include/cy8c6245azi_s3d42.h | 1190 +++++++ .../devices/include/cy8c6245azi_s3d62.h | 1180 +++++++ .../devices/include/cy8c6245azi_s3d72.h | 1190 +++++++ .../devices/include/cy8c6245fni_s3d11.h | 1180 +++++++ .../devices/include/cy8c6245fni_s3d41.h | 1190 +++++++ .../devices/include/cy8c6245fni_s3d71.h | 1190 +++++++ .../devices/include/cy8c6245lqi_s3d02.h | 1180 +++++++ .../devices/include/cy8c6245lqi_s3d12.h | 1180 +++++++ .../devices/include/cy8c6245lqi_s3d42.h | 1190 +++++++ .../devices/include/cy8c6245lqi_s3d62.h | 1180 +++++++ .../devices/include/cy8c6245lqi_s3d72.h | 1190 +++++++ .../devices/include/cy8c6246bzi_d04.h | 4 +- .../devices/include/cy8c6247bfi_d54.h | 4 +- .../devices/include/cy8c6247bzi_aud54.h | 4 +- .../devices/include/cy8c6247bzi_d34.h | 4 +- .../devices/include/cy8c6247bzi_d44.h | 4 +- .../devices/include/cy8c6247bzi_d54.h | 4 +- .../devices/include/cy8c6247fdi_d02.h | 4 +- .../devices/include/cy8c6247fdi_d32.h | 4 +- .../devices/include/cy8c6247fdi_d52.h | 4 +- .../devices/include/cy8c6247fti_d52.h | 4 +- .../psoc6pdl/devices/include/cy8c6247wi_d54.h | 6 +- .../devices/include/cy8c6248azi_d14.h | 1316 +++++++ .../devices/include/cy8c6248azi_d44.h | 1326 +++++++ .../devices/include/cy8c6248azi_s2d14.h | 1316 +++++++ .../devices/include/cy8c6248azi_s2d44.h | 1326 +++++++ .../devices/include/cy8c6248bzi_d44.h | 1326 +++++++ .../devices/include/cy8c6248bzi_s2d44.h | 1326 +++++++ .../devices/include/cy8c6248fni_d43.h | 1326 +++++++ .../devices/include/cy8c6248fni_s2d43.h | 1326 +++++++ .../devices/include/cy8c624aazi_d14.h | 1316 +++++++ .../devices/include/cy8c624aazi_d44.h | 4 +- .../devices/include/cy8c624aazi_s2d14.h | 1316 +++++++ .../devices/include/cy8c624aazi_s2d44.h | 1326 +++++++ .../devices/include/cy8c624abzi_d04.h | 1316 +++++++ .../devices/include/cy8c624abzi_d14.h | 1316 +++++++ .../devices/include/cy8c624abzi_d44.h | 4 +- .../devices/include/cy8c624abzi_s2d04.h | 1316 +++++++ .../devices/include/cy8c624abzi_s2d14.h | 1316 +++++++ .../devices/include/cy8c624abzi_s2d44.h | 1326 +++++++ .../devices/include/cy8c624abzi_s2d44a0.h | 1326 +++++++ .../devices/include/cy8c624afni_d43.h | 4 +- .../devices/include/cy8c624afni_s2d43.h | 1326 +++++++ .../devices/include/cy8c624alqi_d42.h | 1326 +++++++ .../devices/include/cy8c6316bzi_blf03.h | 4 +- .../devices/include/cy8c6316bzi_blf04.h | 4 +- .../devices/include/cy8c6316bzi_blf53.h | 4 +- .../devices/include/cy8c6316bzi_blf54.h | 4 +- .../devices/include/cy8c6336bzi_bld13.h | 4 +- .../devices/include/cy8c6336bzi_bld14.h | 4 +- .../devices/include/cy8c6336bzi_blf03.h | 4 +- .../devices/include/cy8c6336bzi_blf04.h | 4 +- .../devices/include/cy8c6336bzi_bud13.h | 4 +- .../devices/include/cy8c6336lqi_blf02.h | 953 +++++ .../devices/include/cy8c6336lqi_blf42.h | 963 +++++ .../devices/include/cy8c6337bzi_blf13.h | 4 +- .../devices/include/cy8c6347bzi_bld33.h | 4 +- .../devices/include/cy8c6347bzi_bld34.h | 4 +- .../devices/include/cy8c6347bzi_bld43.h | 4 +- .../devices/include/cy8c6347bzi_bld44.h | 4 +- .../devices/include/cy8c6347bzi_bld53.h | 4 +- .../devices/include/cy8c6347bzi_bld54.h | 4 +- .../devices/include/cy8c6347bzi_bud33.h | 4 +- .../devices/include/cy8c6347bzi_bud43.h | 4 +- .../devices/include/cy8c6347bzi_bud53.h | 4 +- .../devices/include/cy8c6347fmi_bld13.h | 4 +- .../devices/include/cy8c6347fmi_bld33.h | 4 +- .../devices/include/cy8c6347fmi_bld43.h | 4 +- .../devices/include/cy8c6347fmi_bld53.h | 4 +- .../devices/include/cy8c6347fmi_bud13.h | 4 +- .../devices/include/cy8c6347fmi_bud33.h | 4 +- .../devices/include/cy8c6347fmi_bud43.h | 4 +- .../devices/include/cy8c6347fmi_bud53.h | 4 +- .../devices/include/cy8c6347lqi_bld52.h | 1253 +++++++ .../devices/include/cy8c637bzi_bld74.h | 4 +- .../devices/include/cy8c637bzi_md76.h | 4 +- .../devices/include/cy8c637fmi_bld73.h | 4 +- .../devices/include/cy8c68237bz_ble.h | 2 +- .../devices/include/cy8c68237fm_ble.h | 2 +- .../devices/include/cy_device_common.h | 8 +- .../devices/include/cy_device_headers.h | 80 +- .../devices/include/cyb06447bzi_bld53.h | 1253 +++++++ .../devices/include/cyb06447bzi_bld54.h | 1266 +++++++ .../devices/include/cyb06447bzi_d54.h | 1252 +++++++ .../devices/include/cyb0644abzi_d44.h | 1326 +++++++ .../devices/include/cyble_416045_02.h | 18 +- .../include/gpio_psoc6_01_104_m_csp_ble.h | 2 +- .../include/gpio_psoc6_01_104_m_csp_ble_usb.h | 2 +- .../include/gpio_psoc6_01_116_bga_ble.h | 2 +- .../include/gpio_psoc6_01_116_bga_usb.h | 2 +- .../devices/include/gpio_psoc6_01_124_bga.h | 2 +- .../include/gpio_psoc6_01_124_bga_sip.h | 2 +- .../devices/include/gpio_psoc6_01_43_smt.h | 2 +- .../include/gpio_psoc6_01_68_qfn_ble.h | 1150 ++++++ .../devices/include/gpio_psoc6_01_80_wlcsp.h | 2 +- .../devices/include/gpio_psoc6_02_100_wlcsp.h | 2 +- .../devices/include/gpio_psoc6_02_124_bga.h | 2 +- .../devices/include/gpio_psoc6_02_128_tqfp.h | 2 +- .../devices/include/gpio_psoc6_02_68_qfn.h | 1302 +++++++ .../devices/include/gpio_psoc6_03_100_tqfp.h | 1437 ++++++++ .../devices/include/gpio_psoc6_03_49_wlcsp.h | 889 +++++ .../devices/include/gpio_psoc6_03_68_qfn.h | 1227 +++++++ .../psoc6pdl/devices/include/ip/cyip_backup.h | 2 +- .../psoc6pdl/devices/include/ip/cyip_ble.h | 2 +- .../psoc6pdl/devices/include/ip/cyip_canfd.h | 953 +++++ .../psoc6pdl/devices/include/ip/cyip_cpuss.h | 21 +- .../devices/include/ip/cyip_cpuss_v2.h | 2 +- .../psoc6pdl/devices/include/ip/cyip_crypto.h | 2 +- .../devices/include/ip/cyip_crypto_v2.h | 2 +- .../psoc6pdl/devices/include/ip/cyip_csd.h | 2 +- .../psoc6pdl/devices/include/ip/cyip_ctbm.h | 2 +- .../psoc6pdl/devices/include/ip/cyip_ctdac.h | 2 +- .../devices/include/ip/cyip_dmac_v2.h | 2 +- .../psoc6pdl/devices/include/ip/cyip_dw.h | 2 +- .../psoc6pdl/devices/include/ip/cyip_dw_v2.h | 2 +- .../psoc6pdl/devices/include/ip/cyip_efuse.h | 2 +- .../include/ip/cyip_efuse_data_psoc6_01.h | 2 +- .../include/ip/cyip_efuse_data_psoc6_02.h | 2 +- .../include/ip/cyip_efuse_data_psoc6_03.h | 250 ++ .../psoc6pdl/devices/include/ip/cyip_fault.h | 2 +- .../devices/include/ip/cyip_fault_v2.h | 2 +- .../psoc6pdl/devices/include/ip/cyip_flashc.h | 2 +- .../devices/include/ip/cyip_flashc_v2.h | 2 +- .../psoc6pdl/devices/include/ip/cyip_gpio.h | 2 +- .../devices/include/ip/cyip_gpio_v2.h | 2 +- .../psoc6pdl/devices/include/ip/cyip_hsiom.h | 2 +- .../devices/include/ip/cyip_hsiom_v2.h | 2 +- .../psoc6pdl/devices/include/ip/cyip_i2s.h | 2 +- .../psoc6pdl/devices/include/ip/cyip_ipc.h | 2 +- .../psoc6pdl/devices/include/ip/cyip_ipc_v2.h | 2 +- .../psoc6pdl/devices/include/ip/cyip_lcd.h | 2 +- .../psoc6pdl/devices/include/ip/cyip_lcd_v2.h | 103 + .../psoc6pdl/devices/include/ip/cyip_lpcomp.h | 2 +- .../psoc6pdl/devices/include/ip/cyip_pass.h | 2 +- .../psoc6pdl/devices/include/ip/cyip_pdm.h | 2 +- .../psoc6pdl/devices/include/ip/cyip_peri.h | 2 +- .../devices/include/ip/cyip_peri_ms_v2.h | 2 +- .../devices/include/ip/cyip_peri_v2.h | 2 +- .../devices/include/ip/cyip_profile.h | 2 +- .../psoc6pdl/devices/include/ip/cyip_prot.h | 2 +- .../devices/include/ip/cyip_prot_v2.h | 9 +- .../psoc6pdl/devices/include/ip/cyip_sar.h | 2 +- .../psoc6pdl/devices/include/ip/cyip_scb.h | 43 +- .../psoc6pdl/devices/include/ip/cyip_sdhc.h | 2 +- .../psoc6pdl/devices/include/ip/cyip_sflash.h | 65 +- .../devices/include/ip/cyip_smartio.h | 2 +- .../devices/include/ip/cyip_smartio_v2.h | 2 +- .../psoc6pdl/devices/include/ip/cyip_smif.h | 2 +- .../psoc6pdl/devices/include/ip/cyip_srss.h | 35 +- .../psoc6pdl/devices/include/ip/cyip_tcpwm.h | 2 +- .../psoc6pdl/devices/include/ip/cyip_udb.h | 2 +- .../psoc6pdl/devices/include/ip/cyip_usbfs.h | 2 +- .../devices/include/psoc6_01_config.h | 2 +- .../devices/include/psoc6_02_config.h | 102 +- .../devices/include/psoc6_03_config.h | 3116 +++++++++++++++++ .../psoc6pdl/drivers/include/cy_ble_clk.h | 11 +- .../psoc6pdl/drivers/include/cy_crypto.h | 224 +- .../drivers/include/cy_crypto_common.h | 139 +- .../psoc6pdl/drivers/include/cy_crypto_core.h | 2 +- .../drivers/include/cy_crypto_core_aes.h | 112 +- .../drivers/include/cy_crypto_core_aes_v1.h | 26 +- .../drivers/include/cy_crypto_core_aes_v2.h | 11 +- .../drivers/include/cy_crypto_core_cmac.h | 4 +- .../drivers/include/cy_crypto_core_cmac_v1.h | 2 +- .../drivers/include/cy_crypto_core_cmac_v2.h | 2 +- .../drivers/include/cy_crypto_core_crc.h | 16 +- .../drivers/include/cy_crypto_core_crc_v1.h | 2 +- .../drivers/include/cy_crypto_core_crc_v2.h | 2 +- .../drivers/include/cy_crypto_core_des.h | 6 +- .../drivers/include/cy_crypto_core_des_v1.h | 2 +- .../drivers/include/cy_crypto_core_des_v2.h | 2 +- .../drivers/include/cy_crypto_core_ecc.h | 68 +- .../include/cy_crypto_core_ecc_nist_p.h | 2 +- .../drivers/include/cy_crypto_core_hmac.h | 4 +- .../drivers/include/cy_crypto_core_hmac_v1.h | 2 +- .../drivers/include/cy_crypto_core_hmac_v2.h | 2 +- .../drivers/include/cy_crypto_core_hw.h | 98 +- .../drivers/include/cy_crypto_core_hw_v1.h | 2 +- .../drivers/include/cy_crypto_core_hw_v2.h | 38 +- .../drivers/include/cy_crypto_core_hw_vu.h | 225 +- .../drivers/include/cy_crypto_core_mem.h | 10 +- .../drivers/include/cy_crypto_core_mem_v1.h | 2 +- .../drivers/include/cy_crypto_core_mem_v2.h | 2 +- .../drivers/include/cy_crypto_core_prng.h | 6 +- .../drivers/include/cy_crypto_core_prng_v1.h | 2 +- .../drivers/include/cy_crypto_core_prng_v2.h | 2 +- .../drivers/include/cy_crypto_core_rsa.h | 2 +- .../drivers/include/cy_crypto_core_sha.h | 14 +- .../drivers/include/cy_crypto_core_sha_v1.h | 2 +- .../drivers/include/cy_crypto_core_sha_v2.h | 29 +- .../drivers/include/cy_crypto_core_trng.h | 4 +- .../include/cy_crypto_core_trng_config_v1.h | 2 +- .../include/cy_crypto_core_trng_config_v2.h | 2 +- .../drivers/include/cy_crypto_core_trng_v1.h | 2 +- .../drivers/include/cy_crypto_core_trng_v2.h | 2 +- .../drivers/include/cy_crypto_core_vu.h | 49 +- .../drivers/include/cy_crypto_server.h | 4 +- .../psoc6pdl/drivers/include/cy_csd.h | 42 +- .../psoc6pdl/drivers/include/cy_device.h | 69 +- .../psoc6pdl/drivers/include/cy_dma.h | 143 +- .../psoc6pdl/drivers/include/cy_dmac.h | 102 +- .../psoc6pdl/drivers/include/cy_i2s.h | 58 +- .../psoc6pdl/drivers/include/cy_ipc_drv.h | 30 +- .../psoc6pdl/drivers/include/cy_lpcomp.h | 2 +- .../psoc6pdl/drivers/include/cy_pdl.h | 1 + .../psoc6pdl/drivers/include/cy_prot.h | 6 +- .../psoc6pdl/drivers/include/cy_scb_common.h | 317 +- .../psoc6pdl/drivers/include/cy_scb_ezi2c.h | 93 +- .../psoc6pdl/drivers/include/cy_scb_i2c.h | 169 +- .../psoc6pdl/drivers/include/cy_scb_spi.h | 118 +- .../psoc6pdl/drivers/include/cy_scb_uart.h | 114 +- .../psoc6pdl/drivers/include/cy_sd_host.h | 60 +- .../psoc6pdl/drivers/include/cy_seglcd.h | 651 ++++ .../psoc6pdl/drivers/include/cy_smartio.h | 20 +- .../psoc6pdl/drivers/include/cy_smif.h | 174 +- .../drivers/include/cy_smif_memslot.h | 29 +- .../psoc6pdl/drivers/include/cy_sysclk.h | 528 ++- .../psoc6pdl/drivers/include/cy_sysint.h | 8 +- .../psoc6pdl/drivers/include/cy_syslib.h | 33 +- .../psoc6pdl/drivers/include/cy_syspm.h | 193 +- .../psoc6pdl/drivers/include/cy_tcpwm.h | 28 +- .../drivers/include/cy_tcpwm_counter.h | 28 +- .../psoc6pdl/drivers/include/cy_tcpwm_pwm.h | 30 +- .../drivers/include/cy_tcpwm_quaddec.h | 14 +- .../drivers/include/cy_usbfs_dev_drv.h | 774 ++-- .../drivers/include/cy_usbfs_dev_drv_pvt.h | 4 +- .../drivers/include/cy_usbfs_dev_drv_reg.h | 236 +- .../source/TOOLCHAIN_ARM/cy_syslib_mdk.S | 2 +- .../source/TOOLCHAIN_GCC_ARM/cy_syslib_gcc.S | 2 +- .../source/TOOLCHAIN_IAR/cy_syslib_iar.S | 2 +- .../psoc6pdl/drivers/source/cy_ble_clk.c | 11 +- .../psoc6pdl/drivers/source/cy_crypto.c | 107 +- .../drivers/source/cy_crypto_core_aes_v1.c | 77 +- .../drivers/source/cy_crypto_core_aes_v2.c | 106 +- .../drivers/source/cy_crypto_core_cmac_v1.c | 7 +- .../drivers/source/cy_crypto_core_cmac_v2.c | 21 +- .../drivers/source/cy_crypto_core_crc_v1.c | 2 +- .../drivers/source/cy_crypto_core_crc_v2.c | 2 +- .../drivers/source/cy_crypto_core_des_v1.c | 6 +- .../drivers/source/cy_crypto_core_des_v2.c | 2 +- .../source/cy_crypto_core_ecc_domain_params.c | 9 +- .../drivers/source/cy_crypto_core_ecc_ecdsa.c | 119 +- .../source/cy_crypto_core_ecc_key_gen.c | 224 +- .../source/cy_crypto_core_ecc_nist_p.c | 42 +- .../drivers/source/cy_crypto_core_hmac_v1.c | 4 +- .../drivers/source/cy_crypto_core_hmac_v2.c | 11 +- .../drivers/source/cy_crypto_core_hw.c | 271 +- .../drivers/source/cy_crypto_core_hw_v1.c | 22 +- .../drivers/source/cy_crypto_core_mem_v1.c | 136 +- .../drivers/source/cy_crypto_core_mem_v2.c | 126 +- .../drivers/source/cy_crypto_core_prng_v1.c | 2 +- .../drivers/source/cy_crypto_core_prng_v2.c | 2 +- .../drivers/source/cy_crypto_core_rsa.c | 42 +- .../drivers/source/cy_crypto_core_sha_v1.c | 169 +- .../drivers/source/cy_crypto_core_sha_v2.c | 192 +- .../drivers/source/cy_crypto_core_trng_v1.c | 2 +- .../drivers/source/cy_crypto_core_trng_v2.c | 2 +- .../drivers/source/cy_crypto_core_vu.c | 47 +- .../drivers/source/cy_crypto_server.c | 55 +- .../psoc6pdl/drivers/source/cy_csd.c | 9 +- .../psoc6pdl/drivers/source/cy_device.c | 148 +- .../psoc6pdl/drivers/source/cy_dma.c | 22 +- .../psoc6pdl/drivers/source/cy_dmac.c | 18 +- .../psoc6pdl/drivers/source/cy_flash.c | 8 +- .../psoc6pdl/drivers/source/cy_i2s.c | 6 +- .../psoc6pdl/drivers/source/cy_ipc_drv.c | 6 +- .../psoc6pdl/drivers/source/cy_ipc_pipe.c | 36 +- .../psoc6pdl/drivers/source/cy_ipc_sema.c | 10 +- .../psoc6pdl/drivers/source/cy_prot.c | 86 +- .../psoc6pdl/drivers/source/cy_scb_common.c | 2 +- .../psoc6pdl/drivers/source/cy_scb_ezi2c.c | 2 +- .../psoc6pdl/drivers/source/cy_scb_i2c.c | 22 +- .../psoc6pdl/drivers/source/cy_scb_spi.c | 2 +- .../psoc6pdl/drivers/source/cy_scb_uart.c | 24 +- .../psoc6pdl/drivers/source/cy_sd_host.c | 83 +- .../psoc6pdl/drivers/source/cy_seglcd.c | 969 +++++ .../psoc6pdl/drivers/source/cy_smartio.c | 40 +- .../psoc6pdl/drivers/source/cy_smif.c | 108 +- .../psoc6pdl/drivers/source/cy_smif_memslot.c | 1574 ++++++--- .../psoc6pdl/drivers/source/cy_sysclk.c | 360 +- .../psoc6pdl/drivers/source/cy_sysint.c | 16 +- .../psoc6pdl/drivers/source/cy_syslib.c | 2 +- .../psoc6pdl/drivers/source/cy_syspm.c | 191 +- .../drivers/source/cy_tcpwm_counter.c | 6 +- .../psoc6pdl/drivers/source/cy_tcpwm_pwm.c | 6 +- .../drivers/source/cy_tcpwm_quaddec.c | 6 +- .../psoc6pdl/drivers/source/cy_trigmux.c | 10 +- .../drivers/source/cy_usbfs_dev_drv.c | 599 ++-- .../drivers/source/cy_usbfs_dev_drv_io.c | 470 +-- .../drivers/source/cy_usbfs_dev_drv_io_dma.c | 50 +- .../TARGET_PSOC6/psoc6pdl/version.xml | 1 + 310 files changed, 67914 insertions(+), 4163 deletions(-) create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/LICENSE create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/README.md create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d02.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d12.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d42.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d62.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d72.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245fni_s3d11.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245fni_s3d41.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245fni_s3d71.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d02.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d12.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d42.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d62.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d72.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248azi_d14.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248azi_d44.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248azi_s2d14.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248azi_s2d44.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248bzi_d44.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248bzi_s2d44.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248fni_d43.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248fni_s2d43.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624aazi_d14.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624aazi_s2d14.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624aazi_s2d44.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_d04.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_d14.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_s2d04.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_s2d14.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_s2d44.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_s2d44a0.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624afni_s2d43.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624alqi_d42.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336lqi_blf02.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336lqi_blf42.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347lqi_bld52.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06447bzi_bld53.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06447bzi_bld54.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06447bzi_d54.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb0644abzi_d44.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_68_qfn_ble.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_02_68_qfn.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_03_100_tqfp.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_03_49_wlcsp.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_03_68_qfn.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_canfd.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_efuse_data_psoc6_03.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_lcd_v2.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/psoc6_03_config.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_seglcd.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_seglcd.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/version.xml diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/LICENSE b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/LICENSE new file mode 100644 index 0000000000..59cd3f8a32 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/LICENSE @@ -0,0 +1,165 @@ +Apache License +Version 2.0, January 2004 +http://www.apache.org/licenses/ + +TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + +1. 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Limitation of Liability. + +In no event and under no legal theory, whether in tort (including negligence), +contract, or otherwise, unless required by applicable law (such as deliberate +and grossly negligent acts) or agreed to in writing, shall any Contributor be +liable to You for damages, including any direct, indirect, special, incidental, +or consequential damages of any character arising as a result of this License or +out of the use or inability to use the Work (including but not limited to +damages for loss of goodwill, work stoppage, computer failure or malfunction, or +any and all other commercial damages or losses), even if such Contributor has +been advised of the possibility of such damages. + +9. Accepting Warranty or Additional Liability. + +While redistributing the Work or Derivative Works thereof, You may choose to +offer, and charge a fee for, acceptance of support, warranty, indemnity, or +other liability obligations and/or rights consistent with this License. However, +in accepting such obligations, You may act only on Your own behalf and on Your +sole responsibility, not on behalf of any other Contributor, and only if You +agree to indemnify, defend, and hold each Contributor harmless for any liability +incurred by, or claims asserted against, such Contributor by reason of your +accepting any such warranty or additional liability. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/README.md b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/README.md new file mode 100644 index 0000000000..05b54d123d --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/README.md @@ -0,0 +1,40 @@ +# PSoC 6 Peripheral Driver Library + +### Overview +The Cypress PDL simplifies software development for PSoC 6 family of devices. +The PDL integrates device header files, startup code, and +peripheral drivers into a single package. The drivers abstract the hardware functions into a set of +easy-to-use APIs. These are fully documented in the [PDL API Reference Manual](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/index.html). + +### Features +* Includes all the updates made to the peripheral drivers for ModusToolbox™ software +* Contains standard set of PSoC® 6 digital and analog peripheral drivers that enable rapid peripheral software development in third-party IDEs +* The ARM Cortex® Microcontroller Software Interface Standard (CMSIS) core access header files +* CMSIS compliant device header files, startup code (platform initialization) and device configuration header files + +The PDL reduces the need to understand register usage and bit structures, +thus easing software development for the extensive set of peripherals in the +PSoC 6 series. +See the [PDL API Reference Manual](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/index.html) for more detailed information. +See the [PDL Release Notes](./RELEASE.md) for release-specific information. + +### Peripheral Drivers +The PDL provides a high-level API to configure, initialize, and use a peripheral driver. +The drivers are designed for peripheral IP blocks. +See [PDL API Reference](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/modules.html) for the list of drivers. + +### Quick Start +See the [PDL API Reference Manual Getting Started section](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/page_getting_started.html) for quick start instructions. + +### More information +* [Peripheral Driver Library Release Notes](./RELEASE.md) +* [Peripheral Driver Library API Reference Manual](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/index.html) +* [ModusToolbox Software Environment, Quick Start Guide, Documentation, and Videos](https://www.cypress.com/products/modustoolbox-software-environment) +* [ModusToolbox Device Configurator Tool Guide](https://www.cypress.com/ModusToolboxDeviceConfig) +* [AN210781 Getting Started with PSoC 6 MCU with Bluetooth Low Energy (BLE) Connectivity](http://www.cypress.com/an210781) +* [PSoC 6 Technical Reference Manuals](https://www.cypress.com/search/all/PSoC%206%20Technical%20Reference%20Manual?f%5b0%5d=meta_type%3Atechnical_documents&f%5b1%5d=resource_meta_type%3A583) +* [PSoC 6 MCU Datasheets](https://www.cypress.com/search/all?f%5b0%5d=meta_type%3Atechnical_documents&f%5b1%5d=resource_meta_type%3A575&f%5b2%5d=field_related_products%3A114026) +* [Cypress Semiconductor](http://www.cypress.com) + +--- +© Cypress Semiconductor Corporation, 2019. \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6016bzi_f04.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6016bzi_f04.h index e3624c8657..710bd0e39f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6016bzi_f04.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6016bzi_f04.h @@ -5,7 +5,7 @@ * CY8C6016BZI-F04 device header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -286,7 +286,7 @@ typedef enum { #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u -#define CY_IP_MXS40PASS_SAR_INSTANCES 16u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6036bzi_f04.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6036bzi_f04.h index bb50dd08d0..621b731d89 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6036bzi_f04.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6036bzi_f04.h @@ -5,7 +5,7 @@ * CY8C6036BZI-F04 device header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -286,7 +286,7 @@ typedef enum { #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u -#define CY_IP_MXS40PASS_SAR_INSTANCES 16u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6116bzi_f54.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6116bzi_f54.h index 8e8b3e7d67..d367c26453 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6116bzi_f54.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6116bzi_f54.h @@ -5,7 +5,7 @@ * CY8C6116BZI-F54 device header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -289,7 +289,7 @@ typedef enum { #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u -#define CY_IP_MXS40PASS_SAR_INSTANCES 16u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6117bzi_f34.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6117bzi_f34.h index 2dc5a8b857..a64db4fdcc 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6117bzi_f34.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6117bzi_f34.h @@ -5,7 +5,7 @@ * CY8C6117BZI-F34 device header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -286,7 +286,7 @@ typedef enum { #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u -#define CY_IP_MXS40PASS_SAR_INSTANCES 16u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6117fdi_f02.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6117fdi_f02.h index 51f556b79c..828f24e93b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6117fdi_f02.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6117fdi_f02.h @@ -5,7 +5,7 @@ * CY8C6117FDI-F02 device header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -286,7 +286,7 @@ typedef enum { #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u -#define CY_IP_MXS40PASS_SAR_INSTANCES 16u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6117wi_f34.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6117wi_f34.h index 1bee615868..524c6df606 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6117wi_f34.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6117wi_f34.h @@ -5,7 +5,7 @@ * CY8C6117WI-F34 device header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -286,7 +286,7 @@ typedef enum { #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u -#define CY_IP_MXS40PASS_SAR_INSTANCES 16u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u @@ -317,7 +317,7 @@ typedef enum { #include "gpio_psoc6_01_124_bga.h" #define CY_DEVICE_PSOC6ABLE2 -#define CY_SILICON_ID 0xE2182100UL +#define CY_SILICON_ID 0xE2492100UL #define CY_HF_CLK_MAX_FREQ 50000000UL #define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6136bzi_f14.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6136bzi_f14.h index 2a81ecfa39..2ec820920c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6136bzi_f14.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6136bzi_f14.h @@ -5,7 +5,7 @@ * CY8C6136BZI-F14 device header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -286,7 +286,7 @@ typedef enum { #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u -#define CY_IP_MXS40PASS_SAR_INSTANCES 16u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6136bzi_f34.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6136bzi_f34.h index d0a1d974c7..bb2ff5c592 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6136bzi_f34.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6136bzi_f34.h @@ -5,7 +5,7 @@ * CY8C6136BZI-F34 device header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -286,7 +286,7 @@ typedef enum { #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u -#define CY_IP_MXS40PASS_SAR_INSTANCES 16u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6136fdi_f42.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6136fdi_f42.h index 6c92e8ff67..0b83771fad 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6136fdi_f42.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6136fdi_f42.h @@ -5,7 +5,7 @@ * CY8C6136FDI-F42 device header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -289,7 +289,7 @@ typedef enum { #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u -#define CY_IP_MXS40PASS_SAR_INSTANCES 16u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6136fti_f42.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6136fti_f42.h index 4fc4cd91ea..ab7ba44d34 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6136fti_f42.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6136fti_f42.h @@ -5,7 +5,7 @@ * CY8C6136FTI-F42 device header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -289,7 +289,7 @@ typedef enum { #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u -#define CY_IP_MXS40PASS_SAR_INSTANCES 16u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137bzi_f14.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137bzi_f14.h index b259aeec55..cb4e422a01 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137bzi_f14.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137bzi_f14.h @@ -5,7 +5,7 @@ * CY8C6137BZI-F14 device header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -286,7 +286,7 @@ typedef enum { #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u -#define CY_IP_MXS40PASS_SAR_INSTANCES 16u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137bzi_f34.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137bzi_f34.h index 4d0e0c7770..755664eb1e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137bzi_f34.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137bzi_f34.h @@ -5,7 +5,7 @@ * CY8C6137BZI-F34 device header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -286,7 +286,7 @@ typedef enum { #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u -#define CY_IP_MXS40PASS_SAR_INSTANCES 16u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137bzi_f54.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137bzi_f54.h index b6fe4f7c1c..cce62e3597 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137bzi_f54.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137bzi_f54.h @@ -5,7 +5,7 @@ * CY8C6137BZI-F54 device header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -289,7 +289,7 @@ typedef enum { #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u -#define CY_IP_MXS40PASS_SAR_INSTANCES 16u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137fdi_f02.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137fdi_f02.h index 44fd65501b..0da09fb4ce 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137fdi_f02.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137fdi_f02.h @@ -5,7 +5,7 @@ * CY8C6137FDI-F02 device header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -286,7 +286,7 @@ typedef enum { #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u -#define CY_IP_MXS40PASS_SAR_INSTANCES 16u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137wi_f54.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137wi_f54.h index e8b9f65261..0d1988e1ca 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137wi_f54.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137wi_f54.h @@ -5,7 +5,7 @@ * CY8C6137WI-F54 device header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -289,7 +289,7 @@ typedef enum { #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u -#define CY_IP_MXS40PASS_SAR_INSTANCES 16u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u @@ -320,7 +320,7 @@ typedef enum { #include "gpio_psoc6_01_124_bga.h" #define CY_DEVICE_PSOC6ABLE2 -#define CY_SILICON_ID 0xE2172100UL +#define CY_SILICON_ID 0xE2482100UL #define CY_HF_CLK_MAX_FREQ 150000000UL #define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d02.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d02.h new file mode 100644 index 0000000000..78f89e2ebc --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d02.h @@ -0,0 +1,1180 @@ +/***************************************************************************//** +* \file cy8c6245azi_s3d02.h +* +* \brief +* CY8C6245AZI-S3D02 device header +* +* \note +* Generator version: 1.5.0.1274 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6245AZI_S3D02_H_ +#define _CY8C6245AZI_S3D02_H_ + +/** +* \addtogroup group_device CY8C6245AZI-S3D02 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + /* ARM Cortex-M0+ Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6245AZI-S3D02 User Interrupt Numbers */ + NvicMux0_IRQn = 0, /*!< 0 [DeepSleep] CPU User Interrupt #0 */ + NvicMux1_IRQn = 1, /*!< 1 [DeepSleep] CPU User Interrupt #1 */ + NvicMux2_IRQn = 2, /*!< 2 [DeepSleep] CPU User Interrupt #2 */ + NvicMux3_IRQn = 3, /*!< 3 [DeepSleep] CPU User Interrupt #3 */ + NvicMux4_IRQn = 4, /*!< 4 [DeepSleep] CPU User Interrupt #4 */ + NvicMux5_IRQn = 5, /*!< 5 [DeepSleep] CPU User Interrupt #5 */ + NvicMux6_IRQn = 6, /*!< 6 [DeepSleep] CPU User Interrupt #6 */ + NvicMux7_IRQn = 7, /*!< 7 [DeepSleep] CPU User Interrupt #7 */ + /* CY8C6245AZI-S3D02 Internal SW Interrupt Numbers */ + Internal0_IRQn = 8, /*!< 8 [Active] Internal SW Interrupt #0 */ + Internal1_IRQn = 9, /*!< 9 [Active] Internal SW Interrupt #1 */ + Internal2_IRQn = 10, /*!< 10 [Active] Internal SW Interrupt #2 */ + Internal3_IRQn = 11, /*!< 11 [Active] Internal SW Interrupt #3 */ + Internal4_IRQn = 12, /*!< 12 [Active] Internal SW Interrupt #4 */ + Internal5_IRQn = 13, /*!< 13 [Active] Internal SW Interrupt #5 */ + Internal6_IRQn = 14, /*!< 14 [Active] Internal SW Interrupt #6 */ + Internal7_IRQn = 15, /*!< 15 [Active] Internal SW Interrupt #7 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#else + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6245AZI-S3D02 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#endif +} IRQn_Type; + + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* CY8C6245AZI-S3D02 interrupts that can be routed to the CM0+ NVIC */ +typedef enum { + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + disconnected_IRQn =1023 /*!< 1023 Disconnected */ +} cy_en_intr_t; + +#endif + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */ +#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ + +#else + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 1 /*!< CM0P present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + +#endif + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00040000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00080000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u + +#include "psoc6_03_config.h" +#include "gpio_psoc6_03_100_tqfp.h" + +#define CY_DEVICE_PSOC6A512K +#define CY_SILICON_ID 0xE70B1105UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/** \} CY8C6245AZI-S3D02 */ + +#endif /* _CY8C6245AZI_S3D02_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d12.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d12.h new file mode 100644 index 0000000000..e58e516863 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d12.h @@ -0,0 +1,1180 @@ +/***************************************************************************//** +* \file cy8c6245azi_s3d12.h +* +* \brief +* CY8C6245AZI-S3D12 device header +* +* \note +* Generator version: 1.5.0.1274 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6245AZI_S3D12_H_ +#define _CY8C6245AZI_S3D12_H_ + +/** +* \addtogroup group_device CY8C6245AZI-S3D12 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + /* ARM Cortex-M0+ Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6245AZI-S3D12 User Interrupt Numbers */ + NvicMux0_IRQn = 0, /*!< 0 [DeepSleep] CPU User Interrupt #0 */ + NvicMux1_IRQn = 1, /*!< 1 [DeepSleep] CPU User Interrupt #1 */ + NvicMux2_IRQn = 2, /*!< 2 [DeepSleep] CPU User Interrupt #2 */ + NvicMux3_IRQn = 3, /*!< 3 [DeepSleep] CPU User Interrupt #3 */ + NvicMux4_IRQn = 4, /*!< 4 [DeepSleep] CPU User Interrupt #4 */ + NvicMux5_IRQn = 5, /*!< 5 [DeepSleep] CPU User Interrupt #5 */ + NvicMux6_IRQn = 6, /*!< 6 [DeepSleep] CPU User Interrupt #6 */ + NvicMux7_IRQn = 7, /*!< 7 [DeepSleep] CPU User Interrupt #7 */ + /* CY8C6245AZI-S3D12 Internal SW Interrupt Numbers */ + Internal0_IRQn = 8, /*!< 8 [Active] Internal SW Interrupt #0 */ + Internal1_IRQn = 9, /*!< 9 [Active] Internal SW Interrupt #1 */ + Internal2_IRQn = 10, /*!< 10 [Active] Internal SW Interrupt #2 */ + Internal3_IRQn = 11, /*!< 11 [Active] Internal SW Interrupt #3 */ + Internal4_IRQn = 12, /*!< 12 [Active] Internal SW Interrupt #4 */ + Internal5_IRQn = 13, /*!< 13 [Active] Internal SW Interrupt #5 */ + Internal6_IRQn = 14, /*!< 14 [Active] Internal SW Interrupt #6 */ + Internal7_IRQn = 15, /*!< 15 [Active] Internal SW Interrupt #7 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#else + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6245AZI-S3D12 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#endif +} IRQn_Type; + + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* CY8C6245AZI-S3D12 interrupts that can be routed to the CM0+ NVIC */ +typedef enum { + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + disconnected_IRQn =1023 /*!< 1023 Disconnected */ +} cy_en_intr_t; + +#endif + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */ +#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ + +#else + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 1 /*!< CM0P present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + +#endif + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00040000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00080000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u + +#include "psoc6_03_config.h" +#include "gpio_psoc6_03_100_tqfp.h" + +#define CY_DEVICE_PSOC6A512K +#define CY_SILICON_ID 0xE7081105UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/** \} CY8C6245AZI-S3D12 */ + +#endif /* _CY8C6245AZI_S3D12_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d42.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d42.h new file mode 100644 index 0000000000..7b8a73ce3f --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d42.h @@ -0,0 +1,1190 @@ +/***************************************************************************//** +* \file cy8c6245azi_s3d42.h +* +* \brief +* CY8C6245AZI-S3D42 device header +* +* \note +* Generator version: 1.5.0.1274 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6245AZI_S3D42_H_ +#define _CY8C6245AZI_S3D42_H_ + +/** +* \addtogroup group_device CY8C6245AZI-S3D42 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + /* ARM Cortex-M0+ Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6245AZI-S3D42 User Interrupt Numbers */ + NvicMux0_IRQn = 0, /*!< 0 [DeepSleep] CPU User Interrupt #0 */ + NvicMux1_IRQn = 1, /*!< 1 [DeepSleep] CPU User Interrupt #1 */ + NvicMux2_IRQn = 2, /*!< 2 [DeepSleep] CPU User Interrupt #2 */ + NvicMux3_IRQn = 3, /*!< 3 [DeepSleep] CPU User Interrupt #3 */ + NvicMux4_IRQn = 4, /*!< 4 [DeepSleep] CPU User Interrupt #4 */ + NvicMux5_IRQn = 5, /*!< 5 [DeepSleep] CPU User Interrupt #5 */ + NvicMux6_IRQn = 6, /*!< 6 [DeepSleep] CPU User Interrupt #6 */ + NvicMux7_IRQn = 7, /*!< 7 [DeepSleep] CPU User Interrupt #7 */ + /* CY8C6245AZI-S3D42 Internal SW Interrupt Numbers */ + Internal0_IRQn = 8, /*!< 8 [Active] Internal SW Interrupt #0 */ + Internal1_IRQn = 9, /*!< 9 [Active] Internal SW Interrupt #1 */ + Internal2_IRQn = 10, /*!< 10 [Active] Internal SW Interrupt #2 */ + Internal3_IRQn = 11, /*!< 11 [Active] Internal SW Interrupt #3 */ + Internal4_IRQn = 12, /*!< 12 [Active] Internal SW Interrupt #4 */ + Internal5_IRQn = 13, /*!< 13 [Active] Internal SW Interrupt #5 */ + Internal6_IRQn = 14, /*!< 14 [Active] Internal SW Interrupt #6 */ + Internal7_IRQn = 15, /*!< 15 [Active] Internal SW Interrupt #7 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#else + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6245AZI-S3D42 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#endif +} IRQn_Type; + + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* CY8C6245AZI-S3D42 interrupts that can be routed to the CM0+ NVIC */ +typedef enum { + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + disconnected_IRQn =1023 /*!< 1023 Disconnected */ +} cy_en_intr_t; + +#endif + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */ +#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ + +#else + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 1 /*!< CM0P present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + +#endif + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00040000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00080000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 2u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u + +#include "psoc6_03_config.h" +#include "gpio_psoc6_03_100_tqfp.h" + +#define CY_DEVICE_PSOC6A512K +#define CY_SILICON_ID 0xE7051105UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40100000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40100000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/** \} CY8C6245AZI-S3D42 */ + +#endif /* _CY8C6245AZI_S3D42_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d62.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d62.h new file mode 100644 index 0000000000..09b2bde374 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d62.h @@ -0,0 +1,1180 @@ +/***************************************************************************//** +* \file cy8c6245azi_s3d62.h +* +* \brief +* CY8C6245AZI-S3D62 device header +* +* \note +* Generator version: 1.5.0.1274 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6245AZI_S3D62_H_ +#define _CY8C6245AZI_S3D62_H_ + +/** +* \addtogroup group_device CY8C6245AZI-S3D62 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + /* ARM Cortex-M0+ Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6245AZI-S3D62 User Interrupt Numbers */ + NvicMux0_IRQn = 0, /*!< 0 [DeepSleep] CPU User Interrupt #0 */ + NvicMux1_IRQn = 1, /*!< 1 [DeepSleep] CPU User Interrupt #1 */ + NvicMux2_IRQn = 2, /*!< 2 [DeepSleep] CPU User Interrupt #2 */ + NvicMux3_IRQn = 3, /*!< 3 [DeepSleep] CPU User Interrupt #3 */ + NvicMux4_IRQn = 4, /*!< 4 [DeepSleep] CPU User Interrupt #4 */ + NvicMux5_IRQn = 5, /*!< 5 [DeepSleep] CPU User Interrupt #5 */ + NvicMux6_IRQn = 6, /*!< 6 [DeepSleep] CPU User Interrupt #6 */ + NvicMux7_IRQn = 7, /*!< 7 [DeepSleep] CPU User Interrupt #7 */ + /* CY8C6245AZI-S3D62 Internal SW Interrupt Numbers */ + Internal0_IRQn = 8, /*!< 8 [Active] Internal SW Interrupt #0 */ + Internal1_IRQn = 9, /*!< 9 [Active] Internal SW Interrupt #1 */ + Internal2_IRQn = 10, /*!< 10 [Active] Internal SW Interrupt #2 */ + Internal3_IRQn = 11, /*!< 11 [Active] Internal SW Interrupt #3 */ + Internal4_IRQn = 12, /*!< 12 [Active] Internal SW Interrupt #4 */ + Internal5_IRQn = 13, /*!< 13 [Active] Internal SW Interrupt #5 */ + Internal6_IRQn = 14, /*!< 14 [Active] Internal SW Interrupt #6 */ + Internal7_IRQn = 15, /*!< 15 [Active] Internal SW Interrupt #7 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#else + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6245AZI-S3D62 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#endif +} IRQn_Type; + + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* CY8C6245AZI-S3D62 interrupts that can be routed to the CM0+ NVIC */ +typedef enum { + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + disconnected_IRQn =1023 /*!< 1023 Disconnected */ +} cy_en_intr_t; + +#endif + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */ +#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ + +#else + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 1 /*!< CM0P present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + +#endif + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00040000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00080000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u + +#include "psoc6_03_config.h" +#include "gpio_psoc6_03_100_tqfp.h" + +#define CY_DEVICE_PSOC6A512K +#define CY_SILICON_ID 0xE7031105UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/** \} CY8C6245AZI-S3D62 */ + +#endif /* _CY8C6245AZI_S3D62_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d72.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d72.h new file mode 100644 index 0000000000..48ede74a3e --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d72.h @@ -0,0 +1,1190 @@ +/***************************************************************************//** +* \file cy8c6245azi_s3d72.h +* +* \brief +* CY8C6245AZI-S3D72 device header +* +* \note +* Generator version: 1.5.0.1274 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6245AZI_S3D72_H_ +#define _CY8C6245AZI_S3D72_H_ + +/** +* \addtogroup group_device CY8C6245AZI-S3D72 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + /* ARM Cortex-M0+ Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6245AZI-S3D72 User Interrupt Numbers */ + NvicMux0_IRQn = 0, /*!< 0 [DeepSleep] CPU User Interrupt #0 */ + NvicMux1_IRQn = 1, /*!< 1 [DeepSleep] CPU User Interrupt #1 */ + NvicMux2_IRQn = 2, /*!< 2 [DeepSleep] CPU User Interrupt #2 */ + NvicMux3_IRQn = 3, /*!< 3 [DeepSleep] CPU User Interrupt #3 */ + NvicMux4_IRQn = 4, /*!< 4 [DeepSleep] CPU User Interrupt #4 */ + NvicMux5_IRQn = 5, /*!< 5 [DeepSleep] CPU User Interrupt #5 */ + NvicMux6_IRQn = 6, /*!< 6 [DeepSleep] CPU User Interrupt #6 */ + NvicMux7_IRQn = 7, /*!< 7 [DeepSleep] CPU User Interrupt #7 */ + /* CY8C6245AZI-S3D72 Internal SW Interrupt Numbers */ + Internal0_IRQn = 8, /*!< 8 [Active] Internal SW Interrupt #0 */ + Internal1_IRQn = 9, /*!< 9 [Active] Internal SW Interrupt #1 */ + Internal2_IRQn = 10, /*!< 10 [Active] Internal SW Interrupt #2 */ + Internal3_IRQn = 11, /*!< 11 [Active] Internal SW Interrupt #3 */ + Internal4_IRQn = 12, /*!< 12 [Active] Internal SW Interrupt #4 */ + Internal5_IRQn = 13, /*!< 13 [Active] Internal SW Interrupt #5 */ + Internal6_IRQn = 14, /*!< 14 [Active] Internal SW Interrupt #6 */ + Internal7_IRQn = 15, /*!< 15 [Active] Internal SW Interrupt #7 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#else + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6245AZI-S3D72 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#endif +} IRQn_Type; + + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* CY8C6245AZI-S3D72 interrupts that can be routed to the CM0+ NVIC */ +typedef enum { + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + disconnected_IRQn =1023 /*!< 1023 Disconnected */ +} cy_en_intr_t; + +#endif + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */ +#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ + +#else + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 1 /*!< CM0P present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + +#endif + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00040000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00080000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 2u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u + +#include "psoc6_03_config.h" +#include "gpio_psoc6_03_100_tqfp.h" + +#define CY_DEVICE_PSOC6A512K +#define CY_SILICON_ID 0xE7001105UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40100000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40100000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/** \} CY8C6245AZI-S3D72 */ + +#endif /* _CY8C6245AZI_S3D72_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245fni_s3d11.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245fni_s3d11.h new file mode 100644 index 0000000000..907fa05d5c --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245fni_s3d11.h @@ -0,0 +1,1180 @@ +/***************************************************************************//** +* \file cy8c6245fni_s3d11.h +* +* \brief +* CY8C6245FNI-S3D11 device header +* +* \note +* Generator version: 1.5.0.1274 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6245FNI_S3D11_H_ +#define _CY8C6245FNI_S3D11_H_ + +/** +* \addtogroup group_device CY8C6245FNI-S3D11 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + /* ARM Cortex-M0+ Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6245FNI-S3D11 User Interrupt Numbers */ + NvicMux0_IRQn = 0, /*!< 0 [DeepSleep] CPU User Interrupt #0 */ + NvicMux1_IRQn = 1, /*!< 1 [DeepSleep] CPU User Interrupt #1 */ + NvicMux2_IRQn = 2, /*!< 2 [DeepSleep] CPU User Interrupt #2 */ + NvicMux3_IRQn = 3, /*!< 3 [DeepSleep] CPU User Interrupt #3 */ + NvicMux4_IRQn = 4, /*!< 4 [DeepSleep] CPU User Interrupt #4 */ + NvicMux5_IRQn = 5, /*!< 5 [DeepSleep] CPU User Interrupt #5 */ + NvicMux6_IRQn = 6, /*!< 6 [DeepSleep] CPU User Interrupt #6 */ + NvicMux7_IRQn = 7, /*!< 7 [DeepSleep] CPU User Interrupt #7 */ + /* CY8C6245FNI-S3D11 Internal SW Interrupt Numbers */ + Internal0_IRQn = 8, /*!< 8 [Active] Internal SW Interrupt #0 */ + Internal1_IRQn = 9, /*!< 9 [Active] Internal SW Interrupt #1 */ + Internal2_IRQn = 10, /*!< 10 [Active] Internal SW Interrupt #2 */ + Internal3_IRQn = 11, /*!< 11 [Active] Internal SW Interrupt #3 */ + Internal4_IRQn = 12, /*!< 12 [Active] Internal SW Interrupt #4 */ + Internal5_IRQn = 13, /*!< 13 [Active] Internal SW Interrupt #5 */ + Internal6_IRQn = 14, /*!< 14 [Active] Internal SW Interrupt #6 */ + Internal7_IRQn = 15, /*!< 15 [Active] Internal SW Interrupt #7 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#else + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6245FNI-S3D11 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#endif +} IRQn_Type; + + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* CY8C6245FNI-S3D11 interrupts that can be routed to the CM0+ NVIC */ +typedef enum { + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + disconnected_IRQn =1023 /*!< 1023 Disconnected */ +} cy_en_intr_t; + +#endif + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */ +#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ + +#else + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 1 /*!< CM0P present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + +#endif + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00040000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00080000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u + +#include "psoc6_03_config.h" +#include "gpio_psoc6_03_49_wlcsp.h" + +#define CY_DEVICE_PSOC6A512K +#define CY_SILICON_ID 0xE70A1105UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/** \} CY8C6245FNI-S3D11 */ + +#endif /* _CY8C6245FNI_S3D11_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245fni_s3d41.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245fni_s3d41.h new file mode 100644 index 0000000000..2328ee0cdc --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245fni_s3d41.h @@ -0,0 +1,1190 @@ +/***************************************************************************//** +* \file cy8c6245fni_s3d41.h +* +* \brief +* CY8C6245FNI-S3D41 device header +* +* \note +* Generator version: 1.5.0.1274 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6245FNI_S3D41_H_ +#define _CY8C6245FNI_S3D41_H_ + +/** +* \addtogroup group_device CY8C6245FNI-S3D41 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + /* ARM Cortex-M0+ Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6245FNI-S3D41 User Interrupt Numbers */ + NvicMux0_IRQn = 0, /*!< 0 [DeepSleep] CPU User Interrupt #0 */ + NvicMux1_IRQn = 1, /*!< 1 [DeepSleep] CPU User Interrupt #1 */ + NvicMux2_IRQn = 2, /*!< 2 [DeepSleep] CPU User Interrupt #2 */ + NvicMux3_IRQn = 3, /*!< 3 [DeepSleep] CPU User Interrupt #3 */ + NvicMux4_IRQn = 4, /*!< 4 [DeepSleep] CPU User Interrupt #4 */ + NvicMux5_IRQn = 5, /*!< 5 [DeepSleep] CPU User Interrupt #5 */ + NvicMux6_IRQn = 6, /*!< 6 [DeepSleep] CPU User Interrupt #6 */ + NvicMux7_IRQn = 7, /*!< 7 [DeepSleep] CPU User Interrupt #7 */ + /* CY8C6245FNI-S3D41 Internal SW Interrupt Numbers */ + Internal0_IRQn = 8, /*!< 8 [Active] Internal SW Interrupt #0 */ + Internal1_IRQn = 9, /*!< 9 [Active] Internal SW Interrupt #1 */ + Internal2_IRQn = 10, /*!< 10 [Active] Internal SW Interrupt #2 */ + Internal3_IRQn = 11, /*!< 11 [Active] Internal SW Interrupt #3 */ + Internal4_IRQn = 12, /*!< 12 [Active] Internal SW Interrupt #4 */ + Internal5_IRQn = 13, /*!< 13 [Active] Internal SW Interrupt #5 */ + Internal6_IRQn = 14, /*!< 14 [Active] Internal SW Interrupt #6 */ + Internal7_IRQn = 15, /*!< 15 [Active] Internal SW Interrupt #7 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#else + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6245FNI-S3D41 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#endif +} IRQn_Type; + + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* CY8C6245FNI-S3D41 interrupts that can be routed to the CM0+ NVIC */ +typedef enum { + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + disconnected_IRQn =1023 /*!< 1023 Disconnected */ +} cy_en_intr_t; + +#endif + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */ +#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ + +#else + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 1 /*!< CM0P present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + +#endif + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00040000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00080000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 2u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u + +#include "psoc6_03_config.h" +#include "gpio_psoc6_03_49_wlcsp.h" + +#define CY_DEVICE_PSOC6A512K +#define CY_SILICON_ID 0xE7071105UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40100000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40100000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/** \} CY8C6245FNI-S3D41 */ + +#endif /* _CY8C6245FNI_S3D41_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245fni_s3d71.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245fni_s3d71.h new file mode 100644 index 0000000000..86917f278a --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245fni_s3d71.h @@ -0,0 +1,1190 @@ +/***************************************************************************//** +* \file cy8c6245fni_s3d71.h +* +* \brief +* CY8C6245FNI-S3D71 device header +* +* \note +* Generator version: 1.5.0.1274 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6245FNI_S3D71_H_ +#define _CY8C6245FNI_S3D71_H_ + +/** +* \addtogroup group_device CY8C6245FNI-S3D71 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + /* ARM Cortex-M0+ Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6245FNI-S3D71 User Interrupt Numbers */ + NvicMux0_IRQn = 0, /*!< 0 [DeepSleep] CPU User Interrupt #0 */ + NvicMux1_IRQn = 1, /*!< 1 [DeepSleep] CPU User Interrupt #1 */ + NvicMux2_IRQn = 2, /*!< 2 [DeepSleep] CPU User Interrupt #2 */ + NvicMux3_IRQn = 3, /*!< 3 [DeepSleep] CPU User Interrupt #3 */ + NvicMux4_IRQn = 4, /*!< 4 [DeepSleep] CPU User Interrupt #4 */ + NvicMux5_IRQn = 5, /*!< 5 [DeepSleep] CPU User Interrupt #5 */ + NvicMux6_IRQn = 6, /*!< 6 [DeepSleep] CPU User Interrupt #6 */ + NvicMux7_IRQn = 7, /*!< 7 [DeepSleep] CPU User Interrupt #7 */ + /* CY8C6245FNI-S3D71 Internal SW Interrupt Numbers */ + Internal0_IRQn = 8, /*!< 8 [Active] Internal SW Interrupt #0 */ + Internal1_IRQn = 9, /*!< 9 [Active] Internal SW Interrupt #1 */ + Internal2_IRQn = 10, /*!< 10 [Active] Internal SW Interrupt #2 */ + Internal3_IRQn = 11, /*!< 11 [Active] Internal SW Interrupt #3 */ + Internal4_IRQn = 12, /*!< 12 [Active] Internal SW Interrupt #4 */ + Internal5_IRQn = 13, /*!< 13 [Active] Internal SW Interrupt #5 */ + Internal6_IRQn = 14, /*!< 14 [Active] Internal SW Interrupt #6 */ + Internal7_IRQn = 15, /*!< 15 [Active] Internal SW Interrupt #7 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#else + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6245FNI-S3D71 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#endif +} IRQn_Type; + + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* CY8C6245FNI-S3D71 interrupts that can be routed to the CM0+ NVIC */ +typedef enum { + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + disconnected_IRQn =1023 /*!< 1023 Disconnected */ +} cy_en_intr_t; + +#endif + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */ +#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ + +#else + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 1 /*!< CM0P present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + +#endif + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00040000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00080000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 2u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u + +#include "psoc6_03_config.h" +#include "gpio_psoc6_03_49_wlcsp.h" + +#define CY_DEVICE_PSOC6A512K +#define CY_SILICON_ID 0xE7021105UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40100000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40100000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/** \} CY8C6245FNI-S3D71 */ + +#endif /* _CY8C6245FNI_S3D71_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d02.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d02.h new file mode 100644 index 0000000000..dec9f98271 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d02.h @@ -0,0 +1,1180 @@ +/***************************************************************************//** +* \file cy8c6245lqi_s3d02.h +* +* \brief +* CY8C6245LQI-S3D02 device header +* +* \note +* Generator version: 1.5.0.1274 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6245LQI_S3D02_H_ +#define _CY8C6245LQI_S3D02_H_ + +/** +* \addtogroup group_device CY8C6245LQI-S3D02 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + /* ARM Cortex-M0+ Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6245LQI-S3D02 User Interrupt Numbers */ + NvicMux0_IRQn = 0, /*!< 0 [DeepSleep] CPU User Interrupt #0 */ + NvicMux1_IRQn = 1, /*!< 1 [DeepSleep] CPU User Interrupt #1 */ + NvicMux2_IRQn = 2, /*!< 2 [DeepSleep] CPU User Interrupt #2 */ + NvicMux3_IRQn = 3, /*!< 3 [DeepSleep] CPU User Interrupt #3 */ + NvicMux4_IRQn = 4, /*!< 4 [DeepSleep] CPU User Interrupt #4 */ + NvicMux5_IRQn = 5, /*!< 5 [DeepSleep] CPU User Interrupt #5 */ + NvicMux6_IRQn = 6, /*!< 6 [DeepSleep] CPU User Interrupt #6 */ + NvicMux7_IRQn = 7, /*!< 7 [DeepSleep] CPU User Interrupt #7 */ + /* CY8C6245LQI-S3D02 Internal SW Interrupt Numbers */ + Internal0_IRQn = 8, /*!< 8 [Active] Internal SW Interrupt #0 */ + Internal1_IRQn = 9, /*!< 9 [Active] Internal SW Interrupt #1 */ + Internal2_IRQn = 10, /*!< 10 [Active] Internal SW Interrupt #2 */ + Internal3_IRQn = 11, /*!< 11 [Active] Internal SW Interrupt #3 */ + Internal4_IRQn = 12, /*!< 12 [Active] Internal SW Interrupt #4 */ + Internal5_IRQn = 13, /*!< 13 [Active] Internal SW Interrupt #5 */ + Internal6_IRQn = 14, /*!< 14 [Active] Internal SW Interrupt #6 */ + Internal7_IRQn = 15, /*!< 15 [Active] Internal SW Interrupt #7 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#else + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6245LQI-S3D02 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#endif +} IRQn_Type; + + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* CY8C6245LQI-S3D02 interrupts that can be routed to the CM0+ NVIC */ +typedef enum { + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + disconnected_IRQn =1023 /*!< 1023 Disconnected */ +} cy_en_intr_t; + +#endif + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */ +#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ + +#else + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 1 /*!< CM0P present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + +#endif + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00040000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00080000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u + +#include "psoc6_03_config.h" +#include "gpio_psoc6_03_68_qfn.h" + +#define CY_DEVICE_PSOC6A512K +#define CY_SILICON_ID 0xE70C1105UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/** \} CY8C6245LQI-S3D02 */ + +#endif /* _CY8C6245LQI_S3D02_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d12.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d12.h new file mode 100644 index 0000000000..2f02c44157 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d12.h @@ -0,0 +1,1180 @@ +/***************************************************************************//** +* \file cy8c6245lqi_s3d12.h +* +* \brief +* CY8C6245LQI-S3D12 device header +* +* \note +* Generator version: 1.5.0.1274 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6245LQI_S3D12_H_ +#define _CY8C6245LQI_S3D12_H_ + +/** +* \addtogroup group_device CY8C6245LQI-S3D12 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + /* ARM Cortex-M0+ Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6245LQI-S3D12 User Interrupt Numbers */ + NvicMux0_IRQn = 0, /*!< 0 [DeepSleep] CPU User Interrupt #0 */ + NvicMux1_IRQn = 1, /*!< 1 [DeepSleep] CPU User Interrupt #1 */ + NvicMux2_IRQn = 2, /*!< 2 [DeepSleep] CPU User Interrupt #2 */ + NvicMux3_IRQn = 3, /*!< 3 [DeepSleep] CPU User Interrupt #3 */ + NvicMux4_IRQn = 4, /*!< 4 [DeepSleep] CPU User Interrupt #4 */ + NvicMux5_IRQn = 5, /*!< 5 [DeepSleep] CPU User Interrupt #5 */ + NvicMux6_IRQn = 6, /*!< 6 [DeepSleep] CPU User Interrupt #6 */ + NvicMux7_IRQn = 7, /*!< 7 [DeepSleep] CPU User Interrupt #7 */ + /* CY8C6245LQI-S3D12 Internal SW Interrupt Numbers */ + Internal0_IRQn = 8, /*!< 8 [Active] Internal SW Interrupt #0 */ + Internal1_IRQn = 9, /*!< 9 [Active] Internal SW Interrupt #1 */ + Internal2_IRQn = 10, /*!< 10 [Active] Internal SW Interrupt #2 */ + Internal3_IRQn = 11, /*!< 11 [Active] Internal SW Interrupt #3 */ + Internal4_IRQn = 12, /*!< 12 [Active] Internal SW Interrupt #4 */ + Internal5_IRQn = 13, /*!< 13 [Active] Internal SW Interrupt #5 */ + Internal6_IRQn = 14, /*!< 14 [Active] Internal SW Interrupt #6 */ + Internal7_IRQn = 15, /*!< 15 [Active] Internal SW Interrupt #7 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#else + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6245LQI-S3D12 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#endif +} IRQn_Type; + + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* CY8C6245LQI-S3D12 interrupts that can be routed to the CM0+ NVIC */ +typedef enum { + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + disconnected_IRQn =1023 /*!< 1023 Disconnected */ +} cy_en_intr_t; + +#endif + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */ +#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ + +#else + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 1 /*!< CM0P present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + +#endif + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00040000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00080000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u + +#include "psoc6_03_config.h" +#include "gpio_psoc6_03_68_qfn.h" + +#define CY_DEVICE_PSOC6A512K +#define CY_SILICON_ID 0xE7091105UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/** \} CY8C6245LQI-S3D12 */ + +#endif /* _CY8C6245LQI_S3D12_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d42.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d42.h new file mode 100644 index 0000000000..2840fe5592 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d42.h @@ -0,0 +1,1190 @@ +/***************************************************************************//** +* \file cy8c6245lqi_s3d42.h +* +* \brief +* CY8C6245LQI-S3D42 device header +* +* \note +* Generator version: 1.5.0.1274 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6245LQI_S3D42_H_ +#define _CY8C6245LQI_S3D42_H_ + +/** +* \addtogroup group_device CY8C6245LQI-S3D42 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + /* ARM Cortex-M0+ Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6245LQI-S3D42 User Interrupt Numbers */ + NvicMux0_IRQn = 0, /*!< 0 [DeepSleep] CPU User Interrupt #0 */ + NvicMux1_IRQn = 1, /*!< 1 [DeepSleep] CPU User Interrupt #1 */ + NvicMux2_IRQn = 2, /*!< 2 [DeepSleep] CPU User Interrupt #2 */ + NvicMux3_IRQn = 3, /*!< 3 [DeepSleep] CPU User Interrupt #3 */ + NvicMux4_IRQn = 4, /*!< 4 [DeepSleep] CPU User Interrupt #4 */ + NvicMux5_IRQn = 5, /*!< 5 [DeepSleep] CPU User Interrupt #5 */ + NvicMux6_IRQn = 6, /*!< 6 [DeepSleep] CPU User Interrupt #6 */ + NvicMux7_IRQn = 7, /*!< 7 [DeepSleep] CPU User Interrupt #7 */ + /* CY8C6245LQI-S3D42 Internal SW Interrupt Numbers */ + Internal0_IRQn = 8, /*!< 8 [Active] Internal SW Interrupt #0 */ + Internal1_IRQn = 9, /*!< 9 [Active] Internal SW Interrupt #1 */ + Internal2_IRQn = 10, /*!< 10 [Active] Internal SW Interrupt #2 */ + Internal3_IRQn = 11, /*!< 11 [Active] Internal SW Interrupt #3 */ + Internal4_IRQn = 12, /*!< 12 [Active] Internal SW Interrupt #4 */ + Internal5_IRQn = 13, /*!< 13 [Active] Internal SW Interrupt #5 */ + Internal6_IRQn = 14, /*!< 14 [Active] Internal SW Interrupt #6 */ + Internal7_IRQn = 15, /*!< 15 [Active] Internal SW Interrupt #7 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#else + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6245LQI-S3D42 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#endif +} IRQn_Type; + + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* CY8C6245LQI-S3D42 interrupts that can be routed to the CM0+ NVIC */ +typedef enum { + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + disconnected_IRQn =1023 /*!< 1023 Disconnected */ +} cy_en_intr_t; + +#endif + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */ +#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ + +#else + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 1 /*!< CM0P present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + +#endif + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00040000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00080000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 2u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u + +#include "psoc6_03_config.h" +#include "gpio_psoc6_03_68_qfn.h" + +#define CY_DEVICE_PSOC6A512K +#define CY_SILICON_ID 0xE7061105UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40100000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40100000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/** \} CY8C6245LQI-S3D42 */ + +#endif /* _CY8C6245LQI_S3D42_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d62.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d62.h new file mode 100644 index 0000000000..1e7ac8a70e --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d62.h @@ -0,0 +1,1180 @@ +/***************************************************************************//** +* \file cy8c6245lqi_s3d62.h +* +* \brief +* CY8C6245LQI-S3D62 device header +* +* \note +* Generator version: 1.5.0.1274 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6245LQI_S3D62_H_ +#define _CY8C6245LQI_S3D62_H_ + +/** +* \addtogroup group_device CY8C6245LQI-S3D62 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + /* ARM Cortex-M0+ Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6245LQI-S3D62 User Interrupt Numbers */ + NvicMux0_IRQn = 0, /*!< 0 [DeepSleep] CPU User Interrupt #0 */ + NvicMux1_IRQn = 1, /*!< 1 [DeepSleep] CPU User Interrupt #1 */ + NvicMux2_IRQn = 2, /*!< 2 [DeepSleep] CPU User Interrupt #2 */ + NvicMux3_IRQn = 3, /*!< 3 [DeepSleep] CPU User Interrupt #3 */ + NvicMux4_IRQn = 4, /*!< 4 [DeepSleep] CPU User Interrupt #4 */ + NvicMux5_IRQn = 5, /*!< 5 [DeepSleep] CPU User Interrupt #5 */ + NvicMux6_IRQn = 6, /*!< 6 [DeepSleep] CPU User Interrupt #6 */ + NvicMux7_IRQn = 7, /*!< 7 [DeepSleep] CPU User Interrupt #7 */ + /* CY8C6245LQI-S3D62 Internal SW Interrupt Numbers */ + Internal0_IRQn = 8, /*!< 8 [Active] Internal SW Interrupt #0 */ + Internal1_IRQn = 9, /*!< 9 [Active] Internal SW Interrupt #1 */ + Internal2_IRQn = 10, /*!< 10 [Active] Internal SW Interrupt #2 */ + Internal3_IRQn = 11, /*!< 11 [Active] Internal SW Interrupt #3 */ + Internal4_IRQn = 12, /*!< 12 [Active] Internal SW Interrupt #4 */ + Internal5_IRQn = 13, /*!< 13 [Active] Internal SW Interrupt #5 */ + Internal6_IRQn = 14, /*!< 14 [Active] Internal SW Interrupt #6 */ + Internal7_IRQn = 15, /*!< 15 [Active] Internal SW Interrupt #7 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#else + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6245LQI-S3D62 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#endif +} IRQn_Type; + + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* CY8C6245LQI-S3D62 interrupts that can be routed to the CM0+ NVIC */ +typedef enum { + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + disconnected_IRQn =1023 /*!< 1023 Disconnected */ +} cy_en_intr_t; + +#endif + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */ +#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ + +#else + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 1 /*!< CM0P present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + +#endif + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00040000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00080000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u + +#include "psoc6_03_config.h" +#include "gpio_psoc6_03_68_qfn.h" + +#define CY_DEVICE_PSOC6A512K +#define CY_SILICON_ID 0xE7041105UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/** \} CY8C6245LQI-S3D62 */ + +#endif /* _CY8C6245LQI_S3D62_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d72.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d72.h new file mode 100644 index 0000000000..05f144710c --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d72.h @@ -0,0 +1,1190 @@ +/***************************************************************************//** +* \file cy8c6245lqi_s3d72.h +* +* \brief +* CY8C6245LQI-S3D72 device header +* +* \note +* Generator version: 1.5.0.1274 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6245LQI_S3D72_H_ +#define _CY8C6245LQI_S3D72_H_ + +/** +* \addtogroup group_device CY8C6245LQI-S3D72 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + /* ARM Cortex-M0+ Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6245LQI-S3D72 User Interrupt Numbers */ + NvicMux0_IRQn = 0, /*!< 0 [DeepSleep] CPU User Interrupt #0 */ + NvicMux1_IRQn = 1, /*!< 1 [DeepSleep] CPU User Interrupt #1 */ + NvicMux2_IRQn = 2, /*!< 2 [DeepSleep] CPU User Interrupt #2 */ + NvicMux3_IRQn = 3, /*!< 3 [DeepSleep] CPU User Interrupt #3 */ + NvicMux4_IRQn = 4, /*!< 4 [DeepSleep] CPU User Interrupt #4 */ + NvicMux5_IRQn = 5, /*!< 5 [DeepSleep] CPU User Interrupt #5 */ + NvicMux6_IRQn = 6, /*!< 6 [DeepSleep] CPU User Interrupt #6 */ + NvicMux7_IRQn = 7, /*!< 7 [DeepSleep] CPU User Interrupt #7 */ + /* CY8C6245LQI-S3D72 Internal SW Interrupt Numbers */ + Internal0_IRQn = 8, /*!< 8 [Active] Internal SW Interrupt #0 */ + Internal1_IRQn = 9, /*!< 9 [Active] Internal SW Interrupt #1 */ + Internal2_IRQn = 10, /*!< 10 [Active] Internal SW Interrupt #2 */ + Internal3_IRQn = 11, /*!< 11 [Active] Internal SW Interrupt #3 */ + Internal4_IRQn = 12, /*!< 12 [Active] Internal SW Interrupt #4 */ + Internal5_IRQn = 13, /*!< 13 [Active] Internal SW Interrupt #5 */ + Internal6_IRQn = 14, /*!< 14 [Active] Internal SW Interrupt #6 */ + Internal7_IRQn = 15, /*!< 15 [Active] Internal SW Interrupt #7 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#else + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6245LQI-S3D72 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#endif +} IRQn_Type; + + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* CY8C6245LQI-S3D72 interrupts that can be routed to the CM0+ NVIC */ +typedef enum { + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + disconnected_IRQn =1023 /*!< 1023 Disconnected */ +} cy_en_intr_t; + +#endif + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */ +#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ + +#else + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 1 /*!< CM0P present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + +#endif + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00040000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00080000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 2u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u + +#include "psoc6_03_config.h" +#include "gpio_psoc6_03_68_qfn.h" + +#define CY_DEVICE_PSOC6A512K +#define CY_SILICON_ID 0xE7011105UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40100000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40100000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/** \} CY8C6245LQI-S3D72 */ + +#endif /* _CY8C6245LQI_S3D72_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6246bzi_d04.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6246bzi_d04.h index 5adb12c062..1410514d01 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6246bzi_d04.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6246bzi_d04.h @@ -5,7 +5,7 @@ * CY8C6246BZI-D04 device header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -511,7 +511,7 @@ typedef enum { #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u -#define CY_IP_MXS40PASS_SAR_INSTANCES 16u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bfi_d54.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bfi_d54.h index 96a63bffb4..713a424510 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bfi_d54.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bfi_d54.h @@ -5,7 +5,7 @@ * CY8C6247BFI-D54 device header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -514,7 +514,7 @@ typedef enum { #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u -#define CY_IP_MXS40PASS_SAR_INSTANCES 16u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bzi_aud54.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bzi_aud54.h index db41cb76a8..265fd2fcd7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bzi_aud54.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bzi_aud54.h @@ -5,7 +5,7 @@ * CY8C6247BZI-AUD54 device header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -514,7 +514,7 @@ typedef enum { #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u -#define CY_IP_MXS40PASS_SAR_INSTANCES 16u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bzi_d34.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bzi_d34.h index c0fde284b4..a16d86eff7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bzi_d34.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bzi_d34.h @@ -5,7 +5,7 @@ * CY8C6247BZI-D34 device header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -511,7 +511,7 @@ typedef enum { #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u -#define CY_IP_MXS40PASS_SAR_INSTANCES 16u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bzi_d44.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bzi_d44.h index 322029086c..dc1b42ad29 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bzi_d44.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bzi_d44.h @@ -5,7 +5,7 @@ * CY8C6247BZI-D44 device header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -514,7 +514,7 @@ typedef enum { #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u -#define CY_IP_MXS40PASS_SAR_INSTANCES 16u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bzi_d54.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bzi_d54.h index fa636f5dfd..e88eb3cbbe 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bzi_d54.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bzi_d54.h @@ -5,7 +5,7 @@ * CY8C6247BZI-D54 device header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -514,7 +514,7 @@ typedef enum { #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u -#define CY_IP_MXS40PASS_SAR_INSTANCES 16u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247fdi_d02.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247fdi_d02.h index b0e8acb743..f7b00b4332 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247fdi_d02.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247fdi_d02.h @@ -5,7 +5,7 @@ * CY8C6247FDI-D02 device header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -511,7 +511,7 @@ typedef enum { #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u -#define CY_IP_MXS40PASS_SAR_INSTANCES 16u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247fdi_d32.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247fdi_d32.h index 396f5272ab..a9ae407c99 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247fdi_d32.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247fdi_d32.h @@ -5,7 +5,7 @@ * CY8C6247FDI-D32 device header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -511,7 +511,7 @@ typedef enum { #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u -#define CY_IP_MXS40PASS_SAR_INSTANCES 16u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247fdi_d52.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247fdi_d52.h index c4aedb1a61..ed3e126156 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247fdi_d52.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247fdi_d52.h @@ -5,7 +5,7 @@ * CY8C6247FDI-D52 device header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -514,7 +514,7 @@ typedef enum { #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u -#define CY_IP_MXS40PASS_SAR_INSTANCES 16u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247fti_d52.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247fti_d52.h index da5abaf9b6..1c3fef6cce 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247fti_d52.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247fti_d52.h @@ -5,7 +5,7 @@ * CY8C6247FTI-D52 device header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -514,7 +514,7 @@ typedef enum { #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u -#define CY_IP_MXS40PASS_SAR_INSTANCES 16u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247wi_d54.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247wi_d54.h index dfdd946fdb..c0900a8071 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247wi_d54.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247wi_d54.h @@ -5,7 +5,7 @@ * CY8C6247WI-D54 device header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -514,7 +514,7 @@ typedef enum { #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u -#define CY_IP_MXS40PASS_SAR_INSTANCES 16u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u @@ -545,7 +545,7 @@ typedef enum { #include "gpio_psoc6_01_124_bga.h" #define CY_DEVICE_PSOC6ABLE2 -#define CY_SILICON_ID 0xE2062100UL +#define CY_SILICON_ID 0xE2502100UL #define CY_HF_CLK_MAX_FREQ 150000000UL #define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248azi_d14.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248azi_d14.h new file mode 100644 index 0000000000..6437c4c8e7 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248azi_d14.h @@ -0,0 +1,1316 @@ +/***************************************************************************//** +* \file cy8c6248azi_d14.h +* +* \brief +* CY8C6248AZI-D14 device header +* +* \note +* Generator version: 1.5.0.1274 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6248AZI_D14_H_ +#define _CY8C6248AZI_D14_H_ + +/** +* \addtogroup group_device CY8C6248AZI-D14 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + /* ARM Cortex-M0+ Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6248AZI-D14 User Interrupt Numbers */ + NvicMux0_IRQn = 0, /*!< 0 [DeepSleep] CPU User Interrupt #0 */ + NvicMux1_IRQn = 1, /*!< 1 [DeepSleep] CPU User Interrupt #1 */ + NvicMux2_IRQn = 2, /*!< 2 [DeepSleep] CPU User Interrupt #2 */ + NvicMux3_IRQn = 3, /*!< 3 [DeepSleep] CPU User Interrupt #3 */ + NvicMux4_IRQn = 4, /*!< 4 [DeepSleep] CPU User Interrupt #4 */ + NvicMux5_IRQn = 5, /*!< 5 [DeepSleep] CPU User Interrupt #5 */ + NvicMux6_IRQn = 6, /*!< 6 [DeepSleep] CPU User Interrupt #6 */ + NvicMux7_IRQn = 7, /*!< 7 [DeepSleep] CPU User Interrupt #7 */ + /* CY8C6248AZI-D14 Internal SW Interrupt Numbers */ + Internal0_IRQn = 8, /*!< 8 [Active] Internal SW Interrupt #0 */ + Internal1_IRQn = 9, /*!< 9 [Active] Internal SW Interrupt #1 */ + Internal2_IRQn = 10, /*!< 10 [Active] Internal SW Interrupt #2 */ + Internal3_IRQn = 11, /*!< 11 [Active] Internal SW Interrupt #3 */ + Internal4_IRQn = 12, /*!< 12 [Active] Internal SW Interrupt #4 */ + Internal5_IRQn = 13, /*!< 13 [Active] Internal SW Interrupt #5 */ + Internal6_IRQn = 14, /*!< 14 [Active] Internal SW Interrupt #6 */ + Internal7_IRQn = 15, /*!< 15 [Active] Internal SW Interrupt #7 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#else + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6248AZI-D14 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#endif +} IRQn_Type; + + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* CY8C6248AZI-D14 interrupts that can be routed to the CM0+ NVIC */ +typedef enum { + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + disconnected_IRQn =1023 /*!< 1023 Disconnected */ +} cy_en_intr_t; + +#endif + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */ +#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ + +#else + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 1 /*!< CM0P present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + +#endif + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00100000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00200000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPROFILE 1u +#define CY_IP_MXPROFILE_INSTANCES 1u +#define CY_IP_MXPROFILE_VERSION 1u + +#include "psoc6_02_config.h" +#include "gpio_psoc6_02_128_tqfp.h" + +#define CY_DEVICE_PSOC6A2M +#define CY_SILICON_ID 0xE40C1102UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40004140 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR10_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU6_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_DMAC_CH3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_PROFILE ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_SDHC1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB8 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB9 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB10 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB11 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB12 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ +#define PERI_MS_PPU_FX_PDM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[226]) /* 0x40014080 */ +#define PERI_MS_PPU_FX_I2S0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[227]) /* 0x400140C0 */ +#define PERI_MS_PPU_FX_I2S1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[228]) /* 0x40014100 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU6_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[0]) /* 0x40235A00 */ +#define PROT_MPU6_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[1]) /* 0x40235A20 */ +#define PROT_MPU6_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[2]) /* 0x40235A40 */ +#define PROT_MPU6_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[3]) /* 0x40235A60 */ +#define PROT_MPU6_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[4]) /* 0x40235A80 */ +#define PROT_MPU6_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[5]) /* 0x40235AA0 */ +#define PROT_MPU6_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[6]) /* 0x40235AC0 */ +#define PROT_MPU6_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[7]) /* 0x40235AE0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ +#define DMAC_CH2 ((DMAC_CH_Type*) &DMAC->CH[2]) /* 0x402A1200 */ +#define DMAC_CH3 ((DMAC_CH_Type*) &DMAC->CH[3]) /* 0x402A1300 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* PROFILE +*******************************************************************************/ + +#define PROFILE_BASE 0x402D0000UL +#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */ +#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */ +#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */ +#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */ +#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */ +#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */ +#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */ +#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */ +#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */ +#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */ +#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */ +#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ +#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */ +#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */ +#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */ +#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */ +#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */ +#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */ +#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */ +#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */ +#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */ +#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */ +#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */ +#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */ +#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */ +#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */ +#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */ +#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ +#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC1_BASE 0x40470000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC1 ((SDHC_Type*) SDHC1_BASE) /* 0x40470000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC1_WRAP ((SDHC_WRAP_Type*) &SDHC1->WRAP) /* 0x40470000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ +#define SDHC1_CORE ((SDHC_CORE_Type*) &SDHC1->CORE) /* 0x40471000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB7_BASE 0x40670000UL +#define SCB8_BASE 0x40680000UL +#define SCB9_BASE 0x40690000UL +#define SCB10_BASE 0x406A0000UL +#define SCB11_BASE 0x406B0000UL +#define SCB12_BASE 0x406C0000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ +#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40670000 */ +#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40680000 */ +#define SCB9 ((CySCB_Type*) SCB9_BASE) /* 0x40690000 */ +#define SCB10 ((CySCB_Type*) SCB10_BASE) /* 0x406A0000 */ +#define SCB11 ((CySCB_Type*) SCB11_BASE) /* 0x406B0000 */ +#define SCB12 ((CySCB_Type*) SCB12_BASE) /* 0x406C0000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/******************************************************************************* +* PDM +*******************************************************************************/ + +#define PDM0_BASE 0x40A00000UL +#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x40A00000 */ + +/******************************************************************************* +* I2S +*******************************************************************************/ + +#define I2S0_BASE 0x40A10000UL +#define I2S1_BASE 0x40A11000UL +#define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x40A10000 */ +#define I2S1 ((I2S_Type*) I2S1_BASE) /* 0x40A11000 */ + +/** \} CY8C6248AZI-D14 */ + +#endif /* _CY8C6248AZI_D14_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248azi_d44.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248azi_d44.h new file mode 100644 index 0000000000..b6569811d8 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248azi_d44.h @@ -0,0 +1,1326 @@ +/***************************************************************************//** +* \file cy8c6248azi_d44.h +* +* \brief +* CY8C6248AZI-D44 device header +* +* \note +* Generator version: 1.5.0.1274 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6248AZI_D44_H_ +#define _CY8C6248AZI_D44_H_ + +/** +* \addtogroup group_device CY8C6248AZI-D44 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + /* ARM Cortex-M0+ Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6248AZI-D44 User Interrupt Numbers */ + NvicMux0_IRQn = 0, /*!< 0 [DeepSleep] CPU User Interrupt #0 */ + NvicMux1_IRQn = 1, /*!< 1 [DeepSleep] CPU User Interrupt #1 */ + NvicMux2_IRQn = 2, /*!< 2 [DeepSleep] CPU User Interrupt #2 */ + NvicMux3_IRQn = 3, /*!< 3 [DeepSleep] CPU User Interrupt #3 */ + NvicMux4_IRQn = 4, /*!< 4 [DeepSleep] CPU User Interrupt #4 */ + NvicMux5_IRQn = 5, /*!< 5 [DeepSleep] CPU User Interrupt #5 */ + NvicMux6_IRQn = 6, /*!< 6 [DeepSleep] CPU User Interrupt #6 */ + NvicMux7_IRQn = 7, /*!< 7 [DeepSleep] CPU User Interrupt #7 */ + /* CY8C6248AZI-D44 Internal SW Interrupt Numbers */ + Internal0_IRQn = 8, /*!< 8 [Active] Internal SW Interrupt #0 */ + Internal1_IRQn = 9, /*!< 9 [Active] Internal SW Interrupt #1 */ + Internal2_IRQn = 10, /*!< 10 [Active] Internal SW Interrupt #2 */ + Internal3_IRQn = 11, /*!< 11 [Active] Internal SW Interrupt #3 */ + Internal4_IRQn = 12, /*!< 12 [Active] Internal SW Interrupt #4 */ + Internal5_IRQn = 13, /*!< 13 [Active] Internal SW Interrupt #5 */ + Internal6_IRQn = 14, /*!< 14 [Active] Internal SW Interrupt #6 */ + Internal7_IRQn = 15, /*!< 15 [Active] Internal SW Interrupt #7 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#else + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6248AZI-D44 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#endif +} IRQn_Type; + + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* CY8C6248AZI-D44 interrupts that can be routed to the CM0+ NVIC */ +typedef enum { + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + disconnected_IRQn =1023 /*!< 1023 Disconnected */ +} cy_en_intr_t; + +#endif + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */ +#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ + +#else + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 1 /*!< CM0P present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + +#endif + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00080000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00100000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 2u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPROFILE 1u +#define CY_IP_MXPROFILE_INSTANCES 1u +#define CY_IP_MXPROFILE_VERSION 1u + +#include "psoc6_02_config.h" +#include "gpio_psoc6_02_128_tqfp.h" + +#define CY_DEVICE_PSOC6A2M +#define CY_SILICON_ID 0xE40D1102UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40004140 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR10_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU6_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_DMAC_CH3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_PROFILE ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_SDHC1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB8 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB9 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB10 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB11 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB12 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ +#define PERI_MS_PPU_FX_PDM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[226]) /* 0x40014080 */ +#define PERI_MS_PPU_FX_I2S0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[227]) /* 0x400140C0 */ +#define PERI_MS_PPU_FX_I2S1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[228]) /* 0x40014100 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40100000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40100000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU6_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[0]) /* 0x40235A00 */ +#define PROT_MPU6_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[1]) /* 0x40235A20 */ +#define PROT_MPU6_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[2]) /* 0x40235A40 */ +#define PROT_MPU6_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[3]) /* 0x40235A60 */ +#define PROT_MPU6_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[4]) /* 0x40235A80 */ +#define PROT_MPU6_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[5]) /* 0x40235AA0 */ +#define PROT_MPU6_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[6]) /* 0x40235AC0 */ +#define PROT_MPU6_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[7]) /* 0x40235AE0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ +#define DMAC_CH2 ((DMAC_CH_Type*) &DMAC->CH[2]) /* 0x402A1200 */ +#define DMAC_CH3 ((DMAC_CH_Type*) &DMAC->CH[3]) /* 0x402A1300 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* PROFILE +*******************************************************************************/ + +#define PROFILE_BASE 0x402D0000UL +#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */ +#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */ +#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */ +#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */ +#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */ +#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */ +#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */ +#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */ +#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */ +#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */ +#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */ +#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ +#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */ +#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */ +#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */ +#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */ +#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */ +#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */ +#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */ +#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */ +#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */ +#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */ +#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */ +#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */ +#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */ +#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */ +#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */ +#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ +#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC1_BASE 0x40470000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC1 ((SDHC_Type*) SDHC1_BASE) /* 0x40470000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC1_WRAP ((SDHC_WRAP_Type*) &SDHC1->WRAP) /* 0x40470000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ +#define SDHC1_CORE ((SDHC_CORE_Type*) &SDHC1->CORE) /* 0x40471000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB7_BASE 0x40670000UL +#define SCB8_BASE 0x40680000UL +#define SCB9_BASE 0x40690000UL +#define SCB10_BASE 0x406A0000UL +#define SCB11_BASE 0x406B0000UL +#define SCB12_BASE 0x406C0000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ +#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40670000 */ +#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40680000 */ +#define SCB9 ((CySCB_Type*) SCB9_BASE) /* 0x40690000 */ +#define SCB10 ((CySCB_Type*) SCB10_BASE) /* 0x406A0000 */ +#define SCB11 ((CySCB_Type*) SCB11_BASE) /* 0x406B0000 */ +#define SCB12 ((CySCB_Type*) SCB12_BASE) /* 0x406C0000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/******************************************************************************* +* PDM +*******************************************************************************/ + +#define PDM0_BASE 0x40A00000UL +#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x40A00000 */ + +/******************************************************************************* +* I2S +*******************************************************************************/ + +#define I2S0_BASE 0x40A10000UL +#define I2S1_BASE 0x40A11000UL +#define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x40A10000 */ +#define I2S1 ((I2S_Type*) I2S1_BASE) /* 0x40A11000 */ + +/** \} CY8C6248AZI-D44 */ + +#endif /* _CY8C6248AZI_D44_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248azi_s2d14.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248azi_s2d14.h new file mode 100644 index 0000000000..670bfdb8af --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248azi_s2d14.h @@ -0,0 +1,1316 @@ +/***************************************************************************//** +* \file cy8c6248azi_s2d14.h +* +* \brief +* CY8C6248AZI-S2D14 device header +* +* \note +* Generator version: 1.5.0.1274 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6248AZI_S2D14_H_ +#define _CY8C6248AZI_S2D14_H_ + +/** +* \addtogroup group_device CY8C6248AZI-S2D14 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + /* ARM Cortex-M0+ Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6248AZI-S2D14 User Interrupt Numbers */ + NvicMux0_IRQn = 0, /*!< 0 [DeepSleep] CPU User Interrupt #0 */ + NvicMux1_IRQn = 1, /*!< 1 [DeepSleep] CPU User Interrupt #1 */ + NvicMux2_IRQn = 2, /*!< 2 [DeepSleep] CPU User Interrupt #2 */ + NvicMux3_IRQn = 3, /*!< 3 [DeepSleep] CPU User Interrupt #3 */ + NvicMux4_IRQn = 4, /*!< 4 [DeepSleep] CPU User Interrupt #4 */ + NvicMux5_IRQn = 5, /*!< 5 [DeepSleep] CPU User Interrupt #5 */ + NvicMux6_IRQn = 6, /*!< 6 [DeepSleep] CPU User Interrupt #6 */ + NvicMux7_IRQn = 7, /*!< 7 [DeepSleep] CPU User Interrupt #7 */ + /* CY8C6248AZI-S2D14 Internal SW Interrupt Numbers */ + Internal0_IRQn = 8, /*!< 8 [Active] Internal SW Interrupt #0 */ + Internal1_IRQn = 9, /*!< 9 [Active] Internal SW Interrupt #1 */ + Internal2_IRQn = 10, /*!< 10 [Active] Internal SW Interrupt #2 */ + Internal3_IRQn = 11, /*!< 11 [Active] Internal SW Interrupt #3 */ + Internal4_IRQn = 12, /*!< 12 [Active] Internal SW Interrupt #4 */ + Internal5_IRQn = 13, /*!< 13 [Active] Internal SW Interrupt #5 */ + Internal6_IRQn = 14, /*!< 14 [Active] Internal SW Interrupt #6 */ + Internal7_IRQn = 15, /*!< 15 [Active] Internal SW Interrupt #7 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#else + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6248AZI-S2D14 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#endif +} IRQn_Type; + + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* CY8C6248AZI-S2D14 interrupts that can be routed to the CM0+ NVIC */ +typedef enum { + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + disconnected_IRQn =1023 /*!< 1023 Disconnected */ +} cy_en_intr_t; + +#endif + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */ +#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ + +#else + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 1 /*!< CM0P present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + +#endif + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00100000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00200000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPROFILE 1u +#define CY_IP_MXPROFILE_INSTANCES 1u +#define CY_IP_MXPROFILE_VERSION 1u + +#include "psoc6_02_config.h" +#include "gpio_psoc6_02_128_tqfp.h" + +#define CY_DEVICE_PSOC6A2M +#define CY_SILICON_ID 0xE4561102UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40004140 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR10_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU6_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_DMAC_CH3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_PROFILE ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_SDHC1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB8 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB9 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB10 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB11 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB12 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ +#define PERI_MS_PPU_FX_PDM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[226]) /* 0x40014080 */ +#define PERI_MS_PPU_FX_I2S0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[227]) /* 0x400140C0 */ +#define PERI_MS_PPU_FX_I2S1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[228]) /* 0x40014100 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU6_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[0]) /* 0x40235A00 */ +#define PROT_MPU6_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[1]) /* 0x40235A20 */ +#define PROT_MPU6_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[2]) /* 0x40235A40 */ +#define PROT_MPU6_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[3]) /* 0x40235A60 */ +#define PROT_MPU6_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[4]) /* 0x40235A80 */ +#define PROT_MPU6_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[5]) /* 0x40235AA0 */ +#define PROT_MPU6_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[6]) /* 0x40235AC0 */ +#define PROT_MPU6_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[7]) /* 0x40235AE0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ +#define DMAC_CH2 ((DMAC_CH_Type*) &DMAC->CH[2]) /* 0x402A1200 */ +#define DMAC_CH3 ((DMAC_CH_Type*) &DMAC->CH[3]) /* 0x402A1300 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* PROFILE +*******************************************************************************/ + +#define PROFILE_BASE 0x402D0000UL +#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */ +#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */ +#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */ +#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */ +#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */ +#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */ +#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */ +#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */ +#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */ +#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */ +#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */ +#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ +#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */ +#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */ +#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */ +#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */ +#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */ +#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */ +#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */ +#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */ +#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */ +#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */ +#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */ +#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */ +#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */ +#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */ +#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */ +#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ +#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC1_BASE 0x40470000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC1 ((SDHC_Type*) SDHC1_BASE) /* 0x40470000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC1_WRAP ((SDHC_WRAP_Type*) &SDHC1->WRAP) /* 0x40470000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ +#define SDHC1_CORE ((SDHC_CORE_Type*) &SDHC1->CORE) /* 0x40471000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB7_BASE 0x40670000UL +#define SCB8_BASE 0x40680000UL +#define SCB9_BASE 0x40690000UL +#define SCB10_BASE 0x406A0000UL +#define SCB11_BASE 0x406B0000UL +#define SCB12_BASE 0x406C0000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ +#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40670000 */ +#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40680000 */ +#define SCB9 ((CySCB_Type*) SCB9_BASE) /* 0x40690000 */ +#define SCB10 ((CySCB_Type*) SCB10_BASE) /* 0x406A0000 */ +#define SCB11 ((CySCB_Type*) SCB11_BASE) /* 0x406B0000 */ +#define SCB12 ((CySCB_Type*) SCB12_BASE) /* 0x406C0000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/******************************************************************************* +* PDM +*******************************************************************************/ + +#define PDM0_BASE 0x40A00000UL +#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x40A00000 */ + +/******************************************************************************* +* I2S +*******************************************************************************/ + +#define I2S0_BASE 0x40A10000UL +#define I2S1_BASE 0x40A11000UL +#define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x40A10000 */ +#define I2S1 ((I2S_Type*) I2S1_BASE) /* 0x40A11000 */ + +/** \} CY8C6248AZI-S2D14 */ + +#endif /* _CY8C6248AZI_S2D14_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248azi_s2d44.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248azi_s2d44.h new file mode 100644 index 0000000000..3ada3b7c84 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248azi_s2d44.h @@ -0,0 +1,1326 @@ +/***************************************************************************//** +* \file cy8c6248azi_s2d44.h +* +* \brief +* CY8C6248AZI-S2D44 device header +* +* \note +* Generator version: 1.5.0.1274 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6248AZI_S2D44_H_ +#define _CY8C6248AZI_S2D44_H_ + +/** +* \addtogroup group_device CY8C6248AZI-S2D44 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + /* ARM Cortex-M0+ Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6248AZI-S2D44 User Interrupt Numbers */ + NvicMux0_IRQn = 0, /*!< 0 [DeepSleep] CPU User Interrupt #0 */ + NvicMux1_IRQn = 1, /*!< 1 [DeepSleep] CPU User Interrupt #1 */ + NvicMux2_IRQn = 2, /*!< 2 [DeepSleep] CPU User Interrupt #2 */ + NvicMux3_IRQn = 3, /*!< 3 [DeepSleep] CPU User Interrupt #3 */ + NvicMux4_IRQn = 4, /*!< 4 [DeepSleep] CPU User Interrupt #4 */ + NvicMux5_IRQn = 5, /*!< 5 [DeepSleep] CPU User Interrupt #5 */ + NvicMux6_IRQn = 6, /*!< 6 [DeepSleep] CPU User Interrupt #6 */ + NvicMux7_IRQn = 7, /*!< 7 [DeepSleep] CPU User Interrupt #7 */ + /* CY8C6248AZI-S2D44 Internal SW Interrupt Numbers */ + Internal0_IRQn = 8, /*!< 8 [Active] Internal SW Interrupt #0 */ + Internal1_IRQn = 9, /*!< 9 [Active] Internal SW Interrupt #1 */ + Internal2_IRQn = 10, /*!< 10 [Active] Internal SW Interrupt #2 */ + Internal3_IRQn = 11, /*!< 11 [Active] Internal SW Interrupt #3 */ + Internal4_IRQn = 12, /*!< 12 [Active] Internal SW Interrupt #4 */ + Internal5_IRQn = 13, /*!< 13 [Active] Internal SW Interrupt #5 */ + Internal6_IRQn = 14, /*!< 14 [Active] Internal SW Interrupt #6 */ + Internal7_IRQn = 15, /*!< 15 [Active] Internal SW Interrupt #7 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#else + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6248AZI-S2D44 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#endif +} IRQn_Type; + + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* CY8C6248AZI-S2D44 interrupts that can be routed to the CM0+ NVIC */ +typedef enum { + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + disconnected_IRQn =1023 /*!< 1023 Disconnected */ +} cy_en_intr_t; + +#endif + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */ +#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ + +#else + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 1 /*!< CM0P present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + +#endif + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00080000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00100000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 2u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPROFILE 1u +#define CY_IP_MXPROFILE_INSTANCES 1u +#define CY_IP_MXPROFILE_VERSION 1u + +#include "psoc6_02_config.h" +#include "gpio_psoc6_02_128_tqfp.h" + +#define CY_DEVICE_PSOC6A2M +#define CY_SILICON_ID 0xE4581102UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40004140 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR10_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU6_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_DMAC_CH3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_PROFILE ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_SDHC1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB8 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB9 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB10 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB11 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB12 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ +#define PERI_MS_PPU_FX_PDM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[226]) /* 0x40014080 */ +#define PERI_MS_PPU_FX_I2S0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[227]) /* 0x400140C0 */ +#define PERI_MS_PPU_FX_I2S1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[228]) /* 0x40014100 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40100000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40100000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU6_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[0]) /* 0x40235A00 */ +#define PROT_MPU6_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[1]) /* 0x40235A20 */ +#define PROT_MPU6_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[2]) /* 0x40235A40 */ +#define PROT_MPU6_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[3]) /* 0x40235A60 */ +#define PROT_MPU6_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[4]) /* 0x40235A80 */ +#define PROT_MPU6_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[5]) /* 0x40235AA0 */ +#define PROT_MPU6_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[6]) /* 0x40235AC0 */ +#define PROT_MPU6_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[7]) /* 0x40235AE0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ +#define DMAC_CH2 ((DMAC_CH_Type*) &DMAC->CH[2]) /* 0x402A1200 */ +#define DMAC_CH3 ((DMAC_CH_Type*) &DMAC->CH[3]) /* 0x402A1300 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* PROFILE +*******************************************************************************/ + +#define PROFILE_BASE 0x402D0000UL +#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */ +#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */ +#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */ +#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */ +#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */ +#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */ +#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */ +#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */ +#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */ +#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */ +#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */ +#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ +#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */ +#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */ +#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */ +#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */ +#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */ +#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */ +#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */ +#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */ +#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */ +#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */ +#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */ +#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */ +#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */ +#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */ +#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */ +#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ +#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC1_BASE 0x40470000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC1 ((SDHC_Type*) SDHC1_BASE) /* 0x40470000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC1_WRAP ((SDHC_WRAP_Type*) &SDHC1->WRAP) /* 0x40470000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ +#define SDHC1_CORE ((SDHC_CORE_Type*) &SDHC1->CORE) /* 0x40471000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB7_BASE 0x40670000UL +#define SCB8_BASE 0x40680000UL +#define SCB9_BASE 0x40690000UL +#define SCB10_BASE 0x406A0000UL +#define SCB11_BASE 0x406B0000UL +#define SCB12_BASE 0x406C0000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ +#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40670000 */ +#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40680000 */ +#define SCB9 ((CySCB_Type*) SCB9_BASE) /* 0x40690000 */ +#define SCB10 ((CySCB_Type*) SCB10_BASE) /* 0x406A0000 */ +#define SCB11 ((CySCB_Type*) SCB11_BASE) /* 0x406B0000 */ +#define SCB12 ((CySCB_Type*) SCB12_BASE) /* 0x406C0000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/******************************************************************************* +* PDM +*******************************************************************************/ + +#define PDM0_BASE 0x40A00000UL +#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x40A00000 */ + +/******************************************************************************* +* I2S +*******************************************************************************/ + +#define I2S0_BASE 0x40A10000UL +#define I2S1_BASE 0x40A11000UL +#define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x40A10000 */ +#define I2S1 ((I2S_Type*) I2S1_BASE) /* 0x40A11000 */ + +/** \} CY8C6248AZI-S2D44 */ + +#endif /* _CY8C6248AZI_S2D44_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248bzi_d44.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248bzi_d44.h new file mode 100644 index 0000000000..ea09a13bcf --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248bzi_d44.h @@ -0,0 +1,1326 @@ +/***************************************************************************//** +* \file cy8c6248bzi_d44.h +* +* \brief +* CY8C6248BZI-D44 device header +* +* \note +* Generator version: 1.5.0.1274 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6248BZI_D44_H_ +#define _CY8C6248BZI_D44_H_ + +/** +* \addtogroup group_device CY8C6248BZI-D44 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + /* ARM Cortex-M0+ Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6248BZI-D44 User Interrupt Numbers */ + NvicMux0_IRQn = 0, /*!< 0 [DeepSleep] CPU User Interrupt #0 */ + NvicMux1_IRQn = 1, /*!< 1 [DeepSleep] CPU User Interrupt #1 */ + NvicMux2_IRQn = 2, /*!< 2 [DeepSleep] CPU User Interrupt #2 */ + NvicMux3_IRQn = 3, /*!< 3 [DeepSleep] CPU User Interrupt #3 */ + NvicMux4_IRQn = 4, /*!< 4 [DeepSleep] CPU User Interrupt #4 */ + NvicMux5_IRQn = 5, /*!< 5 [DeepSleep] CPU User Interrupt #5 */ + NvicMux6_IRQn = 6, /*!< 6 [DeepSleep] CPU User Interrupt #6 */ + NvicMux7_IRQn = 7, /*!< 7 [DeepSleep] CPU User Interrupt #7 */ + /* CY8C6248BZI-D44 Internal SW Interrupt Numbers */ + Internal0_IRQn = 8, /*!< 8 [Active] Internal SW Interrupt #0 */ + Internal1_IRQn = 9, /*!< 9 [Active] Internal SW Interrupt #1 */ + Internal2_IRQn = 10, /*!< 10 [Active] Internal SW Interrupt #2 */ + Internal3_IRQn = 11, /*!< 11 [Active] Internal SW Interrupt #3 */ + Internal4_IRQn = 12, /*!< 12 [Active] Internal SW Interrupt #4 */ + Internal5_IRQn = 13, /*!< 13 [Active] Internal SW Interrupt #5 */ + Internal6_IRQn = 14, /*!< 14 [Active] Internal SW Interrupt #6 */ + Internal7_IRQn = 15, /*!< 15 [Active] Internal SW Interrupt #7 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#else + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6248BZI-D44 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#endif +} IRQn_Type; + + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* CY8C6248BZI-D44 interrupts that can be routed to the CM0+ NVIC */ +typedef enum { + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + disconnected_IRQn =1023 /*!< 1023 Disconnected */ +} cy_en_intr_t; + +#endif + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */ +#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ + +#else + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 1 /*!< CM0P present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + +#endif + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00080000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00100000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 2u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPROFILE 1u +#define CY_IP_MXPROFILE_INSTANCES 1u +#define CY_IP_MXPROFILE_VERSION 1u + +#include "psoc6_02_config.h" +#include "gpio_psoc6_02_124_bga.h" + +#define CY_DEVICE_PSOC6A2M +#define CY_SILICON_ID 0xE4031102UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40004140 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR10_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU6_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_DMAC_CH3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_PROFILE ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_SDHC1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB8 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB9 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB10 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB11 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB12 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ +#define PERI_MS_PPU_FX_PDM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[226]) /* 0x40014080 */ +#define PERI_MS_PPU_FX_I2S0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[227]) /* 0x400140C0 */ +#define PERI_MS_PPU_FX_I2S1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[228]) /* 0x40014100 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40100000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40100000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU6_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[0]) /* 0x40235A00 */ +#define PROT_MPU6_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[1]) /* 0x40235A20 */ +#define PROT_MPU6_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[2]) /* 0x40235A40 */ +#define PROT_MPU6_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[3]) /* 0x40235A60 */ +#define PROT_MPU6_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[4]) /* 0x40235A80 */ +#define PROT_MPU6_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[5]) /* 0x40235AA0 */ +#define PROT_MPU6_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[6]) /* 0x40235AC0 */ +#define PROT_MPU6_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[7]) /* 0x40235AE0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ +#define DMAC_CH2 ((DMAC_CH_Type*) &DMAC->CH[2]) /* 0x402A1200 */ +#define DMAC_CH3 ((DMAC_CH_Type*) &DMAC->CH[3]) /* 0x402A1300 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* PROFILE +*******************************************************************************/ + +#define PROFILE_BASE 0x402D0000UL +#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */ +#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */ +#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */ +#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */ +#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */ +#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */ +#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */ +#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */ +#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */ +#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */ +#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */ +#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ +#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */ +#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */ +#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */ +#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */ +#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */ +#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */ +#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */ +#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */ +#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */ +#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */ +#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */ +#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */ +#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */ +#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */ +#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */ +#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ +#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC1_BASE 0x40470000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC1 ((SDHC_Type*) SDHC1_BASE) /* 0x40470000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC1_WRAP ((SDHC_WRAP_Type*) &SDHC1->WRAP) /* 0x40470000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ +#define SDHC1_CORE ((SDHC_CORE_Type*) &SDHC1->CORE) /* 0x40471000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB7_BASE 0x40670000UL +#define SCB8_BASE 0x40680000UL +#define SCB9_BASE 0x40690000UL +#define SCB10_BASE 0x406A0000UL +#define SCB11_BASE 0x406B0000UL +#define SCB12_BASE 0x406C0000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ +#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40670000 */ +#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40680000 */ +#define SCB9 ((CySCB_Type*) SCB9_BASE) /* 0x40690000 */ +#define SCB10 ((CySCB_Type*) SCB10_BASE) /* 0x406A0000 */ +#define SCB11 ((CySCB_Type*) SCB11_BASE) /* 0x406B0000 */ +#define SCB12 ((CySCB_Type*) SCB12_BASE) /* 0x406C0000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/******************************************************************************* +* PDM +*******************************************************************************/ + +#define PDM0_BASE 0x40A00000UL +#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x40A00000 */ + +/******************************************************************************* +* I2S +*******************************************************************************/ + +#define I2S0_BASE 0x40A10000UL +#define I2S1_BASE 0x40A11000UL +#define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x40A10000 */ +#define I2S1 ((I2S_Type*) I2S1_BASE) /* 0x40A11000 */ + +/** \} CY8C6248BZI-D44 */ + +#endif /* _CY8C6248BZI_D44_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248bzi_s2d44.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248bzi_s2d44.h new file mode 100644 index 0000000000..ba447ac90f --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248bzi_s2d44.h @@ -0,0 +1,1326 @@ +/***************************************************************************//** +* \file cy8c6248bzi_s2d44.h +* +* \brief +* CY8C6248BZI-S2D44 device header +* +* \note +* Generator version: 1.5.0.1274 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6248BZI_S2D44_H_ +#define _CY8C6248BZI_S2D44_H_ + +/** +* \addtogroup group_device CY8C6248BZI-S2D44 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + /* ARM Cortex-M0+ Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6248BZI-S2D44 User Interrupt Numbers */ + NvicMux0_IRQn = 0, /*!< 0 [DeepSleep] CPU User Interrupt #0 */ + NvicMux1_IRQn = 1, /*!< 1 [DeepSleep] CPU User Interrupt #1 */ + NvicMux2_IRQn = 2, /*!< 2 [DeepSleep] CPU User Interrupt #2 */ + NvicMux3_IRQn = 3, /*!< 3 [DeepSleep] CPU User Interrupt #3 */ + NvicMux4_IRQn = 4, /*!< 4 [DeepSleep] CPU User Interrupt #4 */ + NvicMux5_IRQn = 5, /*!< 5 [DeepSleep] CPU User Interrupt #5 */ + NvicMux6_IRQn = 6, /*!< 6 [DeepSleep] CPU User Interrupt #6 */ + NvicMux7_IRQn = 7, /*!< 7 [DeepSleep] CPU User Interrupt #7 */ + /* CY8C6248BZI-S2D44 Internal SW Interrupt Numbers */ + Internal0_IRQn = 8, /*!< 8 [Active] Internal SW Interrupt #0 */ + Internal1_IRQn = 9, /*!< 9 [Active] Internal SW Interrupt #1 */ + Internal2_IRQn = 10, /*!< 10 [Active] Internal SW Interrupt #2 */ + Internal3_IRQn = 11, /*!< 11 [Active] Internal SW Interrupt #3 */ + Internal4_IRQn = 12, /*!< 12 [Active] Internal SW Interrupt #4 */ + Internal5_IRQn = 13, /*!< 13 [Active] Internal SW Interrupt #5 */ + Internal6_IRQn = 14, /*!< 14 [Active] Internal SW Interrupt #6 */ + Internal7_IRQn = 15, /*!< 15 [Active] Internal SW Interrupt #7 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#else + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6248BZI-S2D44 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#endif +} IRQn_Type; + + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* CY8C6248BZI-S2D44 interrupts that can be routed to the CM0+ NVIC */ +typedef enum { + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + disconnected_IRQn =1023 /*!< 1023 Disconnected */ +} cy_en_intr_t; + +#endif + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */ +#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ + +#else + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 1 /*!< CM0P present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + +#endif + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00080000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00100000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 2u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPROFILE 1u +#define CY_IP_MXPROFILE_INSTANCES 1u +#define CY_IP_MXPROFILE_VERSION 1u + +#include "psoc6_02_config.h" +#include "gpio_psoc6_02_124_bga.h" + +#define CY_DEVICE_PSOC6A2M +#define CY_SILICON_ID 0xE4571102UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40004140 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR10_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU6_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_DMAC_CH3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_PROFILE ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_SDHC1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB8 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB9 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB10 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB11 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB12 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ +#define PERI_MS_PPU_FX_PDM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[226]) /* 0x40014080 */ +#define PERI_MS_PPU_FX_I2S0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[227]) /* 0x400140C0 */ +#define PERI_MS_PPU_FX_I2S1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[228]) /* 0x40014100 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40100000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40100000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU6_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[0]) /* 0x40235A00 */ +#define PROT_MPU6_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[1]) /* 0x40235A20 */ +#define PROT_MPU6_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[2]) /* 0x40235A40 */ +#define PROT_MPU6_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[3]) /* 0x40235A60 */ +#define PROT_MPU6_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[4]) /* 0x40235A80 */ +#define PROT_MPU6_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[5]) /* 0x40235AA0 */ +#define PROT_MPU6_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[6]) /* 0x40235AC0 */ +#define PROT_MPU6_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[7]) /* 0x40235AE0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ +#define DMAC_CH2 ((DMAC_CH_Type*) &DMAC->CH[2]) /* 0x402A1200 */ +#define DMAC_CH3 ((DMAC_CH_Type*) &DMAC->CH[3]) /* 0x402A1300 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* PROFILE +*******************************************************************************/ + +#define PROFILE_BASE 0x402D0000UL +#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */ +#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */ +#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */ +#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */ +#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */ +#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */ +#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */ +#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */ +#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */ +#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */ +#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */ +#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ +#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */ +#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */ +#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */ +#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */ +#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */ +#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */ +#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */ +#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */ +#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */ +#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */ +#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */ +#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */ +#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */ +#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */ +#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */ +#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ +#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC1_BASE 0x40470000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC1 ((SDHC_Type*) SDHC1_BASE) /* 0x40470000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC1_WRAP ((SDHC_WRAP_Type*) &SDHC1->WRAP) /* 0x40470000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ +#define SDHC1_CORE ((SDHC_CORE_Type*) &SDHC1->CORE) /* 0x40471000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB7_BASE 0x40670000UL +#define SCB8_BASE 0x40680000UL +#define SCB9_BASE 0x40690000UL +#define SCB10_BASE 0x406A0000UL +#define SCB11_BASE 0x406B0000UL +#define SCB12_BASE 0x406C0000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ +#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40670000 */ +#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40680000 */ +#define SCB9 ((CySCB_Type*) SCB9_BASE) /* 0x40690000 */ +#define SCB10 ((CySCB_Type*) SCB10_BASE) /* 0x406A0000 */ +#define SCB11 ((CySCB_Type*) SCB11_BASE) /* 0x406B0000 */ +#define SCB12 ((CySCB_Type*) SCB12_BASE) /* 0x406C0000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/******************************************************************************* +* PDM +*******************************************************************************/ + +#define PDM0_BASE 0x40A00000UL +#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x40A00000 */ + +/******************************************************************************* +* I2S +*******************************************************************************/ + +#define I2S0_BASE 0x40A10000UL +#define I2S1_BASE 0x40A11000UL +#define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x40A10000 */ +#define I2S1 ((I2S_Type*) I2S1_BASE) /* 0x40A11000 */ + +/** \} CY8C6248BZI-S2D44 */ + +#endif /* _CY8C6248BZI_S2D44_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248fni_d43.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248fni_d43.h new file mode 100644 index 0000000000..78e9decbf8 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248fni_d43.h @@ -0,0 +1,1326 @@ +/***************************************************************************//** +* \file cy8c6248fni_d43.h +* +* \brief +* CY8C6248FNI-D43 device header +* +* \note +* Generator version: 1.5.0.1274 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6248FNI_D43_H_ +#define _CY8C6248FNI_D43_H_ + +/** +* \addtogroup group_device CY8C6248FNI-D43 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + /* ARM Cortex-M0+ Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6248FNI-D43 User Interrupt Numbers */ + NvicMux0_IRQn = 0, /*!< 0 [DeepSleep] CPU User Interrupt #0 */ + NvicMux1_IRQn = 1, /*!< 1 [DeepSleep] CPU User Interrupt #1 */ + NvicMux2_IRQn = 2, /*!< 2 [DeepSleep] CPU User Interrupt #2 */ + NvicMux3_IRQn = 3, /*!< 3 [DeepSleep] CPU User Interrupt #3 */ + NvicMux4_IRQn = 4, /*!< 4 [DeepSleep] CPU User Interrupt #4 */ + NvicMux5_IRQn = 5, /*!< 5 [DeepSleep] CPU User Interrupt #5 */ + NvicMux6_IRQn = 6, /*!< 6 [DeepSleep] CPU User Interrupt #6 */ + NvicMux7_IRQn = 7, /*!< 7 [DeepSleep] CPU User Interrupt #7 */ + /* CY8C6248FNI-D43 Internal SW Interrupt Numbers */ + Internal0_IRQn = 8, /*!< 8 [Active] Internal SW Interrupt #0 */ + Internal1_IRQn = 9, /*!< 9 [Active] Internal SW Interrupt #1 */ + Internal2_IRQn = 10, /*!< 10 [Active] Internal SW Interrupt #2 */ + Internal3_IRQn = 11, /*!< 11 [Active] Internal SW Interrupt #3 */ + Internal4_IRQn = 12, /*!< 12 [Active] Internal SW Interrupt #4 */ + Internal5_IRQn = 13, /*!< 13 [Active] Internal SW Interrupt #5 */ + Internal6_IRQn = 14, /*!< 14 [Active] Internal SW Interrupt #6 */ + Internal7_IRQn = 15, /*!< 15 [Active] Internal SW Interrupt #7 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#else + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6248FNI-D43 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#endif +} IRQn_Type; + + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* CY8C6248FNI-D43 interrupts that can be routed to the CM0+ NVIC */ +typedef enum { + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + disconnected_IRQn =1023 /*!< 1023 Disconnected */ +} cy_en_intr_t; + +#endif + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */ +#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ + +#else + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 1 /*!< CM0P present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + +#endif + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00080000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00100000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 2u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPROFILE 1u +#define CY_IP_MXPROFILE_INSTANCES 1u +#define CY_IP_MXPROFILE_VERSION 1u + +#include "psoc6_02_config.h" +#include "gpio_psoc6_02_100_wlcsp.h" + +#define CY_DEVICE_PSOC6A2M +#define CY_SILICON_ID 0xE4151102UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40004140 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR10_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU6_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_DMAC_CH3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_PROFILE ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_SDHC1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB8 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB9 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB10 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB11 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB12 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ +#define PERI_MS_PPU_FX_PDM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[226]) /* 0x40014080 */ +#define PERI_MS_PPU_FX_I2S0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[227]) /* 0x400140C0 */ +#define PERI_MS_PPU_FX_I2S1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[228]) /* 0x40014100 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40100000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40100000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU6_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[0]) /* 0x40235A00 */ +#define PROT_MPU6_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[1]) /* 0x40235A20 */ +#define PROT_MPU6_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[2]) /* 0x40235A40 */ +#define PROT_MPU6_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[3]) /* 0x40235A60 */ +#define PROT_MPU6_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[4]) /* 0x40235A80 */ +#define PROT_MPU6_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[5]) /* 0x40235AA0 */ +#define PROT_MPU6_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[6]) /* 0x40235AC0 */ +#define PROT_MPU6_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[7]) /* 0x40235AE0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ +#define DMAC_CH2 ((DMAC_CH_Type*) &DMAC->CH[2]) /* 0x402A1200 */ +#define DMAC_CH3 ((DMAC_CH_Type*) &DMAC->CH[3]) /* 0x402A1300 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* PROFILE +*******************************************************************************/ + +#define PROFILE_BASE 0x402D0000UL +#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */ +#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */ +#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */ +#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */ +#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */ +#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */ +#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */ +#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */ +#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */ +#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */ +#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */ +#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ +#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */ +#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */ +#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */ +#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */ +#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */ +#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */ +#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */ +#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */ +#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */ +#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */ +#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */ +#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */ +#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */ +#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */ +#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */ +#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ +#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC1_BASE 0x40470000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC1 ((SDHC_Type*) SDHC1_BASE) /* 0x40470000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC1_WRAP ((SDHC_WRAP_Type*) &SDHC1->WRAP) /* 0x40470000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ +#define SDHC1_CORE ((SDHC_CORE_Type*) &SDHC1->CORE) /* 0x40471000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB7_BASE 0x40670000UL +#define SCB8_BASE 0x40680000UL +#define SCB9_BASE 0x40690000UL +#define SCB10_BASE 0x406A0000UL +#define SCB11_BASE 0x406B0000UL +#define SCB12_BASE 0x406C0000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ +#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40670000 */ +#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40680000 */ +#define SCB9 ((CySCB_Type*) SCB9_BASE) /* 0x40690000 */ +#define SCB10 ((CySCB_Type*) SCB10_BASE) /* 0x406A0000 */ +#define SCB11 ((CySCB_Type*) SCB11_BASE) /* 0x406B0000 */ +#define SCB12 ((CySCB_Type*) SCB12_BASE) /* 0x406C0000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/******************************************************************************* +* PDM +*******************************************************************************/ + +#define PDM0_BASE 0x40A00000UL +#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x40A00000 */ + +/******************************************************************************* +* I2S +*******************************************************************************/ + +#define I2S0_BASE 0x40A10000UL +#define I2S1_BASE 0x40A11000UL +#define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x40A10000 */ +#define I2S1 ((I2S_Type*) I2S1_BASE) /* 0x40A11000 */ + +/** \} CY8C6248FNI-D43 */ + +#endif /* _CY8C6248FNI_D43_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248fni_s2d43.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248fni_s2d43.h new file mode 100644 index 0000000000..b88c820d70 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248fni_s2d43.h @@ -0,0 +1,1326 @@ +/***************************************************************************//** +* \file cy8c6248fni_s2d43.h +* +* \brief +* CY8C6248FNI-S2D43 device header +* +* \note +* Generator version: 1.5.0.1274 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6248FNI_S2D43_H_ +#define _CY8C6248FNI_S2D43_H_ + +/** +* \addtogroup group_device CY8C6248FNI-S2D43 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + /* ARM Cortex-M0+ Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6248FNI-S2D43 User Interrupt Numbers */ + NvicMux0_IRQn = 0, /*!< 0 [DeepSleep] CPU User Interrupt #0 */ + NvicMux1_IRQn = 1, /*!< 1 [DeepSleep] CPU User Interrupt #1 */ + NvicMux2_IRQn = 2, /*!< 2 [DeepSleep] CPU User Interrupt #2 */ + NvicMux3_IRQn = 3, /*!< 3 [DeepSleep] CPU User Interrupt #3 */ + NvicMux4_IRQn = 4, /*!< 4 [DeepSleep] CPU User Interrupt #4 */ + NvicMux5_IRQn = 5, /*!< 5 [DeepSleep] CPU User Interrupt #5 */ + NvicMux6_IRQn = 6, /*!< 6 [DeepSleep] CPU User Interrupt #6 */ + NvicMux7_IRQn = 7, /*!< 7 [DeepSleep] CPU User Interrupt #7 */ + /* CY8C6248FNI-S2D43 Internal SW Interrupt Numbers */ + Internal0_IRQn = 8, /*!< 8 [Active] Internal SW Interrupt #0 */ + Internal1_IRQn = 9, /*!< 9 [Active] Internal SW Interrupt #1 */ + Internal2_IRQn = 10, /*!< 10 [Active] Internal SW Interrupt #2 */ + Internal3_IRQn = 11, /*!< 11 [Active] Internal SW Interrupt #3 */ + Internal4_IRQn = 12, /*!< 12 [Active] Internal SW Interrupt #4 */ + Internal5_IRQn = 13, /*!< 13 [Active] Internal SW Interrupt #5 */ + Internal6_IRQn = 14, /*!< 14 [Active] Internal SW Interrupt #6 */ + Internal7_IRQn = 15, /*!< 15 [Active] Internal SW Interrupt #7 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#else + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6248FNI-S2D43 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#endif +} IRQn_Type; + + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* CY8C6248FNI-S2D43 interrupts that can be routed to the CM0+ NVIC */ +typedef enum { + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + disconnected_IRQn =1023 /*!< 1023 Disconnected */ +} cy_en_intr_t; + +#endif + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */ +#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ + +#else + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 1 /*!< CM0P present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + +#endif + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00080000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00100000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 2u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPROFILE 1u +#define CY_IP_MXPROFILE_INSTANCES 1u +#define CY_IP_MXPROFILE_VERSION 1u + +#include "psoc6_02_config.h" +#include "gpio_psoc6_02_100_wlcsp.h" + +#define CY_DEVICE_PSOC6A2M +#define CY_SILICON_ID 0xE4591102UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40004140 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR10_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU6_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_DMAC_CH3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_PROFILE ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_SDHC1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB8 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB9 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB10 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB11 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB12 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ +#define PERI_MS_PPU_FX_PDM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[226]) /* 0x40014080 */ +#define PERI_MS_PPU_FX_I2S0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[227]) /* 0x400140C0 */ +#define PERI_MS_PPU_FX_I2S1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[228]) /* 0x40014100 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40100000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40100000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU6_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[0]) /* 0x40235A00 */ +#define PROT_MPU6_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[1]) /* 0x40235A20 */ +#define PROT_MPU6_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[2]) /* 0x40235A40 */ +#define PROT_MPU6_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[3]) /* 0x40235A60 */ +#define PROT_MPU6_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[4]) /* 0x40235A80 */ +#define PROT_MPU6_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[5]) /* 0x40235AA0 */ +#define PROT_MPU6_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[6]) /* 0x40235AC0 */ +#define PROT_MPU6_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[7]) /* 0x40235AE0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ +#define DMAC_CH2 ((DMAC_CH_Type*) &DMAC->CH[2]) /* 0x402A1200 */ +#define DMAC_CH3 ((DMAC_CH_Type*) &DMAC->CH[3]) /* 0x402A1300 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* PROFILE +*******************************************************************************/ + +#define PROFILE_BASE 0x402D0000UL +#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */ +#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */ +#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */ +#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */ +#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */ +#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */ +#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */ +#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */ +#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */ +#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */ +#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */ +#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ +#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */ +#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */ +#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */ +#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */ +#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */ +#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */ +#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */ +#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */ +#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */ +#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */ +#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */ +#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */ +#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */ +#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */ +#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */ +#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ +#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC1_BASE 0x40470000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC1 ((SDHC_Type*) SDHC1_BASE) /* 0x40470000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC1_WRAP ((SDHC_WRAP_Type*) &SDHC1->WRAP) /* 0x40470000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ +#define SDHC1_CORE ((SDHC_CORE_Type*) &SDHC1->CORE) /* 0x40471000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB7_BASE 0x40670000UL +#define SCB8_BASE 0x40680000UL +#define SCB9_BASE 0x40690000UL +#define SCB10_BASE 0x406A0000UL +#define SCB11_BASE 0x406B0000UL +#define SCB12_BASE 0x406C0000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ +#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40670000 */ +#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40680000 */ +#define SCB9 ((CySCB_Type*) SCB9_BASE) /* 0x40690000 */ +#define SCB10 ((CySCB_Type*) SCB10_BASE) /* 0x406A0000 */ +#define SCB11 ((CySCB_Type*) SCB11_BASE) /* 0x406B0000 */ +#define SCB12 ((CySCB_Type*) SCB12_BASE) /* 0x406C0000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/******************************************************************************* +* PDM +*******************************************************************************/ + +#define PDM0_BASE 0x40A00000UL +#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x40A00000 */ + +/******************************************************************************* +* I2S +*******************************************************************************/ + +#define I2S0_BASE 0x40A10000UL +#define I2S1_BASE 0x40A11000UL +#define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x40A10000 */ +#define I2S1 ((I2S_Type*) I2S1_BASE) /* 0x40A11000 */ + +/** \} CY8C6248FNI-S2D43 */ + +#endif /* _CY8C6248FNI_S2D43_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624aazi_d14.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624aazi_d14.h new file mode 100644 index 0000000000..021da93fb9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624aazi_d14.h @@ -0,0 +1,1316 @@ +/***************************************************************************//** +* \file cy8c624aazi_d14.h +* +* \brief +* CY8C624AAZI-D14 device header +* +* \note +* Generator version: 1.5.0.1274 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C624AAZI_D14_H_ +#define _CY8C624AAZI_D14_H_ + +/** +* \addtogroup group_device CY8C624AAZI-D14 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + /* ARM Cortex-M0+ Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C624AAZI-D14 User Interrupt Numbers */ + NvicMux0_IRQn = 0, /*!< 0 [DeepSleep] CPU User Interrupt #0 */ + NvicMux1_IRQn = 1, /*!< 1 [DeepSleep] CPU User Interrupt #1 */ + NvicMux2_IRQn = 2, /*!< 2 [DeepSleep] CPU User Interrupt #2 */ + NvicMux3_IRQn = 3, /*!< 3 [DeepSleep] CPU User Interrupt #3 */ + NvicMux4_IRQn = 4, /*!< 4 [DeepSleep] CPU User Interrupt #4 */ + NvicMux5_IRQn = 5, /*!< 5 [DeepSleep] CPU User Interrupt #5 */ + NvicMux6_IRQn = 6, /*!< 6 [DeepSleep] CPU User Interrupt #6 */ + NvicMux7_IRQn = 7, /*!< 7 [DeepSleep] CPU User Interrupt #7 */ + /* CY8C624AAZI-D14 Internal SW Interrupt Numbers */ + Internal0_IRQn = 8, /*!< 8 [Active] Internal SW Interrupt #0 */ + Internal1_IRQn = 9, /*!< 9 [Active] Internal SW Interrupt #1 */ + Internal2_IRQn = 10, /*!< 10 [Active] Internal SW Interrupt #2 */ + Internal3_IRQn = 11, /*!< 11 [Active] Internal SW Interrupt #3 */ + Internal4_IRQn = 12, /*!< 12 [Active] Internal SW Interrupt #4 */ + Internal5_IRQn = 13, /*!< 13 [Active] Internal SW Interrupt #5 */ + Internal6_IRQn = 14, /*!< 14 [Active] Internal SW Interrupt #6 */ + Internal7_IRQn = 15, /*!< 15 [Active] Internal SW Interrupt #7 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#else + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C624AAZI-D14 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#endif +} IRQn_Type; + + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* CY8C624AAZI-D14 interrupts that can be routed to the CM0+ NVIC */ +typedef enum { + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + disconnected_IRQn =1023 /*!< 1023 Disconnected */ +} cy_en_intr_t; + +#endif + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */ +#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ + +#else + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 1 /*!< CM0P present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + +#endif + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00100000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00200000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPROFILE 1u +#define CY_IP_MXPROFILE_INSTANCES 1u +#define CY_IP_MXPROFILE_VERSION 1u + +#include "psoc6_02_config.h" +#include "gpio_psoc6_02_128_tqfp.h" + +#define CY_DEVICE_PSOC6A2M +#define CY_SILICON_ID 0xE40A1102UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40004140 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR10_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU6_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_DMAC_CH3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_PROFILE ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_SDHC1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB8 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB9 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB10 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB11 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB12 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ +#define PERI_MS_PPU_FX_PDM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[226]) /* 0x40014080 */ +#define PERI_MS_PPU_FX_I2S0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[227]) /* 0x400140C0 */ +#define PERI_MS_PPU_FX_I2S1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[228]) /* 0x40014100 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU6_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[0]) /* 0x40235A00 */ +#define PROT_MPU6_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[1]) /* 0x40235A20 */ +#define PROT_MPU6_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[2]) /* 0x40235A40 */ +#define PROT_MPU6_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[3]) /* 0x40235A60 */ +#define PROT_MPU6_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[4]) /* 0x40235A80 */ +#define PROT_MPU6_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[5]) /* 0x40235AA0 */ +#define PROT_MPU6_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[6]) /* 0x40235AC0 */ +#define PROT_MPU6_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[7]) /* 0x40235AE0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ +#define DMAC_CH2 ((DMAC_CH_Type*) &DMAC->CH[2]) /* 0x402A1200 */ +#define DMAC_CH3 ((DMAC_CH_Type*) &DMAC->CH[3]) /* 0x402A1300 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* PROFILE +*******************************************************************************/ + +#define PROFILE_BASE 0x402D0000UL +#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */ +#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */ +#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */ +#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */ +#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */ +#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */ +#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */ +#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */ +#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */ +#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */ +#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */ +#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ +#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */ +#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */ +#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */ +#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */ +#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */ +#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */ +#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */ +#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */ +#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */ +#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */ +#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */ +#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */ +#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */ +#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */ +#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */ +#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ +#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC1_BASE 0x40470000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC1 ((SDHC_Type*) SDHC1_BASE) /* 0x40470000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC1_WRAP ((SDHC_WRAP_Type*) &SDHC1->WRAP) /* 0x40470000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ +#define SDHC1_CORE ((SDHC_CORE_Type*) &SDHC1->CORE) /* 0x40471000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB7_BASE 0x40670000UL +#define SCB8_BASE 0x40680000UL +#define SCB9_BASE 0x40690000UL +#define SCB10_BASE 0x406A0000UL +#define SCB11_BASE 0x406B0000UL +#define SCB12_BASE 0x406C0000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ +#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40670000 */ +#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40680000 */ +#define SCB9 ((CySCB_Type*) SCB9_BASE) /* 0x40690000 */ +#define SCB10 ((CySCB_Type*) SCB10_BASE) /* 0x406A0000 */ +#define SCB11 ((CySCB_Type*) SCB11_BASE) /* 0x406B0000 */ +#define SCB12 ((CySCB_Type*) SCB12_BASE) /* 0x406C0000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/******************************************************************************* +* PDM +*******************************************************************************/ + +#define PDM0_BASE 0x40A00000UL +#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x40A00000 */ + +/******************************************************************************* +* I2S +*******************************************************************************/ + +#define I2S0_BASE 0x40A10000UL +#define I2S1_BASE 0x40A11000UL +#define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x40A10000 */ +#define I2S1 ((I2S_Type*) I2S1_BASE) /* 0x40A11000 */ + +/** \} CY8C624AAZI-D14 */ + +#endif /* _CY8C624AAZI_D14_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624aazi_d44.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624aazi_d44.h index 92bc2db07d..2c66035b2f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624aazi_d44.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624aazi_d44.h @@ -5,7 +5,7 @@ * CY8C624AAZI-D44 device header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -553,7 +553,7 @@ typedef enum { #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u -#define CY_IP_MXS40PASS_SAR_INSTANCES 16u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u #define CY_IP_MXS40IOSS 1u #define CY_IP_MXS40IOSS_INSTANCES 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624aazi_s2d14.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624aazi_s2d14.h new file mode 100644 index 0000000000..b1b13efade --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624aazi_s2d14.h @@ -0,0 +1,1316 @@ +/***************************************************************************//** +* \file cy8c624aazi_s2d14.h +* +* \brief +* CY8C624AAZI-S2D14 device header +* +* \note +* Generator version: 1.5.0.1274 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C624AAZI_S2D14_H_ +#define _CY8C624AAZI_S2D14_H_ + +/** +* \addtogroup group_device CY8C624AAZI-S2D14 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + /* ARM Cortex-M0+ Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C624AAZI-S2D14 User Interrupt Numbers */ + NvicMux0_IRQn = 0, /*!< 0 [DeepSleep] CPU User Interrupt #0 */ + NvicMux1_IRQn = 1, /*!< 1 [DeepSleep] CPU User Interrupt #1 */ + NvicMux2_IRQn = 2, /*!< 2 [DeepSleep] CPU User Interrupt #2 */ + NvicMux3_IRQn = 3, /*!< 3 [DeepSleep] CPU User Interrupt #3 */ + NvicMux4_IRQn = 4, /*!< 4 [DeepSleep] CPU User Interrupt #4 */ + NvicMux5_IRQn = 5, /*!< 5 [DeepSleep] CPU User Interrupt #5 */ + NvicMux6_IRQn = 6, /*!< 6 [DeepSleep] CPU User Interrupt #6 */ + NvicMux7_IRQn = 7, /*!< 7 [DeepSleep] CPU User Interrupt #7 */ + /* CY8C624AAZI-S2D14 Internal SW Interrupt Numbers */ + Internal0_IRQn = 8, /*!< 8 [Active] Internal SW Interrupt #0 */ + Internal1_IRQn = 9, /*!< 9 [Active] Internal SW Interrupt #1 */ + Internal2_IRQn = 10, /*!< 10 [Active] Internal SW Interrupt #2 */ + Internal3_IRQn = 11, /*!< 11 [Active] Internal SW Interrupt #3 */ + Internal4_IRQn = 12, /*!< 12 [Active] Internal SW Interrupt #4 */ + Internal5_IRQn = 13, /*!< 13 [Active] Internal SW Interrupt #5 */ + Internal6_IRQn = 14, /*!< 14 [Active] Internal SW Interrupt #6 */ + Internal7_IRQn = 15, /*!< 15 [Active] Internal SW Interrupt #7 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#else + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C624AAZI-S2D14 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#endif +} IRQn_Type; + + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* CY8C624AAZI-S2D14 interrupts that can be routed to the CM0+ NVIC */ +typedef enum { + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + disconnected_IRQn =1023 /*!< 1023 Disconnected */ +} cy_en_intr_t; + +#endif + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */ +#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ + +#else + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 1 /*!< CM0P present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + +#endif + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00100000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00200000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPROFILE 1u +#define CY_IP_MXPROFILE_INSTANCES 1u +#define CY_IP_MXPROFILE_VERSION 1u + +#include "psoc6_02_config.h" +#include "gpio_psoc6_02_128_tqfp.h" + +#define CY_DEVICE_PSOC6A2M +#define CY_SILICON_ID 0xE4521102UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40004140 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR10_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU6_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_DMAC_CH3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_PROFILE ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_SDHC1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB8 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB9 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB10 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB11 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB12 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ +#define PERI_MS_PPU_FX_PDM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[226]) /* 0x40014080 */ +#define PERI_MS_PPU_FX_I2S0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[227]) /* 0x400140C0 */ +#define PERI_MS_PPU_FX_I2S1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[228]) /* 0x40014100 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU6_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[0]) /* 0x40235A00 */ +#define PROT_MPU6_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[1]) /* 0x40235A20 */ +#define PROT_MPU6_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[2]) /* 0x40235A40 */ +#define PROT_MPU6_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[3]) /* 0x40235A60 */ +#define PROT_MPU6_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[4]) /* 0x40235A80 */ +#define PROT_MPU6_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[5]) /* 0x40235AA0 */ +#define PROT_MPU6_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[6]) /* 0x40235AC0 */ +#define PROT_MPU6_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[7]) /* 0x40235AE0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ +#define DMAC_CH2 ((DMAC_CH_Type*) &DMAC->CH[2]) /* 0x402A1200 */ +#define DMAC_CH3 ((DMAC_CH_Type*) &DMAC->CH[3]) /* 0x402A1300 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* PROFILE +*******************************************************************************/ + +#define PROFILE_BASE 0x402D0000UL +#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */ +#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */ +#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */ +#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */ +#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */ +#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */ +#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */ +#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */ +#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */ +#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */ +#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */ +#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ +#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */ +#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */ +#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */ +#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */ +#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */ +#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */ +#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */ +#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */ +#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */ +#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */ +#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */ +#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */ +#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */ +#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */ +#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */ +#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ +#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC1_BASE 0x40470000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC1 ((SDHC_Type*) SDHC1_BASE) /* 0x40470000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC1_WRAP ((SDHC_WRAP_Type*) &SDHC1->WRAP) /* 0x40470000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ +#define SDHC1_CORE ((SDHC_CORE_Type*) &SDHC1->CORE) /* 0x40471000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB7_BASE 0x40670000UL +#define SCB8_BASE 0x40680000UL +#define SCB9_BASE 0x40690000UL +#define SCB10_BASE 0x406A0000UL +#define SCB11_BASE 0x406B0000UL +#define SCB12_BASE 0x406C0000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ +#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40670000 */ +#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40680000 */ +#define SCB9 ((CySCB_Type*) SCB9_BASE) /* 0x40690000 */ +#define SCB10 ((CySCB_Type*) SCB10_BASE) /* 0x406A0000 */ +#define SCB11 ((CySCB_Type*) SCB11_BASE) /* 0x406B0000 */ +#define SCB12 ((CySCB_Type*) SCB12_BASE) /* 0x406C0000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/******************************************************************************* +* PDM +*******************************************************************************/ + +#define PDM0_BASE 0x40A00000UL +#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x40A00000 */ + +/******************************************************************************* +* I2S +*******************************************************************************/ + +#define I2S0_BASE 0x40A10000UL +#define I2S1_BASE 0x40A11000UL +#define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x40A10000 */ +#define I2S1 ((I2S_Type*) I2S1_BASE) /* 0x40A11000 */ + +/** \} CY8C624AAZI-S2D14 */ + +#endif /* _CY8C624AAZI_S2D14_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624aazi_s2d44.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624aazi_s2d44.h new file mode 100644 index 0000000000..233b1da31a --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624aazi_s2d44.h @@ -0,0 +1,1326 @@ +/***************************************************************************//** +* \file cy8c624aazi_s2d44.h +* +* \brief +* CY8C624AAZI-S2D44 device header +* +* \note +* Generator version: 1.5.0.1274 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C624AAZI_S2D44_H_ +#define _CY8C624AAZI_S2D44_H_ + +/** +* \addtogroup group_device CY8C624AAZI-S2D44 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + /* ARM Cortex-M0+ Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C624AAZI-S2D44 User Interrupt Numbers */ + NvicMux0_IRQn = 0, /*!< 0 [DeepSleep] CPU User Interrupt #0 */ + NvicMux1_IRQn = 1, /*!< 1 [DeepSleep] CPU User Interrupt #1 */ + NvicMux2_IRQn = 2, /*!< 2 [DeepSleep] CPU User Interrupt #2 */ + NvicMux3_IRQn = 3, /*!< 3 [DeepSleep] CPU User Interrupt #3 */ + NvicMux4_IRQn = 4, /*!< 4 [DeepSleep] CPU User Interrupt #4 */ + NvicMux5_IRQn = 5, /*!< 5 [DeepSleep] CPU User Interrupt #5 */ + NvicMux6_IRQn = 6, /*!< 6 [DeepSleep] CPU User Interrupt #6 */ + NvicMux7_IRQn = 7, /*!< 7 [DeepSleep] CPU User Interrupt #7 */ + /* CY8C624AAZI-S2D44 Internal SW Interrupt Numbers */ + Internal0_IRQn = 8, /*!< 8 [Active] Internal SW Interrupt #0 */ + Internal1_IRQn = 9, /*!< 9 [Active] Internal SW Interrupt #1 */ + Internal2_IRQn = 10, /*!< 10 [Active] Internal SW Interrupt #2 */ + Internal3_IRQn = 11, /*!< 11 [Active] Internal SW Interrupt #3 */ + Internal4_IRQn = 12, /*!< 12 [Active] Internal SW Interrupt #4 */ + Internal5_IRQn = 13, /*!< 13 [Active] Internal SW Interrupt #5 */ + Internal6_IRQn = 14, /*!< 14 [Active] Internal SW Interrupt #6 */ + Internal7_IRQn = 15, /*!< 15 [Active] Internal SW Interrupt #7 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#else + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C624AAZI-S2D44 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#endif +} IRQn_Type; + + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* CY8C624AAZI-S2D44 interrupts that can be routed to the CM0+ NVIC */ +typedef enum { + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + disconnected_IRQn =1023 /*!< 1023 Disconnected */ +} cy_en_intr_t; + +#endif + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */ +#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ + +#else + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 1 /*!< CM0P present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + +#endif + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00100000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00200000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 2u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPROFILE 1u +#define CY_IP_MXPROFILE_INSTANCES 1u +#define CY_IP_MXPROFILE_VERSION 1u + +#include "psoc6_02_config.h" +#include "gpio_psoc6_02_128_tqfp.h" + +#define CY_DEVICE_PSOC6A2M +#define CY_SILICON_ID 0xE4541102UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40004140 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR10_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU6_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_DMAC_CH3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_PROFILE ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_SDHC1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB8 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB9 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB10 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB11 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB12 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ +#define PERI_MS_PPU_FX_PDM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[226]) /* 0x40014080 */ +#define PERI_MS_PPU_FX_I2S0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[227]) /* 0x400140C0 */ +#define PERI_MS_PPU_FX_I2S1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[228]) /* 0x40014100 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40100000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40100000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU6_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[0]) /* 0x40235A00 */ +#define PROT_MPU6_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[1]) /* 0x40235A20 */ +#define PROT_MPU6_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[2]) /* 0x40235A40 */ +#define PROT_MPU6_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[3]) /* 0x40235A60 */ +#define PROT_MPU6_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[4]) /* 0x40235A80 */ +#define PROT_MPU6_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[5]) /* 0x40235AA0 */ +#define PROT_MPU6_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[6]) /* 0x40235AC0 */ +#define PROT_MPU6_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[7]) /* 0x40235AE0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ +#define DMAC_CH2 ((DMAC_CH_Type*) &DMAC->CH[2]) /* 0x402A1200 */ +#define DMAC_CH3 ((DMAC_CH_Type*) &DMAC->CH[3]) /* 0x402A1300 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* PROFILE +*******************************************************************************/ + +#define PROFILE_BASE 0x402D0000UL +#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */ +#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */ +#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */ +#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */ +#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */ +#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */ +#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */ +#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */ +#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */ +#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */ +#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */ +#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ +#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */ +#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */ +#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */ +#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */ +#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */ +#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */ +#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */ +#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */ +#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */ +#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */ +#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */ +#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */ +#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */ +#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */ +#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */ +#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ +#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC1_BASE 0x40470000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC1 ((SDHC_Type*) SDHC1_BASE) /* 0x40470000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC1_WRAP ((SDHC_WRAP_Type*) &SDHC1->WRAP) /* 0x40470000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ +#define SDHC1_CORE ((SDHC_CORE_Type*) &SDHC1->CORE) /* 0x40471000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB7_BASE 0x40670000UL +#define SCB8_BASE 0x40680000UL +#define SCB9_BASE 0x40690000UL +#define SCB10_BASE 0x406A0000UL +#define SCB11_BASE 0x406B0000UL +#define SCB12_BASE 0x406C0000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ +#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40670000 */ +#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40680000 */ +#define SCB9 ((CySCB_Type*) SCB9_BASE) /* 0x40690000 */ +#define SCB10 ((CySCB_Type*) SCB10_BASE) /* 0x406A0000 */ +#define SCB11 ((CySCB_Type*) SCB11_BASE) /* 0x406B0000 */ +#define SCB12 ((CySCB_Type*) SCB12_BASE) /* 0x406C0000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/******************************************************************************* +* PDM +*******************************************************************************/ + +#define PDM0_BASE 0x40A00000UL +#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x40A00000 */ + +/******************************************************************************* +* I2S +*******************************************************************************/ + +#define I2S0_BASE 0x40A10000UL +#define I2S1_BASE 0x40A11000UL +#define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x40A10000 */ +#define I2S1 ((I2S_Type*) I2S1_BASE) /* 0x40A11000 */ + +/** \} CY8C624AAZI-S2D44 */ + +#endif /* _CY8C624AAZI_S2D44_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_d04.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_d04.h new file mode 100644 index 0000000000..0ad860910c --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_d04.h @@ -0,0 +1,1316 @@ +/***************************************************************************//** +* \file cy8c624abzi_d04.h +* +* \brief +* CY8C624ABZI-D04 device header +* +* \note +* Generator version: 1.5.0.1274 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C624ABZI_D04_H_ +#define _CY8C624ABZI_D04_H_ + +/** +* \addtogroup group_device CY8C624ABZI-D04 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + /* ARM Cortex-M0+ Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C624ABZI-D04 User Interrupt Numbers */ + NvicMux0_IRQn = 0, /*!< 0 [DeepSleep] CPU User Interrupt #0 */ + NvicMux1_IRQn = 1, /*!< 1 [DeepSleep] CPU User Interrupt #1 */ + NvicMux2_IRQn = 2, /*!< 2 [DeepSleep] CPU User Interrupt #2 */ + NvicMux3_IRQn = 3, /*!< 3 [DeepSleep] CPU User Interrupt #3 */ + NvicMux4_IRQn = 4, /*!< 4 [DeepSleep] CPU User Interrupt #4 */ + NvicMux5_IRQn = 5, /*!< 5 [DeepSleep] CPU User Interrupt #5 */ + NvicMux6_IRQn = 6, /*!< 6 [DeepSleep] CPU User Interrupt #6 */ + NvicMux7_IRQn = 7, /*!< 7 [DeepSleep] CPU User Interrupt #7 */ + /* CY8C624ABZI-D04 Internal SW Interrupt Numbers */ + Internal0_IRQn = 8, /*!< 8 [Active] Internal SW Interrupt #0 */ + Internal1_IRQn = 9, /*!< 9 [Active] Internal SW Interrupt #1 */ + Internal2_IRQn = 10, /*!< 10 [Active] Internal SW Interrupt #2 */ + Internal3_IRQn = 11, /*!< 11 [Active] Internal SW Interrupt #3 */ + Internal4_IRQn = 12, /*!< 12 [Active] Internal SW Interrupt #4 */ + Internal5_IRQn = 13, /*!< 13 [Active] Internal SW Interrupt #5 */ + Internal6_IRQn = 14, /*!< 14 [Active] Internal SW Interrupt #6 */ + Internal7_IRQn = 15, /*!< 15 [Active] Internal SW Interrupt #7 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#else + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C624ABZI-D04 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#endif +} IRQn_Type; + + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* CY8C624ABZI-D04 interrupts that can be routed to the CM0+ NVIC */ +typedef enum { + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + disconnected_IRQn =1023 /*!< 1023 Disconnected */ +} cy_en_intr_t; + +#endif + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */ +#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ + +#else + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 1 /*!< CM0P present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + +#endif + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00100000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00200000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPROFILE 1u +#define CY_IP_MXPROFILE_INSTANCES 1u +#define CY_IP_MXPROFILE_VERSION 1u + +#include "psoc6_02_config.h" +#include "gpio_psoc6_02_124_bga.h" + +#define CY_DEVICE_PSOC6A2M +#define CY_SILICON_ID 0xE4001102UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40004140 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR10_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU6_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_DMAC_CH3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_PROFILE ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_SDHC1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB8 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB9 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB10 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB11 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB12 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ +#define PERI_MS_PPU_FX_PDM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[226]) /* 0x40014080 */ +#define PERI_MS_PPU_FX_I2S0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[227]) /* 0x400140C0 */ +#define PERI_MS_PPU_FX_I2S1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[228]) /* 0x40014100 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU6_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[0]) /* 0x40235A00 */ +#define PROT_MPU6_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[1]) /* 0x40235A20 */ +#define PROT_MPU6_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[2]) /* 0x40235A40 */ +#define PROT_MPU6_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[3]) /* 0x40235A60 */ +#define PROT_MPU6_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[4]) /* 0x40235A80 */ +#define PROT_MPU6_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[5]) /* 0x40235AA0 */ +#define PROT_MPU6_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[6]) /* 0x40235AC0 */ +#define PROT_MPU6_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[7]) /* 0x40235AE0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ +#define DMAC_CH2 ((DMAC_CH_Type*) &DMAC->CH[2]) /* 0x402A1200 */ +#define DMAC_CH3 ((DMAC_CH_Type*) &DMAC->CH[3]) /* 0x402A1300 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* PROFILE +*******************************************************************************/ + +#define PROFILE_BASE 0x402D0000UL +#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */ +#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */ +#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */ +#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */ +#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */ +#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */ +#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */ +#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */ +#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */ +#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */ +#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */ +#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ +#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */ +#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */ +#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */ +#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */ +#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */ +#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */ +#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */ +#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */ +#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */ +#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */ +#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */ +#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */ +#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */ +#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */ +#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */ +#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ +#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC1_BASE 0x40470000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC1 ((SDHC_Type*) SDHC1_BASE) /* 0x40470000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC1_WRAP ((SDHC_WRAP_Type*) &SDHC1->WRAP) /* 0x40470000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ +#define SDHC1_CORE ((SDHC_CORE_Type*) &SDHC1->CORE) /* 0x40471000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB7_BASE 0x40670000UL +#define SCB8_BASE 0x40680000UL +#define SCB9_BASE 0x40690000UL +#define SCB10_BASE 0x406A0000UL +#define SCB11_BASE 0x406B0000UL +#define SCB12_BASE 0x406C0000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ +#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40670000 */ +#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40680000 */ +#define SCB9 ((CySCB_Type*) SCB9_BASE) /* 0x40690000 */ +#define SCB10 ((CySCB_Type*) SCB10_BASE) /* 0x406A0000 */ +#define SCB11 ((CySCB_Type*) SCB11_BASE) /* 0x406B0000 */ +#define SCB12 ((CySCB_Type*) SCB12_BASE) /* 0x406C0000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/******************************************************************************* +* PDM +*******************************************************************************/ + +#define PDM0_BASE 0x40A00000UL +#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x40A00000 */ + +/******************************************************************************* +* I2S +*******************************************************************************/ + +#define I2S0_BASE 0x40A10000UL +#define I2S1_BASE 0x40A11000UL +#define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x40A10000 */ +#define I2S1 ((I2S_Type*) I2S1_BASE) /* 0x40A11000 */ + +/** \} CY8C624ABZI-D04 */ + +#endif /* _CY8C624ABZI_D04_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_d14.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_d14.h new file mode 100644 index 0000000000..7609ab5a52 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_d14.h @@ -0,0 +1,1316 @@ +/***************************************************************************//** +* \file cy8c624abzi_d14.h +* +* \brief +* CY8C624ABZI-D14 device header +* +* \note +* Generator version: 1.5.0.1274 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C624ABZI_D14_H_ +#define _CY8C624ABZI_D14_H_ + +/** +* \addtogroup group_device CY8C624ABZI-D14 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + /* ARM Cortex-M0+ Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C624ABZI-D14 User Interrupt Numbers */ + NvicMux0_IRQn = 0, /*!< 0 [DeepSleep] CPU User Interrupt #0 */ + NvicMux1_IRQn = 1, /*!< 1 [DeepSleep] CPU User Interrupt #1 */ + NvicMux2_IRQn = 2, /*!< 2 [DeepSleep] CPU User Interrupt #2 */ + NvicMux3_IRQn = 3, /*!< 3 [DeepSleep] CPU User Interrupt #3 */ + NvicMux4_IRQn = 4, /*!< 4 [DeepSleep] CPU User Interrupt #4 */ + NvicMux5_IRQn = 5, /*!< 5 [DeepSleep] CPU User Interrupt #5 */ + NvicMux6_IRQn = 6, /*!< 6 [DeepSleep] CPU User Interrupt #6 */ + NvicMux7_IRQn = 7, /*!< 7 [DeepSleep] CPU User Interrupt #7 */ + /* CY8C624ABZI-D14 Internal SW Interrupt Numbers */ + Internal0_IRQn = 8, /*!< 8 [Active] Internal SW Interrupt #0 */ + Internal1_IRQn = 9, /*!< 9 [Active] Internal SW Interrupt #1 */ + Internal2_IRQn = 10, /*!< 10 [Active] Internal SW Interrupt #2 */ + Internal3_IRQn = 11, /*!< 11 [Active] Internal SW Interrupt #3 */ + Internal4_IRQn = 12, /*!< 12 [Active] Internal SW Interrupt #4 */ + Internal5_IRQn = 13, /*!< 13 [Active] Internal SW Interrupt #5 */ + Internal6_IRQn = 14, /*!< 14 [Active] Internal SW Interrupt #6 */ + Internal7_IRQn = 15, /*!< 15 [Active] Internal SW Interrupt #7 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#else + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C624ABZI-D14 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#endif +} IRQn_Type; + + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* CY8C624ABZI-D14 interrupts that can be routed to the CM0+ NVIC */ +typedef enum { + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + disconnected_IRQn =1023 /*!< 1023 Disconnected */ +} cy_en_intr_t; + +#endif + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */ +#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ + +#else + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 1 /*!< CM0P present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + +#endif + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00100000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00200000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPROFILE 1u +#define CY_IP_MXPROFILE_INSTANCES 1u +#define CY_IP_MXPROFILE_VERSION 1u + +#include "psoc6_02_config.h" +#include "gpio_psoc6_02_124_bga.h" + +#define CY_DEVICE_PSOC6A2M +#define CY_SILICON_ID 0xE4011102UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40004140 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR10_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU6_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_DMAC_CH3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_PROFILE ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_SDHC1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB8 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB9 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB10 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB11 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB12 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ +#define PERI_MS_PPU_FX_PDM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[226]) /* 0x40014080 */ +#define PERI_MS_PPU_FX_I2S0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[227]) /* 0x400140C0 */ +#define PERI_MS_PPU_FX_I2S1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[228]) /* 0x40014100 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU6_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[0]) /* 0x40235A00 */ +#define PROT_MPU6_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[1]) /* 0x40235A20 */ +#define PROT_MPU6_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[2]) /* 0x40235A40 */ +#define PROT_MPU6_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[3]) /* 0x40235A60 */ +#define PROT_MPU6_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[4]) /* 0x40235A80 */ +#define PROT_MPU6_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[5]) /* 0x40235AA0 */ +#define PROT_MPU6_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[6]) /* 0x40235AC0 */ +#define PROT_MPU6_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[7]) /* 0x40235AE0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ +#define DMAC_CH2 ((DMAC_CH_Type*) &DMAC->CH[2]) /* 0x402A1200 */ +#define DMAC_CH3 ((DMAC_CH_Type*) &DMAC->CH[3]) /* 0x402A1300 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* PROFILE +*******************************************************************************/ + +#define PROFILE_BASE 0x402D0000UL +#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */ +#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */ +#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */ +#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */ +#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */ +#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */ +#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */ +#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */ +#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */ +#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */ +#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */ +#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ +#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */ +#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */ +#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */ +#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */ +#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */ +#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */ +#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */ +#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */ +#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */ +#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */ +#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */ +#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */ +#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */ +#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */ +#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */ +#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ +#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC1_BASE 0x40470000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC1 ((SDHC_Type*) SDHC1_BASE) /* 0x40470000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC1_WRAP ((SDHC_WRAP_Type*) &SDHC1->WRAP) /* 0x40470000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ +#define SDHC1_CORE ((SDHC_CORE_Type*) &SDHC1->CORE) /* 0x40471000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB7_BASE 0x40670000UL +#define SCB8_BASE 0x40680000UL +#define SCB9_BASE 0x40690000UL +#define SCB10_BASE 0x406A0000UL +#define SCB11_BASE 0x406B0000UL +#define SCB12_BASE 0x406C0000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ +#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40670000 */ +#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40680000 */ +#define SCB9 ((CySCB_Type*) SCB9_BASE) /* 0x40690000 */ +#define SCB10 ((CySCB_Type*) SCB10_BASE) /* 0x406A0000 */ +#define SCB11 ((CySCB_Type*) SCB11_BASE) /* 0x406B0000 */ +#define SCB12 ((CySCB_Type*) SCB12_BASE) /* 0x406C0000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/******************************************************************************* +* PDM +*******************************************************************************/ + +#define PDM0_BASE 0x40A00000UL +#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x40A00000 */ + +/******************************************************************************* +* I2S +*******************************************************************************/ + +#define I2S0_BASE 0x40A10000UL +#define I2S1_BASE 0x40A11000UL +#define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x40A10000 */ +#define I2S1 ((I2S_Type*) I2S1_BASE) /* 0x40A11000 */ + +/** \} CY8C624ABZI-D14 */ + +#endif /* _CY8C624ABZI_D14_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_d44.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_d44.h index 078a2ff173..98715efe2f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_d44.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_d44.h @@ -5,7 +5,7 @@ * CY8C624ABZI-D44 device header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -553,7 +553,7 @@ typedef enum { #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u -#define CY_IP_MXS40PASS_SAR_INSTANCES 16u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u #define CY_IP_MXS40IOSS 1u #define CY_IP_MXS40IOSS_INSTANCES 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_s2d04.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_s2d04.h new file mode 100644 index 0000000000..6cc8b75154 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_s2d04.h @@ -0,0 +1,1316 @@ +/***************************************************************************//** +* \file cy8c624abzi_s2d04.h +* +* \brief +* CY8C624ABZI-S2D04 device header +* +* \note +* Generator version: 1.5.0.1274 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C624ABZI_S2D04_H_ +#define _CY8C624ABZI_S2D04_H_ + +/** +* \addtogroup group_device CY8C624ABZI-S2D04 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + /* ARM Cortex-M0+ Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C624ABZI-S2D04 User Interrupt Numbers */ + NvicMux0_IRQn = 0, /*!< 0 [DeepSleep] CPU User Interrupt #0 */ + NvicMux1_IRQn = 1, /*!< 1 [DeepSleep] CPU User Interrupt #1 */ + NvicMux2_IRQn = 2, /*!< 2 [DeepSleep] CPU User Interrupt #2 */ + NvicMux3_IRQn = 3, /*!< 3 [DeepSleep] CPU User Interrupt #3 */ + NvicMux4_IRQn = 4, /*!< 4 [DeepSleep] CPU User Interrupt #4 */ + NvicMux5_IRQn = 5, /*!< 5 [DeepSleep] CPU User Interrupt #5 */ + NvicMux6_IRQn = 6, /*!< 6 [DeepSleep] CPU User Interrupt #6 */ + NvicMux7_IRQn = 7, /*!< 7 [DeepSleep] CPU User Interrupt #7 */ + /* CY8C624ABZI-S2D04 Internal SW Interrupt Numbers */ + Internal0_IRQn = 8, /*!< 8 [Active] Internal SW Interrupt #0 */ + Internal1_IRQn = 9, /*!< 9 [Active] Internal SW Interrupt #1 */ + Internal2_IRQn = 10, /*!< 10 [Active] Internal SW Interrupt #2 */ + Internal3_IRQn = 11, /*!< 11 [Active] Internal SW Interrupt #3 */ + Internal4_IRQn = 12, /*!< 12 [Active] Internal SW Interrupt #4 */ + Internal5_IRQn = 13, /*!< 13 [Active] Internal SW Interrupt #5 */ + Internal6_IRQn = 14, /*!< 14 [Active] Internal SW Interrupt #6 */ + Internal7_IRQn = 15, /*!< 15 [Active] Internal SW Interrupt #7 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#else + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C624ABZI-S2D04 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#endif +} IRQn_Type; + + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* CY8C624ABZI-S2D04 interrupts that can be routed to the CM0+ NVIC */ +typedef enum { + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + disconnected_IRQn =1023 /*!< 1023 Disconnected */ +} cy_en_intr_t; + +#endif + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */ +#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ + +#else + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 1 /*!< CM0P present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + +#endif + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00100000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00200000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPROFILE 1u +#define CY_IP_MXPROFILE_INSTANCES 1u +#define CY_IP_MXPROFILE_VERSION 1u + +#include "psoc6_02_config.h" +#include "gpio_psoc6_02_124_bga.h" + +#define CY_DEVICE_PSOC6A2M +#define CY_SILICON_ID 0xE4501102UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40004140 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR10_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU6_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_DMAC_CH3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_PROFILE ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_SDHC1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB8 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB9 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB10 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB11 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB12 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ +#define PERI_MS_PPU_FX_PDM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[226]) /* 0x40014080 */ +#define PERI_MS_PPU_FX_I2S0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[227]) /* 0x400140C0 */ +#define PERI_MS_PPU_FX_I2S1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[228]) /* 0x40014100 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU6_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[0]) /* 0x40235A00 */ +#define PROT_MPU6_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[1]) /* 0x40235A20 */ +#define PROT_MPU6_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[2]) /* 0x40235A40 */ +#define PROT_MPU6_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[3]) /* 0x40235A60 */ +#define PROT_MPU6_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[4]) /* 0x40235A80 */ +#define PROT_MPU6_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[5]) /* 0x40235AA0 */ +#define PROT_MPU6_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[6]) /* 0x40235AC0 */ +#define PROT_MPU6_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[7]) /* 0x40235AE0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ +#define DMAC_CH2 ((DMAC_CH_Type*) &DMAC->CH[2]) /* 0x402A1200 */ +#define DMAC_CH3 ((DMAC_CH_Type*) &DMAC->CH[3]) /* 0x402A1300 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* PROFILE +*******************************************************************************/ + +#define PROFILE_BASE 0x402D0000UL +#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */ +#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */ +#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */ +#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */ +#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */ +#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */ +#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */ +#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */ +#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */ +#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */ +#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */ +#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ +#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */ +#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */ +#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */ +#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */ +#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */ +#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */ +#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */ +#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */ +#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */ +#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */ +#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */ +#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */ +#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */ +#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */ +#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */ +#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ +#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC1_BASE 0x40470000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC1 ((SDHC_Type*) SDHC1_BASE) /* 0x40470000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC1_WRAP ((SDHC_WRAP_Type*) &SDHC1->WRAP) /* 0x40470000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ +#define SDHC1_CORE ((SDHC_CORE_Type*) &SDHC1->CORE) /* 0x40471000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB7_BASE 0x40670000UL +#define SCB8_BASE 0x40680000UL +#define SCB9_BASE 0x40690000UL +#define SCB10_BASE 0x406A0000UL +#define SCB11_BASE 0x406B0000UL +#define SCB12_BASE 0x406C0000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ +#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40670000 */ +#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40680000 */ +#define SCB9 ((CySCB_Type*) SCB9_BASE) /* 0x40690000 */ +#define SCB10 ((CySCB_Type*) SCB10_BASE) /* 0x406A0000 */ +#define SCB11 ((CySCB_Type*) SCB11_BASE) /* 0x406B0000 */ +#define SCB12 ((CySCB_Type*) SCB12_BASE) /* 0x406C0000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/******************************************************************************* +* PDM +*******************************************************************************/ + +#define PDM0_BASE 0x40A00000UL +#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x40A00000 */ + +/******************************************************************************* +* I2S +*******************************************************************************/ + +#define I2S0_BASE 0x40A10000UL +#define I2S1_BASE 0x40A11000UL +#define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x40A10000 */ +#define I2S1 ((I2S_Type*) I2S1_BASE) /* 0x40A11000 */ + +/** \} CY8C624ABZI-S2D04 */ + +#endif /* _CY8C624ABZI_S2D04_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_s2d14.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_s2d14.h new file mode 100644 index 0000000000..80a9cda81f --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_s2d14.h @@ -0,0 +1,1316 @@ +/***************************************************************************//** +* \file cy8c624abzi_s2d14.h +* +* \brief +* CY8C624ABZI-S2D14 device header +* +* \note +* Generator version: 1.5.0.1274 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C624ABZI_S2D14_H_ +#define _CY8C624ABZI_S2D14_H_ + +/** +* \addtogroup group_device CY8C624ABZI-S2D14 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + /* ARM Cortex-M0+ Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C624ABZI-S2D14 User Interrupt Numbers */ + NvicMux0_IRQn = 0, /*!< 0 [DeepSleep] CPU User Interrupt #0 */ + NvicMux1_IRQn = 1, /*!< 1 [DeepSleep] CPU User Interrupt #1 */ + NvicMux2_IRQn = 2, /*!< 2 [DeepSleep] CPU User Interrupt #2 */ + NvicMux3_IRQn = 3, /*!< 3 [DeepSleep] CPU User Interrupt #3 */ + NvicMux4_IRQn = 4, /*!< 4 [DeepSleep] CPU User Interrupt #4 */ + NvicMux5_IRQn = 5, /*!< 5 [DeepSleep] CPU User Interrupt #5 */ + NvicMux6_IRQn = 6, /*!< 6 [DeepSleep] CPU User Interrupt #6 */ + NvicMux7_IRQn = 7, /*!< 7 [DeepSleep] CPU User Interrupt #7 */ + /* CY8C624ABZI-S2D14 Internal SW Interrupt Numbers */ + Internal0_IRQn = 8, /*!< 8 [Active] Internal SW Interrupt #0 */ + Internal1_IRQn = 9, /*!< 9 [Active] Internal SW Interrupt #1 */ + Internal2_IRQn = 10, /*!< 10 [Active] Internal SW Interrupt #2 */ + Internal3_IRQn = 11, /*!< 11 [Active] Internal SW Interrupt #3 */ + Internal4_IRQn = 12, /*!< 12 [Active] Internal SW Interrupt #4 */ + Internal5_IRQn = 13, /*!< 13 [Active] Internal SW Interrupt #5 */ + Internal6_IRQn = 14, /*!< 14 [Active] Internal SW Interrupt #6 */ + Internal7_IRQn = 15, /*!< 15 [Active] Internal SW Interrupt #7 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#else + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C624ABZI-S2D14 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#endif +} IRQn_Type; + + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* CY8C624ABZI-S2D14 interrupts that can be routed to the CM0+ NVIC */ +typedef enum { + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + disconnected_IRQn =1023 /*!< 1023 Disconnected */ +} cy_en_intr_t; + +#endif + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */ +#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ + +#else + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 1 /*!< CM0P present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + +#endif + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00100000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00200000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPROFILE 1u +#define CY_IP_MXPROFILE_INSTANCES 1u +#define CY_IP_MXPROFILE_VERSION 1u + +#include "psoc6_02_config.h" +#include "gpio_psoc6_02_124_bga.h" + +#define CY_DEVICE_PSOC6A2M +#define CY_SILICON_ID 0xE4511102UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40004140 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR10_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU6_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_DMAC_CH3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_PROFILE ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_SDHC1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB8 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB9 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB10 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB11 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB12 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ +#define PERI_MS_PPU_FX_PDM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[226]) /* 0x40014080 */ +#define PERI_MS_PPU_FX_I2S0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[227]) /* 0x400140C0 */ +#define PERI_MS_PPU_FX_I2S1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[228]) /* 0x40014100 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU6_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[0]) /* 0x40235A00 */ +#define PROT_MPU6_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[1]) /* 0x40235A20 */ +#define PROT_MPU6_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[2]) /* 0x40235A40 */ +#define PROT_MPU6_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[3]) /* 0x40235A60 */ +#define PROT_MPU6_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[4]) /* 0x40235A80 */ +#define PROT_MPU6_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[5]) /* 0x40235AA0 */ +#define PROT_MPU6_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[6]) /* 0x40235AC0 */ +#define PROT_MPU6_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[7]) /* 0x40235AE0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ +#define DMAC_CH2 ((DMAC_CH_Type*) &DMAC->CH[2]) /* 0x402A1200 */ +#define DMAC_CH3 ((DMAC_CH_Type*) &DMAC->CH[3]) /* 0x402A1300 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* PROFILE +*******************************************************************************/ + +#define PROFILE_BASE 0x402D0000UL +#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */ +#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */ +#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */ +#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */ +#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */ +#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */ +#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */ +#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */ +#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */ +#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */ +#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */ +#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ +#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */ +#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */ +#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */ +#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */ +#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */ +#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */ +#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */ +#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */ +#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */ +#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */ +#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */ +#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */ +#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */ +#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */ +#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */ +#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ +#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC1_BASE 0x40470000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC1 ((SDHC_Type*) SDHC1_BASE) /* 0x40470000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC1_WRAP ((SDHC_WRAP_Type*) &SDHC1->WRAP) /* 0x40470000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ +#define SDHC1_CORE ((SDHC_CORE_Type*) &SDHC1->CORE) /* 0x40471000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB7_BASE 0x40670000UL +#define SCB8_BASE 0x40680000UL +#define SCB9_BASE 0x40690000UL +#define SCB10_BASE 0x406A0000UL +#define SCB11_BASE 0x406B0000UL +#define SCB12_BASE 0x406C0000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ +#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40670000 */ +#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40680000 */ +#define SCB9 ((CySCB_Type*) SCB9_BASE) /* 0x40690000 */ +#define SCB10 ((CySCB_Type*) SCB10_BASE) /* 0x406A0000 */ +#define SCB11 ((CySCB_Type*) SCB11_BASE) /* 0x406B0000 */ +#define SCB12 ((CySCB_Type*) SCB12_BASE) /* 0x406C0000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/******************************************************************************* +* PDM +*******************************************************************************/ + +#define PDM0_BASE 0x40A00000UL +#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x40A00000 */ + +/******************************************************************************* +* I2S +*******************************************************************************/ + +#define I2S0_BASE 0x40A10000UL +#define I2S1_BASE 0x40A11000UL +#define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x40A10000 */ +#define I2S1 ((I2S_Type*) I2S1_BASE) /* 0x40A11000 */ + +/** \} CY8C624ABZI-S2D14 */ + +#endif /* _CY8C624ABZI_S2D14_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_s2d44.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_s2d44.h new file mode 100644 index 0000000000..39b74fe266 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_s2d44.h @@ -0,0 +1,1326 @@ +/***************************************************************************//** +* \file cy8c624abzi_s2d44.h +* +* \brief +* CY8C624ABZI-S2D44 device header +* +* \note +* Generator version: 1.5.0.1274 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C624ABZI_S2D44_H_ +#define _CY8C624ABZI_S2D44_H_ + +/** +* \addtogroup group_device CY8C624ABZI-S2D44 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + /* ARM Cortex-M0+ Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C624ABZI-S2D44 User Interrupt Numbers */ + NvicMux0_IRQn = 0, /*!< 0 [DeepSleep] CPU User Interrupt #0 */ + NvicMux1_IRQn = 1, /*!< 1 [DeepSleep] CPU User Interrupt #1 */ + NvicMux2_IRQn = 2, /*!< 2 [DeepSleep] CPU User Interrupt #2 */ + NvicMux3_IRQn = 3, /*!< 3 [DeepSleep] CPU User Interrupt #3 */ + NvicMux4_IRQn = 4, /*!< 4 [DeepSleep] CPU User Interrupt #4 */ + NvicMux5_IRQn = 5, /*!< 5 [DeepSleep] CPU User Interrupt #5 */ + NvicMux6_IRQn = 6, /*!< 6 [DeepSleep] CPU User Interrupt #6 */ + NvicMux7_IRQn = 7, /*!< 7 [DeepSleep] CPU User Interrupt #7 */ + /* CY8C624ABZI-S2D44 Internal SW Interrupt Numbers */ + Internal0_IRQn = 8, /*!< 8 [Active] Internal SW Interrupt #0 */ + Internal1_IRQn = 9, /*!< 9 [Active] Internal SW Interrupt #1 */ + Internal2_IRQn = 10, /*!< 10 [Active] Internal SW Interrupt #2 */ + Internal3_IRQn = 11, /*!< 11 [Active] Internal SW Interrupt #3 */ + Internal4_IRQn = 12, /*!< 12 [Active] Internal SW Interrupt #4 */ + Internal5_IRQn = 13, /*!< 13 [Active] Internal SW Interrupt #5 */ + Internal6_IRQn = 14, /*!< 14 [Active] Internal SW Interrupt #6 */ + Internal7_IRQn = 15, /*!< 15 [Active] Internal SW Interrupt #7 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#else + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C624ABZI-S2D44 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#endif +} IRQn_Type; + + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* CY8C624ABZI-S2D44 interrupts that can be routed to the CM0+ NVIC */ +typedef enum { + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + disconnected_IRQn =1023 /*!< 1023 Disconnected */ +} cy_en_intr_t; + +#endif + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */ +#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ + +#else + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 1 /*!< CM0P present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + +#endif + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00100000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00200000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 2u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPROFILE 1u +#define CY_IP_MXPROFILE_INSTANCES 1u +#define CY_IP_MXPROFILE_VERSION 1u + +#include "psoc6_02_config.h" +#include "gpio_psoc6_02_124_bga.h" + +#define CY_DEVICE_PSOC6A2M +#define CY_SILICON_ID 0xE4531102UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40004140 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR10_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU6_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_DMAC_CH3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_PROFILE ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_SDHC1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB8 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB9 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB10 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB11 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB12 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ +#define PERI_MS_PPU_FX_PDM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[226]) /* 0x40014080 */ +#define PERI_MS_PPU_FX_I2S0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[227]) /* 0x400140C0 */ +#define PERI_MS_PPU_FX_I2S1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[228]) /* 0x40014100 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40100000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40100000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU6_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[0]) /* 0x40235A00 */ +#define PROT_MPU6_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[1]) /* 0x40235A20 */ +#define PROT_MPU6_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[2]) /* 0x40235A40 */ +#define PROT_MPU6_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[3]) /* 0x40235A60 */ +#define PROT_MPU6_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[4]) /* 0x40235A80 */ +#define PROT_MPU6_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[5]) /* 0x40235AA0 */ +#define PROT_MPU6_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[6]) /* 0x40235AC0 */ +#define PROT_MPU6_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[7]) /* 0x40235AE0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ +#define DMAC_CH2 ((DMAC_CH_Type*) &DMAC->CH[2]) /* 0x402A1200 */ +#define DMAC_CH3 ((DMAC_CH_Type*) &DMAC->CH[3]) /* 0x402A1300 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* PROFILE +*******************************************************************************/ + +#define PROFILE_BASE 0x402D0000UL +#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */ +#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */ +#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */ +#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */ +#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */ +#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */ +#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */ +#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */ +#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */ +#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */ +#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */ +#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ +#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */ +#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */ +#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */ +#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */ +#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */ +#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */ +#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */ +#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */ +#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */ +#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */ +#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */ +#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */ +#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */ +#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */ +#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */ +#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ +#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC1_BASE 0x40470000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC1 ((SDHC_Type*) SDHC1_BASE) /* 0x40470000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC1_WRAP ((SDHC_WRAP_Type*) &SDHC1->WRAP) /* 0x40470000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ +#define SDHC1_CORE ((SDHC_CORE_Type*) &SDHC1->CORE) /* 0x40471000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB7_BASE 0x40670000UL +#define SCB8_BASE 0x40680000UL +#define SCB9_BASE 0x40690000UL +#define SCB10_BASE 0x406A0000UL +#define SCB11_BASE 0x406B0000UL +#define SCB12_BASE 0x406C0000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ +#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40670000 */ +#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40680000 */ +#define SCB9 ((CySCB_Type*) SCB9_BASE) /* 0x40690000 */ +#define SCB10 ((CySCB_Type*) SCB10_BASE) /* 0x406A0000 */ +#define SCB11 ((CySCB_Type*) SCB11_BASE) /* 0x406B0000 */ +#define SCB12 ((CySCB_Type*) SCB12_BASE) /* 0x406C0000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/******************************************************************************* +* PDM +*******************************************************************************/ + +#define PDM0_BASE 0x40A00000UL +#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x40A00000 */ + +/******************************************************************************* +* I2S +*******************************************************************************/ + +#define I2S0_BASE 0x40A10000UL +#define I2S1_BASE 0x40A11000UL +#define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x40A10000 */ +#define I2S1 ((I2S_Type*) I2S1_BASE) /* 0x40A11000 */ + +/** \} CY8C624ABZI-S2D44 */ + +#endif /* _CY8C624ABZI_S2D44_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_s2d44a0.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_s2d44a0.h new file mode 100644 index 0000000000..dc373d7842 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_s2d44a0.h @@ -0,0 +1,1326 @@ +/***************************************************************************//** +* \file cy8c624abzi_s2d44a0.h +* +* \brief +* CY8C624ABZI-S2D44A0 device header +* +* \note +* Generator version: 1.5.0.1274 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C624ABZI_S2D44A0_H_ +#define _CY8C624ABZI_S2D44A0_H_ + +/** +* \addtogroup group_device CY8C624ABZI-S2D44A0 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + /* ARM Cortex-M0+ Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C624ABZI-S2D44A0 User Interrupt Numbers */ + NvicMux0_IRQn = 0, /*!< 0 [DeepSleep] CPU User Interrupt #0 */ + NvicMux1_IRQn = 1, /*!< 1 [DeepSleep] CPU User Interrupt #1 */ + NvicMux2_IRQn = 2, /*!< 2 [DeepSleep] CPU User Interrupt #2 */ + NvicMux3_IRQn = 3, /*!< 3 [DeepSleep] CPU User Interrupt #3 */ + NvicMux4_IRQn = 4, /*!< 4 [DeepSleep] CPU User Interrupt #4 */ + NvicMux5_IRQn = 5, /*!< 5 [DeepSleep] CPU User Interrupt #5 */ + NvicMux6_IRQn = 6, /*!< 6 [DeepSleep] CPU User Interrupt #6 */ + NvicMux7_IRQn = 7, /*!< 7 [DeepSleep] CPU User Interrupt #7 */ + /* CY8C624ABZI-S2D44A0 Internal SW Interrupt Numbers */ + Internal0_IRQn = 8, /*!< 8 [Active] Internal SW Interrupt #0 */ + Internal1_IRQn = 9, /*!< 9 [Active] Internal SW Interrupt #1 */ + Internal2_IRQn = 10, /*!< 10 [Active] Internal SW Interrupt #2 */ + Internal3_IRQn = 11, /*!< 11 [Active] Internal SW Interrupt #3 */ + Internal4_IRQn = 12, /*!< 12 [Active] Internal SW Interrupt #4 */ + Internal5_IRQn = 13, /*!< 13 [Active] Internal SW Interrupt #5 */ + Internal6_IRQn = 14, /*!< 14 [Active] Internal SW Interrupt #6 */ + Internal7_IRQn = 15, /*!< 15 [Active] Internal SW Interrupt #7 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#else + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C624ABZI-S2D44A0 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#endif +} IRQn_Type; + + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* CY8C624ABZI-S2D44A0 interrupts that can be routed to the CM0+ NVIC */ +typedef enum { + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + disconnected_IRQn =1023 /*!< 1023 Disconnected */ +} cy_en_intr_t; + +#endif + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */ +#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ + +#else + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 1 /*!< CM0P present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + +#endif + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00100000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00200000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 2u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPROFILE 1u +#define CY_IP_MXPROFILE_INSTANCES 1u +#define CY_IP_MXPROFILE_VERSION 1u + +#include "psoc6_02_config.h" +#include "gpio_psoc6_02_124_bga.h" + +#define CY_DEVICE_PSOC6A2M +#define CY_SILICON_ID 0xE4021102UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40004140 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR10_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU6_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_DMAC_CH3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_PROFILE ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_SDHC1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB8 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB9 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB10 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB11 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB12 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ +#define PERI_MS_PPU_FX_PDM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[226]) /* 0x40014080 */ +#define PERI_MS_PPU_FX_I2S0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[227]) /* 0x400140C0 */ +#define PERI_MS_PPU_FX_I2S1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[228]) /* 0x40014100 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40100000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40100000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU6_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[0]) /* 0x40235A00 */ +#define PROT_MPU6_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[1]) /* 0x40235A20 */ +#define PROT_MPU6_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[2]) /* 0x40235A40 */ +#define PROT_MPU6_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[3]) /* 0x40235A60 */ +#define PROT_MPU6_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[4]) /* 0x40235A80 */ +#define PROT_MPU6_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[5]) /* 0x40235AA0 */ +#define PROT_MPU6_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[6]) /* 0x40235AC0 */ +#define PROT_MPU6_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[7]) /* 0x40235AE0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ +#define DMAC_CH2 ((DMAC_CH_Type*) &DMAC->CH[2]) /* 0x402A1200 */ +#define DMAC_CH3 ((DMAC_CH_Type*) &DMAC->CH[3]) /* 0x402A1300 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* PROFILE +*******************************************************************************/ + +#define PROFILE_BASE 0x402D0000UL +#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */ +#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */ +#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */ +#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */ +#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */ +#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */ +#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */ +#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */ +#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */ +#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */ +#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */ +#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ +#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */ +#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */ +#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */ +#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */ +#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */ +#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */ +#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */ +#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */ +#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */ +#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */ +#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */ +#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */ +#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */ +#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */ +#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */ +#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ +#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC1_BASE 0x40470000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC1 ((SDHC_Type*) SDHC1_BASE) /* 0x40470000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC1_WRAP ((SDHC_WRAP_Type*) &SDHC1->WRAP) /* 0x40470000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ +#define SDHC1_CORE ((SDHC_CORE_Type*) &SDHC1->CORE) /* 0x40471000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB7_BASE 0x40670000UL +#define SCB8_BASE 0x40680000UL +#define SCB9_BASE 0x40690000UL +#define SCB10_BASE 0x406A0000UL +#define SCB11_BASE 0x406B0000UL +#define SCB12_BASE 0x406C0000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ +#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40670000 */ +#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40680000 */ +#define SCB9 ((CySCB_Type*) SCB9_BASE) /* 0x40690000 */ +#define SCB10 ((CySCB_Type*) SCB10_BASE) /* 0x406A0000 */ +#define SCB11 ((CySCB_Type*) SCB11_BASE) /* 0x406B0000 */ +#define SCB12 ((CySCB_Type*) SCB12_BASE) /* 0x406C0000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/******************************************************************************* +* PDM +*******************************************************************************/ + +#define PDM0_BASE 0x40A00000UL +#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x40A00000 */ + +/******************************************************************************* +* I2S +*******************************************************************************/ + +#define I2S0_BASE 0x40A10000UL +#define I2S1_BASE 0x40A11000UL +#define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x40A10000 */ +#define I2S1 ((I2S_Type*) I2S1_BASE) /* 0x40A11000 */ + +/** \} CY8C624ABZI-S2D44A0 */ + +#endif /* _CY8C624ABZI_S2D44A0_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624afni_d43.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624afni_d43.h index dc2f540d5e..fc4b91ea1e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624afni_d43.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624afni_d43.h @@ -5,7 +5,7 @@ * CY8C624AFNI-D43 device header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -553,7 +553,7 @@ typedef enum { #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u -#define CY_IP_MXS40PASS_SAR_INSTANCES 16u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u #define CY_IP_MXS40IOSS 1u #define CY_IP_MXS40IOSS_INSTANCES 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624afni_s2d43.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624afni_s2d43.h new file mode 100644 index 0000000000..0ed00503c1 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624afni_s2d43.h @@ -0,0 +1,1326 @@ +/***************************************************************************//** +* \file cy8c624afni_s2d43.h +* +* \brief +* CY8C624AFNI-S2D43 device header +* +* \note +* Generator version: 1.5.0.1274 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C624AFNI_S2D43_H_ +#define _CY8C624AFNI_S2D43_H_ + +/** +* \addtogroup group_device CY8C624AFNI-S2D43 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + /* ARM Cortex-M0+ Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C624AFNI-S2D43 User Interrupt Numbers */ + NvicMux0_IRQn = 0, /*!< 0 [DeepSleep] CPU User Interrupt #0 */ + NvicMux1_IRQn = 1, /*!< 1 [DeepSleep] CPU User Interrupt #1 */ + NvicMux2_IRQn = 2, /*!< 2 [DeepSleep] CPU User Interrupt #2 */ + NvicMux3_IRQn = 3, /*!< 3 [DeepSleep] CPU User Interrupt #3 */ + NvicMux4_IRQn = 4, /*!< 4 [DeepSleep] CPU User Interrupt #4 */ + NvicMux5_IRQn = 5, /*!< 5 [DeepSleep] CPU User Interrupt #5 */ + NvicMux6_IRQn = 6, /*!< 6 [DeepSleep] CPU User Interrupt #6 */ + NvicMux7_IRQn = 7, /*!< 7 [DeepSleep] CPU User Interrupt #7 */ + /* CY8C624AFNI-S2D43 Internal SW Interrupt Numbers */ + Internal0_IRQn = 8, /*!< 8 [Active] Internal SW Interrupt #0 */ + Internal1_IRQn = 9, /*!< 9 [Active] Internal SW Interrupt #1 */ + Internal2_IRQn = 10, /*!< 10 [Active] Internal SW Interrupt #2 */ + Internal3_IRQn = 11, /*!< 11 [Active] Internal SW Interrupt #3 */ + Internal4_IRQn = 12, /*!< 12 [Active] Internal SW Interrupt #4 */ + Internal5_IRQn = 13, /*!< 13 [Active] Internal SW Interrupt #5 */ + Internal6_IRQn = 14, /*!< 14 [Active] Internal SW Interrupt #6 */ + Internal7_IRQn = 15, /*!< 15 [Active] Internal SW Interrupt #7 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#else + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C624AFNI-S2D43 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#endif +} IRQn_Type; + + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* CY8C624AFNI-S2D43 interrupts that can be routed to the CM0+ NVIC */ +typedef enum { + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + disconnected_IRQn =1023 /*!< 1023 Disconnected */ +} cy_en_intr_t; + +#endif + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */ +#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ + +#else + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 1 /*!< CM0P present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + +#endif + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00100000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00200000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 2u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPROFILE 1u +#define CY_IP_MXPROFILE_INSTANCES 1u +#define CY_IP_MXPROFILE_VERSION 1u + +#include "psoc6_02_config.h" +#include "gpio_psoc6_02_100_wlcsp.h" + +#define CY_DEVICE_PSOC6A2M +#define CY_SILICON_ID 0xE4551102UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40004140 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR10_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU6_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_DMAC_CH3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_PROFILE ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_SDHC1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB8 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB9 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB10 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB11 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB12 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ +#define PERI_MS_PPU_FX_PDM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[226]) /* 0x40014080 */ +#define PERI_MS_PPU_FX_I2S0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[227]) /* 0x400140C0 */ +#define PERI_MS_PPU_FX_I2S1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[228]) /* 0x40014100 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40100000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40100000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU6_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[0]) /* 0x40235A00 */ +#define PROT_MPU6_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[1]) /* 0x40235A20 */ +#define PROT_MPU6_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[2]) /* 0x40235A40 */ +#define PROT_MPU6_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[3]) /* 0x40235A60 */ +#define PROT_MPU6_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[4]) /* 0x40235A80 */ +#define PROT_MPU6_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[5]) /* 0x40235AA0 */ +#define PROT_MPU6_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[6]) /* 0x40235AC0 */ +#define PROT_MPU6_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[7]) /* 0x40235AE0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ +#define DMAC_CH2 ((DMAC_CH_Type*) &DMAC->CH[2]) /* 0x402A1200 */ +#define DMAC_CH3 ((DMAC_CH_Type*) &DMAC->CH[3]) /* 0x402A1300 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* PROFILE +*******************************************************************************/ + +#define PROFILE_BASE 0x402D0000UL +#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */ +#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */ +#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */ +#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */ +#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */ +#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */ +#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */ +#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */ +#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */ +#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */ +#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */ +#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ +#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */ +#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */ +#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */ +#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */ +#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */ +#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */ +#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */ +#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */ +#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */ +#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */ +#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */ +#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */ +#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */ +#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */ +#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */ +#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ +#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC1_BASE 0x40470000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC1 ((SDHC_Type*) SDHC1_BASE) /* 0x40470000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC1_WRAP ((SDHC_WRAP_Type*) &SDHC1->WRAP) /* 0x40470000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ +#define SDHC1_CORE ((SDHC_CORE_Type*) &SDHC1->CORE) /* 0x40471000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB7_BASE 0x40670000UL +#define SCB8_BASE 0x40680000UL +#define SCB9_BASE 0x40690000UL +#define SCB10_BASE 0x406A0000UL +#define SCB11_BASE 0x406B0000UL +#define SCB12_BASE 0x406C0000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ +#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40670000 */ +#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40680000 */ +#define SCB9 ((CySCB_Type*) SCB9_BASE) /* 0x40690000 */ +#define SCB10 ((CySCB_Type*) SCB10_BASE) /* 0x406A0000 */ +#define SCB11 ((CySCB_Type*) SCB11_BASE) /* 0x406B0000 */ +#define SCB12 ((CySCB_Type*) SCB12_BASE) /* 0x406C0000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/******************************************************************************* +* PDM +*******************************************************************************/ + +#define PDM0_BASE 0x40A00000UL +#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x40A00000 */ + +/******************************************************************************* +* I2S +*******************************************************************************/ + +#define I2S0_BASE 0x40A10000UL +#define I2S1_BASE 0x40A11000UL +#define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x40A10000 */ +#define I2S1 ((I2S_Type*) I2S1_BASE) /* 0x40A11000 */ + +/** \} CY8C624AFNI-S2D43 */ + +#endif /* _CY8C624AFNI_S2D43_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624alqi_d42.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624alqi_d42.h new file mode 100644 index 0000000000..32b126ab0a --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624alqi_d42.h @@ -0,0 +1,1326 @@ +/***************************************************************************//** +* \file cy8c624alqi_d42.h +* +* \brief +* CY8C624ALQI-D42 device header +* +* \note +* Generator version: 1.5.0.1274 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C624ALQI_D42_H_ +#define _CY8C624ALQI_D42_H_ + +/** +* \addtogroup group_device CY8C624ALQI-D42 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + /* ARM Cortex-M0+ Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C624ALQI-D42 User Interrupt Numbers */ + NvicMux0_IRQn = 0, /*!< 0 [DeepSleep] CPU User Interrupt #0 */ + NvicMux1_IRQn = 1, /*!< 1 [DeepSleep] CPU User Interrupt #1 */ + NvicMux2_IRQn = 2, /*!< 2 [DeepSleep] CPU User Interrupt #2 */ + NvicMux3_IRQn = 3, /*!< 3 [DeepSleep] CPU User Interrupt #3 */ + NvicMux4_IRQn = 4, /*!< 4 [DeepSleep] CPU User Interrupt #4 */ + NvicMux5_IRQn = 5, /*!< 5 [DeepSleep] CPU User Interrupt #5 */ + NvicMux6_IRQn = 6, /*!< 6 [DeepSleep] CPU User Interrupt #6 */ + NvicMux7_IRQn = 7, /*!< 7 [DeepSleep] CPU User Interrupt #7 */ + /* CY8C624ALQI-D42 Internal SW Interrupt Numbers */ + Internal0_IRQn = 8, /*!< 8 [Active] Internal SW Interrupt #0 */ + Internal1_IRQn = 9, /*!< 9 [Active] Internal SW Interrupt #1 */ + Internal2_IRQn = 10, /*!< 10 [Active] Internal SW Interrupt #2 */ + Internal3_IRQn = 11, /*!< 11 [Active] Internal SW Interrupt #3 */ + Internal4_IRQn = 12, /*!< 12 [Active] Internal SW Interrupt #4 */ + Internal5_IRQn = 13, /*!< 13 [Active] Internal SW Interrupt #5 */ + Internal6_IRQn = 14, /*!< 14 [Active] Internal SW Interrupt #6 */ + Internal7_IRQn = 15, /*!< 15 [Active] Internal SW Interrupt #7 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#else + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C624ALQI-D42 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#endif +} IRQn_Type; + + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* CY8C624ALQI-D42 interrupts that can be routed to the CM0+ NVIC */ +typedef enum { + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + disconnected_IRQn =1023 /*!< 1023 Disconnected */ +} cy_en_intr_t; + +#endif + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */ +#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ + +#else + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 1 /*!< CM0P present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + +#endif + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00100000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00200000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 2u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPROFILE 1u +#define CY_IP_MXPROFILE_INSTANCES 1u +#define CY_IP_MXPROFILE_VERSION 1u + +#include "psoc6_02_config.h" +#include "gpio_psoc6_02_68_qfn.h" + +#define CY_DEVICE_PSOC6A2M +#define CY_SILICON_ID 0xE4191102UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40004140 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR10_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU6_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_DMAC_CH3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_PROFILE ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_SDHC1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB8 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB9 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB10 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB11 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB12 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ +#define PERI_MS_PPU_FX_PDM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[226]) /* 0x40014080 */ +#define PERI_MS_PPU_FX_I2S0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[227]) /* 0x400140C0 */ +#define PERI_MS_PPU_FX_I2S1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[228]) /* 0x40014100 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40100000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40100000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU6_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[0]) /* 0x40235A00 */ +#define PROT_MPU6_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[1]) /* 0x40235A20 */ +#define PROT_MPU6_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[2]) /* 0x40235A40 */ +#define PROT_MPU6_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[3]) /* 0x40235A60 */ +#define PROT_MPU6_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[4]) /* 0x40235A80 */ +#define PROT_MPU6_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[5]) /* 0x40235AA0 */ +#define PROT_MPU6_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[6]) /* 0x40235AC0 */ +#define PROT_MPU6_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[7]) /* 0x40235AE0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ +#define DMAC_CH2 ((DMAC_CH_Type*) &DMAC->CH[2]) /* 0x402A1200 */ +#define DMAC_CH3 ((DMAC_CH_Type*) &DMAC->CH[3]) /* 0x402A1300 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* PROFILE +*******************************************************************************/ + +#define PROFILE_BASE 0x402D0000UL +#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */ +#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */ +#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */ +#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */ +#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */ +#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */ +#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */ +#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */ +#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */ +#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */ +#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */ +#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ +#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */ +#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */ +#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */ +#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */ +#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */ +#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */ +#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */ +#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */ +#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */ +#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */ +#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */ +#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */ +#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */ +#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */ +#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */ +#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ +#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC1_BASE 0x40470000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC1 ((SDHC_Type*) SDHC1_BASE) /* 0x40470000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC1_WRAP ((SDHC_WRAP_Type*) &SDHC1->WRAP) /* 0x40470000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ +#define SDHC1_CORE ((SDHC_CORE_Type*) &SDHC1->CORE) /* 0x40471000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB7_BASE 0x40670000UL +#define SCB8_BASE 0x40680000UL +#define SCB9_BASE 0x40690000UL +#define SCB10_BASE 0x406A0000UL +#define SCB11_BASE 0x406B0000UL +#define SCB12_BASE 0x406C0000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ +#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40670000 */ +#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40680000 */ +#define SCB9 ((CySCB_Type*) SCB9_BASE) /* 0x40690000 */ +#define SCB10 ((CySCB_Type*) SCB10_BASE) /* 0x406A0000 */ +#define SCB11 ((CySCB_Type*) SCB11_BASE) /* 0x406B0000 */ +#define SCB12 ((CySCB_Type*) SCB12_BASE) /* 0x406C0000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/******************************************************************************* +* PDM +*******************************************************************************/ + +#define PDM0_BASE 0x40A00000UL +#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x40A00000 */ + +/******************************************************************************* +* I2S +*******************************************************************************/ + +#define I2S0_BASE 0x40A10000UL +#define I2S1_BASE 0x40A11000UL +#define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x40A10000 */ +#define I2S1 ((I2S_Type*) I2S1_BASE) /* 0x40A11000 */ + +/** \} CY8C624ALQI-D42 */ + +#endif /* _CY8C624ALQI_D42_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6316bzi_blf03.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6316bzi_blf03.h index e9d42cb773..56f2b811c1 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6316bzi_blf03.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6316bzi_blf03.h @@ -5,7 +5,7 @@ * CY8C6316BZI-BLF03 device header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -289,7 +289,7 @@ typedef enum { #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u -#define CY_IP_MXS40PASS_SAR_INSTANCES 16u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6316bzi_blf04.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6316bzi_blf04.h index 4a97b84f85..710b183004 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6316bzi_blf04.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6316bzi_blf04.h @@ -5,7 +5,7 @@ * CY8C6316BZI-BLF04 device header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -289,7 +289,7 @@ typedef enum { #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u -#define CY_IP_MXS40PASS_SAR_INSTANCES 16u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6316bzi_blf53.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6316bzi_blf53.h index 24324dcb38..440c7977ce 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6316bzi_blf53.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6316bzi_blf53.h @@ -5,7 +5,7 @@ * CY8C6316BZI-BLF53 device header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -292,7 +292,7 @@ typedef enum { #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u -#define CY_IP_MXS40PASS_SAR_INSTANCES 16u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6316bzi_blf54.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6316bzi_blf54.h index 73f5f52958..45316437ab 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6316bzi_blf54.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6316bzi_blf54.h @@ -5,7 +5,7 @@ * CY8C6316BZI-BLF54 device header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -292,7 +292,7 @@ typedef enum { #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u -#define CY_IP_MXS40PASS_SAR_INSTANCES 16u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336bzi_bld13.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336bzi_bld13.h index 890ed2d77c..98604776d5 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336bzi_bld13.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336bzi_bld13.h @@ -5,7 +5,7 @@ * CY8C6336BZI-BLD13 device header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -514,7 +514,7 @@ typedef enum { #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u -#define CY_IP_MXS40PASS_SAR_INSTANCES 16u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336bzi_bld14.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336bzi_bld14.h index b141aa2e46..6aec1a5169 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336bzi_bld14.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336bzi_bld14.h @@ -5,7 +5,7 @@ * CY8C6336BZI-BLD14 device header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -514,7 +514,7 @@ typedef enum { #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u -#define CY_IP_MXS40PASS_SAR_INSTANCES 16u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336bzi_blf03.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336bzi_blf03.h index 9243e8b172..8931cda30f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336bzi_blf03.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336bzi_blf03.h @@ -5,7 +5,7 @@ * CY8C6336BZI-BLF03 device header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -289,7 +289,7 @@ typedef enum { #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u -#define CY_IP_MXS40PASS_SAR_INSTANCES 16u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336bzi_blf04.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336bzi_blf04.h index 18d9f68951..4fed38cd3b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336bzi_blf04.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336bzi_blf04.h @@ -5,7 +5,7 @@ * CY8C6336BZI-BLF04 device header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -289,7 +289,7 @@ typedef enum { #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u -#define CY_IP_MXS40PASS_SAR_INSTANCES 16u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336bzi_bud13.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336bzi_bud13.h index 239fe087e2..62515d3b62 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336bzi_bud13.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336bzi_bud13.h @@ -5,7 +5,7 @@ * CY8C6336BZI-BUD13 device header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -514,7 +514,7 @@ typedef enum { #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u -#define CY_IP_MXS40PASS_SAR_INSTANCES 16u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336lqi_blf02.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336lqi_blf02.h new file mode 100644 index 0000000000..8d565acdd3 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336lqi_blf02.h @@ -0,0 +1,953 @@ +/***************************************************************************//** +* \file cy8c6336lqi_blf02.h +* +* \brief +* CY8C6336LQI-BLF02 device header +* +* \note +* Generator version: 1.5.0.1274 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6336LQI_BLF02_H_ +#define _CY8C6336LQI_BLF02_H_ + +/** +* \addtogroup group_device CY8C6336LQI-BLF02 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6336LQI-BLF02 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + pass_interrupt_ctbs_IRQn = 23, /*!< 23 [DeepSleep] CTBm Interrupt (all CTBms) */ + bless_interrupt_IRQn = 24, /*!< 24 [DeepSleep] Bluetooth Radio interrupt */ + cpuss_interrupts_ipc_0_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 39, /*!< 39 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 40, /*!< 40 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #7 */ + csd_interrupt_IRQn = 49, /*!< 49 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dw0_0_IRQn = 50, /*!< 50 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 51, /*!< 51 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 52, /*!< 52 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 53, /*!< 53 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 54, /*!< 54 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 55, /*!< 55 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw1_0_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_fault_0_IRQn = 82, /*!< 82 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 83, /*!< 83 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 84, /*!< 84 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 85, /*!< 85 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm0_cti_0_IRQn = 86, /*!< 86 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 87, /*!< 87 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 88, /*!< 88 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 89, /*!< 89 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 90, /*!< 90 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 91, /*!< 91 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 92, /*!< 92 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 93, /*!< 93 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 94, /*!< 94 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 95, /*!< 95 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 96, /*!< 96 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 97, /*!< 97 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 98, /*!< 98 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 99, /*!< 99 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 100, /*!< 100 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 101, /*!< 101 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 102, /*!< 102 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 103, /*!< 103 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 104, /*!< 104 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 105, /*!< 105 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 106, /*!< 106 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 107, /*!< 107 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 108, /*!< 108 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 109, /*!< 109 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 110, /*!< 110 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 111, /*!< 111 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 112, /*!< 112 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 113, /*!< 113 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 114, /*!< 114 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 115, /*!< 115 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 116, /*!< 116 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 117, /*!< 117 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 118, /*!< 118 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 119, /*!< 119 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 120, /*!< 120 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 121, /*!< 121 [Active] TCPWM #1, Counter #23 */ + udb_interrupts_0_IRQn = 122, /*!< 122 [Active] UDB Interrupt #0 */ + udb_interrupts_1_IRQn = 123, /*!< 123 [Active] UDB Interrupt #1 */ + udb_interrupts_2_IRQn = 124, /*!< 124 [Active] UDB Interrupt #2 */ + udb_interrupts_3_IRQn = 125, /*!< 125 [Active] UDB Interrupt #3 */ + udb_interrupts_4_IRQn = 126, /*!< 126 [Active] UDB Interrupt #4 */ + udb_interrupts_5_IRQn = 127, /*!< 127 [Active] UDB Interrupt #5 */ + udb_interrupts_6_IRQn = 128, /*!< 128 [Active] UDB Interrupt #6 */ + udb_interrupts_7_IRQn = 129, /*!< 129 [Active] UDB Interrupt #7 */ + udb_interrupts_8_IRQn = 130, /*!< 130 [Active] UDB Interrupt #8 */ + udb_interrupts_9_IRQn = 131, /*!< 131 [Active] UDB Interrupt #9 */ + udb_interrupts_10_IRQn = 132, /*!< 132 [Active] UDB Interrupt #10 */ + udb_interrupts_11_IRQn = 133, /*!< 133 [Active] UDB Interrupt #11 */ + udb_interrupts_12_IRQn = 134, /*!< 134 [Active] UDB Interrupt #12 */ + udb_interrupts_13_IRQn = 135, /*!< 135 [Active] UDB Interrupt #13 */ + udb_interrupts_14_IRQn = 136, /*!< 136 [Active] UDB Interrupt #14 */ + udb_interrupts_15_IRQn = 137, /*!< 137 [Active] UDB Interrupt #15 */ + pass_interrupt_sar_IRQn = 138, /*!< 138 [Active] SAR ADC interrupt */ + audioss_interrupt_i2s_IRQn = 139, /*!< 139 [Active] I2S Audio interrupt */ + audioss_interrupt_pdm_IRQn = 140, /*!< 140 [Active] PDM/PCM Audio interrupt */ + profile_interrupt_IRQn = 141, /*!< 141 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 142, /*!< 142 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 143, /*!< 143 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 144, /*!< 144 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 145, /*!< 145 [Active] USB Interrupt */ + pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00020000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00020000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00080000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 1u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXS40PASS_CTDAC 1u +#define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u +#define CY_IP_MXS40PASS_CTDAC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPROFILE 1u +#define CY_IP_MXPROFILE_INSTANCES 1u +#define CY_IP_MXPROFILE_VERSION 1u + +#include "psoc6_01_config.h" +#include "gpio_psoc6_01_68_qfn_ble.h" + +#define CY_DEVICE_PSOC6ABLE2 +#define CY_SILICON_ID 0xE2512100UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40010000UL +#define PERI_PPU_GR_MMIO0_BASE 0x40015000UL +#define PERI_PPU_GR_MMIO1_BASE 0x40015040UL +#define PERI_PPU_GR_MMIO2_BASE 0x40015080UL +#define PERI_PPU_GR_MMIO3_BASE 0x400150C0UL +#define PERI_PPU_GR_MMIO4_BASE 0x40015100UL +#define PERI_PPU_GR_MMIO6_BASE 0x40015180UL +#define PERI_PPU_GR_MMIO9_BASE 0x40015240UL +#define PERI_PPU_GR_MMIO10_BASE 0x40015280UL +#define PERI_GR_PPU_SL_PERI_GR1_BASE 0x40100000UL +#define PERI_GR_PPU_SL_CRYPTO_BASE 0x40100040UL +#define PERI_GR_PPU_SL_PERI_GR2_BASE 0x40200000UL +#define PERI_GR_PPU_SL_CPUSS_BASE 0x40200040UL +#define PERI_GR_PPU_SL_FAULT_BASE 0x40200080UL +#define PERI_GR_PPU_SL_IPC_BASE 0x402000C0UL +#define PERI_GR_PPU_SL_PROT_BASE 0x40200100UL +#define PERI_GR_PPU_SL_FLASHC_BASE 0x40200140UL +#define PERI_GR_PPU_SL_SRSS_BASE 0x40200180UL +#define PERI_GR_PPU_SL_BACKUP_BASE 0x402001C0UL +#define PERI_GR_PPU_SL_DW0_BASE 0x40200200UL +#define PERI_GR_PPU_SL_DW1_BASE 0x40200240UL +#define PERI_GR_PPU_SL_EFUSE_BASE 0x40200300UL +#define PERI_GR_PPU_SL_PROFILE_BASE 0x40200340UL +#define PERI_GR_PPU_RG_IPC_STRUCT0_BASE 0x40201000UL +#define PERI_GR_PPU_RG_IPC_STRUCT1_BASE 0x40201040UL +#define PERI_GR_PPU_RG_IPC_STRUCT2_BASE 0x40201080UL +#define PERI_GR_PPU_RG_IPC_STRUCT3_BASE 0x402010C0UL +#define PERI_GR_PPU_RG_IPC_STRUCT4_BASE 0x40201100UL +#define PERI_GR_PPU_RG_IPC_STRUCT5_BASE 0x40201140UL +#define PERI_GR_PPU_RG_IPC_STRUCT6_BASE 0x40201180UL +#define PERI_GR_PPU_RG_IPC_STRUCT7_BASE 0x402011C0UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT0_BASE 0x40201200UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT1_BASE 0x40201240UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT2_BASE 0x40201280UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT3_BASE 0x402012C0UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT4_BASE 0x40201300UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT5_BASE 0x40201340UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT6_BASE 0x40201380UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT7_BASE 0x402013C0UL +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0_BASE 0x40201400UL +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1_BASE 0x40201440UL +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2_BASE 0x40201480UL +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3_BASE 0x402014C0UL +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0_BASE 0x40201500UL +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1_BASE 0x40201540UL +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2_BASE 0x40201580UL +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3_BASE 0x402015C0UL +#define PERI_GR_PPU_RG_SMPU_BASE 0x40201600UL +#define PERI_GR_PPU_RG_MPU_CM0P_BASE 0x40201640UL +#define PERI_GR_PPU_RG_MPU_CRYPTO_BASE 0x40201680UL +#define PERI_GR_PPU_RG_MPU_CM4_BASE 0x402016C0UL +#define PERI_GR_PPU_RG_MPU_TC_BASE 0x40201700UL +#define PERI_GR_PPU_SL_PERI_GR3_BASE 0x40300000UL +#define PERI_GR_PPU_SL_HSIOM_BASE 0x40300040UL +#define PERI_GR_PPU_SL_GPIO_BASE 0x40300080UL +#define PERI_GR_PPU_SL_SMARTIO_BASE 0x403000C0UL +#define PERI_GR_PPU_SL_UDB_BASE 0x40300100UL +#define PERI_GR_PPU_SL_LPCOMP_BASE 0x40300140UL +#define PERI_GR_PPU_SL_CSD_BASE 0x40300180UL +#define PERI_GR_PPU_SL_TCPWM0_BASE 0x40300200UL +#define PERI_GR_PPU_SL_TCPWM1_BASE 0x40300240UL +#define PERI_GR_PPU_SL_LCD_BASE 0x40300280UL +#define PERI_GR_PPU_SL_BLE_BASE 0x403002C0UL +#define PERI_GR_PPU_SL_USBFS_BASE 0x40300300UL +#define PERI_GR_PPU_SL_PERI_GR4_BASE 0x40400000UL +#define PERI_GR_PPU_SL_SMIF_BASE 0x40400080UL +#define PERI_GR_PPU_SL_PERI_GR6_BASE 0x40600000UL +#define PERI_GR_PPU_SL_SCB0_BASE 0x40600040UL +#define PERI_GR_PPU_SL_SCB1_BASE 0x40600080UL +#define PERI_GR_PPU_SL_SCB2_BASE 0x406000C0UL +#define PERI_GR_PPU_SL_SCB3_BASE 0x40600100UL +#define PERI_GR_PPU_SL_SCB4_BASE 0x40600140UL +#define PERI_GR_PPU_SL_SCB5_BASE 0x40600180UL +#define PERI_GR_PPU_SL_SCB6_BASE 0x406001C0UL +#define PERI_GR_PPU_SL_SCB7_BASE 0x40600200UL +#define PERI_GR_PPU_SL_SCB8_BASE 0x40600240UL +#define PERI_GR_PPU_SL_PERI_GR9_BASE 0x41000000UL +#define PERI_GR_PPU_SL_PASS_BASE 0x41000040UL +#define PERI_GR_PPU_SL_PERI_GR10_BASE 0x42A00000UL +#define PERI_GR_PPU_SL_I2S_BASE 0x42A00040UL +#define PERI_GR_PPU_SL_PDM_BASE 0x42A00080UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40010000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40010000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40010040 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40010080 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x400100C0 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40010100 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x40010180 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40010240 */ +#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40010280 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40012000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40012200 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40012400 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40012600 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40012800 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40012A00 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40012C00 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40012E00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x40013000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x40013200 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x40013400 */ +#define PERI_TR_GR11 ((PERI_TR_GR_Type*) &PERI->TR_GR[11]) /* 0x40013600 */ +#define PERI_TR_GR12 ((PERI_TR_GR_Type*) &PERI->TR_GR[12]) /* 0x40013800 */ +#define PERI_TR_GR13 ((PERI_TR_GR_Type*) &PERI->TR_GR[13]) /* 0x40013A00 */ +#define PERI_TR_GR14 ((PERI_TR_GR_Type*) &PERI->TR_GR[14]) /* 0x40013C00 */ +#define PERI_PPU_PR0 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[0]) /* 0x40014000 */ +#define PERI_PPU_PR1 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[1]) /* 0x40014040 */ +#define PERI_PPU_PR2 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[2]) /* 0x40014080 */ +#define PERI_PPU_PR3 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[3]) /* 0x400140C0 */ +#define PERI_PPU_PR4 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[4]) /* 0x40014100 */ +#define PERI_PPU_PR5 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[5]) /* 0x40014140 */ +#define PERI_PPU_PR6 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[6]) /* 0x40014180 */ +#define PERI_PPU_PR7 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[7]) /* 0x400141C0 */ +#define PERI_PPU_PR8 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[8]) /* 0x40014200 */ +#define PERI_PPU_PR9 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[9]) /* 0x40014240 */ +#define PERI_PPU_PR10 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[10]) /* 0x40014280 */ +#define PERI_PPU_PR11 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[11]) /* 0x400142C0 */ +#define PERI_PPU_PR12 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[12]) /* 0x40014300 */ +#define PERI_PPU_PR13 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[13]) /* 0x40014340 */ +#define PERI_PPU_PR14 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[14]) /* 0x40014380 */ +#define PERI_PPU_PR15 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[15]) /* 0x400143C0 */ +#define PERI_PPU_GR0 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[0]) /* 0x40015000 */ +#define PERI_PPU_GR1 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[1]) /* 0x40015040 */ +#define PERI_PPU_GR2 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[2]) /* 0x40015080 */ +#define PERI_PPU_GR3 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[3]) /* 0x400150C0 */ +#define PERI_PPU_GR4 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[4]) /* 0x40015100 */ +#define PERI_PPU_GR6 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[6]) /* 0x40015180 */ +#define PERI_PPU_GR9 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[9]) /* 0x40015240 */ +#define PERI_PPU_GR10 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[10]) /* 0x40015280 */ +#define PERI_PPU_GR_MMIO0 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO0_BASE) /* 0x40015000 */ +#define PERI_PPU_GR_MMIO1 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO1_BASE) /* 0x40015040 */ +#define PERI_PPU_GR_MMIO2 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO2_BASE) /* 0x40015080 */ +#define PERI_PPU_GR_MMIO3 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO3_BASE) /* 0x400150C0 */ +#define PERI_PPU_GR_MMIO4 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO4_BASE) /* 0x40015100 */ +#define PERI_PPU_GR_MMIO6 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO6_BASE) /* 0x40015180 */ +#define PERI_PPU_GR_MMIO9 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO9_BASE) /* 0x40015240 */ +#define PERI_PPU_GR_MMIO10 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO10_BASE) /* 0x40015280 */ +#define PERI_GR_PPU_SL_PERI_GR1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR1_BASE) /* 0x40100000 */ +#define PERI_GR_PPU_SL_CRYPTO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CRYPTO_BASE) /* 0x40100040 */ +#define PERI_GR_PPU_SL_PERI_GR2 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR2_BASE) /* 0x40200000 */ +#define PERI_GR_PPU_SL_CPUSS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CPUSS_BASE) /* 0x40200040 */ +#define PERI_GR_PPU_SL_FAULT ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_FAULT_BASE) /* 0x40200080 */ +#define PERI_GR_PPU_SL_IPC ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_IPC_BASE) /* 0x402000C0 */ +#define PERI_GR_PPU_SL_PROT ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PROT_BASE) /* 0x40200100 */ +#define PERI_GR_PPU_SL_FLASHC ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_FLASHC_BASE) /* 0x40200140 */ +#define PERI_GR_PPU_SL_SRSS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SRSS_BASE) /* 0x40200180 */ +#define PERI_GR_PPU_SL_BACKUP ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_BACKUP_BASE) /* 0x402001C0 */ +#define PERI_GR_PPU_SL_DW0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_DW0_BASE) /* 0x40200200 */ +#define PERI_GR_PPU_SL_DW1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_DW1_BASE) /* 0x40200240 */ +#define PERI_GR_PPU_SL_EFUSE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_EFUSE_BASE) /* 0x40200300 */ +#define PERI_GR_PPU_SL_PROFILE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PROFILE_BASE) /* 0x40200340 */ +#define PERI_GR_PPU_RG_IPC_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT0_BASE) /* 0x40201000 */ +#define PERI_GR_PPU_RG_IPC_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT1_BASE) /* 0x40201040 */ +#define PERI_GR_PPU_RG_IPC_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT2_BASE) /* 0x40201080 */ +#define PERI_GR_PPU_RG_IPC_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT3_BASE) /* 0x402010C0 */ +#define PERI_GR_PPU_RG_IPC_STRUCT4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT4_BASE) /* 0x40201100 */ +#define PERI_GR_PPU_RG_IPC_STRUCT5 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT5_BASE) /* 0x40201140 */ +#define PERI_GR_PPU_RG_IPC_STRUCT6 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT6_BASE) /* 0x40201180 */ +#define PERI_GR_PPU_RG_IPC_STRUCT7 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT7_BASE) /* 0x402011C0 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT0_BASE) /* 0x40201200 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT1_BASE) /* 0x40201240 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT2_BASE) /* 0x40201280 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT3_BASE) /* 0x402012C0 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT4_BASE) /* 0x40201300 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT5 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT5_BASE) /* 0x40201340 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT6 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT6_BASE) /* 0x40201380 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT7 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT7_BASE) /* 0x402013C0 */ +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0_BASE) /* 0x40201400 */ +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1_BASE) /* 0x40201440 */ +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2_BASE) /* 0x40201480 */ +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3_BASE) /* 0x402014C0 */ +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0_BASE) /* 0x40201500 */ +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1_BASE) /* 0x40201540 */ +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2_BASE) /* 0x40201580 */ +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3_BASE) /* 0x402015C0 */ +#define PERI_GR_PPU_RG_SMPU ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_SMPU_BASE) /* 0x40201600 */ +#define PERI_GR_PPU_RG_MPU_CM0P ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CM0P_BASE) /* 0x40201640 */ +#define PERI_GR_PPU_RG_MPU_CRYPTO ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CRYPTO_BASE) /* 0x40201680 */ +#define PERI_GR_PPU_RG_MPU_CM4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CM4_BASE) /* 0x402016C0 */ +#define PERI_GR_PPU_RG_MPU_TC ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_TC_BASE) /* 0x40201700 */ +#define PERI_GR_PPU_SL_PERI_GR3 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR3_BASE) /* 0x40300000 */ +#define PERI_GR_PPU_SL_HSIOM ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_HSIOM_BASE) /* 0x40300040 */ +#define PERI_GR_PPU_SL_GPIO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_GPIO_BASE) /* 0x40300080 */ +#define PERI_GR_PPU_SL_SMARTIO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SMARTIO_BASE) /* 0x403000C0 */ +#define PERI_GR_PPU_SL_UDB ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_UDB_BASE) /* 0x40300100 */ +#define PERI_GR_PPU_SL_LPCOMP ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_LPCOMP_BASE) /* 0x40300140 */ +#define PERI_GR_PPU_SL_CSD ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CSD_BASE) /* 0x40300180 */ +#define PERI_GR_PPU_SL_TCPWM0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_TCPWM0_BASE) /* 0x40300200 */ +#define PERI_GR_PPU_SL_TCPWM1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_TCPWM1_BASE) /* 0x40300240 */ +#define PERI_GR_PPU_SL_LCD ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_LCD_BASE) /* 0x40300280 */ +#define PERI_GR_PPU_SL_BLE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_BLE_BASE) /* 0x403002C0 */ +#define PERI_GR_PPU_SL_USBFS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_USBFS_BASE) /* 0x40300300 */ +#define PERI_GR_PPU_SL_PERI_GR4 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR4_BASE) /* 0x40400000 */ +#define PERI_GR_PPU_SL_SMIF ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SMIF_BASE) /* 0x40400080 */ +#define PERI_GR_PPU_SL_PERI_GR6 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR6_BASE) /* 0x40600000 */ +#define PERI_GR_PPU_SL_SCB0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB0_BASE) /* 0x40600040 */ +#define PERI_GR_PPU_SL_SCB1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB1_BASE) /* 0x40600080 */ +#define PERI_GR_PPU_SL_SCB2 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB2_BASE) /* 0x406000C0 */ +#define PERI_GR_PPU_SL_SCB3 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB3_BASE) /* 0x40600100 */ +#define PERI_GR_PPU_SL_SCB4 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB4_BASE) /* 0x40600140 */ +#define PERI_GR_PPU_SL_SCB5 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB5_BASE) /* 0x40600180 */ +#define PERI_GR_PPU_SL_SCB6 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB6_BASE) /* 0x406001C0 */ +#define PERI_GR_PPU_SL_SCB7 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB7_BASE) /* 0x40600200 */ +#define PERI_GR_PPU_SL_SCB8 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB8_BASE) /* 0x40600240 */ +#define PERI_GR_PPU_SL_PERI_GR9 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR9_BASE) /* 0x41000000 */ +#define PERI_GR_PPU_SL_PASS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PASS_BASE) /* 0x41000040 */ +#define PERI_GR_PPU_SL_PERI_GR10 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR10_BASE) /* 0x42A00000 */ +#define PERI_GR_PPU_SL_I2S ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_I2S_BASE) /* 0x42A00040 */ +#define PERI_GR_PPU_SL_PDM ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PDM_BASE) /* 0x42A00080 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40210000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40210000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40220000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40220000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40220000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40220100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40230000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40230000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40230000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40230020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40230040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40230060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40230080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402300A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402300C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402300E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40230100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40230120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40230140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40230160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40230180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402301A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402301C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402301E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40231000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40231020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40231040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40231060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40231080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402310A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402310C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402310E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40231100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40231120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40231140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40231160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40231180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402311A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402311C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402311E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40240000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402420C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40242100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40242140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40242180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402421C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40242200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40242240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40242280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402422C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40242300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40244C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40245000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40245400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40245800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40245C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40246000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40246400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40246800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40246C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40247000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40250000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40250000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4025F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40281000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40281000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40280800 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40280820 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40280840 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x40280860 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40280880 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x402808A0 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x402808C0 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402808E0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40280900 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40280920 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40280940 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x40280960 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40280980 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x402809A0 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x402809C0 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402809E0 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40281800 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40281820 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40281840 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x40281860 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40281880 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x402818A0 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x402818C0 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402818E0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40281900 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40281920 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40281940 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x40281960 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40281980 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x402819A0 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x402819C0 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402819E0 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* PROFILE +*******************************************************************************/ + +#define PROFILE_BASE 0x402D0000UL +#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */ +#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */ +#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */ +#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */ +#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */ +#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */ +#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */ +#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */ +#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40310000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40310000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40310000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40310010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40310020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40310030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40310040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40310050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40310060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40310070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40310080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40310090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403100A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403100B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403100C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403100D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403100E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40320000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40320000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40320000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40320080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40320100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40320180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40320200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40320280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40320300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40320380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40320400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40320480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40320500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40320580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40320600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40320680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40320700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40330000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40330000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40330800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40330900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */ +#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */ +#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */ +#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ +#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */ +#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */ +#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */ +#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */ +#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */ +#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */ +#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */ +#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */ +#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */ +#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */ +#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */ +#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */ +#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */ +#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */ +#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */ +#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* BLE +*******************************************************************************/ + +#define BLE_BASE 0x403C0000UL +#define BLE ((BLE_Type*) BLE_BASE) /* 0x403C0000 */ +#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ +#define BLE_RCB ((BLE_RCB_Type*) &BLE->RCB) /* 0x403C0000 */ +#define BLE_BLELL ((BLE_BLELL_Type*) &BLE->BLELL) /* 0x403C1000 */ +#define BLE_BLESS ((BLE_BLESS_Type*) &BLE->BLESS) /* 0x403DF000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ +#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40610000UL +#define SCB1_BASE 0x40620000UL +#define SCB2_BASE 0x40630000UL +#define SCB3_BASE 0x40640000UL +#define SCB4_BASE 0x40650000UL +#define SCB5_BASE 0x40660000UL +#define SCB6_BASE 0x40670000UL +#define SCB7_BASE 0x40680000UL +#define SCB8_BASE 0x40690000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40610000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40620000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40630000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40640000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40650000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40660000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40670000 */ +#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40680000 */ +#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40690000 */ + +/******************************************************************************* +* CTBM +*******************************************************************************/ + +#define CTBM0_BASE 0x41100000UL +#define CTBM0 ((CTBM_Type*) CTBM0_BASE) /* 0x41100000 */ + +/******************************************************************************* +* CTDAC +*******************************************************************************/ + +#define CTDAC0_BASE 0x41140000UL +#define CTDAC0 ((CTDAC_Type*) CTDAC0_BASE) /* 0x41140000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x411D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x411D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x411F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x411F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x411F0E00 */ + +/******************************************************************************* +* I2S +*******************************************************************************/ + +#define I2S0_BASE 0x42A10000UL +#define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x42A10000 */ + +/******************************************************************************* +* PDM +*******************************************************************************/ + +#define PDM0_BASE 0x42A20000UL +#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x42A20000 */ + + +/* Backward compatibility definitions */ +#define CY_SRAM0_BASE CY_SRAM_BASE +#define CY_SRAM0_SIZE CY_SRAM_SIZE +#define I2S I2S0 +#define PDM PDM0 + +/** \} CY8C6336LQI-BLF02 */ + +#endif /* _CY8C6336LQI_BLF02_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336lqi_blf42.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336lqi_blf42.h new file mode 100644 index 0000000000..54347e0f2e --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336lqi_blf42.h @@ -0,0 +1,963 @@ +/***************************************************************************//** +* \file cy8c6336lqi_blf42.h +* +* \brief +* CY8C6336LQI-BLF42 device header +* +* \note +* Generator version: 1.5.0.1274 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6336LQI_BLF42_H_ +#define _CY8C6336LQI_BLF42_H_ + +/** +* \addtogroup group_device CY8C6336LQI-BLF42 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6336LQI-BLF42 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + pass_interrupt_ctbs_IRQn = 23, /*!< 23 [DeepSleep] CTBm Interrupt (all CTBms) */ + bless_interrupt_IRQn = 24, /*!< 24 [DeepSleep] Bluetooth Radio interrupt */ + cpuss_interrupts_ipc_0_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 39, /*!< 39 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 40, /*!< 40 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #7 */ + csd_interrupt_IRQn = 49, /*!< 49 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dw0_0_IRQn = 50, /*!< 50 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 51, /*!< 51 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 52, /*!< 52 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 53, /*!< 53 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 54, /*!< 54 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 55, /*!< 55 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw1_0_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_fault_0_IRQn = 82, /*!< 82 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 83, /*!< 83 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 84, /*!< 84 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 85, /*!< 85 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm0_cti_0_IRQn = 86, /*!< 86 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 87, /*!< 87 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 88, /*!< 88 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 89, /*!< 89 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 90, /*!< 90 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 91, /*!< 91 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 92, /*!< 92 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 93, /*!< 93 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 94, /*!< 94 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 95, /*!< 95 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 96, /*!< 96 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 97, /*!< 97 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 98, /*!< 98 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 99, /*!< 99 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 100, /*!< 100 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 101, /*!< 101 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 102, /*!< 102 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 103, /*!< 103 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 104, /*!< 104 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 105, /*!< 105 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 106, /*!< 106 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 107, /*!< 107 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 108, /*!< 108 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 109, /*!< 109 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 110, /*!< 110 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 111, /*!< 111 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 112, /*!< 112 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 113, /*!< 113 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 114, /*!< 114 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 115, /*!< 115 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 116, /*!< 116 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 117, /*!< 117 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 118, /*!< 118 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 119, /*!< 119 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 120, /*!< 120 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 121, /*!< 121 [Active] TCPWM #1, Counter #23 */ + udb_interrupts_0_IRQn = 122, /*!< 122 [Active] UDB Interrupt #0 */ + udb_interrupts_1_IRQn = 123, /*!< 123 [Active] UDB Interrupt #1 */ + udb_interrupts_2_IRQn = 124, /*!< 124 [Active] UDB Interrupt #2 */ + udb_interrupts_3_IRQn = 125, /*!< 125 [Active] UDB Interrupt #3 */ + udb_interrupts_4_IRQn = 126, /*!< 126 [Active] UDB Interrupt #4 */ + udb_interrupts_5_IRQn = 127, /*!< 127 [Active] UDB Interrupt #5 */ + udb_interrupts_6_IRQn = 128, /*!< 128 [Active] UDB Interrupt #6 */ + udb_interrupts_7_IRQn = 129, /*!< 129 [Active] UDB Interrupt #7 */ + udb_interrupts_8_IRQn = 130, /*!< 130 [Active] UDB Interrupt #8 */ + udb_interrupts_9_IRQn = 131, /*!< 131 [Active] UDB Interrupt #9 */ + udb_interrupts_10_IRQn = 132, /*!< 132 [Active] UDB Interrupt #10 */ + udb_interrupts_11_IRQn = 133, /*!< 133 [Active] UDB Interrupt #11 */ + udb_interrupts_12_IRQn = 134, /*!< 134 [Active] UDB Interrupt #12 */ + udb_interrupts_13_IRQn = 135, /*!< 135 [Active] UDB Interrupt #13 */ + udb_interrupts_14_IRQn = 136, /*!< 136 [Active] UDB Interrupt #14 */ + udb_interrupts_15_IRQn = 137, /*!< 137 [Active] UDB Interrupt #15 */ + pass_interrupt_sar_IRQn = 138, /*!< 138 [Active] SAR ADC interrupt */ + audioss_interrupt_i2s_IRQn = 139, /*!< 139 [Active] I2S Audio interrupt */ + audioss_interrupt_pdm_IRQn = 140, /*!< 140 [Active] PDM/PCM Audio interrupt */ + profile_interrupt_IRQn = 141, /*!< 141 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 142, /*!< 142 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 143, /*!< 143 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 144, /*!< 144 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 145, /*!< 145 [Active] USB Interrupt */ + pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00020000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00020000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00080000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 1u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 1u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXS40PASS_CTDAC 1u +#define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u +#define CY_IP_MXS40PASS_CTDAC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPROFILE 1u +#define CY_IP_MXPROFILE_INSTANCES 1u +#define CY_IP_MXPROFILE_VERSION 1u + +#include "psoc6_01_config.h" +#include "gpio_psoc6_01_68_qfn_ble.h" + +#define CY_DEVICE_PSOC6ABLE2 +#define CY_SILICON_ID 0xE2522100UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40010000UL +#define PERI_PPU_GR_MMIO0_BASE 0x40015000UL +#define PERI_PPU_GR_MMIO1_BASE 0x40015040UL +#define PERI_PPU_GR_MMIO2_BASE 0x40015080UL +#define PERI_PPU_GR_MMIO3_BASE 0x400150C0UL +#define PERI_PPU_GR_MMIO4_BASE 0x40015100UL +#define PERI_PPU_GR_MMIO6_BASE 0x40015180UL +#define PERI_PPU_GR_MMIO9_BASE 0x40015240UL +#define PERI_PPU_GR_MMIO10_BASE 0x40015280UL +#define PERI_GR_PPU_SL_PERI_GR1_BASE 0x40100000UL +#define PERI_GR_PPU_SL_CRYPTO_BASE 0x40100040UL +#define PERI_GR_PPU_SL_PERI_GR2_BASE 0x40200000UL +#define PERI_GR_PPU_SL_CPUSS_BASE 0x40200040UL +#define PERI_GR_PPU_SL_FAULT_BASE 0x40200080UL +#define PERI_GR_PPU_SL_IPC_BASE 0x402000C0UL +#define PERI_GR_PPU_SL_PROT_BASE 0x40200100UL +#define PERI_GR_PPU_SL_FLASHC_BASE 0x40200140UL +#define PERI_GR_PPU_SL_SRSS_BASE 0x40200180UL +#define PERI_GR_PPU_SL_BACKUP_BASE 0x402001C0UL +#define PERI_GR_PPU_SL_DW0_BASE 0x40200200UL +#define PERI_GR_PPU_SL_DW1_BASE 0x40200240UL +#define PERI_GR_PPU_SL_EFUSE_BASE 0x40200300UL +#define PERI_GR_PPU_SL_PROFILE_BASE 0x40200340UL +#define PERI_GR_PPU_RG_IPC_STRUCT0_BASE 0x40201000UL +#define PERI_GR_PPU_RG_IPC_STRUCT1_BASE 0x40201040UL +#define PERI_GR_PPU_RG_IPC_STRUCT2_BASE 0x40201080UL +#define PERI_GR_PPU_RG_IPC_STRUCT3_BASE 0x402010C0UL +#define PERI_GR_PPU_RG_IPC_STRUCT4_BASE 0x40201100UL +#define PERI_GR_PPU_RG_IPC_STRUCT5_BASE 0x40201140UL +#define PERI_GR_PPU_RG_IPC_STRUCT6_BASE 0x40201180UL +#define PERI_GR_PPU_RG_IPC_STRUCT7_BASE 0x402011C0UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT0_BASE 0x40201200UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT1_BASE 0x40201240UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT2_BASE 0x40201280UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT3_BASE 0x402012C0UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT4_BASE 0x40201300UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT5_BASE 0x40201340UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT6_BASE 0x40201380UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT7_BASE 0x402013C0UL +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0_BASE 0x40201400UL +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1_BASE 0x40201440UL +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2_BASE 0x40201480UL +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3_BASE 0x402014C0UL +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0_BASE 0x40201500UL +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1_BASE 0x40201540UL +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2_BASE 0x40201580UL +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3_BASE 0x402015C0UL +#define PERI_GR_PPU_RG_SMPU_BASE 0x40201600UL +#define PERI_GR_PPU_RG_MPU_CM0P_BASE 0x40201640UL +#define PERI_GR_PPU_RG_MPU_CRYPTO_BASE 0x40201680UL +#define PERI_GR_PPU_RG_MPU_CM4_BASE 0x402016C0UL +#define PERI_GR_PPU_RG_MPU_TC_BASE 0x40201700UL +#define PERI_GR_PPU_SL_PERI_GR3_BASE 0x40300000UL +#define PERI_GR_PPU_SL_HSIOM_BASE 0x40300040UL +#define PERI_GR_PPU_SL_GPIO_BASE 0x40300080UL +#define PERI_GR_PPU_SL_SMARTIO_BASE 0x403000C0UL +#define PERI_GR_PPU_SL_UDB_BASE 0x40300100UL +#define PERI_GR_PPU_SL_LPCOMP_BASE 0x40300140UL +#define PERI_GR_PPU_SL_CSD_BASE 0x40300180UL +#define PERI_GR_PPU_SL_TCPWM0_BASE 0x40300200UL +#define PERI_GR_PPU_SL_TCPWM1_BASE 0x40300240UL +#define PERI_GR_PPU_SL_LCD_BASE 0x40300280UL +#define PERI_GR_PPU_SL_BLE_BASE 0x403002C0UL +#define PERI_GR_PPU_SL_USBFS_BASE 0x40300300UL +#define PERI_GR_PPU_SL_PERI_GR4_BASE 0x40400000UL +#define PERI_GR_PPU_SL_SMIF_BASE 0x40400080UL +#define PERI_GR_PPU_SL_PERI_GR6_BASE 0x40600000UL +#define PERI_GR_PPU_SL_SCB0_BASE 0x40600040UL +#define PERI_GR_PPU_SL_SCB1_BASE 0x40600080UL +#define PERI_GR_PPU_SL_SCB2_BASE 0x406000C0UL +#define PERI_GR_PPU_SL_SCB3_BASE 0x40600100UL +#define PERI_GR_PPU_SL_SCB4_BASE 0x40600140UL +#define PERI_GR_PPU_SL_SCB5_BASE 0x40600180UL +#define PERI_GR_PPU_SL_SCB6_BASE 0x406001C0UL +#define PERI_GR_PPU_SL_SCB7_BASE 0x40600200UL +#define PERI_GR_PPU_SL_SCB8_BASE 0x40600240UL +#define PERI_GR_PPU_SL_PERI_GR9_BASE 0x41000000UL +#define PERI_GR_PPU_SL_PASS_BASE 0x41000040UL +#define PERI_GR_PPU_SL_PERI_GR10_BASE 0x42A00000UL +#define PERI_GR_PPU_SL_I2S_BASE 0x42A00040UL +#define PERI_GR_PPU_SL_PDM_BASE 0x42A00080UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40010000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40010000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40010040 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40010080 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x400100C0 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40010100 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x40010180 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40010240 */ +#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40010280 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40012000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40012200 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40012400 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40012600 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40012800 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40012A00 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40012C00 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40012E00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x40013000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x40013200 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x40013400 */ +#define PERI_TR_GR11 ((PERI_TR_GR_Type*) &PERI->TR_GR[11]) /* 0x40013600 */ +#define PERI_TR_GR12 ((PERI_TR_GR_Type*) &PERI->TR_GR[12]) /* 0x40013800 */ +#define PERI_TR_GR13 ((PERI_TR_GR_Type*) &PERI->TR_GR[13]) /* 0x40013A00 */ +#define PERI_TR_GR14 ((PERI_TR_GR_Type*) &PERI->TR_GR[14]) /* 0x40013C00 */ +#define PERI_PPU_PR0 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[0]) /* 0x40014000 */ +#define PERI_PPU_PR1 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[1]) /* 0x40014040 */ +#define PERI_PPU_PR2 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[2]) /* 0x40014080 */ +#define PERI_PPU_PR3 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[3]) /* 0x400140C0 */ +#define PERI_PPU_PR4 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[4]) /* 0x40014100 */ +#define PERI_PPU_PR5 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[5]) /* 0x40014140 */ +#define PERI_PPU_PR6 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[6]) /* 0x40014180 */ +#define PERI_PPU_PR7 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[7]) /* 0x400141C0 */ +#define PERI_PPU_PR8 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[8]) /* 0x40014200 */ +#define PERI_PPU_PR9 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[9]) /* 0x40014240 */ +#define PERI_PPU_PR10 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[10]) /* 0x40014280 */ +#define PERI_PPU_PR11 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[11]) /* 0x400142C0 */ +#define PERI_PPU_PR12 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[12]) /* 0x40014300 */ +#define PERI_PPU_PR13 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[13]) /* 0x40014340 */ +#define PERI_PPU_PR14 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[14]) /* 0x40014380 */ +#define PERI_PPU_PR15 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[15]) /* 0x400143C0 */ +#define PERI_PPU_GR0 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[0]) /* 0x40015000 */ +#define PERI_PPU_GR1 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[1]) /* 0x40015040 */ +#define PERI_PPU_GR2 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[2]) /* 0x40015080 */ +#define PERI_PPU_GR3 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[3]) /* 0x400150C0 */ +#define PERI_PPU_GR4 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[4]) /* 0x40015100 */ +#define PERI_PPU_GR6 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[6]) /* 0x40015180 */ +#define PERI_PPU_GR9 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[9]) /* 0x40015240 */ +#define PERI_PPU_GR10 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[10]) /* 0x40015280 */ +#define PERI_PPU_GR_MMIO0 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO0_BASE) /* 0x40015000 */ +#define PERI_PPU_GR_MMIO1 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO1_BASE) /* 0x40015040 */ +#define PERI_PPU_GR_MMIO2 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO2_BASE) /* 0x40015080 */ +#define PERI_PPU_GR_MMIO3 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO3_BASE) /* 0x400150C0 */ +#define PERI_PPU_GR_MMIO4 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO4_BASE) /* 0x40015100 */ +#define PERI_PPU_GR_MMIO6 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO6_BASE) /* 0x40015180 */ +#define PERI_PPU_GR_MMIO9 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO9_BASE) /* 0x40015240 */ +#define PERI_PPU_GR_MMIO10 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO10_BASE) /* 0x40015280 */ +#define PERI_GR_PPU_SL_PERI_GR1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR1_BASE) /* 0x40100000 */ +#define PERI_GR_PPU_SL_CRYPTO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CRYPTO_BASE) /* 0x40100040 */ +#define PERI_GR_PPU_SL_PERI_GR2 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR2_BASE) /* 0x40200000 */ +#define PERI_GR_PPU_SL_CPUSS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CPUSS_BASE) /* 0x40200040 */ +#define PERI_GR_PPU_SL_FAULT ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_FAULT_BASE) /* 0x40200080 */ +#define PERI_GR_PPU_SL_IPC ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_IPC_BASE) /* 0x402000C0 */ +#define PERI_GR_PPU_SL_PROT ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PROT_BASE) /* 0x40200100 */ +#define PERI_GR_PPU_SL_FLASHC ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_FLASHC_BASE) /* 0x40200140 */ +#define PERI_GR_PPU_SL_SRSS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SRSS_BASE) /* 0x40200180 */ +#define PERI_GR_PPU_SL_BACKUP ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_BACKUP_BASE) /* 0x402001C0 */ +#define PERI_GR_PPU_SL_DW0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_DW0_BASE) /* 0x40200200 */ +#define PERI_GR_PPU_SL_DW1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_DW1_BASE) /* 0x40200240 */ +#define PERI_GR_PPU_SL_EFUSE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_EFUSE_BASE) /* 0x40200300 */ +#define PERI_GR_PPU_SL_PROFILE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PROFILE_BASE) /* 0x40200340 */ +#define PERI_GR_PPU_RG_IPC_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT0_BASE) /* 0x40201000 */ +#define PERI_GR_PPU_RG_IPC_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT1_BASE) /* 0x40201040 */ +#define PERI_GR_PPU_RG_IPC_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT2_BASE) /* 0x40201080 */ +#define PERI_GR_PPU_RG_IPC_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT3_BASE) /* 0x402010C0 */ +#define PERI_GR_PPU_RG_IPC_STRUCT4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT4_BASE) /* 0x40201100 */ +#define PERI_GR_PPU_RG_IPC_STRUCT5 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT5_BASE) /* 0x40201140 */ +#define PERI_GR_PPU_RG_IPC_STRUCT6 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT6_BASE) /* 0x40201180 */ +#define PERI_GR_PPU_RG_IPC_STRUCT7 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT7_BASE) /* 0x402011C0 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT0_BASE) /* 0x40201200 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT1_BASE) /* 0x40201240 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT2_BASE) /* 0x40201280 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT3_BASE) /* 0x402012C0 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT4_BASE) /* 0x40201300 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT5 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT5_BASE) /* 0x40201340 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT6 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT6_BASE) /* 0x40201380 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT7 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT7_BASE) /* 0x402013C0 */ +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0_BASE) /* 0x40201400 */ +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1_BASE) /* 0x40201440 */ +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2_BASE) /* 0x40201480 */ +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3_BASE) /* 0x402014C0 */ +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0_BASE) /* 0x40201500 */ +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1_BASE) /* 0x40201540 */ +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2_BASE) /* 0x40201580 */ +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3_BASE) /* 0x402015C0 */ +#define PERI_GR_PPU_RG_SMPU ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_SMPU_BASE) /* 0x40201600 */ +#define PERI_GR_PPU_RG_MPU_CM0P ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CM0P_BASE) /* 0x40201640 */ +#define PERI_GR_PPU_RG_MPU_CRYPTO ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CRYPTO_BASE) /* 0x40201680 */ +#define PERI_GR_PPU_RG_MPU_CM4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CM4_BASE) /* 0x402016C0 */ +#define PERI_GR_PPU_RG_MPU_TC ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_TC_BASE) /* 0x40201700 */ +#define PERI_GR_PPU_SL_PERI_GR3 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR3_BASE) /* 0x40300000 */ +#define PERI_GR_PPU_SL_HSIOM ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_HSIOM_BASE) /* 0x40300040 */ +#define PERI_GR_PPU_SL_GPIO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_GPIO_BASE) /* 0x40300080 */ +#define PERI_GR_PPU_SL_SMARTIO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SMARTIO_BASE) /* 0x403000C0 */ +#define PERI_GR_PPU_SL_UDB ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_UDB_BASE) /* 0x40300100 */ +#define PERI_GR_PPU_SL_LPCOMP ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_LPCOMP_BASE) /* 0x40300140 */ +#define PERI_GR_PPU_SL_CSD ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CSD_BASE) /* 0x40300180 */ +#define PERI_GR_PPU_SL_TCPWM0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_TCPWM0_BASE) /* 0x40300200 */ +#define PERI_GR_PPU_SL_TCPWM1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_TCPWM1_BASE) /* 0x40300240 */ +#define PERI_GR_PPU_SL_LCD ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_LCD_BASE) /* 0x40300280 */ +#define PERI_GR_PPU_SL_BLE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_BLE_BASE) /* 0x403002C0 */ +#define PERI_GR_PPU_SL_USBFS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_USBFS_BASE) /* 0x40300300 */ +#define PERI_GR_PPU_SL_PERI_GR4 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR4_BASE) /* 0x40400000 */ +#define PERI_GR_PPU_SL_SMIF ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SMIF_BASE) /* 0x40400080 */ +#define PERI_GR_PPU_SL_PERI_GR6 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR6_BASE) /* 0x40600000 */ +#define PERI_GR_PPU_SL_SCB0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB0_BASE) /* 0x40600040 */ +#define PERI_GR_PPU_SL_SCB1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB1_BASE) /* 0x40600080 */ +#define PERI_GR_PPU_SL_SCB2 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB2_BASE) /* 0x406000C0 */ +#define PERI_GR_PPU_SL_SCB3 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB3_BASE) /* 0x40600100 */ +#define PERI_GR_PPU_SL_SCB4 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB4_BASE) /* 0x40600140 */ +#define PERI_GR_PPU_SL_SCB5 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB5_BASE) /* 0x40600180 */ +#define PERI_GR_PPU_SL_SCB6 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB6_BASE) /* 0x406001C0 */ +#define PERI_GR_PPU_SL_SCB7 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB7_BASE) /* 0x40600200 */ +#define PERI_GR_PPU_SL_SCB8 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB8_BASE) /* 0x40600240 */ +#define PERI_GR_PPU_SL_PERI_GR9 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR9_BASE) /* 0x41000000 */ +#define PERI_GR_PPU_SL_PASS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PASS_BASE) /* 0x41000040 */ +#define PERI_GR_PPU_SL_PERI_GR10 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR10_BASE) /* 0x42A00000 */ +#define PERI_GR_PPU_SL_I2S ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_I2S_BASE) /* 0x42A00040 */ +#define PERI_GR_PPU_SL_PDM ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PDM_BASE) /* 0x42A00080 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40110000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40110000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40210000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40210000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40220000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40220000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40220000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40220100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40230000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40230000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40230000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40230020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40230040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40230060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40230080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402300A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402300C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402300E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40230100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40230120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40230140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40230160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40230180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402301A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402301C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402301E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40231000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40231020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40231040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40231060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40231080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402310A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402310C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402310E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40231100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40231120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40231140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40231160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40231180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402311A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402311C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402311E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40240000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402420C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40242100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40242140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40242180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402421C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40242200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40242240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40242280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402422C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40242300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40244C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40245000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40245400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40245800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40245C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40246000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40246400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40246800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40246C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40247000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40250000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40250000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4025F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40281000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40281000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40280800 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40280820 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40280840 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x40280860 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40280880 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x402808A0 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x402808C0 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402808E0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40280900 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40280920 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40280940 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x40280960 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40280980 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x402809A0 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x402809C0 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402809E0 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40281800 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40281820 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40281840 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x40281860 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40281880 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x402818A0 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x402818C0 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402818E0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40281900 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40281920 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40281940 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x40281960 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40281980 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x402819A0 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x402819C0 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402819E0 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* PROFILE +*******************************************************************************/ + +#define PROFILE_BASE 0x402D0000UL +#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */ +#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */ +#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */ +#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */ +#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */ +#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */ +#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */ +#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */ +#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40310000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40310000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40310000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40310010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40310020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40310030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40310040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40310050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40310060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40310070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40310080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40310090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403100A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403100B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403100C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403100D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403100E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40320000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40320000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40320000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40320080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40320100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40320180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40320200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40320280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40320300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40320380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40320400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40320480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40320500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40320580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40320600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40320680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40320700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40330000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40330000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40330800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40330900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */ +#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */ +#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */ +#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ +#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */ +#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */ +#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */ +#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */ +#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */ +#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */ +#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */ +#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */ +#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */ +#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */ +#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */ +#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */ +#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */ +#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */ +#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */ +#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* BLE +*******************************************************************************/ + +#define BLE_BASE 0x403C0000UL +#define BLE ((BLE_Type*) BLE_BASE) /* 0x403C0000 */ +#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ +#define BLE_RCB ((BLE_RCB_Type*) &BLE->RCB) /* 0x403C0000 */ +#define BLE_BLELL ((BLE_BLELL_Type*) &BLE->BLELL) /* 0x403C1000 */ +#define BLE_BLESS ((BLE_BLESS_Type*) &BLE->BLESS) /* 0x403DF000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ +#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40610000UL +#define SCB1_BASE 0x40620000UL +#define SCB2_BASE 0x40630000UL +#define SCB3_BASE 0x40640000UL +#define SCB4_BASE 0x40650000UL +#define SCB5_BASE 0x40660000UL +#define SCB6_BASE 0x40670000UL +#define SCB7_BASE 0x40680000UL +#define SCB8_BASE 0x40690000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40610000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40620000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40630000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40640000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40650000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40660000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40670000 */ +#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40680000 */ +#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40690000 */ + +/******************************************************************************* +* CTBM +*******************************************************************************/ + +#define CTBM0_BASE 0x41100000UL +#define CTBM0 ((CTBM_Type*) CTBM0_BASE) /* 0x41100000 */ + +/******************************************************************************* +* CTDAC +*******************************************************************************/ + +#define CTDAC0_BASE 0x41140000UL +#define CTDAC0 ((CTDAC_Type*) CTDAC0_BASE) /* 0x41140000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x411D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x411D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x411F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x411F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x411F0E00 */ + +/******************************************************************************* +* I2S +*******************************************************************************/ + +#define I2S0_BASE 0x42A10000UL +#define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x42A10000 */ + +/******************************************************************************* +* PDM +*******************************************************************************/ + +#define PDM0_BASE 0x42A20000UL +#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x42A20000 */ + + +/* Backward compatibility definitions */ +#define CY_SRAM0_BASE CY_SRAM_BASE +#define CY_SRAM0_SIZE CY_SRAM_SIZE +#define I2S I2S0 +#define PDM PDM0 + +/** \} CY8C6336LQI-BLF42 */ + +#endif /* _CY8C6336LQI_BLF42_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6337bzi_blf13.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6337bzi_blf13.h index 8e3b4c9fb6..40f3371fda 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6337bzi_blf13.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6337bzi_blf13.h @@ -5,7 +5,7 @@ * CY8C6337BZI-BLF13 device header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -289,7 +289,7 @@ typedef enum { #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u -#define CY_IP_MXS40PASS_SAR_INSTANCES 16u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld33.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld33.h index ff9ced021a..409b8c80a6 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld33.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld33.h @@ -5,7 +5,7 @@ * CY8C6347BZI-BLD33 device header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -514,7 +514,7 @@ typedef enum { #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u -#define CY_IP_MXS40PASS_SAR_INSTANCES 16u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld34.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld34.h index c619ce9eb6..810fb54aaa 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld34.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld34.h @@ -5,7 +5,7 @@ * CY8C6347BZI-BLD34 device header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -514,7 +514,7 @@ typedef enum { #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u -#define CY_IP_MXS40PASS_SAR_INSTANCES 16u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld43.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld43.h index 838ba636d8..c704229caa 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld43.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld43.h @@ -5,7 +5,7 @@ * CY8C6347BZI-BLD43 device header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -517,7 +517,7 @@ typedef enum { #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u -#define CY_IP_MXS40PASS_SAR_INSTANCES 16u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld44.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld44.h index 4b44246045..d19d4341be 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld44.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld44.h @@ -5,7 +5,7 @@ * CY8C6347BZI-BLD44 device header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -517,7 +517,7 @@ typedef enum { #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u -#define CY_IP_MXS40PASS_SAR_INSTANCES 16u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld53.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld53.h index 7e4248730f..e1a80e2539 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld53.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld53.h @@ -5,7 +5,7 @@ * CY8C6347BZI-BLD53 device header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -517,7 +517,7 @@ typedef enum { #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u -#define CY_IP_MXS40PASS_SAR_INSTANCES 16u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld54.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld54.h index d1e16aa087..e947938b89 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld54.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld54.h @@ -5,7 +5,7 @@ * CY8C6347BZI-BLD54 device header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -517,7 +517,7 @@ typedef enum { #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u -#define CY_IP_MXS40PASS_SAR_INSTANCES 16u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bud33.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bud33.h index d69c15e95f..872b5b09d0 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bud33.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bud33.h @@ -5,7 +5,7 @@ * CY8C6347BZI-BUD33 device header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -514,7 +514,7 @@ typedef enum { #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u -#define CY_IP_MXS40PASS_SAR_INSTANCES 16u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bud43.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bud43.h index 845e6cc3de..0bd94c8f55 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bud43.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bud43.h @@ -5,7 +5,7 @@ * CY8C6347BZI-BUD43 device header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -517,7 +517,7 @@ typedef enum { #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u -#define CY_IP_MXS40PASS_SAR_INSTANCES 16u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bud53.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bud53.h index 38e7a23772..92aa9adc5c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bud53.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bud53.h @@ -5,7 +5,7 @@ * CY8C6347BZI-BUD53 device header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -517,7 +517,7 @@ typedef enum { #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u -#define CY_IP_MXS40PASS_SAR_INSTANCES 16u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bld13.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bld13.h index 947999e066..c181097bea 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bld13.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bld13.h @@ -5,7 +5,7 @@ * CY8C6347FMI-BLD13 device header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -514,7 +514,7 @@ typedef enum { #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u -#define CY_IP_MXS40PASS_SAR_INSTANCES 16u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bld33.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bld33.h index b1d3f10765..bca572fbe9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bld33.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bld33.h @@ -5,7 +5,7 @@ * CY8C6347FMI-BLD33 device header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -514,7 +514,7 @@ typedef enum { #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u -#define CY_IP_MXS40PASS_SAR_INSTANCES 16u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bld43.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bld43.h index 49a9afa36d..669735a93f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bld43.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bld43.h @@ -5,7 +5,7 @@ * CY8C6347FMI-BLD43 device header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -517,7 +517,7 @@ typedef enum { #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u -#define CY_IP_MXS40PASS_SAR_INSTANCES 16u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bld53.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bld53.h index f28ddf79e4..2df468ee04 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bld53.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bld53.h @@ -5,7 +5,7 @@ * CY8C6347FMI-BLD53 device header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -517,7 +517,7 @@ typedef enum { #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u -#define CY_IP_MXS40PASS_SAR_INSTANCES 16u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bud13.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bud13.h index 3ecbfb0b8d..9ba7dbd377 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bud13.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bud13.h @@ -5,7 +5,7 @@ * CY8C6347FMI-BUD13 device header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -514,7 +514,7 @@ typedef enum { #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u -#define CY_IP_MXS40PASS_SAR_INSTANCES 16u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bud33.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bud33.h index 27177094b0..d25a66cab2 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bud33.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bud33.h @@ -5,7 +5,7 @@ * CY8C6347FMI-BUD33 device header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -514,7 +514,7 @@ typedef enum { #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u -#define CY_IP_MXS40PASS_SAR_INSTANCES 16u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bud43.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bud43.h index 54953019df..6fd4a9b119 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bud43.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bud43.h @@ -5,7 +5,7 @@ * CY8C6347FMI-BUD43 device header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -517,7 +517,7 @@ typedef enum { #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u -#define CY_IP_MXS40PASS_SAR_INSTANCES 16u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bud53.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bud53.h index 98ca94ef9d..92efcd4b62 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bud53.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bud53.h @@ -5,7 +5,7 @@ * CY8C6347FMI-BUD53 device header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -517,7 +517,7 @@ typedef enum { #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u -#define CY_IP_MXS40PASS_SAR_INSTANCES 16u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347lqi_bld52.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347lqi_bld52.h new file mode 100644 index 0000000000..c885082ea2 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347lqi_bld52.h @@ -0,0 +1,1253 @@ +/***************************************************************************//** +* \file cy8c6347lqi_bld52.h +* +* \brief +* CY8C6347LQI-BLD52 device header +* +* \note +* Generator version: 1.5.0.1274 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6347LQI_BLD52_H_ +#define _CY8C6347LQI_BLD52_H_ + +/** +* \addtogroup group_device CY8C6347LQI-BLD52 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + /* ARM Cortex-M0+ Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* ARM Cortex-M0+ NVIC Mux inputs. Allow routing of device interrupts to the CM0+ NVIC */ + NvicMux0_IRQn = 0, /*!< 0 [DeepSleep] CM0+ NVIC Mux input 0 */ + NvicMux1_IRQn = 1, /*!< 1 [DeepSleep] CM0+ NVIC Mux input 1 */ + NvicMux2_IRQn = 2, /*!< 2 [DeepSleep] CM0+ NVIC Mux input 2 */ + NvicMux3_IRQn = 3, /*!< 3 [DeepSleep] CM0+ NVIC Mux input 3 */ + NvicMux4_IRQn = 4, /*!< 4 [DeepSleep] CM0+ NVIC Mux input 4 */ + NvicMux5_IRQn = 5, /*!< 5 [DeepSleep] CM0+ NVIC Mux input 5 */ + NvicMux6_IRQn = 6, /*!< 6 [DeepSleep] CM0+ NVIC Mux input 6 */ + NvicMux7_IRQn = 7, /*!< 7 [DeepSleep] CM0+ NVIC Mux input 7 */ + NvicMux8_IRQn = 8, /*!< 8 [Active] CM0+ NVIC Mux input 8 */ + NvicMux9_IRQn = 9, /*!< 9 [Active] CM0+ NVIC Mux input 9 */ + NvicMux10_IRQn = 10, /*!< 10 [Active] CM0+ NVIC Mux input 10 */ + NvicMux11_IRQn = 11, /*!< 11 [Active] CM0+ NVIC Mux input 11 */ + NvicMux12_IRQn = 12, /*!< 12 [Active] CM0+ NVIC Mux input 12 */ + NvicMux13_IRQn = 13, /*!< 13 [Active] CM0+ NVIC Mux input 13 */ + NvicMux14_IRQn = 14, /*!< 14 [Active] CM0+ NVIC Mux input 14 */ + NvicMux15_IRQn = 15, /*!< 15 [Active] CM0+ NVIC Mux input 15 */ + NvicMux16_IRQn = 16, /*!< 16 [Active] CM0+ NVIC Mux input 16 */ + NvicMux17_IRQn = 17, /*!< 17 [Active] CM0+ NVIC Mux input 17 */ + NvicMux18_IRQn = 18, /*!< 18 [Active] CM0+ NVIC Mux input 18 */ + NvicMux19_IRQn = 19, /*!< 19 [Active] CM0+ NVIC Mux input 19 */ + NvicMux20_IRQn = 20, /*!< 20 [Active] CM0+ NVIC Mux input 20 */ + NvicMux21_IRQn = 21, /*!< 21 [Active] CM0+ NVIC Mux input 21 */ + NvicMux22_IRQn = 22, /*!< 22 [Active] CM0+ NVIC Mux input 22 */ + NvicMux23_IRQn = 23, /*!< 23 [Active] CM0+ NVIC Mux input 23 */ + NvicMux24_IRQn = 24, /*!< 24 [Active] CM0+ NVIC Mux input 24 */ + NvicMux25_IRQn = 25, /*!< 25 [Active] CM0+ NVIC Mux input 25 */ + NvicMux26_IRQn = 26, /*!< 26 [Active] CM0+ NVIC Mux input 26 */ + NvicMux27_IRQn = 27, /*!< 27 [Active] CM0+ NVIC Mux input 27 */ + NvicMux28_IRQn = 28, /*!< 28 [Active] CM0+ NVIC Mux input 28 */ + NvicMux29_IRQn = 29, /*!< 29 [Active] CM0+ NVIC Mux input 29 */ + NvicMux30_IRQn = 30, /*!< 30 [Active] CM0+ NVIC Mux input 30 */ + NvicMux31_IRQn = 31, /*!< 31 [Active] CM0+ NVIC Mux input 31 */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +#else + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6347LQI-BLD52 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + pass_interrupt_ctbs_IRQn = 23, /*!< 23 [DeepSleep] CTBm Interrupt (all CTBms) */ + bless_interrupt_IRQn = 24, /*!< 24 [DeepSleep] Bluetooth Radio interrupt */ + cpuss_interrupts_ipc_0_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 39, /*!< 39 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 40, /*!< 40 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #7 */ + csd_interrupt_IRQn = 49, /*!< 49 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dw0_0_IRQn = 50, /*!< 50 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 51, /*!< 51 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 52, /*!< 52 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 53, /*!< 53 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 54, /*!< 54 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 55, /*!< 55 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw1_0_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_fault_0_IRQn = 82, /*!< 82 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 83, /*!< 83 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 84, /*!< 84 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 85, /*!< 85 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm0_cti_0_IRQn = 86, /*!< 86 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 87, /*!< 87 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 88, /*!< 88 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 89, /*!< 89 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 90, /*!< 90 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 91, /*!< 91 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 92, /*!< 92 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 93, /*!< 93 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 94, /*!< 94 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 95, /*!< 95 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 96, /*!< 96 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 97, /*!< 97 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 98, /*!< 98 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 99, /*!< 99 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 100, /*!< 100 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 101, /*!< 101 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 102, /*!< 102 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 103, /*!< 103 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 104, /*!< 104 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 105, /*!< 105 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 106, /*!< 106 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 107, /*!< 107 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 108, /*!< 108 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 109, /*!< 109 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 110, /*!< 110 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 111, /*!< 111 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 112, /*!< 112 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 113, /*!< 113 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 114, /*!< 114 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 115, /*!< 115 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 116, /*!< 116 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 117, /*!< 117 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 118, /*!< 118 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 119, /*!< 119 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 120, /*!< 120 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 121, /*!< 121 [Active] TCPWM #1, Counter #23 */ + udb_interrupts_0_IRQn = 122, /*!< 122 [Active] UDB Interrupt #0 */ + udb_interrupts_1_IRQn = 123, /*!< 123 [Active] UDB Interrupt #1 */ + udb_interrupts_2_IRQn = 124, /*!< 124 [Active] UDB Interrupt #2 */ + udb_interrupts_3_IRQn = 125, /*!< 125 [Active] UDB Interrupt #3 */ + udb_interrupts_4_IRQn = 126, /*!< 126 [Active] UDB Interrupt #4 */ + udb_interrupts_5_IRQn = 127, /*!< 127 [Active] UDB Interrupt #5 */ + udb_interrupts_6_IRQn = 128, /*!< 128 [Active] UDB Interrupt #6 */ + udb_interrupts_7_IRQn = 129, /*!< 129 [Active] UDB Interrupt #7 */ + udb_interrupts_8_IRQn = 130, /*!< 130 [Active] UDB Interrupt #8 */ + udb_interrupts_9_IRQn = 131, /*!< 131 [Active] UDB Interrupt #9 */ + udb_interrupts_10_IRQn = 132, /*!< 132 [Active] UDB Interrupt #10 */ + udb_interrupts_11_IRQn = 133, /*!< 133 [Active] UDB Interrupt #11 */ + udb_interrupts_12_IRQn = 134, /*!< 134 [Active] UDB Interrupt #12 */ + udb_interrupts_13_IRQn = 135, /*!< 135 [Active] UDB Interrupt #13 */ + udb_interrupts_14_IRQn = 136, /*!< 136 [Active] UDB Interrupt #14 */ + udb_interrupts_15_IRQn = 137, /*!< 137 [Active] UDB Interrupt #15 */ + pass_interrupt_sar_IRQn = 138, /*!< 138 [Active] SAR ADC interrupt */ + audioss_interrupt_i2s_IRQn = 139, /*!< 139 [Active] I2S Audio interrupt */ + audioss_interrupt_pdm_IRQn = 140, /*!< 140 [Active] PDM/PCM Audio interrupt */ + profile_interrupt_IRQn = 141, /*!< 141 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 142, /*!< 142 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 143, /*!< 143 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 144, /*!< 144 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 145, /*!< 145 [Active] USB Interrupt */ + pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +#endif +} IRQn_Type; + + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* CY8C6347LQI-BLD52 interrupts that can be routed to the CM0+ NVIC */ +typedef enum { + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + pass_interrupt_ctbs_IRQn = 23, /*!< 23 [DeepSleep] CTBm Interrupt (all CTBms) */ + bless_interrupt_IRQn = 24, /*!< 24 [DeepSleep] Bluetooth Radio interrupt */ + cpuss_interrupts_ipc_0_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 39, /*!< 39 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 40, /*!< 40 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #7 */ + csd_interrupt_IRQn = 49, /*!< 49 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dw0_0_IRQn = 50, /*!< 50 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 51, /*!< 51 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 52, /*!< 52 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 53, /*!< 53 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 54, /*!< 54 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 55, /*!< 55 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw1_0_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_fault_0_IRQn = 82, /*!< 82 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 83, /*!< 83 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 84, /*!< 84 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 85, /*!< 85 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm0_cti_0_IRQn = 86, /*!< 86 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 87, /*!< 87 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 88, /*!< 88 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 89, /*!< 89 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 90, /*!< 90 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 91, /*!< 91 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 92, /*!< 92 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 93, /*!< 93 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 94, /*!< 94 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 95, /*!< 95 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 96, /*!< 96 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 97, /*!< 97 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 98, /*!< 98 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 99, /*!< 99 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 100, /*!< 100 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 101, /*!< 101 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 102, /*!< 102 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 103, /*!< 103 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 104, /*!< 104 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 105, /*!< 105 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 106, /*!< 106 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 107, /*!< 107 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 108, /*!< 108 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 109, /*!< 109 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 110, /*!< 110 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 111, /*!< 111 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 112, /*!< 112 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 113, /*!< 113 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 114, /*!< 114 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 115, /*!< 115 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 116, /*!< 116 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 117, /*!< 117 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 118, /*!< 118 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 119, /*!< 119 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 120, /*!< 120 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 121, /*!< 121 [Active] TCPWM #1, Counter #23 */ + udb_interrupts_0_IRQn = 122, /*!< 122 [Active] UDB Interrupt #0 */ + udb_interrupts_1_IRQn = 123, /*!< 123 [Active] UDB Interrupt #1 */ + udb_interrupts_2_IRQn = 124, /*!< 124 [Active] UDB Interrupt #2 */ + udb_interrupts_3_IRQn = 125, /*!< 125 [Active] UDB Interrupt #3 */ + udb_interrupts_4_IRQn = 126, /*!< 126 [Active] UDB Interrupt #4 */ + udb_interrupts_5_IRQn = 127, /*!< 127 [Active] UDB Interrupt #5 */ + udb_interrupts_6_IRQn = 128, /*!< 128 [Active] UDB Interrupt #6 */ + udb_interrupts_7_IRQn = 129, /*!< 129 [Active] UDB Interrupt #7 */ + udb_interrupts_8_IRQn = 130, /*!< 130 [Active] UDB Interrupt #8 */ + udb_interrupts_9_IRQn = 131, /*!< 131 [Active] UDB Interrupt #9 */ + udb_interrupts_10_IRQn = 132, /*!< 132 [Active] UDB Interrupt #10 */ + udb_interrupts_11_IRQn = 133, /*!< 133 [Active] UDB Interrupt #11 */ + udb_interrupts_12_IRQn = 134, /*!< 134 [Active] UDB Interrupt #12 */ + udb_interrupts_13_IRQn = 135, /*!< 135 [Active] UDB Interrupt #13 */ + udb_interrupts_14_IRQn = 136, /*!< 136 [Active] UDB Interrupt #14 */ + udb_interrupts_15_IRQn = 137, /*!< 137 [Active] UDB Interrupt #15 */ + pass_interrupt_sar_IRQn = 138, /*!< 138 [Active] SAR ADC interrupt */ + audioss_interrupt_i2s_IRQn = 139, /*!< 139 [Active] I2S Audio interrupt */ + audioss_interrupt_pdm_IRQn = 140, /*!< 140 [Active] PDM/PCM Audio interrupt */ + profile_interrupt_IRQn = 141, /*!< 141 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 142, /*!< 142 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 143, /*!< 143 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 144, /*!< 144 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 145, /*!< 145 [Active] USB Interrupt */ + pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */ + disconnected_IRQn = 240 /*!< 240 Disconnected */ +} cy_en_intr_t; + +#endif + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */ +#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ + +#else + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 1 /*!< CM0P present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + +#endif + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00020000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00048000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00100000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 1u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 1u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXS40PASS_CTDAC 1u +#define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u +#define CY_IP_MXS40PASS_CTDAC_VERSION 1u +#define CY_IP_MXS40PASS_CTB 1u +#define CY_IP_MXS40PASS_CTB_INSTANCES 1u +#define CY_IP_MXS40PASS_CTB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPROFILE 1u +#define CY_IP_MXPROFILE_INSTANCES 1u +#define CY_IP_MXPROFILE_VERSION 1u + +#include "psoc6_01_config.h" +#include "gpio_psoc6_01_68_qfn_ble.h" + +#define CY_DEVICE_PSOC6ABLE2 +#define CY_SILICON_ID 0xE2532100UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40010000UL +#define PERI_PPU_GR_MMIO0_BASE 0x40015000UL +#define PERI_PPU_GR_MMIO1_BASE 0x40015040UL +#define PERI_PPU_GR_MMIO2_BASE 0x40015080UL +#define PERI_PPU_GR_MMIO3_BASE 0x400150C0UL +#define PERI_PPU_GR_MMIO4_BASE 0x40015100UL +#define PERI_PPU_GR_MMIO6_BASE 0x40015180UL +#define PERI_PPU_GR_MMIO9_BASE 0x40015240UL +#define PERI_PPU_GR_MMIO10_BASE 0x40015280UL +#define PERI_GR_PPU_SL_PERI_GR1_BASE 0x40100000UL +#define PERI_GR_PPU_SL_CRYPTO_BASE 0x40100040UL +#define PERI_GR_PPU_SL_PERI_GR2_BASE 0x40200000UL +#define PERI_GR_PPU_SL_CPUSS_BASE 0x40200040UL +#define PERI_GR_PPU_SL_FAULT_BASE 0x40200080UL +#define PERI_GR_PPU_SL_IPC_BASE 0x402000C0UL +#define PERI_GR_PPU_SL_PROT_BASE 0x40200100UL +#define PERI_GR_PPU_SL_FLASHC_BASE 0x40200140UL +#define PERI_GR_PPU_SL_SRSS_BASE 0x40200180UL +#define PERI_GR_PPU_SL_BACKUP_BASE 0x402001C0UL +#define PERI_GR_PPU_SL_DW0_BASE 0x40200200UL +#define PERI_GR_PPU_SL_DW1_BASE 0x40200240UL +#define PERI_GR_PPU_SL_EFUSE_BASE 0x40200300UL +#define PERI_GR_PPU_SL_PROFILE_BASE 0x40200340UL +#define PERI_GR_PPU_RG_IPC_STRUCT0_BASE 0x40201000UL +#define PERI_GR_PPU_RG_IPC_STRUCT1_BASE 0x40201040UL +#define PERI_GR_PPU_RG_IPC_STRUCT2_BASE 0x40201080UL +#define PERI_GR_PPU_RG_IPC_STRUCT3_BASE 0x402010C0UL +#define PERI_GR_PPU_RG_IPC_STRUCT4_BASE 0x40201100UL +#define PERI_GR_PPU_RG_IPC_STRUCT5_BASE 0x40201140UL +#define PERI_GR_PPU_RG_IPC_STRUCT6_BASE 0x40201180UL +#define PERI_GR_PPU_RG_IPC_STRUCT7_BASE 0x402011C0UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT0_BASE 0x40201200UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT1_BASE 0x40201240UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT2_BASE 0x40201280UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT3_BASE 0x402012C0UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT4_BASE 0x40201300UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT5_BASE 0x40201340UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT6_BASE 0x40201380UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT7_BASE 0x402013C0UL +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0_BASE 0x40201400UL +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1_BASE 0x40201440UL +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2_BASE 0x40201480UL +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3_BASE 0x402014C0UL +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0_BASE 0x40201500UL +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1_BASE 0x40201540UL +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2_BASE 0x40201580UL +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3_BASE 0x402015C0UL +#define PERI_GR_PPU_RG_SMPU_BASE 0x40201600UL +#define PERI_GR_PPU_RG_MPU_CM0P_BASE 0x40201640UL +#define PERI_GR_PPU_RG_MPU_CRYPTO_BASE 0x40201680UL +#define PERI_GR_PPU_RG_MPU_CM4_BASE 0x402016C0UL +#define PERI_GR_PPU_RG_MPU_TC_BASE 0x40201700UL +#define PERI_GR_PPU_SL_PERI_GR3_BASE 0x40300000UL +#define PERI_GR_PPU_SL_HSIOM_BASE 0x40300040UL +#define PERI_GR_PPU_SL_GPIO_BASE 0x40300080UL +#define PERI_GR_PPU_SL_SMARTIO_BASE 0x403000C0UL +#define PERI_GR_PPU_SL_UDB_BASE 0x40300100UL +#define PERI_GR_PPU_SL_LPCOMP_BASE 0x40300140UL +#define PERI_GR_PPU_SL_CSD_BASE 0x40300180UL +#define PERI_GR_PPU_SL_TCPWM0_BASE 0x40300200UL +#define PERI_GR_PPU_SL_TCPWM1_BASE 0x40300240UL +#define PERI_GR_PPU_SL_LCD_BASE 0x40300280UL +#define PERI_GR_PPU_SL_BLE_BASE 0x403002C0UL +#define PERI_GR_PPU_SL_USBFS_BASE 0x40300300UL +#define PERI_GR_PPU_SL_PERI_GR4_BASE 0x40400000UL +#define PERI_GR_PPU_SL_SMIF_BASE 0x40400080UL +#define PERI_GR_PPU_SL_PERI_GR6_BASE 0x40600000UL +#define PERI_GR_PPU_SL_SCB0_BASE 0x40600040UL +#define PERI_GR_PPU_SL_SCB1_BASE 0x40600080UL +#define PERI_GR_PPU_SL_SCB2_BASE 0x406000C0UL +#define PERI_GR_PPU_SL_SCB3_BASE 0x40600100UL +#define PERI_GR_PPU_SL_SCB4_BASE 0x40600140UL +#define PERI_GR_PPU_SL_SCB5_BASE 0x40600180UL +#define PERI_GR_PPU_SL_SCB6_BASE 0x406001C0UL +#define PERI_GR_PPU_SL_SCB7_BASE 0x40600200UL +#define PERI_GR_PPU_SL_SCB8_BASE 0x40600240UL +#define PERI_GR_PPU_SL_PERI_GR9_BASE 0x41000000UL +#define PERI_GR_PPU_SL_PASS_BASE 0x41000040UL +#define PERI_GR_PPU_SL_PERI_GR10_BASE 0x42A00000UL +#define PERI_GR_PPU_SL_I2S_BASE 0x42A00040UL +#define PERI_GR_PPU_SL_PDM_BASE 0x42A00080UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40010000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40010000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40010040 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40010080 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x400100C0 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40010100 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x40010180 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40010240 */ +#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40010280 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40012000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40012200 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40012400 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40012600 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40012800 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40012A00 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40012C00 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40012E00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x40013000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x40013200 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x40013400 */ +#define PERI_TR_GR11 ((PERI_TR_GR_Type*) &PERI->TR_GR[11]) /* 0x40013600 */ +#define PERI_TR_GR12 ((PERI_TR_GR_Type*) &PERI->TR_GR[12]) /* 0x40013800 */ +#define PERI_TR_GR13 ((PERI_TR_GR_Type*) &PERI->TR_GR[13]) /* 0x40013A00 */ +#define PERI_TR_GR14 ((PERI_TR_GR_Type*) &PERI->TR_GR[14]) /* 0x40013C00 */ +#define PERI_PPU_PR0 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[0]) /* 0x40014000 */ +#define PERI_PPU_PR1 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[1]) /* 0x40014040 */ +#define PERI_PPU_PR2 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[2]) /* 0x40014080 */ +#define PERI_PPU_PR3 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[3]) /* 0x400140C0 */ +#define PERI_PPU_PR4 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[4]) /* 0x40014100 */ +#define PERI_PPU_PR5 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[5]) /* 0x40014140 */ +#define PERI_PPU_PR6 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[6]) /* 0x40014180 */ +#define PERI_PPU_PR7 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[7]) /* 0x400141C0 */ +#define PERI_PPU_PR8 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[8]) /* 0x40014200 */ +#define PERI_PPU_PR9 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[9]) /* 0x40014240 */ +#define PERI_PPU_PR10 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[10]) /* 0x40014280 */ +#define PERI_PPU_PR11 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[11]) /* 0x400142C0 */ +#define PERI_PPU_PR12 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[12]) /* 0x40014300 */ +#define PERI_PPU_PR13 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[13]) /* 0x40014340 */ +#define PERI_PPU_PR14 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[14]) /* 0x40014380 */ +#define PERI_PPU_PR15 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[15]) /* 0x400143C0 */ +#define PERI_PPU_GR0 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[0]) /* 0x40015000 */ +#define PERI_PPU_GR1 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[1]) /* 0x40015040 */ +#define PERI_PPU_GR2 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[2]) /* 0x40015080 */ +#define PERI_PPU_GR3 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[3]) /* 0x400150C0 */ +#define PERI_PPU_GR4 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[4]) /* 0x40015100 */ +#define PERI_PPU_GR6 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[6]) /* 0x40015180 */ +#define PERI_PPU_GR9 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[9]) /* 0x40015240 */ +#define PERI_PPU_GR10 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[10]) /* 0x40015280 */ +#define PERI_PPU_GR_MMIO0 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO0_BASE) /* 0x40015000 */ +#define PERI_PPU_GR_MMIO1 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO1_BASE) /* 0x40015040 */ +#define PERI_PPU_GR_MMIO2 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO2_BASE) /* 0x40015080 */ +#define PERI_PPU_GR_MMIO3 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO3_BASE) /* 0x400150C0 */ +#define PERI_PPU_GR_MMIO4 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO4_BASE) /* 0x40015100 */ +#define PERI_PPU_GR_MMIO6 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO6_BASE) /* 0x40015180 */ +#define PERI_PPU_GR_MMIO9 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO9_BASE) /* 0x40015240 */ +#define PERI_PPU_GR_MMIO10 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO10_BASE) /* 0x40015280 */ +#define PERI_GR_PPU_SL_PERI_GR1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR1_BASE) /* 0x40100000 */ +#define PERI_GR_PPU_SL_CRYPTO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CRYPTO_BASE) /* 0x40100040 */ +#define PERI_GR_PPU_SL_PERI_GR2 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR2_BASE) /* 0x40200000 */ +#define PERI_GR_PPU_SL_CPUSS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CPUSS_BASE) /* 0x40200040 */ +#define PERI_GR_PPU_SL_FAULT ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_FAULT_BASE) /* 0x40200080 */ +#define PERI_GR_PPU_SL_IPC ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_IPC_BASE) /* 0x402000C0 */ +#define PERI_GR_PPU_SL_PROT ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PROT_BASE) /* 0x40200100 */ +#define PERI_GR_PPU_SL_FLASHC ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_FLASHC_BASE) /* 0x40200140 */ +#define PERI_GR_PPU_SL_SRSS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SRSS_BASE) /* 0x40200180 */ +#define PERI_GR_PPU_SL_BACKUP ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_BACKUP_BASE) /* 0x402001C0 */ +#define PERI_GR_PPU_SL_DW0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_DW0_BASE) /* 0x40200200 */ +#define PERI_GR_PPU_SL_DW1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_DW1_BASE) /* 0x40200240 */ +#define PERI_GR_PPU_SL_EFUSE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_EFUSE_BASE) /* 0x40200300 */ +#define PERI_GR_PPU_SL_PROFILE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PROFILE_BASE) /* 0x40200340 */ +#define PERI_GR_PPU_RG_IPC_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT0_BASE) /* 0x40201000 */ +#define PERI_GR_PPU_RG_IPC_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT1_BASE) /* 0x40201040 */ +#define PERI_GR_PPU_RG_IPC_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT2_BASE) /* 0x40201080 */ +#define PERI_GR_PPU_RG_IPC_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT3_BASE) /* 0x402010C0 */ +#define PERI_GR_PPU_RG_IPC_STRUCT4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT4_BASE) /* 0x40201100 */ +#define PERI_GR_PPU_RG_IPC_STRUCT5 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT5_BASE) /* 0x40201140 */ +#define PERI_GR_PPU_RG_IPC_STRUCT6 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT6_BASE) /* 0x40201180 */ +#define PERI_GR_PPU_RG_IPC_STRUCT7 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT7_BASE) /* 0x402011C0 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT0_BASE) /* 0x40201200 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT1_BASE) /* 0x40201240 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT2_BASE) /* 0x40201280 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT3_BASE) /* 0x402012C0 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT4_BASE) /* 0x40201300 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT5 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT5_BASE) /* 0x40201340 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT6 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT6_BASE) /* 0x40201380 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT7 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT7_BASE) /* 0x402013C0 */ +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0_BASE) /* 0x40201400 */ +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1_BASE) /* 0x40201440 */ +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2_BASE) /* 0x40201480 */ +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3_BASE) /* 0x402014C0 */ +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0_BASE) /* 0x40201500 */ +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1_BASE) /* 0x40201540 */ +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2_BASE) /* 0x40201580 */ +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3_BASE) /* 0x402015C0 */ +#define PERI_GR_PPU_RG_SMPU ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_SMPU_BASE) /* 0x40201600 */ +#define PERI_GR_PPU_RG_MPU_CM0P ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CM0P_BASE) /* 0x40201640 */ +#define PERI_GR_PPU_RG_MPU_CRYPTO ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CRYPTO_BASE) /* 0x40201680 */ +#define PERI_GR_PPU_RG_MPU_CM4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CM4_BASE) /* 0x402016C0 */ +#define PERI_GR_PPU_RG_MPU_TC ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_TC_BASE) /* 0x40201700 */ +#define PERI_GR_PPU_SL_PERI_GR3 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR3_BASE) /* 0x40300000 */ +#define PERI_GR_PPU_SL_HSIOM ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_HSIOM_BASE) /* 0x40300040 */ +#define PERI_GR_PPU_SL_GPIO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_GPIO_BASE) /* 0x40300080 */ +#define PERI_GR_PPU_SL_SMARTIO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SMARTIO_BASE) /* 0x403000C0 */ +#define PERI_GR_PPU_SL_UDB ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_UDB_BASE) /* 0x40300100 */ +#define PERI_GR_PPU_SL_LPCOMP ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_LPCOMP_BASE) /* 0x40300140 */ +#define PERI_GR_PPU_SL_CSD ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CSD_BASE) /* 0x40300180 */ +#define PERI_GR_PPU_SL_TCPWM0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_TCPWM0_BASE) /* 0x40300200 */ +#define PERI_GR_PPU_SL_TCPWM1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_TCPWM1_BASE) /* 0x40300240 */ +#define PERI_GR_PPU_SL_LCD ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_LCD_BASE) /* 0x40300280 */ +#define PERI_GR_PPU_SL_BLE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_BLE_BASE) /* 0x403002C0 */ +#define PERI_GR_PPU_SL_USBFS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_USBFS_BASE) /* 0x40300300 */ +#define PERI_GR_PPU_SL_PERI_GR4 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR4_BASE) /* 0x40400000 */ +#define PERI_GR_PPU_SL_SMIF ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SMIF_BASE) /* 0x40400080 */ +#define PERI_GR_PPU_SL_PERI_GR6 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR6_BASE) /* 0x40600000 */ +#define PERI_GR_PPU_SL_SCB0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB0_BASE) /* 0x40600040 */ +#define PERI_GR_PPU_SL_SCB1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB1_BASE) /* 0x40600080 */ +#define PERI_GR_PPU_SL_SCB2 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB2_BASE) /* 0x406000C0 */ +#define PERI_GR_PPU_SL_SCB3 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB3_BASE) /* 0x40600100 */ +#define PERI_GR_PPU_SL_SCB4 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB4_BASE) /* 0x40600140 */ +#define PERI_GR_PPU_SL_SCB5 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB5_BASE) /* 0x40600180 */ +#define PERI_GR_PPU_SL_SCB6 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB6_BASE) /* 0x406001C0 */ +#define PERI_GR_PPU_SL_SCB7 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB7_BASE) /* 0x40600200 */ +#define PERI_GR_PPU_SL_SCB8 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB8_BASE) /* 0x40600240 */ +#define PERI_GR_PPU_SL_PERI_GR9 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR9_BASE) /* 0x41000000 */ +#define PERI_GR_PPU_SL_PASS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PASS_BASE) /* 0x41000040 */ +#define PERI_GR_PPU_SL_PERI_GR10 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR10_BASE) /* 0x42A00000 */ +#define PERI_GR_PPU_SL_I2S ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_I2S_BASE) /* 0x42A00040 */ +#define PERI_GR_PPU_SL_PDM ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PDM_BASE) /* 0x42A00080 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40110000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40110000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40210000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40210000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40220000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40220000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40220000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40220100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40230000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40230000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40230000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40230020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40230040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40230060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40230080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402300A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402300C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402300E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40230100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40230120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40230140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40230160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40230180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402301A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402301C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402301E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40231000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40231020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40231040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40231060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40231080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402310A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402310C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402310E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40231100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40231120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40231140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40231160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40231180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402311A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402311C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402311E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40240000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402420C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40242100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40242140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40242180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402421C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40242200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40242240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40242280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402422C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40242300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40244C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40245000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40245400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40245800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40245C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40246000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40246400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40246800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40246C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40247000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40250000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40250000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4025F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40281000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40281000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40280800 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40280820 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40280840 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x40280860 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40280880 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x402808A0 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x402808C0 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402808E0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40280900 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40280920 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40280940 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x40280960 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40280980 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x402809A0 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x402809C0 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402809E0 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40281800 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40281820 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40281840 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x40281860 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40281880 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x402818A0 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x402818C0 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402818E0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40281900 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40281920 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40281940 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x40281960 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40281980 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x402819A0 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x402819C0 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402819E0 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* PROFILE +*******************************************************************************/ + +#define PROFILE_BASE 0x402D0000UL +#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */ +#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */ +#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */ +#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */ +#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */ +#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */ +#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */ +#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */ +#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40310000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40310000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40310000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40310010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40310020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40310030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40310040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40310050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40310060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40310070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40310080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40310090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403100A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403100B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403100C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403100D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403100E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40320000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40320000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40320000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40320080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40320100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40320180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40320200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40320280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40320300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40320380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40320400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40320480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40320500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40320580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40320600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40320680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40320700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40330000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40330000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40330800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40330900 */ + +/******************************************************************************* +* UDB +*******************************************************************************/ + +#define UDB_BASE 0x40340000UL +#define UDB ((UDB_Type*) UDB_BASE) /* 0x40340000 */ +#define UDB_WRKONE ((UDB_WRKONE_Type*) &UDB->WRKONE) /* 0x40340000 */ +#define UDB_WRKMULT ((UDB_WRKMULT_Type*) &UDB->WRKMULT) /* 0x40341000 */ +#define UDB_UDBPAIR0_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[0]) /* 0x40342000 */ +#define UDB_UDBPAIR0_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[1]) /* 0x40342080 */ +#define UDB_UDBPAIR1_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[1].UDBSNG[0]) /* 0x40342200 */ +#define UDB_UDBPAIR1_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[1].UDBSNG[1]) /* 0x40342280 */ +#define UDB_UDBPAIR2_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[2].UDBSNG[0]) /* 0x40342400 */ +#define UDB_UDBPAIR2_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[2].UDBSNG[1]) /* 0x40342480 */ +#define UDB_UDBPAIR3_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[3].UDBSNG[0]) /* 0x40342600 */ +#define UDB_UDBPAIR3_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[3].UDBSNG[1]) /* 0x40342680 */ +#define UDB_UDBPAIR4_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[4].UDBSNG[0]) /* 0x40342800 */ +#define UDB_UDBPAIR4_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[4].UDBSNG[1]) /* 0x40342880 */ +#define UDB_UDBPAIR5_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[5].UDBSNG[0]) /* 0x40342A00 */ +#define UDB_UDBPAIR5_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[5].UDBSNG[1]) /* 0x40342A80 */ +#define UDB_UDBPAIR0_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[0].ROUTE) /* 0x40342100 */ +#define UDB_UDBPAIR1_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[1].ROUTE) /* 0x40342300 */ +#define UDB_UDBPAIR2_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[2].ROUTE) /* 0x40342500 */ +#define UDB_UDBPAIR3_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[3].ROUTE) /* 0x40342700 */ +#define UDB_UDBPAIR4_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[4].ROUTE) /* 0x40342900 */ +#define UDB_UDBPAIR5_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[5].ROUTE) /* 0x40342B00 */ +#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ +#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ +#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ +#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ +#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ +#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ +#define UDB_DSI0 ((UDB_DSI_Type*) &UDB->DSI[0]) /* 0x40346000 */ +#define UDB_DSI1 ((UDB_DSI_Type*) &UDB->DSI[1]) /* 0x40346080 */ +#define UDB_DSI2 ((UDB_DSI_Type*) &UDB->DSI[2]) /* 0x40346100 */ +#define UDB_DSI3 ((UDB_DSI_Type*) &UDB->DSI[3]) /* 0x40346180 */ +#define UDB_DSI4 ((UDB_DSI_Type*) &UDB->DSI[4]) /* 0x40346200 */ +#define UDB_DSI5 ((UDB_DSI_Type*) &UDB->DSI[5]) /* 0x40346280 */ +#define UDB_DSI6 ((UDB_DSI_Type*) &UDB->DSI[6]) /* 0x40346300 */ +#define UDB_DSI7 ((UDB_DSI_Type*) &UDB->DSI[7]) /* 0x40346380 */ +#define UDB_DSI8 ((UDB_DSI_Type*) &UDB->DSI[8]) /* 0x40346400 */ +#define UDB_DSI9 ((UDB_DSI_Type*) &UDB->DSI[9]) /* 0x40346480 */ +#define UDB_DSI10 ((UDB_DSI_Type*) &UDB->DSI[10]) /* 0x40346500 */ +#define UDB_DSI11 ((UDB_DSI_Type*) &UDB->DSI[11]) /* 0x40346580 */ +#define UDB_PA0 ((UDB_PA_Type*) &UDB->PA[0]) /* 0x40347000 */ +#define UDB_PA1 ((UDB_PA_Type*) &UDB->PA[1]) /* 0x40347040 */ +#define UDB_PA2 ((UDB_PA_Type*) &UDB->PA[2]) /* 0x40347080 */ +#define UDB_PA3 ((UDB_PA_Type*) &UDB->PA[3]) /* 0x403470C0 */ +#define UDB_PA4 ((UDB_PA_Type*) &UDB->PA[4]) /* 0x40347100 */ +#define UDB_PA5 ((UDB_PA_Type*) &UDB->PA[5]) /* 0x40347140 */ +#define UDB_PA6 ((UDB_PA_Type*) &UDB->PA[6]) /* 0x40347180 */ +#define UDB_PA7 ((UDB_PA_Type*) &UDB->PA[7]) /* 0x403471C0 */ +#define UDB_PA8 ((UDB_PA_Type*) &UDB->PA[8]) /* 0x40347200 */ +#define UDB_PA9 ((UDB_PA_Type*) &UDB->PA[9]) /* 0x40347240 */ +#define UDB_PA10 ((UDB_PA_Type*) &UDB->PA[10]) /* 0x40347280 */ +#define UDB_PA11 ((UDB_PA_Type*) &UDB->PA[11]) /* 0x403472C0 */ +#define UDB_BCTL ((UDB_BCTL_Type*) &UDB->BCTL) /* 0x40347800 */ +#define UDB_UDBIF ((UDB_UDBIF_Type*) &UDB->UDBIF) /* 0x40347900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */ +#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */ +#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */ +#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ +#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */ +#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */ +#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */ +#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */ +#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */ +#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */ +#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */ +#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */ +#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */ +#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */ +#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */ +#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */ +#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */ +#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */ +#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */ +#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* BLE +*******************************************************************************/ + +#define BLE_BASE 0x403C0000UL +#define BLE ((BLE_Type*) BLE_BASE) /* 0x403C0000 */ +#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ +#define BLE_RCB ((BLE_RCB_Type*) &BLE->RCB) /* 0x403C0000 */ +#define BLE_BLELL ((BLE_BLELL_Type*) &BLE->BLELL) /* 0x403C1000 */ +#define BLE_BLESS ((BLE_BLESS_Type*) &BLE->BLESS) /* 0x403DF000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ +#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40610000UL +#define SCB1_BASE 0x40620000UL +#define SCB2_BASE 0x40630000UL +#define SCB3_BASE 0x40640000UL +#define SCB4_BASE 0x40650000UL +#define SCB5_BASE 0x40660000UL +#define SCB6_BASE 0x40670000UL +#define SCB7_BASE 0x40680000UL +#define SCB8_BASE 0x40690000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40610000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40620000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40630000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40640000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40650000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40660000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40670000 */ +#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40680000 */ +#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40690000 */ + +/******************************************************************************* +* CTBM +*******************************************************************************/ + +#define CTBM0_BASE 0x41100000UL +#define CTBM0 ((CTBM_Type*) CTBM0_BASE) /* 0x41100000 */ + +/******************************************************************************* +* CTDAC +*******************************************************************************/ + +#define CTDAC0_BASE 0x41140000UL +#define CTDAC0 ((CTDAC_Type*) CTDAC0_BASE) /* 0x41140000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x411D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x411D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x411F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x411F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x411F0E00 */ + +/******************************************************************************* +* I2S +*******************************************************************************/ + +#define I2S0_BASE 0x42A10000UL +#define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x42A10000 */ + +/******************************************************************************* +* PDM +*******************************************************************************/ + +#define PDM0_BASE 0x42A20000UL +#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x42A20000 */ + + +/* Backward compatibility definitions */ +#define CY_SRAM0_BASE CY_SRAM_BASE +#define CY_SRAM0_SIZE CY_SRAM_SIZE +#define I2S I2S0 +#define PDM PDM0 + +/** \} CY8C6347LQI-BLD52 */ + +#endif /* _CY8C6347LQI_BLD52_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c637bzi_bld74.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c637bzi_bld74.h index d2d7bb64cf..cefe77543f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c637bzi_bld74.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c637bzi_bld74.h @@ -5,7 +5,7 @@ * CY8C637BZI-BLD74 device header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -517,7 +517,7 @@ typedef enum { #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u -#define CY_IP_MXS40PASS_SAR_INSTANCES 16u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c637bzi_md76.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c637bzi_md76.h index 6ca822bcda..3dc5218fbb 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c637bzi_md76.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c637bzi_md76.h @@ -5,7 +5,7 @@ * CY8C637BZI-MD76 device header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -514,7 +514,7 @@ typedef enum { #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u -#define CY_IP_MXS40PASS_SAR_INSTANCES 16u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c637fmi_bld73.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c637fmi_bld73.h index bf35befe39..70c9b65ab0 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c637fmi_bld73.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c637fmi_bld73.h @@ -5,7 +5,7 @@ * CY8C637FMI-BLD73 device header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -517,7 +517,7 @@ typedef enum { #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u -#define CY_IP_MXS40PASS_SAR_INSTANCES 16u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c68237bz_ble.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c68237bz_ble.h index 0f78d1181e..1ed4280b31 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c68237bz_ble.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c68237bz_ble.h @@ -5,7 +5,7 @@ * CY8C68237BZ-BLE device header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c68237fm_ble.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c68237fm_ble.h index f0039b2e25..38844106f8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c68237fm_ble.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c68237fm_ble.h @@ -5,7 +5,7 @@ * CY8C68237FM-BLE device header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy_device_common.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy_device_common.h index d91a9c6711..a815706a5d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy_device_common.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy_device_common.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_device_common.h -* \version 2.30 +* \version 2.40 * * \brief * This file provides types and IP block definitions common for all PSoC 6 @@ -177,6 +177,7 @@ typedef enum #define CY_IP_MXCRYPTO 1u #define CY_IP_MXBLESS 1u #define CY_IP_MXSDHC 1u +#define CY_IP_MXTTCANFD 1u #define CY_IP_MXAUDIOSS 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXS40PASS 1u @@ -190,6 +191,7 @@ typedef enum #define CY_IP_MXUDB 1u #define CY_IP_MXPROFILE 1u + /******************************************************************************* * Include IP Block Definitions *******************************************************************************/ @@ -238,6 +240,7 @@ typedef enum #include "ip/cyip_pass.h" #include "ip/cyip_i2s.h" #include "ip/cyip_pdm.h" +#include "ip/cyip_canfd.h" /******************************************************************************* * IP Type Definitions @@ -321,6 +324,9 @@ typedef PASS_AREF_V1_Type PASS_AREF_Type; typedef PASS_V1_Type PASS_Type; typedef PDM_V1_Type PDM_Type; typedef I2S_V1_Type I2S_Type; +typedef CANFD_V1_Type CANFD_Type; +typedef CANFD_CH_V1_Type CANFD_CH_Type; +typedef CANFD_CH_M_TTCAN_V1_Type CANFD_CH_M_TTCAN_Type; /******************************************************************************* * Symbols with External Linkage diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy_device_headers.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy_device_headers.h index 2f73431430..92e6fd4aff 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy_device_headers.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy_device_headers.h @@ -5,7 +5,7 @@ * Common header file to be included by the drivers. * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -148,12 +148,90 @@ #include "cy8c6117wi_f34.h" #elif defined (CY8C6247WI_D54) #include "cy8c6247wi_d54.h" +#elif defined (CYB06447BZI_BLD54) + #include "cyb06447bzi_bld54.h" +#elif defined (CYB06447BZI_BLD53) + #include "cyb06447bzi_bld53.h" +#elif defined (CYB06447BZI_D54) + #include "cyb06447bzi_d54.h" +#elif defined (CY8C6336LQI_BLF02) + #include "cy8c6336lqi_blf02.h" +#elif defined (CY8C6336LQI_BLF42) + #include "cy8c6336lqi_blf42.h" +#elif defined (CY8C6347LQI_BLD52) + #include "cy8c6347lqi_bld52.h" #elif defined (CY8C624ABZI_D44) #include "cy8c624abzi_d44.h" #elif defined (CY8C624AAZI_D44) #include "cy8c624aazi_d44.h" #elif defined (CY8C624AFNI_D43) #include "cy8c624afni_d43.h" +#elif defined (CY8C624ABZI_D04) + #include "cy8c624abzi_d04.h" +#elif defined (CY8C624ABZI_D14) + #include "cy8c624abzi_d14.h" +#elif defined (CY8C624AAZI_D14) + #include "cy8c624aazi_d14.h" +#elif defined (CY8C6248AZI_D14) + #include "cy8c6248azi_d14.h" +#elif defined (CY8C6248BZI_D44) + #include "cy8c6248bzi_d44.h" +#elif defined (CY8C6248AZI_D44) + #include "cy8c6248azi_d44.h" +#elif defined (CY8C6248FNI_D43) + #include "cy8c6248fni_d43.h" +#elif defined (CY8C624ALQI_D42) + #include "cy8c624alqi_d42.h" +#elif defined (CYB0644ABZI_D44) + #include "cyb0644abzi_d44.h" +#elif defined (CY8C624ABZI_S2D44A0) + #include "cy8c624abzi_s2d44a0.h" +#elif defined (CY8C624ABZI_S2D44) + #include "cy8c624abzi_s2d44.h" +#elif defined (CY8C624AAZI_S2D44) + #include "cy8c624aazi_s2d44.h" +#elif defined (CY8C624AFNI_S2D43) + #include "cy8c624afni_s2d43.h" +#elif defined (CY8C624ABZI_S2D04) + #include "cy8c624abzi_s2d04.h" +#elif defined (CY8C624ABZI_S2D14) + #include "cy8c624abzi_s2d14.h" +#elif defined (CY8C624AAZI_S2D14) + #include "cy8c624aazi_s2d14.h" +#elif defined (CY8C6248AZI_S2D14) + #include "cy8c6248azi_s2d14.h" +#elif defined (CY8C6248BZI_S2D44) + #include "cy8c6248bzi_s2d44.h" +#elif defined (CY8C6248AZI_S2D44) + #include "cy8c6248azi_s2d44.h" +#elif defined (CY8C6248FNI_S2D43) + #include "cy8c6248fni_s2d43.h" +#elif defined (CY8C6245AZI_S3D72) + #include "cy8c6245azi_s3d72.h" +#elif defined (CY8C6245LQI_S3D72) + #include "cy8c6245lqi_s3d72.h" +#elif defined (CY8C6245FNI_S3D71) + #include "cy8c6245fni_s3d71.h" +#elif defined (CY8C6245AZI_S3D62) + #include "cy8c6245azi_s3d62.h" +#elif defined (CY8C6245LQI_S3D62) + #include "cy8c6245lqi_s3d62.h" +#elif defined (CY8C6245AZI_S3D42) + #include "cy8c6245azi_s3d42.h" +#elif defined (CY8C6245LQI_S3D42) + #include "cy8c6245lqi_s3d42.h" +#elif defined (CY8C6245FNI_S3D41) + #include "cy8c6245fni_s3d41.h" +#elif defined (CY8C6245AZI_S3D12) + #include "cy8c6245azi_s3d12.h" +#elif defined (CY8C6245LQI_S3D12) + #include "cy8c6245lqi_s3d12.h" +#elif defined (CY8C6245FNI_S3D11) + #include "cy8c6245fni_s3d11.h" +#elif defined (CY8C6245AZI_S3D02) + #include "cy8c6245azi_s3d02.h" +#elif defined (CY8C6245LQI_S3D02) + #include "cy8c6245lqi_s3d02.h" #else #include "cy_device_common.h" #endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06447bzi_bld53.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06447bzi_bld53.h new file mode 100644 index 0000000000..010ae19ad9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06447bzi_bld53.h @@ -0,0 +1,1253 @@ +/***************************************************************************//** +* \file cyb06447bzi_bld53.h +* +* \brief +* CYB06447BZI-BLD53 device header +* +* \note +* Generator version: 1.5.0.1274 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CYB06447BZI_BLD53_H_ +#define _CYB06447BZI_BLD53_H_ + +/** +* \addtogroup group_device CYB06447BZI-BLD53 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + /* ARM Cortex-M0+ Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* ARM Cortex-M0+ NVIC Mux inputs. Allow routing of device interrupts to the CM0+ NVIC */ + NvicMux0_IRQn = 0, /*!< 0 [DeepSleep] CM0+ NVIC Mux input 0 */ + NvicMux1_IRQn = 1, /*!< 1 [DeepSleep] CM0+ NVIC Mux input 1 */ + NvicMux2_IRQn = 2, /*!< 2 [DeepSleep] CM0+ NVIC Mux input 2 */ + NvicMux3_IRQn = 3, /*!< 3 [DeepSleep] CM0+ NVIC Mux input 3 */ + NvicMux4_IRQn = 4, /*!< 4 [DeepSleep] CM0+ NVIC Mux input 4 */ + NvicMux5_IRQn = 5, /*!< 5 [DeepSleep] CM0+ NVIC Mux input 5 */ + NvicMux6_IRQn = 6, /*!< 6 [DeepSleep] CM0+ NVIC Mux input 6 */ + NvicMux7_IRQn = 7, /*!< 7 [DeepSleep] CM0+ NVIC Mux input 7 */ + NvicMux8_IRQn = 8, /*!< 8 [Active] CM0+ NVIC Mux input 8 */ + NvicMux9_IRQn = 9, /*!< 9 [Active] CM0+ NVIC Mux input 9 */ + NvicMux10_IRQn = 10, /*!< 10 [Active] CM0+ NVIC Mux input 10 */ + NvicMux11_IRQn = 11, /*!< 11 [Active] CM0+ NVIC Mux input 11 */ + NvicMux12_IRQn = 12, /*!< 12 [Active] CM0+ NVIC Mux input 12 */ + NvicMux13_IRQn = 13, /*!< 13 [Active] CM0+ NVIC Mux input 13 */ + NvicMux14_IRQn = 14, /*!< 14 [Active] CM0+ NVIC Mux input 14 */ + NvicMux15_IRQn = 15, /*!< 15 [Active] CM0+ NVIC Mux input 15 */ + NvicMux16_IRQn = 16, /*!< 16 [Active] CM0+ NVIC Mux input 16 */ + NvicMux17_IRQn = 17, /*!< 17 [Active] CM0+ NVIC Mux input 17 */ + NvicMux18_IRQn = 18, /*!< 18 [Active] CM0+ NVIC Mux input 18 */ + NvicMux19_IRQn = 19, /*!< 19 [Active] CM0+ NVIC Mux input 19 */ + NvicMux20_IRQn = 20, /*!< 20 [Active] CM0+ NVIC Mux input 20 */ + NvicMux21_IRQn = 21, /*!< 21 [Active] CM0+ NVIC Mux input 21 */ + NvicMux22_IRQn = 22, /*!< 22 [Active] CM0+ NVIC Mux input 22 */ + NvicMux23_IRQn = 23, /*!< 23 [Active] CM0+ NVIC Mux input 23 */ + NvicMux24_IRQn = 24, /*!< 24 [Active] CM0+ NVIC Mux input 24 */ + NvicMux25_IRQn = 25, /*!< 25 [Active] CM0+ NVIC Mux input 25 */ + NvicMux26_IRQn = 26, /*!< 26 [Active] CM0+ NVIC Mux input 26 */ + NvicMux27_IRQn = 27, /*!< 27 [Active] CM0+ NVIC Mux input 27 */ + NvicMux28_IRQn = 28, /*!< 28 [Active] CM0+ NVIC Mux input 28 */ + NvicMux29_IRQn = 29, /*!< 29 [Active] CM0+ NVIC Mux input 29 */ + NvicMux30_IRQn = 30, /*!< 30 [Active] CM0+ NVIC Mux input 30 */ + NvicMux31_IRQn = 31, /*!< 31 [Active] CM0+ NVIC Mux input 31 */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +#else + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CYB06447BZI-BLD53 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + pass_interrupt_ctbs_IRQn = 23, /*!< 23 [DeepSleep] CTBm Interrupt (all CTBms) */ + bless_interrupt_IRQn = 24, /*!< 24 [DeepSleep] Bluetooth Radio interrupt */ + cpuss_interrupts_ipc_0_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 39, /*!< 39 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 40, /*!< 40 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #7 */ + csd_interrupt_IRQn = 49, /*!< 49 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dw0_0_IRQn = 50, /*!< 50 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 51, /*!< 51 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 52, /*!< 52 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 53, /*!< 53 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 54, /*!< 54 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 55, /*!< 55 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw1_0_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_fault_0_IRQn = 82, /*!< 82 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 83, /*!< 83 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 84, /*!< 84 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 85, /*!< 85 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm0_cti_0_IRQn = 86, /*!< 86 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 87, /*!< 87 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 88, /*!< 88 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 89, /*!< 89 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 90, /*!< 90 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 91, /*!< 91 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 92, /*!< 92 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 93, /*!< 93 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 94, /*!< 94 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 95, /*!< 95 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 96, /*!< 96 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 97, /*!< 97 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 98, /*!< 98 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 99, /*!< 99 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 100, /*!< 100 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 101, /*!< 101 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 102, /*!< 102 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 103, /*!< 103 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 104, /*!< 104 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 105, /*!< 105 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 106, /*!< 106 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 107, /*!< 107 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 108, /*!< 108 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 109, /*!< 109 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 110, /*!< 110 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 111, /*!< 111 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 112, /*!< 112 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 113, /*!< 113 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 114, /*!< 114 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 115, /*!< 115 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 116, /*!< 116 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 117, /*!< 117 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 118, /*!< 118 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 119, /*!< 119 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 120, /*!< 120 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 121, /*!< 121 [Active] TCPWM #1, Counter #23 */ + udb_interrupts_0_IRQn = 122, /*!< 122 [Active] UDB Interrupt #0 */ + udb_interrupts_1_IRQn = 123, /*!< 123 [Active] UDB Interrupt #1 */ + udb_interrupts_2_IRQn = 124, /*!< 124 [Active] UDB Interrupt #2 */ + udb_interrupts_3_IRQn = 125, /*!< 125 [Active] UDB Interrupt #3 */ + udb_interrupts_4_IRQn = 126, /*!< 126 [Active] UDB Interrupt #4 */ + udb_interrupts_5_IRQn = 127, /*!< 127 [Active] UDB Interrupt #5 */ + udb_interrupts_6_IRQn = 128, /*!< 128 [Active] UDB Interrupt #6 */ + udb_interrupts_7_IRQn = 129, /*!< 129 [Active] UDB Interrupt #7 */ + udb_interrupts_8_IRQn = 130, /*!< 130 [Active] UDB Interrupt #8 */ + udb_interrupts_9_IRQn = 131, /*!< 131 [Active] UDB Interrupt #9 */ + udb_interrupts_10_IRQn = 132, /*!< 132 [Active] UDB Interrupt #10 */ + udb_interrupts_11_IRQn = 133, /*!< 133 [Active] UDB Interrupt #11 */ + udb_interrupts_12_IRQn = 134, /*!< 134 [Active] UDB Interrupt #12 */ + udb_interrupts_13_IRQn = 135, /*!< 135 [Active] UDB Interrupt #13 */ + udb_interrupts_14_IRQn = 136, /*!< 136 [Active] UDB Interrupt #14 */ + udb_interrupts_15_IRQn = 137, /*!< 137 [Active] UDB Interrupt #15 */ + pass_interrupt_sar_IRQn = 138, /*!< 138 [Active] SAR ADC interrupt */ + audioss_interrupt_i2s_IRQn = 139, /*!< 139 [Active] I2S Audio interrupt */ + audioss_interrupt_pdm_IRQn = 140, /*!< 140 [Active] PDM/PCM Audio interrupt */ + profile_interrupt_IRQn = 141, /*!< 141 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 142, /*!< 142 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 143, /*!< 143 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 144, /*!< 144 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 145, /*!< 145 [Active] USB Interrupt */ + pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +#endif +} IRQn_Type; + + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* CYB06447BZI-BLD53 interrupts that can be routed to the CM0+ NVIC */ +typedef enum { + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + pass_interrupt_ctbs_IRQn = 23, /*!< 23 [DeepSleep] CTBm Interrupt (all CTBms) */ + bless_interrupt_IRQn = 24, /*!< 24 [DeepSleep] Bluetooth Radio interrupt */ + cpuss_interrupts_ipc_0_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 39, /*!< 39 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 40, /*!< 40 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #7 */ + csd_interrupt_IRQn = 49, /*!< 49 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dw0_0_IRQn = 50, /*!< 50 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 51, /*!< 51 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 52, /*!< 52 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 53, /*!< 53 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 54, /*!< 54 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 55, /*!< 55 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw1_0_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_fault_0_IRQn = 82, /*!< 82 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 83, /*!< 83 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 84, /*!< 84 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 85, /*!< 85 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm0_cti_0_IRQn = 86, /*!< 86 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 87, /*!< 87 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 88, /*!< 88 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 89, /*!< 89 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 90, /*!< 90 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 91, /*!< 91 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 92, /*!< 92 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 93, /*!< 93 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 94, /*!< 94 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 95, /*!< 95 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 96, /*!< 96 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 97, /*!< 97 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 98, /*!< 98 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 99, /*!< 99 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 100, /*!< 100 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 101, /*!< 101 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 102, /*!< 102 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 103, /*!< 103 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 104, /*!< 104 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 105, /*!< 105 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 106, /*!< 106 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 107, /*!< 107 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 108, /*!< 108 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 109, /*!< 109 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 110, /*!< 110 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 111, /*!< 111 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 112, /*!< 112 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 113, /*!< 113 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 114, /*!< 114 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 115, /*!< 115 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 116, /*!< 116 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 117, /*!< 117 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 118, /*!< 118 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 119, /*!< 119 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 120, /*!< 120 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 121, /*!< 121 [Active] TCPWM #1, Counter #23 */ + udb_interrupts_0_IRQn = 122, /*!< 122 [Active] UDB Interrupt #0 */ + udb_interrupts_1_IRQn = 123, /*!< 123 [Active] UDB Interrupt #1 */ + udb_interrupts_2_IRQn = 124, /*!< 124 [Active] UDB Interrupt #2 */ + udb_interrupts_3_IRQn = 125, /*!< 125 [Active] UDB Interrupt #3 */ + udb_interrupts_4_IRQn = 126, /*!< 126 [Active] UDB Interrupt #4 */ + udb_interrupts_5_IRQn = 127, /*!< 127 [Active] UDB Interrupt #5 */ + udb_interrupts_6_IRQn = 128, /*!< 128 [Active] UDB Interrupt #6 */ + udb_interrupts_7_IRQn = 129, /*!< 129 [Active] UDB Interrupt #7 */ + udb_interrupts_8_IRQn = 130, /*!< 130 [Active] UDB Interrupt #8 */ + udb_interrupts_9_IRQn = 131, /*!< 131 [Active] UDB Interrupt #9 */ + udb_interrupts_10_IRQn = 132, /*!< 132 [Active] UDB Interrupt #10 */ + udb_interrupts_11_IRQn = 133, /*!< 133 [Active] UDB Interrupt #11 */ + udb_interrupts_12_IRQn = 134, /*!< 134 [Active] UDB Interrupt #12 */ + udb_interrupts_13_IRQn = 135, /*!< 135 [Active] UDB Interrupt #13 */ + udb_interrupts_14_IRQn = 136, /*!< 136 [Active] UDB Interrupt #14 */ + udb_interrupts_15_IRQn = 137, /*!< 137 [Active] UDB Interrupt #15 */ + pass_interrupt_sar_IRQn = 138, /*!< 138 [Active] SAR ADC interrupt */ + audioss_interrupt_i2s_IRQn = 139, /*!< 139 [Active] I2S Audio interrupt */ + audioss_interrupt_pdm_IRQn = 140, /*!< 140 [Active] PDM/PCM Audio interrupt */ + profile_interrupt_IRQn = 141, /*!< 141 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 142, /*!< 142 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 143, /*!< 143 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 144, /*!< 144 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 145, /*!< 145 [Active] USB Interrupt */ + pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */ + disconnected_IRQn = 240 /*!< 240 Disconnected */ +} cy_en_intr_t; + +#endif + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */ +#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ + +#else + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 1 /*!< CM0P present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + +#endif + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00020000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00048000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00100000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 1u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 1u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXS40PASS_CTDAC 1u +#define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u +#define CY_IP_MXS40PASS_CTDAC_VERSION 1u +#define CY_IP_MXS40PASS_CTB 1u +#define CY_IP_MXS40PASS_CTB_INSTANCES 1u +#define CY_IP_MXS40PASS_CTB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPROFILE 1u +#define CY_IP_MXPROFILE_INSTANCES 1u +#define CY_IP_MXPROFILE_VERSION 1u + +#include "psoc6_01_config.h" +#include "gpio_psoc6_01_116_bga_ble.h" + +#define CY_DEVICE_PSOC6ABLE2 +#define CY_SILICON_ID 0xE2612100UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40010000UL +#define PERI_PPU_GR_MMIO0_BASE 0x40015000UL +#define PERI_PPU_GR_MMIO1_BASE 0x40015040UL +#define PERI_PPU_GR_MMIO2_BASE 0x40015080UL +#define PERI_PPU_GR_MMIO3_BASE 0x400150C0UL +#define PERI_PPU_GR_MMIO4_BASE 0x40015100UL +#define PERI_PPU_GR_MMIO6_BASE 0x40015180UL +#define PERI_PPU_GR_MMIO9_BASE 0x40015240UL +#define PERI_PPU_GR_MMIO10_BASE 0x40015280UL +#define PERI_GR_PPU_SL_PERI_GR1_BASE 0x40100000UL +#define PERI_GR_PPU_SL_CRYPTO_BASE 0x40100040UL +#define PERI_GR_PPU_SL_PERI_GR2_BASE 0x40200000UL +#define PERI_GR_PPU_SL_CPUSS_BASE 0x40200040UL +#define PERI_GR_PPU_SL_FAULT_BASE 0x40200080UL +#define PERI_GR_PPU_SL_IPC_BASE 0x402000C0UL +#define PERI_GR_PPU_SL_PROT_BASE 0x40200100UL +#define PERI_GR_PPU_SL_FLASHC_BASE 0x40200140UL +#define PERI_GR_PPU_SL_SRSS_BASE 0x40200180UL +#define PERI_GR_PPU_SL_BACKUP_BASE 0x402001C0UL +#define PERI_GR_PPU_SL_DW0_BASE 0x40200200UL +#define PERI_GR_PPU_SL_DW1_BASE 0x40200240UL +#define PERI_GR_PPU_SL_EFUSE_BASE 0x40200300UL +#define PERI_GR_PPU_SL_PROFILE_BASE 0x40200340UL +#define PERI_GR_PPU_RG_IPC_STRUCT0_BASE 0x40201000UL +#define PERI_GR_PPU_RG_IPC_STRUCT1_BASE 0x40201040UL +#define PERI_GR_PPU_RG_IPC_STRUCT2_BASE 0x40201080UL +#define PERI_GR_PPU_RG_IPC_STRUCT3_BASE 0x402010C0UL +#define PERI_GR_PPU_RG_IPC_STRUCT4_BASE 0x40201100UL +#define PERI_GR_PPU_RG_IPC_STRUCT5_BASE 0x40201140UL +#define PERI_GR_PPU_RG_IPC_STRUCT6_BASE 0x40201180UL +#define PERI_GR_PPU_RG_IPC_STRUCT7_BASE 0x402011C0UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT0_BASE 0x40201200UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT1_BASE 0x40201240UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT2_BASE 0x40201280UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT3_BASE 0x402012C0UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT4_BASE 0x40201300UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT5_BASE 0x40201340UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT6_BASE 0x40201380UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT7_BASE 0x402013C0UL +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0_BASE 0x40201400UL +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1_BASE 0x40201440UL +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2_BASE 0x40201480UL +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3_BASE 0x402014C0UL +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0_BASE 0x40201500UL +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1_BASE 0x40201540UL +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2_BASE 0x40201580UL +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3_BASE 0x402015C0UL +#define PERI_GR_PPU_RG_SMPU_BASE 0x40201600UL +#define PERI_GR_PPU_RG_MPU_CM0P_BASE 0x40201640UL +#define PERI_GR_PPU_RG_MPU_CRYPTO_BASE 0x40201680UL +#define PERI_GR_PPU_RG_MPU_CM4_BASE 0x402016C0UL +#define PERI_GR_PPU_RG_MPU_TC_BASE 0x40201700UL +#define PERI_GR_PPU_SL_PERI_GR3_BASE 0x40300000UL +#define PERI_GR_PPU_SL_HSIOM_BASE 0x40300040UL +#define PERI_GR_PPU_SL_GPIO_BASE 0x40300080UL +#define PERI_GR_PPU_SL_SMARTIO_BASE 0x403000C0UL +#define PERI_GR_PPU_SL_UDB_BASE 0x40300100UL +#define PERI_GR_PPU_SL_LPCOMP_BASE 0x40300140UL +#define PERI_GR_PPU_SL_CSD_BASE 0x40300180UL +#define PERI_GR_PPU_SL_TCPWM0_BASE 0x40300200UL +#define PERI_GR_PPU_SL_TCPWM1_BASE 0x40300240UL +#define PERI_GR_PPU_SL_LCD_BASE 0x40300280UL +#define PERI_GR_PPU_SL_BLE_BASE 0x403002C0UL +#define PERI_GR_PPU_SL_USBFS_BASE 0x40300300UL +#define PERI_GR_PPU_SL_PERI_GR4_BASE 0x40400000UL +#define PERI_GR_PPU_SL_SMIF_BASE 0x40400080UL +#define PERI_GR_PPU_SL_PERI_GR6_BASE 0x40600000UL +#define PERI_GR_PPU_SL_SCB0_BASE 0x40600040UL +#define PERI_GR_PPU_SL_SCB1_BASE 0x40600080UL +#define PERI_GR_PPU_SL_SCB2_BASE 0x406000C0UL +#define PERI_GR_PPU_SL_SCB3_BASE 0x40600100UL +#define PERI_GR_PPU_SL_SCB4_BASE 0x40600140UL +#define PERI_GR_PPU_SL_SCB5_BASE 0x40600180UL +#define PERI_GR_PPU_SL_SCB6_BASE 0x406001C0UL +#define PERI_GR_PPU_SL_SCB7_BASE 0x40600200UL +#define PERI_GR_PPU_SL_SCB8_BASE 0x40600240UL +#define PERI_GR_PPU_SL_PERI_GR9_BASE 0x41000000UL +#define PERI_GR_PPU_SL_PASS_BASE 0x41000040UL +#define PERI_GR_PPU_SL_PERI_GR10_BASE 0x42A00000UL +#define PERI_GR_PPU_SL_I2S_BASE 0x42A00040UL +#define PERI_GR_PPU_SL_PDM_BASE 0x42A00080UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40010000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40010000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40010040 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40010080 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x400100C0 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40010100 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x40010180 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40010240 */ +#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40010280 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40012000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40012200 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40012400 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40012600 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40012800 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40012A00 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40012C00 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40012E00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x40013000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x40013200 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x40013400 */ +#define PERI_TR_GR11 ((PERI_TR_GR_Type*) &PERI->TR_GR[11]) /* 0x40013600 */ +#define PERI_TR_GR12 ((PERI_TR_GR_Type*) &PERI->TR_GR[12]) /* 0x40013800 */ +#define PERI_TR_GR13 ((PERI_TR_GR_Type*) &PERI->TR_GR[13]) /* 0x40013A00 */ +#define PERI_TR_GR14 ((PERI_TR_GR_Type*) &PERI->TR_GR[14]) /* 0x40013C00 */ +#define PERI_PPU_PR0 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[0]) /* 0x40014000 */ +#define PERI_PPU_PR1 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[1]) /* 0x40014040 */ +#define PERI_PPU_PR2 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[2]) /* 0x40014080 */ +#define PERI_PPU_PR3 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[3]) /* 0x400140C0 */ +#define PERI_PPU_PR4 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[4]) /* 0x40014100 */ +#define PERI_PPU_PR5 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[5]) /* 0x40014140 */ +#define PERI_PPU_PR6 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[6]) /* 0x40014180 */ +#define PERI_PPU_PR7 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[7]) /* 0x400141C0 */ +#define PERI_PPU_PR8 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[8]) /* 0x40014200 */ +#define PERI_PPU_PR9 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[9]) /* 0x40014240 */ +#define PERI_PPU_PR10 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[10]) /* 0x40014280 */ +#define PERI_PPU_PR11 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[11]) /* 0x400142C0 */ +#define PERI_PPU_PR12 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[12]) /* 0x40014300 */ +#define PERI_PPU_PR13 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[13]) /* 0x40014340 */ +#define PERI_PPU_PR14 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[14]) /* 0x40014380 */ +#define PERI_PPU_PR15 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[15]) /* 0x400143C0 */ +#define PERI_PPU_GR0 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[0]) /* 0x40015000 */ +#define PERI_PPU_GR1 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[1]) /* 0x40015040 */ +#define PERI_PPU_GR2 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[2]) /* 0x40015080 */ +#define PERI_PPU_GR3 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[3]) /* 0x400150C0 */ +#define PERI_PPU_GR4 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[4]) /* 0x40015100 */ +#define PERI_PPU_GR6 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[6]) /* 0x40015180 */ +#define PERI_PPU_GR9 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[9]) /* 0x40015240 */ +#define PERI_PPU_GR10 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[10]) /* 0x40015280 */ +#define PERI_PPU_GR_MMIO0 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO0_BASE) /* 0x40015000 */ +#define PERI_PPU_GR_MMIO1 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO1_BASE) /* 0x40015040 */ +#define PERI_PPU_GR_MMIO2 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO2_BASE) /* 0x40015080 */ +#define PERI_PPU_GR_MMIO3 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO3_BASE) /* 0x400150C0 */ +#define PERI_PPU_GR_MMIO4 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO4_BASE) /* 0x40015100 */ +#define PERI_PPU_GR_MMIO6 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO6_BASE) /* 0x40015180 */ +#define PERI_PPU_GR_MMIO9 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO9_BASE) /* 0x40015240 */ +#define PERI_PPU_GR_MMIO10 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO10_BASE) /* 0x40015280 */ +#define PERI_GR_PPU_SL_PERI_GR1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR1_BASE) /* 0x40100000 */ +#define PERI_GR_PPU_SL_CRYPTO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CRYPTO_BASE) /* 0x40100040 */ +#define PERI_GR_PPU_SL_PERI_GR2 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR2_BASE) /* 0x40200000 */ +#define PERI_GR_PPU_SL_CPUSS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CPUSS_BASE) /* 0x40200040 */ +#define PERI_GR_PPU_SL_FAULT ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_FAULT_BASE) /* 0x40200080 */ +#define PERI_GR_PPU_SL_IPC ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_IPC_BASE) /* 0x402000C0 */ +#define PERI_GR_PPU_SL_PROT ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PROT_BASE) /* 0x40200100 */ +#define PERI_GR_PPU_SL_FLASHC ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_FLASHC_BASE) /* 0x40200140 */ +#define PERI_GR_PPU_SL_SRSS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SRSS_BASE) /* 0x40200180 */ +#define PERI_GR_PPU_SL_BACKUP ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_BACKUP_BASE) /* 0x402001C0 */ +#define PERI_GR_PPU_SL_DW0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_DW0_BASE) /* 0x40200200 */ +#define PERI_GR_PPU_SL_DW1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_DW1_BASE) /* 0x40200240 */ +#define PERI_GR_PPU_SL_EFUSE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_EFUSE_BASE) /* 0x40200300 */ +#define PERI_GR_PPU_SL_PROFILE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PROFILE_BASE) /* 0x40200340 */ +#define PERI_GR_PPU_RG_IPC_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT0_BASE) /* 0x40201000 */ +#define PERI_GR_PPU_RG_IPC_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT1_BASE) /* 0x40201040 */ +#define PERI_GR_PPU_RG_IPC_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT2_BASE) /* 0x40201080 */ +#define PERI_GR_PPU_RG_IPC_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT3_BASE) /* 0x402010C0 */ +#define PERI_GR_PPU_RG_IPC_STRUCT4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT4_BASE) /* 0x40201100 */ +#define PERI_GR_PPU_RG_IPC_STRUCT5 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT5_BASE) /* 0x40201140 */ +#define PERI_GR_PPU_RG_IPC_STRUCT6 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT6_BASE) /* 0x40201180 */ +#define PERI_GR_PPU_RG_IPC_STRUCT7 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT7_BASE) /* 0x402011C0 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT0_BASE) /* 0x40201200 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT1_BASE) /* 0x40201240 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT2_BASE) /* 0x40201280 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT3_BASE) /* 0x402012C0 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT4_BASE) /* 0x40201300 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT5 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT5_BASE) /* 0x40201340 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT6 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT6_BASE) /* 0x40201380 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT7 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT7_BASE) /* 0x402013C0 */ +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0_BASE) /* 0x40201400 */ +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1_BASE) /* 0x40201440 */ +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2_BASE) /* 0x40201480 */ +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3_BASE) /* 0x402014C0 */ +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0_BASE) /* 0x40201500 */ +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1_BASE) /* 0x40201540 */ +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2_BASE) /* 0x40201580 */ +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3_BASE) /* 0x402015C0 */ +#define PERI_GR_PPU_RG_SMPU ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_SMPU_BASE) /* 0x40201600 */ +#define PERI_GR_PPU_RG_MPU_CM0P ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CM0P_BASE) /* 0x40201640 */ +#define PERI_GR_PPU_RG_MPU_CRYPTO ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CRYPTO_BASE) /* 0x40201680 */ +#define PERI_GR_PPU_RG_MPU_CM4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CM4_BASE) /* 0x402016C0 */ +#define PERI_GR_PPU_RG_MPU_TC ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_TC_BASE) /* 0x40201700 */ +#define PERI_GR_PPU_SL_PERI_GR3 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR3_BASE) /* 0x40300000 */ +#define PERI_GR_PPU_SL_HSIOM ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_HSIOM_BASE) /* 0x40300040 */ +#define PERI_GR_PPU_SL_GPIO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_GPIO_BASE) /* 0x40300080 */ +#define PERI_GR_PPU_SL_SMARTIO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SMARTIO_BASE) /* 0x403000C0 */ +#define PERI_GR_PPU_SL_UDB ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_UDB_BASE) /* 0x40300100 */ +#define PERI_GR_PPU_SL_LPCOMP ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_LPCOMP_BASE) /* 0x40300140 */ +#define PERI_GR_PPU_SL_CSD ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CSD_BASE) /* 0x40300180 */ +#define PERI_GR_PPU_SL_TCPWM0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_TCPWM0_BASE) /* 0x40300200 */ +#define PERI_GR_PPU_SL_TCPWM1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_TCPWM1_BASE) /* 0x40300240 */ +#define PERI_GR_PPU_SL_LCD ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_LCD_BASE) /* 0x40300280 */ +#define PERI_GR_PPU_SL_BLE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_BLE_BASE) /* 0x403002C0 */ +#define PERI_GR_PPU_SL_USBFS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_USBFS_BASE) /* 0x40300300 */ +#define PERI_GR_PPU_SL_PERI_GR4 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR4_BASE) /* 0x40400000 */ +#define PERI_GR_PPU_SL_SMIF ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SMIF_BASE) /* 0x40400080 */ +#define PERI_GR_PPU_SL_PERI_GR6 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR6_BASE) /* 0x40600000 */ +#define PERI_GR_PPU_SL_SCB0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB0_BASE) /* 0x40600040 */ +#define PERI_GR_PPU_SL_SCB1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB1_BASE) /* 0x40600080 */ +#define PERI_GR_PPU_SL_SCB2 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB2_BASE) /* 0x406000C0 */ +#define PERI_GR_PPU_SL_SCB3 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB3_BASE) /* 0x40600100 */ +#define PERI_GR_PPU_SL_SCB4 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB4_BASE) /* 0x40600140 */ +#define PERI_GR_PPU_SL_SCB5 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB5_BASE) /* 0x40600180 */ +#define PERI_GR_PPU_SL_SCB6 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB6_BASE) /* 0x406001C0 */ +#define PERI_GR_PPU_SL_SCB7 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB7_BASE) /* 0x40600200 */ +#define PERI_GR_PPU_SL_SCB8 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB8_BASE) /* 0x40600240 */ +#define PERI_GR_PPU_SL_PERI_GR9 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR9_BASE) /* 0x41000000 */ +#define PERI_GR_PPU_SL_PASS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PASS_BASE) /* 0x41000040 */ +#define PERI_GR_PPU_SL_PERI_GR10 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR10_BASE) /* 0x42A00000 */ +#define PERI_GR_PPU_SL_I2S ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_I2S_BASE) /* 0x42A00040 */ +#define PERI_GR_PPU_SL_PDM ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PDM_BASE) /* 0x42A00080 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40110000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40110000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40210000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40210000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40220000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40220000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40220000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40220100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40230000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40230000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40230000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40230020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40230040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40230060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40230080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402300A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402300C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402300E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40230100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40230120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40230140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40230160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40230180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402301A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402301C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402301E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40231000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40231020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40231040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40231060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40231080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402310A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402310C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402310E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40231100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40231120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40231140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40231160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40231180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402311A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402311C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402311E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40240000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402420C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40242100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40242140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40242180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402421C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40242200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40242240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40242280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402422C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40242300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40244C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40245000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40245400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40245800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40245C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40246000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40246400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40246800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40246C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40247000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40250000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40250000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4025F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40281000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40281000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40280800 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40280820 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40280840 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x40280860 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40280880 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x402808A0 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x402808C0 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402808E0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40280900 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40280920 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40280940 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x40280960 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40280980 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x402809A0 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x402809C0 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402809E0 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40281800 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40281820 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40281840 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x40281860 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40281880 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x402818A0 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x402818C0 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402818E0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40281900 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40281920 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40281940 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x40281960 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40281980 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x402819A0 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x402819C0 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402819E0 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* PROFILE +*******************************************************************************/ + +#define PROFILE_BASE 0x402D0000UL +#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */ +#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */ +#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */ +#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */ +#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */ +#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */ +#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */ +#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */ +#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40310000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40310000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40310000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40310010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40310020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40310030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40310040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40310050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40310060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40310070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40310080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40310090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403100A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403100B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403100C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403100D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403100E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40320000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40320000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40320000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40320080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40320100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40320180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40320200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40320280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40320300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40320380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40320400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40320480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40320500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40320580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40320600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40320680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40320700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40330000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40330000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40330800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40330900 */ + +/******************************************************************************* +* UDB +*******************************************************************************/ + +#define UDB_BASE 0x40340000UL +#define UDB ((UDB_Type*) UDB_BASE) /* 0x40340000 */ +#define UDB_WRKONE ((UDB_WRKONE_Type*) &UDB->WRKONE) /* 0x40340000 */ +#define UDB_WRKMULT ((UDB_WRKMULT_Type*) &UDB->WRKMULT) /* 0x40341000 */ +#define UDB_UDBPAIR0_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[0]) /* 0x40342000 */ +#define UDB_UDBPAIR0_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[1]) /* 0x40342080 */ +#define UDB_UDBPAIR1_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[1].UDBSNG[0]) /* 0x40342200 */ +#define UDB_UDBPAIR1_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[1].UDBSNG[1]) /* 0x40342280 */ +#define UDB_UDBPAIR2_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[2].UDBSNG[0]) /* 0x40342400 */ +#define UDB_UDBPAIR2_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[2].UDBSNG[1]) /* 0x40342480 */ +#define UDB_UDBPAIR3_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[3].UDBSNG[0]) /* 0x40342600 */ +#define UDB_UDBPAIR3_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[3].UDBSNG[1]) /* 0x40342680 */ +#define UDB_UDBPAIR4_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[4].UDBSNG[0]) /* 0x40342800 */ +#define UDB_UDBPAIR4_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[4].UDBSNG[1]) /* 0x40342880 */ +#define UDB_UDBPAIR5_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[5].UDBSNG[0]) /* 0x40342A00 */ +#define UDB_UDBPAIR5_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[5].UDBSNG[1]) /* 0x40342A80 */ +#define UDB_UDBPAIR0_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[0].ROUTE) /* 0x40342100 */ +#define UDB_UDBPAIR1_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[1].ROUTE) /* 0x40342300 */ +#define UDB_UDBPAIR2_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[2].ROUTE) /* 0x40342500 */ +#define UDB_UDBPAIR3_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[3].ROUTE) /* 0x40342700 */ +#define UDB_UDBPAIR4_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[4].ROUTE) /* 0x40342900 */ +#define UDB_UDBPAIR5_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[5].ROUTE) /* 0x40342B00 */ +#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ +#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ +#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ +#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ +#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ +#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ +#define UDB_DSI0 ((UDB_DSI_Type*) &UDB->DSI[0]) /* 0x40346000 */ +#define UDB_DSI1 ((UDB_DSI_Type*) &UDB->DSI[1]) /* 0x40346080 */ +#define UDB_DSI2 ((UDB_DSI_Type*) &UDB->DSI[2]) /* 0x40346100 */ +#define UDB_DSI3 ((UDB_DSI_Type*) &UDB->DSI[3]) /* 0x40346180 */ +#define UDB_DSI4 ((UDB_DSI_Type*) &UDB->DSI[4]) /* 0x40346200 */ +#define UDB_DSI5 ((UDB_DSI_Type*) &UDB->DSI[5]) /* 0x40346280 */ +#define UDB_DSI6 ((UDB_DSI_Type*) &UDB->DSI[6]) /* 0x40346300 */ +#define UDB_DSI7 ((UDB_DSI_Type*) &UDB->DSI[7]) /* 0x40346380 */ +#define UDB_DSI8 ((UDB_DSI_Type*) &UDB->DSI[8]) /* 0x40346400 */ +#define UDB_DSI9 ((UDB_DSI_Type*) &UDB->DSI[9]) /* 0x40346480 */ +#define UDB_DSI10 ((UDB_DSI_Type*) &UDB->DSI[10]) /* 0x40346500 */ +#define UDB_DSI11 ((UDB_DSI_Type*) &UDB->DSI[11]) /* 0x40346580 */ +#define UDB_PA0 ((UDB_PA_Type*) &UDB->PA[0]) /* 0x40347000 */ +#define UDB_PA1 ((UDB_PA_Type*) &UDB->PA[1]) /* 0x40347040 */ +#define UDB_PA2 ((UDB_PA_Type*) &UDB->PA[2]) /* 0x40347080 */ +#define UDB_PA3 ((UDB_PA_Type*) &UDB->PA[3]) /* 0x403470C0 */ +#define UDB_PA4 ((UDB_PA_Type*) &UDB->PA[4]) /* 0x40347100 */ +#define UDB_PA5 ((UDB_PA_Type*) &UDB->PA[5]) /* 0x40347140 */ +#define UDB_PA6 ((UDB_PA_Type*) &UDB->PA[6]) /* 0x40347180 */ +#define UDB_PA7 ((UDB_PA_Type*) &UDB->PA[7]) /* 0x403471C0 */ +#define UDB_PA8 ((UDB_PA_Type*) &UDB->PA[8]) /* 0x40347200 */ +#define UDB_PA9 ((UDB_PA_Type*) &UDB->PA[9]) /* 0x40347240 */ +#define UDB_PA10 ((UDB_PA_Type*) &UDB->PA[10]) /* 0x40347280 */ +#define UDB_PA11 ((UDB_PA_Type*) &UDB->PA[11]) /* 0x403472C0 */ +#define UDB_BCTL ((UDB_BCTL_Type*) &UDB->BCTL) /* 0x40347800 */ +#define UDB_UDBIF ((UDB_UDBIF_Type*) &UDB->UDBIF) /* 0x40347900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */ +#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */ +#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */ +#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ +#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */ +#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */ +#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */ +#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */ +#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */ +#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */ +#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */ +#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */ +#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */ +#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */ +#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */ +#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */ +#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */ +#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */ +#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */ +#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* BLE +*******************************************************************************/ + +#define BLE_BASE 0x403C0000UL +#define BLE ((BLE_Type*) BLE_BASE) /* 0x403C0000 */ +#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ +#define BLE_RCB ((BLE_RCB_Type*) &BLE->RCB) /* 0x403C0000 */ +#define BLE_BLELL ((BLE_BLELL_Type*) &BLE->BLELL) /* 0x403C1000 */ +#define BLE_BLESS ((BLE_BLESS_Type*) &BLE->BLESS) /* 0x403DF000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ +#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40610000UL +#define SCB1_BASE 0x40620000UL +#define SCB2_BASE 0x40630000UL +#define SCB3_BASE 0x40640000UL +#define SCB4_BASE 0x40650000UL +#define SCB5_BASE 0x40660000UL +#define SCB6_BASE 0x40670000UL +#define SCB7_BASE 0x40680000UL +#define SCB8_BASE 0x40690000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40610000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40620000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40630000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40640000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40650000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40660000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40670000 */ +#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40680000 */ +#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40690000 */ + +/******************************************************************************* +* CTBM +*******************************************************************************/ + +#define CTBM0_BASE 0x41100000UL +#define CTBM0 ((CTBM_Type*) CTBM0_BASE) /* 0x41100000 */ + +/******************************************************************************* +* CTDAC +*******************************************************************************/ + +#define CTDAC0_BASE 0x41140000UL +#define CTDAC0 ((CTDAC_Type*) CTDAC0_BASE) /* 0x41140000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x411D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x411D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x411F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x411F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x411F0E00 */ + +/******************************************************************************* +* I2S +*******************************************************************************/ + +#define I2S0_BASE 0x42A10000UL +#define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x42A10000 */ + +/******************************************************************************* +* PDM +*******************************************************************************/ + +#define PDM0_BASE 0x42A20000UL +#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x42A20000 */ + + +/* Backward compatibility definitions */ +#define CY_SRAM0_BASE CY_SRAM_BASE +#define CY_SRAM0_SIZE CY_SRAM_SIZE +#define I2S I2S0 +#define PDM PDM0 + +/** \} CYB06447BZI-BLD53 */ + +#endif /* _CYB06447BZI_BLD53_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06447bzi_bld54.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06447bzi_bld54.h new file mode 100644 index 0000000000..98b1cc299d --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06447bzi_bld54.h @@ -0,0 +1,1266 @@ +/***************************************************************************//** +* \file cyb06447bzi_bld54.h +* +* \brief +* CYB06447BZI-BLD54 device header +* +* \note +* Generator version: 1.5.0.1274 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CYB06447BZI_BLD54_H_ +#define _CYB06447BZI_BLD54_H_ + +/** +* \addtogroup group_device CYB06447BZI-BLD54 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + /* ARM Cortex-M0+ Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* ARM Cortex-M0+ NVIC Mux inputs. Allow routing of device interrupts to the CM0+ NVIC */ + NvicMux0_IRQn = 0, /*!< 0 [DeepSleep] CM0+ NVIC Mux input 0 */ + NvicMux1_IRQn = 1, /*!< 1 [DeepSleep] CM0+ NVIC Mux input 1 */ + NvicMux2_IRQn = 2, /*!< 2 [DeepSleep] CM0+ NVIC Mux input 2 */ + NvicMux3_IRQn = 3, /*!< 3 [DeepSleep] CM0+ NVIC Mux input 3 */ + NvicMux4_IRQn = 4, /*!< 4 [DeepSleep] CM0+ NVIC Mux input 4 */ + NvicMux5_IRQn = 5, /*!< 5 [DeepSleep] CM0+ NVIC Mux input 5 */ + NvicMux6_IRQn = 6, /*!< 6 [DeepSleep] CM0+ NVIC Mux input 6 */ + NvicMux7_IRQn = 7, /*!< 7 [DeepSleep] CM0+ NVIC Mux input 7 */ + NvicMux8_IRQn = 8, /*!< 8 [Active] CM0+ NVIC Mux input 8 */ + NvicMux9_IRQn = 9, /*!< 9 [Active] CM0+ NVIC Mux input 9 */ + NvicMux10_IRQn = 10, /*!< 10 [Active] CM0+ NVIC Mux input 10 */ + NvicMux11_IRQn = 11, /*!< 11 [Active] CM0+ NVIC Mux input 11 */ + NvicMux12_IRQn = 12, /*!< 12 [Active] CM0+ NVIC Mux input 12 */ + NvicMux13_IRQn = 13, /*!< 13 [Active] CM0+ NVIC Mux input 13 */ + NvicMux14_IRQn = 14, /*!< 14 [Active] CM0+ NVIC Mux input 14 */ + NvicMux15_IRQn = 15, /*!< 15 [Active] CM0+ NVIC Mux input 15 */ + NvicMux16_IRQn = 16, /*!< 16 [Active] CM0+ NVIC Mux input 16 */ + NvicMux17_IRQn = 17, /*!< 17 [Active] CM0+ NVIC Mux input 17 */ + NvicMux18_IRQn = 18, /*!< 18 [Active] CM0+ NVIC Mux input 18 */ + NvicMux19_IRQn = 19, /*!< 19 [Active] CM0+ NVIC Mux input 19 */ + NvicMux20_IRQn = 20, /*!< 20 [Active] CM0+ NVIC Mux input 20 */ + NvicMux21_IRQn = 21, /*!< 21 [Active] CM0+ NVIC Mux input 21 */ + NvicMux22_IRQn = 22, /*!< 22 [Active] CM0+ NVIC Mux input 22 */ + NvicMux23_IRQn = 23, /*!< 23 [Active] CM0+ NVIC Mux input 23 */ + NvicMux24_IRQn = 24, /*!< 24 [Active] CM0+ NVIC Mux input 24 */ + NvicMux25_IRQn = 25, /*!< 25 [Active] CM0+ NVIC Mux input 25 */ + NvicMux26_IRQn = 26, /*!< 26 [Active] CM0+ NVIC Mux input 26 */ + NvicMux27_IRQn = 27, /*!< 27 [Active] CM0+ NVIC Mux input 27 */ + NvicMux28_IRQn = 28, /*!< 28 [Active] CM0+ NVIC Mux input 28 */ + NvicMux29_IRQn = 29, /*!< 29 [Active] CM0+ NVIC Mux input 29 */ + NvicMux30_IRQn = 30, /*!< 30 [Active] CM0+ NVIC Mux input 30 */ + NvicMux31_IRQn = 31, /*!< 31 [Active] CM0+ NVIC Mux input 31 */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +#else + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CYB06447BZI-BLD54 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + pass_interrupt_ctbs_IRQn = 23, /*!< 23 [DeepSleep] CTBm Interrupt (all CTBms) */ + bless_interrupt_IRQn = 24, /*!< 24 [DeepSleep] Bluetooth Radio interrupt */ + cpuss_interrupts_ipc_0_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 39, /*!< 39 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 40, /*!< 40 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #7 */ + csd_interrupt_IRQn = 49, /*!< 49 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dw0_0_IRQn = 50, /*!< 50 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 51, /*!< 51 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 52, /*!< 52 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 53, /*!< 53 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 54, /*!< 54 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 55, /*!< 55 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw1_0_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_fault_0_IRQn = 82, /*!< 82 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 83, /*!< 83 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 84, /*!< 84 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 85, /*!< 85 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm0_cti_0_IRQn = 86, /*!< 86 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 87, /*!< 87 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 88, /*!< 88 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 89, /*!< 89 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 90, /*!< 90 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 91, /*!< 91 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 92, /*!< 92 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 93, /*!< 93 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 94, /*!< 94 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 95, /*!< 95 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 96, /*!< 96 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 97, /*!< 97 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 98, /*!< 98 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 99, /*!< 99 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 100, /*!< 100 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 101, /*!< 101 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 102, /*!< 102 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 103, /*!< 103 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 104, /*!< 104 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 105, /*!< 105 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 106, /*!< 106 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 107, /*!< 107 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 108, /*!< 108 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 109, /*!< 109 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 110, /*!< 110 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 111, /*!< 111 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 112, /*!< 112 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 113, /*!< 113 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 114, /*!< 114 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 115, /*!< 115 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 116, /*!< 116 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 117, /*!< 117 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 118, /*!< 118 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 119, /*!< 119 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 120, /*!< 120 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 121, /*!< 121 [Active] TCPWM #1, Counter #23 */ + udb_interrupts_0_IRQn = 122, /*!< 122 [Active] UDB Interrupt #0 */ + udb_interrupts_1_IRQn = 123, /*!< 123 [Active] UDB Interrupt #1 */ + udb_interrupts_2_IRQn = 124, /*!< 124 [Active] UDB Interrupt #2 */ + udb_interrupts_3_IRQn = 125, /*!< 125 [Active] UDB Interrupt #3 */ + udb_interrupts_4_IRQn = 126, /*!< 126 [Active] UDB Interrupt #4 */ + udb_interrupts_5_IRQn = 127, /*!< 127 [Active] UDB Interrupt #5 */ + udb_interrupts_6_IRQn = 128, /*!< 128 [Active] UDB Interrupt #6 */ + udb_interrupts_7_IRQn = 129, /*!< 129 [Active] UDB Interrupt #7 */ + udb_interrupts_8_IRQn = 130, /*!< 130 [Active] UDB Interrupt #8 */ + udb_interrupts_9_IRQn = 131, /*!< 131 [Active] UDB Interrupt #9 */ + udb_interrupts_10_IRQn = 132, /*!< 132 [Active] UDB Interrupt #10 */ + udb_interrupts_11_IRQn = 133, /*!< 133 [Active] UDB Interrupt #11 */ + udb_interrupts_12_IRQn = 134, /*!< 134 [Active] UDB Interrupt #12 */ + udb_interrupts_13_IRQn = 135, /*!< 135 [Active] UDB Interrupt #13 */ + udb_interrupts_14_IRQn = 136, /*!< 136 [Active] UDB Interrupt #14 */ + udb_interrupts_15_IRQn = 137, /*!< 137 [Active] UDB Interrupt #15 */ + pass_interrupt_sar_IRQn = 138, /*!< 138 [Active] SAR ADC interrupt */ + audioss_interrupt_i2s_IRQn = 139, /*!< 139 [Active] I2S Audio interrupt */ + audioss_interrupt_pdm_IRQn = 140, /*!< 140 [Active] PDM/PCM Audio interrupt */ + profile_interrupt_IRQn = 141, /*!< 141 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 142, /*!< 142 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 143, /*!< 143 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 144, /*!< 144 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 145, /*!< 145 [Active] USB Interrupt */ + pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +#endif +} IRQn_Type; + + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* CYB06447BZI-BLD54 interrupts that can be routed to the CM0+ NVIC */ +typedef enum { + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + pass_interrupt_ctbs_IRQn = 23, /*!< 23 [DeepSleep] CTBm Interrupt (all CTBms) */ + bless_interrupt_IRQn = 24, /*!< 24 [DeepSleep] Bluetooth Radio interrupt */ + cpuss_interrupts_ipc_0_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 39, /*!< 39 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 40, /*!< 40 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #7 */ + csd_interrupt_IRQn = 49, /*!< 49 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dw0_0_IRQn = 50, /*!< 50 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 51, /*!< 51 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 52, /*!< 52 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 53, /*!< 53 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 54, /*!< 54 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 55, /*!< 55 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw1_0_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_fault_0_IRQn = 82, /*!< 82 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 83, /*!< 83 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 84, /*!< 84 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 85, /*!< 85 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm0_cti_0_IRQn = 86, /*!< 86 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 87, /*!< 87 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 88, /*!< 88 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 89, /*!< 89 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 90, /*!< 90 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 91, /*!< 91 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 92, /*!< 92 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 93, /*!< 93 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 94, /*!< 94 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 95, /*!< 95 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 96, /*!< 96 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 97, /*!< 97 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 98, /*!< 98 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 99, /*!< 99 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 100, /*!< 100 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 101, /*!< 101 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 102, /*!< 102 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 103, /*!< 103 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 104, /*!< 104 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 105, /*!< 105 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 106, /*!< 106 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 107, /*!< 107 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 108, /*!< 108 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 109, /*!< 109 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 110, /*!< 110 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 111, /*!< 111 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 112, /*!< 112 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 113, /*!< 113 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 114, /*!< 114 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 115, /*!< 115 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 116, /*!< 116 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 117, /*!< 117 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 118, /*!< 118 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 119, /*!< 119 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 120, /*!< 120 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 121, /*!< 121 [Active] TCPWM #1, Counter #23 */ + udb_interrupts_0_IRQn = 122, /*!< 122 [Active] UDB Interrupt #0 */ + udb_interrupts_1_IRQn = 123, /*!< 123 [Active] UDB Interrupt #1 */ + udb_interrupts_2_IRQn = 124, /*!< 124 [Active] UDB Interrupt #2 */ + udb_interrupts_3_IRQn = 125, /*!< 125 [Active] UDB Interrupt #3 */ + udb_interrupts_4_IRQn = 126, /*!< 126 [Active] UDB Interrupt #4 */ + udb_interrupts_5_IRQn = 127, /*!< 127 [Active] UDB Interrupt #5 */ + udb_interrupts_6_IRQn = 128, /*!< 128 [Active] UDB Interrupt #6 */ + udb_interrupts_7_IRQn = 129, /*!< 129 [Active] UDB Interrupt #7 */ + udb_interrupts_8_IRQn = 130, /*!< 130 [Active] UDB Interrupt #8 */ + udb_interrupts_9_IRQn = 131, /*!< 131 [Active] UDB Interrupt #9 */ + udb_interrupts_10_IRQn = 132, /*!< 132 [Active] UDB Interrupt #10 */ + udb_interrupts_11_IRQn = 133, /*!< 133 [Active] UDB Interrupt #11 */ + udb_interrupts_12_IRQn = 134, /*!< 134 [Active] UDB Interrupt #12 */ + udb_interrupts_13_IRQn = 135, /*!< 135 [Active] UDB Interrupt #13 */ + udb_interrupts_14_IRQn = 136, /*!< 136 [Active] UDB Interrupt #14 */ + udb_interrupts_15_IRQn = 137, /*!< 137 [Active] UDB Interrupt #15 */ + pass_interrupt_sar_IRQn = 138, /*!< 138 [Active] SAR ADC interrupt */ + audioss_interrupt_i2s_IRQn = 139, /*!< 139 [Active] I2S Audio interrupt */ + audioss_interrupt_pdm_IRQn = 140, /*!< 140 [Active] PDM/PCM Audio interrupt */ + profile_interrupt_IRQn = 141, /*!< 141 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 142, /*!< 142 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 143, /*!< 143 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 144, /*!< 144 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 145, /*!< 145 [Active] USB Interrupt */ + pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */ + disconnected_IRQn = 240 /*!< 240 Disconnected */ +} cy_en_intr_t; + +#endif + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */ +#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ + +#else + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 1 /*!< CM0P present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + +#endif + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00020000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00048000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00100000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 1u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 1u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXS40PASS_CTDAC 1u +#define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u +#define CY_IP_MXS40PASS_CTDAC_VERSION 1u +#define CY_IP_MXS40PASS_CTB 1u +#define CY_IP_MXS40PASS_CTB_INSTANCES 1u +#define CY_IP_MXS40PASS_CTB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPROFILE 1u +#define CY_IP_MXPROFILE_INSTANCES 1u +#define CY_IP_MXPROFILE_VERSION 1u + +#include "psoc6_01_config.h" +#include "gpio_psoc6_01_124_bga_sip.h" + +#define CY_DEVICE_PSOC6ABLE2 +#define CY_SILICON_ID 0xE2602100UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40010000UL +#define PERI_PPU_GR_MMIO0_BASE 0x40015000UL +#define PERI_PPU_GR_MMIO1_BASE 0x40015040UL +#define PERI_PPU_GR_MMIO2_BASE 0x40015080UL +#define PERI_PPU_GR_MMIO3_BASE 0x400150C0UL +#define PERI_PPU_GR_MMIO4_BASE 0x40015100UL +#define PERI_PPU_GR_MMIO6_BASE 0x40015180UL +#define PERI_PPU_GR_MMIO9_BASE 0x40015240UL +#define PERI_PPU_GR_MMIO10_BASE 0x40015280UL +#define PERI_GR_PPU_SL_PERI_GR1_BASE 0x40100000UL +#define PERI_GR_PPU_SL_CRYPTO_BASE 0x40100040UL +#define PERI_GR_PPU_SL_PERI_GR2_BASE 0x40200000UL +#define PERI_GR_PPU_SL_CPUSS_BASE 0x40200040UL +#define PERI_GR_PPU_SL_FAULT_BASE 0x40200080UL +#define PERI_GR_PPU_SL_IPC_BASE 0x402000C0UL +#define PERI_GR_PPU_SL_PROT_BASE 0x40200100UL +#define PERI_GR_PPU_SL_FLASHC_BASE 0x40200140UL +#define PERI_GR_PPU_SL_SRSS_BASE 0x40200180UL +#define PERI_GR_PPU_SL_BACKUP_BASE 0x402001C0UL +#define PERI_GR_PPU_SL_DW0_BASE 0x40200200UL +#define PERI_GR_PPU_SL_DW1_BASE 0x40200240UL +#define PERI_GR_PPU_SL_EFUSE_BASE 0x40200300UL +#define PERI_GR_PPU_SL_PROFILE_BASE 0x40200340UL +#define PERI_GR_PPU_RG_IPC_STRUCT0_BASE 0x40201000UL +#define PERI_GR_PPU_RG_IPC_STRUCT1_BASE 0x40201040UL +#define PERI_GR_PPU_RG_IPC_STRUCT2_BASE 0x40201080UL +#define PERI_GR_PPU_RG_IPC_STRUCT3_BASE 0x402010C0UL +#define PERI_GR_PPU_RG_IPC_STRUCT4_BASE 0x40201100UL +#define PERI_GR_PPU_RG_IPC_STRUCT5_BASE 0x40201140UL +#define PERI_GR_PPU_RG_IPC_STRUCT6_BASE 0x40201180UL +#define PERI_GR_PPU_RG_IPC_STRUCT7_BASE 0x402011C0UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT0_BASE 0x40201200UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT1_BASE 0x40201240UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT2_BASE 0x40201280UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT3_BASE 0x402012C0UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT4_BASE 0x40201300UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT5_BASE 0x40201340UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT6_BASE 0x40201380UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT7_BASE 0x402013C0UL +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0_BASE 0x40201400UL +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1_BASE 0x40201440UL +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2_BASE 0x40201480UL +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3_BASE 0x402014C0UL +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0_BASE 0x40201500UL +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1_BASE 0x40201540UL +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2_BASE 0x40201580UL +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3_BASE 0x402015C0UL +#define PERI_GR_PPU_RG_SMPU_BASE 0x40201600UL +#define PERI_GR_PPU_RG_MPU_CM0P_BASE 0x40201640UL +#define PERI_GR_PPU_RG_MPU_CRYPTO_BASE 0x40201680UL +#define PERI_GR_PPU_RG_MPU_CM4_BASE 0x402016C0UL +#define PERI_GR_PPU_RG_MPU_TC_BASE 0x40201700UL +#define PERI_GR_PPU_SL_PERI_GR3_BASE 0x40300000UL +#define PERI_GR_PPU_SL_HSIOM_BASE 0x40300040UL +#define PERI_GR_PPU_SL_GPIO_BASE 0x40300080UL +#define PERI_GR_PPU_SL_SMARTIO_BASE 0x403000C0UL +#define PERI_GR_PPU_SL_UDB_BASE 0x40300100UL +#define PERI_GR_PPU_SL_LPCOMP_BASE 0x40300140UL +#define PERI_GR_PPU_SL_CSD_BASE 0x40300180UL +#define PERI_GR_PPU_SL_TCPWM0_BASE 0x40300200UL +#define PERI_GR_PPU_SL_TCPWM1_BASE 0x40300240UL +#define PERI_GR_PPU_SL_LCD_BASE 0x40300280UL +#define PERI_GR_PPU_SL_BLE_BASE 0x403002C0UL +#define PERI_GR_PPU_SL_USBFS_BASE 0x40300300UL +#define PERI_GR_PPU_SL_PERI_GR4_BASE 0x40400000UL +#define PERI_GR_PPU_SL_SMIF_BASE 0x40400080UL +#define PERI_GR_PPU_SL_PERI_GR6_BASE 0x40600000UL +#define PERI_GR_PPU_SL_SCB0_BASE 0x40600040UL +#define PERI_GR_PPU_SL_SCB1_BASE 0x40600080UL +#define PERI_GR_PPU_SL_SCB2_BASE 0x406000C0UL +#define PERI_GR_PPU_SL_SCB3_BASE 0x40600100UL +#define PERI_GR_PPU_SL_SCB4_BASE 0x40600140UL +#define PERI_GR_PPU_SL_SCB5_BASE 0x40600180UL +#define PERI_GR_PPU_SL_SCB6_BASE 0x406001C0UL +#define PERI_GR_PPU_SL_SCB7_BASE 0x40600200UL +#define PERI_GR_PPU_SL_SCB8_BASE 0x40600240UL +#define PERI_GR_PPU_SL_PERI_GR9_BASE 0x41000000UL +#define PERI_GR_PPU_SL_PASS_BASE 0x41000040UL +#define PERI_GR_PPU_SL_PERI_GR10_BASE 0x42A00000UL +#define PERI_GR_PPU_SL_I2S_BASE 0x42A00040UL +#define PERI_GR_PPU_SL_PDM_BASE 0x42A00080UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40010000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40010000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40010040 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40010080 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x400100C0 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40010100 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x40010180 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40010240 */ +#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40010280 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40012000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40012200 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40012400 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40012600 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40012800 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40012A00 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40012C00 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40012E00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x40013000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x40013200 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x40013400 */ +#define PERI_TR_GR11 ((PERI_TR_GR_Type*) &PERI->TR_GR[11]) /* 0x40013600 */ +#define PERI_TR_GR12 ((PERI_TR_GR_Type*) &PERI->TR_GR[12]) /* 0x40013800 */ +#define PERI_TR_GR13 ((PERI_TR_GR_Type*) &PERI->TR_GR[13]) /* 0x40013A00 */ +#define PERI_TR_GR14 ((PERI_TR_GR_Type*) &PERI->TR_GR[14]) /* 0x40013C00 */ +#define PERI_PPU_PR0 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[0]) /* 0x40014000 */ +#define PERI_PPU_PR1 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[1]) /* 0x40014040 */ +#define PERI_PPU_PR2 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[2]) /* 0x40014080 */ +#define PERI_PPU_PR3 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[3]) /* 0x400140C0 */ +#define PERI_PPU_PR4 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[4]) /* 0x40014100 */ +#define PERI_PPU_PR5 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[5]) /* 0x40014140 */ +#define PERI_PPU_PR6 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[6]) /* 0x40014180 */ +#define PERI_PPU_PR7 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[7]) /* 0x400141C0 */ +#define PERI_PPU_PR8 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[8]) /* 0x40014200 */ +#define PERI_PPU_PR9 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[9]) /* 0x40014240 */ +#define PERI_PPU_PR10 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[10]) /* 0x40014280 */ +#define PERI_PPU_PR11 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[11]) /* 0x400142C0 */ +#define PERI_PPU_PR12 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[12]) /* 0x40014300 */ +#define PERI_PPU_PR13 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[13]) /* 0x40014340 */ +#define PERI_PPU_PR14 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[14]) /* 0x40014380 */ +#define PERI_PPU_PR15 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[15]) /* 0x400143C0 */ +#define PERI_PPU_GR0 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[0]) /* 0x40015000 */ +#define PERI_PPU_GR1 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[1]) /* 0x40015040 */ +#define PERI_PPU_GR2 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[2]) /* 0x40015080 */ +#define PERI_PPU_GR3 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[3]) /* 0x400150C0 */ +#define PERI_PPU_GR4 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[4]) /* 0x40015100 */ +#define PERI_PPU_GR6 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[6]) /* 0x40015180 */ +#define PERI_PPU_GR9 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[9]) /* 0x40015240 */ +#define PERI_PPU_GR10 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[10]) /* 0x40015280 */ +#define PERI_PPU_GR_MMIO0 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO0_BASE) /* 0x40015000 */ +#define PERI_PPU_GR_MMIO1 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO1_BASE) /* 0x40015040 */ +#define PERI_PPU_GR_MMIO2 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO2_BASE) /* 0x40015080 */ +#define PERI_PPU_GR_MMIO3 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO3_BASE) /* 0x400150C0 */ +#define PERI_PPU_GR_MMIO4 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO4_BASE) /* 0x40015100 */ +#define PERI_PPU_GR_MMIO6 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO6_BASE) /* 0x40015180 */ +#define PERI_PPU_GR_MMIO9 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO9_BASE) /* 0x40015240 */ +#define PERI_PPU_GR_MMIO10 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO10_BASE) /* 0x40015280 */ +#define PERI_GR_PPU_SL_PERI_GR1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR1_BASE) /* 0x40100000 */ +#define PERI_GR_PPU_SL_CRYPTO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CRYPTO_BASE) /* 0x40100040 */ +#define PERI_GR_PPU_SL_PERI_GR2 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR2_BASE) /* 0x40200000 */ +#define PERI_GR_PPU_SL_CPUSS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CPUSS_BASE) /* 0x40200040 */ +#define PERI_GR_PPU_SL_FAULT ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_FAULT_BASE) /* 0x40200080 */ +#define PERI_GR_PPU_SL_IPC ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_IPC_BASE) /* 0x402000C0 */ +#define PERI_GR_PPU_SL_PROT ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PROT_BASE) /* 0x40200100 */ +#define PERI_GR_PPU_SL_FLASHC ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_FLASHC_BASE) /* 0x40200140 */ +#define PERI_GR_PPU_SL_SRSS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SRSS_BASE) /* 0x40200180 */ +#define PERI_GR_PPU_SL_BACKUP ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_BACKUP_BASE) /* 0x402001C0 */ +#define PERI_GR_PPU_SL_DW0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_DW0_BASE) /* 0x40200200 */ +#define PERI_GR_PPU_SL_DW1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_DW1_BASE) /* 0x40200240 */ +#define PERI_GR_PPU_SL_EFUSE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_EFUSE_BASE) /* 0x40200300 */ +#define PERI_GR_PPU_SL_PROFILE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PROFILE_BASE) /* 0x40200340 */ +#define PERI_GR_PPU_RG_IPC_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT0_BASE) /* 0x40201000 */ +#define PERI_GR_PPU_RG_IPC_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT1_BASE) /* 0x40201040 */ +#define PERI_GR_PPU_RG_IPC_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT2_BASE) /* 0x40201080 */ +#define PERI_GR_PPU_RG_IPC_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT3_BASE) /* 0x402010C0 */ +#define PERI_GR_PPU_RG_IPC_STRUCT4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT4_BASE) /* 0x40201100 */ +#define PERI_GR_PPU_RG_IPC_STRUCT5 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT5_BASE) /* 0x40201140 */ +#define PERI_GR_PPU_RG_IPC_STRUCT6 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT6_BASE) /* 0x40201180 */ +#define PERI_GR_PPU_RG_IPC_STRUCT7 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT7_BASE) /* 0x402011C0 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT0_BASE) /* 0x40201200 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT1_BASE) /* 0x40201240 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT2_BASE) /* 0x40201280 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT3_BASE) /* 0x402012C0 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT4_BASE) /* 0x40201300 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT5 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT5_BASE) /* 0x40201340 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT6 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT6_BASE) /* 0x40201380 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT7 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT7_BASE) /* 0x402013C0 */ +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0_BASE) /* 0x40201400 */ +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1_BASE) /* 0x40201440 */ +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2_BASE) /* 0x40201480 */ +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3_BASE) /* 0x402014C0 */ +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0_BASE) /* 0x40201500 */ +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1_BASE) /* 0x40201540 */ +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2_BASE) /* 0x40201580 */ +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3_BASE) /* 0x402015C0 */ +#define PERI_GR_PPU_RG_SMPU ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_SMPU_BASE) /* 0x40201600 */ +#define PERI_GR_PPU_RG_MPU_CM0P ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CM0P_BASE) /* 0x40201640 */ +#define PERI_GR_PPU_RG_MPU_CRYPTO ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CRYPTO_BASE) /* 0x40201680 */ +#define PERI_GR_PPU_RG_MPU_CM4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CM4_BASE) /* 0x402016C0 */ +#define PERI_GR_PPU_RG_MPU_TC ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_TC_BASE) /* 0x40201700 */ +#define PERI_GR_PPU_SL_PERI_GR3 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR3_BASE) /* 0x40300000 */ +#define PERI_GR_PPU_SL_HSIOM ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_HSIOM_BASE) /* 0x40300040 */ +#define PERI_GR_PPU_SL_GPIO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_GPIO_BASE) /* 0x40300080 */ +#define PERI_GR_PPU_SL_SMARTIO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SMARTIO_BASE) /* 0x403000C0 */ +#define PERI_GR_PPU_SL_UDB ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_UDB_BASE) /* 0x40300100 */ +#define PERI_GR_PPU_SL_LPCOMP ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_LPCOMP_BASE) /* 0x40300140 */ +#define PERI_GR_PPU_SL_CSD ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CSD_BASE) /* 0x40300180 */ +#define PERI_GR_PPU_SL_TCPWM0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_TCPWM0_BASE) /* 0x40300200 */ +#define PERI_GR_PPU_SL_TCPWM1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_TCPWM1_BASE) /* 0x40300240 */ +#define PERI_GR_PPU_SL_LCD ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_LCD_BASE) /* 0x40300280 */ +#define PERI_GR_PPU_SL_BLE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_BLE_BASE) /* 0x403002C0 */ +#define PERI_GR_PPU_SL_USBFS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_USBFS_BASE) /* 0x40300300 */ +#define PERI_GR_PPU_SL_PERI_GR4 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR4_BASE) /* 0x40400000 */ +#define PERI_GR_PPU_SL_SMIF ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SMIF_BASE) /* 0x40400080 */ +#define PERI_GR_PPU_SL_PERI_GR6 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR6_BASE) /* 0x40600000 */ +#define PERI_GR_PPU_SL_SCB0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB0_BASE) /* 0x40600040 */ +#define PERI_GR_PPU_SL_SCB1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB1_BASE) /* 0x40600080 */ +#define PERI_GR_PPU_SL_SCB2 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB2_BASE) /* 0x406000C0 */ +#define PERI_GR_PPU_SL_SCB3 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB3_BASE) /* 0x40600100 */ +#define PERI_GR_PPU_SL_SCB4 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB4_BASE) /* 0x40600140 */ +#define PERI_GR_PPU_SL_SCB5 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB5_BASE) /* 0x40600180 */ +#define PERI_GR_PPU_SL_SCB6 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB6_BASE) /* 0x406001C0 */ +#define PERI_GR_PPU_SL_SCB7 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB7_BASE) /* 0x40600200 */ +#define PERI_GR_PPU_SL_SCB8 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB8_BASE) /* 0x40600240 */ +#define PERI_GR_PPU_SL_PERI_GR9 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR9_BASE) /* 0x41000000 */ +#define PERI_GR_PPU_SL_PASS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PASS_BASE) /* 0x41000040 */ +#define PERI_GR_PPU_SL_PERI_GR10 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR10_BASE) /* 0x42A00000 */ +#define PERI_GR_PPU_SL_I2S ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_I2S_BASE) /* 0x42A00040 */ +#define PERI_GR_PPU_SL_PDM ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PDM_BASE) /* 0x42A00080 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40110000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40110000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40210000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40210000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40220000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40220000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40220000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40220100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40230000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40230000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40230000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40230020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40230040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40230060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40230080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402300A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402300C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402300E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40230100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40230120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40230140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40230160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40230180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402301A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402301C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402301E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40231000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40231020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40231040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40231060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40231080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402310A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402310C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402310E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40231100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40231120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40231140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40231160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40231180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402311A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402311C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402311E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40240000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402420C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40242100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40242140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40242180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402421C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40242200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40242240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40242280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402422C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40242300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40244C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40245000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40245400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40245800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40245C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40246000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40246400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40246800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40246C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40247000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40250000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40250000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4025F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40281000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40281000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40280800 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40280820 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40280840 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x40280860 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40280880 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x402808A0 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x402808C0 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402808E0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40280900 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40280920 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40280940 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x40280960 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40280980 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x402809A0 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x402809C0 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402809E0 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40281800 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40281820 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40281840 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x40281860 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40281880 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x402818A0 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x402818C0 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402818E0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40281900 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40281920 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40281940 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x40281960 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40281980 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x402819A0 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x402819C0 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402819E0 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* PROFILE +*******************************************************************************/ + +#define PROFILE_BASE 0x402D0000UL +#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */ +#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */ +#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */ +#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */ +#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */ +#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */ +#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */ +#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */ +#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40310000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40310000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40310000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40310010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40310020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40310030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40310040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40310050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40310060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40310070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40310080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40310090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403100A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403100B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403100C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403100D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403100E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40320000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40320000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40320000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40320080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40320100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40320180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40320200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40320280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40320300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40320380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40320400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40320480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40320500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40320580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40320600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40320680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40320700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40330000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40330000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40330800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40330900 */ + +/******************************************************************************* +* UDB +*******************************************************************************/ + +#define UDB_BASE 0x40340000UL +#define UDB ((UDB_Type*) UDB_BASE) /* 0x40340000 */ +#define UDB_WRKONE ((UDB_WRKONE_Type*) &UDB->WRKONE) /* 0x40340000 */ +#define UDB_WRKMULT ((UDB_WRKMULT_Type*) &UDB->WRKMULT) /* 0x40341000 */ +#define UDB_UDBPAIR0_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[0]) /* 0x40342000 */ +#define UDB_UDBPAIR0_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[1]) /* 0x40342080 */ +#define UDB_UDBPAIR1_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[1].UDBSNG[0]) /* 0x40342200 */ +#define UDB_UDBPAIR1_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[1].UDBSNG[1]) /* 0x40342280 */ +#define UDB_UDBPAIR2_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[2].UDBSNG[0]) /* 0x40342400 */ +#define UDB_UDBPAIR2_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[2].UDBSNG[1]) /* 0x40342480 */ +#define UDB_UDBPAIR3_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[3].UDBSNG[0]) /* 0x40342600 */ +#define UDB_UDBPAIR3_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[3].UDBSNG[1]) /* 0x40342680 */ +#define UDB_UDBPAIR4_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[4].UDBSNG[0]) /* 0x40342800 */ +#define UDB_UDBPAIR4_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[4].UDBSNG[1]) /* 0x40342880 */ +#define UDB_UDBPAIR5_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[5].UDBSNG[0]) /* 0x40342A00 */ +#define UDB_UDBPAIR5_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[5].UDBSNG[1]) /* 0x40342A80 */ +#define UDB_UDBPAIR0_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[0].ROUTE) /* 0x40342100 */ +#define UDB_UDBPAIR1_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[1].ROUTE) /* 0x40342300 */ +#define UDB_UDBPAIR2_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[2].ROUTE) /* 0x40342500 */ +#define UDB_UDBPAIR3_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[3].ROUTE) /* 0x40342700 */ +#define UDB_UDBPAIR4_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[4].ROUTE) /* 0x40342900 */ +#define UDB_UDBPAIR5_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[5].ROUTE) /* 0x40342B00 */ +#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ +#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ +#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ +#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ +#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ +#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ +#define UDB_DSI0 ((UDB_DSI_Type*) &UDB->DSI[0]) /* 0x40346000 */ +#define UDB_DSI1 ((UDB_DSI_Type*) &UDB->DSI[1]) /* 0x40346080 */ +#define UDB_DSI2 ((UDB_DSI_Type*) &UDB->DSI[2]) /* 0x40346100 */ +#define UDB_DSI3 ((UDB_DSI_Type*) &UDB->DSI[3]) /* 0x40346180 */ +#define UDB_DSI4 ((UDB_DSI_Type*) &UDB->DSI[4]) /* 0x40346200 */ +#define UDB_DSI5 ((UDB_DSI_Type*) &UDB->DSI[5]) /* 0x40346280 */ +#define UDB_DSI6 ((UDB_DSI_Type*) &UDB->DSI[6]) /* 0x40346300 */ +#define UDB_DSI7 ((UDB_DSI_Type*) &UDB->DSI[7]) /* 0x40346380 */ +#define UDB_DSI8 ((UDB_DSI_Type*) &UDB->DSI[8]) /* 0x40346400 */ +#define UDB_DSI9 ((UDB_DSI_Type*) &UDB->DSI[9]) /* 0x40346480 */ +#define UDB_DSI10 ((UDB_DSI_Type*) &UDB->DSI[10]) /* 0x40346500 */ +#define UDB_DSI11 ((UDB_DSI_Type*) &UDB->DSI[11]) /* 0x40346580 */ +#define UDB_PA0 ((UDB_PA_Type*) &UDB->PA[0]) /* 0x40347000 */ +#define UDB_PA1 ((UDB_PA_Type*) &UDB->PA[1]) /* 0x40347040 */ +#define UDB_PA2 ((UDB_PA_Type*) &UDB->PA[2]) /* 0x40347080 */ +#define UDB_PA3 ((UDB_PA_Type*) &UDB->PA[3]) /* 0x403470C0 */ +#define UDB_PA4 ((UDB_PA_Type*) &UDB->PA[4]) /* 0x40347100 */ +#define UDB_PA5 ((UDB_PA_Type*) &UDB->PA[5]) /* 0x40347140 */ +#define UDB_PA6 ((UDB_PA_Type*) &UDB->PA[6]) /* 0x40347180 */ +#define UDB_PA7 ((UDB_PA_Type*) &UDB->PA[7]) /* 0x403471C0 */ +#define UDB_PA8 ((UDB_PA_Type*) &UDB->PA[8]) /* 0x40347200 */ +#define UDB_PA9 ((UDB_PA_Type*) &UDB->PA[9]) /* 0x40347240 */ +#define UDB_PA10 ((UDB_PA_Type*) &UDB->PA[10]) /* 0x40347280 */ +#define UDB_PA11 ((UDB_PA_Type*) &UDB->PA[11]) /* 0x403472C0 */ +#define UDB_BCTL ((UDB_BCTL_Type*) &UDB->BCTL) /* 0x40347800 */ +#define UDB_UDBIF ((UDB_UDBIF_Type*) &UDB->UDBIF) /* 0x40347900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */ +#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */ +#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */ +#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ +#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */ +#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */ +#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */ +#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */ +#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */ +#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */ +#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */ +#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */ +#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */ +#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */ +#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */ +#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */ +#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */ +#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */ +#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */ +#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* BLE +*******************************************************************************/ + +#define BLE_BASE 0x403C0000UL +#define BLE ((BLE_Type*) BLE_BASE) /* 0x403C0000 */ +#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ +#define BLE_RCB ((BLE_RCB_Type*) &BLE->RCB) /* 0x403C0000 */ +#define BLE_BLELL ((BLE_BLELL_Type*) &BLE->BLELL) /* 0x403C1000 */ +#define BLE_BLESS ((BLE_BLESS_Type*) &BLE->BLESS) /* 0x403DF000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ +#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40610000UL +#define SCB1_BASE 0x40620000UL +#define SCB2_BASE 0x40630000UL +#define SCB3_BASE 0x40640000UL +#define SCB4_BASE 0x40650000UL +#define SCB5_BASE 0x40660000UL +#define SCB6_BASE 0x40670000UL +#define SCB7_BASE 0x40680000UL +#define SCB8_BASE 0x40690000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40610000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40620000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40630000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40640000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40650000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40660000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40670000 */ +#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40680000 */ +#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40690000 */ + +/******************************************************************************* +* CTBM +*******************************************************************************/ + +#define CTBM0_BASE 0x41100000UL +#define CTBM0 ((CTBM_Type*) CTBM0_BASE) /* 0x41100000 */ + +/******************************************************************************* +* CTDAC +*******************************************************************************/ + +#define CTDAC0_BASE 0x41140000UL +#define CTDAC0 ((CTDAC_Type*) CTDAC0_BASE) /* 0x41140000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x411D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x411D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x411F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x411F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x411F0E00 */ + +/******************************************************************************* +* I2S +*******************************************************************************/ + +#define I2S0_BASE 0x42A10000UL +#define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x42A10000 */ + +/******************************************************************************* +* PDM +*******************************************************************************/ + +#define PDM0_BASE 0x42A20000UL +#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x42A20000 */ + + +/* Backward compatibility definitions */ +#define CY_SRAM0_BASE CY_SRAM_BASE +#define CY_SRAM0_SIZE CY_SRAM_SIZE +#define I2S I2S0 +#define PDM PDM0 + +/** \} CYB06447BZI-BLD54 */ + +#endif /* _CYB06447BZI_BLD54_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06447bzi_d54.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06447bzi_d54.h new file mode 100644 index 0000000000..b15abfe7a1 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06447bzi_d54.h @@ -0,0 +1,1252 @@ +/***************************************************************************//** +* \file cyb06447bzi_d54.h +* +* \brief +* CYB06447BZI-D54 device header +* +* \note +* Generator version: 1.5.0.1274 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CYB06447BZI_D54_H_ +#define _CYB06447BZI_D54_H_ + +/** +* \addtogroup group_device CYB06447BZI-D54 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + /* ARM Cortex-M0+ Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* ARM Cortex-M0+ NVIC Mux inputs. Allow routing of device interrupts to the CM0+ NVIC */ + NvicMux0_IRQn = 0, /*!< 0 [DeepSleep] CM0+ NVIC Mux input 0 */ + NvicMux1_IRQn = 1, /*!< 1 [DeepSleep] CM0+ NVIC Mux input 1 */ + NvicMux2_IRQn = 2, /*!< 2 [DeepSleep] CM0+ NVIC Mux input 2 */ + NvicMux3_IRQn = 3, /*!< 3 [DeepSleep] CM0+ NVIC Mux input 3 */ + NvicMux4_IRQn = 4, /*!< 4 [DeepSleep] CM0+ NVIC Mux input 4 */ + NvicMux5_IRQn = 5, /*!< 5 [DeepSleep] CM0+ NVIC Mux input 5 */ + NvicMux6_IRQn = 6, /*!< 6 [DeepSleep] CM0+ NVIC Mux input 6 */ + NvicMux7_IRQn = 7, /*!< 7 [DeepSleep] CM0+ NVIC Mux input 7 */ + NvicMux8_IRQn = 8, /*!< 8 [Active] CM0+ NVIC Mux input 8 */ + NvicMux9_IRQn = 9, /*!< 9 [Active] CM0+ NVIC Mux input 9 */ + NvicMux10_IRQn = 10, /*!< 10 [Active] CM0+ NVIC Mux input 10 */ + NvicMux11_IRQn = 11, /*!< 11 [Active] CM0+ NVIC Mux input 11 */ + NvicMux12_IRQn = 12, /*!< 12 [Active] CM0+ NVIC Mux input 12 */ + NvicMux13_IRQn = 13, /*!< 13 [Active] CM0+ NVIC Mux input 13 */ + NvicMux14_IRQn = 14, /*!< 14 [Active] CM0+ NVIC Mux input 14 */ + NvicMux15_IRQn = 15, /*!< 15 [Active] CM0+ NVIC Mux input 15 */ + NvicMux16_IRQn = 16, /*!< 16 [Active] CM0+ NVIC Mux input 16 */ + NvicMux17_IRQn = 17, /*!< 17 [Active] CM0+ NVIC Mux input 17 */ + NvicMux18_IRQn = 18, /*!< 18 [Active] CM0+ NVIC Mux input 18 */ + NvicMux19_IRQn = 19, /*!< 19 [Active] CM0+ NVIC Mux input 19 */ + NvicMux20_IRQn = 20, /*!< 20 [Active] CM0+ NVIC Mux input 20 */ + NvicMux21_IRQn = 21, /*!< 21 [Active] CM0+ NVIC Mux input 21 */ + NvicMux22_IRQn = 22, /*!< 22 [Active] CM0+ NVIC Mux input 22 */ + NvicMux23_IRQn = 23, /*!< 23 [Active] CM0+ NVIC Mux input 23 */ + NvicMux24_IRQn = 24, /*!< 24 [Active] CM0+ NVIC Mux input 24 */ + NvicMux25_IRQn = 25, /*!< 25 [Active] CM0+ NVIC Mux input 25 */ + NvicMux26_IRQn = 26, /*!< 26 [Active] CM0+ NVIC Mux input 26 */ + NvicMux27_IRQn = 27, /*!< 27 [Active] CM0+ NVIC Mux input 27 */ + NvicMux28_IRQn = 28, /*!< 28 [Active] CM0+ NVIC Mux input 28 */ + NvicMux29_IRQn = 29, /*!< 29 [Active] CM0+ NVIC Mux input 29 */ + NvicMux30_IRQn = 30, /*!< 30 [Active] CM0+ NVIC Mux input 30 */ + NvicMux31_IRQn = 31, /*!< 31 [Active] CM0+ NVIC Mux input 31 */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +#else + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CYB06447BZI-D54 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + pass_interrupt_ctbs_IRQn = 23, /*!< 23 [DeepSleep] CTBm Interrupt (all CTBms) */ + bless_interrupt_IRQn = 24, /*!< 24 [DeepSleep] Bluetooth Radio interrupt */ + cpuss_interrupts_ipc_0_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 39, /*!< 39 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 40, /*!< 40 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #7 */ + csd_interrupt_IRQn = 49, /*!< 49 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dw0_0_IRQn = 50, /*!< 50 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 51, /*!< 51 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 52, /*!< 52 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 53, /*!< 53 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 54, /*!< 54 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 55, /*!< 55 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw1_0_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_fault_0_IRQn = 82, /*!< 82 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 83, /*!< 83 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 84, /*!< 84 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 85, /*!< 85 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm0_cti_0_IRQn = 86, /*!< 86 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 87, /*!< 87 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 88, /*!< 88 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 89, /*!< 89 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 90, /*!< 90 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 91, /*!< 91 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 92, /*!< 92 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 93, /*!< 93 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 94, /*!< 94 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 95, /*!< 95 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 96, /*!< 96 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 97, /*!< 97 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 98, /*!< 98 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 99, /*!< 99 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 100, /*!< 100 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 101, /*!< 101 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 102, /*!< 102 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 103, /*!< 103 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 104, /*!< 104 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 105, /*!< 105 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 106, /*!< 106 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 107, /*!< 107 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 108, /*!< 108 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 109, /*!< 109 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 110, /*!< 110 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 111, /*!< 111 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 112, /*!< 112 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 113, /*!< 113 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 114, /*!< 114 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 115, /*!< 115 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 116, /*!< 116 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 117, /*!< 117 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 118, /*!< 118 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 119, /*!< 119 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 120, /*!< 120 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 121, /*!< 121 [Active] TCPWM #1, Counter #23 */ + udb_interrupts_0_IRQn = 122, /*!< 122 [Active] UDB Interrupt #0 */ + udb_interrupts_1_IRQn = 123, /*!< 123 [Active] UDB Interrupt #1 */ + udb_interrupts_2_IRQn = 124, /*!< 124 [Active] UDB Interrupt #2 */ + udb_interrupts_3_IRQn = 125, /*!< 125 [Active] UDB Interrupt #3 */ + udb_interrupts_4_IRQn = 126, /*!< 126 [Active] UDB Interrupt #4 */ + udb_interrupts_5_IRQn = 127, /*!< 127 [Active] UDB Interrupt #5 */ + udb_interrupts_6_IRQn = 128, /*!< 128 [Active] UDB Interrupt #6 */ + udb_interrupts_7_IRQn = 129, /*!< 129 [Active] UDB Interrupt #7 */ + udb_interrupts_8_IRQn = 130, /*!< 130 [Active] UDB Interrupt #8 */ + udb_interrupts_9_IRQn = 131, /*!< 131 [Active] UDB Interrupt #9 */ + udb_interrupts_10_IRQn = 132, /*!< 132 [Active] UDB Interrupt #10 */ + udb_interrupts_11_IRQn = 133, /*!< 133 [Active] UDB Interrupt #11 */ + udb_interrupts_12_IRQn = 134, /*!< 134 [Active] UDB Interrupt #12 */ + udb_interrupts_13_IRQn = 135, /*!< 135 [Active] UDB Interrupt #13 */ + udb_interrupts_14_IRQn = 136, /*!< 136 [Active] UDB Interrupt #14 */ + udb_interrupts_15_IRQn = 137, /*!< 137 [Active] UDB Interrupt #15 */ + pass_interrupt_sar_IRQn = 138, /*!< 138 [Active] SAR ADC interrupt */ + audioss_interrupt_i2s_IRQn = 139, /*!< 139 [Active] I2S Audio interrupt */ + audioss_interrupt_pdm_IRQn = 140, /*!< 140 [Active] PDM/PCM Audio interrupt */ + profile_interrupt_IRQn = 141, /*!< 141 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 142, /*!< 142 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 143, /*!< 143 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 144, /*!< 144 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 145, /*!< 145 [Active] USB Interrupt */ + pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +#endif +} IRQn_Type; + + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* CYB06447BZI-D54 interrupts that can be routed to the CM0+ NVIC */ +typedef enum { + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + pass_interrupt_ctbs_IRQn = 23, /*!< 23 [DeepSleep] CTBm Interrupt (all CTBms) */ + bless_interrupt_IRQn = 24, /*!< 24 [DeepSleep] Bluetooth Radio interrupt */ + cpuss_interrupts_ipc_0_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 39, /*!< 39 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 40, /*!< 40 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #7 */ + csd_interrupt_IRQn = 49, /*!< 49 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dw0_0_IRQn = 50, /*!< 50 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 51, /*!< 51 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 52, /*!< 52 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 53, /*!< 53 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 54, /*!< 54 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 55, /*!< 55 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw1_0_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_fault_0_IRQn = 82, /*!< 82 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 83, /*!< 83 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 84, /*!< 84 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 85, /*!< 85 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm0_cti_0_IRQn = 86, /*!< 86 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 87, /*!< 87 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 88, /*!< 88 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 89, /*!< 89 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 90, /*!< 90 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 91, /*!< 91 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 92, /*!< 92 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 93, /*!< 93 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 94, /*!< 94 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 95, /*!< 95 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 96, /*!< 96 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 97, /*!< 97 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 98, /*!< 98 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 99, /*!< 99 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 100, /*!< 100 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 101, /*!< 101 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 102, /*!< 102 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 103, /*!< 103 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 104, /*!< 104 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 105, /*!< 105 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 106, /*!< 106 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 107, /*!< 107 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 108, /*!< 108 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 109, /*!< 109 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 110, /*!< 110 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 111, /*!< 111 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 112, /*!< 112 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 113, /*!< 113 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 114, /*!< 114 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 115, /*!< 115 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 116, /*!< 116 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 117, /*!< 117 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 118, /*!< 118 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 119, /*!< 119 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 120, /*!< 120 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 121, /*!< 121 [Active] TCPWM #1, Counter #23 */ + udb_interrupts_0_IRQn = 122, /*!< 122 [Active] UDB Interrupt #0 */ + udb_interrupts_1_IRQn = 123, /*!< 123 [Active] UDB Interrupt #1 */ + udb_interrupts_2_IRQn = 124, /*!< 124 [Active] UDB Interrupt #2 */ + udb_interrupts_3_IRQn = 125, /*!< 125 [Active] UDB Interrupt #3 */ + udb_interrupts_4_IRQn = 126, /*!< 126 [Active] UDB Interrupt #4 */ + udb_interrupts_5_IRQn = 127, /*!< 127 [Active] UDB Interrupt #5 */ + udb_interrupts_6_IRQn = 128, /*!< 128 [Active] UDB Interrupt #6 */ + udb_interrupts_7_IRQn = 129, /*!< 129 [Active] UDB Interrupt #7 */ + udb_interrupts_8_IRQn = 130, /*!< 130 [Active] UDB Interrupt #8 */ + udb_interrupts_9_IRQn = 131, /*!< 131 [Active] UDB Interrupt #9 */ + udb_interrupts_10_IRQn = 132, /*!< 132 [Active] UDB Interrupt #10 */ + udb_interrupts_11_IRQn = 133, /*!< 133 [Active] UDB Interrupt #11 */ + udb_interrupts_12_IRQn = 134, /*!< 134 [Active] UDB Interrupt #12 */ + udb_interrupts_13_IRQn = 135, /*!< 135 [Active] UDB Interrupt #13 */ + udb_interrupts_14_IRQn = 136, /*!< 136 [Active] UDB Interrupt #14 */ + udb_interrupts_15_IRQn = 137, /*!< 137 [Active] UDB Interrupt #15 */ + pass_interrupt_sar_IRQn = 138, /*!< 138 [Active] SAR ADC interrupt */ + audioss_interrupt_i2s_IRQn = 139, /*!< 139 [Active] I2S Audio interrupt */ + audioss_interrupt_pdm_IRQn = 140, /*!< 140 [Active] PDM/PCM Audio interrupt */ + profile_interrupt_IRQn = 141, /*!< 141 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 142, /*!< 142 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 143, /*!< 143 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 144, /*!< 144 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 145, /*!< 145 [Active] USB Interrupt */ + pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */ + disconnected_IRQn = 240 /*!< 240 Disconnected */ +} cy_en_intr_t; + +#endif + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */ +#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ + +#else + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 1 /*!< CM0P present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + +#endif + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00020000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00048000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00100000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 1u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 1u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXS40PASS_CTDAC 1u +#define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u +#define CY_IP_MXS40PASS_CTDAC_VERSION 1u +#define CY_IP_MXS40PASS_CTB 1u +#define CY_IP_MXS40PASS_CTB_INSTANCES 1u +#define CY_IP_MXS40PASS_CTB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPROFILE 1u +#define CY_IP_MXPROFILE_INSTANCES 1u +#define CY_IP_MXPROFILE_VERSION 1u + +#include "psoc6_01_config.h" +#include "gpio_psoc6_01_124_bga.h" + +#define CY_DEVICE_PSOC6ABLE2 +#define CY_SILICON_ID 0xE2622100UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40010000UL +#define PERI_PPU_GR_MMIO0_BASE 0x40015000UL +#define PERI_PPU_GR_MMIO1_BASE 0x40015040UL +#define PERI_PPU_GR_MMIO2_BASE 0x40015080UL +#define PERI_PPU_GR_MMIO3_BASE 0x400150C0UL +#define PERI_PPU_GR_MMIO4_BASE 0x40015100UL +#define PERI_PPU_GR_MMIO6_BASE 0x40015180UL +#define PERI_PPU_GR_MMIO9_BASE 0x40015240UL +#define PERI_PPU_GR_MMIO10_BASE 0x40015280UL +#define PERI_GR_PPU_SL_PERI_GR1_BASE 0x40100000UL +#define PERI_GR_PPU_SL_CRYPTO_BASE 0x40100040UL +#define PERI_GR_PPU_SL_PERI_GR2_BASE 0x40200000UL +#define PERI_GR_PPU_SL_CPUSS_BASE 0x40200040UL +#define PERI_GR_PPU_SL_FAULT_BASE 0x40200080UL +#define PERI_GR_PPU_SL_IPC_BASE 0x402000C0UL +#define PERI_GR_PPU_SL_PROT_BASE 0x40200100UL +#define PERI_GR_PPU_SL_FLASHC_BASE 0x40200140UL +#define PERI_GR_PPU_SL_SRSS_BASE 0x40200180UL +#define PERI_GR_PPU_SL_BACKUP_BASE 0x402001C0UL +#define PERI_GR_PPU_SL_DW0_BASE 0x40200200UL +#define PERI_GR_PPU_SL_DW1_BASE 0x40200240UL +#define PERI_GR_PPU_SL_EFUSE_BASE 0x40200300UL +#define PERI_GR_PPU_SL_PROFILE_BASE 0x40200340UL +#define PERI_GR_PPU_RG_IPC_STRUCT0_BASE 0x40201000UL +#define PERI_GR_PPU_RG_IPC_STRUCT1_BASE 0x40201040UL +#define PERI_GR_PPU_RG_IPC_STRUCT2_BASE 0x40201080UL +#define PERI_GR_PPU_RG_IPC_STRUCT3_BASE 0x402010C0UL +#define PERI_GR_PPU_RG_IPC_STRUCT4_BASE 0x40201100UL +#define PERI_GR_PPU_RG_IPC_STRUCT5_BASE 0x40201140UL +#define PERI_GR_PPU_RG_IPC_STRUCT6_BASE 0x40201180UL +#define PERI_GR_PPU_RG_IPC_STRUCT7_BASE 0x402011C0UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT0_BASE 0x40201200UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT1_BASE 0x40201240UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT2_BASE 0x40201280UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT3_BASE 0x402012C0UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT4_BASE 0x40201300UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT5_BASE 0x40201340UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT6_BASE 0x40201380UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT7_BASE 0x402013C0UL +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0_BASE 0x40201400UL +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1_BASE 0x40201440UL +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2_BASE 0x40201480UL +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3_BASE 0x402014C0UL +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0_BASE 0x40201500UL +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1_BASE 0x40201540UL +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2_BASE 0x40201580UL +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3_BASE 0x402015C0UL +#define PERI_GR_PPU_RG_SMPU_BASE 0x40201600UL +#define PERI_GR_PPU_RG_MPU_CM0P_BASE 0x40201640UL +#define PERI_GR_PPU_RG_MPU_CRYPTO_BASE 0x40201680UL +#define PERI_GR_PPU_RG_MPU_CM4_BASE 0x402016C0UL +#define PERI_GR_PPU_RG_MPU_TC_BASE 0x40201700UL +#define PERI_GR_PPU_SL_PERI_GR3_BASE 0x40300000UL +#define PERI_GR_PPU_SL_HSIOM_BASE 0x40300040UL +#define PERI_GR_PPU_SL_GPIO_BASE 0x40300080UL +#define PERI_GR_PPU_SL_SMARTIO_BASE 0x403000C0UL +#define PERI_GR_PPU_SL_UDB_BASE 0x40300100UL +#define PERI_GR_PPU_SL_LPCOMP_BASE 0x40300140UL +#define PERI_GR_PPU_SL_CSD_BASE 0x40300180UL +#define PERI_GR_PPU_SL_TCPWM0_BASE 0x40300200UL +#define PERI_GR_PPU_SL_TCPWM1_BASE 0x40300240UL +#define PERI_GR_PPU_SL_LCD_BASE 0x40300280UL +#define PERI_GR_PPU_SL_BLE_BASE 0x403002C0UL +#define PERI_GR_PPU_SL_USBFS_BASE 0x40300300UL +#define PERI_GR_PPU_SL_PERI_GR4_BASE 0x40400000UL +#define PERI_GR_PPU_SL_SMIF_BASE 0x40400080UL +#define PERI_GR_PPU_SL_PERI_GR6_BASE 0x40600000UL +#define PERI_GR_PPU_SL_SCB0_BASE 0x40600040UL +#define PERI_GR_PPU_SL_SCB1_BASE 0x40600080UL +#define PERI_GR_PPU_SL_SCB2_BASE 0x406000C0UL +#define PERI_GR_PPU_SL_SCB3_BASE 0x40600100UL +#define PERI_GR_PPU_SL_SCB4_BASE 0x40600140UL +#define PERI_GR_PPU_SL_SCB5_BASE 0x40600180UL +#define PERI_GR_PPU_SL_SCB6_BASE 0x406001C0UL +#define PERI_GR_PPU_SL_SCB7_BASE 0x40600200UL +#define PERI_GR_PPU_SL_SCB8_BASE 0x40600240UL +#define PERI_GR_PPU_SL_PERI_GR9_BASE 0x41000000UL +#define PERI_GR_PPU_SL_PASS_BASE 0x41000040UL +#define PERI_GR_PPU_SL_PERI_GR10_BASE 0x42A00000UL +#define PERI_GR_PPU_SL_I2S_BASE 0x42A00040UL +#define PERI_GR_PPU_SL_PDM_BASE 0x42A00080UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40010000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40010000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40010040 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40010080 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x400100C0 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40010100 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x40010180 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40010240 */ +#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40010280 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40012000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40012200 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40012400 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40012600 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40012800 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40012A00 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40012C00 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40012E00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x40013000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x40013200 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x40013400 */ +#define PERI_TR_GR11 ((PERI_TR_GR_Type*) &PERI->TR_GR[11]) /* 0x40013600 */ +#define PERI_TR_GR12 ((PERI_TR_GR_Type*) &PERI->TR_GR[12]) /* 0x40013800 */ +#define PERI_TR_GR13 ((PERI_TR_GR_Type*) &PERI->TR_GR[13]) /* 0x40013A00 */ +#define PERI_TR_GR14 ((PERI_TR_GR_Type*) &PERI->TR_GR[14]) /* 0x40013C00 */ +#define PERI_PPU_PR0 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[0]) /* 0x40014000 */ +#define PERI_PPU_PR1 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[1]) /* 0x40014040 */ +#define PERI_PPU_PR2 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[2]) /* 0x40014080 */ +#define PERI_PPU_PR3 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[3]) /* 0x400140C0 */ +#define PERI_PPU_PR4 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[4]) /* 0x40014100 */ +#define PERI_PPU_PR5 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[5]) /* 0x40014140 */ +#define PERI_PPU_PR6 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[6]) /* 0x40014180 */ +#define PERI_PPU_PR7 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[7]) /* 0x400141C0 */ +#define PERI_PPU_PR8 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[8]) /* 0x40014200 */ +#define PERI_PPU_PR9 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[9]) /* 0x40014240 */ +#define PERI_PPU_PR10 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[10]) /* 0x40014280 */ +#define PERI_PPU_PR11 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[11]) /* 0x400142C0 */ +#define PERI_PPU_PR12 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[12]) /* 0x40014300 */ +#define PERI_PPU_PR13 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[13]) /* 0x40014340 */ +#define PERI_PPU_PR14 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[14]) /* 0x40014380 */ +#define PERI_PPU_PR15 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[15]) /* 0x400143C0 */ +#define PERI_PPU_GR0 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[0]) /* 0x40015000 */ +#define PERI_PPU_GR1 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[1]) /* 0x40015040 */ +#define PERI_PPU_GR2 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[2]) /* 0x40015080 */ +#define PERI_PPU_GR3 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[3]) /* 0x400150C0 */ +#define PERI_PPU_GR4 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[4]) /* 0x40015100 */ +#define PERI_PPU_GR6 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[6]) /* 0x40015180 */ +#define PERI_PPU_GR9 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[9]) /* 0x40015240 */ +#define PERI_PPU_GR10 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[10]) /* 0x40015280 */ +#define PERI_PPU_GR_MMIO0 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO0_BASE) /* 0x40015000 */ +#define PERI_PPU_GR_MMIO1 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO1_BASE) /* 0x40015040 */ +#define PERI_PPU_GR_MMIO2 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO2_BASE) /* 0x40015080 */ +#define PERI_PPU_GR_MMIO3 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO3_BASE) /* 0x400150C0 */ +#define PERI_PPU_GR_MMIO4 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO4_BASE) /* 0x40015100 */ +#define PERI_PPU_GR_MMIO6 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO6_BASE) /* 0x40015180 */ +#define PERI_PPU_GR_MMIO9 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO9_BASE) /* 0x40015240 */ +#define PERI_PPU_GR_MMIO10 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO10_BASE) /* 0x40015280 */ +#define PERI_GR_PPU_SL_PERI_GR1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR1_BASE) /* 0x40100000 */ +#define PERI_GR_PPU_SL_CRYPTO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CRYPTO_BASE) /* 0x40100040 */ +#define PERI_GR_PPU_SL_PERI_GR2 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR2_BASE) /* 0x40200000 */ +#define PERI_GR_PPU_SL_CPUSS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CPUSS_BASE) /* 0x40200040 */ +#define PERI_GR_PPU_SL_FAULT ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_FAULT_BASE) /* 0x40200080 */ +#define PERI_GR_PPU_SL_IPC ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_IPC_BASE) /* 0x402000C0 */ +#define PERI_GR_PPU_SL_PROT ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PROT_BASE) /* 0x40200100 */ +#define PERI_GR_PPU_SL_FLASHC ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_FLASHC_BASE) /* 0x40200140 */ +#define PERI_GR_PPU_SL_SRSS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SRSS_BASE) /* 0x40200180 */ +#define PERI_GR_PPU_SL_BACKUP ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_BACKUP_BASE) /* 0x402001C0 */ +#define PERI_GR_PPU_SL_DW0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_DW0_BASE) /* 0x40200200 */ +#define PERI_GR_PPU_SL_DW1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_DW1_BASE) /* 0x40200240 */ +#define PERI_GR_PPU_SL_EFUSE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_EFUSE_BASE) /* 0x40200300 */ +#define PERI_GR_PPU_SL_PROFILE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PROFILE_BASE) /* 0x40200340 */ +#define PERI_GR_PPU_RG_IPC_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT0_BASE) /* 0x40201000 */ +#define PERI_GR_PPU_RG_IPC_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT1_BASE) /* 0x40201040 */ +#define PERI_GR_PPU_RG_IPC_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT2_BASE) /* 0x40201080 */ +#define PERI_GR_PPU_RG_IPC_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT3_BASE) /* 0x402010C0 */ +#define PERI_GR_PPU_RG_IPC_STRUCT4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT4_BASE) /* 0x40201100 */ +#define PERI_GR_PPU_RG_IPC_STRUCT5 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT5_BASE) /* 0x40201140 */ +#define PERI_GR_PPU_RG_IPC_STRUCT6 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT6_BASE) /* 0x40201180 */ +#define PERI_GR_PPU_RG_IPC_STRUCT7 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT7_BASE) /* 0x402011C0 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT0_BASE) /* 0x40201200 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT1_BASE) /* 0x40201240 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT2_BASE) /* 0x40201280 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT3_BASE) /* 0x402012C0 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT4_BASE) /* 0x40201300 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT5 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT5_BASE) /* 0x40201340 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT6 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT6_BASE) /* 0x40201380 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT7 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT7_BASE) /* 0x402013C0 */ +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0_BASE) /* 0x40201400 */ +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1_BASE) /* 0x40201440 */ +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2_BASE) /* 0x40201480 */ +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3_BASE) /* 0x402014C0 */ +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0_BASE) /* 0x40201500 */ +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1_BASE) /* 0x40201540 */ +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2_BASE) /* 0x40201580 */ +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3_BASE) /* 0x402015C0 */ +#define PERI_GR_PPU_RG_SMPU ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_SMPU_BASE) /* 0x40201600 */ +#define PERI_GR_PPU_RG_MPU_CM0P ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CM0P_BASE) /* 0x40201640 */ +#define PERI_GR_PPU_RG_MPU_CRYPTO ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CRYPTO_BASE) /* 0x40201680 */ +#define PERI_GR_PPU_RG_MPU_CM4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CM4_BASE) /* 0x402016C0 */ +#define PERI_GR_PPU_RG_MPU_TC ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_TC_BASE) /* 0x40201700 */ +#define PERI_GR_PPU_SL_PERI_GR3 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR3_BASE) /* 0x40300000 */ +#define PERI_GR_PPU_SL_HSIOM ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_HSIOM_BASE) /* 0x40300040 */ +#define PERI_GR_PPU_SL_GPIO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_GPIO_BASE) /* 0x40300080 */ +#define PERI_GR_PPU_SL_SMARTIO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SMARTIO_BASE) /* 0x403000C0 */ +#define PERI_GR_PPU_SL_UDB ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_UDB_BASE) /* 0x40300100 */ +#define PERI_GR_PPU_SL_LPCOMP ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_LPCOMP_BASE) /* 0x40300140 */ +#define PERI_GR_PPU_SL_CSD ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CSD_BASE) /* 0x40300180 */ +#define PERI_GR_PPU_SL_TCPWM0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_TCPWM0_BASE) /* 0x40300200 */ +#define PERI_GR_PPU_SL_TCPWM1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_TCPWM1_BASE) /* 0x40300240 */ +#define PERI_GR_PPU_SL_LCD ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_LCD_BASE) /* 0x40300280 */ +#define PERI_GR_PPU_SL_BLE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_BLE_BASE) /* 0x403002C0 */ +#define PERI_GR_PPU_SL_USBFS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_USBFS_BASE) /* 0x40300300 */ +#define PERI_GR_PPU_SL_PERI_GR4 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR4_BASE) /* 0x40400000 */ +#define PERI_GR_PPU_SL_SMIF ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SMIF_BASE) /* 0x40400080 */ +#define PERI_GR_PPU_SL_PERI_GR6 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR6_BASE) /* 0x40600000 */ +#define PERI_GR_PPU_SL_SCB0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB0_BASE) /* 0x40600040 */ +#define PERI_GR_PPU_SL_SCB1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB1_BASE) /* 0x40600080 */ +#define PERI_GR_PPU_SL_SCB2 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB2_BASE) /* 0x406000C0 */ +#define PERI_GR_PPU_SL_SCB3 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB3_BASE) /* 0x40600100 */ +#define PERI_GR_PPU_SL_SCB4 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB4_BASE) /* 0x40600140 */ +#define PERI_GR_PPU_SL_SCB5 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB5_BASE) /* 0x40600180 */ +#define PERI_GR_PPU_SL_SCB6 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB6_BASE) /* 0x406001C0 */ +#define PERI_GR_PPU_SL_SCB7 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB7_BASE) /* 0x40600200 */ +#define PERI_GR_PPU_SL_SCB8 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB8_BASE) /* 0x40600240 */ +#define PERI_GR_PPU_SL_PERI_GR9 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR9_BASE) /* 0x41000000 */ +#define PERI_GR_PPU_SL_PASS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PASS_BASE) /* 0x41000040 */ +#define PERI_GR_PPU_SL_PERI_GR10 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR10_BASE) /* 0x42A00000 */ +#define PERI_GR_PPU_SL_I2S ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_I2S_BASE) /* 0x42A00040 */ +#define PERI_GR_PPU_SL_PDM ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PDM_BASE) /* 0x42A00080 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40110000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40110000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40210000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40210000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40220000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40220000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40220000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40220100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40230000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40230000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40230000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40230020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40230040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40230060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40230080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402300A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402300C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402300E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40230100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40230120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40230140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40230160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40230180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402301A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402301C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402301E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40231000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40231020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40231040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40231060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40231080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402310A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402310C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402310E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40231100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40231120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40231140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40231160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40231180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402311A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402311C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402311E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40240000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402420C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40242100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40242140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40242180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402421C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40242200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40242240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40242280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402422C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40242300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40244C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40245000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40245400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40245800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40245C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40246000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40246400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40246800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40246C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40247000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40250000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40250000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4025F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40281000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40281000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40280800 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40280820 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40280840 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x40280860 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40280880 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x402808A0 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x402808C0 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402808E0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40280900 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40280920 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40280940 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x40280960 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40280980 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x402809A0 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x402809C0 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402809E0 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40281800 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40281820 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40281840 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x40281860 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40281880 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x402818A0 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x402818C0 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402818E0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40281900 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40281920 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40281940 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x40281960 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40281980 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x402819A0 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x402819C0 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402819E0 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* PROFILE +*******************************************************************************/ + +#define PROFILE_BASE 0x402D0000UL +#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */ +#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */ +#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */ +#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */ +#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */ +#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */ +#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */ +#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */ +#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40310000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40310000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40310000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40310010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40310020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40310030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40310040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40310050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40310060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40310070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40310080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40310090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403100A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403100B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403100C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403100D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403100E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40320000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40320000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40320000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40320080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40320100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40320180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40320200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40320280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40320300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40320380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40320400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40320480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40320500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40320580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40320600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40320680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40320700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40330000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40330000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40330800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40330900 */ + +/******************************************************************************* +* UDB +*******************************************************************************/ + +#define UDB_BASE 0x40340000UL +#define UDB ((UDB_Type*) UDB_BASE) /* 0x40340000 */ +#define UDB_WRKONE ((UDB_WRKONE_Type*) &UDB->WRKONE) /* 0x40340000 */ +#define UDB_WRKMULT ((UDB_WRKMULT_Type*) &UDB->WRKMULT) /* 0x40341000 */ +#define UDB_UDBPAIR0_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[0]) /* 0x40342000 */ +#define UDB_UDBPAIR0_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[1]) /* 0x40342080 */ +#define UDB_UDBPAIR1_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[1].UDBSNG[0]) /* 0x40342200 */ +#define UDB_UDBPAIR1_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[1].UDBSNG[1]) /* 0x40342280 */ +#define UDB_UDBPAIR2_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[2].UDBSNG[0]) /* 0x40342400 */ +#define UDB_UDBPAIR2_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[2].UDBSNG[1]) /* 0x40342480 */ +#define UDB_UDBPAIR3_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[3].UDBSNG[0]) /* 0x40342600 */ +#define UDB_UDBPAIR3_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[3].UDBSNG[1]) /* 0x40342680 */ +#define UDB_UDBPAIR4_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[4].UDBSNG[0]) /* 0x40342800 */ +#define UDB_UDBPAIR4_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[4].UDBSNG[1]) /* 0x40342880 */ +#define UDB_UDBPAIR5_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[5].UDBSNG[0]) /* 0x40342A00 */ +#define UDB_UDBPAIR5_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[5].UDBSNG[1]) /* 0x40342A80 */ +#define UDB_UDBPAIR0_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[0].ROUTE) /* 0x40342100 */ +#define UDB_UDBPAIR1_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[1].ROUTE) /* 0x40342300 */ +#define UDB_UDBPAIR2_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[2].ROUTE) /* 0x40342500 */ +#define UDB_UDBPAIR3_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[3].ROUTE) /* 0x40342700 */ +#define UDB_UDBPAIR4_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[4].ROUTE) /* 0x40342900 */ +#define UDB_UDBPAIR5_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[5].ROUTE) /* 0x40342B00 */ +#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ +#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ +#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ +#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ +#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ +#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ +#define UDB_DSI0 ((UDB_DSI_Type*) &UDB->DSI[0]) /* 0x40346000 */ +#define UDB_DSI1 ((UDB_DSI_Type*) &UDB->DSI[1]) /* 0x40346080 */ +#define UDB_DSI2 ((UDB_DSI_Type*) &UDB->DSI[2]) /* 0x40346100 */ +#define UDB_DSI3 ((UDB_DSI_Type*) &UDB->DSI[3]) /* 0x40346180 */ +#define UDB_DSI4 ((UDB_DSI_Type*) &UDB->DSI[4]) /* 0x40346200 */ +#define UDB_DSI5 ((UDB_DSI_Type*) &UDB->DSI[5]) /* 0x40346280 */ +#define UDB_DSI6 ((UDB_DSI_Type*) &UDB->DSI[6]) /* 0x40346300 */ +#define UDB_DSI7 ((UDB_DSI_Type*) &UDB->DSI[7]) /* 0x40346380 */ +#define UDB_DSI8 ((UDB_DSI_Type*) &UDB->DSI[8]) /* 0x40346400 */ +#define UDB_DSI9 ((UDB_DSI_Type*) &UDB->DSI[9]) /* 0x40346480 */ +#define UDB_DSI10 ((UDB_DSI_Type*) &UDB->DSI[10]) /* 0x40346500 */ +#define UDB_DSI11 ((UDB_DSI_Type*) &UDB->DSI[11]) /* 0x40346580 */ +#define UDB_PA0 ((UDB_PA_Type*) &UDB->PA[0]) /* 0x40347000 */ +#define UDB_PA1 ((UDB_PA_Type*) &UDB->PA[1]) /* 0x40347040 */ +#define UDB_PA2 ((UDB_PA_Type*) &UDB->PA[2]) /* 0x40347080 */ +#define UDB_PA3 ((UDB_PA_Type*) &UDB->PA[3]) /* 0x403470C0 */ +#define UDB_PA4 ((UDB_PA_Type*) &UDB->PA[4]) /* 0x40347100 */ +#define UDB_PA5 ((UDB_PA_Type*) &UDB->PA[5]) /* 0x40347140 */ +#define UDB_PA6 ((UDB_PA_Type*) &UDB->PA[6]) /* 0x40347180 */ +#define UDB_PA7 ((UDB_PA_Type*) &UDB->PA[7]) /* 0x403471C0 */ +#define UDB_PA8 ((UDB_PA_Type*) &UDB->PA[8]) /* 0x40347200 */ +#define UDB_PA9 ((UDB_PA_Type*) &UDB->PA[9]) /* 0x40347240 */ +#define UDB_PA10 ((UDB_PA_Type*) &UDB->PA[10]) /* 0x40347280 */ +#define UDB_PA11 ((UDB_PA_Type*) &UDB->PA[11]) /* 0x403472C0 */ +#define UDB_BCTL ((UDB_BCTL_Type*) &UDB->BCTL) /* 0x40347800 */ +#define UDB_UDBIF ((UDB_UDBIF_Type*) &UDB->UDBIF) /* 0x40347900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */ +#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */ +#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */ +#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ +#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */ +#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */ +#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */ +#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */ +#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */ +#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */ +#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */ +#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */ +#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */ +#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */ +#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */ +#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */ +#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */ +#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */ +#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */ +#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ +#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40610000UL +#define SCB1_BASE 0x40620000UL +#define SCB2_BASE 0x40630000UL +#define SCB3_BASE 0x40640000UL +#define SCB4_BASE 0x40650000UL +#define SCB5_BASE 0x40660000UL +#define SCB6_BASE 0x40670000UL +#define SCB7_BASE 0x40680000UL +#define SCB8_BASE 0x40690000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40610000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40620000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40630000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40640000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40650000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40660000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40670000 */ +#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40680000 */ +#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40690000 */ + +/******************************************************************************* +* CTBM +*******************************************************************************/ + +#define CTBM0_BASE 0x41100000UL +#define CTBM0 ((CTBM_Type*) CTBM0_BASE) /* 0x41100000 */ + +/******************************************************************************* +* CTDAC +*******************************************************************************/ + +#define CTDAC0_BASE 0x41140000UL +#define CTDAC0 ((CTDAC_Type*) CTDAC0_BASE) /* 0x41140000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x411D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x411D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x411F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x411F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x411F0E00 */ + +/******************************************************************************* +* I2S +*******************************************************************************/ + +#define I2S0_BASE 0x42A10000UL +#define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x42A10000 */ + +/******************************************************************************* +* PDM +*******************************************************************************/ + +#define PDM0_BASE 0x42A20000UL +#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x42A20000 */ + + +/* Backward compatibility definitions */ +#define CY_SRAM0_BASE CY_SRAM_BASE +#define CY_SRAM0_SIZE CY_SRAM_SIZE +#define I2S I2S0 +#define PDM PDM0 + +/** \} CYB06447BZI-D54 */ + +#endif /* _CYB06447BZI_D54_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb0644abzi_d44.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb0644abzi_d44.h new file mode 100644 index 0000000000..da828d3d7e --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb0644abzi_d44.h @@ -0,0 +1,1326 @@ +/***************************************************************************//** +* \file cyb0644abzi_d44.h +* +* \brief +* CYB0644ABZI-D44 device header +* +* \note +* Generator version: 1.5.0.1274 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CYB0644ABZI_D44_H_ +#define _CYB0644ABZI_D44_H_ + +/** +* \addtogroup group_device CYB0644ABZI-D44 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + /* ARM Cortex-M0+ Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CYB0644ABZI-D44 User Interrupt Numbers */ + NvicMux0_IRQn = 0, /*!< 0 [DeepSleep] CPU User Interrupt #0 */ + NvicMux1_IRQn = 1, /*!< 1 [DeepSleep] CPU User Interrupt #1 */ + NvicMux2_IRQn = 2, /*!< 2 [DeepSleep] CPU User Interrupt #2 */ + NvicMux3_IRQn = 3, /*!< 3 [DeepSleep] CPU User Interrupt #3 */ + NvicMux4_IRQn = 4, /*!< 4 [DeepSleep] CPU User Interrupt #4 */ + NvicMux5_IRQn = 5, /*!< 5 [DeepSleep] CPU User Interrupt #5 */ + NvicMux6_IRQn = 6, /*!< 6 [DeepSleep] CPU User Interrupt #6 */ + NvicMux7_IRQn = 7, /*!< 7 [DeepSleep] CPU User Interrupt #7 */ + /* CYB0644ABZI-D44 Internal SW Interrupt Numbers */ + Internal0_IRQn = 8, /*!< 8 [Active] Internal SW Interrupt #0 */ + Internal1_IRQn = 9, /*!< 9 [Active] Internal SW Interrupt #1 */ + Internal2_IRQn = 10, /*!< 10 [Active] Internal SW Interrupt #2 */ + Internal3_IRQn = 11, /*!< 11 [Active] Internal SW Interrupt #3 */ + Internal4_IRQn = 12, /*!< 12 [Active] Internal SW Interrupt #4 */ + Internal5_IRQn = 13, /*!< 13 [Active] Internal SW Interrupt #5 */ + Internal6_IRQn = 14, /*!< 14 [Active] Internal SW Interrupt #6 */ + Internal7_IRQn = 15, /*!< 15 [Active] Internal SW Interrupt #7 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#else + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CYB0644ABZI-D44 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#endif +} IRQn_Type; + + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* CYB0644ABZI-D44 interrupts that can be routed to the CM0+ NVIC */ +typedef enum { + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + disconnected_IRQn =1023 /*!< 1023 Disconnected */ +} cy_en_intr_t; + +#endif + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */ +#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ + +#else + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 1 /*!< CM0P present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + +#endif + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00100000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00200000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 2u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPROFILE 1u +#define CY_IP_MXPROFILE_INSTANCES 1u +#define CY_IP_MXPROFILE_VERSION 1u + +#include "psoc6_02_config.h" +#include "gpio_psoc6_02_124_bga.h" + +#define CY_DEVICE_PSOC6A2M +#define CY_SILICON_ID 0xE4301102UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40004140 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR10_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU6_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_DMAC_CH3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_PROFILE ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_SDHC1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB8 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB9 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB10 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB11 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB12 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ +#define PERI_MS_PPU_FX_PDM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[226]) /* 0x40014080 */ +#define PERI_MS_PPU_FX_I2S0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[227]) /* 0x400140C0 */ +#define PERI_MS_PPU_FX_I2S1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[228]) /* 0x40014100 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40100000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40100000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU6_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[0]) /* 0x40235A00 */ +#define PROT_MPU6_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[1]) /* 0x40235A20 */ +#define PROT_MPU6_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[2]) /* 0x40235A40 */ +#define PROT_MPU6_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[3]) /* 0x40235A60 */ +#define PROT_MPU6_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[4]) /* 0x40235A80 */ +#define PROT_MPU6_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[5]) /* 0x40235AA0 */ +#define PROT_MPU6_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[6]) /* 0x40235AC0 */ +#define PROT_MPU6_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[7]) /* 0x40235AE0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ +#define DMAC_CH2 ((DMAC_CH_Type*) &DMAC->CH[2]) /* 0x402A1200 */ +#define DMAC_CH3 ((DMAC_CH_Type*) &DMAC->CH[3]) /* 0x402A1300 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* PROFILE +*******************************************************************************/ + +#define PROFILE_BASE 0x402D0000UL +#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */ +#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */ +#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */ +#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */ +#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */ +#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */ +#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */ +#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */ +#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */ +#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */ +#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */ +#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ +#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */ +#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */ +#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */ +#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */ +#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */ +#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */ +#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */ +#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */ +#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */ +#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */ +#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */ +#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */ +#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */ +#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */ +#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */ +#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ +#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC1_BASE 0x40470000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC1 ((SDHC_Type*) SDHC1_BASE) /* 0x40470000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC1_WRAP ((SDHC_WRAP_Type*) &SDHC1->WRAP) /* 0x40470000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ +#define SDHC1_CORE ((SDHC_CORE_Type*) &SDHC1->CORE) /* 0x40471000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB7_BASE 0x40670000UL +#define SCB8_BASE 0x40680000UL +#define SCB9_BASE 0x40690000UL +#define SCB10_BASE 0x406A0000UL +#define SCB11_BASE 0x406B0000UL +#define SCB12_BASE 0x406C0000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ +#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40670000 */ +#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40680000 */ +#define SCB9 ((CySCB_Type*) SCB9_BASE) /* 0x40690000 */ +#define SCB10 ((CySCB_Type*) SCB10_BASE) /* 0x406A0000 */ +#define SCB11 ((CySCB_Type*) SCB11_BASE) /* 0x406B0000 */ +#define SCB12 ((CySCB_Type*) SCB12_BASE) /* 0x406C0000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/******************************************************************************* +* PDM +*******************************************************************************/ + +#define PDM0_BASE 0x40A00000UL +#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x40A00000 */ + +/******************************************************************************* +* I2S +*******************************************************************************/ + +#define I2S0_BASE 0x40A10000UL +#define I2S1_BASE 0x40A11000UL +#define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x40A10000 */ +#define I2S1 ((I2S_Type*) I2S1_BASE) /* 0x40A11000 */ + +/** \} CYB0644ABZI-D44 */ + +#endif /* _CYB0644ABZI_D44_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyble_416045_02.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyble_416045_02.h index 6331481cc1..afb0bc22ea 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyble_416045_02.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyble_416045_02.h @@ -5,7 +5,7 @@ * CYBLE-416045-02 device header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -517,7 +517,7 @@ typedef enum { #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u -#define CY_IP_MXS40PASS_SAR_INSTANCES 16u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u @@ -525,9 +525,6 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u #define CY_IP_MXS40IOSS 1u #define CY_IP_MXS40IOSS_INSTANCES 1u #define CY_IP_MXS40IOSS_VERSION 1u @@ -1161,17 +1158,6 @@ typedef enum { #define BLE_BLELL ((BLE_BLELL_Type*) &BLE->BLELL) /* 0x403C1000 */ #define BLE_BLESS ((BLE_BLESS_Type*) &BLE->BLESS) /* 0x403DF000 */ -/******************************************************************************* -* SMIF -*******************************************************************************/ - -#define SMIF0_BASE 0x40420000UL -#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ -#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ -#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ -#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ -#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */ - /******************************************************************************* * SCB *******************************************************************************/ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_104_m_csp_ble.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_104_m_csp_ble.h index 4ca546e111..be6b0e8c14 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_104_m_csp_ble.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_104_m_csp_ble.h @@ -5,7 +5,7 @@ * PSoC6_01 device GPIO header for 104-M-CSP-BLE package * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_104_m_csp_ble_usb.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_104_m_csp_ble_usb.h index 2bdb72c85e..17b82e07e5 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_104_m_csp_ble_usb.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_104_m_csp_ble_usb.h @@ -5,7 +5,7 @@ * PSoC6_01 device GPIO header for 104-M-CSP-BLE-USB package * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_116_bga_ble.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_116_bga_ble.h index 504225d23f..9a3c807cfa 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_116_bga_ble.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_116_bga_ble.h @@ -5,7 +5,7 @@ * PSoC6_01 device GPIO header for 116-BGA-BLE package * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_116_bga_usb.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_116_bga_usb.h index 6637ecb238..8e163136ef 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_116_bga_usb.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_116_bga_usb.h @@ -5,7 +5,7 @@ * PSoC6_01 device GPIO header for 116-BGA-USB package * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_124_bga.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_124_bga.h index 779816a716..d744007125 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_124_bga.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_124_bga.h @@ -5,7 +5,7 @@ * PSoC6_01 device GPIO header for 124-BGA package * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_124_bga_sip.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_124_bga_sip.h index 23094ac521..b623a69dbb 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_124_bga_sip.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_124_bga_sip.h @@ -5,7 +5,7 @@ * PSoC6_01 device GPIO header for 124-BGA-SIP package * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_43_smt.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_43_smt.h index 1ce7d20779..4072e3f1fc 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_43_smt.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_43_smt.h @@ -5,7 +5,7 @@ * PSoC6_01 device GPIO header for 43-SMT package * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_68_qfn_ble.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_68_qfn_ble.h new file mode 100644 index 0000000000..f5f68225ca --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_68_qfn_ble.h @@ -0,0 +1,1150 @@ +/***************************************************************************//** +* \file gpio_psoc6_01_68_qfn_ble.h +* +* \brief +* PSoC6_01 device GPIO header for 68-QFN-BLE package +* +* \note +* Generator version: 1.5.0.1274 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _GPIO_PSOC6_01_68_QFN_BLE_H_ +#define _GPIO_PSOC6_01_68_QFN_BLE_H_ + +/* Package type */ +enum +{ + CY_GPIO_PACKAGE_QFN, + CY_GPIO_PACKAGE_BGA, + CY_GPIO_PACKAGE_CSP, + CY_GPIO_PACKAGE_WLCSP, + CY_GPIO_PACKAGE_LQFP, + CY_GPIO_PACKAGE_TQFP, + CY_GPIO_PACKAGE_SMT, +}; + +#define CY_GPIO_PACKAGE_TYPE CY_GPIO_PACKAGE_QFN +#define CY_GPIO_PIN_COUNT 68u + +/* AMUXBUS Segments */ +enum +{ + AMUXBUS_MAIN, + AMUXBUS_ADFT0_VDDD, + AMUXBUS_NOISY, + AMUXBUS_ADFT1_VDDD, + AMUXBUS_CSD0, + AMUXBUS_VDDIO_1, + AMUXBUS_CSD1, + AMUXBUS_SAR, + AMUXBUS_ANALOG_VDDD, + AMUXBUS_ANALOG_VDDA, +}; + +/* AMUX Splitter Controls */ +typedef enum +{ + AMUX_SPLIT_CTL_0 = 0x0000u, /* Left = AMUXBUS_ADFT0_VDDD; Right = AMUXBUS_MAIN */ + AMUX_SPLIT_CTL_1 = 0x0001u, /* Left = AMUXBUS_MAIN; Right = AMUXBUS_NOISY */ + AMUX_SPLIT_CTL_7 = 0x0007u, /* Left = AMUXBUS_ADFT1_VDDD; Right = AMUXBUS_NOISY */ + AMUX_SPLIT_CTL_2 = 0x0002u, /* Left = AMUXBUS_CSD0; Right = AMUXBUS_NOISY */ + AMUX_SPLIT_CTL_3 = 0x0003u, /* Left = AMUXBUS_VDDIO_1; Right = AMUXBUS_CSD0 */ + AMUX_SPLIT_CTL_4 = 0x0004u, /* Left = AMUXBUS_CSD1; Right = AMUXBUS_CSD0 */ + AMUX_SPLIT_CTL_5 = 0x0005u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_CSD1 */ + AMUX_SPLIT_CTL_6 = 0x0006u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_MAIN */ + AMUX_SPLIT_CTL_8 = 0x0008u /* Left = AMUXBUS_ANALOG_VDDD; Right = AMUXBUS_ANALOG_VDDA */ +} cy_en_amux_split_t; + +/* Port List */ +/* PORT 0 (GPIO) */ +#define P0_0_PORT GPIO_PRT0 +#define P0_0_PIN 0u +#define P0_0_NUM 0u +#define P0_0_AMUXSEGMENT AMUXBUS_MAIN +#define P0_1_PORT GPIO_PRT0 +#define P0_1_PIN 1u +#define P0_1_NUM 1u +#define P0_1_AMUXSEGMENT AMUXBUS_MAIN +#define P0_2_PORT GPIO_PRT0 +#define P0_2_PIN 2u +#define P0_2_NUM 2u +#define P0_2_AMUXSEGMENT AMUXBUS_MAIN +#define P0_3_PORT GPIO_PRT0 +#define P0_3_PIN 3u +#define P0_3_NUM 3u +#define P0_3_AMUXSEGMENT AMUXBUS_MAIN +#define P0_4_PORT GPIO_PRT0 +#define P0_4_PIN 4u +#define P0_4_NUM 4u +#define P0_4_AMUXSEGMENT AMUXBUS_MAIN +#define P0_5_PORT GPIO_PRT0 +#define P0_5_PIN 5u +#define P0_5_NUM 5u +#define P0_5_AMUXSEGMENT AMUXBUS_MAIN + +/* PORT 6 (GPIO) */ +#define P6_0_PORT GPIO_PRT6 +#define P6_0_PIN 0u +#define P6_0_NUM 0u +#define P6_0_AMUXSEGMENT AMUXBUS_CSD0 +#define P6_1_PORT GPIO_PRT6 +#define P6_1_PIN 1u +#define P6_1_NUM 1u +#define P6_1_AMUXSEGMENT AMUXBUS_CSD0 +#define P6_2_PORT GPIO_PRT6 +#define P6_2_PIN 2u +#define P6_2_NUM 2u +#define P6_2_AMUXSEGMENT AMUXBUS_CSD0 +#define P6_3_PORT GPIO_PRT6 +#define P6_3_PIN 3u +#define P6_3_NUM 3u +#define P6_3_AMUXSEGMENT AMUXBUS_CSD0 +#define P6_4_PORT GPIO_PRT6 +#define P6_4_PIN 4u +#define P6_4_NUM 4u +#define P6_4_AMUXSEGMENT AMUXBUS_CSD0 +#define P6_5_PORT GPIO_PRT6 +#define P6_5_PIN 5u +#define P6_5_NUM 5u +#define P6_5_AMUXSEGMENT AMUXBUS_CSD0 +#define P6_6_PORT GPIO_PRT6 +#define P6_6_PIN 6u +#define P6_6_NUM 6u +#define P6_6_AMUXSEGMENT AMUXBUS_CSD0 +#define P6_7_PORT GPIO_PRT6 +#define P6_7_PIN 7u +#define P6_7_NUM 7u +#define P6_7_AMUXSEGMENT AMUXBUS_CSD0 + +/* PORT 7 (GPIO) */ +#define P7_0_PORT GPIO_PRT7 +#define P7_0_PIN 0u +#define P7_0_NUM 0u +#define P7_0_AMUXSEGMENT AMUXBUS_CSD0 +#define P7_1_PORT GPIO_PRT7 +#define P7_1_PIN 1u +#define P7_1_NUM 1u +#define P7_1_AMUXSEGMENT AMUXBUS_CSD0 +#define P7_2_PORT GPIO_PRT7 +#define P7_2_PIN 2u +#define P7_2_NUM 2u +#define P7_2_AMUXSEGMENT AMUXBUS_CSD0 +#define P7_3_PORT GPIO_PRT7 +#define P7_3_PIN 3u +#define P7_3_NUM 3u +#define P7_3_AMUXSEGMENT AMUXBUS_CSD0 +#define P7_4_PORT GPIO_PRT7 +#define P7_4_PIN 4u +#define P7_4_NUM 4u +#define P7_4_AMUXSEGMENT AMUXBUS_CSD0 +#define P7_5_PORT GPIO_PRT7 +#define P7_5_PIN 5u +#define P7_5_NUM 5u +#define P7_5_AMUXSEGMENT AMUXBUS_CSD0 +#define P7_6_PORT GPIO_PRT7 +#define P7_6_PIN 6u +#define P7_6_NUM 6u +#define P7_6_AMUXSEGMENT AMUXBUS_CSD0 +#define P7_7_PORT GPIO_PRT7 +#define P7_7_PIN 7u +#define P7_7_NUM 7u +#define P7_7_AMUXSEGMENT AMUXBUS_CSD0 + +/* PORT 8 (GPIO) */ +#define P8_0_PORT GPIO_PRT8 +#define P8_0_PIN 0u +#define P8_0_NUM 0u +#define P8_0_AMUXSEGMENT AMUXBUS_CSD0 +#define P8_1_PORT GPIO_PRT8 +#define P8_1_PIN 1u +#define P8_1_NUM 1u +#define P8_1_AMUXSEGMENT AMUXBUS_CSD0 +#define P8_2_PORT GPIO_PRT8 +#define P8_2_PIN 2u +#define P8_2_NUM 2u +#define P8_2_AMUXSEGMENT AMUXBUS_CSD0 + +/* PORT 9 (GPIO) */ +#define P9_0_PORT GPIO_PRT9 +#define P9_0_PIN 0u +#define P9_0_NUM 0u +#define P9_0_AMUXSEGMENT AMUXBUS_SAR +#define P9_1_PORT GPIO_PRT9 +#define P9_1_PIN 1u +#define P9_1_NUM 1u +#define P9_1_AMUXSEGMENT AMUXBUS_SAR +#define P9_2_PORT GPIO_PRT9 +#define P9_2_PIN 2u +#define P9_2_NUM 2u +#define P9_2_AMUXSEGMENT AMUXBUS_SAR +#define P9_3_PORT GPIO_PRT9 +#define P9_3_PIN 3u +#define P9_3_NUM 3u +#define P9_3_AMUXSEGMENT AMUXBUS_SAR + +/* PORT 10 (GPIO) */ +#define P10_0_PORT GPIO_PRT10 +#define P10_0_PIN 0u +#define P10_0_NUM 0u +#define P10_0_AMUXSEGMENT AMUXBUS_SAR +#define P10_1_PORT GPIO_PRT10 +#define P10_1_PIN 1u +#define P10_1_NUM 1u +#define P10_1_AMUXSEGMENT AMUXBUS_SAR + +/* PORT 11 (GPIO) */ +#define P11_0_PORT GPIO_PRT11 +#define P11_0_PIN 0u +#define P11_0_NUM 0u +#define P11_0_AMUXSEGMENT AMUXBUS_MAIN +#define P11_1_PORT GPIO_PRT11 +#define P11_1_PIN 1u +#define P11_1_NUM 1u +#define P11_1_AMUXSEGMENT AMUXBUS_MAIN +#define P11_2_PORT GPIO_PRT11 +#define P11_2_PIN 2u +#define P11_2_NUM 2u +#define P11_2_AMUXSEGMENT AMUXBUS_MAIN +#define P11_3_PORT GPIO_PRT11 +#define P11_3_PIN 3u +#define P11_3_NUM 3u +#define P11_3_AMUXSEGMENT AMUXBUS_MAIN +#define P11_4_PORT GPIO_PRT11 +#define P11_4_PIN 4u +#define P11_4_NUM 4u +#define P11_4_AMUXSEGMENT AMUXBUS_MAIN +#define P11_5_PORT GPIO_PRT11 +#define P11_5_PIN 5u +#define P11_5_NUM 5u +#define P11_5_AMUXSEGMENT AMUXBUS_MAIN +#define P11_6_PORT GPIO_PRT11 +#define P11_6_PIN 6u +#define P11_6_NUM 6u +#define P11_6_AMUXSEGMENT AMUXBUS_MAIN +#define P11_7_PORT GPIO_PRT11 +#define P11_7_PIN 7u +#define P11_7_NUM 7u +#define P11_7_AMUXSEGMENT AMUXBUS_MAIN + +/* PORT 12 (GPIO) */ +#define P12_6_PORT GPIO_PRT12 +#define P12_6_PIN 6u +#define P12_6_NUM 6u +#define P12_6_AMUXSEGMENT AMUXBUS_MAIN +#define P12_7_PORT GPIO_PRT12 +#define P12_7_PIN 7u +#define P12_7_NUM 7u +#define P12_7_AMUXSEGMENT AMUXBUS_MAIN + +/* Analog Connections */ +#define CSD_CMODPADD_PORT 7u +#define CSD_CMODPADD_PIN 1u +#define CSD_CMODPADS_PORT 7u +#define CSD_CMODPADS_PIN 1u +#define CSD_CSH_TANKPADD_PORT 7u +#define CSD_CSH_TANKPADD_PIN 2u +#define CSD_CSH_TANKPADS_PORT 7u +#define CSD_CSH_TANKPADS_PIN 2u +#define CSD_CSHIELDPADS_PORT 7u +#define CSD_CSHIELDPADS_PIN 7u +#define CSD_VREF_EXT_PORT 7u +#define CSD_VREF_EXT_PIN 3u +#define IOSS_ADFT0_NET_PORT 10u +#define IOSS_ADFT0_NET_PIN 0u +#define IOSS_ADFT1_NET_PORT 10u +#define IOSS_ADFT1_NET_PIN 1u +#define LPCOMP_INN_COMP1_PORT 6u +#define LPCOMP_INN_COMP1_PIN 3u +#define LPCOMP_INP_COMP1_PORT 6u +#define LPCOMP_INP_COMP1_PIN 2u +#define PASS_CTB_OA0_OUT_10X_PORT 9u +#define PASS_CTB_OA0_OUT_10X_PIN 2u +#define PASS_CTB_OA1_OUT_10X_PORT 9u +#define PASS_CTB_OA1_OUT_10X_PIN 3u +#define PASS_CTB_PADS0_PORT 9u +#define PASS_CTB_PADS0_PIN 0u +#define PASS_CTB_PADS1_PORT 9u +#define PASS_CTB_PADS1_PIN 1u +#define PASS_CTB_PADS2_PORT 9u +#define PASS_CTB_PADS2_PIN 2u +#define PASS_CTB_PADS3_PORT 9u +#define PASS_CTB_PADS3_PIN 3u +#define PASS_SARMUX_PADS0_PORT 10u +#define PASS_SARMUX_PADS0_PIN 0u +#define PASS_SARMUX_PADS1_PORT 10u +#define PASS_SARMUX_PADS1_PIN 1u +#define SRSS_ADFT_PIN0_PORT 10u +#define SRSS_ADFT_PIN0_PIN 0u +#define SRSS_ADFT_PIN1_PORT 10u +#define SRSS_ADFT_PIN1_PIN 1u +#define SRSS_ECO_IN_PORT 12u +#define SRSS_ECO_IN_PIN 6u +#define SRSS_ECO_OUT_PORT 12u +#define SRSS_ECO_OUT_PIN 7u +#define SRSS_WCO_IN_PORT 0u +#define SRSS_WCO_IN_PIN 0u +#define SRSS_WCO_OUT_PORT 0u +#define SRSS_WCO_OUT_PIN 1u + +/* HSIOM Connections */ +typedef enum +{ + /* Generic HSIOM connections */ + HSIOM_SEL_GPIO = 0, /* GPIO controls 'out' */ + HSIOM_SEL_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + HSIOM_SEL_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + HSIOM_SEL_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + HSIOM_SEL_AMUXA = 4, /* Analog mux bus A */ + HSIOM_SEL_AMUXB = 5, /* Analog mux bus B */ + HSIOM_SEL_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + HSIOM_SEL_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + HSIOM_SEL_ACT_0 = 8, /* Active functionality 0 */ + HSIOM_SEL_ACT_1 = 9, /* Active functionality 1 */ + HSIOM_SEL_ACT_2 = 10, /* Active functionality 2 */ + HSIOM_SEL_ACT_3 = 11, /* Active functionality 3 */ + HSIOM_SEL_DS_0 = 12, /* DeepSleep functionality 0 */ + HSIOM_SEL_DS_1 = 13, /* DeepSleep functionality 1 */ + HSIOM_SEL_DS_2 = 14, /* DeepSleep functionality 2 */ + HSIOM_SEL_DS_3 = 15, /* DeepSleep functionality 3 */ + HSIOM_SEL_ACT_4 = 16, /* Active functionality 4 */ + HSIOM_SEL_ACT_5 = 17, /* Active functionality 5 */ + HSIOM_SEL_ACT_6 = 18, /* Active functionality 6 */ + HSIOM_SEL_ACT_7 = 19, /* Active functionality 7 */ + HSIOM_SEL_ACT_8 = 20, /* Active functionality 8 */ + HSIOM_SEL_ACT_9 = 21, /* Active functionality 9 */ + HSIOM_SEL_ACT_10 = 22, /* Active functionality 10 */ + HSIOM_SEL_ACT_11 = 23, /* Active functionality 11 */ + HSIOM_SEL_ACT_12 = 24, /* Active functionality 12 */ + HSIOM_SEL_ACT_13 = 25, /* Active functionality 13 */ + HSIOM_SEL_ACT_14 = 26, /* Active functionality 14 */ + HSIOM_SEL_ACT_15 = 27, /* Active functionality 15 */ + HSIOM_SEL_DS_4 = 28, /* DeepSleep functionality 4 */ + HSIOM_SEL_DS_5 = 29, /* DeepSleep functionality 5 */ + HSIOM_SEL_DS_6 = 30, /* DeepSleep functionality 6 */ + HSIOM_SEL_DS_7 = 31, /* DeepSleep functionality 7 */ + + /* P0.0 */ + P0_0_GPIO = 0, /* GPIO controls 'out' */ + P0_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P0_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P0_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P0_0_AMUXA = 4, /* Analog mux bus A */ + P0_0_AMUXB = 5, /* Analog mux bus B */ + P0_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P0_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P0_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:0 */ + P0_0_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:0 */ + P0_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:0 */ + P0_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:0 */ + P0_0_LCD_COM0 = 12, /* Digital Deep Sleep - lcd.com[0]:0 */ + P0_0_LCD_SEG0 = 13, /* Digital Deep Sleep - lcd.seg[0]:0 */ + P0_0_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:0 */ + P0_0_SCB0_SPI_SELECT1 = 20, /* Digital Active - scb[0].spi_select1:0 */ + P0_0_PERI_TR_IO_INPUT0 = 24, /* Digital Active - peri.tr_io_input[0]:0 */ + + /* P0.1 */ + P0_1_GPIO = 0, /* GPIO controls 'out' */ + P0_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P0_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P0_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P0_1_AMUXA = 4, /* Analog mux bus A */ + P0_1_AMUXB = 5, /* Analog mux bus B */ + P0_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P0_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P0_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:0 */ + P0_1_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:0 */ + P0_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:1 */ + P0_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:1 */ + P0_1_LCD_COM1 = 12, /* Digital Deep Sleep - lcd.com[1]:0 */ + P0_1_LCD_SEG1 = 13, /* Digital Deep Sleep - lcd.seg[1]:0 */ + P0_1_SCB0_SPI_SELECT2 = 20, /* Digital Active - scb[0].spi_select2:0 */ + P0_1_PERI_TR_IO_INPUT1 = 24, /* Digital Active - peri.tr_io_input[1]:0 */ + P0_1_CPUSS_SWJ_TRSTN = 29, /* Digital Deep Sleep - cpuss.swj_trstn */ + + /* P0.2 */ + P0_2_GPIO = 0, /* GPIO controls 'out' */ + P0_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P0_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P0_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P0_2_AMUXA = 4, /* Analog mux bus A */ + P0_2_AMUXB = 5, /* Analog mux bus B */ + P0_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P0_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P0_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:0 */ + P0_2_TCPWM1_LINE1 = 9, /* Digital Active - tcpwm[1].line[1]:0 */ + P0_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:2 */ + P0_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:2 */ + P0_2_LCD_COM2 = 12, /* Digital Deep Sleep - lcd.com[2]:0 */ + P0_2_LCD_SEG2 = 13, /* Digital Deep Sleep - lcd.seg[2]:0 */ + P0_2_SCB0_UART_RX = 18, /* Digital Active - scb[0].uart_rx:0 */ + P0_2_SCB0_I2C_SCL = 19, /* Digital Active - scb[0].i2c_scl:0 */ + P0_2_SCB0_SPI_MOSI = 20, /* Digital Active - scb[0].spi_mosi:0 */ + + /* P0.3 */ + P0_3_GPIO = 0, /* GPIO controls 'out' */ + P0_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P0_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P0_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P0_3_AMUXA = 4, /* Analog mux bus A */ + P0_3_AMUXB = 5, /* Analog mux bus B */ + P0_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P0_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P0_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:0 */ + P0_3_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:0 */ + P0_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:3 */ + P0_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:3 */ + P0_3_LCD_COM3 = 12, /* Digital Deep Sleep - lcd.com[3]:0 */ + P0_3_LCD_SEG3 = 13, /* Digital Deep Sleep - lcd.seg[3]:0 */ + P0_3_SCB0_UART_TX = 18, /* Digital Active - scb[0].uart_tx:0 */ + P0_3_SCB0_I2C_SDA = 19, /* Digital Active - scb[0].i2c_sda:0 */ + P0_3_SCB0_SPI_MISO = 20, /* Digital Active - scb[0].spi_miso:0 */ + + /* P0.4 */ + P0_4_GPIO = 0, /* GPIO controls 'out' */ + P0_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P0_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P0_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P0_4_AMUXA = 4, /* Analog mux bus A */ + P0_4_AMUXB = 5, /* Analog mux bus B */ + P0_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P0_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P0_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:0 */ + P0_4_TCPWM1_LINE2 = 9, /* Digital Active - tcpwm[1].line[2]:0 */ + P0_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:4 */ + P0_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:4 */ + P0_4_LCD_COM4 = 12, /* Digital Deep Sleep - lcd.com[4]:0 */ + P0_4_LCD_SEG4 = 13, /* Digital Deep Sleep - lcd.seg[4]:0 */ + P0_4_SCB0_UART_RTS = 18, /* Digital Active - scb[0].uart_rts:0 */ + P0_4_SCB0_SPI_CLK = 20, /* Digital Active - scb[0].spi_clk:0 */ + P0_4_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:2 */ + + /* P0.5 */ + P0_5_GPIO = 0, /* GPIO controls 'out' */ + P0_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P0_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P0_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P0_5_AMUXA = 4, /* Analog mux bus A */ + P0_5_AMUXB = 5, /* Analog mux bus B */ + P0_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P0_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P0_5_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:0 */ + P0_5_TCPWM1_LINE_COMPL2 = 9, /* Digital Active - tcpwm[1].line_compl[2]:0 */ + P0_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:5 */ + P0_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:5 */ + P0_5_LCD_COM5 = 12, /* Digital Deep Sleep - lcd.com[5]:0 */ + P0_5_LCD_SEG5 = 13, /* Digital Deep Sleep - lcd.seg[5]:0 */ + P0_5_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:1 */ + P0_5_SCB0_UART_CTS = 18, /* Digital Active - scb[0].uart_cts:0 */ + P0_5_SCB0_SPI_SELECT0 = 20, /* Digital Active - scb[0].spi_select0:0 */ + P0_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:2 */ + + /* P6.0 */ + P6_0_GPIO = 0, /* GPIO controls 'out' */ + P6_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P6_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P6_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P6_0_AMUXA = 4, /* Analog mux bus A */ + P6_0_AMUXB = 5, /* Analog mux bus B */ + P6_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P6_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P6_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:1 */ + P6_0_TCPWM1_LINE8 = 9, /* Digital Active - tcpwm[1].line[8]:0 */ + P6_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:38 */ + P6_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:38 */ + P6_0_LCD_COM38 = 12, /* Digital Deep Sleep - lcd.com[38]:0 */ + P6_0_LCD_SEG38 = 13, /* Digital Deep Sleep - lcd.seg[38]:0 */ + P6_0_SCB8_I2C_SCL = 14, /* Digital Deep Sleep - scb[8].i2c_scl:0 */ + P6_0_SCB3_UART_RX = 18, /* Digital Active - scb[3].uart_rx:0 */ + P6_0_SCB3_I2C_SCL = 19, /* Digital Active - scb[3].i2c_scl:0 */ + P6_0_SCB3_SPI_MOSI = 20, /* Digital Active - scb[3].spi_mosi:0 */ + P6_0_CPUSS_FAULT_OUT0 = 25, /* Digital Active - cpuss.fault_out[0] */ + P6_0_SCB8_SPI_MOSI = 30, /* Digital Deep Sleep - scb[8].spi_mosi:0 */ + + /* P6.1 */ + P6_1_GPIO = 0, /* GPIO controls 'out' */ + P6_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P6_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P6_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P6_1_AMUXA = 4, /* Analog mux bus A */ + P6_1_AMUXB = 5, /* Analog mux bus B */ + P6_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P6_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P6_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:1 */ + P6_1_TCPWM1_LINE_COMPL8 = 9, /* Digital Active - tcpwm[1].line_compl[8]:0 */ + P6_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:39 */ + P6_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:39 */ + P6_1_LCD_COM39 = 12, /* Digital Deep Sleep - lcd.com[39]:0 */ + P6_1_LCD_SEG39 = 13, /* Digital Deep Sleep - lcd.seg[39]:0 */ + P6_1_SCB8_I2C_SDA = 14, /* Digital Deep Sleep - scb[8].i2c_sda:0 */ + P6_1_SCB3_UART_TX = 18, /* Digital Active - scb[3].uart_tx:0 */ + P6_1_SCB3_I2C_SDA = 19, /* Digital Active - scb[3].i2c_sda:0 */ + P6_1_SCB3_SPI_MISO = 20, /* Digital Active - scb[3].spi_miso:0 */ + P6_1_CPUSS_FAULT_OUT1 = 25, /* Digital Active - cpuss.fault_out[1] */ + P6_1_SCB8_SPI_MISO = 30, /* Digital Deep Sleep - scb[8].spi_miso:0 */ + + /* P6.2 */ + P6_2_GPIO = 0, /* GPIO controls 'out' */ + P6_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P6_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P6_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P6_2_AMUXA = 4, /* Analog mux bus A */ + P6_2_AMUXB = 5, /* Analog mux bus B */ + P6_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P6_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P6_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:1 */ + P6_2_TCPWM1_LINE9 = 9, /* Digital Active - tcpwm[1].line[9]:0 */ + P6_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:40 */ + P6_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:40 */ + P6_2_LCD_COM40 = 12, /* Digital Deep Sleep - lcd.com[40]:0 */ + P6_2_LCD_SEG40 = 13, /* Digital Deep Sleep - lcd.seg[40]:0 */ + P6_2_SCB3_UART_RTS = 18, /* Digital Active - scb[3].uart_rts:0 */ + P6_2_SCB3_SPI_CLK = 20, /* Digital Active - scb[3].spi_clk:0 */ + P6_2_SCB8_SPI_CLK = 30, /* Digital Deep Sleep - scb[8].spi_clk:0 */ + + /* P6.3 */ + P6_3_GPIO = 0, /* GPIO controls 'out' */ + P6_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P6_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P6_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P6_3_AMUXA = 4, /* Analog mux bus A */ + P6_3_AMUXB = 5, /* Analog mux bus B */ + P6_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P6_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P6_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:1 */ + P6_3_TCPWM1_LINE_COMPL9 = 9, /* Digital Active - tcpwm[1].line_compl[9]:0 */ + P6_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:41 */ + P6_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:41 */ + P6_3_LCD_COM41 = 12, /* Digital Deep Sleep - lcd.com[41]:0 */ + P6_3_LCD_SEG41 = 13, /* Digital Deep Sleep - lcd.seg[41]:0 */ + P6_3_SCB3_UART_CTS = 18, /* Digital Active - scb[3].uart_cts:0 */ + P6_3_SCB3_SPI_SELECT0 = 20, /* Digital Active - scb[3].spi_select0:0 */ + P6_3_SCB8_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[8].spi_select0:0 */ + + /* P6.4 */ + P6_4_GPIO = 0, /* GPIO controls 'out' */ + P6_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P6_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P6_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P6_4_AMUXA = 4, /* Analog mux bus A */ + P6_4_AMUXB = 5, /* Analog mux bus B */ + P6_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P6_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P6_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:1 */ + P6_4_TCPWM1_LINE10 = 9, /* Digital Active - tcpwm[1].line[10]:0 */ + P6_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:42 */ + P6_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:42 */ + P6_4_LCD_COM42 = 12, /* Digital Deep Sleep - lcd.com[42]:0 */ + P6_4_LCD_SEG42 = 13, /* Digital Deep Sleep - lcd.seg[42]:0 */ + P6_4_SCB8_I2C_SCL = 14, /* Digital Deep Sleep - scb[8].i2c_scl:1 */ + P6_4_SCB6_UART_RX = 18, /* Digital Active - scb[6].uart_rx:2 */ + P6_4_SCB6_I2C_SCL = 19, /* Digital Active - scb[6].i2c_scl:2 */ + P6_4_SCB6_SPI_MOSI = 20, /* Digital Active - scb[6].spi_mosi:2 */ + P6_4_PERI_TR_IO_INPUT12 = 24, /* Digital Active - peri.tr_io_input[12]:0 */ + P6_4_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:1 */ + P6_4_CPUSS_SWJ_SWO_TDO = 29, /* Digital Deep Sleep - cpuss.swj_swo_tdo */ + P6_4_SCB8_SPI_MOSI = 30, /* Digital Deep Sleep - scb[8].spi_mosi:1 */ + P6_4_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:0 */ + + /* P6.5 */ + P6_5_GPIO = 0, /* GPIO controls 'out' */ + P6_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P6_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P6_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P6_5_AMUXA = 4, /* Analog mux bus A */ + P6_5_AMUXB = 5, /* Analog mux bus B */ + P6_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P6_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P6_5_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:1 */ + P6_5_TCPWM1_LINE_COMPL10 = 9, /* Digital Active - tcpwm[1].line_compl[10]:0 */ + P6_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:43 */ + P6_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:43 */ + P6_5_LCD_COM43 = 12, /* Digital Deep Sleep - lcd.com[43]:0 */ + P6_5_LCD_SEG43 = 13, /* Digital Deep Sleep - lcd.seg[43]:0 */ + P6_5_SCB8_I2C_SDA = 14, /* Digital Deep Sleep - scb[8].i2c_sda:1 */ + P6_5_SCB6_UART_TX = 18, /* Digital Active - scb[6].uart_tx:2 */ + P6_5_SCB6_I2C_SDA = 19, /* Digital Active - scb[6].i2c_sda:2 */ + P6_5_SCB6_SPI_MISO = 20, /* Digital Active - scb[6].spi_miso:2 */ + P6_5_PERI_TR_IO_INPUT13 = 24, /* Digital Active - peri.tr_io_input[13]:0 */ + P6_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:1 */ + P6_5_CPUSS_SWJ_SWDOE_TDI = 29, /* Digital Deep Sleep - cpuss.swj_swdoe_tdi */ + P6_5_SCB8_SPI_MISO = 30, /* Digital Deep Sleep - scb[8].spi_miso:1 */ + P6_5_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:0 */ + + /* P6.6 */ + P6_6_GPIO = 0, /* GPIO controls 'out' */ + P6_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P6_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P6_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P6_6_AMUXA = 4, /* Analog mux bus A */ + P6_6_AMUXB = 5, /* Analog mux bus B */ + P6_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P6_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P6_6_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:1 */ + P6_6_TCPWM1_LINE11 = 9, /* Digital Active - tcpwm[1].line[11]:0 */ + P6_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:44 */ + P6_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:44 */ + P6_6_LCD_COM44 = 12, /* Digital Deep Sleep - lcd.com[44]:0 */ + P6_6_LCD_SEG44 = 13, /* Digital Deep Sleep - lcd.seg[44]:0 */ + P6_6_SCB6_UART_RTS = 18, /* Digital Active - scb[6].uart_rts:2 */ + P6_6_SCB6_SPI_CLK = 20, /* Digital Active - scb[6].spi_clk:2 */ + P6_6_CPUSS_SWJ_SWDIO_TMS = 29, /* Digital Deep Sleep - cpuss.swj_swdio_tms */ + P6_6_SCB8_SPI_CLK = 30, /* Digital Deep Sleep - scb[8].spi_clk:1 */ + + /* P6.7 */ + P6_7_GPIO = 0, /* GPIO controls 'out' */ + P6_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P6_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P6_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P6_7_AMUXA = 4, /* Analog mux bus A */ + P6_7_AMUXB = 5, /* Analog mux bus B */ + P6_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P6_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P6_7_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:1 */ + P6_7_TCPWM1_LINE_COMPL11 = 9, /* Digital Active - tcpwm[1].line_compl[11]:0 */ + P6_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:45 */ + P6_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:45 */ + P6_7_LCD_COM45 = 12, /* Digital Deep Sleep - lcd.com[45]:0 */ + P6_7_LCD_SEG45 = 13, /* Digital Deep Sleep - lcd.seg[45]:0 */ + P6_7_SCB6_UART_CTS = 18, /* Digital Active - scb[6].uart_cts:2 */ + P6_7_SCB6_SPI_SELECT0 = 20, /* Digital Active - scb[6].spi_select0:2 */ + P6_7_CPUSS_SWJ_SWCLK_TCLK = 29, /* Digital Deep Sleep - cpuss.swj_swclk_tclk */ + P6_7_SCB8_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[8].spi_select0:1 */ + + /* P7.0 */ + P7_0_GPIO = 0, /* GPIO controls 'out' */ + P7_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P7_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P7_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P7_0_AMUXA = 4, /* Analog mux bus A */ + P7_0_AMUXB = 5, /* Analog mux bus B */ + P7_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P7_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:1 */ + P7_0_TCPWM1_LINE12 = 9, /* Digital Active - tcpwm[1].line[12]:0 */ + P7_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:46 */ + P7_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:46 */ + P7_0_LCD_COM46 = 12, /* Digital Deep Sleep - lcd.com[46]:0 */ + P7_0_LCD_SEG46 = 13, /* Digital Deep Sleep - lcd.seg[46]:0 */ + P7_0_SCB4_UART_RX = 18, /* Digital Active - scb[4].uart_rx:1 */ + P7_0_SCB4_I2C_SCL = 19, /* Digital Active - scb[4].i2c_scl:1 */ + P7_0_SCB4_SPI_MOSI = 20, /* Digital Active - scb[4].spi_mosi:1 */ + P7_0_PERI_TR_IO_INPUT14 = 24, /* Digital Active - peri.tr_io_input[14]:0 */ + P7_0_CPUSS_TRACE_CLOCK = 26, /* Digital Active - cpuss.trace_clock */ + + /* P7.1 */ + P7_1_GPIO = 0, /* GPIO controls 'out' */ + P7_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P7_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P7_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P7_1_AMUXA = 4, /* Analog mux bus A */ + P7_1_AMUXB = 5, /* Analog mux bus B */ + P7_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P7_1_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:1 */ + P7_1_TCPWM1_LINE_COMPL12 = 9, /* Digital Active - tcpwm[1].line_compl[12]:0 */ + P7_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:47 */ + P7_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:47 */ + P7_1_LCD_COM47 = 12, /* Digital Deep Sleep - lcd.com[47]:0 */ + P7_1_LCD_SEG47 = 13, /* Digital Deep Sleep - lcd.seg[47]:0 */ + P7_1_SCB4_UART_TX = 18, /* Digital Active - scb[4].uart_tx:1 */ + P7_1_SCB4_I2C_SDA = 19, /* Digital Active - scb[4].i2c_sda:1 */ + P7_1_SCB4_SPI_MISO = 20, /* Digital Active - scb[4].spi_miso:1 */ + P7_1_PERI_TR_IO_INPUT15 = 24, /* Digital Active - peri.tr_io_input[15]:0 */ + + /* P7.2 */ + P7_2_GPIO = 0, /* GPIO controls 'out' */ + P7_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P7_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P7_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P7_2_AMUXA = 4, /* Analog mux bus A */ + P7_2_AMUXB = 5, /* Analog mux bus B */ + P7_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P7_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:1 */ + P7_2_TCPWM1_LINE13 = 9, /* Digital Active - tcpwm[1].line[13]:0 */ + P7_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:48 */ + P7_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:48 */ + P7_2_LCD_COM48 = 12, /* Digital Deep Sleep - lcd.com[48]:0 */ + P7_2_LCD_SEG48 = 13, /* Digital Deep Sleep - lcd.seg[48]:0 */ + P7_2_SCB4_UART_RTS = 18, /* Digital Active - scb[4].uart_rts:1 */ + P7_2_SCB4_SPI_CLK = 20, /* Digital Active - scb[4].spi_clk:1 */ + + /* P7.3 */ + P7_3_GPIO = 0, /* GPIO controls 'out' */ + P7_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P7_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P7_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P7_3_AMUXA = 4, /* Analog mux bus A */ + P7_3_AMUXB = 5, /* Analog mux bus B */ + P7_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P7_3_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:1 */ + P7_3_TCPWM1_LINE_COMPL13 = 9, /* Digital Active - tcpwm[1].line_compl[13]:0 */ + P7_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:49 */ + P7_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:49 */ + P7_3_LCD_COM49 = 12, /* Digital Deep Sleep - lcd.com[49]:0 */ + P7_3_LCD_SEG49 = 13, /* Digital Deep Sleep - lcd.seg[49]:0 */ + P7_3_SCB4_UART_CTS = 18, /* Digital Active - scb[4].uart_cts:1 */ + P7_3_SCB4_SPI_SELECT0 = 20, /* Digital Active - scb[4].spi_select0:1 */ + + /* P7.4 */ + P7_4_GPIO = 0, /* GPIO controls 'out' */ + P7_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P7_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P7_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P7_4_AMUXA = 4, /* Analog mux bus A */ + P7_4_AMUXB = 5, /* Analog mux bus B */ + P7_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P7_4_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:1 */ + P7_4_TCPWM1_LINE14 = 9, /* Digital Active - tcpwm[1].line[14]:0 */ + P7_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:50 */ + P7_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:50 */ + P7_4_LCD_COM50 = 12, /* Digital Deep Sleep - lcd.com[50]:0 */ + P7_4_LCD_SEG50 = 13, /* Digital Deep Sleep - lcd.seg[50]:0 */ + P7_4_SCB4_SPI_SELECT1 = 20, /* Digital Active - scb[4].spi_select1:1 */ + P7_4_BLESS_EXT_LNA_RX_CTL_OUT = 26, /* Digital Active - bless.ext_lna_rx_ctl_out */ + P7_4_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:2 */ + + /* P7.5 */ + P7_5_GPIO = 0, /* GPIO controls 'out' */ + P7_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P7_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P7_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P7_5_AMUXA = 4, /* Analog mux bus A */ + P7_5_AMUXB = 5, /* Analog mux bus B */ + P7_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P7_5_TCPWM0_LINE_COMPL6 = 8, /* Digital Active - tcpwm[0].line_compl[6]:1 */ + P7_5_TCPWM1_LINE_COMPL14 = 9, /* Digital Active - tcpwm[1].line_compl[14]:0 */ + P7_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:51 */ + P7_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:51 */ + P7_5_LCD_COM51 = 12, /* Digital Deep Sleep - lcd.com[51]:0 */ + P7_5_LCD_SEG51 = 13, /* Digital Deep Sleep - lcd.seg[51]:0 */ + P7_5_SCB4_SPI_SELECT2 = 20, /* Digital Active - scb[4].spi_select2:1 */ + P7_5_BLESS_EXT_PA_TX_CTL_OUT = 26, /* Digital Active - bless.ext_pa_tx_ctl_out */ + P7_5_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:2 */ + + /* P7.6 */ + P7_6_GPIO = 0, /* GPIO controls 'out' */ + P7_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P7_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P7_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P7_6_AMUXA = 4, /* Analog mux bus A */ + P7_6_AMUXB = 5, /* Analog mux bus B */ + P7_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P7_6_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:1 */ + P7_6_TCPWM1_LINE15 = 9, /* Digital Active - tcpwm[1].line[15]:0 */ + P7_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:52 */ + P7_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:52 */ + P7_6_LCD_COM52 = 12, /* Digital Deep Sleep - lcd.com[52]:0 */ + P7_6_LCD_SEG52 = 13, /* Digital Deep Sleep - lcd.seg[52]:0 */ + P7_6_SCB4_SPI_SELECT3 = 20, /* Digital Active - scb[4].spi_select3:1 */ + P7_6_BLESS_EXT_PA_LNA_CHIP_EN_OUT = 26, /* Digital Active - bless.ext_pa_lna_chip_en_out */ + P7_6_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:2 */ + + /* P7.7 */ + P7_7_GPIO = 0, /* GPIO controls 'out' */ + P7_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P7_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P7_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P7_7_AMUXA = 4, /* Analog mux bus A */ + P7_7_AMUXB = 5, /* Analog mux bus B */ + P7_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P7_7_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:1 */ + P7_7_TCPWM1_LINE_COMPL15 = 9, /* Digital Active - tcpwm[1].line_compl[15]:0 */ + P7_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:53 */ + P7_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:53 */ + P7_7_LCD_COM53 = 12, /* Digital Deep Sleep - lcd.com[53]:0 */ + P7_7_LCD_SEG53 = 13, /* Digital Deep Sleep - lcd.seg[53]:0 */ + P7_7_SCB3_SPI_SELECT1 = 20, /* Digital Active - scb[3].spi_select1:0 */ + P7_7_CPUSS_CLK_FM_PUMP = 21, /* Digital Active - cpuss.clk_fm_pump */ + P7_7_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:2 */ + + /* P8.0 */ + P8_0_GPIO = 0, /* GPIO controls 'out' */ + P8_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P8_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P8_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P8_0_AMUXA = 4, /* Analog mux bus A */ + P8_0_AMUXB = 5, /* Analog mux bus B */ + P8_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P8_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P8_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:2 */ + P8_0_TCPWM1_LINE16 = 9, /* Digital Active - tcpwm[1].line[16]:0 */ + P8_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:54 */ + P8_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:54 */ + P8_0_LCD_COM54 = 12, /* Digital Deep Sleep - lcd.com[54]:0 */ + P8_0_LCD_SEG54 = 13, /* Digital Deep Sleep - lcd.seg[54]:0 */ + P8_0_SCB4_UART_RX = 18, /* Digital Active - scb[4].uart_rx:0 */ + P8_0_SCB4_I2C_SCL = 19, /* Digital Active - scb[4].i2c_scl:0 */ + P8_0_SCB4_SPI_MOSI = 20, /* Digital Active - scb[4].spi_mosi:0 */ + P8_0_PERI_TR_IO_INPUT16 = 24, /* Digital Active - peri.tr_io_input[16]:0 */ + + /* P8.1 */ + P8_1_GPIO = 0, /* GPIO controls 'out' */ + P8_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P8_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P8_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P8_1_AMUXA = 4, /* Analog mux bus A */ + P8_1_AMUXB = 5, /* Analog mux bus B */ + P8_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P8_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P8_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:2 */ + P8_1_TCPWM1_LINE_COMPL16 = 9, /* Digital Active - tcpwm[1].line_compl[16]:0 */ + P8_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:55 */ + P8_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:55 */ + P8_1_LCD_COM55 = 12, /* Digital Deep Sleep - lcd.com[55]:0 */ + P8_1_LCD_SEG55 = 13, /* Digital Deep Sleep - lcd.seg[55]:0 */ + P8_1_SCB4_UART_TX = 18, /* Digital Active - scb[4].uart_tx:0 */ + P8_1_SCB4_I2C_SDA = 19, /* Digital Active - scb[4].i2c_sda:0 */ + P8_1_SCB4_SPI_MISO = 20, /* Digital Active - scb[4].spi_miso:0 */ + P8_1_PERI_TR_IO_INPUT17 = 24, /* Digital Active - peri.tr_io_input[17]:0 */ + + /* P8.2 */ + P8_2_GPIO = 0, /* GPIO controls 'out' */ + P8_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P8_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P8_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P8_2_AMUXA = 4, /* Analog mux bus A */ + P8_2_AMUXB = 5, /* Analog mux bus B */ + P8_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P8_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P8_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:2 */ + P8_2_TCPWM1_LINE17 = 9, /* Digital Active - tcpwm[1].line[17]:0 */ + P8_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:56 */ + P8_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:56 */ + P8_2_LCD_COM56 = 12, /* Digital Deep Sleep - lcd.com[56]:0 */ + P8_2_LCD_SEG56 = 13, /* Digital Deep Sleep - lcd.seg[56]:0 */ + P8_2_LPCOMP_DSI_COMP0 = 15, /* Digital Deep Sleep - lpcomp.dsi_comp0:0 */ + P8_2_SCB4_UART_RTS = 18, /* Digital Active - scb[4].uart_rts:0 */ + P8_2_SCB4_SPI_CLK = 20, /* Digital Active - scb[4].spi_clk:0 */ + + /* P9.0 */ + P9_0_GPIO = 0, /* GPIO controls 'out' */ + P9_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P9_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P9_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P9_0_AMUXA = 4, /* Analog mux bus A */ + P9_0_AMUXB = 5, /* Analog mux bus B */ + P9_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P9_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P9_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:2 */ + P9_0_TCPWM1_LINE20 = 9, /* Digital Active - tcpwm[1].line[20]:0 */ + P9_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:62 */ + P9_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:62 */ + P9_0_LCD_COM0 = 12, /* Digital Deep Sleep - lcd.com[0]:1 */ + P9_0_LCD_SEG0 = 13, /* Digital Deep Sleep - lcd.seg[0]:1 */ + P9_0_SCB2_UART_RX = 18, /* Digital Active - scb[2].uart_rx:0 */ + P9_0_SCB2_I2C_SCL = 19, /* Digital Active - scb[2].i2c_scl:0 */ + P9_0_SCB2_SPI_MOSI = 20, /* Digital Active - scb[2].spi_mosi:0 */ + P9_0_PERI_TR_IO_INPUT18 = 24, /* Digital Active - peri.tr_io_input[18]:0 */ + P9_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:0 */ + + /* P9.1 */ + P9_1_GPIO = 0, /* GPIO controls 'out' */ + P9_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P9_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P9_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P9_1_AMUXA = 4, /* Analog mux bus A */ + P9_1_AMUXB = 5, /* Analog mux bus B */ + P9_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P9_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P9_1_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:2 */ + P9_1_TCPWM1_LINE_COMPL20 = 9, /* Digital Active - tcpwm[1].line_compl[20]:0 */ + P9_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:63 */ + P9_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:63 */ + P9_1_LCD_COM1 = 12, /* Digital Deep Sleep - lcd.com[1]:1 */ + P9_1_LCD_SEG1 = 13, /* Digital Deep Sleep - lcd.seg[1]:1 */ + P9_1_SCB2_UART_TX = 18, /* Digital Active - scb[2].uart_tx:0 */ + P9_1_SCB2_I2C_SDA = 19, /* Digital Active - scb[2].i2c_sda:0 */ + P9_1_SCB2_SPI_MISO = 20, /* Digital Active - scb[2].spi_miso:0 */ + P9_1_PERI_TR_IO_INPUT19 = 24, /* Digital Active - peri.tr_io_input[19]:0 */ + P9_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:0 */ + P9_1_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:1 */ + + /* P9.2 */ + P9_2_GPIO = 0, /* GPIO controls 'out' */ + P9_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P9_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P9_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P9_2_AMUXA = 4, /* Analog mux bus A */ + P9_2_AMUXB = 5, /* Analog mux bus B */ + P9_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P9_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P9_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:2 */ + P9_2_TCPWM1_LINE21 = 9, /* Digital Active - tcpwm[1].line[21]:0 */ + P9_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:64 */ + P9_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:64 */ + P9_2_LCD_COM2 = 12, /* Digital Deep Sleep - lcd.com[2]:1 */ + P9_2_LCD_SEG2 = 13, /* Digital Deep Sleep - lcd.seg[2]:1 */ + P9_2_SCB2_UART_RTS = 18, /* Digital Active - scb[2].uart_rts:0 */ + P9_2_SCB2_SPI_CLK = 20, /* Digital Active - scb[2].spi_clk:0 */ + P9_2_PASS_DSI_CTB_CMP0 = 22, /* Digital Active - pass.dsi_ctb_cmp0:1 */ + P9_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:0 */ + + /* P9.3 */ + P9_3_GPIO = 0, /* GPIO controls 'out' */ + P9_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P9_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P9_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P9_3_AMUXA = 4, /* Analog mux bus A */ + P9_3_AMUXB = 5, /* Analog mux bus B */ + P9_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P9_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P9_3_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:2 */ + P9_3_TCPWM1_LINE_COMPL21 = 9, /* Digital Active - tcpwm[1].line_compl[21]:0 */ + P9_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:65 */ + P9_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:65 */ + P9_3_LCD_COM3 = 12, /* Digital Deep Sleep - lcd.com[3]:1 */ + P9_3_LCD_SEG3 = 13, /* Digital Deep Sleep - lcd.seg[3]:1 */ + P9_3_SCB2_UART_CTS = 18, /* Digital Active - scb[2].uart_cts:0 */ + P9_3_SCB2_SPI_SELECT0 = 20, /* Digital Active - scb[2].spi_select0:0 */ + P9_3_PASS_DSI_CTB_CMP1 = 22, /* Digital Active - pass.dsi_ctb_cmp1:1 */ + P9_3_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:0 */ + P9_3_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:1 */ + + /* P10.0 */ + P10_0_GPIO = 0, /* GPIO controls 'out' */ + P10_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P10_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P10_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P10_0_AMUXA = 4, /* Analog mux bus A */ + P10_0_AMUXB = 5, /* Analog mux bus B */ + P10_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P10_0_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:2 */ + P10_0_TCPWM1_LINE22 = 9, /* Digital Active - tcpwm[1].line[22]:0 */ + P10_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:70 */ + P10_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:70 */ + P10_0_LCD_COM8 = 12, /* Digital Deep Sleep - lcd.com[8]:1 */ + P10_0_LCD_SEG8 = 13, /* Digital Deep Sleep - lcd.seg[8]:1 */ + P10_0_SCB1_UART_RX = 18, /* Digital Active - scb[1].uart_rx:1 */ + P10_0_SCB1_I2C_SCL = 19, /* Digital Active - scb[1].i2c_scl:1 */ + P10_0_SCB1_SPI_MOSI = 20, /* Digital Active - scb[1].spi_mosi:1 */ + P10_0_PERI_TR_IO_INPUT20 = 24, /* Digital Active - peri.tr_io_input[20]:0 */ + P10_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:1 */ + + /* P10.1 */ + P10_1_GPIO = 0, /* GPIO controls 'out' */ + P10_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P10_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P10_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P10_1_AMUXA = 4, /* Analog mux bus A */ + P10_1_AMUXB = 5, /* Analog mux bus B */ + P10_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P10_1_TCPWM0_LINE_COMPL6 = 8, /* Digital Active - tcpwm[0].line_compl[6]:2 */ + P10_1_TCPWM1_LINE_COMPL22 = 9, /* Digital Active - tcpwm[1].line_compl[22]:0 */ + P10_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:71 */ + P10_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:71 */ + P10_1_LCD_COM9 = 12, /* Digital Deep Sleep - lcd.com[9]:1 */ + P10_1_LCD_SEG9 = 13, /* Digital Deep Sleep - lcd.seg[9]:1 */ + P10_1_SCB1_UART_TX = 18, /* Digital Active - scb[1].uart_tx:1 */ + P10_1_SCB1_I2C_SDA = 19, /* Digital Active - scb[1].i2c_sda:1 */ + P10_1_SCB1_SPI_MISO = 20, /* Digital Active - scb[1].spi_miso:1 */ + P10_1_PERI_TR_IO_INPUT21 = 24, /* Digital Active - peri.tr_io_input[21]:0 */ + P10_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:1 */ + + /* P11.0 */ + P11_0_GPIO = 0, /* GPIO controls 'out' */ + P11_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P11_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P11_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P11_0_AMUXA = 4, /* Analog mux bus A */ + P11_0_AMUXB = 5, /* Analog mux bus B */ + P11_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P11_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P11_0_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:3 */ + P11_0_TCPWM1_LINE1 = 9, /* Digital Active - tcpwm[1].line[1]:1 */ + P11_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:78 */ + P11_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:78 */ + P11_0_LCD_COM16 = 12, /* Digital Deep Sleep - lcd.com[16]:1 */ + P11_0_LCD_SEG16 = 13, /* Digital Deep Sleep - lcd.seg[16]:1 */ + P11_0_SMIF_SPI_SELECT2 = 17, /* Digital Active - smif.spi_select2 */ + P11_0_SCB5_UART_RX = 18, /* Digital Active - scb[5].uart_rx:1 */ + P11_0_SCB5_I2C_SCL = 19, /* Digital Active - scb[5].i2c_scl:1 */ + P11_0_SCB5_SPI_MOSI = 20, /* Digital Active - scb[5].spi_mosi:1 */ + P11_0_PERI_TR_IO_INPUT22 = 24, /* Digital Active - peri.tr_io_input[22]:0 */ + + /* P11.1 */ + P11_1_GPIO = 0, /* GPIO controls 'out' */ + P11_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P11_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P11_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P11_1_AMUXA = 4, /* Analog mux bus A */ + P11_1_AMUXB = 5, /* Analog mux bus B */ + P11_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P11_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P11_1_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:3 */ + P11_1_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:1 */ + P11_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:79 */ + P11_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:79 */ + P11_1_LCD_COM17 = 12, /* Digital Deep Sleep - lcd.com[17]:1 */ + P11_1_LCD_SEG17 = 13, /* Digital Deep Sleep - lcd.seg[17]:1 */ + P11_1_SMIF_SPI_SELECT1 = 17, /* Digital Active - smif.spi_select1 */ + P11_1_SCB5_UART_TX = 18, /* Digital Active - scb[5].uart_tx:1 */ + P11_1_SCB5_I2C_SDA = 19, /* Digital Active - scb[5].i2c_sda:1 */ + P11_1_SCB5_SPI_MISO = 20, /* Digital Active - scb[5].spi_miso:1 */ + P11_1_PERI_TR_IO_INPUT23 = 24, /* Digital Active - peri.tr_io_input[23]:0 */ + + /* P11.2 */ + P11_2_GPIO = 0, /* GPIO controls 'out' */ + P11_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P11_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P11_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P11_2_AMUXA = 4, /* Analog mux bus A */ + P11_2_AMUXB = 5, /* Analog mux bus B */ + P11_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P11_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P11_2_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:3 */ + P11_2_TCPWM1_LINE2 = 9, /* Digital Active - tcpwm[1].line[2]:1 */ + P11_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:80 */ + P11_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:80 */ + P11_2_LCD_COM18 = 12, /* Digital Deep Sleep - lcd.com[18]:1 */ + P11_2_LCD_SEG18 = 13, /* Digital Deep Sleep - lcd.seg[18]:1 */ + P11_2_SMIF_SPI_SELECT0 = 17, /* Digital Active - smif.spi_select0 */ + P11_2_SCB5_UART_RTS = 18, /* Digital Active - scb[5].uart_rts:1 */ + P11_2_SCB5_SPI_CLK = 20, /* Digital Active - scb[5].spi_clk:1 */ + + /* P11.3 */ + P11_3_GPIO = 0, /* GPIO controls 'out' */ + P11_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P11_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P11_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P11_3_AMUXA = 4, /* Analog mux bus A */ + P11_3_AMUXB = 5, /* Analog mux bus B */ + P11_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P11_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P11_3_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:3 */ + P11_3_TCPWM1_LINE_COMPL2 = 9, /* Digital Active - tcpwm[1].line_compl[2]:1 */ + P11_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:81 */ + P11_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:81 */ + P11_3_LCD_COM19 = 12, /* Digital Deep Sleep - lcd.com[19]:1 */ + P11_3_LCD_SEG19 = 13, /* Digital Deep Sleep - lcd.seg[19]:1 */ + P11_3_SMIF_SPI_DATA3 = 17, /* Digital Active - smif.spi_data3 */ + P11_3_SCB5_UART_CTS = 18, /* Digital Active - scb[5].uart_cts:1 */ + P11_3_SCB5_SPI_SELECT0 = 20, /* Digital Active - scb[5].spi_select0:1 */ + P11_3_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:0 */ + + /* P11.4 */ + P11_4_GPIO = 0, /* GPIO controls 'out' */ + P11_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P11_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P11_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P11_4_AMUXA = 4, /* Analog mux bus A */ + P11_4_AMUXB = 5, /* Analog mux bus B */ + P11_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P11_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P11_4_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:3 */ + P11_4_TCPWM1_LINE3 = 9, /* Digital Active - tcpwm[1].line[3]:1 */ + P11_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:82 */ + P11_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:82 */ + P11_4_LCD_COM20 = 12, /* Digital Deep Sleep - lcd.com[20]:1 */ + P11_4_LCD_SEG20 = 13, /* Digital Deep Sleep - lcd.seg[20]:1 */ + P11_4_SMIF_SPI_DATA2 = 17, /* Digital Active - smif.spi_data2 */ + P11_4_SCB5_SPI_SELECT1 = 20, /* Digital Active - scb[5].spi_select1:1 */ + P11_4_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:0 */ + + /* P11.5 */ + P11_5_GPIO = 0, /* GPIO controls 'out' */ + P11_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P11_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P11_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P11_5_AMUXA = 4, /* Analog mux bus A */ + P11_5_AMUXB = 5, /* Analog mux bus B */ + P11_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P11_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P11_5_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:3 */ + P11_5_TCPWM1_LINE_COMPL3 = 9, /* Digital Active - tcpwm[1].line_compl[3]:1 */ + P11_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:83 */ + P11_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:83 */ + P11_5_LCD_COM21 = 12, /* Digital Deep Sleep - lcd.com[21]:1 */ + P11_5_LCD_SEG21 = 13, /* Digital Deep Sleep - lcd.seg[21]:1 */ + P11_5_SMIF_SPI_DATA1 = 17, /* Digital Active - smif.spi_data1 */ + P11_5_SCB5_SPI_SELECT2 = 20, /* Digital Active - scb[5].spi_select2:1 */ + + /* P11.6 */ + P11_6_GPIO = 0, /* GPIO controls 'out' */ + P11_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P11_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P11_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P11_6_AMUXA = 4, /* Analog mux bus A */ + P11_6_AMUXB = 5, /* Analog mux bus B */ + P11_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P11_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P11_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:84 */ + P11_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:84 */ + P11_6_LCD_COM22 = 12, /* Digital Deep Sleep - lcd.com[22]:1 */ + P11_6_LCD_SEG22 = 13, /* Digital Deep Sleep - lcd.seg[22]:1 */ + P11_6_SMIF_SPI_DATA0 = 17, /* Digital Active - smif.spi_data0 */ + P11_6_SCB5_SPI_SELECT3 = 20, /* Digital Active - scb[5].spi_select3:1 */ + + /* P11.7 */ + P11_7_GPIO = 0, /* GPIO controls 'out' */ + P11_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P11_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P11_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P11_7_AMUXA = 4, /* Analog mux bus A */ + P11_7_AMUXB = 5, /* Analog mux bus B */ + P11_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P11_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P11_7_SMIF_SPI_CLK = 17, /* Digital Active - smif.spi_clk */ + + /* P12.6 */ + P12_6_GPIO = 0, /* GPIO controls 'out' */ + P12_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P12_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P12_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P12_6_AMUXA = 4, /* Analog mux bus A */ + P12_6_AMUXB = 5, /* Analog mux bus B */ + P12_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P12_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P12_6_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:3 */ + P12_6_TCPWM1_LINE7 = 9, /* Digital Active - tcpwm[1].line[7]:1 */ + P12_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:91 */ + P12_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:91 */ + P12_6_LCD_COM29 = 12, /* Digital Deep Sleep - lcd.com[29]:1 */ + P12_6_LCD_SEG29 = 13, /* Digital Deep Sleep - lcd.seg[29]:1 */ + P12_6_SCB6_SPI_SELECT3 = 20, /* Digital Active - scb[6].spi_select3:0 */ + + /* P12.7 */ + P12_7_GPIO = 0, /* GPIO controls 'out' */ + P12_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P12_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P12_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P12_7_AMUXA = 4, /* Analog mux bus A */ + P12_7_AMUXB = 5, /* Analog mux bus B */ + P12_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P12_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P12_7_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:3 */ + P12_7_TCPWM1_LINE_COMPL7 = 9, /* Digital Active - tcpwm[1].line_compl[7]:1 */ + P12_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:92 */ + P12_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:92 */ + P12_7_LCD_COM30 = 12, /* Digital Deep Sleep - lcd.com[30]:1 */ + P12_7_LCD_SEG30 = 13 /* Digital Deep Sleep - lcd.seg[30]:1 */ +} en_hsiom_sel_t; + +#endif /* _GPIO_PSOC6_01_68_QFN_BLE_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_80_wlcsp.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_80_wlcsp.h index 563d18a3b9..584ab42be7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_80_wlcsp.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_80_wlcsp.h @@ -5,7 +5,7 @@ * PSoC6_01 device GPIO header for 80-WLCSP package * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_02_100_wlcsp.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_02_100_wlcsp.h index ddec3419fe..a8def7e5ce 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_02_100_wlcsp.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_02_100_wlcsp.h @@ -5,7 +5,7 @@ * PSoC6_02 device GPIO header for 100-WLCSP package * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_02_124_bga.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_02_124_bga.h index 959d8dfc89..49d3f2d021 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_02_124_bga.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_02_124_bga.h @@ -5,7 +5,7 @@ * PSoC6_02 device GPIO header for 124-BGA package * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_02_128_tqfp.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_02_128_tqfp.h index e9b1269744..3bb6778477 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_02_128_tqfp.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_02_128_tqfp.h @@ -5,7 +5,7 @@ * PSoC6_02 device GPIO header for 128-TQFP package * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_02_68_qfn.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_02_68_qfn.h new file mode 100644 index 0000000000..475c6e6295 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_02_68_qfn.h @@ -0,0 +1,1302 @@ +/***************************************************************************//** +* \file gpio_psoc6_02_68_qfn.h +* +* \brief +* PSoC6_02 device GPIO header for 68-QFN package +* +* \note +* Generator version: 1.5.0.1274 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _GPIO_PSOC6_02_68_QFN_H_ +#define _GPIO_PSOC6_02_68_QFN_H_ + +/* Package type */ +enum +{ + CY_GPIO_PACKAGE_QFN, + CY_GPIO_PACKAGE_BGA, + CY_GPIO_PACKAGE_CSP, + CY_GPIO_PACKAGE_WLCSP, + CY_GPIO_PACKAGE_LQFP, + CY_GPIO_PACKAGE_TQFP, + CY_GPIO_PACKAGE_SMT, +}; + +#define CY_GPIO_PACKAGE_TYPE CY_GPIO_PACKAGE_QFN +#define CY_GPIO_PIN_COUNT 68u + +/* AMUXBUS Segments */ +enum +{ + AMUXBUS_MAIN, + AMUXBUS_ADFT0_VDDD, + AMUXBUS_NOISY, + AMUXBUS_CSD0, + AMUXBUS_VDDIO_1, + AMUXBUS_CSD1, + AMUXBUS_SAR, + AMUXBUS_ANALOG_VDDD, + AMUXBUS_ANALOG_VDDA, +}; + +/* AMUX Splitter Controls */ +typedef enum +{ + AMUX_SPLIT_CTL_0 = 0x0000u, /* Left = AMUXBUS_ADFT0_VDDD; Right = AMUXBUS_MAIN */ + AMUX_SPLIT_CTL_1 = 0x0001u, /* Left = AMUXBUS_MAIN; Right = AMUXBUS_NOISY */ + AMUX_SPLIT_CTL_2 = 0x0002u, /* Left = AMUXBUS_NOISY; Right = AMUXBUS_CSD0 */ + AMUX_SPLIT_CTL_3 = 0x0003u, /* Left = AMUXBUS_VDDIO_1; Right = AMUXBUS_CSD0 */ + AMUX_SPLIT_CTL_4 = 0x0004u, /* Left = AMUXBUS_CSD1; Right = AMUXBUS_CSD0 */ + AMUX_SPLIT_CTL_5 = 0x0005u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_CSD1 */ + AMUX_SPLIT_CTL_6 = 0x0006u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_MAIN */ + AMUX_SPLIT_CTL_7 = 0x0007u /* Left = AMUXBUS_ANALOG_VDDD; Right = AMUXBUS_ANALOG_VDDA */ +} cy_en_amux_split_t; + +/* Port List */ +/* PORT 0 (GPIO) */ +#define P0_0_PORT GPIO_PRT0 +#define P0_0_PIN 0u +#define P0_0_NUM 0u +#define P0_0_AMUXSEGMENT AMUXBUS_MAIN +#define P0_1_PORT GPIO_PRT0 +#define P0_1_PIN 1u +#define P0_1_NUM 1u +#define P0_1_AMUXSEGMENT AMUXBUS_MAIN +#define P0_2_PORT GPIO_PRT0 +#define P0_2_PIN 2u +#define P0_2_NUM 2u +#define P0_2_AMUXSEGMENT AMUXBUS_MAIN +#define P0_3_PORT GPIO_PRT0 +#define P0_3_PIN 3u +#define P0_3_NUM 3u +#define P0_3_AMUXSEGMENT AMUXBUS_MAIN +#define P0_4_PORT GPIO_PRT0 +#define P0_4_PIN 4u +#define P0_4_NUM 4u +#define P0_4_AMUXSEGMENT AMUXBUS_MAIN +#define P0_5_PORT GPIO_PRT0 +#define P0_5_PIN 5u +#define P0_5_NUM 5u +#define P0_5_AMUXSEGMENT AMUXBUS_MAIN + +/* PORT 2 (GPIO) */ +#define P2_0_PORT GPIO_PRT2 +#define P2_0_PIN 0u +#define P2_0_NUM 0u +#define P2_0_AMUXSEGMENT AMUXBUS_NOISY +#define P2_1_PORT GPIO_PRT2 +#define P2_1_PIN 1u +#define P2_1_NUM 1u +#define P2_1_AMUXSEGMENT AMUXBUS_NOISY +#define P2_2_PORT GPIO_PRT2 +#define P2_2_PIN 2u +#define P2_2_NUM 2u +#define P2_2_AMUXSEGMENT AMUXBUS_NOISY +#define P2_3_PORT GPIO_PRT2 +#define P2_3_PIN 3u +#define P2_3_NUM 3u +#define P2_3_AMUXSEGMENT AMUXBUS_NOISY +#define P2_4_PORT GPIO_PRT2 +#define P2_4_PIN 4u +#define P2_4_NUM 4u +#define P2_4_AMUXSEGMENT AMUXBUS_NOISY +#define P2_5_PORT GPIO_PRT2 +#define P2_5_PIN 5u +#define P2_5_NUM 5u +#define P2_5_AMUXSEGMENT AMUXBUS_NOISY +#define P2_6_PORT GPIO_PRT2 +#define P2_6_PIN 6u +#define P2_6_NUM 6u +#define P2_6_AMUXSEGMENT AMUXBUS_NOISY +#define P2_7_PORT GPIO_PRT2 +#define P2_7_PIN 7u +#define P2_7_NUM 7u +#define P2_7_AMUXSEGMENT AMUXBUS_NOISY + +/* PORT 3 (GPIO) */ +#define P3_0_PORT GPIO_PRT3 +#define P3_0_PIN 0u +#define P3_0_NUM 0u +#define P3_0_AMUXSEGMENT AMUXBUS_NOISY +#define P3_1_PORT GPIO_PRT3 +#define P3_1_PIN 1u +#define P3_1_NUM 1u +#define P3_1_AMUXSEGMENT AMUXBUS_NOISY + +/* PORT 5 (GPIO) */ +#define P5_0_PORT GPIO_PRT5 +#define P5_0_PIN 0u +#define P5_0_NUM 0u +#define P5_0_AMUXSEGMENT AMUXBUS_CSD0 +#define P5_1_PORT GPIO_PRT5 +#define P5_1_PIN 1u +#define P5_1_NUM 1u +#define P5_1_AMUXSEGMENT AMUXBUS_CSD0 +#define P5_6_PORT GPIO_PRT5 +#define P5_6_PIN 6u +#define P5_6_NUM 6u +#define P5_6_AMUXSEGMENT AMUXBUS_CSD0 +#define P5_7_PORT GPIO_PRT5 +#define P5_7_PIN 7u +#define P5_7_NUM 7u +#define P5_7_AMUXSEGMENT AMUXBUS_CSD0 + +/* PORT 6 (GPIO) */ +#define P6_2_PORT GPIO_PRT6 +#define P6_2_PIN 2u +#define P6_2_NUM 2u +#define P6_2_AMUXSEGMENT AMUXBUS_CSD0 +#define P6_3_PORT GPIO_PRT6 +#define P6_3_PIN 3u +#define P6_3_NUM 3u +#define P6_3_AMUXSEGMENT AMUXBUS_CSD0 +#define P6_4_PORT GPIO_PRT6 +#define P6_4_PIN 4u +#define P6_4_NUM 4u +#define P6_4_AMUXSEGMENT AMUXBUS_CSD0 +#define P6_5_PORT GPIO_PRT6 +#define P6_5_PIN 5u +#define P6_5_NUM 5u +#define P6_5_AMUXSEGMENT AMUXBUS_CSD0 +#define P6_6_PORT GPIO_PRT6 +#define P6_6_PIN 6u +#define P6_6_NUM 6u +#define P6_6_AMUXSEGMENT AMUXBUS_CSD0 +#define P6_7_PORT GPIO_PRT6 +#define P6_7_PIN 7u +#define P6_7_NUM 7u +#define P6_7_AMUXSEGMENT AMUXBUS_CSD0 + +/* PORT 7 (GPIO) */ +#define P7_0_PORT GPIO_PRT7 +#define P7_0_PIN 0u +#define P7_0_NUM 0u +#define P7_0_AMUXSEGMENT AMUXBUS_CSD0 +#define P7_1_PORT GPIO_PRT7 +#define P7_1_PIN 1u +#define P7_1_NUM 1u +#define P7_1_AMUXSEGMENT AMUXBUS_CSD0 +#define P7_2_PORT GPIO_PRT7 +#define P7_2_PIN 2u +#define P7_2_NUM 2u +#define P7_2_AMUXSEGMENT AMUXBUS_CSD0 +#define P7_3_PORT GPIO_PRT7 +#define P7_3_PIN 3u +#define P7_3_NUM 3u +#define P7_3_AMUXSEGMENT AMUXBUS_CSD0 +#define P7_7_PORT GPIO_PRT7 +#define P7_7_PIN 7u +#define P7_7_NUM 7u +#define P7_7_AMUXSEGMENT AMUXBUS_CSD0 + +/* PORT 8 (GPIO) */ +#define P8_0_PORT GPIO_PRT8 +#define P8_0_PIN 0u +#define P8_0_NUM 0u +#define P8_0_AMUXSEGMENT AMUXBUS_CSD0 +#define P8_1_PORT GPIO_PRT8 +#define P8_1_PIN 1u +#define P8_1_NUM 1u +#define P8_1_AMUXSEGMENT AMUXBUS_CSD0 + +/* PORT 9 (GPIO) */ +#define P9_0_PORT GPIO_PRT9 +#define P9_0_PIN 0u +#define P9_0_NUM 0u +#define P9_0_AMUXSEGMENT AMUXBUS_SAR +#define P9_1_PORT GPIO_PRT9 +#define P9_1_PIN 1u +#define P9_1_NUM 1u +#define P9_1_AMUXSEGMENT AMUXBUS_SAR +#define P9_2_PORT GPIO_PRT9 +#define P9_2_PIN 2u +#define P9_2_NUM 2u +#define P9_2_AMUXSEGMENT AMUXBUS_SAR +#define P9_3_PORT GPIO_PRT9 +#define P9_3_PIN 3u +#define P9_3_NUM 3u +#define P9_3_AMUXSEGMENT AMUXBUS_SAR + +/* PORT 10 (GPIO) */ +#define P10_0_PORT GPIO_PRT10 +#define P10_0_PIN 0u +#define P10_0_NUM 0u +#define P10_0_AMUXSEGMENT AMUXBUS_SAR +#define P10_1_PORT GPIO_PRT10 +#define P10_1_PIN 1u +#define P10_1_NUM 1u +#define P10_1_AMUXSEGMENT AMUXBUS_SAR +#define P10_2_PORT GPIO_PRT10 +#define P10_2_PIN 2u +#define P10_2_NUM 2u +#define P10_2_AMUXSEGMENT AMUXBUS_SAR +#define P10_3_PORT GPIO_PRT10 +#define P10_3_PIN 3u +#define P10_3_NUM 3u +#define P10_3_AMUXSEGMENT AMUXBUS_SAR +#define P10_4_PORT GPIO_PRT10 +#define P10_4_PIN 4u +#define P10_4_NUM 4u +#define P10_4_AMUXSEGMENT AMUXBUS_SAR +#define P10_5_PORT GPIO_PRT10 +#define P10_5_PIN 5u +#define P10_5_NUM 5u +#define P10_5_AMUXSEGMENT AMUXBUS_SAR + +/* PORT 11 (GPIO) */ +#define P11_0_PORT GPIO_PRT11 +#define P11_0_PIN 0u +#define P11_0_NUM 0u +#define P11_0_AMUXSEGMENT AMUXBUS_MAIN +#define P11_1_PORT GPIO_PRT11 +#define P11_1_PIN 1u +#define P11_1_NUM 1u +#define P11_1_AMUXSEGMENT AMUXBUS_MAIN +#define P11_2_PORT GPIO_PRT11 +#define P11_2_PIN 2u +#define P11_2_NUM 2u +#define P11_2_AMUXSEGMENT AMUXBUS_MAIN +#define P11_3_PORT GPIO_PRT11 +#define P11_3_PIN 3u +#define P11_3_NUM 3u +#define P11_3_AMUXSEGMENT AMUXBUS_MAIN +#define P11_4_PORT GPIO_PRT11 +#define P11_4_PIN 4u +#define P11_4_NUM 4u +#define P11_4_AMUXSEGMENT AMUXBUS_MAIN +#define P11_5_PORT GPIO_PRT11 +#define P11_5_PIN 5u +#define P11_5_NUM 5u +#define P11_5_AMUXSEGMENT AMUXBUS_MAIN +#define P11_6_PORT GPIO_PRT11 +#define P11_6_PIN 6u +#define P11_6_NUM 6u +#define P11_6_AMUXSEGMENT AMUXBUS_MAIN +#define P11_7_PORT GPIO_PRT11 +#define P11_7_PIN 7u +#define P11_7_NUM 7u +#define P11_7_AMUXSEGMENT AMUXBUS_MAIN + +/* PORT 12 (GPIO) */ +#define P12_6_PORT GPIO_PRT12 +#define P12_6_PIN 6u +#define P12_6_NUM 6u +#define P12_6_AMUXSEGMENT AMUXBUS_MAIN +#define P12_7_PORT GPIO_PRT12 +#define P12_7_PIN 7u +#define P12_7_NUM 7u +#define P12_7_AMUXSEGMENT AMUXBUS_MAIN + +/* PORT 14 (AUX) */ +#define USBDP_PORT GPIO_PRT14 +#define USBDP_PIN 0u +#define USBDP_NUM 0u +#define USBDP_AMUXSEGMENT AMUXBUS_NOISY +#define USBDM_PORT GPIO_PRT14 +#define USBDM_PIN 1u +#define USBDM_NUM 1u +#define USBDM_AMUXSEGMENT AMUXBUS_NOISY + +/* Analog Connections */ +#define CSD_CMODPADD_PORT 7u +#define CSD_CMODPADD_PIN 1u +#define CSD_CMODPADS_PORT 7u +#define CSD_CMODPADS_PIN 1u +#define CSD_CSH_TANKPADD_PORT 7u +#define CSD_CSH_TANKPADD_PIN 2u +#define CSD_CSH_TANKPADS_PORT 7u +#define CSD_CSH_TANKPADS_PIN 2u +#define CSD_CSHIELDPADS_PORT 7u +#define CSD_CSHIELDPADS_PIN 7u +#define CSD_VREF_EXT_PORT 7u +#define CSD_VREF_EXT_PIN 3u +#define IOSS_ADFT0_NET_PORT 10u +#define IOSS_ADFT0_NET_PIN 0u +#define IOSS_ADFT1_NET_PORT 10u +#define IOSS_ADFT1_NET_PIN 1u +#define LPCOMP_INN_COMP0_PORT 5u +#define LPCOMP_INN_COMP0_PIN 7u +#define LPCOMP_INN_COMP1_PORT 6u +#define LPCOMP_INN_COMP1_PIN 3u +#define LPCOMP_INP_COMP0_PORT 5u +#define LPCOMP_INP_COMP0_PIN 6u +#define LPCOMP_INP_COMP1_PORT 6u +#define LPCOMP_INP_COMP1_PIN 2u +#define PASS_SARMUX_PADS0_PORT 10u +#define PASS_SARMUX_PADS0_PIN 0u +#define PASS_SARMUX_PADS1_PORT 10u +#define PASS_SARMUX_PADS1_PIN 1u +#define PASS_SARMUX_PADS2_PORT 10u +#define PASS_SARMUX_PADS2_PIN 2u +#define PASS_SARMUX_PADS3_PORT 10u +#define PASS_SARMUX_PADS3_PIN 3u +#define PASS_SARMUX_PADS4_PORT 10u +#define PASS_SARMUX_PADS4_PIN 4u +#define PASS_SARMUX_PADS5_PORT 10u +#define PASS_SARMUX_PADS5_PIN 5u +#define SRSS_ADFT_PIN0_PORT 10u +#define SRSS_ADFT_PIN0_PIN 0u +#define SRSS_ADFT_PIN1_PORT 10u +#define SRSS_ADFT_PIN1_PIN 1u +#define SRSS_ECO_IN_PORT 12u +#define SRSS_ECO_IN_PIN 6u +#define SRSS_ECO_OUT_PORT 12u +#define SRSS_ECO_OUT_PIN 7u +#define SRSS_WCO_IN_PORT 0u +#define SRSS_WCO_IN_PIN 0u +#define SRSS_WCO_OUT_PORT 0u +#define SRSS_WCO_OUT_PIN 1u + +/* HSIOM Connections */ +typedef enum +{ + /* Generic HSIOM connections */ + HSIOM_SEL_GPIO = 0, /* GPIO controls 'out' */ + HSIOM_SEL_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + HSIOM_SEL_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + HSIOM_SEL_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + HSIOM_SEL_AMUXA = 4, /* Analog mux bus A */ + HSIOM_SEL_AMUXB = 5, /* Analog mux bus B */ + HSIOM_SEL_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + HSIOM_SEL_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + HSIOM_SEL_ACT_0 = 8, /* Active functionality 0 */ + HSIOM_SEL_ACT_1 = 9, /* Active functionality 1 */ + HSIOM_SEL_ACT_2 = 10, /* Active functionality 2 */ + HSIOM_SEL_ACT_3 = 11, /* Active functionality 3 */ + HSIOM_SEL_DS_0 = 12, /* DeepSleep functionality 0 */ + HSIOM_SEL_DS_1 = 13, /* DeepSleep functionality 1 */ + HSIOM_SEL_DS_2 = 14, /* DeepSleep functionality 2 */ + HSIOM_SEL_DS_3 = 15, /* DeepSleep functionality 3 */ + HSIOM_SEL_ACT_4 = 16, /* Active functionality 4 */ + HSIOM_SEL_ACT_5 = 17, /* Active functionality 5 */ + HSIOM_SEL_ACT_6 = 18, /* Active functionality 6 */ + HSIOM_SEL_ACT_7 = 19, /* Active functionality 7 */ + HSIOM_SEL_ACT_8 = 20, /* Active functionality 8 */ + HSIOM_SEL_ACT_9 = 21, /* Active functionality 9 */ + HSIOM_SEL_ACT_10 = 22, /* Active functionality 10 */ + HSIOM_SEL_ACT_11 = 23, /* Active functionality 11 */ + HSIOM_SEL_ACT_12 = 24, /* Active functionality 12 */ + HSIOM_SEL_ACT_13 = 25, /* Active functionality 13 */ + HSIOM_SEL_ACT_14 = 26, /* Active functionality 14 */ + HSIOM_SEL_ACT_15 = 27, /* Active functionality 15 */ + HSIOM_SEL_DS_4 = 28, /* DeepSleep functionality 4 */ + HSIOM_SEL_DS_5 = 29, /* DeepSleep functionality 5 */ + HSIOM_SEL_DS_6 = 30, /* DeepSleep functionality 6 */ + HSIOM_SEL_DS_7 = 31, /* DeepSleep functionality 7 */ + + /* P0.0 */ + P0_0_GPIO = 0, /* GPIO controls 'out' */ + P0_0_AMUXA = 4, /* Analog mux bus A */ + P0_0_AMUXB = 5, /* Analog mux bus B */ + P0_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P0_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P0_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:0 */ + P0_0_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:0 */ + P0_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:0 */ + P0_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:0 */ + P0_0_LCD_COM0 = 12, /* Digital Deep Sleep - lcd.com[0]:0 */ + P0_0_LCD_SEG0 = 13, /* Digital Deep Sleep - lcd.seg[0]:0 */ + P0_0_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:0 */ + P0_0_SCB0_SPI_SELECT1 = 20, /* Digital Active - scb[0].spi_select1:0 */ + P0_0_PERI_TR_IO_INPUT0 = 24, /* Digital Active - peri.tr_io_input[0]:0 */ + + /* P0.1 */ + P0_1_GPIO = 0, /* GPIO controls 'out' */ + P0_1_AMUXA = 4, /* Analog mux bus A */ + P0_1_AMUXB = 5, /* Analog mux bus B */ + P0_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P0_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P0_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:0 */ + P0_1_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:0 */ + P0_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:1 */ + P0_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:1 */ + P0_1_LCD_COM1 = 12, /* Digital Deep Sleep - lcd.com[1]:0 */ + P0_1_LCD_SEG1 = 13, /* Digital Deep Sleep - lcd.seg[1]:0 */ + P0_1_SCB0_SPI_SELECT2 = 20, /* Digital Active - scb[0].spi_select2:0 */ + P0_1_PERI_TR_IO_INPUT1 = 24, /* Digital Active - peri.tr_io_input[1]:0 */ + P0_1_CPUSS_SWJ_TRSTN = 29, /* Digital Deep Sleep - cpuss.swj_trstn */ + + /* P0.2 */ + P0_2_GPIO = 0, /* GPIO controls 'out' */ + P0_2_AMUXA = 4, /* Analog mux bus A */ + P0_2_AMUXB = 5, /* Analog mux bus B */ + P0_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P0_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P0_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:0 */ + P0_2_TCPWM1_LINE1 = 9, /* Digital Active - tcpwm[1].line[1]:0 */ + P0_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:2 */ + P0_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:2 */ + P0_2_LCD_COM2 = 12, /* Digital Deep Sleep - lcd.com[2]:0 */ + P0_2_LCD_SEG2 = 13, /* Digital Deep Sleep - lcd.seg[2]:0 */ + P0_2_SCB0_UART_RX = 18, /* Digital Active - scb[0].uart_rx:0 */ + P0_2_SCB0_I2C_SCL = 19, /* Digital Active - scb[0].i2c_scl:0 */ + P0_2_SCB0_SPI_MOSI = 20, /* Digital Active - scb[0].spi_mosi:0 */ + + /* P0.3 */ + P0_3_GPIO = 0, /* GPIO controls 'out' */ + P0_3_AMUXA = 4, /* Analog mux bus A */ + P0_3_AMUXB = 5, /* Analog mux bus B */ + P0_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P0_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P0_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:0 */ + P0_3_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:0 */ + P0_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:3 */ + P0_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:3 */ + P0_3_LCD_COM3 = 12, /* Digital Deep Sleep - lcd.com[3]:0 */ + P0_3_LCD_SEG3 = 13, /* Digital Deep Sleep - lcd.seg[3]:0 */ + P0_3_SCB0_UART_TX = 18, /* Digital Active - scb[0].uart_tx:0 */ + P0_3_SCB0_I2C_SDA = 19, /* Digital Active - scb[0].i2c_sda:0 */ + P0_3_SCB0_SPI_MISO = 20, /* Digital Active - scb[0].spi_miso:0 */ + + /* P0.4 */ + P0_4_GPIO = 0, /* GPIO controls 'out' */ + P0_4_AMUXA = 4, /* Analog mux bus A */ + P0_4_AMUXB = 5, /* Analog mux bus B */ + P0_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P0_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P0_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:0 */ + P0_4_TCPWM1_LINE2 = 9, /* Digital Active - tcpwm[1].line[2]:0 */ + P0_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:4 */ + P0_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:4 */ + P0_4_LCD_COM4 = 12, /* Digital Deep Sleep - lcd.com[4]:0 */ + P0_4_LCD_SEG4 = 13, /* Digital Deep Sleep - lcd.seg[4]:0 */ + P0_4_SCB0_UART_RTS = 18, /* Digital Active - scb[0].uart_rts:0 */ + P0_4_SCB0_SPI_CLK = 20, /* Digital Active - scb[0].spi_clk:0 */ + P0_4_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:2 */ + + /* P0.5 */ + P0_5_GPIO = 0, /* GPIO controls 'out' */ + P0_5_AMUXA = 4, /* Analog mux bus A */ + P0_5_AMUXB = 5, /* Analog mux bus B */ + P0_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P0_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P0_5_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:0 */ + P0_5_TCPWM1_LINE_COMPL2 = 9, /* Digital Active - tcpwm[1].line_compl[2]:0 */ + P0_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:5 */ + P0_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:5 */ + P0_5_LCD_COM5 = 12, /* Digital Deep Sleep - lcd.com[5]:0 */ + P0_5_LCD_SEG5 = 13, /* Digital Deep Sleep - lcd.seg[5]:0 */ + P0_5_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:1 */ + P0_5_SCB0_UART_CTS = 18, /* Digital Active - scb[0].uart_cts:0 */ + P0_5_SCB0_SPI_SELECT0 = 20, /* Digital Active - scb[0].spi_select0:0 */ + P0_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:2 */ + + /* USBDM */ + USBDM_GPIO = 0, /* GPIO controls 'out' */ + + /* USBDP */ + USBDP_GPIO = 0, /* GPIO controls 'out' */ + + /* P2.0 */ + P2_0_GPIO = 0, /* GPIO controls 'out' */ + P2_0_AMUXA = 4, /* Analog mux bus A */ + P2_0_AMUXB = 5, /* Analog mux bus B */ + P2_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P2_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P2_0_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:4 */ + P2_0_TCPWM1_LINE15 = 9, /* Digital Active - tcpwm[1].line[15]:1 */ + P2_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:12 */ + P2_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:12 */ + P2_0_LCD_COM12 = 12, /* Digital Deep Sleep - lcd.com[12]:0 */ + P2_0_LCD_SEG12 = 13, /* Digital Deep Sleep - lcd.seg[12]:0 */ + P2_0_SCB1_UART_RX = 18, /* Digital Active - scb[1].uart_rx:0 */ + P2_0_SCB1_I2C_SCL = 19, /* Digital Active - scb[1].i2c_scl:0 */ + P2_0_SCB1_SPI_MOSI = 20, /* Digital Active - scb[1].spi_mosi:0 */ + P2_0_PERI_TR_IO_INPUT4 = 24, /* Digital Active - peri.tr_io_input[4]:0 */ + P2_0_SDHC0_CARD_DAT_3TO00 = 26, /* Digital Active - sdhc[0].card_dat_3to0[0] */ + + /* P2.1 */ + P2_1_GPIO = 0, /* GPIO controls 'out' */ + P2_1_AMUXA = 4, /* Analog mux bus A */ + P2_1_AMUXB = 5, /* Analog mux bus B */ + P2_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P2_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P2_1_TCPWM0_LINE_COMPL6 = 8, /* Digital Active - tcpwm[0].line_compl[6]:4 */ + P2_1_TCPWM1_LINE_COMPL15 = 9, /* Digital Active - tcpwm[1].line_compl[15]:1 */ + P2_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:13 */ + P2_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:13 */ + P2_1_LCD_COM13 = 12, /* Digital Deep Sleep - lcd.com[13]:0 */ + P2_1_LCD_SEG13 = 13, /* Digital Deep Sleep - lcd.seg[13]:0 */ + P2_1_SCB1_UART_TX = 18, /* Digital Active - scb[1].uart_tx:0 */ + P2_1_SCB1_I2C_SDA = 19, /* Digital Active - scb[1].i2c_sda:0 */ + P2_1_SCB1_SPI_MISO = 20, /* Digital Active - scb[1].spi_miso:0 */ + P2_1_PERI_TR_IO_INPUT5 = 24, /* Digital Active - peri.tr_io_input[5]:0 */ + P2_1_SDHC0_CARD_DAT_3TO01 = 26, /* Digital Active - sdhc[0].card_dat_3to0[1] */ + + /* P2.2 */ + P2_2_GPIO = 0, /* GPIO controls 'out' */ + P2_2_AMUXA = 4, /* Analog mux bus A */ + P2_2_AMUXB = 5, /* Analog mux bus B */ + P2_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P2_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P2_2_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:4 */ + P2_2_TCPWM1_LINE16 = 9, /* Digital Active - tcpwm[1].line[16]:1 */ + P2_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:14 */ + P2_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:14 */ + P2_2_LCD_COM14 = 12, /* Digital Deep Sleep - lcd.com[14]:0 */ + P2_2_LCD_SEG14 = 13, /* Digital Deep Sleep - lcd.seg[14]:0 */ + P2_2_SCB1_UART_RTS = 18, /* Digital Active - scb[1].uart_rts:0 */ + P2_2_SCB1_SPI_CLK = 20, /* Digital Active - scb[1].spi_clk:0 */ + P2_2_SDHC0_CARD_DAT_3TO02 = 26, /* Digital Active - sdhc[0].card_dat_3to0[2] */ + + /* P2.3 */ + P2_3_GPIO = 0, /* GPIO controls 'out' */ + P2_3_AMUXA = 4, /* Analog mux bus A */ + P2_3_AMUXB = 5, /* Analog mux bus B */ + P2_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P2_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P2_3_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:4 */ + P2_3_TCPWM1_LINE_COMPL16 = 9, /* Digital Active - tcpwm[1].line_compl[16]:1 */ + P2_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:15 */ + P2_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:15 */ + P2_3_LCD_COM15 = 12, /* Digital Deep Sleep - lcd.com[15]:0 */ + P2_3_LCD_SEG15 = 13, /* Digital Deep Sleep - lcd.seg[15]:0 */ + P2_3_SCB1_UART_CTS = 18, /* Digital Active - scb[1].uart_cts:0 */ + P2_3_SCB1_SPI_SELECT0 = 20, /* Digital Active - scb[1].spi_select0:0 */ + P2_3_SDHC0_CARD_DAT_3TO03 = 26, /* Digital Active - sdhc[0].card_dat_3to0[3] */ + + /* P2.4 */ + P2_4_GPIO = 0, /* GPIO controls 'out' */ + P2_4_AMUXA = 4, /* Analog mux bus A */ + P2_4_AMUXB = 5, /* Analog mux bus B */ + P2_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P2_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P2_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:5 */ + P2_4_TCPWM1_LINE17 = 9, /* Digital Active - tcpwm[1].line[17]:1 */ + P2_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:16 */ + P2_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:16 */ + P2_4_LCD_COM16 = 12, /* Digital Deep Sleep - lcd.com[16]:0 */ + P2_4_LCD_SEG16 = 13, /* Digital Deep Sleep - lcd.seg[16]:0 */ + P2_4_SCB9_UART_RX = 18, /* Digital Active - scb[9].uart_rx:0 */ + P2_4_SCB9_I2C_SCL = 19, /* Digital Active - scb[9].i2c_scl:0 */ + P2_4_SCB1_SPI_SELECT1 = 20, /* Digital Active - scb[1].spi_select1:0 */ + P2_4_SDHC0_CARD_CMD = 26, /* Digital Active - sdhc[0].card_cmd */ + + /* P2.5 */ + P2_5_GPIO = 0, /* GPIO controls 'out' */ + P2_5_AMUXA = 4, /* Analog mux bus A */ + P2_5_AMUXB = 5, /* Analog mux bus B */ + P2_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P2_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P2_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:5 */ + P2_5_TCPWM1_LINE_COMPL17 = 9, /* Digital Active - tcpwm[1].line_compl[17]:1 */ + P2_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:17 */ + P2_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:17 */ + P2_5_LCD_COM17 = 12, /* Digital Deep Sleep - lcd.com[17]:0 */ + P2_5_LCD_SEG17 = 13, /* Digital Deep Sleep - lcd.seg[17]:0 */ + P2_5_SCB9_UART_TX = 18, /* Digital Active - scb[9].uart_tx:0 */ + P2_5_SCB9_I2C_SDA = 19, /* Digital Active - scb[9].i2c_sda:0 */ + P2_5_SCB1_SPI_SELECT2 = 20, /* Digital Active - scb[1].spi_select2:0 */ + P2_5_SDHC0_CLK_CARD = 26, /* Digital Active - sdhc[0].clk_card */ + + /* P2.6 */ + P2_6_GPIO = 0, /* GPIO controls 'out' */ + P2_6_AMUXA = 4, /* Analog mux bus A */ + P2_6_AMUXB = 5, /* Analog mux bus B */ + P2_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P2_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P2_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:5 */ + P2_6_TCPWM1_LINE18 = 9, /* Digital Active - tcpwm[1].line[18]:1 */ + P2_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:18 */ + P2_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:18 */ + P2_6_LCD_COM18 = 12, /* Digital Deep Sleep - lcd.com[18]:0 */ + P2_6_LCD_SEG18 = 13, /* Digital Deep Sleep - lcd.seg[18]:0 */ + P2_6_SCB9_UART_RTS = 18, /* Digital Active - scb[9].uart_rts:0 */ + P2_6_SCB1_SPI_SELECT3 = 20, /* Digital Active - scb[1].spi_select3:0 */ + P2_6_SDHC0_CARD_DETECT_N = 26, /* Digital Active - sdhc[0].card_detect_n */ + + /* P2.7 */ + P2_7_GPIO = 0, /* GPIO controls 'out' */ + P2_7_AMUXA = 4, /* Analog mux bus A */ + P2_7_AMUXB = 5, /* Analog mux bus B */ + P2_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P2_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P2_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:5 */ + P2_7_TCPWM1_LINE_COMPL18 = 9, /* Digital Active - tcpwm[1].line_compl[18]:1 */ + P2_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:19 */ + P2_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:19 */ + P2_7_LCD_COM19 = 12, /* Digital Deep Sleep - lcd.com[19]:0 */ + P2_7_LCD_SEG19 = 13, /* Digital Deep Sleep - lcd.seg[19]:0 */ + P2_7_SCB9_UART_CTS = 18, /* Digital Active - scb[9].uart_cts:0 */ + P2_7_SDHC0_CARD_MECH_WRITE_PROT = 26, /* Digital Active - sdhc[0].card_mech_write_prot */ + + /* P3.0 */ + P3_0_GPIO = 0, /* GPIO controls 'out' */ + P3_0_AMUXA = 4, /* Analog mux bus A */ + P3_0_AMUXB = 5, /* Analog mux bus B */ + P3_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P3_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P3_0_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:5 */ + P3_0_TCPWM1_LINE19 = 9, /* Digital Active - tcpwm[1].line[19]:1 */ + P3_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:20 */ + P3_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:20 */ + P3_0_LCD_COM20 = 12, /* Digital Deep Sleep - lcd.com[20]:0 */ + P3_0_LCD_SEG20 = 13, /* Digital Deep Sleep - lcd.seg[20]:0 */ + P3_0_SCB2_UART_RX = 18, /* Digital Active - scb[2].uart_rx:1 */ + P3_0_SCB2_I2C_SCL = 19, /* Digital Active - scb[2].i2c_scl:1 */ + P3_0_SCB2_SPI_MOSI = 20, /* Digital Active - scb[2].spi_mosi:1 */ + P3_0_PERI_TR_IO_INPUT6 = 24, /* Digital Active - peri.tr_io_input[6]:0 */ + P3_0_SDHC0_IO_VOLT_SEL = 26, /* Digital Active - sdhc[0].io_volt_sel */ + + /* P3.1 */ + P3_1_GPIO = 0, /* GPIO controls 'out' */ + P3_1_AMUXA = 4, /* Analog mux bus A */ + P3_1_AMUXB = 5, /* Analog mux bus B */ + P3_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P3_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P3_1_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:5 */ + P3_1_TCPWM1_LINE_COMPL19 = 9, /* Digital Active - tcpwm[1].line_compl[19]:1 */ + P3_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:21 */ + P3_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:21 */ + P3_1_LCD_COM21 = 12, /* Digital Deep Sleep - lcd.com[21]:0 */ + P3_1_LCD_SEG21 = 13, /* Digital Deep Sleep - lcd.seg[21]:0 */ + P3_1_SCB2_UART_TX = 18, /* Digital Active - scb[2].uart_tx:1 */ + P3_1_SCB2_I2C_SDA = 19, /* Digital Active - scb[2].i2c_sda:1 */ + P3_1_SCB2_SPI_MISO = 20, /* Digital Active - scb[2].spi_miso:1 */ + P3_1_PERI_TR_IO_INPUT7 = 24, /* Digital Active - peri.tr_io_input[7]:0 */ + P3_1_SDHC0_CARD_IF_PWR_EN = 26, /* Digital Active - sdhc[0].card_if_pwr_en */ + + /* P5.0 */ + P5_0_GPIO = 0, /* GPIO controls 'out' */ + P5_0_AMUXA = 4, /* Analog mux bus A */ + P5_0_AMUXB = 5, /* Analog mux bus B */ + P5_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P5_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P5_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:0 */ + P5_0_TCPWM1_LINE4 = 9, /* Digital Active - tcpwm[1].line[4]:0 */ + P5_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:30 */ + P5_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:30 */ + P5_0_LCD_COM30 = 12, /* Digital Deep Sleep - lcd.com[30]:0 */ + P5_0_LCD_SEG30 = 13, /* Digital Deep Sleep - lcd.seg[30]:0 */ + P5_0_SCB5_UART_RX = 18, /* Digital Active - scb[5].uart_rx:0 */ + P5_0_SCB5_I2C_SCL = 19, /* Digital Active - scb[5].i2c_scl:0 */ + P5_0_SCB5_SPI_MOSI = 20, /* Digital Active - scb[5].spi_mosi:0 */ + P5_0_AUDIOSS0_CLK_I2S_IF = 22, /* Digital Active - audioss[0].clk_i2s_if:0 */ + P5_0_PERI_TR_IO_INPUT10 = 24, /* Digital Active - peri.tr_io_input[10]:0 */ + + /* P5.1 */ + P5_1_GPIO = 0, /* GPIO controls 'out' */ + P5_1_AMUXA = 4, /* Analog mux bus A */ + P5_1_AMUXB = 5, /* Analog mux bus B */ + P5_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P5_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P5_1_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:0 */ + P5_1_TCPWM1_LINE_COMPL4 = 9, /* Digital Active - tcpwm[1].line_compl[4]:0 */ + P5_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:31 */ + P5_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:31 */ + P5_1_LCD_COM31 = 12, /* Digital Deep Sleep - lcd.com[31]:0 */ + P5_1_LCD_SEG31 = 13, /* Digital Deep Sleep - lcd.seg[31]:0 */ + P5_1_SCB5_UART_TX = 18, /* Digital Active - scb[5].uart_tx:0 */ + P5_1_SCB5_I2C_SDA = 19, /* Digital Active - scb[5].i2c_sda:0 */ + P5_1_SCB5_SPI_MISO = 20, /* Digital Active - scb[5].spi_miso:0 */ + P5_1_AUDIOSS0_TX_SCK = 22, /* Digital Active - audioss[0].tx_sck:0 */ + P5_1_PERI_TR_IO_INPUT11 = 24, /* Digital Active - peri.tr_io_input[11]:0 */ + + /* P5.6 */ + P5_6_GPIO = 0, /* GPIO controls 'out' */ + P5_6_AMUXA = 4, /* Analog mux bus A */ + P5_6_AMUXB = 5, /* Analog mux bus B */ + P5_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P5_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P5_6_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:0 */ + P5_6_TCPWM1_LINE7 = 9, /* Digital Active - tcpwm[1].line[7]:0 */ + P5_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:36 */ + P5_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:36 */ + P5_6_LCD_COM36 = 12, /* Digital Deep Sleep - lcd.com[36]:0 */ + P5_6_LCD_SEG36 = 13, /* Digital Deep Sleep - lcd.seg[36]:0 */ + P5_6_SCB10_UART_RTS = 18, /* Digital Active - scb[10].uart_rts:0 */ + P5_6_SCB5_SPI_SELECT3 = 20, /* Digital Active - scb[5].spi_select3:0 */ + P5_6_AUDIOSS0_RX_SDI = 22, /* Digital Active - audioss[0].rx_sdi:0 */ + + /* P5.7 */ + P5_7_GPIO = 0, /* GPIO controls 'out' */ + P5_7_AMUXA = 4, /* Analog mux bus A */ + P5_7_AMUXB = 5, /* Analog mux bus B */ + P5_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P5_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P5_7_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:0 */ + P5_7_TCPWM1_LINE_COMPL7 = 9, /* Digital Active - tcpwm[1].line_compl[7]:0 */ + P5_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:37 */ + P5_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:37 */ + P5_7_LCD_COM37 = 12, /* Digital Deep Sleep - lcd.com[37]:0 */ + P5_7_LCD_SEG37 = 13, /* Digital Deep Sleep - lcd.seg[37]:0 */ + P5_7_SCB10_UART_CTS = 18, /* Digital Active - scb[10].uart_cts:0 */ + P5_7_SCB3_SPI_SELECT3 = 20, /* Digital Active - scb[3].spi_select3:0 */ + + /* P6.2 */ + P6_2_GPIO = 0, /* GPIO controls 'out' */ + P6_2_AMUXA = 4, /* Analog mux bus A */ + P6_2_AMUXB = 5, /* Analog mux bus B */ + P6_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P6_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P6_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:1 */ + P6_2_TCPWM1_LINE9 = 9, /* Digital Active - tcpwm[1].line[9]:0 */ + P6_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:40 */ + P6_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:40 */ + P6_2_LCD_COM40 = 12, /* Digital Deep Sleep - lcd.com[40]:0 */ + P6_2_LCD_SEG40 = 13, /* Digital Deep Sleep - lcd.seg[40]:0 */ + P6_2_SCB3_UART_RTS = 18, /* Digital Active - scb[3].uart_rts:0 */ + P6_2_SCB3_SPI_CLK = 20, /* Digital Active - scb[3].spi_clk:0 */ + P6_2_SCB8_SPI_CLK = 30, /* Digital Deep Sleep - scb[8].spi_clk:0 */ + + /* P6.3 */ + P6_3_GPIO = 0, /* GPIO controls 'out' */ + P6_3_AMUXA = 4, /* Analog mux bus A */ + P6_3_AMUXB = 5, /* Analog mux bus B */ + P6_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P6_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P6_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:1 */ + P6_3_TCPWM1_LINE_COMPL9 = 9, /* Digital Active - tcpwm[1].line_compl[9]:0 */ + P6_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:41 */ + P6_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:41 */ + P6_3_LCD_COM41 = 12, /* Digital Deep Sleep - lcd.com[41]:0 */ + P6_3_LCD_SEG41 = 13, /* Digital Deep Sleep - lcd.seg[41]:0 */ + P6_3_SCB3_UART_CTS = 18, /* Digital Active - scb[3].uart_cts:0 */ + P6_3_SCB3_SPI_SELECT0 = 20, /* Digital Active - scb[3].spi_select0:0 */ + P6_3_SCB8_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[8].spi_select0:0 */ + + /* P6.4 */ + P6_4_GPIO = 0, /* GPIO controls 'out' */ + P6_4_AMUXA = 4, /* Analog mux bus A */ + P6_4_AMUXB = 5, /* Analog mux bus B */ + P6_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P6_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P6_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:1 */ + P6_4_TCPWM1_LINE10 = 9, /* Digital Active - tcpwm[1].line[10]:0 */ + P6_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:42 */ + P6_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:42 */ + P6_4_LCD_COM42 = 12, /* Digital Deep Sleep - lcd.com[42]:0 */ + P6_4_LCD_SEG42 = 13, /* Digital Deep Sleep - lcd.seg[42]:0 */ + P6_4_SCB8_I2C_SCL = 14, /* Digital Deep Sleep - scb[8].i2c_scl:1 */ + P6_4_SCB6_UART_RX = 18, /* Digital Active - scb[6].uart_rx:2 */ + P6_4_SCB6_I2C_SCL = 19, /* Digital Active - scb[6].i2c_scl:2 */ + P6_4_SCB6_SPI_MOSI = 20, /* Digital Active - scb[6].spi_mosi:2 */ + P6_4_PERI_TR_IO_INPUT12 = 24, /* Digital Active - peri.tr_io_input[12]:0 */ + P6_4_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:1 */ + P6_4_CPUSS_SWJ_SWO_TDO = 29, /* Digital Deep Sleep - cpuss.swj_swo_tdo */ + P6_4_SCB8_SPI_MOSI = 30, /* Digital Deep Sleep - scb[8].spi_mosi:1 */ + P6_4_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:0 */ + + /* P6.5 */ + P6_5_GPIO = 0, /* GPIO controls 'out' */ + P6_5_AMUXA = 4, /* Analog mux bus A */ + P6_5_AMUXB = 5, /* Analog mux bus B */ + P6_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P6_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P6_5_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:1 */ + P6_5_TCPWM1_LINE_COMPL10 = 9, /* Digital Active - tcpwm[1].line_compl[10]:0 */ + P6_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:43 */ + P6_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:43 */ + P6_5_LCD_COM43 = 12, /* Digital Deep Sleep - lcd.com[43]:0 */ + P6_5_LCD_SEG43 = 13, /* Digital Deep Sleep - lcd.seg[43]:0 */ + P6_5_SCB8_I2C_SDA = 14, /* Digital Deep Sleep - scb[8].i2c_sda:1 */ + P6_5_SCB6_UART_TX = 18, /* Digital Active - scb[6].uart_tx:2 */ + P6_5_SCB6_I2C_SDA = 19, /* Digital Active - scb[6].i2c_sda:2 */ + P6_5_SCB6_SPI_MISO = 20, /* Digital Active - scb[6].spi_miso:2 */ + P6_5_PERI_TR_IO_INPUT13 = 24, /* Digital Active - peri.tr_io_input[13]:0 */ + P6_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:1 */ + P6_5_CPUSS_SWJ_SWDOE_TDI = 29, /* Digital Deep Sleep - cpuss.swj_swdoe_tdi */ + P6_5_SCB8_SPI_MISO = 30, /* Digital Deep Sleep - scb[8].spi_miso:1 */ + P6_5_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:0 */ + + /* P6.6 */ + P6_6_GPIO = 0, /* GPIO controls 'out' */ + P6_6_AMUXA = 4, /* Analog mux bus A */ + P6_6_AMUXB = 5, /* Analog mux bus B */ + P6_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P6_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P6_6_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:1 */ + P6_6_TCPWM1_LINE11 = 9, /* Digital Active - tcpwm[1].line[11]:0 */ + P6_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:44 */ + P6_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:44 */ + P6_6_LCD_COM44 = 12, /* Digital Deep Sleep - lcd.com[44]:0 */ + P6_6_LCD_SEG44 = 13, /* Digital Deep Sleep - lcd.seg[44]:0 */ + P6_6_SCB6_UART_RTS = 18, /* Digital Active - scb[6].uart_rts:2 */ + P6_6_SCB6_SPI_CLK = 20, /* Digital Active - scb[6].spi_clk:2 */ + P6_6_CPUSS_SWJ_SWDIO_TMS = 29, /* Digital Deep Sleep - cpuss.swj_swdio_tms */ + P6_6_SCB8_SPI_CLK = 30, /* Digital Deep Sleep - scb[8].spi_clk:1 */ + + /* P6.7 */ + P6_7_GPIO = 0, /* GPIO controls 'out' */ + P6_7_AMUXA = 4, /* Analog mux bus A */ + P6_7_AMUXB = 5, /* Analog mux bus B */ + P6_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P6_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P6_7_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:1 */ + P6_7_TCPWM1_LINE_COMPL11 = 9, /* Digital Active - tcpwm[1].line_compl[11]:0 */ + P6_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:45 */ + P6_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:45 */ + P6_7_LCD_COM45 = 12, /* Digital Deep Sleep - lcd.com[45]:0 */ + P6_7_LCD_SEG45 = 13, /* Digital Deep Sleep - lcd.seg[45]:0 */ + P6_7_SCB6_UART_CTS = 18, /* Digital Active - scb[6].uart_cts:2 */ + P6_7_SCB6_SPI_SELECT0 = 20, /* Digital Active - scb[6].spi_select0:2 */ + P6_7_CPUSS_SWJ_SWCLK_TCLK = 29, /* Digital Deep Sleep - cpuss.swj_swclk_tclk */ + P6_7_SCB8_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[8].spi_select0:1 */ + + /* P7.0 */ + P7_0_GPIO = 0, /* GPIO controls 'out' */ + P7_0_AMUXA = 4, /* Analog mux bus A */ + P7_0_AMUXB = 5, /* Analog mux bus B */ + P7_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P7_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:1 */ + P7_0_TCPWM1_LINE12 = 9, /* Digital Active - tcpwm[1].line[12]:0 */ + P7_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:46 */ + P7_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:46 */ + P7_0_LCD_COM46 = 12, /* Digital Deep Sleep - lcd.com[46]:0 */ + P7_0_LCD_SEG46 = 13, /* Digital Deep Sleep - lcd.seg[46]:0 */ + P7_0_SCB4_UART_RX = 18, /* Digital Active - scb[4].uart_rx:1 */ + P7_0_SCB4_I2C_SCL = 19, /* Digital Active - scb[4].i2c_scl:1 */ + P7_0_SCB4_SPI_MOSI = 20, /* Digital Active - scb[4].spi_mosi:1 */ + P7_0_PERI_TR_IO_INPUT14 = 24, /* Digital Active - peri.tr_io_input[14]:0 */ + P7_0_CPUSS_TRACE_CLOCK = 26, /* Digital Active - cpuss.trace_clock */ + + /* P7.1 */ + P7_1_GPIO = 0, /* GPIO controls 'out' */ + P7_1_AMUXA = 4, /* Analog mux bus A */ + P7_1_AMUXB = 5, /* Analog mux bus B */ + P7_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P7_1_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:1 */ + P7_1_TCPWM1_LINE_COMPL12 = 9, /* Digital Active - tcpwm[1].line_compl[12]:0 */ + P7_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:47 */ + P7_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:47 */ + P7_1_LCD_COM47 = 12, /* Digital Deep Sleep - lcd.com[47]:0 */ + P7_1_LCD_SEG47 = 13, /* Digital Deep Sleep - lcd.seg[47]:0 */ + P7_1_SCB4_UART_TX = 18, /* Digital Active - scb[4].uart_tx:1 */ + P7_1_SCB4_I2C_SDA = 19, /* Digital Active - scb[4].i2c_sda:1 */ + P7_1_SCB4_SPI_MISO = 20, /* Digital Active - scb[4].spi_miso:1 */ + P7_1_PERI_TR_IO_INPUT15 = 24, /* Digital Active - peri.tr_io_input[15]:0 */ + + /* P7.2 */ + P7_2_GPIO = 0, /* GPIO controls 'out' */ + P7_2_AMUXA = 4, /* Analog mux bus A */ + P7_2_AMUXB = 5, /* Analog mux bus B */ + P7_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P7_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:1 */ + P7_2_TCPWM1_LINE13 = 9, /* Digital Active - tcpwm[1].line[13]:0 */ + P7_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:48 */ + P7_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:48 */ + P7_2_LCD_COM48 = 12, /* Digital Deep Sleep - lcd.com[48]:0 */ + P7_2_LCD_SEG48 = 13, /* Digital Deep Sleep - lcd.seg[48]:0 */ + P7_2_SCB4_UART_RTS = 18, /* Digital Active - scb[4].uart_rts:1 */ + P7_2_SCB4_SPI_CLK = 20, /* Digital Active - scb[4].spi_clk:1 */ + + /* P7.3 */ + P7_3_GPIO = 0, /* GPIO controls 'out' */ + P7_3_AMUXA = 4, /* Analog mux bus A */ + P7_3_AMUXB = 5, /* Analog mux bus B */ + P7_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P7_3_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:1 */ + P7_3_TCPWM1_LINE_COMPL13 = 9, /* Digital Active - tcpwm[1].line_compl[13]:0 */ + P7_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:49 */ + P7_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:49 */ + P7_3_LCD_COM49 = 12, /* Digital Deep Sleep - lcd.com[49]:0 */ + P7_3_LCD_SEG49 = 13, /* Digital Deep Sleep - lcd.seg[49]:0 */ + P7_3_SCB4_UART_CTS = 18, /* Digital Active - scb[4].uart_cts:1 */ + P7_3_SCB4_SPI_SELECT0 = 20, /* Digital Active - scb[4].spi_select0:1 */ + + /* P7.7 */ + P7_7_GPIO = 0, /* GPIO controls 'out' */ + P7_7_AMUXA = 4, /* Analog mux bus A */ + P7_7_AMUXB = 5, /* Analog mux bus B */ + P7_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P7_7_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:1 */ + P7_7_TCPWM1_LINE_COMPL15 = 9, /* Digital Active - tcpwm[1].line_compl[15]:0 */ + P7_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:53 */ + P7_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:53 */ + P7_7_LCD_COM53 = 12, /* Digital Deep Sleep - lcd.com[53]:0 */ + P7_7_LCD_SEG53 = 13, /* Digital Deep Sleep - lcd.seg[53]:0 */ + P7_7_SCB3_SPI_SELECT1 = 20, /* Digital Active - scb[3].spi_select1:0 */ + P7_7_CPUSS_CLK_FM_PUMP = 21, /* Digital Active - cpuss.clk_fm_pump */ + P7_7_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:2 */ + + /* P8.0 */ + P8_0_GPIO = 0, /* GPIO controls 'out' */ + P8_0_AMUXA = 4, /* Analog mux bus A */ + P8_0_AMUXB = 5, /* Analog mux bus B */ + P8_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P8_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P8_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:2 */ + P8_0_TCPWM1_LINE16 = 9, /* Digital Active - tcpwm[1].line[16]:0 */ + P8_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:54 */ + P8_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:54 */ + P8_0_LCD_COM54 = 12, /* Digital Deep Sleep - lcd.com[54]:0 */ + P8_0_LCD_SEG54 = 13, /* Digital Deep Sleep - lcd.seg[54]:0 */ + P8_0_SCB4_UART_RX = 18, /* Digital Active - scb[4].uart_rx:0 */ + P8_0_SCB4_I2C_SCL = 19, /* Digital Active - scb[4].i2c_scl:0 */ + P8_0_SCB4_SPI_MOSI = 20, /* Digital Active - scb[4].spi_mosi:0 */ + P8_0_PERI_TR_IO_INPUT16 = 24, /* Digital Active - peri.tr_io_input[16]:0 */ + + /* P8.1 */ + P8_1_GPIO = 0, /* GPIO controls 'out' */ + P8_1_AMUXA = 4, /* Analog mux bus A */ + P8_1_AMUXB = 5, /* Analog mux bus B */ + P8_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P8_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P8_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:2 */ + P8_1_TCPWM1_LINE_COMPL16 = 9, /* Digital Active - tcpwm[1].line_compl[16]:0 */ + P8_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:55 */ + P8_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:55 */ + P8_1_LCD_COM55 = 12, /* Digital Deep Sleep - lcd.com[55]:0 */ + P8_1_LCD_SEG55 = 13, /* Digital Deep Sleep - lcd.seg[55]:0 */ + P8_1_SCB4_UART_TX = 18, /* Digital Active - scb[4].uart_tx:0 */ + P8_1_SCB4_I2C_SDA = 19, /* Digital Active - scb[4].i2c_sda:0 */ + P8_1_SCB4_SPI_MISO = 20, /* Digital Active - scb[4].spi_miso:0 */ + P8_1_PERI_TR_IO_INPUT17 = 24, /* Digital Active - peri.tr_io_input[17]:0 */ + + /* P9.0 */ + P9_0_GPIO = 0, /* GPIO controls 'out' */ + P9_0_AMUXA = 4, /* Analog mux bus A */ + P9_0_AMUXB = 5, /* Analog mux bus B */ + P9_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P9_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P9_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:2 */ + P9_0_TCPWM1_LINE20 = 9, /* Digital Active - tcpwm[1].line[20]:0 */ + P9_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:62 */ + P9_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:62 */ + P9_0_LCD_COM0 = 12, /* Digital Deep Sleep - lcd.com[0]:1 */ + P9_0_LCD_SEG0 = 13, /* Digital Deep Sleep - lcd.seg[0]:1 */ + P9_0_SCB2_UART_RX = 18, /* Digital Active - scb[2].uart_rx:0 */ + P9_0_SCB2_I2C_SCL = 19, /* Digital Active - scb[2].i2c_scl:0 */ + P9_0_SCB2_SPI_MOSI = 20, /* Digital Active - scb[2].spi_mosi:0 */ + P9_0_AUDIOSS0_CLK_I2S_IF = 22, /* Digital Active - audioss[0].clk_i2s_if:1 */ + P9_0_PERI_TR_IO_INPUT18 = 24, /* Digital Active - peri.tr_io_input[18]:0 */ + P9_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:0 */ + + /* P9.1 */ + P9_1_GPIO = 0, /* GPIO controls 'out' */ + P9_1_AMUXA = 4, /* Analog mux bus A */ + P9_1_AMUXB = 5, /* Analog mux bus B */ + P9_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P9_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P9_1_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:2 */ + P9_1_TCPWM1_LINE_COMPL20 = 9, /* Digital Active - tcpwm[1].line_compl[20]:0 */ + P9_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:63 */ + P9_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:63 */ + P9_1_LCD_COM1 = 12, /* Digital Deep Sleep - lcd.com[1]:1 */ + P9_1_LCD_SEG1 = 13, /* Digital Deep Sleep - lcd.seg[1]:1 */ + P9_1_SCB2_UART_TX = 18, /* Digital Active - scb[2].uart_tx:0 */ + P9_1_SCB2_I2C_SDA = 19, /* Digital Active - scb[2].i2c_sda:0 */ + P9_1_SCB2_SPI_MISO = 20, /* Digital Active - scb[2].spi_miso:0 */ + P9_1_AUDIOSS0_TX_SCK = 22, /* Digital Active - audioss[0].tx_sck:1 */ + P9_1_PERI_TR_IO_INPUT19 = 24, /* Digital Active - peri.tr_io_input[19]:0 */ + P9_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:0 */ + P9_1_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:1 */ + + /* P9.2 */ + P9_2_GPIO = 0, /* GPIO controls 'out' */ + P9_2_AMUXA = 4, /* Analog mux bus A */ + P9_2_AMUXB = 5, /* Analog mux bus B */ + P9_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P9_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P9_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:2 */ + P9_2_TCPWM1_LINE21 = 9, /* Digital Active - tcpwm[1].line[21]:0 */ + P9_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:64 */ + P9_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:64 */ + P9_2_LCD_COM2 = 12, /* Digital Deep Sleep - lcd.com[2]:1 */ + P9_2_LCD_SEG2 = 13, /* Digital Deep Sleep - lcd.seg[2]:1 */ + P9_2_SCB2_UART_RTS = 18, /* Digital Active - scb[2].uart_rts:0 */ + P9_2_SCB2_SPI_CLK = 20, /* Digital Active - scb[2].spi_clk:0 */ + P9_2_AUDIOSS0_TX_WS = 22, /* Digital Active - audioss[0].tx_ws:1 */ + P9_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:0 */ + + /* P9.3 */ + P9_3_GPIO = 0, /* GPIO controls 'out' */ + P9_3_AMUXA = 4, /* Analog mux bus A */ + P9_3_AMUXB = 5, /* Analog mux bus B */ + P9_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P9_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P9_3_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:2 */ + P9_3_TCPWM1_LINE_COMPL21 = 9, /* Digital Active - tcpwm[1].line_compl[21]:0 */ + P9_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:65 */ + P9_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:65 */ + P9_3_LCD_COM3 = 12, /* Digital Deep Sleep - lcd.com[3]:1 */ + P9_3_LCD_SEG3 = 13, /* Digital Deep Sleep - lcd.seg[3]:1 */ + P9_3_SCB2_UART_CTS = 18, /* Digital Active - scb[2].uart_cts:0 */ + P9_3_SCB2_SPI_SELECT0 = 20, /* Digital Active - scb[2].spi_select0:0 */ + P9_3_AUDIOSS0_TX_SDO = 22, /* Digital Active - audioss[0].tx_sdo:1 */ + P9_3_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:0 */ + P9_3_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:1 */ + + /* P10.0 */ + P10_0_GPIO = 0, /* GPIO controls 'out' */ + P10_0_AMUXA = 4, /* Analog mux bus A */ + P10_0_AMUXB = 5, /* Analog mux bus B */ + P10_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P10_0_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:2 */ + P10_0_TCPWM1_LINE22 = 9, /* Digital Active - tcpwm[1].line[22]:0 */ + P10_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:70 */ + P10_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:70 */ + P10_0_LCD_COM8 = 12, /* Digital Deep Sleep - lcd.com[8]:1 */ + P10_0_LCD_SEG8 = 13, /* Digital Deep Sleep - lcd.seg[8]:1 */ + P10_0_SCB1_UART_RX = 18, /* Digital Active - scb[1].uart_rx:1 */ + P10_0_SCB1_I2C_SCL = 19, /* Digital Active - scb[1].i2c_scl:1 */ + P10_0_SCB1_SPI_MOSI = 20, /* Digital Active - scb[1].spi_mosi:1 */ + P10_0_PERI_TR_IO_INPUT20 = 24, /* Digital Active - peri.tr_io_input[20]:0 */ + P10_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:1 */ + + /* P10.1 */ + P10_1_GPIO = 0, /* GPIO controls 'out' */ + P10_1_AMUXA = 4, /* Analog mux bus A */ + P10_1_AMUXB = 5, /* Analog mux bus B */ + P10_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P10_1_TCPWM0_LINE_COMPL6 = 8, /* Digital Active - tcpwm[0].line_compl[6]:2 */ + P10_1_TCPWM1_LINE_COMPL22 = 9, /* Digital Active - tcpwm[1].line_compl[22]:0 */ + P10_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:71 */ + P10_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:71 */ + P10_1_LCD_COM9 = 12, /* Digital Deep Sleep - lcd.com[9]:1 */ + P10_1_LCD_SEG9 = 13, /* Digital Deep Sleep - lcd.seg[9]:1 */ + P10_1_SCB1_UART_TX = 18, /* Digital Active - scb[1].uart_tx:1 */ + P10_1_SCB1_I2C_SDA = 19, /* Digital Active - scb[1].i2c_sda:1 */ + P10_1_SCB1_SPI_MISO = 20, /* Digital Active - scb[1].spi_miso:1 */ + P10_1_PERI_TR_IO_INPUT21 = 24, /* Digital Active - peri.tr_io_input[21]:0 */ + P10_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:1 */ + + /* P10.2 */ + P10_2_GPIO = 0, /* GPIO controls 'out' */ + P10_2_AMUXA = 4, /* Analog mux bus A */ + P10_2_AMUXB = 5, /* Analog mux bus B */ + P10_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P10_2_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:2 */ + P10_2_TCPWM1_LINE23 = 9, /* Digital Active - tcpwm[1].line[23]:0 */ + P10_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:72 */ + P10_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:72 */ + P10_2_LCD_COM10 = 12, /* Digital Deep Sleep - lcd.com[10]:1 */ + P10_2_LCD_SEG10 = 13, /* Digital Deep Sleep - lcd.seg[10]:1 */ + P10_2_SCB1_UART_RTS = 18, /* Digital Active - scb[1].uart_rts:1 */ + P10_2_SCB1_SPI_CLK = 20, /* Digital Active - scb[1].spi_clk:1 */ + P10_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:1 */ + + /* P10.3 */ + P10_3_GPIO = 0, /* GPIO controls 'out' */ + P10_3_AMUXA = 4, /* Analog mux bus A */ + P10_3_AMUXB = 5, /* Analog mux bus B */ + P10_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P10_3_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:2 */ + P10_3_TCPWM1_LINE_COMPL23 = 9, /* Digital Active - tcpwm[1].line_compl[23]:0 */ + P10_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:73 */ + P10_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:73 */ + P10_3_LCD_COM11 = 12, /* Digital Deep Sleep - lcd.com[11]:1 */ + P10_3_LCD_SEG11 = 13, /* Digital Deep Sleep - lcd.seg[11]:1 */ + P10_3_SCB1_UART_CTS = 18, /* Digital Active - scb[1].uart_cts:1 */ + P10_3_SCB1_SPI_SELECT0 = 20, /* Digital Active - scb[1].spi_select0:1 */ + P10_3_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:1 */ + + /* P10.4 */ + P10_4_GPIO = 0, /* GPIO controls 'out' */ + P10_4_AMUXA = 4, /* Analog mux bus A */ + P10_4_AMUXB = 5, /* Analog mux bus B */ + P10_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P10_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:3 */ + P10_4_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:1 */ + P10_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:74 */ + P10_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:74 */ + P10_4_LCD_COM12 = 12, /* Digital Deep Sleep - lcd.com[12]:1 */ + P10_4_LCD_SEG12 = 13, /* Digital Deep Sleep - lcd.seg[12]:1 */ + P10_4_SCB1_SPI_SELECT1 = 20, /* Digital Active - scb[1].spi_select1:1 */ + P10_4_AUDIOSS0_PDM_CLK = 21, /* Digital Active - audioss[0].pdm_clk:0 */ + + /* P10.5 */ + P10_5_GPIO = 0, /* GPIO controls 'out' */ + P10_5_AMUXA = 4, /* Analog mux bus A */ + P10_5_AMUXB = 5, /* Analog mux bus B */ + P10_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P10_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:3 */ + P10_5_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:1 */ + P10_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:75 */ + P10_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:75 */ + P10_5_LCD_COM13 = 12, /* Digital Deep Sleep - lcd.com[13]:1 */ + P10_5_LCD_SEG13 = 13, /* Digital Deep Sleep - lcd.seg[13]:1 */ + P10_5_SCB1_SPI_SELECT2 = 20, /* Digital Active - scb[1].spi_select2:1 */ + P10_5_AUDIOSS0_PDM_DATA = 21, /* Digital Active - audioss[0].pdm_data:0 */ + + /* P11.0 */ + P11_0_GPIO = 0, /* GPIO controls 'out' */ + P11_0_AMUXA = 4, /* Analog mux bus A */ + P11_0_AMUXB = 5, /* Analog mux bus B */ + P11_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P11_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P11_0_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:3 */ + P11_0_TCPWM1_LINE1 = 9, /* Digital Active - tcpwm[1].line[1]:1 */ + P11_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:78 */ + P11_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:78 */ + P11_0_LCD_COM16 = 12, /* Digital Deep Sleep - lcd.com[16]:1 */ + P11_0_LCD_SEG16 = 13, /* Digital Deep Sleep - lcd.seg[16]:1 */ + P11_0_SMIF_SPI_SELECT2 = 17, /* Digital Active - smif.spi_select2 */ + P11_0_SCB5_UART_RX = 18, /* Digital Active - scb[5].uart_rx:1 */ + P11_0_SCB5_I2C_SCL = 19, /* Digital Active - scb[5].i2c_scl:1 */ + P11_0_SCB5_SPI_MOSI = 20, /* Digital Active - scb[5].spi_mosi:1 */ + P11_0_AUDIOSS1_CLK_I2S_IF = 22, /* Digital Active - audioss[1].clk_i2s_if:1 */ + P11_0_PERI_TR_IO_INPUT22 = 24, /* Digital Active - peri.tr_io_input[22]:0 */ + + /* P11.1 */ + P11_1_GPIO = 0, /* GPIO controls 'out' */ + P11_1_AMUXA = 4, /* Analog mux bus A */ + P11_1_AMUXB = 5, /* Analog mux bus B */ + P11_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P11_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P11_1_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:3 */ + P11_1_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:1 */ + P11_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:79 */ + P11_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:79 */ + P11_1_LCD_COM17 = 12, /* Digital Deep Sleep - lcd.com[17]:1 */ + P11_1_LCD_SEG17 = 13, /* Digital Deep Sleep - lcd.seg[17]:1 */ + P11_1_SMIF_SPI_SELECT1 = 17, /* Digital Active - smif.spi_select1 */ + P11_1_SCB5_UART_TX = 18, /* Digital Active - scb[5].uart_tx:1 */ + P11_1_SCB5_I2C_SDA = 19, /* Digital Active - scb[5].i2c_sda:1 */ + P11_1_SCB5_SPI_MISO = 20, /* Digital Active - scb[5].spi_miso:1 */ + P11_1_AUDIOSS1_TX_SCK = 22, /* Digital Active - audioss[1].tx_sck:1 */ + P11_1_PERI_TR_IO_INPUT23 = 24, /* Digital Active - peri.tr_io_input[23]:0 */ + + /* P11.2 */ + P11_2_GPIO = 0, /* GPIO controls 'out' */ + P11_2_AMUXA = 4, /* Analog mux bus A */ + P11_2_AMUXB = 5, /* Analog mux bus B */ + P11_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P11_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P11_2_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:3 */ + P11_2_TCPWM1_LINE2 = 9, /* Digital Active - tcpwm[1].line[2]:1 */ + P11_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:80 */ + P11_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:80 */ + P11_2_LCD_COM18 = 12, /* Digital Deep Sleep - lcd.com[18]:1 */ + P11_2_LCD_SEG18 = 13, /* Digital Deep Sleep - lcd.seg[18]:1 */ + P11_2_SMIF_SPI_SELECT0 = 17, /* Digital Active - smif.spi_select0 */ + P11_2_SCB5_UART_RTS = 18, /* Digital Active - scb[5].uart_rts:1 */ + P11_2_SCB5_SPI_CLK = 20, /* Digital Active - scb[5].spi_clk:1 */ + P11_2_AUDIOSS1_TX_WS = 22, /* Digital Active - audioss[1].tx_ws:1 */ + + /* P11.3 */ + P11_3_GPIO = 0, /* GPIO controls 'out' */ + P11_3_AMUXA = 4, /* Analog mux bus A */ + P11_3_AMUXB = 5, /* Analog mux bus B */ + P11_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P11_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P11_3_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:3 */ + P11_3_TCPWM1_LINE_COMPL2 = 9, /* Digital Active - tcpwm[1].line_compl[2]:1 */ + P11_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:81 */ + P11_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:81 */ + P11_3_LCD_COM19 = 12, /* Digital Deep Sleep - lcd.com[19]:1 */ + P11_3_LCD_SEG19 = 13, /* Digital Deep Sleep - lcd.seg[19]:1 */ + P11_3_SMIF_SPI_DATA3 = 17, /* Digital Active - smif.spi_data3 */ + P11_3_SCB5_UART_CTS = 18, /* Digital Active - scb[5].uart_cts:1 */ + P11_3_SCB5_SPI_SELECT0 = 20, /* Digital Active - scb[5].spi_select0:1 */ + P11_3_AUDIOSS1_TX_SDO = 22, /* Digital Active - audioss[1].tx_sdo:1 */ + P11_3_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:0 */ + + /* P11.4 */ + P11_4_GPIO = 0, /* GPIO controls 'out' */ + P11_4_AMUXA = 4, /* Analog mux bus A */ + P11_4_AMUXB = 5, /* Analog mux bus B */ + P11_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P11_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P11_4_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:3 */ + P11_4_TCPWM1_LINE3 = 9, /* Digital Active - tcpwm[1].line[3]:1 */ + P11_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:82 */ + P11_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:82 */ + P11_4_LCD_COM20 = 12, /* Digital Deep Sleep - lcd.com[20]:1 */ + P11_4_LCD_SEG20 = 13, /* Digital Deep Sleep - lcd.seg[20]:1 */ + P11_4_SMIF_SPI_DATA2 = 17, /* Digital Active - smif.spi_data2 */ + P11_4_SCB5_SPI_SELECT1 = 20, /* Digital Active - scb[5].spi_select1:1 */ + P11_4_AUDIOSS1_RX_SCK = 22, /* Digital Active - audioss[1].rx_sck:1 */ + P11_4_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:0 */ + + /* P11.5 */ + P11_5_GPIO = 0, /* GPIO controls 'out' */ + P11_5_AMUXA = 4, /* Analog mux bus A */ + P11_5_AMUXB = 5, /* Analog mux bus B */ + P11_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P11_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P11_5_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:3 */ + P11_5_TCPWM1_LINE_COMPL3 = 9, /* Digital Active - tcpwm[1].line_compl[3]:1 */ + P11_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:83 */ + P11_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:83 */ + P11_5_LCD_COM21 = 12, /* Digital Deep Sleep - lcd.com[21]:1 */ + P11_5_LCD_SEG21 = 13, /* Digital Deep Sleep - lcd.seg[21]:1 */ + P11_5_SMIF_SPI_DATA1 = 17, /* Digital Active - smif.spi_data1 */ + P11_5_SCB5_SPI_SELECT2 = 20, /* Digital Active - scb[5].spi_select2:1 */ + P11_5_AUDIOSS1_RX_WS = 22, /* Digital Active - audioss[1].rx_ws:1 */ + + /* P11.6 */ + P11_6_GPIO = 0, /* GPIO controls 'out' */ + P11_6_AMUXA = 4, /* Analog mux bus A */ + P11_6_AMUXB = 5, /* Analog mux bus B */ + P11_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P11_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P11_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:84 */ + P11_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:84 */ + P11_6_LCD_COM22 = 12, /* Digital Deep Sleep - lcd.com[22]:1 */ + P11_6_LCD_SEG22 = 13, /* Digital Deep Sleep - lcd.seg[22]:1 */ + P11_6_SMIF_SPI_DATA0 = 17, /* Digital Active - smif.spi_data0 */ + P11_6_SCB5_SPI_SELECT3 = 20, /* Digital Active - scb[5].spi_select3:1 */ + P11_6_AUDIOSS1_RX_SDI = 22, /* Digital Active - audioss[1].rx_sdi:1 */ + + /* P11.7 */ + P11_7_GPIO = 0, /* GPIO controls 'out' */ + P11_7_AMUXA = 4, /* Analog mux bus A */ + P11_7_AMUXB = 5, /* Analog mux bus B */ + P11_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P11_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P11_7_SMIF_SPI_CLK = 17, /* Digital Active - smif.spi_clk */ + + /* P12.6 */ + P12_6_GPIO = 0, /* GPIO controls 'out' */ + P12_6_AMUXA = 4, /* Analog mux bus A */ + P12_6_AMUXB = 5, /* Analog mux bus B */ + P12_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P12_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P12_6_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:3 */ + P12_6_TCPWM1_LINE7 = 9, /* Digital Active - tcpwm[1].line[7]:1 */ + P12_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:91 */ + P12_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:91 */ + P12_6_LCD_COM29 = 12, /* Digital Deep Sleep - lcd.com[29]:1 */ + P12_6_LCD_SEG29 = 13, /* Digital Deep Sleep - lcd.seg[29]:1 */ + P12_6_SCB6_SPI_SELECT3 = 20, /* Digital Active - scb[6].spi_select3:0 */ + P12_6_SDHC1_CARD_IF_PWR_EN = 26, /* Digital Active - sdhc[1].card_if_pwr_en */ + + /* P12.7 */ + P12_7_GPIO = 0, /* GPIO controls 'out' */ + P12_7_AMUXA = 4, /* Analog mux bus A */ + P12_7_AMUXB = 5, /* Analog mux bus B */ + P12_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P12_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P12_7_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:3 */ + P12_7_TCPWM1_LINE_COMPL7 = 9, /* Digital Active - tcpwm[1].line_compl[7]:1 */ + P12_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:92 */ + P12_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:92 */ + P12_7_LCD_COM30 = 12, /* Digital Deep Sleep - lcd.com[30]:1 */ + P12_7_LCD_SEG30 = 13, /* Digital Deep Sleep - lcd.seg[30]:1 */ + P12_7_SDHC1_IO_VOLT_SEL = 26 /* Digital Active - sdhc[1].io_volt_sel */ +} en_hsiom_sel_t; + +#endif /* _GPIO_PSOC6_02_68_QFN_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_03_100_tqfp.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_03_100_tqfp.h new file mode 100644 index 0000000000..e4e4fe4ad6 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_03_100_tqfp.h @@ -0,0 +1,1437 @@ +/***************************************************************************//** +* \file gpio_psoc6_03_100_tqfp.h +* +* \brief +* PSoC6_03 device GPIO header for 100-TQFP package +* +* \note +* Generator version: 1.5.0.1274 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _GPIO_PSOC6_03_100_TQFP_H_ +#define _GPIO_PSOC6_03_100_TQFP_H_ + +/* Package type */ +enum +{ + CY_GPIO_PACKAGE_QFN, + CY_GPIO_PACKAGE_BGA, + CY_GPIO_PACKAGE_CSP, + CY_GPIO_PACKAGE_WLCSP, + CY_GPIO_PACKAGE_LQFP, + CY_GPIO_PACKAGE_TQFP, + CY_GPIO_PACKAGE_SMT, +}; + +#define CY_GPIO_PACKAGE_TYPE CY_GPIO_PACKAGE_TQFP +#define CY_GPIO_PIN_COUNT 100u + +/* AMUXBUS Segments */ +enum +{ + AMUXBUS_SRSS_AMUXBUSA_ADFT_VDDD, + AMUXBUS_SRSS_AMUXBUSB_ADFT_VDDD, + AMUXBUS_VSSA, + AMUXBUS_VDDIO_1, + AMUXBUS_CSD0, + AMUXBUS_CSD1, + AMUXBUS_SAR, + AMUXBUS_ANALOG_VDDD, +}; + +/* AMUX Splitter Controls */ +typedef enum +{ + AMUX_SPLIT_CTL_2 = 0x0002u, /* Left = AMUXBUS_CSD1; Right = AMUXBUS_CSD0 */ + AMUX_SPLIT_CTL_3 = 0x0003u /* Left = AMUXBUS_SAR; Right = AMUXBUS_CSD1 */ +} cy_en_amux_split_t; + +/* Port List */ +/* PORT 0 (GPIO) */ +#define P0_0_PORT GPIO_PRT0 +#define P0_0_PIN 0u +#define P0_0_NUM 0u +#define P0_1_PORT GPIO_PRT0 +#define P0_1_PIN 1u +#define P0_1_NUM 1u +#define P0_2_PORT GPIO_PRT0 +#define P0_2_PIN 2u +#define P0_2_NUM 2u +#define P0_3_PORT GPIO_PRT0 +#define P0_3_PIN 3u +#define P0_3_NUM 3u +#define P0_4_PORT GPIO_PRT0 +#define P0_4_PIN 4u +#define P0_4_NUM 4u +#define P0_5_PORT GPIO_PRT0 +#define P0_5_PIN 5u +#define P0_5_NUM 5u + +/* PORT 2 (GPIO) */ +#define P2_0_PORT GPIO_PRT2 +#define P2_0_PIN 0u +#define P2_0_NUM 0u +#define P2_1_PORT GPIO_PRT2 +#define P2_1_PIN 1u +#define P2_1_NUM 1u +#define P2_2_PORT GPIO_PRT2 +#define P2_2_PIN 2u +#define P2_2_NUM 2u +#define P2_3_PORT GPIO_PRT2 +#define P2_3_PIN 3u +#define P2_3_NUM 3u +#define P2_4_PORT GPIO_PRT2 +#define P2_4_PIN 4u +#define P2_4_NUM 4u +#define P2_5_PORT GPIO_PRT2 +#define P2_5_PIN 5u +#define P2_5_NUM 5u +#define P2_6_PORT GPIO_PRT2 +#define P2_6_PIN 6u +#define P2_6_NUM 6u +#define P2_7_PORT GPIO_PRT2 +#define P2_7_PIN 7u +#define P2_7_NUM 7u + +/* PORT 3 (GPIO_OVT) */ +#define P3_0_PORT GPIO_PRT3 +#define P3_0_PIN 0u +#define P3_0_NUM 0u +#define P3_0_AMUXSEGMENT AMUXBUS_VSSA +#define P3_1_PORT GPIO_PRT3 +#define P3_1_PIN 1u +#define P3_1_NUM 1u +#define P3_1_AMUXSEGMENT AMUXBUS_VSSA + +/* PORT 5 (GPIO) */ +#define P5_0_PORT GPIO_PRT5 +#define P5_0_PIN 0u +#define P5_0_NUM 0u +#define P5_1_PORT GPIO_PRT5 +#define P5_1_PIN 1u +#define P5_1_NUM 1u +#define P5_6_PORT GPIO_PRT5 +#define P5_6_PIN 6u +#define P5_6_NUM 6u +#define P5_7_PORT GPIO_PRT5 +#define P5_7_PIN 7u +#define P5_7_NUM 7u + +/* PORT 6 (GPIO) */ +#define P6_0_PORT GPIO_PRT6 +#define P6_0_PIN 0u +#define P6_0_NUM 0u +#define P6_1_PORT GPIO_PRT6 +#define P6_1_PIN 1u +#define P6_1_NUM 1u +#define P6_2_PORT GPIO_PRT6 +#define P6_2_PIN 2u +#define P6_2_NUM 2u +#define P6_3_PORT GPIO_PRT6 +#define P6_3_PIN 3u +#define P6_3_NUM 3u +#define P6_4_PORT GPIO_PRT6 +#define P6_4_PIN 4u +#define P6_4_NUM 4u +#define P6_5_PORT GPIO_PRT6 +#define P6_5_PIN 5u +#define P6_5_NUM 5u +#define P6_6_PORT GPIO_PRT6 +#define P6_6_PIN 6u +#define P6_6_NUM 6u +#define P6_7_PORT GPIO_PRT6 +#define P6_7_PIN 7u +#define P6_7_NUM 7u + +/* PORT 7 (GPIO) */ +#define P7_0_PORT GPIO_PRT7 +#define P7_0_PIN 0u +#define P7_0_NUM 0u +#define P7_0_AMUXSEGMENT AMUXBUS_CSD0 +#define P7_1_PORT GPIO_PRT7 +#define P7_1_PIN 1u +#define P7_1_NUM 1u +#define P7_1_AMUXSEGMENT AMUXBUS_CSD0 +#define P7_2_PORT GPIO_PRT7 +#define P7_2_PIN 2u +#define P7_2_NUM 2u +#define P7_2_AMUXSEGMENT AMUXBUS_CSD0 +#define P7_3_PORT GPIO_PRT7 +#define P7_3_PIN 3u +#define P7_3_NUM 3u +#define P7_3_AMUXSEGMENT AMUXBUS_CSD0 +#define P7_4_PORT GPIO_PRT7 +#define P7_4_PIN 4u +#define P7_4_NUM 4u +#define P7_4_AMUXSEGMENT AMUXBUS_CSD0 +#define P7_5_PORT GPIO_PRT7 +#define P7_5_PIN 5u +#define P7_5_NUM 5u +#define P7_5_AMUXSEGMENT AMUXBUS_CSD0 +#define P7_6_PORT GPIO_PRT7 +#define P7_6_PIN 6u +#define P7_6_NUM 6u +#define P7_6_AMUXSEGMENT AMUXBUS_CSD0 +#define P7_7_PORT GPIO_PRT7 +#define P7_7_PIN 7u +#define P7_7_NUM 7u +#define P7_7_AMUXSEGMENT AMUXBUS_CSD0 + +/* PORT 8 (GPIO) */ +#define P8_0_PORT GPIO_PRT8 +#define P8_0_PIN 0u +#define P8_0_NUM 0u +#define P8_0_AMUXSEGMENT AMUXBUS_CSD0 +#define P8_1_PORT GPIO_PRT8 +#define P8_1_PIN 1u +#define P8_1_NUM 1u +#define P8_1_AMUXSEGMENT AMUXBUS_CSD0 +#define P8_2_PORT GPIO_PRT8 +#define P8_2_PIN 2u +#define P8_2_NUM 2u +#define P8_2_AMUXSEGMENT AMUXBUS_CSD0 +#define P8_3_PORT GPIO_PRT8 +#define P8_3_PIN 3u +#define P8_3_NUM 3u +#define P8_3_AMUXSEGMENT AMUXBUS_CSD0 + +/* PORT 9 (GPIO) */ +#define P9_0_PORT GPIO_PRT9 +#define P9_0_PIN 0u +#define P9_0_NUM 0u +#define P9_0_AMUXSEGMENT AMUXBUS_SAR +#define P9_1_PORT GPIO_PRT9 +#define P9_1_PIN 1u +#define P9_1_NUM 1u +#define P9_1_AMUXSEGMENT AMUXBUS_SAR +#define P9_2_PORT GPIO_PRT9 +#define P9_2_PIN 2u +#define P9_2_NUM 2u +#define P9_2_AMUXSEGMENT AMUXBUS_SAR +#define P9_3_PORT GPIO_PRT9 +#define P9_3_PIN 3u +#define P9_3_NUM 3u +#define P9_3_AMUXSEGMENT AMUXBUS_SAR + +/* PORT 10 (GPIO) */ +#define P10_0_PORT GPIO_PRT10 +#define P10_0_PIN 0u +#define P10_0_NUM 0u +#define P10_1_PORT GPIO_PRT10 +#define P10_1_PIN 1u +#define P10_1_NUM 1u +#define P10_2_PORT GPIO_PRT10 +#define P10_2_PIN 2u +#define P10_2_NUM 2u +#define P10_3_PORT GPIO_PRT10 +#define P10_3_PIN 3u +#define P10_3_NUM 3u +#define P10_4_PORT GPIO_PRT10 +#define P10_4_PIN 4u +#define P10_4_NUM 4u +#define P10_5_PORT GPIO_PRT10 +#define P10_5_PIN 5u +#define P10_5_NUM 5u +#define P10_6_PORT GPIO_PRT10 +#define P10_6_PIN 6u +#define P10_6_NUM 6u +#define P10_7_PORT GPIO_PRT10 +#define P10_7_PIN 7u +#define P10_7_NUM 7u + +/* PORT 11 (GPIO) */ +#define P11_0_PORT GPIO_PRT11 +#define P11_0_PIN 0u +#define P11_0_NUM 0u +#define P11_1_PORT GPIO_PRT11 +#define P11_1_PIN 1u +#define P11_1_NUM 1u +#define P11_2_PORT GPIO_PRT11 +#define P11_2_PIN 2u +#define P11_2_NUM 2u +#define P11_3_PORT GPIO_PRT11 +#define P11_3_PIN 3u +#define P11_3_NUM 3u +#define P11_4_PORT GPIO_PRT11 +#define P11_4_PIN 4u +#define P11_4_NUM 4u +#define P11_5_PORT GPIO_PRT11 +#define P11_5_PIN 5u +#define P11_5_NUM 5u +#define P11_6_PORT GPIO_PRT11 +#define P11_6_PIN 6u +#define P11_6_NUM 6u +#define P11_7_PORT GPIO_PRT11 +#define P11_7_PIN 7u +#define P11_7_NUM 7u + +/* PORT 12 (GPIO) */ +#define P12_0_PORT GPIO_PRT12 +#define P12_0_PIN 0u +#define P12_0_NUM 0u +#define P12_1_PORT GPIO_PRT12 +#define P12_1_PIN 1u +#define P12_1_NUM 1u +#define P12_6_PORT GPIO_PRT12 +#define P12_6_PIN 6u +#define P12_6_NUM 6u +#define P12_7_PORT GPIO_PRT12 +#define P12_7_PIN 7u +#define P12_7_NUM 7u + +/* PORT 14 (AUX) */ +#define USBDP_PORT GPIO_PRT14 +#define USBDP_PIN 0u +#define USBDP_NUM 0u +#define USBDM_PORT GPIO_PRT14 +#define USBDM_PIN 1u +#define USBDM_NUM 1u + +/* Analog Connections */ +#define CSD_CMODPADD_PORT 7u +#define CSD_CMODPADD_PIN 1u +#define CSD_CMODPADS_PORT 7u +#define CSD_CMODPADS_PIN 1u +#define CSD_CSH_TANKPADD_PORT 7u +#define CSD_CSH_TANKPADD_PIN 2u +#define CSD_CSH_TANKPADS_PORT 7u +#define CSD_CSH_TANKPADS_PIN 2u +#define CSD_CSHIELDPADS_PORT 7u +#define CSD_CSHIELDPADS_PIN 7u +#define CSD_VREF_EXT_PORT 7u +#define CSD_VREF_EXT_PIN 3u +#define IOSS_ADFT0_NET_PORT 10u +#define IOSS_ADFT0_NET_PIN 0u +#define IOSS_ADFT1_NET_PORT 10u +#define IOSS_ADFT1_NET_PIN 1u +#define LPCOMP_INN_COMP0_PORT 5u +#define LPCOMP_INN_COMP0_PIN 7u +#define LPCOMP_INN_COMP1_PORT 6u +#define LPCOMP_INN_COMP1_PIN 3u +#define LPCOMP_INP_COMP0_PORT 5u +#define LPCOMP_INP_COMP0_PIN 6u +#define LPCOMP_INP_COMP1_PORT 6u +#define LPCOMP_INP_COMP1_PIN 2u +#define PASS_AREF_EXT_VREF_PORT 9u +#define PASS_AREF_EXT_VREF_PIN 3u +#define PASS_SARMUX_PADS0_PORT 10u +#define PASS_SARMUX_PADS0_PIN 0u +#define PASS_SARMUX_PADS1_PORT 10u +#define PASS_SARMUX_PADS1_PIN 1u +#define PASS_SARMUX_PADS2_PORT 10u +#define PASS_SARMUX_PADS2_PIN 2u +#define PASS_SARMUX_PADS3_PORT 10u +#define PASS_SARMUX_PADS3_PIN 3u +#define PASS_SARMUX_PADS4_PORT 10u +#define PASS_SARMUX_PADS4_PIN 4u +#define PASS_SARMUX_PADS5_PORT 10u +#define PASS_SARMUX_PADS5_PIN 5u +#define PASS_SARMUX_PADS6_PORT 10u +#define PASS_SARMUX_PADS6_PIN 6u +#define PASS_SARMUX_PADS7_PORT 10u +#define PASS_SARMUX_PADS7_PIN 7u +#define SRSS_ADFT_PIN0_PORT 10u +#define SRSS_ADFT_PIN0_PIN 0u +#define SRSS_ADFT_PIN1_PORT 10u +#define SRSS_ADFT_PIN1_PIN 1u +#define SRSS_ECO_IN_PORT 12u +#define SRSS_ECO_IN_PIN 6u +#define SRSS_ECO_OUT_PORT 12u +#define SRSS_ECO_OUT_PIN 7u +#define SRSS_WCO_IN_PORT 0u +#define SRSS_WCO_IN_PIN 0u +#define SRSS_WCO_OUT_PORT 0u +#define SRSS_WCO_OUT_PIN 1u + +/* HSIOM Connections */ +typedef enum +{ + /* Generic HSIOM connections */ + HSIOM_SEL_GPIO = 0, /* GPIO controls 'out' */ + HSIOM_SEL_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + HSIOM_SEL_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + HSIOM_SEL_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + HSIOM_SEL_AMUXA = 4, /* Analog mux bus A */ + HSIOM_SEL_AMUXB = 5, /* Analog mux bus B */ + HSIOM_SEL_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + HSIOM_SEL_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + HSIOM_SEL_ACT_0 = 8, /* Active functionality 0 */ + HSIOM_SEL_ACT_1 = 9, /* Active functionality 1 */ + HSIOM_SEL_ACT_2 = 10, /* Active functionality 2 */ + HSIOM_SEL_ACT_3 = 11, /* Active functionality 3 */ + HSIOM_SEL_DS_0 = 12, /* DeepSleep functionality 0 */ + HSIOM_SEL_DS_1 = 13, /* DeepSleep functionality 1 */ + HSIOM_SEL_DS_2 = 14, /* DeepSleep functionality 2 */ + HSIOM_SEL_DS_3 = 15, /* DeepSleep functionality 3 */ + HSIOM_SEL_ACT_4 = 16, /* Active functionality 4 */ + HSIOM_SEL_ACT_5 = 17, /* Active functionality 5 */ + HSIOM_SEL_ACT_6 = 18, /* Active functionality 6 */ + HSIOM_SEL_ACT_7 = 19, /* Active functionality 7 */ + HSIOM_SEL_ACT_8 = 20, /* Active functionality 8 */ + HSIOM_SEL_ACT_9 = 21, /* Active functionality 9 */ + HSIOM_SEL_ACT_10 = 22, /* Active functionality 10 */ + HSIOM_SEL_ACT_11 = 23, /* Active functionality 11 */ + HSIOM_SEL_ACT_12 = 24, /* Active functionality 12 */ + HSIOM_SEL_ACT_13 = 25, /* Active functionality 13 */ + HSIOM_SEL_ACT_14 = 26, /* Active functionality 14 */ + HSIOM_SEL_ACT_15 = 27, /* Active functionality 15 */ + HSIOM_SEL_DS_4 = 28, /* DeepSleep functionality 4 */ + HSIOM_SEL_DS_5 = 29, /* DeepSleep functionality 5 */ + HSIOM_SEL_DS_6 = 30, /* DeepSleep functionality 6 */ + HSIOM_SEL_DS_7 = 31, /* DeepSleep functionality 7 */ + + /* P0.0 */ + P0_0_GPIO = 0, /* GPIO controls 'out' */ + P0_0_AMUXA = 4, /* Analog mux bus A */ + P0_0_AMUXB = 5, /* Analog mux bus B */ + P0_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P0_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P0_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:0 */ + P0_0_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:0 */ + P0_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:0 */ + P0_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:0 */ + P0_0_LCD_COM0 = 12, /* Digital Deep Sleep - lcd.com[0]:0 */ + P0_0_LCD_SEG0 = 13, /* Digital Deep Sleep - lcd.seg[0]:0 */ + P0_0_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:0 */ + P0_0_SCB0_SPI_SELECT1 = 20, /* Digital Active - scb[0].spi_select1:0 */ + P0_0_PERI_TR_IO_INPUT0 = 24, /* Digital Active - peri.tr_io_input[0]:0 */ + + /* P0.1 */ + P0_1_GPIO = 0, /* GPIO controls 'out' */ + P0_1_AMUXA = 4, /* Analog mux bus A */ + P0_1_AMUXB = 5, /* Analog mux bus B */ + P0_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P0_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P0_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:0 */ + P0_1_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:0 */ + P0_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:1 */ + P0_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:1 */ + P0_1_LCD_COM1 = 12, /* Digital Deep Sleep - lcd.com[1]:0 */ + P0_1_LCD_SEG1 = 13, /* Digital Deep Sleep - lcd.seg[1]:0 */ + P0_1_SCB0_SPI_SELECT2 = 20, /* Digital Active - scb[0].spi_select2:0 */ + P0_1_PERI_TR_IO_INPUT1 = 24, /* Digital Active - peri.tr_io_input[1]:0 */ + P0_1_CPUSS_SWJ_TRSTN = 29, /* Digital Deep Sleep - cpuss.swj_trstn */ + + /* P0.2 */ + P0_2_GPIO = 0, /* GPIO controls 'out' */ + P0_2_AMUXA = 4, /* Analog mux bus A */ + P0_2_AMUXB = 5, /* Analog mux bus B */ + P0_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P0_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P0_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:0 */ + P0_2_TCPWM1_LINE1 = 9, /* Digital Active - tcpwm[1].line[1]:0 */ + P0_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:2 */ + P0_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:2 */ + P0_2_LCD_COM2 = 12, /* Digital Deep Sleep - lcd.com[2]:0 */ + P0_2_LCD_SEG2 = 13, /* Digital Deep Sleep - lcd.seg[2]:0 */ + P0_2_SCB0_UART_RX = 18, /* Digital Active - scb[0].uart_rx:0 */ + P0_2_SCB0_I2C_SCL = 19, /* Digital Active - scb[0].i2c_scl:0 */ + P0_2_SCB0_SPI_MOSI = 20, /* Digital Active - scb[0].spi_mosi:0 */ + + /* P0.3 */ + P0_3_GPIO = 0, /* GPIO controls 'out' */ + P0_3_AMUXA = 4, /* Analog mux bus A */ + P0_3_AMUXB = 5, /* Analog mux bus B */ + P0_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P0_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P0_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:0 */ + P0_3_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:0 */ + P0_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:3 */ + P0_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:3 */ + P0_3_LCD_COM3 = 12, /* Digital Deep Sleep - lcd.com[3]:0 */ + P0_3_LCD_SEG3 = 13, /* Digital Deep Sleep - lcd.seg[3]:0 */ + P0_3_SCB0_UART_TX = 18, /* Digital Active - scb[0].uart_tx:0 */ + P0_3_SCB0_I2C_SDA = 19, /* Digital Active - scb[0].i2c_sda:0 */ + P0_3_SCB0_SPI_MISO = 20, /* Digital Active - scb[0].spi_miso:0 */ + + /* P0.4 */ + P0_4_GPIO = 0, /* GPIO controls 'out' */ + P0_4_AMUXA = 4, /* Analog mux bus A */ + P0_4_AMUXB = 5, /* Analog mux bus B */ + P0_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P0_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P0_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:0 */ + P0_4_TCPWM1_LINE2 = 9, /* Digital Active - tcpwm[1].line[2]:0 */ + P0_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:4 */ + P0_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:4 */ + P0_4_LCD_COM4 = 12, /* Digital Deep Sleep - lcd.com[4]:0 */ + P0_4_LCD_SEG4 = 13, /* Digital Deep Sleep - lcd.seg[4]:0 */ + P0_4_SCB0_UART_RTS = 18, /* Digital Active - scb[0].uart_rts:0 */ + P0_4_SCB0_SPI_CLK = 20, /* Digital Active - scb[0].spi_clk:0 */ + P0_4_PERI_TR_IO_INPUT2 = 24, /* Digital Active - peri.tr_io_input[2]:0 */ + P0_4_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:2 */ + + /* P0.5 */ + P0_5_GPIO = 0, /* GPIO controls 'out' */ + P0_5_AMUXA = 4, /* Analog mux bus A */ + P0_5_AMUXB = 5, /* Analog mux bus B */ + P0_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P0_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P0_5_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:0 */ + P0_5_TCPWM1_LINE_COMPL2 = 9, /* Digital Active - tcpwm[1].line_compl[2]:0 */ + P0_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:5 */ + P0_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:5 */ + P0_5_LCD_COM5 = 12, /* Digital Deep Sleep - lcd.com[5]:0 */ + P0_5_LCD_SEG5 = 13, /* Digital Deep Sleep - lcd.seg[5]:0 */ + P0_5_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:1 */ + P0_5_SCB0_UART_CTS = 18, /* Digital Active - scb[0].uart_cts:0 */ + P0_5_SCB0_SPI_SELECT0 = 20, /* Digital Active - scb[0].spi_select0:0 */ + P0_5_PERI_TR_IO_INPUT3 = 24, /* Digital Active - peri.tr_io_input[3]:0 */ + P0_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:2 */ + + /* USBDM */ + USBDM_GPIO = 0, /* GPIO controls 'out' */ + + /* USBDP */ + USBDP_GPIO = 0, /* GPIO controls 'out' */ + + /* P2.0 */ + P2_0_GPIO = 0, /* GPIO controls 'out' */ + P2_0_AMUXA = 4, /* Analog mux bus A */ + P2_0_AMUXB = 5, /* Analog mux bus B */ + P2_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P2_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P2_0_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:0 */ + P2_0_TCPWM1_LINE3 = 9, /* Digital Active - tcpwm[1].line[3]:0 */ + P2_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:6 */ + P2_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:6 */ + P2_0_LCD_COM6 = 12, /* Digital Deep Sleep - lcd.com[6]:0 */ + P2_0_LCD_SEG6 = 13, /* Digital Deep Sleep - lcd.seg[6]:0 */ + P2_0_SCB1_UART_RX = 18, /* Digital Active - scb[1].uart_rx:0 */ + P2_0_SCB1_I2C_SCL = 19, /* Digital Active - scb[1].i2c_scl:0 */ + P2_0_SCB1_SPI_MOSI = 20, /* Digital Active - scb[1].spi_mosi:0 */ + P2_0_PERI_TR_IO_INPUT4 = 24, /* Digital Active - peri.tr_io_input[4]:0 */ + P2_0_SDHC0_CARD_DAT_3TO00 = 26, /* Digital Active - sdhc[0].card_dat_3to0[0] */ + + /* P2.1 */ + P2_1_GPIO = 0, /* GPIO controls 'out' */ + P2_1_AMUXA = 4, /* Analog mux bus A */ + P2_1_AMUXB = 5, /* Analog mux bus B */ + P2_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P2_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P2_1_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:0 */ + P2_1_TCPWM1_LINE_COMPL3 = 9, /* Digital Active - tcpwm[1].line_compl[3]:0 */ + P2_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:7 */ + P2_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:7 */ + P2_1_LCD_COM7 = 12, /* Digital Deep Sleep - lcd.com[7]:0 */ + P2_1_LCD_SEG7 = 13, /* Digital Deep Sleep - lcd.seg[7]:0 */ + P2_1_SCB1_UART_TX = 18, /* Digital Active - scb[1].uart_tx:0 */ + P2_1_SCB1_I2C_SDA = 19, /* Digital Active - scb[1].i2c_sda:0 */ + P2_1_SCB1_SPI_MISO = 20, /* Digital Active - scb[1].spi_miso:0 */ + P2_1_PERI_TR_IO_INPUT5 = 24, /* Digital Active - peri.tr_io_input[5]:0 */ + P2_1_SDHC0_CARD_DAT_3TO01 = 26, /* Digital Active - sdhc[0].card_dat_3to0[1] */ + + /* P2.2 */ + P2_2_GPIO = 0, /* GPIO controls 'out' */ + P2_2_AMUXA = 4, /* Analog mux bus A */ + P2_2_AMUXB = 5, /* Analog mux bus B */ + P2_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P2_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P2_2_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:1 */ + P2_2_TCPWM1_LINE4 = 9, /* Digital Active - tcpwm[1].line[4]:0 */ + P2_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:8 */ + P2_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:8 */ + P2_2_LCD_COM8 = 12, /* Digital Deep Sleep - lcd.com[8]:0 */ + P2_2_LCD_SEG8 = 13, /* Digital Deep Sleep - lcd.seg[8]:0 */ + P2_2_SCB1_UART_RTS = 18, /* Digital Active - scb[1].uart_rts:0 */ + P2_2_SCB1_SPI_CLK = 20, /* Digital Active - scb[1].spi_clk:0 */ + P2_2_SDHC0_CARD_DAT_3TO02 = 26, /* Digital Active - sdhc[0].card_dat_3to0[2] */ + + /* P2.3 */ + P2_3_GPIO = 0, /* GPIO controls 'out' */ + P2_3_AMUXA = 4, /* Analog mux bus A */ + P2_3_AMUXB = 5, /* Analog mux bus B */ + P2_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P2_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P2_3_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:1 */ + P2_3_TCPWM1_LINE_COMPL4 = 9, /* Digital Active - tcpwm[1].line_compl[4]:0 */ + P2_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:9 */ + P2_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:9 */ + P2_3_LCD_COM9 = 12, /* Digital Deep Sleep - lcd.com[9]:0 */ + P2_3_LCD_SEG9 = 13, /* Digital Deep Sleep - lcd.seg[9]:0 */ + P2_3_SCB1_UART_CTS = 18, /* Digital Active - scb[1].uart_cts:0 */ + P2_3_SCB1_SPI_SELECT0 = 20, /* Digital Active - scb[1].spi_select0:0 */ + P2_3_SDHC0_CARD_DAT_3TO03 = 26, /* Digital Active - sdhc[0].card_dat_3to0[3] */ + + /* P2.4 */ + P2_4_GPIO = 0, /* GPIO controls 'out' */ + P2_4_AMUXA = 4, /* Analog mux bus A */ + P2_4_AMUXB = 5, /* Analog mux bus B */ + P2_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P2_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P2_4_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:1 */ + P2_4_TCPWM1_LINE5 = 9, /* Digital Active - tcpwm[1].line[5]:0 */ + P2_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:10 */ + P2_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:10 */ + P2_4_LCD_COM10 = 12, /* Digital Deep Sleep - lcd.com[10]:0 */ + P2_4_LCD_SEG10 = 13, /* Digital Deep Sleep - lcd.seg[10]:0 */ + P2_4_SCB1_SPI_SELECT1 = 20, /* Digital Active - scb[1].spi_select1:0 */ + P2_4_SDHC0_CARD_CMD = 26, /* Digital Active - sdhc[0].card_cmd */ + + /* P2.5 */ + P2_5_GPIO = 0, /* GPIO controls 'out' */ + P2_5_AMUXA = 4, /* Analog mux bus A */ + P2_5_AMUXB = 5, /* Analog mux bus B */ + P2_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P2_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P2_5_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:1 */ + P2_5_TCPWM1_LINE_COMPL5 = 9, /* Digital Active - tcpwm[1].line_compl[5]:0 */ + P2_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:11 */ + P2_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:11 */ + P2_5_LCD_COM11 = 12, /* Digital Deep Sleep - lcd.com[11]:0 */ + P2_5_LCD_SEG11 = 13, /* Digital Deep Sleep - lcd.seg[11]:0 */ + P2_5_SCB1_SPI_SELECT2 = 20, /* Digital Active - scb[1].spi_select2:0 */ + P2_5_SDHC0_CLK_CARD = 26, /* Digital Active - sdhc[0].clk_card */ + + /* P2.6 */ + P2_6_GPIO = 0, /* GPIO controls 'out' */ + P2_6_AMUXA = 4, /* Analog mux bus A */ + P2_6_AMUXB = 5, /* Analog mux bus B */ + P2_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P2_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P2_6_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:1 */ + P2_6_TCPWM1_LINE6 = 9, /* Digital Active - tcpwm[1].line[6]:0 */ + P2_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:12 */ + P2_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:12 */ + P2_6_LCD_COM12 = 12, /* Digital Deep Sleep - lcd.com[12]:0 */ + P2_6_LCD_SEG12 = 13, /* Digital Deep Sleep - lcd.seg[12]:0 */ + P2_6_SCB1_SPI_SELECT3 = 20, /* Digital Active - scb[1].spi_select3:0 */ + P2_6_PERI_TR_IO_INPUT8 = 24, /* Digital Active - peri.tr_io_input[8]:0 */ + P2_6_SDHC0_CARD_DETECT_N = 26, /* Digital Active - sdhc[0].card_detect_n */ + + /* P2.7 */ + P2_7_GPIO = 0, /* GPIO controls 'out' */ + P2_7_AMUXA = 4, /* Analog mux bus A */ + P2_7_AMUXB = 5, /* Analog mux bus B */ + P2_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P2_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P2_7_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:1 */ + P2_7_TCPWM1_LINE_COMPL6 = 9, /* Digital Active - tcpwm[1].line_compl[6]:0 */ + P2_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:13 */ + P2_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:13 */ + P2_7_LCD_COM13 = 12, /* Digital Deep Sleep - lcd.com[13]:0 */ + P2_7_LCD_SEG13 = 13, /* Digital Deep Sleep - lcd.seg[13]:0 */ + P2_7_PERI_TR_IO_INPUT9 = 24, /* Digital Active - peri.tr_io_input[9]:0 */ + P2_7_SDHC0_CARD_MECH_WRITE_PROT = 26, /* Digital Active - sdhc[0].card_mech_write_prot */ + + /* P3.0 */ + P3_0_GPIO = 0, /* GPIO controls 'out' */ + P3_0_AMUXA = 4, /* Analog mux bus A */ + P3_0_AMUXB = 5, /* Analog mux bus B */ + P3_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P3_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P3_0_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:1 */ + P3_0_TCPWM1_LINE7 = 9, /* Digital Active - tcpwm[1].line[7]:0 */ + P3_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:14 */ + P3_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:14 */ + P3_0_LCD_COM14 = 12, /* Digital Deep Sleep - lcd.com[14]:0 */ + P3_0_LCD_SEG14 = 13, /* Digital Deep Sleep - lcd.seg[14]:0 */ + P3_0_SCB2_UART_RX = 18, /* Digital Active - scb[2].uart_rx:1 */ + P3_0_SCB2_I2C_SCL = 19, /* Digital Active - scb[2].i2c_scl:1 */ + P3_0_SCB2_SPI_MOSI = 20, /* Digital Active - scb[2].spi_mosi:1 */ + P3_0_PERI_TR_IO_INPUT6 = 24, /* Digital Active - peri.tr_io_input[6]:0 */ + P3_0_SDHC0_IO_VOLT_SEL = 26, /* Digital Active - sdhc[0].io_volt_sel */ + + /* P3.1 */ + P3_1_GPIO = 0, /* GPIO controls 'out' */ + P3_1_AMUXA = 4, /* Analog mux bus A */ + P3_1_AMUXB = 5, /* Analog mux bus B */ + P3_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P3_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P3_1_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:1 */ + P3_1_TCPWM1_LINE_COMPL7 = 9, /* Digital Active - tcpwm[1].line_compl[7]:0 */ + P3_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:15 */ + P3_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:15 */ + P3_1_LCD_COM15 = 12, /* Digital Deep Sleep - lcd.com[15]:0 */ + P3_1_LCD_SEG15 = 13, /* Digital Deep Sleep - lcd.seg[15]:0 */ + P3_1_SCB2_UART_TX = 18, /* Digital Active - scb[2].uart_tx:1 */ + P3_1_SCB2_I2C_SDA = 19, /* Digital Active - scb[2].i2c_sda:1 */ + P3_1_SCB2_SPI_MISO = 20, /* Digital Active - scb[2].spi_miso:1 */ + P3_1_PERI_TR_IO_INPUT7 = 24, /* Digital Active - peri.tr_io_input[7]:0 */ + P3_1_SDHC0_CARD_IF_PWR_EN = 26, /* Digital Active - sdhc[0].card_if_pwr_en */ + + /* P5.0 */ + P5_0_GPIO = 0, /* GPIO controls 'out' */ + P5_0_AMUXA = 4, /* Analog mux bus A */ + P5_0_AMUXB = 5, /* Analog mux bus B */ + P5_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P5_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P5_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:2 */ + P5_0_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:1 */ + P5_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:16 */ + P5_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:16 */ + P5_0_LCD_COM16 = 12, /* Digital Deep Sleep - lcd.com[16]:0 */ + P5_0_LCD_SEG16 = 13, /* Digital Deep Sleep - lcd.seg[16]:0 */ + P5_0_SCB5_UART_RX = 18, /* Digital Active - scb[5].uart_rx:1 */ + P5_0_SCB5_I2C_SCL = 19, /* Digital Active - scb[5].i2c_scl:1 */ + P5_0_SCB5_SPI_MOSI = 20, /* Digital Active - scb[5].spi_mosi:1 */ + P5_0_CANFD0_TTCAN_RX0 = 22, /* Digital Active - canfd[0].ttcan_rx[0] */ + P5_0_PERI_TR_IO_INPUT10 = 24, /* Digital Active - peri.tr_io_input[10]:0 */ + + /* P5.1 */ + P5_1_GPIO = 0, /* GPIO controls 'out' */ + P5_1_AMUXA = 4, /* Analog mux bus A */ + P5_1_AMUXB = 5, /* Analog mux bus B */ + P5_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P5_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P5_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:2 */ + P5_1_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:1 */ + P5_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:17 */ + P5_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:17 */ + P5_1_LCD_COM17 = 12, /* Digital Deep Sleep - lcd.com[17]:0 */ + P5_1_LCD_SEG17 = 13, /* Digital Deep Sleep - lcd.seg[17]:0 */ + P5_1_SCB5_UART_TX = 18, /* Digital Active - scb[5].uart_tx:1 */ + P5_1_SCB5_I2C_SDA = 19, /* Digital Active - scb[5].i2c_sda:1 */ + P5_1_SCB5_SPI_MISO = 20, /* Digital Active - scb[5].spi_miso:1 */ + P5_1_CANFD0_TTCAN_TX0 = 22, /* Digital Active - canfd[0].ttcan_tx[0] */ + P5_1_PERI_TR_IO_INPUT11 = 24, /* Digital Active - peri.tr_io_input[11]:0 */ + + /* P5.6 */ + P5_6_GPIO = 0, /* GPIO controls 'out' */ + P5_6_AMUXA = 4, /* Analog mux bus A */ + P5_6_AMUXB = 5, /* Analog mux bus B */ + P5_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P5_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P5_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:2 */ + P5_6_TCPWM1_LINE1 = 9, /* Digital Active - tcpwm[1].line[1]:1 */ + P5_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:18 */ + P5_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:18 */ + P5_6_LCD_COM18 = 12, /* Digital Deep Sleep - lcd.com[18]:0 */ + P5_6_LCD_SEG18 = 13, /* Digital Deep Sleep - lcd.seg[18]:0 */ + + /* P5.7 */ + P5_7_GPIO = 0, /* GPIO controls 'out' */ + P5_7_AMUXA = 4, /* Analog mux bus A */ + P5_7_AMUXB = 5, /* Analog mux bus B */ + P5_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P5_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P5_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:2 */ + P5_7_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:1 */ + P5_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:19 */ + P5_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:19 */ + P5_7_LCD_COM19 = 12, /* Digital Deep Sleep - lcd.com[19]:0 */ + P5_7_LCD_SEG19 = 13, /* Digital Deep Sleep - lcd.seg[19]:0 */ + + /* P6.0 */ + P6_0_GPIO = 0, /* GPIO controls 'out' */ + P6_0_AMUXA = 4, /* Analog mux bus A */ + P6_0_AMUXB = 5, /* Analog mux bus B */ + P6_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P6_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P6_0_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:2 */ + P6_0_TCPWM1_LINE2 = 9, /* Digital Active - tcpwm[1].line[2]:1 */ + P6_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:20 */ + P6_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:20 */ + P6_0_LCD_COM20 = 12, /* Digital Deep Sleep - lcd.com[20]:0 */ + P6_0_LCD_SEG20 = 13, /* Digital Deep Sleep - lcd.seg[20]:0 */ + P6_0_SCB3_UART_RX = 18, /* Digital Active - scb[3].uart_rx:0 */ + P6_0_SCB3_I2C_SCL = 19, /* Digital Active - scb[3].i2c_scl:0 */ + P6_0_SCB3_SPI_MOSI = 20, /* Digital Active - scb[3].spi_mosi:0 */ + P6_0_CPUSS_FAULT_OUT0 = 25, /* Digital Active - cpuss.fault_out[0] */ + + /* P6.1 */ + P6_1_GPIO = 0, /* GPIO controls 'out' */ + P6_1_AMUXA = 4, /* Analog mux bus A */ + P6_1_AMUXB = 5, /* Analog mux bus B */ + P6_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P6_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P6_1_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:2 */ + P6_1_TCPWM1_LINE_COMPL2 = 9, /* Digital Active - tcpwm[1].line_compl[2]:1 */ + P6_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:21 */ + P6_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:21 */ + P6_1_LCD_COM21 = 12, /* Digital Deep Sleep - lcd.com[21]:0 */ + P6_1_LCD_SEG21 = 13, /* Digital Deep Sleep - lcd.seg[21]:0 */ + P6_1_SCB3_UART_TX = 18, /* Digital Active - scb[3].uart_tx:0 */ + P6_1_SCB3_I2C_SDA = 19, /* Digital Active - scb[3].i2c_sda:0 */ + P6_1_SCB3_SPI_MISO = 20, /* Digital Active - scb[3].spi_miso:0 */ + P6_1_CPUSS_FAULT_OUT1 = 25, /* Digital Active - cpuss.fault_out[1] */ + + /* P6.2 */ + P6_2_GPIO = 0, /* GPIO controls 'out' */ + P6_2_AMUXA = 4, /* Analog mux bus A */ + P6_2_AMUXB = 5, /* Analog mux bus B */ + P6_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P6_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P6_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:2 */ + P6_2_TCPWM1_LINE3 = 9, /* Digital Active - tcpwm[1].line[3]:1 */ + P6_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:22 */ + P6_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:22 */ + P6_2_LCD_COM22 = 12, /* Digital Deep Sleep - lcd.com[22]:0 */ + P6_2_LCD_SEG22 = 13, /* Digital Deep Sleep - lcd.seg[22]:0 */ + P6_2_SCB3_UART_RTS = 18, /* Digital Active - scb[3].uart_rts:0 */ + P6_2_SCB3_SPI_CLK = 20, /* Digital Active - scb[3].spi_clk:0 */ + + /* P6.3 */ + P6_3_GPIO = 0, /* GPIO controls 'out' */ + P6_3_AMUXA = 4, /* Analog mux bus A */ + P6_3_AMUXB = 5, /* Analog mux bus B */ + P6_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P6_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P6_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:2 */ + P6_3_TCPWM1_LINE_COMPL3 = 9, /* Digital Active - tcpwm[1].line_compl[3]:1 */ + P6_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:23 */ + P6_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:23 */ + P6_3_LCD_COM23 = 12, /* Digital Deep Sleep - lcd.com[23]:0 */ + P6_3_LCD_SEG23 = 13, /* Digital Deep Sleep - lcd.seg[23]:0 */ + P6_3_SCB3_UART_CTS = 18, /* Digital Active - scb[3].uart_cts:0 */ + P6_3_SCB3_SPI_SELECT0 = 20, /* Digital Active - scb[3].spi_select0:0 */ + + /* P6.4 */ + P6_4_GPIO = 0, /* GPIO controls 'out' */ + P6_4_AMUXA = 4, /* Analog mux bus A */ + P6_4_AMUXB = 5, /* Analog mux bus B */ + P6_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P6_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P6_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:3 */ + P6_4_TCPWM1_LINE4 = 9, /* Digital Active - tcpwm[1].line[4]:1 */ + P6_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:24 */ + P6_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:24 */ + P6_4_LCD_COM24 = 12, /* Digital Deep Sleep - lcd.com[24]:0 */ + P6_4_LCD_SEG24 = 13, /* Digital Deep Sleep - lcd.seg[24]:0 */ + P6_4_SCB6_I2C_SCL = 14, /* Digital Deep Sleep - scb[6].i2c_scl:0 */ + P6_4_PERI_TR_IO_INPUT12 = 24, /* Digital Active - peri.tr_io_input[12]:0 */ + P6_4_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:1 */ + P6_4_CPUSS_SWJ_SWO_TDO = 29, /* Digital Deep Sleep - cpuss.swj_swo_tdo */ + P6_4_SCB6_SPI_MOSI = 30, /* Digital Deep Sleep - scb[6].spi_mosi:0 */ + P6_4_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:0 */ + + /* P6.5 */ + P6_5_GPIO = 0, /* GPIO controls 'out' */ + P6_5_AMUXA = 4, /* Analog mux bus A */ + P6_5_AMUXB = 5, /* Analog mux bus B */ + P6_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P6_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P6_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:3 */ + P6_5_TCPWM1_LINE_COMPL4 = 9, /* Digital Active - tcpwm[1].line_compl[4]:1 */ + P6_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:25 */ + P6_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:25 */ + P6_5_LCD_COM25 = 12, /* Digital Deep Sleep - lcd.com[25]:0 */ + P6_5_LCD_SEG25 = 13, /* Digital Deep Sleep - lcd.seg[25]:0 */ + P6_5_SCB6_I2C_SDA = 14, /* Digital Deep Sleep - scb[6].i2c_sda:0 */ + P6_5_PERI_TR_IO_INPUT13 = 24, /* Digital Active - peri.tr_io_input[13]:0 */ + P6_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:1 */ + P6_5_CPUSS_SWJ_SWDOE_TDI = 29, /* Digital Deep Sleep - cpuss.swj_swdoe_tdi */ + P6_5_SCB6_SPI_MISO = 30, /* Digital Deep Sleep - scb[6].spi_miso:0 */ + P6_5_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:0 */ + + /* P6.6 */ + P6_6_GPIO = 0, /* GPIO controls 'out' */ + P6_6_AMUXA = 4, /* Analog mux bus A */ + P6_6_AMUXB = 5, /* Analog mux bus B */ + P6_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P6_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P6_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:3 */ + P6_6_TCPWM1_LINE5 = 9, /* Digital Active - tcpwm[1].line[5]:1 */ + P6_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:26 */ + P6_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:26 */ + P6_6_LCD_COM26 = 12, /* Digital Deep Sleep - lcd.com[26]:0 */ + P6_6_LCD_SEG26 = 13, /* Digital Deep Sleep - lcd.seg[26]:0 */ + P6_6_CPUSS_SWJ_SWDIO_TMS = 29, /* Digital Deep Sleep - cpuss.swj_swdio_tms */ + P6_6_SCB6_SPI_CLK = 30, /* Digital Deep Sleep - scb[6].spi_clk:0 */ + + /* P6.7 */ + P6_7_GPIO = 0, /* GPIO controls 'out' */ + P6_7_AMUXA = 4, /* Analog mux bus A */ + P6_7_AMUXB = 5, /* Analog mux bus B */ + P6_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P6_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P6_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:3 */ + P6_7_TCPWM1_LINE_COMPL5 = 9, /* Digital Active - tcpwm[1].line_compl[5]:1 */ + P6_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:27 */ + P6_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:27 */ + P6_7_LCD_COM27 = 12, /* Digital Deep Sleep - lcd.com[27]:0 */ + P6_7_LCD_SEG27 = 13, /* Digital Deep Sleep - lcd.seg[27]:0 */ + P6_7_CPUSS_SWJ_SWCLK_TCLK = 29, /* Digital Deep Sleep - cpuss.swj_swclk_tclk */ + P6_7_SCB6_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[6].spi_select0:0 */ + + /* P7.0 */ + P7_0_GPIO = 0, /* GPIO controls 'out' */ + P7_0_AMUXA = 4, /* Analog mux bus A */ + P7_0_AMUXB = 5, /* Analog mux bus B */ + P7_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P7_0_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:3 */ + P7_0_TCPWM1_LINE6 = 9, /* Digital Active - tcpwm[1].line[6]:1 */ + P7_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:28 */ + P7_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:28 */ + P7_0_LCD_COM28 = 12, /* Digital Deep Sleep - lcd.com[28]:0 */ + P7_0_LCD_SEG28 = 13, /* Digital Deep Sleep - lcd.seg[28]:0 */ + P7_0_SCB4_UART_RX = 18, /* Digital Active - scb[4].uart_rx:1 */ + P7_0_SCB4_I2C_SCL = 19, /* Digital Active - scb[4].i2c_scl:1 */ + P7_0_SCB4_SPI_MOSI = 20, /* Digital Active - scb[4].spi_mosi:1 */ + P7_0_PERI_TR_IO_INPUT14 = 24, /* Digital Active - peri.tr_io_input[14]:0 */ + P7_0_CPUSS_TRACE_CLOCK = 26, /* Digital Active - cpuss.trace_clock */ + + /* P7.1 */ + P7_1_GPIO = 0, /* GPIO controls 'out' */ + P7_1_AMUXA = 4, /* Analog mux bus A */ + P7_1_AMUXB = 5, /* Analog mux bus B */ + P7_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P7_1_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:3 */ + P7_1_TCPWM1_LINE_COMPL6 = 9, /* Digital Active - tcpwm[1].line_compl[6]:1 */ + P7_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:29 */ + P7_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:29 */ + P7_1_LCD_COM29 = 12, /* Digital Deep Sleep - lcd.com[29]:0 */ + P7_1_LCD_SEG29 = 13, /* Digital Deep Sleep - lcd.seg[29]:0 */ + P7_1_SCB4_UART_TX = 18, /* Digital Active - scb[4].uart_tx:1 */ + P7_1_SCB4_I2C_SDA = 19, /* Digital Active - scb[4].i2c_sda:1 */ + P7_1_SCB4_SPI_MISO = 20, /* Digital Active - scb[4].spi_miso:1 */ + P7_1_PERI_TR_IO_INPUT15 = 24, /* Digital Active - peri.tr_io_input[15]:0 */ + + /* P7.2 */ + P7_2_GPIO = 0, /* GPIO controls 'out' */ + P7_2_AMUXA = 4, /* Analog mux bus A */ + P7_2_AMUXB = 5, /* Analog mux bus B */ + P7_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P7_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:3 */ + P7_2_TCPWM1_LINE7 = 9, /* Digital Active - tcpwm[1].line[7]:1 */ + P7_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:30 */ + P7_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:30 */ + P7_2_LCD_COM30 = 12, /* Digital Deep Sleep - lcd.com[30]:0 */ + P7_2_LCD_SEG30 = 13, /* Digital Deep Sleep - lcd.seg[30]:0 */ + P7_2_SCB4_UART_RTS = 18, /* Digital Active - scb[4].uart_rts:1 */ + P7_2_SCB4_SPI_CLK = 20, /* Digital Active - scb[4].spi_clk:1 */ + + /* P7.3 */ + P7_3_GPIO = 0, /* GPIO controls 'out' */ + P7_3_AMUXA = 4, /* Analog mux bus A */ + P7_3_AMUXB = 5, /* Analog mux bus B */ + P7_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P7_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:3 */ + P7_3_TCPWM1_LINE_COMPL7 = 9, /* Digital Active - tcpwm[1].line_compl[7]:1 */ + P7_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:31 */ + P7_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:31 */ + P7_3_LCD_COM31 = 12, /* Digital Deep Sleep - lcd.com[31]:0 */ + P7_3_LCD_SEG31 = 13, /* Digital Deep Sleep - lcd.seg[31]:0 */ + P7_3_SCB4_UART_CTS = 18, /* Digital Active - scb[4].uart_cts:1 */ + P7_3_SCB4_SPI_SELECT0 = 20, /* Digital Active - scb[4].spi_select0:1 */ + + /* P7.4 */ + P7_4_GPIO = 0, /* GPIO controls 'out' */ + P7_4_AMUXA = 4, /* Analog mux bus A */ + P7_4_AMUXB = 5, /* Analog mux bus B */ + P7_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P7_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:4 */ + P7_4_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:2 */ + P7_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:32 */ + P7_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:32 */ + P7_4_LCD_COM32 = 12, /* Digital Deep Sleep - lcd.com[32]:0 */ + P7_4_LCD_SEG32 = 13, /* Digital Deep Sleep - lcd.seg[32]:0 */ + P7_4_SCB4_SPI_SELECT1 = 20, /* Digital Active - scb[4].spi_select1:1 */ + P7_4_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:2 */ + + /* P7.5 */ + P7_5_GPIO = 0, /* GPIO controls 'out' */ + P7_5_AMUXA = 4, /* Analog mux bus A */ + P7_5_AMUXB = 5, /* Analog mux bus B */ + P7_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P7_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:4 */ + P7_5_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:2 */ + P7_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:33 */ + P7_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:33 */ + P7_5_LCD_COM33 = 12, /* Digital Deep Sleep - lcd.com[33]:0 */ + P7_5_LCD_SEG33 = 13, /* Digital Deep Sleep - lcd.seg[33]:0 */ + P7_5_SCB4_SPI_SELECT2 = 20, /* Digital Active - scb[4].spi_select2:1 */ + P7_5_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:2 */ + + /* P7.6 */ + P7_6_GPIO = 0, /* GPIO controls 'out' */ + P7_6_AMUXA = 4, /* Analog mux bus A */ + P7_6_AMUXB = 5, /* Analog mux bus B */ + P7_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P7_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:4 */ + P7_6_TCPWM1_LINE1 = 9, /* Digital Active - tcpwm[1].line[1]:2 */ + P7_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:34 */ + P7_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:34 */ + P7_6_LCD_COM34 = 12, /* Digital Deep Sleep - lcd.com[34]:0 */ + P7_6_LCD_SEG34 = 13, /* Digital Deep Sleep - lcd.seg[34]:0 */ + P7_6_SCB4_SPI_SELECT3 = 20, /* Digital Active - scb[4].spi_select3:1 */ + P7_6_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:2 */ + + /* P7.7 */ + P7_7_GPIO = 0, /* GPIO controls 'out' */ + P7_7_AMUXA = 4, /* Analog mux bus A */ + P7_7_AMUXB = 5, /* Analog mux bus B */ + P7_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P7_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:4 */ + P7_7_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:2 */ + P7_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:35 */ + P7_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:35 */ + P7_7_LCD_COM35 = 12, /* Digital Deep Sleep - lcd.com[35]:0 */ + P7_7_LCD_SEG35 = 13, /* Digital Deep Sleep - lcd.seg[35]:0 */ + P7_7_CPUSS_CLK_FM_PUMP = 21, /* Digital Active - cpuss.clk_fm_pump */ + P7_7_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:2 */ + + /* P8.0 */ + P8_0_GPIO = 0, /* GPIO controls 'out' */ + P8_0_AMUXA = 4, /* Analog mux bus A */ + P8_0_AMUXB = 5, /* Analog mux bus B */ + P8_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P8_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P8_0_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:4 */ + P8_0_TCPWM1_LINE2 = 9, /* Digital Active - tcpwm[1].line[2]:2 */ + P8_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:36 */ + P8_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:36 */ + P8_0_LCD_COM36 = 12, /* Digital Deep Sleep - lcd.com[36]:0 */ + P8_0_LCD_SEG36 = 13, /* Digital Deep Sleep - lcd.seg[36]:0 */ + P8_0_SCB4_UART_RX = 18, /* Digital Active - scb[4].uart_rx:0 */ + P8_0_SCB4_I2C_SCL = 19, /* Digital Active - scb[4].i2c_scl:0 */ + P8_0_SCB4_SPI_MOSI = 20, /* Digital Active - scb[4].spi_mosi:0 */ + P8_0_PERI_TR_IO_INPUT16 = 24, /* Digital Active - peri.tr_io_input[16]:0 */ + + /* P8.1 */ + P8_1_GPIO = 0, /* GPIO controls 'out' */ + P8_1_AMUXA = 4, /* Analog mux bus A */ + P8_1_AMUXB = 5, /* Analog mux bus B */ + P8_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P8_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P8_1_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:4 */ + P8_1_TCPWM1_LINE_COMPL2 = 9, /* Digital Active - tcpwm[1].line_compl[2]:2 */ + P8_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:37 */ + P8_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:37 */ + P8_1_LCD_COM37 = 12, /* Digital Deep Sleep - lcd.com[37]:0 */ + P8_1_LCD_SEG37 = 13, /* Digital Deep Sleep - lcd.seg[37]:0 */ + P8_1_SCB4_UART_TX = 18, /* Digital Active - scb[4].uart_tx:0 */ + P8_1_SCB4_I2C_SDA = 19, /* Digital Active - scb[4].i2c_sda:0 */ + P8_1_SCB4_SPI_MISO = 20, /* Digital Active - scb[4].spi_miso:0 */ + P8_1_PERI_TR_IO_INPUT17 = 24, /* Digital Active - peri.tr_io_input[17]:0 */ + + /* P8.2 */ + P8_2_GPIO = 0, /* GPIO controls 'out' */ + P8_2_AMUXA = 4, /* Analog mux bus A */ + P8_2_AMUXB = 5, /* Analog mux bus B */ + P8_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P8_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P8_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:4 */ + P8_2_TCPWM1_LINE3 = 9, /* Digital Active - tcpwm[1].line[3]:2 */ + P8_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:38 */ + P8_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:38 */ + P8_2_LCD_COM38 = 12, /* Digital Deep Sleep - lcd.com[38]:0 */ + P8_2_LCD_SEG38 = 13, /* Digital Deep Sleep - lcd.seg[38]:0 */ + P8_2_LPCOMP_DSI_COMP0 = 15, /* Digital Deep Sleep - lpcomp.dsi_comp0:0 */ + P8_2_SCB4_UART_RTS = 18, /* Digital Active - scb[4].uart_rts:0 */ + P8_2_SCB4_SPI_CLK = 20, /* Digital Active - scb[4].spi_clk:0 */ + + /* P8.3 */ + P8_3_GPIO = 0, /* GPIO controls 'out' */ + P8_3_AMUXA = 4, /* Analog mux bus A */ + P8_3_AMUXB = 5, /* Analog mux bus B */ + P8_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P8_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P8_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:4 */ + P8_3_TCPWM1_LINE_COMPL3 = 9, /* Digital Active - tcpwm[1].line_compl[3]:2 */ + P8_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:39 */ + P8_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:39 */ + P8_3_LCD_COM39 = 12, /* Digital Deep Sleep - lcd.com[39]:0 */ + P8_3_LCD_SEG39 = 13, /* Digital Deep Sleep - lcd.seg[39]:0 */ + P8_3_LPCOMP_DSI_COMP1 = 15, /* Digital Deep Sleep - lpcomp.dsi_comp1:0 */ + P8_3_SCB4_UART_CTS = 18, /* Digital Active - scb[4].uart_cts:0 */ + P8_3_SCB4_SPI_SELECT0 = 20, /* Digital Active - scb[4].spi_select0:0 */ + + /* P9.0 */ + P9_0_GPIO = 0, /* GPIO controls 'out' */ + P9_0_AMUXA = 4, /* Analog mux bus A */ + P9_0_AMUXB = 5, /* Analog mux bus B */ + P9_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P9_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P9_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:5 */ + P9_0_TCPWM1_LINE4 = 9, /* Digital Active - tcpwm[1].line[4]:2 */ + P9_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:40 */ + P9_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:40 */ + P9_0_LCD_COM40 = 12, /* Digital Deep Sleep - lcd.com[40]:0 */ + P9_0_LCD_SEG40 = 13, /* Digital Deep Sleep - lcd.seg[40]:0 */ + P9_0_SCB2_UART_RX = 18, /* Digital Active - scb[2].uart_rx:0 */ + P9_0_SCB2_I2C_SCL = 19, /* Digital Active - scb[2].i2c_scl:0 */ + P9_0_SCB2_SPI_MOSI = 20, /* Digital Active - scb[2].spi_mosi:0 */ + P9_0_PERI_TR_IO_INPUT18 = 24, /* Digital Active - peri.tr_io_input[18]:0 */ + P9_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:0 */ + + /* P9.1 */ + P9_1_GPIO = 0, /* GPIO controls 'out' */ + P9_1_AMUXA = 4, /* Analog mux bus A */ + P9_1_AMUXB = 5, /* Analog mux bus B */ + P9_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P9_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P9_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:5 */ + P9_1_TCPWM1_LINE_COMPL4 = 9, /* Digital Active - tcpwm[1].line_compl[4]:2 */ + P9_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:41 */ + P9_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:41 */ + P9_1_LCD_COM41 = 12, /* Digital Deep Sleep - lcd.com[41]:0 */ + P9_1_LCD_SEG41 = 13, /* Digital Deep Sleep - lcd.seg[41]:0 */ + P9_1_SCB2_UART_TX = 18, /* Digital Active - scb[2].uart_tx:0 */ + P9_1_SCB2_I2C_SDA = 19, /* Digital Active - scb[2].i2c_sda:0 */ + P9_1_SCB2_SPI_MISO = 20, /* Digital Active - scb[2].spi_miso:0 */ + P9_1_PERI_TR_IO_INPUT19 = 24, /* Digital Active - peri.tr_io_input[19]:0 */ + P9_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:0 */ + P9_1_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:1 */ + + /* P9.2 */ + P9_2_GPIO = 0, /* GPIO controls 'out' */ + P9_2_AMUXA = 4, /* Analog mux bus A */ + P9_2_AMUXB = 5, /* Analog mux bus B */ + P9_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P9_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P9_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:5 */ + P9_2_TCPWM1_LINE5 = 9, /* Digital Active - tcpwm[1].line[5]:2 */ + P9_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:42 */ + P9_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:42 */ + P9_2_LCD_COM42 = 12, /* Digital Deep Sleep - lcd.com[42]:0 */ + P9_2_LCD_SEG42 = 13, /* Digital Deep Sleep - lcd.seg[42]:0 */ + P9_2_SCB2_UART_RTS = 18, /* Digital Active - scb[2].uart_rts:0 */ + P9_2_SCB2_SPI_CLK = 20, /* Digital Active - scb[2].spi_clk:0 */ + P9_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:0 */ + + /* P9.3 */ + P9_3_GPIO = 0, /* GPIO controls 'out' */ + P9_3_AMUXA = 4, /* Analog mux bus A */ + P9_3_AMUXB = 5, /* Analog mux bus B */ + P9_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P9_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P9_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:5 */ + P9_3_TCPWM1_LINE_COMPL5 = 9, /* Digital Active - tcpwm[1].line_compl[5]:2 */ + P9_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:43 */ + P9_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:43 */ + P9_3_LCD_COM43 = 12, /* Digital Deep Sleep - lcd.com[43]:0 */ + P9_3_LCD_SEG43 = 13, /* Digital Deep Sleep - lcd.seg[43]:0 */ + P9_3_SCB2_UART_CTS = 18, /* Digital Active - scb[2].uart_cts:0 */ + P9_3_SCB2_SPI_SELECT0 = 20, /* Digital Active - scb[2].spi_select0:0 */ + P9_3_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:0 */ + P9_3_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:1 */ + + /* P10.0 */ + P10_0_GPIO = 0, /* GPIO controls 'out' */ + P10_0_AMUXA = 4, /* Analog mux bus A */ + P10_0_AMUXB = 5, /* Analog mux bus B */ + P10_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P10_0_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:5 */ + P10_0_TCPWM1_LINE6 = 9, /* Digital Active - tcpwm[1].line[6]:2 */ + P10_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:44 */ + P10_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:44 */ + P10_0_LCD_COM44 = 12, /* Digital Deep Sleep - lcd.com[44]:0 */ + P10_0_LCD_SEG44 = 13, /* Digital Deep Sleep - lcd.seg[44]:0 */ + P10_0_SCB1_UART_RX = 18, /* Digital Active - scb[1].uart_rx:1 */ + P10_0_SCB1_I2C_SCL = 19, /* Digital Active - scb[1].i2c_scl:1 */ + P10_0_SCB1_SPI_MOSI = 20, /* Digital Active - scb[1].spi_mosi:1 */ + P10_0_PERI_TR_IO_INPUT20 = 24, /* Digital Active - peri.tr_io_input[20]:0 */ + P10_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:1 */ + + /* P10.1 */ + P10_1_GPIO = 0, /* GPIO controls 'out' */ + P10_1_AMUXA = 4, /* Analog mux bus A */ + P10_1_AMUXB = 5, /* Analog mux bus B */ + P10_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P10_1_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:5 */ + P10_1_TCPWM1_LINE_COMPL6 = 9, /* Digital Active - tcpwm[1].line_compl[6]:2 */ + P10_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:45 */ + P10_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:45 */ + P10_1_LCD_COM45 = 12, /* Digital Deep Sleep - lcd.com[45]:0 */ + P10_1_LCD_SEG45 = 13, /* Digital Deep Sleep - lcd.seg[45]:0 */ + P10_1_SCB1_UART_TX = 18, /* Digital Active - scb[1].uart_tx:1 */ + P10_1_SCB1_I2C_SDA = 19, /* Digital Active - scb[1].i2c_sda:1 */ + P10_1_SCB1_SPI_MISO = 20, /* Digital Active - scb[1].spi_miso:1 */ + P10_1_PERI_TR_IO_INPUT21 = 24, /* Digital Active - peri.tr_io_input[21]:0 */ + P10_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:1 */ + + /* P10.2 */ + P10_2_GPIO = 0, /* GPIO controls 'out' */ + P10_2_AMUXA = 4, /* Analog mux bus A */ + P10_2_AMUXB = 5, /* Analog mux bus B */ + P10_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P10_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:5 */ + P10_2_TCPWM1_LINE7 = 9, /* Digital Active - tcpwm[1].line[7]:2 */ + P10_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:46 */ + P10_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:46 */ + P10_2_LCD_COM46 = 12, /* Digital Deep Sleep - lcd.com[46]:0 */ + P10_2_LCD_SEG46 = 13, /* Digital Deep Sleep - lcd.seg[46]:0 */ + P10_2_SCB1_UART_RTS = 18, /* Digital Active - scb[1].uart_rts:1 */ + P10_2_SCB1_SPI_CLK = 20, /* Digital Active - scb[1].spi_clk:1 */ + P10_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:1 */ + + /* P10.3 */ + P10_3_GPIO = 0, /* GPIO controls 'out' */ + P10_3_AMUXA = 4, /* Analog mux bus A */ + P10_3_AMUXB = 5, /* Analog mux bus B */ + P10_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P10_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:5 */ + P10_3_TCPWM1_LINE_COMPL7 = 9, /* Digital Active - tcpwm[1].line_compl[7]:2 */ + P10_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:47 */ + P10_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:47 */ + P10_3_LCD_COM47 = 12, /* Digital Deep Sleep - lcd.com[47]:0 */ + P10_3_LCD_SEG47 = 13, /* Digital Deep Sleep - lcd.seg[47]:0 */ + P10_3_SCB1_UART_CTS = 18, /* Digital Active - scb[1].uart_cts:1 */ + P10_3_SCB1_SPI_SELECT0 = 20, /* Digital Active - scb[1].spi_select0:1 */ + P10_3_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:1 */ + + /* P10.4 */ + P10_4_GPIO = 0, /* GPIO controls 'out' */ + P10_4_AMUXA = 4, /* Analog mux bus A */ + P10_4_AMUXB = 5, /* Analog mux bus B */ + P10_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P10_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:6 */ + P10_4_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:3 */ + P10_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:48 */ + P10_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:48 */ + P10_4_LCD_COM48 = 12, /* Digital Deep Sleep - lcd.com[48]:0 */ + P10_4_LCD_SEG48 = 13, /* Digital Deep Sleep - lcd.seg[48]:0 */ + P10_4_SCB1_SPI_SELECT1 = 20, /* Digital Active - scb[1].spi_select1:1 */ + + /* P10.5 */ + P10_5_GPIO = 0, /* GPIO controls 'out' */ + P10_5_AMUXA = 4, /* Analog mux bus A */ + P10_5_AMUXB = 5, /* Analog mux bus B */ + P10_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P10_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:6 */ + P10_5_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:3 */ + P10_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:49 */ + P10_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:49 */ + P10_5_LCD_COM49 = 12, /* Digital Deep Sleep - lcd.com[49]:0 */ + P10_5_LCD_SEG49 = 13, /* Digital Deep Sleep - lcd.seg[49]:0 */ + P10_5_SCB1_SPI_SELECT2 = 20, /* Digital Active - scb[1].spi_select2:1 */ + + /* P10.6 */ + P10_6_GPIO = 0, /* GPIO controls 'out' */ + P10_6_AMUXA = 4, /* Analog mux bus A */ + P10_6_AMUXB = 5, /* Analog mux bus B */ + P10_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P10_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:6 */ + P10_6_TCPWM1_LINE1 = 9, /* Digital Active - tcpwm[1].line[1]:3 */ + P10_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:50 */ + P10_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:50 */ + P10_6_LCD_COM50 = 12, /* Digital Deep Sleep - lcd.com[50]:0 */ + P10_6_LCD_SEG50 = 13, /* Digital Deep Sleep - lcd.seg[50]:0 */ + P10_6_SCB1_SPI_SELECT3 = 20, /* Digital Active - scb[1].spi_select3:1 */ + + /* P10.7 */ + P10_7_GPIO = 0, /* GPIO controls 'out' */ + P10_7_AMUXA = 4, /* Analog mux bus A */ + P10_7_AMUXB = 5, /* Analog mux bus B */ + P10_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P10_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:6 */ + P10_7_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:3 */ + P10_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:51 */ + P10_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:51 */ + P10_7_LCD_COM51 = 12, /* Digital Deep Sleep - lcd.com[51]:0 */ + P10_7_LCD_SEG51 = 13, /* Digital Deep Sleep - lcd.seg[51]:0 */ + + /* P11.0 */ + P11_0_GPIO = 0, /* GPIO controls 'out' */ + P11_0_AMUXA = 4, /* Analog mux bus A */ + P11_0_AMUXB = 5, /* Analog mux bus B */ + P11_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P11_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P11_0_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:6 */ + P11_0_TCPWM1_LINE2 = 9, /* Digital Active - tcpwm[1].line[2]:3 */ + P11_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:52 */ + P11_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:52 */ + P11_0_LCD_COM52 = 12, /* Digital Deep Sleep - lcd.com[52]:0 */ + P11_0_LCD_SEG52 = 13, /* Digital Deep Sleep - lcd.seg[52]:0 */ + P11_0_SMIF_SPI_SELECT2 = 17, /* Digital Active - smif.spi_select2 */ + P11_0_SCB5_UART_RX = 18, /* Digital Active - scb[5].uart_rx:0 */ + P11_0_SCB5_I2C_SCL = 19, /* Digital Active - scb[5].i2c_scl:0 */ + P11_0_SCB5_SPI_MOSI = 20, /* Digital Active - scb[5].spi_mosi:0 */ + P11_0_PERI_TR_IO_INPUT22 = 24, /* Digital Active - peri.tr_io_input[22]:0 */ + + /* P11.1 */ + P11_1_GPIO = 0, /* GPIO controls 'out' */ + P11_1_AMUXA = 4, /* Analog mux bus A */ + P11_1_AMUXB = 5, /* Analog mux bus B */ + P11_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P11_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P11_1_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:6 */ + P11_1_TCPWM1_LINE_COMPL2 = 9, /* Digital Active - tcpwm[1].line_compl[2]:3 */ + P11_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:53 */ + P11_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:53 */ + P11_1_LCD_COM53 = 12, /* Digital Deep Sleep - lcd.com[53]:0 */ + P11_1_LCD_SEG53 = 13, /* Digital Deep Sleep - lcd.seg[53]:0 */ + P11_1_SMIF_SPI_SELECT1 = 17, /* Digital Active - smif.spi_select1 */ + P11_1_SCB5_UART_TX = 18, /* Digital Active - scb[5].uart_tx:0 */ + P11_1_SCB5_I2C_SDA = 19, /* Digital Active - scb[5].i2c_sda:0 */ + P11_1_SCB5_SPI_MISO = 20, /* Digital Active - scb[5].spi_miso:0 */ + P11_1_PERI_TR_IO_INPUT23 = 24, /* Digital Active - peri.tr_io_input[23]:0 */ + + /* P11.2 */ + P11_2_GPIO = 0, /* GPIO controls 'out' */ + P11_2_AMUXA = 4, /* Analog mux bus A */ + P11_2_AMUXB = 5, /* Analog mux bus B */ + P11_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P11_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P11_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:6 */ + P11_2_TCPWM1_LINE3 = 9, /* Digital Active - tcpwm[1].line[3]:3 */ + P11_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:54 */ + P11_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:54 */ + P11_2_LCD_COM54 = 12, /* Digital Deep Sleep - lcd.com[54]:0 */ + P11_2_LCD_SEG54 = 13, /* Digital Deep Sleep - lcd.seg[54]:0 */ + P11_2_SMIF_SPI_SELECT0 = 17, /* Digital Active - smif.spi_select0 */ + P11_2_SCB5_UART_RTS = 18, /* Digital Active - scb[5].uart_rts:0 */ + P11_2_SCB5_SPI_CLK = 20, /* Digital Active - scb[5].spi_clk:0 */ + + /* P11.3 */ + P11_3_GPIO = 0, /* GPIO controls 'out' */ + P11_3_AMUXA = 4, /* Analog mux bus A */ + P11_3_AMUXB = 5, /* Analog mux bus B */ + P11_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P11_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P11_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:6 */ + P11_3_TCPWM1_LINE_COMPL3 = 9, /* Digital Active - tcpwm[1].line_compl[3]:3 */ + P11_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:55 */ + P11_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:55 */ + P11_3_LCD_COM55 = 12, /* Digital Deep Sleep - lcd.com[55]:0 */ + P11_3_LCD_SEG55 = 13, /* Digital Deep Sleep - lcd.seg[55]:0 */ + P11_3_SMIF_SPI_DATA3 = 17, /* Digital Active - smif.spi_data3 */ + P11_3_SCB5_UART_CTS = 18, /* Digital Active - scb[5].uart_cts:0 */ + P11_3_SCB5_SPI_SELECT0 = 20, /* Digital Active - scb[5].spi_select0:0 */ + P11_3_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:0 */ + + /* P11.4 */ + P11_4_GPIO = 0, /* GPIO controls 'out' */ + P11_4_AMUXA = 4, /* Analog mux bus A */ + P11_4_AMUXB = 5, /* Analog mux bus B */ + P11_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P11_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P11_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:7 */ + P11_4_TCPWM1_LINE4 = 9, /* Digital Active - tcpwm[1].line[4]:3 */ + P11_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:56 */ + P11_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:56 */ + P11_4_LCD_COM56 = 12, /* Digital Deep Sleep - lcd.com[56]:0 */ + P11_4_LCD_SEG56 = 13, /* Digital Deep Sleep - lcd.seg[56]:0 */ + P11_4_SMIF_SPI_DATA2 = 17, /* Digital Active - smif.spi_data2 */ + P11_4_SCB5_SPI_SELECT1 = 20, /* Digital Active - scb[5].spi_select1:0 */ + P11_4_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:0 */ + + /* P11.5 */ + P11_5_GPIO = 0, /* GPIO controls 'out' */ + P11_5_AMUXA = 4, /* Analog mux bus A */ + P11_5_AMUXB = 5, /* Analog mux bus B */ + P11_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P11_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P11_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:7 */ + P11_5_TCPWM1_LINE_COMPL4 = 9, /* Digital Active - tcpwm[1].line_compl[4]:3 */ + P11_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:57 */ + P11_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:57 */ + P11_5_LCD_COM57 = 12, /* Digital Deep Sleep - lcd.com[57]:0 */ + P11_5_LCD_SEG57 = 13, /* Digital Deep Sleep - lcd.seg[57]:0 */ + P11_5_SMIF_SPI_DATA1 = 17, /* Digital Active - smif.spi_data1 */ + P11_5_SCB5_SPI_SELECT2 = 20, /* Digital Active - scb[5].spi_select2:0 */ + + /* P11.6 */ + P11_6_GPIO = 0, /* GPIO controls 'out' */ + P11_6_AMUXA = 4, /* Analog mux bus A */ + P11_6_AMUXB = 5, /* Analog mux bus B */ + P11_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P11_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P11_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:7 */ + P11_6_TCPWM1_LINE5 = 9, /* Digital Active - tcpwm[1].line[5]:3 */ + P11_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:58 */ + P11_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:58 */ + P11_6_LCD_COM58 = 12, /* Digital Deep Sleep - lcd.com[58]:0 */ + P11_6_LCD_SEG58 = 13, /* Digital Deep Sleep - lcd.seg[58]:0 */ + P11_6_SMIF_SPI_DATA0 = 17, /* Digital Active - smif.spi_data0 */ + P11_6_SCB5_SPI_SELECT3 = 20, /* Digital Active - scb[5].spi_select3:0 */ + + /* P11.7 */ + P11_7_GPIO = 0, /* GPIO controls 'out' */ + P11_7_AMUXA = 4, /* Analog mux bus A */ + P11_7_AMUXB = 5, /* Analog mux bus B */ + P11_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P11_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P11_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:7 */ + P11_7_TCPWM1_LINE_COMPL5 = 9, /* Digital Active - tcpwm[1].line_compl[5]:3 */ + P11_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:59 */ + P11_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:59 */ + P11_7_LCD_COM59 = 12, /* Digital Deep Sleep - lcd.com[59]:0 */ + P11_7_LCD_SEG59 = 13, /* Digital Deep Sleep - lcd.seg[59]:0 */ + P11_7_SMIF_SPI_CLK = 17, /* Digital Active - smif.spi_clk */ + + /* P12.0 */ + P12_0_GPIO = 0, /* GPIO controls 'out' */ + P12_0_AMUXA = 4, /* Analog mux bus A */ + P12_0_AMUXB = 5, /* Analog mux bus B */ + P12_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P12_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P12_0_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:7 */ + P12_0_TCPWM1_LINE6 = 9, /* Digital Active - tcpwm[1].line[6]:3 */ + P12_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:60 */ + P12_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:60 */ + P12_0_LCD_COM0 = 12, /* Digital Deep Sleep - lcd.com[0]:1 */ + P12_0_LCD_SEG0 = 13, /* Digital Deep Sleep - lcd.seg[0]:1 */ + P12_0_SCB6_I2C_SCL = 14, /* Digital Deep Sleep - scb[6].i2c_scl:1 */ + P12_0_PERI_TR_IO_INPUT24 = 24, /* Digital Active - peri.tr_io_input[24]:0 */ + + /* P12.1 */ + P12_1_GPIO = 0, /* GPIO controls 'out' */ + P12_1_AMUXA = 4, /* Analog mux bus A */ + P12_1_AMUXB = 5, /* Analog mux bus B */ + P12_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P12_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P12_1_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:7 */ + P12_1_TCPWM1_LINE_COMPL6 = 9, /* Digital Active - tcpwm[1].line_compl[6]:3 */ + P12_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:61 */ + P12_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:61 */ + P12_1_LCD_COM1 = 12, /* Digital Deep Sleep - lcd.com[1]:1 */ + P12_1_LCD_SEG1 = 13, /* Digital Deep Sleep - lcd.seg[1]:1 */ + P12_1_SCB6_I2C_SDA = 14, /* Digital Deep Sleep - scb[6].i2c_sda:1 */ + P12_1_PERI_TR_IO_INPUT25 = 24, /* Digital Active - peri.tr_io_input[25]:0 */ + + /* P12.6 */ + P12_6_GPIO = 0, /* GPIO controls 'out' */ + P12_6_AMUXA = 4, /* Analog mux bus A */ + P12_6_AMUXB = 5, /* Analog mux bus B */ + P12_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P12_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P12_6_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:7 */ + P12_6_TCPWM1_LINE7 = 9, /* Digital Active - tcpwm[1].line[7]:3 */ + P12_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:62 */ + P12_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:62 */ + P12_6_LCD_COM2 = 12, /* Digital Deep Sleep - lcd.com[2]:1 */ + P12_6_LCD_SEG2 = 13, /* Digital Deep Sleep - lcd.seg[2]:1 */ + + /* P12.7 */ + P12_7_GPIO = 0, /* GPIO controls 'out' */ + P12_7_AMUXA = 4, /* Analog mux bus A */ + P12_7_AMUXB = 5, /* Analog mux bus B */ + P12_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P12_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P12_7_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:7 */ + P12_7_TCPWM1_LINE_COMPL7 = 9, /* Digital Active - tcpwm[1].line_compl[7]:3 */ + P12_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:63 */ + P12_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:63 */ + P12_7_LCD_COM3 = 12, /* Digital Deep Sleep - lcd.com[3]:1 */ + P12_7_LCD_SEG3 = 13 /* Digital Deep Sleep - lcd.seg[3]:1 */ +} en_hsiom_sel_t; + +#endif /* _GPIO_PSOC6_03_100_TQFP_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_03_49_wlcsp.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_03_49_wlcsp.h new file mode 100644 index 0000000000..7917fb3858 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_03_49_wlcsp.h @@ -0,0 +1,889 @@ +/***************************************************************************//** +* \file gpio_psoc6_03_49_wlcsp.h +* +* \brief +* PSoC6_03 device GPIO header for 49-WLCSP package +* +* \note +* Generator version: 1.5.0.1274 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _GPIO_PSOC6_03_49_WLCSP_H_ +#define _GPIO_PSOC6_03_49_WLCSP_H_ + +/* Package type */ +enum +{ + CY_GPIO_PACKAGE_QFN, + CY_GPIO_PACKAGE_BGA, + CY_GPIO_PACKAGE_CSP, + CY_GPIO_PACKAGE_WLCSP, + CY_GPIO_PACKAGE_LQFP, + CY_GPIO_PACKAGE_TQFP, + CY_GPIO_PACKAGE_SMT, +}; + +#define CY_GPIO_PACKAGE_TYPE CY_GPIO_PACKAGE_WLCSP +#define CY_GPIO_PIN_COUNT 49u + +/* AMUXBUS Segments */ +enum +{ + AMUXBUS_SRSS_AMUXBUSA_ADFT_VDDD, + AMUXBUS_SRSS_AMUXBUSB_ADFT_VDDD, + AMUXBUS_VSSA, + AMUXBUS_VDDIO_1, + AMUXBUS_CSD0, + AMUXBUS_CSD1, + AMUXBUS_SAR, + AMUXBUS_ANALOG_VDDD, +}; + +/* AMUX Splitter Controls */ +typedef enum +{ + AMUX_SPLIT_CTL_2 = 0x0002u, /* Left = AMUXBUS_CSD1; Right = AMUXBUS_CSD0 */ + AMUX_SPLIT_CTL_3 = 0x0003u /* Left = AMUXBUS_SAR; Right = AMUXBUS_CSD1 */ +} cy_en_amux_split_t; + +/* Port List */ +/* PORT 0 (GPIO) */ +#define P0_0_PORT GPIO_PRT0 +#define P0_0_PIN 0u +#define P0_0_NUM 0u +#define P0_1_PORT GPIO_PRT0 +#define P0_1_PIN 1u +#define P0_1_NUM 1u + +/* PORT 2 (GPIO) */ +#define P2_0_PORT GPIO_PRT2 +#define P2_0_PIN 0u +#define P2_0_NUM 0u +#define P2_1_PORT GPIO_PRT2 +#define P2_1_PIN 1u +#define P2_1_NUM 1u +#define P2_2_PORT GPIO_PRT2 +#define P2_2_PIN 2u +#define P2_2_NUM 2u +#define P2_3_PORT GPIO_PRT2 +#define P2_3_PIN 3u +#define P2_3_NUM 3u +#define P2_4_PORT GPIO_PRT2 +#define P2_4_PIN 4u +#define P2_4_NUM 4u +#define P2_5_PORT GPIO_PRT2 +#define P2_5_PIN 5u +#define P2_5_NUM 5u + +/* PORT 5 (GPIO) */ +#define P5_0_PORT GPIO_PRT5 +#define P5_0_PIN 0u +#define P5_0_NUM 0u +#define P5_1_PORT GPIO_PRT5 +#define P5_1_PIN 1u +#define P5_1_NUM 1u + +/* PORT 6 (GPIO) */ +#define P6_2_PORT GPIO_PRT6 +#define P6_2_PIN 2u +#define P6_2_NUM 2u +#define P6_3_PORT GPIO_PRT6 +#define P6_3_PIN 3u +#define P6_3_NUM 3u +#define P6_4_PORT GPIO_PRT6 +#define P6_4_PIN 4u +#define P6_4_NUM 4u +#define P6_5_PORT GPIO_PRT6 +#define P6_5_PIN 5u +#define P6_5_NUM 5u +#define P6_6_PORT GPIO_PRT6 +#define P6_6_PIN 6u +#define P6_6_NUM 6u +#define P6_7_PORT GPIO_PRT6 +#define P6_7_PIN 7u +#define P6_7_NUM 7u + +/* PORT 7 (GPIO) */ +#define P7_0_PORT GPIO_PRT7 +#define P7_0_PIN 0u +#define P7_0_NUM 0u +#define P7_0_AMUXSEGMENT AMUXBUS_CSD0 +#define P7_1_PORT GPIO_PRT7 +#define P7_1_PIN 1u +#define P7_1_NUM 1u +#define P7_1_AMUXSEGMENT AMUXBUS_CSD0 +#define P7_2_PORT GPIO_PRT7 +#define P7_2_PIN 2u +#define P7_2_NUM 2u +#define P7_2_AMUXSEGMENT AMUXBUS_CSD0 +#define P7_3_PORT GPIO_PRT7 +#define P7_3_PIN 3u +#define P7_3_NUM 3u +#define P7_3_AMUXSEGMENT AMUXBUS_CSD0 +#define P7_4_PORT GPIO_PRT7 +#define P7_4_PIN 4u +#define P7_4_NUM 4u +#define P7_4_AMUXSEGMENT AMUXBUS_CSD0 + +/* PORT 9 (GPIO) */ +#define P9_0_PORT GPIO_PRT9 +#define P9_0_PIN 0u +#define P9_0_NUM 0u +#define P9_0_AMUXSEGMENT AMUXBUS_SAR +#define P9_1_PORT GPIO_PRT9 +#define P9_1_PIN 1u +#define P9_1_NUM 1u +#define P9_1_AMUXSEGMENT AMUXBUS_SAR +#define P9_2_PORT GPIO_PRT9 +#define P9_2_PIN 2u +#define P9_2_NUM 2u +#define P9_2_AMUXSEGMENT AMUXBUS_SAR +#define P9_3_PORT GPIO_PRT9 +#define P9_3_PIN 3u +#define P9_3_NUM 3u +#define P9_3_AMUXSEGMENT AMUXBUS_SAR + +/* PORT 10 (GPIO) */ +#define P10_0_PORT GPIO_PRT10 +#define P10_0_PIN 0u +#define P10_0_NUM 0u +#define P10_1_PORT GPIO_PRT10 +#define P10_1_PIN 1u +#define P10_1_NUM 1u +#define P10_2_PORT GPIO_PRT10 +#define P10_2_PIN 2u +#define P10_2_NUM 2u +#define P10_3_PORT GPIO_PRT10 +#define P10_3_PIN 3u +#define P10_3_NUM 3u +#define P10_4_PORT GPIO_PRT10 +#define P10_4_PIN 4u +#define P10_4_NUM 4u +#define P10_5_PORT GPIO_PRT10 +#define P10_5_PIN 5u +#define P10_5_NUM 5u + +/* PORT 11 (GPIO) */ +#define P11_2_PORT GPIO_PRT11 +#define P11_2_PIN 2u +#define P11_2_NUM 2u +#define P11_3_PORT GPIO_PRT11 +#define P11_3_PIN 3u +#define P11_3_NUM 3u +#define P11_4_PORT GPIO_PRT11 +#define P11_4_PIN 4u +#define P11_4_NUM 4u +#define P11_5_PORT GPIO_PRT11 +#define P11_5_PIN 5u +#define P11_5_NUM 5u +#define P11_6_PORT GPIO_PRT11 +#define P11_6_PIN 6u +#define P11_6_NUM 6u +#define P11_7_PORT GPIO_PRT11 +#define P11_7_PIN 7u +#define P11_7_NUM 7u + +/* Analog Connections */ +#define CSD_CMODPADD_PORT 7u +#define CSD_CMODPADD_PIN 1u +#define CSD_CMODPADS_PORT 7u +#define CSD_CMODPADS_PIN 1u +#define CSD_CSH_TANKPADD_PORT 7u +#define CSD_CSH_TANKPADD_PIN 2u +#define CSD_CSH_TANKPADS_PORT 7u +#define CSD_CSH_TANKPADS_PIN 2u +#define CSD_VREF_EXT_PORT 7u +#define CSD_VREF_EXT_PIN 3u +#define IOSS_ADFT0_NET_PORT 10u +#define IOSS_ADFT0_NET_PIN 0u +#define IOSS_ADFT1_NET_PORT 10u +#define IOSS_ADFT1_NET_PIN 1u +#define LPCOMP_INN_COMP1_PORT 6u +#define LPCOMP_INN_COMP1_PIN 3u +#define LPCOMP_INP_COMP1_PORT 6u +#define LPCOMP_INP_COMP1_PIN 2u +#define PASS_AREF_EXT_VREF_PORT 9u +#define PASS_AREF_EXT_VREF_PIN 3u +#define PASS_SARMUX_PADS0_PORT 10u +#define PASS_SARMUX_PADS0_PIN 0u +#define PASS_SARMUX_PADS1_PORT 10u +#define PASS_SARMUX_PADS1_PIN 1u +#define PASS_SARMUX_PADS2_PORT 10u +#define PASS_SARMUX_PADS2_PIN 2u +#define PASS_SARMUX_PADS3_PORT 10u +#define PASS_SARMUX_PADS3_PIN 3u +#define PASS_SARMUX_PADS4_PORT 10u +#define PASS_SARMUX_PADS4_PIN 4u +#define PASS_SARMUX_PADS5_PORT 10u +#define PASS_SARMUX_PADS5_PIN 5u +#define SRSS_ADFT_PIN0_PORT 10u +#define SRSS_ADFT_PIN0_PIN 0u +#define SRSS_ADFT_PIN1_PORT 10u +#define SRSS_ADFT_PIN1_PIN 1u +#define SRSS_WCO_IN_PORT 0u +#define SRSS_WCO_IN_PIN 0u +#define SRSS_WCO_OUT_PORT 0u +#define SRSS_WCO_OUT_PIN 1u + +/* HSIOM Connections */ +typedef enum +{ + /* Generic HSIOM connections */ + HSIOM_SEL_GPIO = 0, /* GPIO controls 'out' */ + HSIOM_SEL_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + HSIOM_SEL_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + HSIOM_SEL_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + HSIOM_SEL_AMUXA = 4, /* Analog mux bus A */ + HSIOM_SEL_AMUXB = 5, /* Analog mux bus B */ + HSIOM_SEL_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + HSIOM_SEL_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + HSIOM_SEL_ACT_0 = 8, /* Active functionality 0 */ + HSIOM_SEL_ACT_1 = 9, /* Active functionality 1 */ + HSIOM_SEL_ACT_2 = 10, /* Active functionality 2 */ + HSIOM_SEL_ACT_3 = 11, /* Active functionality 3 */ + HSIOM_SEL_DS_0 = 12, /* DeepSleep functionality 0 */ + HSIOM_SEL_DS_1 = 13, /* DeepSleep functionality 1 */ + HSIOM_SEL_DS_2 = 14, /* DeepSleep functionality 2 */ + HSIOM_SEL_DS_3 = 15, /* DeepSleep functionality 3 */ + HSIOM_SEL_ACT_4 = 16, /* Active functionality 4 */ + HSIOM_SEL_ACT_5 = 17, /* Active functionality 5 */ + HSIOM_SEL_ACT_6 = 18, /* Active functionality 6 */ + HSIOM_SEL_ACT_7 = 19, /* Active functionality 7 */ + HSIOM_SEL_ACT_8 = 20, /* Active functionality 8 */ + HSIOM_SEL_ACT_9 = 21, /* Active functionality 9 */ + HSIOM_SEL_ACT_10 = 22, /* Active functionality 10 */ + HSIOM_SEL_ACT_11 = 23, /* Active functionality 11 */ + HSIOM_SEL_ACT_12 = 24, /* Active functionality 12 */ + HSIOM_SEL_ACT_13 = 25, /* Active functionality 13 */ + HSIOM_SEL_ACT_14 = 26, /* Active functionality 14 */ + HSIOM_SEL_ACT_15 = 27, /* Active functionality 15 */ + HSIOM_SEL_DS_4 = 28, /* DeepSleep functionality 4 */ + HSIOM_SEL_DS_5 = 29, /* DeepSleep functionality 5 */ + HSIOM_SEL_DS_6 = 30, /* DeepSleep functionality 6 */ + HSIOM_SEL_DS_7 = 31, /* DeepSleep functionality 7 */ + + /* P0.0 */ + P0_0_GPIO = 0, /* GPIO controls 'out' */ + P0_0_AMUXA = 4, /* Analog mux bus A */ + P0_0_AMUXB = 5, /* Analog mux bus B */ + P0_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P0_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P0_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:0 */ + P0_0_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:0 */ + P0_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:0 */ + P0_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:0 */ + P0_0_LCD_COM0 = 12, /* Digital Deep Sleep - lcd.com[0]:0 */ + P0_0_LCD_SEG0 = 13, /* Digital Deep Sleep - lcd.seg[0]:0 */ + P0_0_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:0 */ + P0_0_SCB0_SPI_SELECT1 = 20, /* Digital Active - scb[0].spi_select1:0 */ + P0_0_PERI_TR_IO_INPUT0 = 24, /* Digital Active - peri.tr_io_input[0]:0 */ + + /* P0.1 */ + P0_1_GPIO = 0, /* GPIO controls 'out' */ + P0_1_AMUXA = 4, /* Analog mux bus A */ + P0_1_AMUXB = 5, /* Analog mux bus B */ + P0_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P0_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P0_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:0 */ + P0_1_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:0 */ + P0_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:1 */ + P0_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:1 */ + P0_1_LCD_COM1 = 12, /* Digital Deep Sleep - lcd.com[1]:0 */ + P0_1_LCD_SEG1 = 13, /* Digital Deep Sleep - lcd.seg[1]:0 */ + P0_1_SCB0_SPI_SELECT2 = 20, /* Digital Active - scb[0].spi_select2:0 */ + P0_1_PERI_TR_IO_INPUT1 = 24, /* Digital Active - peri.tr_io_input[1]:0 */ + P0_1_CPUSS_SWJ_TRSTN = 29, /* Digital Deep Sleep - cpuss.swj_trstn */ + + /* P2.0 */ + P2_0_GPIO = 0, /* GPIO controls 'out' */ + P2_0_AMUXA = 4, /* Analog mux bus A */ + P2_0_AMUXB = 5, /* Analog mux bus B */ + P2_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P2_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P2_0_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:0 */ + P2_0_TCPWM1_LINE3 = 9, /* Digital Active - tcpwm[1].line[3]:0 */ + P2_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:6 */ + P2_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:6 */ + P2_0_LCD_COM6 = 12, /* Digital Deep Sleep - lcd.com[6]:0 */ + P2_0_LCD_SEG6 = 13, /* Digital Deep Sleep - lcd.seg[6]:0 */ + P2_0_SCB1_UART_RX = 18, /* Digital Active - scb[1].uart_rx:0 */ + P2_0_SCB1_I2C_SCL = 19, /* Digital Active - scb[1].i2c_scl:0 */ + P2_0_SCB1_SPI_MOSI = 20, /* Digital Active - scb[1].spi_mosi:0 */ + P2_0_PERI_TR_IO_INPUT4 = 24, /* Digital Active - peri.tr_io_input[4]:0 */ + P2_0_SDHC0_CARD_DAT_3TO00 = 26, /* Digital Active - sdhc[0].card_dat_3to0[0] */ + + /* P2.1 */ + P2_1_GPIO = 0, /* GPIO controls 'out' */ + P2_1_AMUXA = 4, /* Analog mux bus A */ + P2_1_AMUXB = 5, /* Analog mux bus B */ + P2_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P2_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P2_1_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:0 */ + P2_1_TCPWM1_LINE_COMPL3 = 9, /* Digital Active - tcpwm[1].line_compl[3]:0 */ + P2_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:7 */ + P2_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:7 */ + P2_1_LCD_COM7 = 12, /* Digital Deep Sleep - lcd.com[7]:0 */ + P2_1_LCD_SEG7 = 13, /* Digital Deep Sleep - lcd.seg[7]:0 */ + P2_1_SCB1_UART_TX = 18, /* Digital Active - scb[1].uart_tx:0 */ + P2_1_SCB1_I2C_SDA = 19, /* Digital Active - scb[1].i2c_sda:0 */ + P2_1_SCB1_SPI_MISO = 20, /* Digital Active - scb[1].spi_miso:0 */ + P2_1_PERI_TR_IO_INPUT5 = 24, /* Digital Active - peri.tr_io_input[5]:0 */ + P2_1_SDHC0_CARD_DAT_3TO01 = 26, /* Digital Active - sdhc[0].card_dat_3to0[1] */ + + /* P2.2 */ + P2_2_GPIO = 0, /* GPIO controls 'out' */ + P2_2_AMUXA = 4, /* Analog mux bus A */ + P2_2_AMUXB = 5, /* Analog mux bus B */ + P2_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P2_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P2_2_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:1 */ + P2_2_TCPWM1_LINE4 = 9, /* Digital Active - tcpwm[1].line[4]:0 */ + P2_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:8 */ + P2_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:8 */ + P2_2_LCD_COM8 = 12, /* Digital Deep Sleep - lcd.com[8]:0 */ + P2_2_LCD_SEG8 = 13, /* Digital Deep Sleep - lcd.seg[8]:0 */ + P2_2_SCB1_UART_RTS = 18, /* Digital Active - scb[1].uart_rts:0 */ + P2_2_SCB1_SPI_CLK = 20, /* Digital Active - scb[1].spi_clk:0 */ + P2_2_SDHC0_CARD_DAT_3TO02 = 26, /* Digital Active - sdhc[0].card_dat_3to0[2] */ + + /* P2.3 */ + P2_3_GPIO = 0, /* GPIO controls 'out' */ + P2_3_AMUXA = 4, /* Analog mux bus A */ + P2_3_AMUXB = 5, /* Analog mux bus B */ + P2_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P2_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P2_3_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:1 */ + P2_3_TCPWM1_LINE_COMPL4 = 9, /* Digital Active - tcpwm[1].line_compl[4]:0 */ + P2_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:9 */ + P2_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:9 */ + P2_3_LCD_COM9 = 12, /* Digital Deep Sleep - lcd.com[9]:0 */ + P2_3_LCD_SEG9 = 13, /* Digital Deep Sleep - lcd.seg[9]:0 */ + P2_3_SCB1_UART_CTS = 18, /* Digital Active - scb[1].uart_cts:0 */ + P2_3_SCB1_SPI_SELECT0 = 20, /* Digital Active - scb[1].spi_select0:0 */ + P2_3_SDHC0_CARD_DAT_3TO03 = 26, /* Digital Active - sdhc[0].card_dat_3to0[3] */ + + /* P2.4 */ + P2_4_GPIO = 0, /* GPIO controls 'out' */ + P2_4_AMUXA = 4, /* Analog mux bus A */ + P2_4_AMUXB = 5, /* Analog mux bus B */ + P2_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P2_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P2_4_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:1 */ + P2_4_TCPWM1_LINE5 = 9, /* Digital Active - tcpwm[1].line[5]:0 */ + P2_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:10 */ + P2_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:10 */ + P2_4_LCD_COM10 = 12, /* Digital Deep Sleep - lcd.com[10]:0 */ + P2_4_LCD_SEG10 = 13, /* Digital Deep Sleep - lcd.seg[10]:0 */ + P2_4_SCB1_SPI_SELECT1 = 20, /* Digital Active - scb[1].spi_select1:0 */ + P2_4_SDHC0_CARD_CMD = 26, /* Digital Active - sdhc[0].card_cmd */ + + /* P2.5 */ + P2_5_GPIO = 0, /* GPIO controls 'out' */ + P2_5_AMUXA = 4, /* Analog mux bus A */ + P2_5_AMUXB = 5, /* Analog mux bus B */ + P2_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P2_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P2_5_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:1 */ + P2_5_TCPWM1_LINE_COMPL5 = 9, /* Digital Active - tcpwm[1].line_compl[5]:0 */ + P2_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:11 */ + P2_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:11 */ + P2_5_LCD_COM11 = 12, /* Digital Deep Sleep - lcd.com[11]:0 */ + P2_5_LCD_SEG11 = 13, /* Digital Deep Sleep - lcd.seg[11]:0 */ + P2_5_SCB1_SPI_SELECT2 = 20, /* Digital Active - scb[1].spi_select2:0 */ + P2_5_SDHC0_CLK_CARD = 26, /* Digital Active - sdhc[0].clk_card */ + + /* P5.0 */ + P5_0_GPIO = 0, /* GPIO controls 'out' */ + P5_0_AMUXA = 4, /* Analog mux bus A */ + P5_0_AMUXB = 5, /* Analog mux bus B */ + P5_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P5_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P5_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:2 */ + P5_0_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:1 */ + P5_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:16 */ + P5_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:16 */ + P5_0_LCD_COM16 = 12, /* Digital Deep Sleep - lcd.com[16]:0 */ + P5_0_LCD_SEG16 = 13, /* Digital Deep Sleep - lcd.seg[16]:0 */ + P5_0_SCB5_UART_RX = 18, /* Digital Active - scb[5].uart_rx:1 */ + P5_0_SCB5_I2C_SCL = 19, /* Digital Active - scb[5].i2c_scl:1 */ + P5_0_SCB5_SPI_MOSI = 20, /* Digital Active - scb[5].spi_mosi:1 */ + P5_0_CANFD0_TTCAN_RX0 = 22, /* Digital Active - canfd[0].ttcan_rx[0] */ + P5_0_PERI_TR_IO_INPUT10 = 24, /* Digital Active - peri.tr_io_input[10]:0 */ + + /* P5.1 */ + P5_1_GPIO = 0, /* GPIO controls 'out' */ + P5_1_AMUXA = 4, /* Analog mux bus A */ + P5_1_AMUXB = 5, /* Analog mux bus B */ + P5_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P5_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P5_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:2 */ + P5_1_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:1 */ + P5_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:17 */ + P5_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:17 */ + P5_1_LCD_COM17 = 12, /* Digital Deep Sleep - lcd.com[17]:0 */ + P5_1_LCD_SEG17 = 13, /* Digital Deep Sleep - lcd.seg[17]:0 */ + P5_1_SCB5_UART_TX = 18, /* Digital Active - scb[5].uart_tx:1 */ + P5_1_SCB5_I2C_SDA = 19, /* Digital Active - scb[5].i2c_sda:1 */ + P5_1_SCB5_SPI_MISO = 20, /* Digital Active - scb[5].spi_miso:1 */ + P5_1_CANFD0_TTCAN_TX0 = 22, /* Digital Active - canfd[0].ttcan_tx[0] */ + P5_1_PERI_TR_IO_INPUT11 = 24, /* Digital Active - peri.tr_io_input[11]:0 */ + + /* P6.2 */ + P6_2_GPIO = 0, /* GPIO controls 'out' */ + P6_2_AMUXA = 4, /* Analog mux bus A */ + P6_2_AMUXB = 5, /* Analog mux bus B */ + P6_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P6_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P6_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:2 */ + P6_2_TCPWM1_LINE3 = 9, /* Digital Active - tcpwm[1].line[3]:1 */ + P6_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:22 */ + P6_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:22 */ + P6_2_LCD_COM22 = 12, /* Digital Deep Sleep - lcd.com[22]:0 */ + P6_2_LCD_SEG22 = 13, /* Digital Deep Sleep - lcd.seg[22]:0 */ + P6_2_SCB3_UART_RTS = 18, /* Digital Active - scb[3].uart_rts:0 */ + P6_2_SCB3_SPI_CLK = 20, /* Digital Active - scb[3].spi_clk:0 */ + + /* P6.3 */ + P6_3_GPIO = 0, /* GPIO controls 'out' */ + P6_3_AMUXA = 4, /* Analog mux bus A */ + P6_3_AMUXB = 5, /* Analog mux bus B */ + P6_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P6_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P6_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:2 */ + P6_3_TCPWM1_LINE_COMPL3 = 9, /* Digital Active - tcpwm[1].line_compl[3]:1 */ + P6_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:23 */ + P6_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:23 */ + P6_3_LCD_COM23 = 12, /* Digital Deep Sleep - lcd.com[23]:0 */ + P6_3_LCD_SEG23 = 13, /* Digital Deep Sleep - lcd.seg[23]:0 */ + P6_3_SCB3_UART_CTS = 18, /* Digital Active - scb[3].uart_cts:0 */ + P6_3_SCB3_SPI_SELECT0 = 20, /* Digital Active - scb[3].spi_select0:0 */ + + /* P6.4 */ + P6_4_GPIO = 0, /* GPIO controls 'out' */ + P6_4_AMUXA = 4, /* Analog mux bus A */ + P6_4_AMUXB = 5, /* Analog mux bus B */ + P6_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P6_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P6_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:3 */ + P6_4_TCPWM1_LINE4 = 9, /* Digital Active - tcpwm[1].line[4]:1 */ + P6_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:24 */ + P6_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:24 */ + P6_4_LCD_COM24 = 12, /* Digital Deep Sleep - lcd.com[24]:0 */ + P6_4_LCD_SEG24 = 13, /* Digital Deep Sleep - lcd.seg[24]:0 */ + P6_4_SCB6_I2C_SCL = 14, /* Digital Deep Sleep - scb[6].i2c_scl:0 */ + P6_4_PERI_TR_IO_INPUT12 = 24, /* Digital Active - peri.tr_io_input[12]:0 */ + P6_4_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:1 */ + P6_4_CPUSS_SWJ_SWO_TDO = 29, /* Digital Deep Sleep - cpuss.swj_swo_tdo */ + P6_4_SCB6_SPI_MOSI = 30, /* Digital Deep Sleep - scb[6].spi_mosi:0 */ + P6_4_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:0 */ + + /* P6.5 */ + P6_5_GPIO = 0, /* GPIO controls 'out' */ + P6_5_AMUXA = 4, /* Analog mux bus A */ + P6_5_AMUXB = 5, /* Analog mux bus B */ + P6_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P6_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P6_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:3 */ + P6_5_TCPWM1_LINE_COMPL4 = 9, /* Digital Active - tcpwm[1].line_compl[4]:1 */ + P6_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:25 */ + P6_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:25 */ + P6_5_LCD_COM25 = 12, /* Digital Deep Sleep - lcd.com[25]:0 */ + P6_5_LCD_SEG25 = 13, /* Digital Deep Sleep - lcd.seg[25]:0 */ + P6_5_SCB6_I2C_SDA = 14, /* Digital Deep Sleep - scb[6].i2c_sda:0 */ + P6_5_PERI_TR_IO_INPUT13 = 24, /* Digital Active - peri.tr_io_input[13]:0 */ + P6_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:1 */ + P6_5_CPUSS_SWJ_SWDOE_TDI = 29, /* Digital Deep Sleep - cpuss.swj_swdoe_tdi */ + P6_5_SCB6_SPI_MISO = 30, /* Digital Deep Sleep - scb[6].spi_miso:0 */ + P6_5_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:0 */ + + /* P6.6 */ + P6_6_GPIO = 0, /* GPIO controls 'out' */ + P6_6_AMUXA = 4, /* Analog mux bus A */ + P6_6_AMUXB = 5, /* Analog mux bus B */ + P6_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P6_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P6_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:3 */ + P6_6_TCPWM1_LINE5 = 9, /* Digital Active - tcpwm[1].line[5]:1 */ + P6_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:26 */ + P6_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:26 */ + P6_6_LCD_COM26 = 12, /* Digital Deep Sleep - lcd.com[26]:0 */ + P6_6_LCD_SEG26 = 13, /* Digital Deep Sleep - lcd.seg[26]:0 */ + P6_6_CPUSS_SWJ_SWDIO_TMS = 29, /* Digital Deep Sleep - cpuss.swj_swdio_tms */ + P6_6_SCB6_SPI_CLK = 30, /* Digital Deep Sleep - scb[6].spi_clk:0 */ + + /* P6.7 */ + P6_7_GPIO = 0, /* GPIO controls 'out' */ + P6_7_AMUXA = 4, /* Analog mux bus A */ + P6_7_AMUXB = 5, /* Analog mux bus B */ + P6_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P6_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P6_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:3 */ + P6_7_TCPWM1_LINE_COMPL5 = 9, /* Digital Active - tcpwm[1].line_compl[5]:1 */ + P6_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:27 */ + P6_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:27 */ + P6_7_LCD_COM27 = 12, /* Digital Deep Sleep - lcd.com[27]:0 */ + P6_7_LCD_SEG27 = 13, /* Digital Deep Sleep - lcd.seg[27]:0 */ + P6_7_CPUSS_SWJ_SWCLK_TCLK = 29, /* Digital Deep Sleep - cpuss.swj_swclk_tclk */ + P6_7_SCB6_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[6].spi_select0:0 */ + + /* P7.0 */ + P7_0_GPIO = 0, /* GPIO controls 'out' */ + P7_0_AMUXA = 4, /* Analog mux bus A */ + P7_0_AMUXB = 5, /* Analog mux bus B */ + P7_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P7_0_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:3 */ + P7_0_TCPWM1_LINE6 = 9, /* Digital Active - tcpwm[1].line[6]:1 */ + P7_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:28 */ + P7_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:28 */ + P7_0_LCD_COM28 = 12, /* Digital Deep Sleep - lcd.com[28]:0 */ + P7_0_LCD_SEG28 = 13, /* Digital Deep Sleep - lcd.seg[28]:0 */ + P7_0_SCB4_UART_RX = 18, /* Digital Active - scb[4].uart_rx:1 */ + P7_0_SCB4_I2C_SCL = 19, /* Digital Active - scb[4].i2c_scl:1 */ + P7_0_SCB4_SPI_MOSI = 20, /* Digital Active - scb[4].spi_mosi:1 */ + P7_0_PERI_TR_IO_INPUT14 = 24, /* Digital Active - peri.tr_io_input[14]:0 */ + P7_0_CPUSS_TRACE_CLOCK = 26, /* Digital Active - cpuss.trace_clock */ + + /* P7.1 */ + P7_1_GPIO = 0, /* GPIO controls 'out' */ + P7_1_AMUXA = 4, /* Analog mux bus A */ + P7_1_AMUXB = 5, /* Analog mux bus B */ + P7_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P7_1_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:3 */ + P7_1_TCPWM1_LINE_COMPL6 = 9, /* Digital Active - tcpwm[1].line_compl[6]:1 */ + P7_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:29 */ + P7_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:29 */ + P7_1_LCD_COM29 = 12, /* Digital Deep Sleep - lcd.com[29]:0 */ + P7_1_LCD_SEG29 = 13, /* Digital Deep Sleep - lcd.seg[29]:0 */ + P7_1_SCB4_UART_TX = 18, /* Digital Active - scb[4].uart_tx:1 */ + P7_1_SCB4_I2C_SDA = 19, /* Digital Active - scb[4].i2c_sda:1 */ + P7_1_SCB4_SPI_MISO = 20, /* Digital Active - scb[4].spi_miso:1 */ + P7_1_PERI_TR_IO_INPUT15 = 24, /* Digital Active - peri.tr_io_input[15]:0 */ + + /* P7.2 */ + P7_2_GPIO = 0, /* GPIO controls 'out' */ + P7_2_AMUXA = 4, /* Analog mux bus A */ + P7_2_AMUXB = 5, /* Analog mux bus B */ + P7_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P7_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:3 */ + P7_2_TCPWM1_LINE7 = 9, /* Digital Active - tcpwm[1].line[7]:1 */ + P7_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:30 */ + P7_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:30 */ + P7_2_LCD_COM30 = 12, /* Digital Deep Sleep - lcd.com[30]:0 */ + P7_2_LCD_SEG30 = 13, /* Digital Deep Sleep - lcd.seg[30]:0 */ + P7_2_SCB4_UART_RTS = 18, /* Digital Active - scb[4].uart_rts:1 */ + P7_2_SCB4_SPI_CLK = 20, /* Digital Active - scb[4].spi_clk:1 */ + + /* P7.3 */ + P7_3_GPIO = 0, /* GPIO controls 'out' */ + P7_3_AMUXA = 4, /* Analog mux bus A */ + P7_3_AMUXB = 5, /* Analog mux bus B */ + P7_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P7_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:3 */ + P7_3_TCPWM1_LINE_COMPL7 = 9, /* Digital Active - tcpwm[1].line_compl[7]:1 */ + P7_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:31 */ + P7_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:31 */ + P7_3_LCD_COM31 = 12, /* Digital Deep Sleep - lcd.com[31]:0 */ + P7_3_LCD_SEG31 = 13, /* Digital Deep Sleep - lcd.seg[31]:0 */ + P7_3_SCB4_UART_CTS = 18, /* Digital Active - scb[4].uart_cts:1 */ + P7_3_SCB4_SPI_SELECT0 = 20, /* Digital Active - scb[4].spi_select0:1 */ + + /* P7.4 */ + P7_4_GPIO = 0, /* GPIO controls 'out' */ + P7_4_AMUXA = 4, /* Analog mux bus A */ + P7_4_AMUXB = 5, /* Analog mux bus B */ + P7_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P7_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:4 */ + P7_4_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:2 */ + P7_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:32 */ + P7_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:32 */ + P7_4_LCD_COM32 = 12, /* Digital Deep Sleep - lcd.com[32]:0 */ + P7_4_LCD_SEG32 = 13, /* Digital Deep Sleep - lcd.seg[32]:0 */ + P7_4_SCB4_SPI_SELECT1 = 20, /* Digital Active - scb[4].spi_select1:1 */ + P7_4_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:2 */ + + /* P9.0 */ + P9_0_GPIO = 0, /* GPIO controls 'out' */ + P9_0_AMUXA = 4, /* Analog mux bus A */ + P9_0_AMUXB = 5, /* Analog mux bus B */ + P9_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P9_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P9_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:5 */ + P9_0_TCPWM1_LINE4 = 9, /* Digital Active - tcpwm[1].line[4]:2 */ + P9_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:40 */ + P9_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:40 */ + P9_0_LCD_COM40 = 12, /* Digital Deep Sleep - lcd.com[40]:0 */ + P9_0_LCD_SEG40 = 13, /* Digital Deep Sleep - lcd.seg[40]:0 */ + P9_0_SCB2_UART_RX = 18, /* Digital Active - scb[2].uart_rx:0 */ + P9_0_SCB2_I2C_SCL = 19, /* Digital Active - scb[2].i2c_scl:0 */ + P9_0_SCB2_SPI_MOSI = 20, /* Digital Active - scb[2].spi_mosi:0 */ + P9_0_PERI_TR_IO_INPUT18 = 24, /* Digital Active - peri.tr_io_input[18]:0 */ + P9_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:0 */ + + /* P9.1 */ + P9_1_GPIO = 0, /* GPIO controls 'out' */ + P9_1_AMUXA = 4, /* Analog mux bus A */ + P9_1_AMUXB = 5, /* Analog mux bus B */ + P9_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P9_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P9_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:5 */ + P9_1_TCPWM1_LINE_COMPL4 = 9, /* Digital Active - tcpwm[1].line_compl[4]:2 */ + P9_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:41 */ + P9_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:41 */ + P9_1_LCD_COM41 = 12, /* Digital Deep Sleep - lcd.com[41]:0 */ + P9_1_LCD_SEG41 = 13, /* Digital Deep Sleep - lcd.seg[41]:0 */ + P9_1_SCB2_UART_TX = 18, /* Digital Active - scb[2].uart_tx:0 */ + P9_1_SCB2_I2C_SDA = 19, /* Digital Active - scb[2].i2c_sda:0 */ + P9_1_SCB2_SPI_MISO = 20, /* Digital Active - scb[2].spi_miso:0 */ + P9_1_PERI_TR_IO_INPUT19 = 24, /* Digital Active - peri.tr_io_input[19]:0 */ + P9_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:0 */ + P9_1_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:1 */ + + /* P9.2 */ + P9_2_GPIO = 0, /* GPIO controls 'out' */ + P9_2_AMUXA = 4, /* Analog mux bus A */ + P9_2_AMUXB = 5, /* Analog mux bus B */ + P9_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P9_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P9_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:5 */ + P9_2_TCPWM1_LINE5 = 9, /* Digital Active - tcpwm[1].line[5]:2 */ + P9_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:42 */ + P9_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:42 */ + P9_2_LCD_COM42 = 12, /* Digital Deep Sleep - lcd.com[42]:0 */ + P9_2_LCD_SEG42 = 13, /* Digital Deep Sleep - lcd.seg[42]:0 */ + P9_2_SCB2_UART_RTS = 18, /* Digital Active - scb[2].uart_rts:0 */ + P9_2_SCB2_SPI_CLK = 20, /* Digital Active - scb[2].spi_clk:0 */ + P9_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:0 */ + + /* P9.3 */ + P9_3_GPIO = 0, /* GPIO controls 'out' */ + P9_3_AMUXA = 4, /* Analog mux bus A */ + P9_3_AMUXB = 5, /* Analog mux bus B */ + P9_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P9_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P9_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:5 */ + P9_3_TCPWM1_LINE_COMPL5 = 9, /* Digital Active - tcpwm[1].line_compl[5]:2 */ + P9_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:43 */ + P9_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:43 */ + P9_3_LCD_COM43 = 12, /* Digital Deep Sleep - lcd.com[43]:0 */ + P9_3_LCD_SEG43 = 13, /* Digital Deep Sleep - lcd.seg[43]:0 */ + P9_3_SCB2_UART_CTS = 18, /* Digital Active - scb[2].uart_cts:0 */ + P9_3_SCB2_SPI_SELECT0 = 20, /* Digital Active - scb[2].spi_select0:0 */ + P9_3_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:0 */ + P9_3_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:1 */ + + /* P10.0 */ + P10_0_GPIO = 0, /* GPIO controls 'out' */ + P10_0_AMUXA = 4, /* Analog mux bus A */ + P10_0_AMUXB = 5, /* Analog mux bus B */ + P10_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P10_0_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:5 */ + P10_0_TCPWM1_LINE6 = 9, /* Digital Active - tcpwm[1].line[6]:2 */ + P10_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:44 */ + P10_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:44 */ + P10_0_LCD_COM44 = 12, /* Digital Deep Sleep - lcd.com[44]:0 */ + P10_0_LCD_SEG44 = 13, /* Digital Deep Sleep - lcd.seg[44]:0 */ + P10_0_SCB1_UART_RX = 18, /* Digital Active - scb[1].uart_rx:1 */ + P10_0_SCB1_I2C_SCL = 19, /* Digital Active - scb[1].i2c_scl:1 */ + P10_0_SCB1_SPI_MOSI = 20, /* Digital Active - scb[1].spi_mosi:1 */ + P10_0_PERI_TR_IO_INPUT20 = 24, /* Digital Active - peri.tr_io_input[20]:0 */ + P10_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:1 */ + + /* P10.1 */ + P10_1_GPIO = 0, /* GPIO controls 'out' */ + P10_1_AMUXA = 4, /* Analog mux bus A */ + P10_1_AMUXB = 5, /* Analog mux bus B */ + P10_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P10_1_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:5 */ + P10_1_TCPWM1_LINE_COMPL6 = 9, /* Digital Active - tcpwm[1].line_compl[6]:2 */ + P10_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:45 */ + P10_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:45 */ + P10_1_LCD_COM45 = 12, /* Digital Deep Sleep - lcd.com[45]:0 */ + P10_1_LCD_SEG45 = 13, /* Digital Deep Sleep - lcd.seg[45]:0 */ + P10_1_SCB1_UART_TX = 18, /* Digital Active - scb[1].uart_tx:1 */ + P10_1_SCB1_I2C_SDA = 19, /* Digital Active - scb[1].i2c_sda:1 */ + P10_1_SCB1_SPI_MISO = 20, /* Digital Active - scb[1].spi_miso:1 */ + P10_1_PERI_TR_IO_INPUT21 = 24, /* Digital Active - peri.tr_io_input[21]:0 */ + P10_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:1 */ + + /* P10.2 */ + P10_2_GPIO = 0, /* GPIO controls 'out' */ + P10_2_AMUXA = 4, /* Analog mux bus A */ + P10_2_AMUXB = 5, /* Analog mux bus B */ + P10_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P10_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:5 */ + P10_2_TCPWM1_LINE7 = 9, /* Digital Active - tcpwm[1].line[7]:2 */ + P10_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:46 */ + P10_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:46 */ + P10_2_LCD_COM46 = 12, /* Digital Deep Sleep - lcd.com[46]:0 */ + P10_2_LCD_SEG46 = 13, /* Digital Deep Sleep - lcd.seg[46]:0 */ + P10_2_SCB1_UART_RTS = 18, /* Digital Active - scb[1].uart_rts:1 */ + P10_2_SCB1_SPI_CLK = 20, /* Digital Active - scb[1].spi_clk:1 */ + P10_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:1 */ + + /* P10.3 */ + P10_3_GPIO = 0, /* GPIO controls 'out' */ + P10_3_AMUXA = 4, /* Analog mux bus A */ + P10_3_AMUXB = 5, /* Analog mux bus B */ + P10_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P10_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:5 */ + P10_3_TCPWM1_LINE_COMPL7 = 9, /* Digital Active - tcpwm[1].line_compl[7]:2 */ + P10_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:47 */ + P10_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:47 */ + P10_3_LCD_COM47 = 12, /* Digital Deep Sleep - lcd.com[47]:0 */ + P10_3_LCD_SEG47 = 13, /* Digital Deep Sleep - lcd.seg[47]:0 */ + P10_3_SCB1_UART_CTS = 18, /* Digital Active - scb[1].uart_cts:1 */ + P10_3_SCB1_SPI_SELECT0 = 20, /* Digital Active - scb[1].spi_select0:1 */ + P10_3_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:1 */ + + /* P10.4 */ + P10_4_GPIO = 0, /* GPIO controls 'out' */ + P10_4_AMUXA = 4, /* Analog mux bus A */ + P10_4_AMUXB = 5, /* Analog mux bus B */ + P10_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P10_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:6 */ + P10_4_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:3 */ + P10_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:48 */ + P10_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:48 */ + P10_4_LCD_COM48 = 12, /* Digital Deep Sleep - lcd.com[48]:0 */ + P10_4_LCD_SEG48 = 13, /* Digital Deep Sleep - lcd.seg[48]:0 */ + P10_4_SCB1_SPI_SELECT1 = 20, /* Digital Active - scb[1].spi_select1:1 */ + + /* P10.5 */ + P10_5_GPIO = 0, /* GPIO controls 'out' */ + P10_5_AMUXA = 4, /* Analog mux bus A */ + P10_5_AMUXB = 5, /* Analog mux bus B */ + P10_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P10_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:6 */ + P10_5_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:3 */ + P10_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:49 */ + P10_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:49 */ + P10_5_LCD_COM49 = 12, /* Digital Deep Sleep - lcd.com[49]:0 */ + P10_5_LCD_SEG49 = 13, /* Digital Deep Sleep - lcd.seg[49]:0 */ + P10_5_SCB1_SPI_SELECT2 = 20, /* Digital Active - scb[1].spi_select2:1 */ + + /* P11.2 */ + P11_2_GPIO = 0, /* GPIO controls 'out' */ + P11_2_AMUXA = 4, /* Analog mux bus A */ + P11_2_AMUXB = 5, /* Analog mux bus B */ + P11_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P11_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P11_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:6 */ + P11_2_TCPWM1_LINE3 = 9, /* Digital Active - tcpwm[1].line[3]:3 */ + P11_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:54 */ + P11_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:54 */ + P11_2_LCD_COM54 = 12, /* Digital Deep Sleep - lcd.com[54]:0 */ + P11_2_LCD_SEG54 = 13, /* Digital Deep Sleep - lcd.seg[54]:0 */ + P11_2_SMIF_SPI_SELECT0 = 17, /* Digital Active - smif.spi_select0 */ + P11_2_SCB5_UART_RTS = 18, /* Digital Active - scb[5].uart_rts:0 */ + P11_2_SCB5_SPI_CLK = 20, /* Digital Active - scb[5].spi_clk:0 */ + + /* P11.3 */ + P11_3_GPIO = 0, /* GPIO controls 'out' */ + P11_3_AMUXA = 4, /* Analog mux bus A */ + P11_3_AMUXB = 5, /* Analog mux bus B */ + P11_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P11_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P11_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:6 */ + P11_3_TCPWM1_LINE_COMPL3 = 9, /* Digital Active - tcpwm[1].line_compl[3]:3 */ + P11_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:55 */ + P11_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:55 */ + P11_3_LCD_COM55 = 12, /* Digital Deep Sleep - lcd.com[55]:0 */ + P11_3_LCD_SEG55 = 13, /* Digital Deep Sleep - lcd.seg[55]:0 */ + P11_3_SMIF_SPI_DATA3 = 17, /* Digital Active - smif.spi_data3 */ + P11_3_SCB5_UART_CTS = 18, /* Digital Active - scb[5].uart_cts:0 */ + P11_3_SCB5_SPI_SELECT0 = 20, /* Digital Active - scb[5].spi_select0:0 */ + P11_3_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:0 */ + + /* P11.4 */ + P11_4_GPIO = 0, /* GPIO controls 'out' */ + P11_4_AMUXA = 4, /* Analog mux bus A */ + P11_4_AMUXB = 5, /* Analog mux bus B */ + P11_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P11_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P11_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:7 */ + P11_4_TCPWM1_LINE4 = 9, /* Digital Active - tcpwm[1].line[4]:3 */ + P11_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:56 */ + P11_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:56 */ + P11_4_LCD_COM56 = 12, /* Digital Deep Sleep - lcd.com[56]:0 */ + P11_4_LCD_SEG56 = 13, /* Digital Deep Sleep - lcd.seg[56]:0 */ + P11_4_SMIF_SPI_DATA2 = 17, /* Digital Active - smif.spi_data2 */ + P11_4_SCB5_SPI_SELECT1 = 20, /* Digital Active - scb[5].spi_select1:0 */ + P11_4_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:0 */ + + /* P11.5 */ + P11_5_GPIO = 0, /* GPIO controls 'out' */ + P11_5_AMUXA = 4, /* Analog mux bus A */ + P11_5_AMUXB = 5, /* Analog mux bus B */ + P11_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P11_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P11_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:7 */ + P11_5_TCPWM1_LINE_COMPL4 = 9, /* Digital Active - tcpwm[1].line_compl[4]:3 */ + P11_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:57 */ + P11_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:57 */ + P11_5_LCD_COM57 = 12, /* Digital Deep Sleep - lcd.com[57]:0 */ + P11_5_LCD_SEG57 = 13, /* Digital Deep Sleep - lcd.seg[57]:0 */ + P11_5_SMIF_SPI_DATA1 = 17, /* Digital Active - smif.spi_data1 */ + P11_5_SCB5_SPI_SELECT2 = 20, /* Digital Active - scb[5].spi_select2:0 */ + + /* P11.6 */ + P11_6_GPIO = 0, /* GPIO controls 'out' */ + P11_6_AMUXA = 4, /* Analog mux bus A */ + P11_6_AMUXB = 5, /* Analog mux bus B */ + P11_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P11_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P11_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:7 */ + P11_6_TCPWM1_LINE5 = 9, /* Digital Active - tcpwm[1].line[5]:3 */ + P11_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:58 */ + P11_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:58 */ + P11_6_LCD_COM58 = 12, /* Digital Deep Sleep - lcd.com[58]:0 */ + P11_6_LCD_SEG58 = 13, /* Digital Deep Sleep - lcd.seg[58]:0 */ + P11_6_SMIF_SPI_DATA0 = 17, /* Digital Active - smif.spi_data0 */ + P11_6_SCB5_SPI_SELECT3 = 20, /* Digital Active - scb[5].spi_select3:0 */ + + /* P11.7 */ + P11_7_GPIO = 0, /* GPIO controls 'out' */ + P11_7_AMUXA = 4, /* Analog mux bus A */ + P11_7_AMUXB = 5, /* Analog mux bus B */ + P11_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P11_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P11_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:7 */ + P11_7_TCPWM1_LINE_COMPL5 = 9, /* Digital Active - tcpwm[1].line_compl[5]:3 */ + P11_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:59 */ + P11_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:59 */ + P11_7_LCD_COM59 = 12, /* Digital Deep Sleep - lcd.com[59]:0 */ + P11_7_LCD_SEG59 = 13, /* Digital Deep Sleep - lcd.seg[59]:0 */ + P11_7_SMIF_SPI_CLK = 17 /* Digital Active - smif.spi_clk */ +} en_hsiom_sel_t; + +#endif /* _GPIO_PSOC6_03_49_WLCSP_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_03_68_qfn.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_03_68_qfn.h new file mode 100644 index 0000000000..79e3c4c5cd --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_03_68_qfn.h @@ -0,0 +1,1227 @@ +/***************************************************************************//** +* \file gpio_psoc6_03_68_qfn.h +* +* \brief +* PSoC6_03 device GPIO header for 68-QFN package +* +* \note +* Generator version: 1.5.0.1274 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _GPIO_PSOC6_03_68_QFN_H_ +#define _GPIO_PSOC6_03_68_QFN_H_ + +/* Package type */ +enum +{ + CY_GPIO_PACKAGE_QFN, + CY_GPIO_PACKAGE_BGA, + CY_GPIO_PACKAGE_CSP, + CY_GPIO_PACKAGE_WLCSP, + CY_GPIO_PACKAGE_LQFP, + CY_GPIO_PACKAGE_TQFP, + CY_GPIO_PACKAGE_SMT, +}; + +#define CY_GPIO_PACKAGE_TYPE CY_GPIO_PACKAGE_QFN +#define CY_GPIO_PIN_COUNT 68u + +/* AMUXBUS Segments */ +enum +{ + AMUXBUS_SRSS_AMUXBUSA_ADFT_VDDD, + AMUXBUS_SRSS_AMUXBUSB_ADFT_VDDD, + AMUXBUS_VSSA, + AMUXBUS_VDDIO_1, + AMUXBUS_CSD0, + AMUXBUS_CSD1, + AMUXBUS_SAR, + AMUXBUS_ANALOG_VDDD, +}; + +/* AMUX Splitter Controls */ +typedef enum +{ + AMUX_SPLIT_CTL_2 = 0x0002u, /* Left = AMUXBUS_CSD1; Right = AMUXBUS_CSD0 */ + AMUX_SPLIT_CTL_3 = 0x0003u /* Left = AMUXBUS_SAR; Right = AMUXBUS_CSD1 */ +} cy_en_amux_split_t; + +/* Port List */ +/* PORT 0 (GPIO) */ +#define P0_0_PORT GPIO_PRT0 +#define P0_0_PIN 0u +#define P0_0_NUM 0u +#define P0_1_PORT GPIO_PRT0 +#define P0_1_PIN 1u +#define P0_1_NUM 1u +#define P0_2_PORT GPIO_PRT0 +#define P0_2_PIN 2u +#define P0_2_NUM 2u +#define P0_3_PORT GPIO_PRT0 +#define P0_3_PIN 3u +#define P0_3_NUM 3u +#define P0_4_PORT GPIO_PRT0 +#define P0_4_PIN 4u +#define P0_4_NUM 4u +#define P0_5_PORT GPIO_PRT0 +#define P0_5_PIN 5u +#define P0_5_NUM 5u + +/* PORT 2 (GPIO) */ +#define P2_0_PORT GPIO_PRT2 +#define P2_0_PIN 0u +#define P2_0_NUM 0u +#define P2_1_PORT GPIO_PRT2 +#define P2_1_PIN 1u +#define P2_1_NUM 1u +#define P2_2_PORT GPIO_PRT2 +#define P2_2_PIN 2u +#define P2_2_NUM 2u +#define P2_3_PORT GPIO_PRT2 +#define P2_3_PIN 3u +#define P2_3_NUM 3u +#define P2_4_PORT GPIO_PRT2 +#define P2_4_PIN 4u +#define P2_4_NUM 4u +#define P2_5_PORT GPIO_PRT2 +#define P2_5_PIN 5u +#define P2_5_NUM 5u +#define P2_6_PORT GPIO_PRT2 +#define P2_6_PIN 6u +#define P2_6_NUM 6u +#define P2_7_PORT GPIO_PRT2 +#define P2_7_PIN 7u +#define P2_7_NUM 7u + +/* PORT 3 (GPIO_OVT) */ +#define P3_0_PORT GPIO_PRT3 +#define P3_0_PIN 0u +#define P3_0_NUM 0u +#define P3_0_AMUXSEGMENT AMUXBUS_VSSA +#define P3_1_PORT GPIO_PRT3 +#define P3_1_PIN 1u +#define P3_1_NUM 1u +#define P3_1_AMUXSEGMENT AMUXBUS_VSSA + +/* PORT 5 (GPIO) */ +#define P5_0_PORT GPIO_PRT5 +#define P5_0_PIN 0u +#define P5_0_NUM 0u +#define P5_1_PORT GPIO_PRT5 +#define P5_1_PIN 1u +#define P5_1_NUM 1u +#define P5_6_PORT GPIO_PRT5 +#define P5_6_PIN 6u +#define P5_6_NUM 6u +#define P5_7_PORT GPIO_PRT5 +#define P5_7_PIN 7u +#define P5_7_NUM 7u + +/* PORT 6 (GPIO) */ +#define P6_2_PORT GPIO_PRT6 +#define P6_2_PIN 2u +#define P6_2_NUM 2u +#define P6_3_PORT GPIO_PRT6 +#define P6_3_PIN 3u +#define P6_3_NUM 3u +#define P6_4_PORT GPIO_PRT6 +#define P6_4_PIN 4u +#define P6_4_NUM 4u +#define P6_5_PORT GPIO_PRT6 +#define P6_5_PIN 5u +#define P6_5_NUM 5u +#define P6_6_PORT GPIO_PRT6 +#define P6_6_PIN 6u +#define P6_6_NUM 6u +#define P6_7_PORT GPIO_PRT6 +#define P6_7_PIN 7u +#define P6_7_NUM 7u + +/* PORT 7 (GPIO) */ +#define P7_0_PORT GPIO_PRT7 +#define P7_0_PIN 0u +#define P7_0_NUM 0u +#define P7_0_AMUXSEGMENT AMUXBUS_CSD0 +#define P7_1_PORT GPIO_PRT7 +#define P7_1_PIN 1u +#define P7_1_NUM 1u +#define P7_1_AMUXSEGMENT AMUXBUS_CSD0 +#define P7_2_PORT GPIO_PRT7 +#define P7_2_PIN 2u +#define P7_2_NUM 2u +#define P7_2_AMUXSEGMENT AMUXBUS_CSD0 +#define P7_3_PORT GPIO_PRT7 +#define P7_3_PIN 3u +#define P7_3_NUM 3u +#define P7_3_AMUXSEGMENT AMUXBUS_CSD0 +#define P7_7_PORT GPIO_PRT7 +#define P7_7_PIN 7u +#define P7_7_NUM 7u +#define P7_7_AMUXSEGMENT AMUXBUS_CSD0 + +/* PORT 8 (GPIO) */ +#define P8_0_PORT GPIO_PRT8 +#define P8_0_PIN 0u +#define P8_0_NUM 0u +#define P8_0_AMUXSEGMENT AMUXBUS_CSD0 +#define P8_1_PORT GPIO_PRT8 +#define P8_1_PIN 1u +#define P8_1_NUM 1u +#define P8_1_AMUXSEGMENT AMUXBUS_CSD0 + +/* PORT 9 (GPIO) */ +#define P9_0_PORT GPIO_PRT9 +#define P9_0_PIN 0u +#define P9_0_NUM 0u +#define P9_0_AMUXSEGMENT AMUXBUS_SAR +#define P9_1_PORT GPIO_PRT9 +#define P9_1_PIN 1u +#define P9_1_NUM 1u +#define P9_1_AMUXSEGMENT AMUXBUS_SAR +#define P9_2_PORT GPIO_PRT9 +#define P9_2_PIN 2u +#define P9_2_NUM 2u +#define P9_2_AMUXSEGMENT AMUXBUS_SAR +#define P9_3_PORT GPIO_PRT9 +#define P9_3_PIN 3u +#define P9_3_NUM 3u +#define P9_3_AMUXSEGMENT AMUXBUS_SAR + +/* PORT 10 (GPIO) */ +#define P10_0_PORT GPIO_PRT10 +#define P10_0_PIN 0u +#define P10_0_NUM 0u +#define P10_1_PORT GPIO_PRT10 +#define P10_1_PIN 1u +#define P10_1_NUM 1u +#define P10_2_PORT GPIO_PRT10 +#define P10_2_PIN 2u +#define P10_2_NUM 2u +#define P10_3_PORT GPIO_PRT10 +#define P10_3_PIN 3u +#define P10_3_NUM 3u +#define P10_4_PORT GPIO_PRT10 +#define P10_4_PIN 4u +#define P10_4_NUM 4u +#define P10_5_PORT GPIO_PRT10 +#define P10_5_PIN 5u +#define P10_5_NUM 5u + +/* PORT 11 (GPIO) */ +#define P11_0_PORT GPIO_PRT11 +#define P11_0_PIN 0u +#define P11_0_NUM 0u +#define P11_1_PORT GPIO_PRT11 +#define P11_1_PIN 1u +#define P11_1_NUM 1u +#define P11_2_PORT GPIO_PRT11 +#define P11_2_PIN 2u +#define P11_2_NUM 2u +#define P11_3_PORT GPIO_PRT11 +#define P11_3_PIN 3u +#define P11_3_NUM 3u +#define P11_4_PORT GPIO_PRT11 +#define P11_4_PIN 4u +#define P11_4_NUM 4u +#define P11_5_PORT GPIO_PRT11 +#define P11_5_PIN 5u +#define P11_5_NUM 5u +#define P11_6_PORT GPIO_PRT11 +#define P11_6_PIN 6u +#define P11_6_NUM 6u +#define P11_7_PORT GPIO_PRT11 +#define P11_7_PIN 7u +#define P11_7_NUM 7u + +/* PORT 12 (GPIO) */ +#define P12_6_PORT GPIO_PRT12 +#define P12_6_PIN 6u +#define P12_6_NUM 6u +#define P12_7_PORT GPIO_PRT12 +#define P12_7_PIN 7u +#define P12_7_NUM 7u + +/* PORT 14 (AUX) */ +#define USBDP_PORT GPIO_PRT14 +#define USBDP_PIN 0u +#define USBDP_NUM 0u +#define USBDM_PORT GPIO_PRT14 +#define USBDM_PIN 1u +#define USBDM_NUM 1u + +/* Analog Connections */ +#define CSD_CMODPADD_PORT 7u +#define CSD_CMODPADD_PIN 1u +#define CSD_CMODPADS_PORT 7u +#define CSD_CMODPADS_PIN 1u +#define CSD_CSH_TANKPADD_PORT 7u +#define CSD_CSH_TANKPADD_PIN 2u +#define CSD_CSH_TANKPADS_PORT 7u +#define CSD_CSH_TANKPADS_PIN 2u +#define CSD_CSHIELDPADS_PORT 7u +#define CSD_CSHIELDPADS_PIN 7u +#define CSD_VREF_EXT_PORT 7u +#define CSD_VREF_EXT_PIN 3u +#define IOSS_ADFT0_NET_PORT 10u +#define IOSS_ADFT0_NET_PIN 0u +#define IOSS_ADFT1_NET_PORT 10u +#define IOSS_ADFT1_NET_PIN 1u +#define LPCOMP_INN_COMP0_PORT 5u +#define LPCOMP_INN_COMP0_PIN 7u +#define LPCOMP_INN_COMP1_PORT 6u +#define LPCOMP_INN_COMP1_PIN 3u +#define LPCOMP_INP_COMP0_PORT 5u +#define LPCOMP_INP_COMP0_PIN 6u +#define LPCOMP_INP_COMP1_PORT 6u +#define LPCOMP_INP_COMP1_PIN 2u +#define PASS_AREF_EXT_VREF_PORT 9u +#define PASS_AREF_EXT_VREF_PIN 3u +#define PASS_SARMUX_PADS0_PORT 10u +#define PASS_SARMUX_PADS0_PIN 0u +#define PASS_SARMUX_PADS1_PORT 10u +#define PASS_SARMUX_PADS1_PIN 1u +#define PASS_SARMUX_PADS2_PORT 10u +#define PASS_SARMUX_PADS2_PIN 2u +#define PASS_SARMUX_PADS3_PORT 10u +#define PASS_SARMUX_PADS3_PIN 3u +#define PASS_SARMUX_PADS4_PORT 10u +#define PASS_SARMUX_PADS4_PIN 4u +#define PASS_SARMUX_PADS5_PORT 10u +#define PASS_SARMUX_PADS5_PIN 5u +#define SRSS_ADFT_PIN0_PORT 10u +#define SRSS_ADFT_PIN0_PIN 0u +#define SRSS_ADFT_PIN1_PORT 10u +#define SRSS_ADFT_PIN1_PIN 1u +#define SRSS_ECO_IN_PORT 12u +#define SRSS_ECO_IN_PIN 6u +#define SRSS_ECO_OUT_PORT 12u +#define SRSS_ECO_OUT_PIN 7u +#define SRSS_WCO_IN_PORT 0u +#define SRSS_WCO_IN_PIN 0u +#define SRSS_WCO_OUT_PORT 0u +#define SRSS_WCO_OUT_PIN 1u + +/* HSIOM Connections */ +typedef enum +{ + /* Generic HSIOM connections */ + HSIOM_SEL_GPIO = 0, /* GPIO controls 'out' */ + HSIOM_SEL_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + HSIOM_SEL_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + HSIOM_SEL_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + HSIOM_SEL_AMUXA = 4, /* Analog mux bus A */ + HSIOM_SEL_AMUXB = 5, /* Analog mux bus B */ + HSIOM_SEL_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + HSIOM_SEL_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + HSIOM_SEL_ACT_0 = 8, /* Active functionality 0 */ + HSIOM_SEL_ACT_1 = 9, /* Active functionality 1 */ + HSIOM_SEL_ACT_2 = 10, /* Active functionality 2 */ + HSIOM_SEL_ACT_3 = 11, /* Active functionality 3 */ + HSIOM_SEL_DS_0 = 12, /* DeepSleep functionality 0 */ + HSIOM_SEL_DS_1 = 13, /* DeepSleep functionality 1 */ + HSIOM_SEL_DS_2 = 14, /* DeepSleep functionality 2 */ + HSIOM_SEL_DS_3 = 15, /* DeepSleep functionality 3 */ + HSIOM_SEL_ACT_4 = 16, /* Active functionality 4 */ + HSIOM_SEL_ACT_5 = 17, /* Active functionality 5 */ + HSIOM_SEL_ACT_6 = 18, /* Active functionality 6 */ + HSIOM_SEL_ACT_7 = 19, /* Active functionality 7 */ + HSIOM_SEL_ACT_8 = 20, /* Active functionality 8 */ + HSIOM_SEL_ACT_9 = 21, /* Active functionality 9 */ + HSIOM_SEL_ACT_10 = 22, /* Active functionality 10 */ + HSIOM_SEL_ACT_11 = 23, /* Active functionality 11 */ + HSIOM_SEL_ACT_12 = 24, /* Active functionality 12 */ + HSIOM_SEL_ACT_13 = 25, /* Active functionality 13 */ + HSIOM_SEL_ACT_14 = 26, /* Active functionality 14 */ + HSIOM_SEL_ACT_15 = 27, /* Active functionality 15 */ + HSIOM_SEL_DS_4 = 28, /* DeepSleep functionality 4 */ + HSIOM_SEL_DS_5 = 29, /* DeepSleep functionality 5 */ + HSIOM_SEL_DS_6 = 30, /* DeepSleep functionality 6 */ + HSIOM_SEL_DS_7 = 31, /* DeepSleep functionality 7 */ + + /* P0.0 */ + P0_0_GPIO = 0, /* GPIO controls 'out' */ + P0_0_AMUXA = 4, /* Analog mux bus A */ + P0_0_AMUXB = 5, /* Analog mux bus B */ + P0_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P0_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P0_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:0 */ + P0_0_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:0 */ + P0_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:0 */ + P0_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:0 */ + P0_0_LCD_COM0 = 12, /* Digital Deep Sleep - lcd.com[0]:0 */ + P0_0_LCD_SEG0 = 13, /* Digital Deep Sleep - lcd.seg[0]:0 */ + P0_0_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:0 */ + P0_0_SCB0_SPI_SELECT1 = 20, /* Digital Active - scb[0].spi_select1:0 */ + P0_0_PERI_TR_IO_INPUT0 = 24, /* Digital Active - peri.tr_io_input[0]:0 */ + + /* P0.1 */ + P0_1_GPIO = 0, /* GPIO controls 'out' */ + P0_1_AMUXA = 4, /* Analog mux bus A */ + P0_1_AMUXB = 5, /* Analog mux bus B */ + P0_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P0_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P0_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:0 */ + P0_1_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:0 */ + P0_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:1 */ + P0_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:1 */ + P0_1_LCD_COM1 = 12, /* Digital Deep Sleep - lcd.com[1]:0 */ + P0_1_LCD_SEG1 = 13, /* Digital Deep Sleep - lcd.seg[1]:0 */ + P0_1_SCB0_SPI_SELECT2 = 20, /* Digital Active - scb[0].spi_select2:0 */ + P0_1_PERI_TR_IO_INPUT1 = 24, /* Digital Active - peri.tr_io_input[1]:0 */ + P0_1_CPUSS_SWJ_TRSTN = 29, /* Digital Deep Sleep - cpuss.swj_trstn */ + + /* P0.2 */ + P0_2_GPIO = 0, /* GPIO controls 'out' */ + P0_2_AMUXA = 4, /* Analog mux bus A */ + P0_2_AMUXB = 5, /* Analog mux bus B */ + P0_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P0_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P0_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:0 */ + P0_2_TCPWM1_LINE1 = 9, /* Digital Active - tcpwm[1].line[1]:0 */ + P0_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:2 */ + P0_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:2 */ + P0_2_LCD_COM2 = 12, /* Digital Deep Sleep - lcd.com[2]:0 */ + P0_2_LCD_SEG2 = 13, /* Digital Deep Sleep - lcd.seg[2]:0 */ + P0_2_SCB0_UART_RX = 18, /* Digital Active - scb[0].uart_rx:0 */ + P0_2_SCB0_I2C_SCL = 19, /* Digital Active - scb[0].i2c_scl:0 */ + P0_2_SCB0_SPI_MOSI = 20, /* Digital Active - scb[0].spi_mosi:0 */ + + /* P0.3 */ + P0_3_GPIO = 0, /* GPIO controls 'out' */ + P0_3_AMUXA = 4, /* Analog mux bus A */ + P0_3_AMUXB = 5, /* Analog mux bus B */ + P0_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P0_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P0_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:0 */ + P0_3_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:0 */ + P0_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:3 */ + P0_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:3 */ + P0_3_LCD_COM3 = 12, /* Digital Deep Sleep - lcd.com[3]:0 */ + P0_3_LCD_SEG3 = 13, /* Digital Deep Sleep - lcd.seg[3]:0 */ + P0_3_SCB0_UART_TX = 18, /* Digital Active - scb[0].uart_tx:0 */ + P0_3_SCB0_I2C_SDA = 19, /* Digital Active - scb[0].i2c_sda:0 */ + P0_3_SCB0_SPI_MISO = 20, /* Digital Active - scb[0].spi_miso:0 */ + + /* P0.4 */ + P0_4_GPIO = 0, /* GPIO controls 'out' */ + P0_4_AMUXA = 4, /* Analog mux bus A */ + P0_4_AMUXB = 5, /* Analog mux bus B */ + P0_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P0_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P0_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:0 */ + P0_4_TCPWM1_LINE2 = 9, /* Digital Active - tcpwm[1].line[2]:0 */ + P0_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:4 */ + P0_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:4 */ + P0_4_LCD_COM4 = 12, /* Digital Deep Sleep - lcd.com[4]:0 */ + P0_4_LCD_SEG4 = 13, /* Digital Deep Sleep - lcd.seg[4]:0 */ + P0_4_SCB0_UART_RTS = 18, /* Digital Active - scb[0].uart_rts:0 */ + P0_4_SCB0_SPI_CLK = 20, /* Digital Active - scb[0].spi_clk:0 */ + P0_4_PERI_TR_IO_INPUT2 = 24, /* Digital Active - peri.tr_io_input[2]:0 */ + P0_4_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:2 */ + + /* P0.5 */ + P0_5_GPIO = 0, /* GPIO controls 'out' */ + P0_5_AMUXA = 4, /* Analog mux bus A */ + P0_5_AMUXB = 5, /* Analog mux bus B */ + P0_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P0_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P0_5_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:0 */ + P0_5_TCPWM1_LINE_COMPL2 = 9, /* Digital Active - tcpwm[1].line_compl[2]:0 */ + P0_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:5 */ + P0_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:5 */ + P0_5_LCD_COM5 = 12, /* Digital Deep Sleep - lcd.com[5]:0 */ + P0_5_LCD_SEG5 = 13, /* Digital Deep Sleep - lcd.seg[5]:0 */ + P0_5_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:1 */ + P0_5_SCB0_UART_CTS = 18, /* Digital Active - scb[0].uart_cts:0 */ + P0_5_SCB0_SPI_SELECT0 = 20, /* Digital Active - scb[0].spi_select0:0 */ + P0_5_PERI_TR_IO_INPUT3 = 24, /* Digital Active - peri.tr_io_input[3]:0 */ + P0_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:2 */ + + /* USBDM */ + USBDM_GPIO = 0, /* GPIO controls 'out' */ + + /* USBDP */ + USBDP_GPIO = 0, /* GPIO controls 'out' */ + + /* P2.0 */ + P2_0_GPIO = 0, /* GPIO controls 'out' */ + P2_0_AMUXA = 4, /* Analog mux bus A */ + P2_0_AMUXB = 5, /* Analog mux bus B */ + P2_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P2_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P2_0_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:0 */ + P2_0_TCPWM1_LINE3 = 9, /* Digital Active - tcpwm[1].line[3]:0 */ + P2_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:6 */ + P2_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:6 */ + P2_0_LCD_COM6 = 12, /* Digital Deep Sleep - lcd.com[6]:0 */ + P2_0_LCD_SEG6 = 13, /* Digital Deep Sleep - lcd.seg[6]:0 */ + P2_0_SCB1_UART_RX = 18, /* Digital Active - scb[1].uart_rx:0 */ + P2_0_SCB1_I2C_SCL = 19, /* Digital Active - scb[1].i2c_scl:0 */ + P2_0_SCB1_SPI_MOSI = 20, /* Digital Active - scb[1].spi_mosi:0 */ + P2_0_PERI_TR_IO_INPUT4 = 24, /* Digital Active - peri.tr_io_input[4]:0 */ + P2_0_SDHC0_CARD_DAT_3TO00 = 26, /* Digital Active - sdhc[0].card_dat_3to0[0] */ + + /* P2.1 */ + P2_1_GPIO = 0, /* GPIO controls 'out' */ + P2_1_AMUXA = 4, /* Analog mux bus A */ + P2_1_AMUXB = 5, /* Analog mux bus B */ + P2_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P2_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P2_1_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:0 */ + P2_1_TCPWM1_LINE_COMPL3 = 9, /* Digital Active - tcpwm[1].line_compl[3]:0 */ + P2_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:7 */ + P2_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:7 */ + P2_1_LCD_COM7 = 12, /* Digital Deep Sleep - lcd.com[7]:0 */ + P2_1_LCD_SEG7 = 13, /* Digital Deep Sleep - lcd.seg[7]:0 */ + P2_1_SCB1_UART_TX = 18, /* Digital Active - scb[1].uart_tx:0 */ + P2_1_SCB1_I2C_SDA = 19, /* Digital Active - scb[1].i2c_sda:0 */ + P2_1_SCB1_SPI_MISO = 20, /* Digital Active - scb[1].spi_miso:0 */ + P2_1_PERI_TR_IO_INPUT5 = 24, /* Digital Active - peri.tr_io_input[5]:0 */ + P2_1_SDHC0_CARD_DAT_3TO01 = 26, /* Digital Active - sdhc[0].card_dat_3to0[1] */ + + /* P2.2 */ + P2_2_GPIO = 0, /* GPIO controls 'out' */ + P2_2_AMUXA = 4, /* Analog mux bus A */ + P2_2_AMUXB = 5, /* Analog mux bus B */ + P2_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P2_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P2_2_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:1 */ + P2_2_TCPWM1_LINE4 = 9, /* Digital Active - tcpwm[1].line[4]:0 */ + P2_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:8 */ + P2_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:8 */ + P2_2_LCD_COM8 = 12, /* Digital Deep Sleep - lcd.com[8]:0 */ + P2_2_LCD_SEG8 = 13, /* Digital Deep Sleep - lcd.seg[8]:0 */ + P2_2_SCB1_UART_RTS = 18, /* Digital Active - scb[1].uart_rts:0 */ + P2_2_SCB1_SPI_CLK = 20, /* Digital Active - scb[1].spi_clk:0 */ + P2_2_SDHC0_CARD_DAT_3TO02 = 26, /* Digital Active - sdhc[0].card_dat_3to0[2] */ + + /* P2.3 */ + P2_3_GPIO = 0, /* GPIO controls 'out' */ + P2_3_AMUXA = 4, /* Analog mux bus A */ + P2_3_AMUXB = 5, /* Analog mux bus B */ + P2_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P2_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P2_3_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:1 */ + P2_3_TCPWM1_LINE_COMPL4 = 9, /* Digital Active - tcpwm[1].line_compl[4]:0 */ + P2_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:9 */ + P2_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:9 */ + P2_3_LCD_COM9 = 12, /* Digital Deep Sleep - lcd.com[9]:0 */ + P2_3_LCD_SEG9 = 13, /* Digital Deep Sleep - lcd.seg[9]:0 */ + P2_3_SCB1_UART_CTS = 18, /* Digital Active - scb[1].uart_cts:0 */ + P2_3_SCB1_SPI_SELECT0 = 20, /* Digital Active - scb[1].spi_select0:0 */ + P2_3_SDHC0_CARD_DAT_3TO03 = 26, /* Digital Active - sdhc[0].card_dat_3to0[3] */ + + /* P2.4 */ + P2_4_GPIO = 0, /* GPIO controls 'out' */ + P2_4_AMUXA = 4, /* Analog mux bus A */ + P2_4_AMUXB = 5, /* Analog mux bus B */ + P2_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P2_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P2_4_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:1 */ + P2_4_TCPWM1_LINE5 = 9, /* Digital Active - tcpwm[1].line[5]:0 */ + P2_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:10 */ + P2_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:10 */ + P2_4_LCD_COM10 = 12, /* Digital Deep Sleep - lcd.com[10]:0 */ + P2_4_LCD_SEG10 = 13, /* Digital Deep Sleep - lcd.seg[10]:0 */ + P2_4_SCB1_SPI_SELECT1 = 20, /* Digital Active - scb[1].spi_select1:0 */ + P2_4_SDHC0_CARD_CMD = 26, /* Digital Active - sdhc[0].card_cmd */ + + /* P2.5 */ + P2_5_GPIO = 0, /* GPIO controls 'out' */ + P2_5_AMUXA = 4, /* Analog mux bus A */ + P2_5_AMUXB = 5, /* Analog mux bus B */ + P2_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P2_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P2_5_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:1 */ + P2_5_TCPWM1_LINE_COMPL5 = 9, /* Digital Active - tcpwm[1].line_compl[5]:0 */ + P2_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:11 */ + P2_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:11 */ + P2_5_LCD_COM11 = 12, /* Digital Deep Sleep - lcd.com[11]:0 */ + P2_5_LCD_SEG11 = 13, /* Digital Deep Sleep - lcd.seg[11]:0 */ + P2_5_SCB1_SPI_SELECT2 = 20, /* Digital Active - scb[1].spi_select2:0 */ + P2_5_SDHC0_CLK_CARD = 26, /* Digital Active - sdhc[0].clk_card */ + + /* P2.6 */ + P2_6_GPIO = 0, /* GPIO controls 'out' */ + P2_6_AMUXA = 4, /* Analog mux bus A */ + P2_6_AMUXB = 5, /* Analog mux bus B */ + P2_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P2_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P2_6_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:1 */ + P2_6_TCPWM1_LINE6 = 9, /* Digital Active - tcpwm[1].line[6]:0 */ + P2_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:12 */ + P2_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:12 */ + P2_6_LCD_COM12 = 12, /* Digital Deep Sleep - lcd.com[12]:0 */ + P2_6_LCD_SEG12 = 13, /* Digital Deep Sleep - lcd.seg[12]:0 */ + P2_6_SCB1_SPI_SELECT3 = 20, /* Digital Active - scb[1].spi_select3:0 */ + P2_6_PERI_TR_IO_INPUT8 = 24, /* Digital Active - peri.tr_io_input[8]:0 */ + P2_6_SDHC0_CARD_DETECT_N = 26, /* Digital Active - sdhc[0].card_detect_n */ + + /* P2.7 */ + P2_7_GPIO = 0, /* GPIO controls 'out' */ + P2_7_AMUXA = 4, /* Analog mux bus A */ + P2_7_AMUXB = 5, /* Analog mux bus B */ + P2_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P2_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P2_7_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:1 */ + P2_7_TCPWM1_LINE_COMPL6 = 9, /* Digital Active - tcpwm[1].line_compl[6]:0 */ + P2_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:13 */ + P2_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:13 */ + P2_7_LCD_COM13 = 12, /* Digital Deep Sleep - lcd.com[13]:0 */ + P2_7_LCD_SEG13 = 13, /* Digital Deep Sleep - lcd.seg[13]:0 */ + P2_7_PERI_TR_IO_INPUT9 = 24, /* Digital Active - peri.tr_io_input[9]:0 */ + P2_7_SDHC0_CARD_MECH_WRITE_PROT = 26, /* Digital Active - sdhc[0].card_mech_write_prot */ + + /* P3.0 */ + P3_0_GPIO = 0, /* GPIO controls 'out' */ + P3_0_AMUXA = 4, /* Analog mux bus A */ + P3_0_AMUXB = 5, /* Analog mux bus B */ + P3_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P3_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P3_0_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:1 */ + P3_0_TCPWM1_LINE7 = 9, /* Digital Active - tcpwm[1].line[7]:0 */ + P3_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:14 */ + P3_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:14 */ + P3_0_LCD_COM14 = 12, /* Digital Deep Sleep - lcd.com[14]:0 */ + P3_0_LCD_SEG14 = 13, /* Digital Deep Sleep - lcd.seg[14]:0 */ + P3_0_SCB2_UART_RX = 18, /* Digital Active - scb[2].uart_rx:1 */ + P3_0_SCB2_I2C_SCL = 19, /* Digital Active - scb[2].i2c_scl:1 */ + P3_0_SCB2_SPI_MOSI = 20, /* Digital Active - scb[2].spi_mosi:1 */ + P3_0_PERI_TR_IO_INPUT6 = 24, /* Digital Active - peri.tr_io_input[6]:0 */ + P3_0_SDHC0_IO_VOLT_SEL = 26, /* Digital Active - sdhc[0].io_volt_sel */ + + /* P3.1 */ + P3_1_GPIO = 0, /* GPIO controls 'out' */ + P3_1_AMUXA = 4, /* Analog mux bus A */ + P3_1_AMUXB = 5, /* Analog mux bus B */ + P3_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P3_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P3_1_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:1 */ + P3_1_TCPWM1_LINE_COMPL7 = 9, /* Digital Active - tcpwm[1].line_compl[7]:0 */ + P3_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:15 */ + P3_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:15 */ + P3_1_LCD_COM15 = 12, /* Digital Deep Sleep - lcd.com[15]:0 */ + P3_1_LCD_SEG15 = 13, /* Digital Deep Sleep - lcd.seg[15]:0 */ + P3_1_SCB2_UART_TX = 18, /* Digital Active - scb[2].uart_tx:1 */ + P3_1_SCB2_I2C_SDA = 19, /* Digital Active - scb[2].i2c_sda:1 */ + P3_1_SCB2_SPI_MISO = 20, /* Digital Active - scb[2].spi_miso:1 */ + P3_1_PERI_TR_IO_INPUT7 = 24, /* Digital Active - peri.tr_io_input[7]:0 */ + P3_1_SDHC0_CARD_IF_PWR_EN = 26, /* Digital Active - sdhc[0].card_if_pwr_en */ + + /* P5.0 */ + P5_0_GPIO = 0, /* GPIO controls 'out' */ + P5_0_AMUXA = 4, /* Analog mux bus A */ + P5_0_AMUXB = 5, /* Analog mux bus B */ + P5_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P5_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P5_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:2 */ + P5_0_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:1 */ + P5_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:16 */ + P5_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:16 */ + P5_0_LCD_COM16 = 12, /* Digital Deep Sleep - lcd.com[16]:0 */ + P5_0_LCD_SEG16 = 13, /* Digital Deep Sleep - lcd.seg[16]:0 */ + P5_0_SCB5_UART_RX = 18, /* Digital Active - scb[5].uart_rx:1 */ + P5_0_SCB5_I2C_SCL = 19, /* Digital Active - scb[5].i2c_scl:1 */ + P5_0_SCB5_SPI_MOSI = 20, /* Digital Active - scb[5].spi_mosi:1 */ + P5_0_CANFD0_TTCAN_RX0 = 22, /* Digital Active - canfd[0].ttcan_rx[0] */ + P5_0_PERI_TR_IO_INPUT10 = 24, /* Digital Active - peri.tr_io_input[10]:0 */ + + /* P5.1 */ + P5_1_GPIO = 0, /* GPIO controls 'out' */ + P5_1_AMUXA = 4, /* Analog mux bus A */ + P5_1_AMUXB = 5, /* Analog mux bus B */ + P5_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P5_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P5_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:2 */ + P5_1_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:1 */ + P5_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:17 */ + P5_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:17 */ + P5_1_LCD_COM17 = 12, /* Digital Deep Sleep - lcd.com[17]:0 */ + P5_1_LCD_SEG17 = 13, /* Digital Deep Sleep - lcd.seg[17]:0 */ + P5_1_SCB5_UART_TX = 18, /* Digital Active - scb[5].uart_tx:1 */ + P5_1_SCB5_I2C_SDA = 19, /* Digital Active - scb[5].i2c_sda:1 */ + P5_1_SCB5_SPI_MISO = 20, /* Digital Active - scb[5].spi_miso:1 */ + P5_1_CANFD0_TTCAN_TX0 = 22, /* Digital Active - canfd[0].ttcan_tx[0] */ + P5_1_PERI_TR_IO_INPUT11 = 24, /* Digital Active - peri.tr_io_input[11]:0 */ + + /* P5.6 */ + P5_6_GPIO = 0, /* GPIO controls 'out' */ + P5_6_AMUXA = 4, /* Analog mux bus A */ + P5_6_AMUXB = 5, /* Analog mux bus B */ + P5_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P5_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P5_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:2 */ + P5_6_TCPWM1_LINE1 = 9, /* Digital Active - tcpwm[1].line[1]:1 */ + P5_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:18 */ + P5_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:18 */ + P5_6_LCD_COM18 = 12, /* Digital Deep Sleep - lcd.com[18]:0 */ + P5_6_LCD_SEG18 = 13, /* Digital Deep Sleep - lcd.seg[18]:0 */ + + /* P5.7 */ + P5_7_GPIO = 0, /* GPIO controls 'out' */ + P5_7_AMUXA = 4, /* Analog mux bus A */ + P5_7_AMUXB = 5, /* Analog mux bus B */ + P5_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P5_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P5_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:2 */ + P5_7_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:1 */ + P5_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:19 */ + P5_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:19 */ + P5_7_LCD_COM19 = 12, /* Digital Deep Sleep - lcd.com[19]:0 */ + P5_7_LCD_SEG19 = 13, /* Digital Deep Sleep - lcd.seg[19]:0 */ + + /* P6.2 */ + P6_2_GPIO = 0, /* GPIO controls 'out' */ + P6_2_AMUXA = 4, /* Analog mux bus A */ + P6_2_AMUXB = 5, /* Analog mux bus B */ + P6_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P6_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P6_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:2 */ + P6_2_TCPWM1_LINE3 = 9, /* Digital Active - tcpwm[1].line[3]:1 */ + P6_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:22 */ + P6_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:22 */ + P6_2_LCD_COM22 = 12, /* Digital Deep Sleep - lcd.com[22]:0 */ + P6_2_LCD_SEG22 = 13, /* Digital Deep Sleep - lcd.seg[22]:0 */ + P6_2_SCB3_UART_RTS = 18, /* Digital Active - scb[3].uart_rts:0 */ + P6_2_SCB3_SPI_CLK = 20, /* Digital Active - scb[3].spi_clk:0 */ + + /* P6.3 */ + P6_3_GPIO = 0, /* GPIO controls 'out' */ + P6_3_AMUXA = 4, /* Analog mux bus A */ + P6_3_AMUXB = 5, /* Analog mux bus B */ + P6_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P6_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P6_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:2 */ + P6_3_TCPWM1_LINE_COMPL3 = 9, /* Digital Active - tcpwm[1].line_compl[3]:1 */ + P6_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:23 */ + P6_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:23 */ + P6_3_LCD_COM23 = 12, /* Digital Deep Sleep - lcd.com[23]:0 */ + P6_3_LCD_SEG23 = 13, /* Digital Deep Sleep - lcd.seg[23]:0 */ + P6_3_SCB3_UART_CTS = 18, /* Digital Active - scb[3].uart_cts:0 */ + P6_3_SCB3_SPI_SELECT0 = 20, /* Digital Active - scb[3].spi_select0:0 */ + + /* P6.4 */ + P6_4_GPIO = 0, /* GPIO controls 'out' */ + P6_4_AMUXA = 4, /* Analog mux bus A */ + P6_4_AMUXB = 5, /* Analog mux bus B */ + P6_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P6_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P6_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:3 */ + P6_4_TCPWM1_LINE4 = 9, /* Digital Active - tcpwm[1].line[4]:1 */ + P6_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:24 */ + P6_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:24 */ + P6_4_LCD_COM24 = 12, /* Digital Deep Sleep - lcd.com[24]:0 */ + P6_4_LCD_SEG24 = 13, /* Digital Deep Sleep - lcd.seg[24]:0 */ + P6_4_SCB6_I2C_SCL = 14, /* Digital Deep Sleep - scb[6].i2c_scl:0 */ + P6_4_PERI_TR_IO_INPUT12 = 24, /* Digital Active - peri.tr_io_input[12]:0 */ + P6_4_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:1 */ + P6_4_CPUSS_SWJ_SWO_TDO = 29, /* Digital Deep Sleep - cpuss.swj_swo_tdo */ + P6_4_SCB6_SPI_MOSI = 30, /* Digital Deep Sleep - scb[6].spi_mosi:0 */ + P6_4_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:0 */ + + /* P6.5 */ + P6_5_GPIO = 0, /* GPIO controls 'out' */ + P6_5_AMUXA = 4, /* Analog mux bus A */ + P6_5_AMUXB = 5, /* Analog mux bus B */ + P6_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P6_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P6_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:3 */ + P6_5_TCPWM1_LINE_COMPL4 = 9, /* Digital Active - tcpwm[1].line_compl[4]:1 */ + P6_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:25 */ + P6_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:25 */ + P6_5_LCD_COM25 = 12, /* Digital Deep Sleep - lcd.com[25]:0 */ + P6_5_LCD_SEG25 = 13, /* Digital Deep Sleep - lcd.seg[25]:0 */ + P6_5_SCB6_I2C_SDA = 14, /* Digital Deep Sleep - scb[6].i2c_sda:0 */ + P6_5_PERI_TR_IO_INPUT13 = 24, /* Digital Active - peri.tr_io_input[13]:0 */ + P6_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:1 */ + P6_5_CPUSS_SWJ_SWDOE_TDI = 29, /* Digital Deep Sleep - cpuss.swj_swdoe_tdi */ + P6_5_SCB6_SPI_MISO = 30, /* Digital Deep Sleep - scb[6].spi_miso:0 */ + P6_5_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:0 */ + + /* P6.6 */ + P6_6_GPIO = 0, /* GPIO controls 'out' */ + P6_6_AMUXA = 4, /* Analog mux bus A */ + P6_6_AMUXB = 5, /* Analog mux bus B */ + P6_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P6_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P6_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:3 */ + P6_6_TCPWM1_LINE5 = 9, /* Digital Active - tcpwm[1].line[5]:1 */ + P6_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:26 */ + P6_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:26 */ + P6_6_LCD_COM26 = 12, /* Digital Deep Sleep - lcd.com[26]:0 */ + P6_6_LCD_SEG26 = 13, /* Digital Deep Sleep - lcd.seg[26]:0 */ + P6_6_CPUSS_SWJ_SWDIO_TMS = 29, /* Digital Deep Sleep - cpuss.swj_swdio_tms */ + P6_6_SCB6_SPI_CLK = 30, /* Digital Deep Sleep - scb[6].spi_clk:0 */ + + /* P6.7 */ + P6_7_GPIO = 0, /* GPIO controls 'out' */ + P6_7_AMUXA = 4, /* Analog mux bus A */ + P6_7_AMUXB = 5, /* Analog mux bus B */ + P6_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P6_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P6_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:3 */ + P6_7_TCPWM1_LINE_COMPL5 = 9, /* Digital Active - tcpwm[1].line_compl[5]:1 */ + P6_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:27 */ + P6_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:27 */ + P6_7_LCD_COM27 = 12, /* Digital Deep Sleep - lcd.com[27]:0 */ + P6_7_LCD_SEG27 = 13, /* Digital Deep Sleep - lcd.seg[27]:0 */ + P6_7_CPUSS_SWJ_SWCLK_TCLK = 29, /* Digital Deep Sleep - cpuss.swj_swclk_tclk */ + P6_7_SCB6_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[6].spi_select0:0 */ + + /* P7.0 */ + P7_0_GPIO = 0, /* GPIO controls 'out' */ + P7_0_AMUXA = 4, /* Analog mux bus A */ + P7_0_AMUXB = 5, /* Analog mux bus B */ + P7_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P7_0_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:3 */ + P7_0_TCPWM1_LINE6 = 9, /* Digital Active - tcpwm[1].line[6]:1 */ + P7_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:28 */ + P7_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:28 */ + P7_0_LCD_COM28 = 12, /* Digital Deep Sleep - lcd.com[28]:0 */ + P7_0_LCD_SEG28 = 13, /* Digital Deep Sleep - lcd.seg[28]:0 */ + P7_0_SCB4_UART_RX = 18, /* Digital Active - scb[4].uart_rx:1 */ + P7_0_SCB4_I2C_SCL = 19, /* Digital Active - scb[4].i2c_scl:1 */ + P7_0_SCB4_SPI_MOSI = 20, /* Digital Active - scb[4].spi_mosi:1 */ + P7_0_PERI_TR_IO_INPUT14 = 24, /* Digital Active - peri.tr_io_input[14]:0 */ + P7_0_CPUSS_TRACE_CLOCK = 26, /* Digital Active - cpuss.trace_clock */ + + /* P7.1 */ + P7_1_GPIO = 0, /* GPIO controls 'out' */ + P7_1_AMUXA = 4, /* Analog mux bus A */ + P7_1_AMUXB = 5, /* Analog mux bus B */ + P7_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P7_1_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:3 */ + P7_1_TCPWM1_LINE_COMPL6 = 9, /* Digital Active - tcpwm[1].line_compl[6]:1 */ + P7_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:29 */ + P7_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:29 */ + P7_1_LCD_COM29 = 12, /* Digital Deep Sleep - lcd.com[29]:0 */ + P7_1_LCD_SEG29 = 13, /* Digital Deep Sleep - lcd.seg[29]:0 */ + P7_1_SCB4_UART_TX = 18, /* Digital Active - scb[4].uart_tx:1 */ + P7_1_SCB4_I2C_SDA = 19, /* Digital Active - scb[4].i2c_sda:1 */ + P7_1_SCB4_SPI_MISO = 20, /* Digital Active - scb[4].spi_miso:1 */ + P7_1_PERI_TR_IO_INPUT15 = 24, /* Digital Active - peri.tr_io_input[15]:0 */ + + /* P7.2 */ + P7_2_GPIO = 0, /* GPIO controls 'out' */ + P7_2_AMUXA = 4, /* Analog mux bus A */ + P7_2_AMUXB = 5, /* Analog mux bus B */ + P7_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P7_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:3 */ + P7_2_TCPWM1_LINE7 = 9, /* Digital Active - tcpwm[1].line[7]:1 */ + P7_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:30 */ + P7_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:30 */ + P7_2_LCD_COM30 = 12, /* Digital Deep Sleep - lcd.com[30]:0 */ + P7_2_LCD_SEG30 = 13, /* Digital Deep Sleep - lcd.seg[30]:0 */ + P7_2_SCB4_UART_RTS = 18, /* Digital Active - scb[4].uart_rts:1 */ + P7_2_SCB4_SPI_CLK = 20, /* Digital Active - scb[4].spi_clk:1 */ + + /* P7.3 */ + P7_3_GPIO = 0, /* GPIO controls 'out' */ + P7_3_AMUXA = 4, /* Analog mux bus A */ + P7_3_AMUXB = 5, /* Analog mux bus B */ + P7_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P7_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:3 */ + P7_3_TCPWM1_LINE_COMPL7 = 9, /* Digital Active - tcpwm[1].line_compl[7]:1 */ + P7_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:31 */ + P7_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:31 */ + P7_3_LCD_COM31 = 12, /* Digital Deep Sleep - lcd.com[31]:0 */ + P7_3_LCD_SEG31 = 13, /* Digital Deep Sleep - lcd.seg[31]:0 */ + P7_3_SCB4_UART_CTS = 18, /* Digital Active - scb[4].uart_cts:1 */ + P7_3_SCB4_SPI_SELECT0 = 20, /* Digital Active - scb[4].spi_select0:1 */ + + /* P7.7 */ + P7_7_GPIO = 0, /* GPIO controls 'out' */ + P7_7_AMUXA = 4, /* Analog mux bus A */ + P7_7_AMUXB = 5, /* Analog mux bus B */ + P7_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P7_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:4 */ + P7_7_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:2 */ + P7_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:35 */ + P7_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:35 */ + P7_7_LCD_COM35 = 12, /* Digital Deep Sleep - lcd.com[35]:0 */ + P7_7_LCD_SEG35 = 13, /* Digital Deep Sleep - lcd.seg[35]:0 */ + P7_7_CPUSS_CLK_FM_PUMP = 21, /* Digital Active - cpuss.clk_fm_pump */ + P7_7_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:2 */ + + /* P8.0 */ + P8_0_GPIO = 0, /* GPIO controls 'out' */ + P8_0_AMUXA = 4, /* Analog mux bus A */ + P8_0_AMUXB = 5, /* Analog mux bus B */ + P8_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P8_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P8_0_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:4 */ + P8_0_TCPWM1_LINE2 = 9, /* Digital Active - tcpwm[1].line[2]:2 */ + P8_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:36 */ + P8_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:36 */ + P8_0_LCD_COM36 = 12, /* Digital Deep Sleep - lcd.com[36]:0 */ + P8_0_LCD_SEG36 = 13, /* Digital Deep Sleep - lcd.seg[36]:0 */ + P8_0_SCB4_UART_RX = 18, /* Digital Active - scb[4].uart_rx:0 */ + P8_0_SCB4_I2C_SCL = 19, /* Digital Active - scb[4].i2c_scl:0 */ + P8_0_SCB4_SPI_MOSI = 20, /* Digital Active - scb[4].spi_mosi:0 */ + P8_0_PERI_TR_IO_INPUT16 = 24, /* Digital Active - peri.tr_io_input[16]:0 */ + + /* P8.1 */ + P8_1_GPIO = 0, /* GPIO controls 'out' */ + P8_1_AMUXA = 4, /* Analog mux bus A */ + P8_1_AMUXB = 5, /* Analog mux bus B */ + P8_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P8_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P8_1_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:4 */ + P8_1_TCPWM1_LINE_COMPL2 = 9, /* Digital Active - tcpwm[1].line_compl[2]:2 */ + P8_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:37 */ + P8_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:37 */ + P8_1_LCD_COM37 = 12, /* Digital Deep Sleep - lcd.com[37]:0 */ + P8_1_LCD_SEG37 = 13, /* Digital Deep Sleep - lcd.seg[37]:0 */ + P8_1_SCB4_UART_TX = 18, /* Digital Active - scb[4].uart_tx:0 */ + P8_1_SCB4_I2C_SDA = 19, /* Digital Active - scb[4].i2c_sda:0 */ + P8_1_SCB4_SPI_MISO = 20, /* Digital Active - scb[4].spi_miso:0 */ + P8_1_PERI_TR_IO_INPUT17 = 24, /* Digital Active - peri.tr_io_input[17]:0 */ + + /* P9.0 */ + P9_0_GPIO = 0, /* GPIO controls 'out' */ + P9_0_AMUXA = 4, /* Analog mux bus A */ + P9_0_AMUXB = 5, /* Analog mux bus B */ + P9_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P9_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P9_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:5 */ + P9_0_TCPWM1_LINE4 = 9, /* Digital Active - tcpwm[1].line[4]:2 */ + P9_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:40 */ + P9_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:40 */ + P9_0_LCD_COM40 = 12, /* Digital Deep Sleep - lcd.com[40]:0 */ + P9_0_LCD_SEG40 = 13, /* Digital Deep Sleep - lcd.seg[40]:0 */ + P9_0_SCB2_UART_RX = 18, /* Digital Active - scb[2].uart_rx:0 */ + P9_0_SCB2_I2C_SCL = 19, /* Digital Active - scb[2].i2c_scl:0 */ + P9_0_SCB2_SPI_MOSI = 20, /* Digital Active - scb[2].spi_mosi:0 */ + P9_0_PERI_TR_IO_INPUT18 = 24, /* Digital Active - peri.tr_io_input[18]:0 */ + P9_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:0 */ + + /* P9.1 */ + P9_1_GPIO = 0, /* GPIO controls 'out' */ + P9_1_AMUXA = 4, /* Analog mux bus A */ + P9_1_AMUXB = 5, /* Analog mux bus B */ + P9_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P9_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P9_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:5 */ + P9_1_TCPWM1_LINE_COMPL4 = 9, /* Digital Active - tcpwm[1].line_compl[4]:2 */ + P9_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:41 */ + P9_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:41 */ + P9_1_LCD_COM41 = 12, /* Digital Deep Sleep - lcd.com[41]:0 */ + P9_1_LCD_SEG41 = 13, /* Digital Deep Sleep - lcd.seg[41]:0 */ + P9_1_SCB2_UART_TX = 18, /* Digital Active - scb[2].uart_tx:0 */ + P9_1_SCB2_I2C_SDA = 19, /* Digital Active - scb[2].i2c_sda:0 */ + P9_1_SCB2_SPI_MISO = 20, /* Digital Active - scb[2].spi_miso:0 */ + P9_1_PERI_TR_IO_INPUT19 = 24, /* Digital Active - peri.tr_io_input[19]:0 */ + P9_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:0 */ + P9_1_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:1 */ + + /* P9.2 */ + P9_2_GPIO = 0, /* GPIO controls 'out' */ + P9_2_AMUXA = 4, /* Analog mux bus A */ + P9_2_AMUXB = 5, /* Analog mux bus B */ + P9_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P9_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P9_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:5 */ + P9_2_TCPWM1_LINE5 = 9, /* Digital Active - tcpwm[1].line[5]:2 */ + P9_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:42 */ + P9_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:42 */ + P9_2_LCD_COM42 = 12, /* Digital Deep Sleep - lcd.com[42]:0 */ + P9_2_LCD_SEG42 = 13, /* Digital Deep Sleep - lcd.seg[42]:0 */ + P9_2_SCB2_UART_RTS = 18, /* Digital Active - scb[2].uart_rts:0 */ + P9_2_SCB2_SPI_CLK = 20, /* Digital Active - scb[2].spi_clk:0 */ + P9_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:0 */ + + /* P9.3 */ + P9_3_GPIO = 0, /* GPIO controls 'out' */ + P9_3_AMUXA = 4, /* Analog mux bus A */ + P9_3_AMUXB = 5, /* Analog mux bus B */ + P9_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P9_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P9_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:5 */ + P9_3_TCPWM1_LINE_COMPL5 = 9, /* Digital Active - tcpwm[1].line_compl[5]:2 */ + P9_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:43 */ + P9_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:43 */ + P9_3_LCD_COM43 = 12, /* Digital Deep Sleep - lcd.com[43]:0 */ + P9_3_LCD_SEG43 = 13, /* Digital Deep Sleep - lcd.seg[43]:0 */ + P9_3_SCB2_UART_CTS = 18, /* Digital Active - scb[2].uart_cts:0 */ + P9_3_SCB2_SPI_SELECT0 = 20, /* Digital Active - scb[2].spi_select0:0 */ + P9_3_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:0 */ + P9_3_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:1 */ + + /* P10.0 */ + P10_0_GPIO = 0, /* GPIO controls 'out' */ + P10_0_AMUXA = 4, /* Analog mux bus A */ + P10_0_AMUXB = 5, /* Analog mux bus B */ + P10_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P10_0_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:5 */ + P10_0_TCPWM1_LINE6 = 9, /* Digital Active - tcpwm[1].line[6]:2 */ + P10_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:44 */ + P10_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:44 */ + P10_0_LCD_COM44 = 12, /* Digital Deep Sleep - lcd.com[44]:0 */ + P10_0_LCD_SEG44 = 13, /* Digital Deep Sleep - lcd.seg[44]:0 */ + P10_0_SCB1_UART_RX = 18, /* Digital Active - scb[1].uart_rx:1 */ + P10_0_SCB1_I2C_SCL = 19, /* Digital Active - scb[1].i2c_scl:1 */ + P10_0_SCB1_SPI_MOSI = 20, /* Digital Active - scb[1].spi_mosi:1 */ + P10_0_PERI_TR_IO_INPUT20 = 24, /* Digital Active - peri.tr_io_input[20]:0 */ + P10_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:1 */ + + /* P10.1 */ + P10_1_GPIO = 0, /* GPIO controls 'out' */ + P10_1_AMUXA = 4, /* Analog mux bus A */ + P10_1_AMUXB = 5, /* Analog mux bus B */ + P10_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P10_1_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:5 */ + P10_1_TCPWM1_LINE_COMPL6 = 9, /* Digital Active - tcpwm[1].line_compl[6]:2 */ + P10_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:45 */ + P10_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:45 */ + P10_1_LCD_COM45 = 12, /* Digital Deep Sleep - lcd.com[45]:0 */ + P10_1_LCD_SEG45 = 13, /* Digital Deep Sleep - lcd.seg[45]:0 */ + P10_1_SCB1_UART_TX = 18, /* Digital Active - scb[1].uart_tx:1 */ + P10_1_SCB1_I2C_SDA = 19, /* Digital Active - scb[1].i2c_sda:1 */ + P10_1_SCB1_SPI_MISO = 20, /* Digital Active - scb[1].spi_miso:1 */ + P10_1_PERI_TR_IO_INPUT21 = 24, /* Digital Active - peri.tr_io_input[21]:0 */ + P10_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:1 */ + + /* P10.2 */ + P10_2_GPIO = 0, /* GPIO controls 'out' */ + P10_2_AMUXA = 4, /* Analog mux bus A */ + P10_2_AMUXB = 5, /* Analog mux bus B */ + P10_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P10_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:5 */ + P10_2_TCPWM1_LINE7 = 9, /* Digital Active - tcpwm[1].line[7]:2 */ + P10_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:46 */ + P10_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:46 */ + P10_2_LCD_COM46 = 12, /* Digital Deep Sleep - lcd.com[46]:0 */ + P10_2_LCD_SEG46 = 13, /* Digital Deep Sleep - lcd.seg[46]:0 */ + P10_2_SCB1_UART_RTS = 18, /* Digital Active - scb[1].uart_rts:1 */ + P10_2_SCB1_SPI_CLK = 20, /* Digital Active - scb[1].spi_clk:1 */ + P10_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:1 */ + + /* P10.3 */ + P10_3_GPIO = 0, /* GPIO controls 'out' */ + P10_3_AMUXA = 4, /* Analog mux bus A */ + P10_3_AMUXB = 5, /* Analog mux bus B */ + P10_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P10_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:5 */ + P10_3_TCPWM1_LINE_COMPL7 = 9, /* Digital Active - tcpwm[1].line_compl[7]:2 */ + P10_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:47 */ + P10_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:47 */ + P10_3_LCD_COM47 = 12, /* Digital Deep Sleep - lcd.com[47]:0 */ + P10_3_LCD_SEG47 = 13, /* Digital Deep Sleep - lcd.seg[47]:0 */ + P10_3_SCB1_UART_CTS = 18, /* Digital Active - scb[1].uart_cts:1 */ + P10_3_SCB1_SPI_SELECT0 = 20, /* Digital Active - scb[1].spi_select0:1 */ + P10_3_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:1 */ + + /* P10.4 */ + P10_4_GPIO = 0, /* GPIO controls 'out' */ + P10_4_AMUXA = 4, /* Analog mux bus A */ + P10_4_AMUXB = 5, /* Analog mux bus B */ + P10_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P10_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:6 */ + P10_4_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:3 */ + P10_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:48 */ + P10_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:48 */ + P10_4_LCD_COM48 = 12, /* Digital Deep Sleep - lcd.com[48]:0 */ + P10_4_LCD_SEG48 = 13, /* Digital Deep Sleep - lcd.seg[48]:0 */ + P10_4_SCB1_SPI_SELECT1 = 20, /* Digital Active - scb[1].spi_select1:1 */ + + /* P10.5 */ + P10_5_GPIO = 0, /* GPIO controls 'out' */ + P10_5_AMUXA = 4, /* Analog mux bus A */ + P10_5_AMUXB = 5, /* Analog mux bus B */ + P10_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P10_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:6 */ + P10_5_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:3 */ + P10_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:49 */ + P10_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:49 */ + P10_5_LCD_COM49 = 12, /* Digital Deep Sleep - lcd.com[49]:0 */ + P10_5_LCD_SEG49 = 13, /* Digital Deep Sleep - lcd.seg[49]:0 */ + P10_5_SCB1_SPI_SELECT2 = 20, /* Digital Active - scb[1].spi_select2:1 */ + + /* P11.0 */ + P11_0_GPIO = 0, /* GPIO controls 'out' */ + P11_0_AMUXA = 4, /* Analog mux bus A */ + P11_0_AMUXB = 5, /* Analog mux bus B */ + P11_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P11_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P11_0_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:6 */ + P11_0_TCPWM1_LINE2 = 9, /* Digital Active - tcpwm[1].line[2]:3 */ + P11_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:52 */ + P11_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:52 */ + P11_0_LCD_COM52 = 12, /* Digital Deep Sleep - lcd.com[52]:0 */ + P11_0_LCD_SEG52 = 13, /* Digital Deep Sleep - lcd.seg[52]:0 */ + P11_0_SMIF_SPI_SELECT2 = 17, /* Digital Active - smif.spi_select2 */ + P11_0_SCB5_UART_RX = 18, /* Digital Active - scb[5].uart_rx:0 */ + P11_0_SCB5_I2C_SCL = 19, /* Digital Active - scb[5].i2c_scl:0 */ + P11_0_SCB5_SPI_MOSI = 20, /* Digital Active - scb[5].spi_mosi:0 */ + P11_0_PERI_TR_IO_INPUT22 = 24, /* Digital Active - peri.tr_io_input[22]:0 */ + + /* P11.1 */ + P11_1_GPIO = 0, /* GPIO controls 'out' */ + P11_1_AMUXA = 4, /* Analog mux bus A */ + P11_1_AMUXB = 5, /* Analog mux bus B */ + P11_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P11_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P11_1_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:6 */ + P11_1_TCPWM1_LINE_COMPL2 = 9, /* Digital Active - tcpwm[1].line_compl[2]:3 */ + P11_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:53 */ + P11_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:53 */ + P11_1_LCD_COM53 = 12, /* Digital Deep Sleep - lcd.com[53]:0 */ + P11_1_LCD_SEG53 = 13, /* Digital Deep Sleep - lcd.seg[53]:0 */ + P11_1_SMIF_SPI_SELECT1 = 17, /* Digital Active - smif.spi_select1 */ + P11_1_SCB5_UART_TX = 18, /* Digital Active - scb[5].uart_tx:0 */ + P11_1_SCB5_I2C_SDA = 19, /* Digital Active - scb[5].i2c_sda:0 */ + P11_1_SCB5_SPI_MISO = 20, /* Digital Active - scb[5].spi_miso:0 */ + P11_1_PERI_TR_IO_INPUT23 = 24, /* Digital Active - peri.tr_io_input[23]:0 */ + + /* P11.2 */ + P11_2_GPIO = 0, /* GPIO controls 'out' */ + P11_2_AMUXA = 4, /* Analog mux bus A */ + P11_2_AMUXB = 5, /* Analog mux bus B */ + P11_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P11_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P11_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:6 */ + P11_2_TCPWM1_LINE3 = 9, /* Digital Active - tcpwm[1].line[3]:3 */ + P11_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:54 */ + P11_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:54 */ + P11_2_LCD_COM54 = 12, /* Digital Deep Sleep - lcd.com[54]:0 */ + P11_2_LCD_SEG54 = 13, /* Digital Deep Sleep - lcd.seg[54]:0 */ + P11_2_SMIF_SPI_SELECT0 = 17, /* Digital Active - smif.spi_select0 */ + P11_2_SCB5_UART_RTS = 18, /* Digital Active - scb[5].uart_rts:0 */ + P11_2_SCB5_SPI_CLK = 20, /* Digital Active - scb[5].spi_clk:0 */ + + /* P11.3 */ + P11_3_GPIO = 0, /* GPIO controls 'out' */ + P11_3_AMUXA = 4, /* Analog mux bus A */ + P11_3_AMUXB = 5, /* Analog mux bus B */ + P11_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P11_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P11_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:6 */ + P11_3_TCPWM1_LINE_COMPL3 = 9, /* Digital Active - tcpwm[1].line_compl[3]:3 */ + P11_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:55 */ + P11_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:55 */ + P11_3_LCD_COM55 = 12, /* Digital Deep Sleep - lcd.com[55]:0 */ + P11_3_LCD_SEG55 = 13, /* Digital Deep Sleep - lcd.seg[55]:0 */ + P11_3_SMIF_SPI_DATA3 = 17, /* Digital Active - smif.spi_data3 */ + P11_3_SCB5_UART_CTS = 18, /* Digital Active - scb[5].uart_cts:0 */ + P11_3_SCB5_SPI_SELECT0 = 20, /* Digital Active - scb[5].spi_select0:0 */ + P11_3_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:0 */ + + /* P11.4 */ + P11_4_GPIO = 0, /* GPIO controls 'out' */ + P11_4_AMUXA = 4, /* Analog mux bus A */ + P11_4_AMUXB = 5, /* Analog mux bus B */ + P11_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P11_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P11_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:7 */ + P11_4_TCPWM1_LINE4 = 9, /* Digital Active - tcpwm[1].line[4]:3 */ + P11_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:56 */ + P11_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:56 */ + P11_4_LCD_COM56 = 12, /* Digital Deep Sleep - lcd.com[56]:0 */ + P11_4_LCD_SEG56 = 13, /* Digital Deep Sleep - lcd.seg[56]:0 */ + P11_4_SMIF_SPI_DATA2 = 17, /* Digital Active - smif.spi_data2 */ + P11_4_SCB5_SPI_SELECT1 = 20, /* Digital Active - scb[5].spi_select1:0 */ + P11_4_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:0 */ + + /* P11.5 */ + P11_5_GPIO = 0, /* GPIO controls 'out' */ + P11_5_AMUXA = 4, /* Analog mux bus A */ + P11_5_AMUXB = 5, /* Analog mux bus B */ + P11_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P11_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P11_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:7 */ + P11_5_TCPWM1_LINE_COMPL4 = 9, /* Digital Active - tcpwm[1].line_compl[4]:3 */ + P11_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:57 */ + P11_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:57 */ + P11_5_LCD_COM57 = 12, /* Digital Deep Sleep - lcd.com[57]:0 */ + P11_5_LCD_SEG57 = 13, /* Digital Deep Sleep - lcd.seg[57]:0 */ + P11_5_SMIF_SPI_DATA1 = 17, /* Digital Active - smif.spi_data1 */ + P11_5_SCB5_SPI_SELECT2 = 20, /* Digital Active - scb[5].spi_select2:0 */ + + /* P11.6 */ + P11_6_GPIO = 0, /* GPIO controls 'out' */ + P11_6_AMUXA = 4, /* Analog mux bus A */ + P11_6_AMUXB = 5, /* Analog mux bus B */ + P11_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P11_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P11_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:7 */ + P11_6_TCPWM1_LINE5 = 9, /* Digital Active - tcpwm[1].line[5]:3 */ + P11_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:58 */ + P11_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:58 */ + P11_6_LCD_COM58 = 12, /* Digital Deep Sleep - lcd.com[58]:0 */ + P11_6_LCD_SEG58 = 13, /* Digital Deep Sleep - lcd.seg[58]:0 */ + P11_6_SMIF_SPI_DATA0 = 17, /* Digital Active - smif.spi_data0 */ + P11_6_SCB5_SPI_SELECT3 = 20, /* Digital Active - scb[5].spi_select3:0 */ + + /* P11.7 */ + P11_7_GPIO = 0, /* GPIO controls 'out' */ + P11_7_AMUXA = 4, /* Analog mux bus A */ + P11_7_AMUXB = 5, /* Analog mux bus B */ + P11_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P11_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P11_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:7 */ + P11_7_TCPWM1_LINE_COMPL5 = 9, /* Digital Active - tcpwm[1].line_compl[5]:3 */ + P11_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:59 */ + P11_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:59 */ + P11_7_LCD_COM59 = 12, /* Digital Deep Sleep - lcd.com[59]:0 */ + P11_7_LCD_SEG59 = 13, /* Digital Deep Sleep - lcd.seg[59]:0 */ + P11_7_SMIF_SPI_CLK = 17, /* Digital Active - smif.spi_clk */ + + /* P12.6 */ + P12_6_GPIO = 0, /* GPIO controls 'out' */ + P12_6_AMUXA = 4, /* Analog mux bus A */ + P12_6_AMUXB = 5, /* Analog mux bus B */ + P12_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P12_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P12_6_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:7 */ + P12_6_TCPWM1_LINE7 = 9, /* Digital Active - tcpwm[1].line[7]:3 */ + P12_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:62 */ + P12_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:62 */ + P12_6_LCD_COM2 = 12, /* Digital Deep Sleep - lcd.com[2]:1 */ + P12_6_LCD_SEG2 = 13, /* Digital Deep Sleep - lcd.seg[2]:1 */ + + /* P12.7 */ + P12_7_GPIO = 0, /* GPIO controls 'out' */ + P12_7_AMUXA = 4, /* Analog mux bus A */ + P12_7_AMUXB = 5, /* Analog mux bus B */ + P12_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P12_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P12_7_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:7 */ + P12_7_TCPWM1_LINE_COMPL7 = 9, /* Digital Active - tcpwm[1].line_compl[7]:3 */ + P12_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:63 */ + P12_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:63 */ + P12_7_LCD_COM3 = 12, /* Digital Deep Sleep - lcd.com[3]:1 */ + P12_7_LCD_SEG3 = 13 /* Digital Deep Sleep - lcd.seg[3]:1 */ +} en_hsiom_sel_t; + +#endif /* _GPIO_PSOC6_03_68_QFN_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_backup.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_backup.h index c7d661f17c..fa0a85324b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_backup.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_backup.h @@ -5,7 +5,7 @@ * BACKUP IP definitions * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_ble.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_ble.h index f43b6e0a1e..0e1883bd0c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_ble.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_ble.h @@ -5,7 +5,7 @@ * BLE IP definitions * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_canfd.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_canfd.h new file mode 100644 index 0000000000..c2eea3f166 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_canfd.h @@ -0,0 +1,953 @@ +/***************************************************************************//** +* \file cyip_canfd.h +* +* \brief +* CANFD IP definitions +* +* \note +* Generator version: 1.5.0.1274 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CYIP_CANFD_H_ +#define _CYIP_CANFD_H_ + +#include "cyip_headers.h" + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD_CH_M_TTCAN_SECTION_SIZE 0x00000180UL +#define CANFD_CH_SECTION_SIZE 0x00000200UL +#define CANFD_SECTION_SIZE 0x00020000UL + +/** + * \brief TTCAN 3PIP, includes FD (CANFD_CH_M_TTCAN) + */ +typedef struct { + __IM uint32_t CREL; /*!< 0x00000000 Core Release Register */ + __IM uint32_t ENDN; /*!< 0x00000004 Endian Register */ + __IM uint32_t RESERVED; + __IOM uint32_t DBTP; /*!< 0x0000000C Data Bit Timing & Prescaler Register */ + __IOM uint32_t TEST; /*!< 0x00000010 Test Register */ + __IOM uint32_t RWD; /*!< 0x00000014 RAM Watchdog */ + __IOM uint32_t CCCR; /*!< 0x00000018 CC Control Register */ + __IOM uint32_t NBTP; /*!< 0x0000001C Nominal Bit Timing & Prescaler Register */ + __IOM uint32_t TSCC; /*!< 0x00000020 Timestamp Counter Configuration */ + __IOM uint32_t TSCV; /*!< 0x00000024 Timestamp Counter Value */ + __IOM uint32_t TOCC; /*!< 0x00000028 Timeout Counter Configuration */ + __IOM uint32_t TOCV; /*!< 0x0000002C Timeout Counter Value */ + __IM uint32_t RESERVED1[4]; + __IM uint32_t ECR; /*!< 0x00000040 Error Counter Register */ + __IM uint32_t PSR; /*!< 0x00000044 Protocol Status Register */ + __IOM uint32_t TDCR; /*!< 0x00000048 Transmitter Delay Compensation Register */ + __IM uint32_t RESERVED2; + __IOM uint32_t IR; /*!< 0x00000050 Interrupt Register */ + __IOM uint32_t IE; /*!< 0x00000054 Interrupt Enable */ + __IOM uint32_t ILS; /*!< 0x00000058 Interrupt Line Select */ + __IOM uint32_t ILE; /*!< 0x0000005C Interrupt Line Enable */ + __IM uint32_t RESERVED3[8]; + __IOM uint32_t GFC; /*!< 0x00000080 Global Filter Configuration */ + __IOM uint32_t SIDFC; /*!< 0x00000084 Standard ID Filter Configuration */ + __IOM uint32_t XIDFC; /*!< 0x00000088 Extended ID Filter Configuration */ + __IM uint32_t RESERVED4; + __IOM uint32_t XIDAM; /*!< 0x00000090 Extended ID AND Mask */ + __IM uint32_t HPMS; /*!< 0x00000094 High Priority Message Status */ + __IOM uint32_t NDAT1; /*!< 0x00000098 New Data 1 */ + __IOM uint32_t NDAT2; /*!< 0x0000009C New Data 2 */ + __IOM uint32_t RXF0C; /*!< 0x000000A0 Rx FIFO 0 Configuration */ + __IM uint32_t RXF0S; /*!< 0x000000A4 Rx FIFO 0 Status */ + __IOM uint32_t RXF0A; /*!< 0x000000A8 Rx FIFO 0 Acknowledge */ + __IOM uint32_t RXBC; /*!< 0x000000AC Rx Buffer Configuration */ + __IOM uint32_t RXF1C; /*!< 0x000000B0 Rx FIFO 1 Configuration */ + __IM uint32_t RXF1S; /*!< 0x000000B4 Rx FIFO 1 Status */ + __IOM uint32_t RXF1A; /*!< 0x000000B8 Rx FIFO 1 Acknowledge */ + __IOM uint32_t RXESC; /*!< 0x000000BC Rx Buffer / FIFO Element Size Configuration */ + __IOM uint32_t TXBC; /*!< 0x000000C0 Tx Buffer Configuration */ + __IM uint32_t TXFQS; /*!< 0x000000C4 Tx FIFO/Queue Status */ + __IOM uint32_t TXESC; /*!< 0x000000C8 Tx Buffer Element Size Configuration */ + __IM uint32_t TXBRP; /*!< 0x000000CC Tx Buffer Request Pending */ + __IOM uint32_t TXBAR; /*!< 0x000000D0 Tx Buffer Add Request */ + __IOM uint32_t TXBCR; /*!< 0x000000D4 Tx Buffer Cancellation Request */ + __IM uint32_t TXBTO; /*!< 0x000000D8 Tx Buffer Transmission Occurred */ + __IM uint32_t TXBCF; /*!< 0x000000DC Tx Buffer Cancellation Finished */ + __IOM uint32_t TXBTIE; /*!< 0x000000E0 Tx Buffer Transmission Interrupt Enable */ + __IOM uint32_t TXBCIE; /*!< 0x000000E4 Tx Buffer Cancellation Finished Interrupt Enable */ + __IM uint32_t RESERVED5[2]; + __IOM uint32_t TXEFC; /*!< 0x000000F0 Tx Event FIFO Configuration */ + __IM uint32_t TXEFS; /*!< 0x000000F4 Tx Event FIFO Status */ + __IOM uint32_t TXEFA; /*!< 0x000000F8 Tx Event FIFO Acknowledge */ + __IM uint32_t RESERVED6; + __IOM uint32_t TTTMC; /*!< 0x00000100 TT Trigger Memory Configuration */ + __IOM uint32_t TTRMC; /*!< 0x00000104 TT Reference Message Configuration */ + __IOM uint32_t TTOCF; /*!< 0x00000108 TT Operation Configuration */ + __IOM uint32_t TTMLM; /*!< 0x0000010C TT Matrix Limits */ + __IOM uint32_t TURCF; /*!< 0x00000110 TUR Configuration */ + __IOM uint32_t TTOCN; /*!< 0x00000114 TT Operation Control */ + __IOM uint32_t TTGTP; /*!< 0x00000118 TT Global Time Preset */ + __IOM uint32_t TTTMK; /*!< 0x0000011C TT Time Mark */ + __IOM uint32_t TTIR; /*!< 0x00000120 TT Interrupt Register */ + __IOM uint32_t TTIE; /*!< 0x00000124 TT Interrupt Enable */ + __IOM uint32_t TTILS; /*!< 0x00000128 TT Interrupt Line Select */ + __IM uint32_t TTOST; /*!< 0x0000012C TT Operation Status */ + __IM uint32_t TURNA; /*!< 0x00000130 TUR Numerator Actual */ + __IM uint32_t TTLGT; /*!< 0x00000134 TT Local & Global Time */ + __IM uint32_t TTCTC; /*!< 0x00000138 TT Cycle Time & Count */ + __IM uint32_t TTCPT; /*!< 0x0000013C TT Capture Time */ + __IM uint32_t TTCSM; /*!< 0x00000140 TT Cycle Sync Mark */ + __IM uint32_t RESERVED7[15]; +} CANFD_CH_M_TTCAN_V1_Type; /*!< Size = 384 (0x180) */ + +/** + * \brief FIFO wrapper around M_TTCAN 3PIP, to enable DMA (CANFD_CH) + */ +typedef struct { + CANFD_CH_M_TTCAN_V1_Type M_TTCAN; /*!< 0x00000000 TTCAN 3PIP, includes FD */ + __IOM uint32_t RXFTOP_CTL; /*!< 0x00000180 Receive FIFO Top control */ + __IM uint32_t RESERVED[7]; + __IM uint32_t RXFTOP0_STAT; /*!< 0x000001A0 Receive FIFO 0 Top Status */ + __IM uint32_t RESERVED1; + __IM uint32_t RXFTOP0_DATA; /*!< 0x000001A8 Receive FIFO 0 Top Data */ + __IM uint32_t RESERVED2; + __IM uint32_t RXFTOP1_STAT; /*!< 0x000001B0 Receive FIFO 1 Top Status */ + __IM uint32_t RESERVED3; + __IM uint32_t RXFTOP1_DATA; /*!< 0x000001B8 Receive FIFO 1 Top Data */ + __IM uint32_t RESERVED4[17]; +} CANFD_CH_V1_Type; /*!< Size = 512 (0x200) */ + +/** + * \brief CAN Controller (CANFD) + */ +typedef struct { + CANFD_CH_V1_Type CH[8]; /*!< 0x00000000 FIFO wrapper around M_TTCAN 3PIP, to enable DMA */ + __IOM uint32_t CTL; /*!< 0x00001000 Global CAN control register */ + __IM uint32_t STATUS; /*!< 0x00001004 Global CAN status register */ + __IM uint32_t RESERVED[2]; + __IM uint32_t INTR0_CAUSE; /*!< 0x00001010 Consolidated interrupt0 cause register */ + __IM uint32_t INTR1_CAUSE; /*!< 0x00001014 Consolidated interrupt1 cause register */ + __IM uint32_t RESERVED1[2]; + __IOM uint32_t TS_CTL; /*!< 0x00001020 Time Stamp control register */ + __IOM uint32_t TS_CNT; /*!< 0x00001024 Time Stamp counter value */ + __IM uint32_t RESERVED2[22]; + __IOM uint32_t ECC_CTL; /*!< 0x00001080 ECC control */ + __IOM uint32_t ECC_ERR_INJ; /*!< 0x00001084 ECC error injection */ +} CANFD_V1_Type; /*!< Size = 4232 (0x1088) */ + + +/* CANFD_CH_M_TTCAN.CREL */ +#define CANFD_CH_M_TTCAN_CREL_DAY_Pos 0UL +#define CANFD_CH_M_TTCAN_CREL_DAY_Msk 0xFFUL +#define CANFD_CH_M_TTCAN_CREL_MON_Pos 8UL +#define CANFD_CH_M_TTCAN_CREL_MON_Msk 0xFF00UL +#define CANFD_CH_M_TTCAN_CREL_YEAR_Pos 16UL +#define CANFD_CH_M_TTCAN_CREL_YEAR_Msk 0xF0000UL +#define CANFD_CH_M_TTCAN_CREL_SUBSTEP_Pos 20UL +#define CANFD_CH_M_TTCAN_CREL_SUBSTEP_Msk 0xF00000UL +#define CANFD_CH_M_TTCAN_CREL_STEP_Pos 24UL +#define CANFD_CH_M_TTCAN_CREL_STEP_Msk 0xF000000UL +#define CANFD_CH_M_TTCAN_CREL_REL_Pos 28UL +#define CANFD_CH_M_TTCAN_CREL_REL_Msk 0xF0000000UL +/* CANFD_CH_M_TTCAN.ENDN */ +#define CANFD_CH_M_TTCAN_ENDN_ETV_Pos 0UL +#define CANFD_CH_M_TTCAN_ENDN_ETV_Msk 0xFFFFFFFFUL +/* CANFD_CH_M_TTCAN.DBTP */ +#define CANFD_CH_M_TTCAN_DBTP_DSJW_Pos 0UL +#define CANFD_CH_M_TTCAN_DBTP_DSJW_Msk 0xFUL +#define CANFD_CH_M_TTCAN_DBTP_DTSEG2_Pos 4UL +#define CANFD_CH_M_TTCAN_DBTP_DTSEG2_Msk 0xF0UL +#define CANFD_CH_M_TTCAN_DBTP_DTSEG1_Pos 8UL +#define CANFD_CH_M_TTCAN_DBTP_DTSEG1_Msk 0x1F00UL +#define CANFD_CH_M_TTCAN_DBTP_DBRP_Pos 16UL +#define CANFD_CH_M_TTCAN_DBTP_DBRP_Msk 0x1F0000UL +#define CANFD_CH_M_TTCAN_DBTP_TDC_Pos 23UL +#define CANFD_CH_M_TTCAN_DBTP_TDC_Msk 0x800000UL +/* CANFD_CH_M_TTCAN.TEST */ +#define CANFD_CH_M_TTCAN_TEST_TAM_Pos 0UL +#define CANFD_CH_M_TTCAN_TEST_TAM_Msk 0x1UL +#define CANFD_CH_M_TTCAN_TEST_TAT_Pos 1UL +#define CANFD_CH_M_TTCAN_TEST_TAT_Msk 0x2UL +#define CANFD_CH_M_TTCAN_TEST_CAM_Pos 2UL +#define CANFD_CH_M_TTCAN_TEST_CAM_Msk 0x4UL +#define CANFD_CH_M_TTCAN_TEST_CAT_Pos 3UL +#define CANFD_CH_M_TTCAN_TEST_CAT_Msk 0x8UL +#define CANFD_CH_M_TTCAN_TEST_LBCK_Pos 4UL +#define CANFD_CH_M_TTCAN_TEST_LBCK_Msk 0x10UL +#define CANFD_CH_M_TTCAN_TEST_TX_Pos 5UL +#define CANFD_CH_M_TTCAN_TEST_TX_Msk 0x60UL +#define CANFD_CH_M_TTCAN_TEST_RX_Pos 7UL +#define CANFD_CH_M_TTCAN_TEST_RX_Msk 0x80UL +/* CANFD_CH_M_TTCAN.RWD */ +#define CANFD_CH_M_TTCAN_RWD_WDC_Pos 0UL +#define CANFD_CH_M_TTCAN_RWD_WDC_Msk 0xFFUL +#define CANFD_CH_M_TTCAN_RWD_WDV_Pos 8UL +#define CANFD_CH_M_TTCAN_RWD_WDV_Msk 0xFF00UL +/* CANFD_CH_M_TTCAN.CCCR */ +#define CANFD_CH_M_TTCAN_CCCR_INIT_Pos 0UL +#define CANFD_CH_M_TTCAN_CCCR_INIT_Msk 0x1UL +#define CANFD_CH_M_TTCAN_CCCR_CCE_Pos 1UL +#define CANFD_CH_M_TTCAN_CCCR_CCE_Msk 0x2UL +#define CANFD_CH_M_TTCAN_CCCR_ASM_Pos 2UL +#define CANFD_CH_M_TTCAN_CCCR_ASM_Msk 0x4UL +#define CANFD_CH_M_TTCAN_CCCR_CSA_Pos 3UL +#define CANFD_CH_M_TTCAN_CCCR_CSA_Msk 0x8UL +#define CANFD_CH_M_TTCAN_CCCR_CSR_Pos 4UL +#define CANFD_CH_M_TTCAN_CCCR_CSR_Msk 0x10UL +#define CANFD_CH_M_TTCAN_CCCR_MON__Pos 5UL +#define CANFD_CH_M_TTCAN_CCCR_MON__Msk 0x20UL +#define CANFD_CH_M_TTCAN_CCCR_DAR_Pos 6UL +#define CANFD_CH_M_TTCAN_CCCR_DAR_Msk 0x40UL +#define CANFD_CH_M_TTCAN_CCCR_TEST_Pos 7UL +#define CANFD_CH_M_TTCAN_CCCR_TEST_Msk 0x80UL +#define CANFD_CH_M_TTCAN_CCCR_FDOE_Pos 8UL +#define CANFD_CH_M_TTCAN_CCCR_FDOE_Msk 0x100UL +#define CANFD_CH_M_TTCAN_CCCR_BRSE_Pos 9UL +#define CANFD_CH_M_TTCAN_CCCR_BRSE_Msk 0x200UL +#define CANFD_CH_M_TTCAN_CCCR_PXHD_Pos 12UL +#define CANFD_CH_M_TTCAN_CCCR_PXHD_Msk 0x1000UL +#define CANFD_CH_M_TTCAN_CCCR_EFBI_Pos 13UL +#define CANFD_CH_M_TTCAN_CCCR_EFBI_Msk 0x2000UL +#define CANFD_CH_M_TTCAN_CCCR_TXP_Pos 14UL +#define CANFD_CH_M_TTCAN_CCCR_TXP_Msk 0x4000UL +#define CANFD_CH_M_TTCAN_CCCR_NISO_Pos 15UL +#define CANFD_CH_M_TTCAN_CCCR_NISO_Msk 0x8000UL +/* CANFD_CH_M_TTCAN.NBTP */ +#define CANFD_CH_M_TTCAN_NBTP_NTSEG2_Pos 0UL +#define CANFD_CH_M_TTCAN_NBTP_NTSEG2_Msk 0x7FUL +#define CANFD_CH_M_TTCAN_NBTP_NTSEG1_Pos 8UL +#define CANFD_CH_M_TTCAN_NBTP_NTSEG1_Msk 0xFF00UL +#define CANFD_CH_M_TTCAN_NBTP_NBRP_Pos 16UL +#define CANFD_CH_M_TTCAN_NBTP_NBRP_Msk 0x1FF0000UL +#define CANFD_CH_M_TTCAN_NBTP_NSJW_Pos 25UL +#define CANFD_CH_M_TTCAN_NBTP_NSJW_Msk 0xFE000000UL +/* CANFD_CH_M_TTCAN.TSCC */ +#define CANFD_CH_M_TTCAN_TSCC_TSS_Pos 0UL +#define CANFD_CH_M_TTCAN_TSCC_TSS_Msk 0x3UL +#define CANFD_CH_M_TTCAN_TSCC_TCP_Pos 16UL +#define CANFD_CH_M_TTCAN_TSCC_TCP_Msk 0xF0000UL +/* CANFD_CH_M_TTCAN.TSCV */ +#define CANFD_CH_M_TTCAN_TSCV_TSC_Pos 0UL +#define CANFD_CH_M_TTCAN_TSCV_TSC_Msk 0xFFFFUL +/* CANFD_CH_M_TTCAN.TOCC */ +#define CANFD_CH_M_TTCAN_TOCC_ETOC_Pos 0UL +#define CANFD_CH_M_TTCAN_TOCC_ETOC_Msk 0x1UL +#define CANFD_CH_M_TTCAN_TOCC_TOS_Pos 1UL +#define CANFD_CH_M_TTCAN_TOCC_TOS_Msk 0x6UL +#define CANFD_CH_M_TTCAN_TOCC_TOP_Pos 16UL +#define CANFD_CH_M_TTCAN_TOCC_TOP_Msk 0xFFFF0000UL +/* CANFD_CH_M_TTCAN.TOCV */ +#define CANFD_CH_M_TTCAN_TOCV_TOC_Pos 0UL +#define CANFD_CH_M_TTCAN_TOCV_TOC_Msk 0xFFFFUL +/* CANFD_CH_M_TTCAN.ECR */ +#define CANFD_CH_M_TTCAN_ECR_TEC_Pos 0UL +#define CANFD_CH_M_TTCAN_ECR_TEC_Msk 0xFFUL +#define CANFD_CH_M_TTCAN_ECR_REC_Pos 8UL +#define CANFD_CH_M_TTCAN_ECR_REC_Msk 0x7F00UL +#define CANFD_CH_M_TTCAN_ECR_RP_Pos 15UL +#define CANFD_CH_M_TTCAN_ECR_RP_Msk 0x8000UL +#define CANFD_CH_M_TTCAN_ECR_CEL_Pos 16UL +#define CANFD_CH_M_TTCAN_ECR_CEL_Msk 0xFF0000UL +/* CANFD_CH_M_TTCAN.PSR */ +#define CANFD_CH_M_TTCAN_PSR_LEC_Pos 0UL +#define CANFD_CH_M_TTCAN_PSR_LEC_Msk 0x7UL +#define CANFD_CH_M_TTCAN_PSR_ACT_Pos 3UL +#define CANFD_CH_M_TTCAN_PSR_ACT_Msk 0x18UL +#define CANFD_CH_M_TTCAN_PSR_EP_Pos 5UL +#define CANFD_CH_M_TTCAN_PSR_EP_Msk 0x20UL +#define CANFD_CH_M_TTCAN_PSR_EW_Pos 6UL +#define CANFD_CH_M_TTCAN_PSR_EW_Msk 0x40UL +#define CANFD_CH_M_TTCAN_PSR_BO_Pos 7UL +#define CANFD_CH_M_TTCAN_PSR_BO_Msk 0x80UL +#define CANFD_CH_M_TTCAN_PSR_DLEC_Pos 8UL +#define CANFD_CH_M_TTCAN_PSR_DLEC_Msk 0x700UL +#define CANFD_CH_M_TTCAN_PSR_RESI_Pos 11UL +#define CANFD_CH_M_TTCAN_PSR_RESI_Msk 0x800UL +#define CANFD_CH_M_TTCAN_PSR_RBRS_Pos 12UL +#define CANFD_CH_M_TTCAN_PSR_RBRS_Msk 0x1000UL +#define CANFD_CH_M_TTCAN_PSR_RFDF_Pos 13UL +#define CANFD_CH_M_TTCAN_PSR_RFDF_Msk 0x2000UL +#define CANFD_CH_M_TTCAN_PSR_PXE_Pos 14UL +#define CANFD_CH_M_TTCAN_PSR_PXE_Msk 0x4000UL +#define CANFD_CH_M_TTCAN_PSR_TDCV_Pos 16UL +#define CANFD_CH_M_TTCAN_PSR_TDCV_Msk 0x7F0000UL +/* CANFD_CH_M_TTCAN.TDCR */ +#define CANFD_CH_M_TTCAN_TDCR_TDCF_Pos 0UL +#define CANFD_CH_M_TTCAN_TDCR_TDCF_Msk 0x7FUL +#define CANFD_CH_M_TTCAN_TDCR_TDCO_Pos 8UL +#define CANFD_CH_M_TTCAN_TDCR_TDCO_Msk 0x7F00UL +/* CANFD_CH_M_TTCAN.IR */ +#define CANFD_CH_M_TTCAN_IR_RF0N_Pos 0UL +#define CANFD_CH_M_TTCAN_IR_RF0N_Msk 0x1UL +#define CANFD_CH_M_TTCAN_IR_RF0W_Pos 1UL +#define CANFD_CH_M_TTCAN_IR_RF0W_Msk 0x2UL +#define CANFD_CH_M_TTCAN_IR_RF0F_Pos 2UL +#define CANFD_CH_M_TTCAN_IR_RF0F_Msk 0x4UL +#define CANFD_CH_M_TTCAN_IR_RF0L__Pos 3UL +#define CANFD_CH_M_TTCAN_IR_RF0L__Msk 0x8UL +#define CANFD_CH_M_TTCAN_IR_RF1N_Pos 4UL +#define CANFD_CH_M_TTCAN_IR_RF1N_Msk 0x10UL +#define CANFD_CH_M_TTCAN_IR_RF1W_Pos 5UL +#define CANFD_CH_M_TTCAN_IR_RF1W_Msk 0x20UL +#define CANFD_CH_M_TTCAN_IR_RF1F_Pos 6UL +#define CANFD_CH_M_TTCAN_IR_RF1F_Msk 0x40UL +#define CANFD_CH_M_TTCAN_IR_RF1L__Pos 7UL +#define CANFD_CH_M_TTCAN_IR_RF1L__Msk 0x80UL +#define CANFD_CH_M_TTCAN_IR_HPM_Pos 8UL +#define CANFD_CH_M_TTCAN_IR_HPM_Msk 0x100UL +#define CANFD_CH_M_TTCAN_IR_TC_Pos 9UL +#define CANFD_CH_M_TTCAN_IR_TC_Msk 0x200UL +#define CANFD_CH_M_TTCAN_IR_TCF_Pos 10UL +#define CANFD_CH_M_TTCAN_IR_TCF_Msk 0x400UL +#define CANFD_CH_M_TTCAN_IR_TFE_Pos 11UL +#define CANFD_CH_M_TTCAN_IR_TFE_Msk 0x800UL +#define CANFD_CH_M_TTCAN_IR_TEFN_Pos 12UL +#define CANFD_CH_M_TTCAN_IR_TEFN_Msk 0x1000UL +#define CANFD_CH_M_TTCAN_IR_TEFW_Pos 13UL +#define CANFD_CH_M_TTCAN_IR_TEFW_Msk 0x2000UL +#define CANFD_CH_M_TTCAN_IR_TEFF_Pos 14UL +#define CANFD_CH_M_TTCAN_IR_TEFF_Msk 0x4000UL +#define CANFD_CH_M_TTCAN_IR_TEFL__Pos 15UL +#define CANFD_CH_M_TTCAN_IR_TEFL__Msk 0x8000UL +#define CANFD_CH_M_TTCAN_IR_TSW_Pos 16UL +#define CANFD_CH_M_TTCAN_IR_TSW_Msk 0x10000UL +#define CANFD_CH_M_TTCAN_IR_MRAF_Pos 17UL +#define CANFD_CH_M_TTCAN_IR_MRAF_Msk 0x20000UL +#define CANFD_CH_M_TTCAN_IR_TOO_Pos 18UL +#define CANFD_CH_M_TTCAN_IR_TOO_Msk 0x40000UL +#define CANFD_CH_M_TTCAN_IR_DRX_Pos 19UL +#define CANFD_CH_M_TTCAN_IR_DRX_Msk 0x80000UL +#define CANFD_CH_M_TTCAN_IR_BEC_Pos 20UL +#define CANFD_CH_M_TTCAN_IR_BEC_Msk 0x100000UL +#define CANFD_CH_M_TTCAN_IR_BEU_Pos 21UL +#define CANFD_CH_M_TTCAN_IR_BEU_Msk 0x200000UL +#define CANFD_CH_M_TTCAN_IR_ELO_Pos 22UL +#define CANFD_CH_M_TTCAN_IR_ELO_Msk 0x400000UL +#define CANFD_CH_M_TTCAN_IR_EP__Pos 23UL +#define CANFD_CH_M_TTCAN_IR_EP__Msk 0x800000UL +#define CANFD_CH_M_TTCAN_IR_EW__Pos 24UL +#define CANFD_CH_M_TTCAN_IR_EW__Msk 0x1000000UL +#define CANFD_CH_M_TTCAN_IR_BO__Pos 25UL +#define CANFD_CH_M_TTCAN_IR_BO__Msk 0x2000000UL +#define CANFD_CH_M_TTCAN_IR_WDI_Pos 26UL +#define CANFD_CH_M_TTCAN_IR_WDI_Msk 0x4000000UL +#define CANFD_CH_M_TTCAN_IR_PEA_Pos 27UL +#define CANFD_CH_M_TTCAN_IR_PEA_Msk 0x8000000UL +#define CANFD_CH_M_TTCAN_IR_PED_Pos 28UL +#define CANFD_CH_M_TTCAN_IR_PED_Msk 0x10000000UL +#define CANFD_CH_M_TTCAN_IR_ARA_Pos 29UL +#define CANFD_CH_M_TTCAN_IR_ARA_Msk 0x20000000UL +/* CANFD_CH_M_TTCAN.IE */ +#define CANFD_CH_M_TTCAN_IE_RF0NE_Pos 0UL +#define CANFD_CH_M_TTCAN_IE_RF0NE_Msk 0x1UL +#define CANFD_CH_M_TTCAN_IE_RF0WE_Pos 1UL +#define CANFD_CH_M_TTCAN_IE_RF0WE_Msk 0x2UL +#define CANFD_CH_M_TTCAN_IE_RF0FE_Pos 2UL +#define CANFD_CH_M_TTCAN_IE_RF0FE_Msk 0x4UL +#define CANFD_CH_M_TTCAN_IE_RF0LE_Pos 3UL +#define CANFD_CH_M_TTCAN_IE_RF0LE_Msk 0x8UL +#define CANFD_CH_M_TTCAN_IE_RF1NE_Pos 4UL +#define CANFD_CH_M_TTCAN_IE_RF1NE_Msk 0x10UL +#define CANFD_CH_M_TTCAN_IE_RF1WE_Pos 5UL +#define CANFD_CH_M_TTCAN_IE_RF1WE_Msk 0x20UL +#define CANFD_CH_M_TTCAN_IE_RF1FE_Pos 6UL +#define CANFD_CH_M_TTCAN_IE_RF1FE_Msk 0x40UL +#define CANFD_CH_M_TTCAN_IE_RF1LE_Pos 7UL +#define CANFD_CH_M_TTCAN_IE_RF1LE_Msk 0x80UL +#define CANFD_CH_M_TTCAN_IE_HPME_Pos 8UL +#define CANFD_CH_M_TTCAN_IE_HPME_Msk 0x100UL +#define CANFD_CH_M_TTCAN_IE_TCE_Pos 9UL +#define CANFD_CH_M_TTCAN_IE_TCE_Msk 0x200UL +#define CANFD_CH_M_TTCAN_IE_TCFE_Pos 10UL +#define CANFD_CH_M_TTCAN_IE_TCFE_Msk 0x400UL +#define CANFD_CH_M_TTCAN_IE_TFEE_Pos 11UL +#define CANFD_CH_M_TTCAN_IE_TFEE_Msk 0x800UL +#define CANFD_CH_M_TTCAN_IE_TEFNE_Pos 12UL +#define CANFD_CH_M_TTCAN_IE_TEFNE_Msk 0x1000UL +#define CANFD_CH_M_TTCAN_IE_TEFWE_Pos 13UL +#define CANFD_CH_M_TTCAN_IE_TEFWE_Msk 0x2000UL +#define CANFD_CH_M_TTCAN_IE_TEFFE_Pos 14UL +#define CANFD_CH_M_TTCAN_IE_TEFFE_Msk 0x4000UL +#define CANFD_CH_M_TTCAN_IE_TEFLE_Pos 15UL +#define CANFD_CH_M_TTCAN_IE_TEFLE_Msk 0x8000UL +#define CANFD_CH_M_TTCAN_IE_TSWE_Pos 16UL +#define CANFD_CH_M_TTCAN_IE_TSWE_Msk 0x10000UL +#define CANFD_CH_M_TTCAN_IE_MRAFE_Pos 17UL +#define CANFD_CH_M_TTCAN_IE_MRAFE_Msk 0x20000UL +#define CANFD_CH_M_TTCAN_IE_TOOE_Pos 18UL +#define CANFD_CH_M_TTCAN_IE_TOOE_Msk 0x40000UL +#define CANFD_CH_M_TTCAN_IE_DRXE_Pos 19UL +#define CANFD_CH_M_TTCAN_IE_DRXE_Msk 0x80000UL +#define CANFD_CH_M_TTCAN_IE_BECE_Pos 20UL +#define CANFD_CH_M_TTCAN_IE_BECE_Msk 0x100000UL +#define CANFD_CH_M_TTCAN_IE_BEUE_Pos 21UL +#define CANFD_CH_M_TTCAN_IE_BEUE_Msk 0x200000UL +#define CANFD_CH_M_TTCAN_IE_ELOE_Pos 22UL +#define CANFD_CH_M_TTCAN_IE_ELOE_Msk 0x400000UL +#define CANFD_CH_M_TTCAN_IE_EPE_Pos 23UL +#define CANFD_CH_M_TTCAN_IE_EPE_Msk 0x800000UL +#define CANFD_CH_M_TTCAN_IE_EWE_Pos 24UL +#define CANFD_CH_M_TTCAN_IE_EWE_Msk 0x1000000UL +#define CANFD_CH_M_TTCAN_IE_BOE_Pos 25UL +#define CANFD_CH_M_TTCAN_IE_BOE_Msk 0x2000000UL +#define CANFD_CH_M_TTCAN_IE_WDIE_Pos 26UL +#define CANFD_CH_M_TTCAN_IE_WDIE_Msk 0x4000000UL +#define CANFD_CH_M_TTCAN_IE_PEAE_Pos 27UL +#define CANFD_CH_M_TTCAN_IE_PEAE_Msk 0x8000000UL +#define CANFD_CH_M_TTCAN_IE_PEDE_Pos 28UL +#define CANFD_CH_M_TTCAN_IE_PEDE_Msk 0x10000000UL +#define CANFD_CH_M_TTCAN_IE_ARAE_Pos 29UL +#define CANFD_CH_M_TTCAN_IE_ARAE_Msk 0x20000000UL +/* CANFD_CH_M_TTCAN.ILS */ +#define CANFD_CH_M_TTCAN_ILS_RF0NL_Pos 0UL +#define CANFD_CH_M_TTCAN_ILS_RF0NL_Msk 0x1UL +#define CANFD_CH_M_TTCAN_ILS_RF0WL_Pos 1UL +#define CANFD_CH_M_TTCAN_ILS_RF0WL_Msk 0x2UL +#define CANFD_CH_M_TTCAN_ILS_RF0FL_Pos 2UL +#define CANFD_CH_M_TTCAN_ILS_RF0FL_Msk 0x4UL +#define CANFD_CH_M_TTCAN_ILS_RF0LL_Pos 3UL +#define CANFD_CH_M_TTCAN_ILS_RF0LL_Msk 0x8UL +#define CANFD_CH_M_TTCAN_ILS_RF1NL_Pos 4UL +#define CANFD_CH_M_TTCAN_ILS_RF1NL_Msk 0x10UL +#define CANFD_CH_M_TTCAN_ILS_RF1WL_Pos 5UL +#define CANFD_CH_M_TTCAN_ILS_RF1WL_Msk 0x20UL +#define CANFD_CH_M_TTCAN_ILS_RF1FL_Pos 6UL +#define CANFD_CH_M_TTCAN_ILS_RF1FL_Msk 0x40UL +#define CANFD_CH_M_TTCAN_ILS_RF1LL_Pos 7UL +#define CANFD_CH_M_TTCAN_ILS_RF1LL_Msk 0x80UL +#define CANFD_CH_M_TTCAN_ILS_HPML_Pos 8UL +#define CANFD_CH_M_TTCAN_ILS_HPML_Msk 0x100UL +#define CANFD_CH_M_TTCAN_ILS_TCL_Pos 9UL +#define CANFD_CH_M_TTCAN_ILS_TCL_Msk 0x200UL +#define CANFD_CH_M_TTCAN_ILS_TCFL_Pos 10UL +#define CANFD_CH_M_TTCAN_ILS_TCFL_Msk 0x400UL +#define CANFD_CH_M_TTCAN_ILS_TFEL_Pos 11UL +#define CANFD_CH_M_TTCAN_ILS_TFEL_Msk 0x800UL +#define CANFD_CH_M_TTCAN_ILS_TEFNL_Pos 12UL +#define CANFD_CH_M_TTCAN_ILS_TEFNL_Msk 0x1000UL +#define CANFD_CH_M_TTCAN_ILS_TEFWL_Pos 13UL +#define CANFD_CH_M_TTCAN_ILS_TEFWL_Msk 0x2000UL +#define CANFD_CH_M_TTCAN_ILS_TEFFL_Pos 14UL +#define CANFD_CH_M_TTCAN_ILS_TEFFL_Msk 0x4000UL +#define CANFD_CH_M_TTCAN_ILS_TEFLL_Pos 15UL +#define CANFD_CH_M_TTCAN_ILS_TEFLL_Msk 0x8000UL +#define CANFD_CH_M_TTCAN_ILS_TSWL_Pos 16UL +#define CANFD_CH_M_TTCAN_ILS_TSWL_Msk 0x10000UL +#define CANFD_CH_M_TTCAN_ILS_MRAFL_Pos 17UL +#define CANFD_CH_M_TTCAN_ILS_MRAFL_Msk 0x20000UL +#define CANFD_CH_M_TTCAN_ILS_TOOL_Pos 18UL +#define CANFD_CH_M_TTCAN_ILS_TOOL_Msk 0x40000UL +#define CANFD_CH_M_TTCAN_ILS_DRXL_Pos 19UL +#define CANFD_CH_M_TTCAN_ILS_DRXL_Msk 0x80000UL +#define CANFD_CH_M_TTCAN_ILS_BECL_Pos 20UL +#define CANFD_CH_M_TTCAN_ILS_BECL_Msk 0x100000UL +#define CANFD_CH_M_TTCAN_ILS_BEUL_Pos 21UL +#define CANFD_CH_M_TTCAN_ILS_BEUL_Msk 0x200000UL +#define CANFD_CH_M_TTCAN_ILS_ELOL_Pos 22UL +#define CANFD_CH_M_TTCAN_ILS_ELOL_Msk 0x400000UL +#define CANFD_CH_M_TTCAN_ILS_EPL_Pos 23UL +#define CANFD_CH_M_TTCAN_ILS_EPL_Msk 0x800000UL +#define CANFD_CH_M_TTCAN_ILS_EWL_Pos 24UL +#define CANFD_CH_M_TTCAN_ILS_EWL_Msk 0x1000000UL +#define CANFD_CH_M_TTCAN_ILS_BOL_Pos 25UL +#define CANFD_CH_M_TTCAN_ILS_BOL_Msk 0x2000000UL +#define CANFD_CH_M_TTCAN_ILS_WDIL_Pos 26UL +#define CANFD_CH_M_TTCAN_ILS_WDIL_Msk 0x4000000UL +#define CANFD_CH_M_TTCAN_ILS_PEAL_Pos 27UL +#define CANFD_CH_M_TTCAN_ILS_PEAL_Msk 0x8000000UL +#define CANFD_CH_M_TTCAN_ILS_PEDL_Pos 28UL +#define CANFD_CH_M_TTCAN_ILS_PEDL_Msk 0x10000000UL +#define CANFD_CH_M_TTCAN_ILS_ARAL_Pos 29UL +#define CANFD_CH_M_TTCAN_ILS_ARAL_Msk 0x20000000UL +/* CANFD_CH_M_TTCAN.ILE */ +#define CANFD_CH_M_TTCAN_ILE_EINT0_Pos 0UL +#define CANFD_CH_M_TTCAN_ILE_EINT0_Msk 0x1UL +#define CANFD_CH_M_TTCAN_ILE_EINT1_Pos 1UL +#define CANFD_CH_M_TTCAN_ILE_EINT1_Msk 0x2UL +/* CANFD_CH_M_TTCAN.GFC */ +#define CANFD_CH_M_TTCAN_GFC_RRFE_Pos 0UL +#define CANFD_CH_M_TTCAN_GFC_RRFE_Msk 0x1UL +#define CANFD_CH_M_TTCAN_GFC_RRFS_Pos 1UL +#define CANFD_CH_M_TTCAN_GFC_RRFS_Msk 0x2UL +#define CANFD_CH_M_TTCAN_GFC_ANFE_Pos 2UL +#define CANFD_CH_M_TTCAN_GFC_ANFE_Msk 0xCUL +#define CANFD_CH_M_TTCAN_GFC_ANFS_Pos 4UL +#define CANFD_CH_M_TTCAN_GFC_ANFS_Msk 0x30UL +/* CANFD_CH_M_TTCAN.SIDFC */ +#define CANFD_CH_M_TTCAN_SIDFC_FLSSA_Pos 2UL +#define CANFD_CH_M_TTCAN_SIDFC_FLSSA_Msk 0xFFFCUL +#define CANFD_CH_M_TTCAN_SIDFC_LSS_Pos 16UL +#define CANFD_CH_M_TTCAN_SIDFC_LSS_Msk 0xFF0000UL +/* CANFD_CH_M_TTCAN.XIDFC */ +#define CANFD_CH_M_TTCAN_XIDFC_FLESA_Pos 2UL +#define CANFD_CH_M_TTCAN_XIDFC_FLESA_Msk 0xFFFCUL +#define CANFD_CH_M_TTCAN_XIDFC_LSE_Pos 16UL +#define CANFD_CH_M_TTCAN_XIDFC_LSE_Msk 0x7F0000UL +/* CANFD_CH_M_TTCAN.XIDAM */ +#define CANFD_CH_M_TTCAN_XIDAM_EIDM_Pos 0UL +#define CANFD_CH_M_TTCAN_XIDAM_EIDM_Msk 0x1FFFFFFFUL +/* CANFD_CH_M_TTCAN.HPMS */ +#define CANFD_CH_M_TTCAN_HPMS_BIDX_Pos 0UL +#define CANFD_CH_M_TTCAN_HPMS_BIDX_Msk 0x3FUL +#define CANFD_CH_M_TTCAN_HPMS_MSI_Pos 6UL +#define CANFD_CH_M_TTCAN_HPMS_MSI_Msk 0xC0UL +#define CANFD_CH_M_TTCAN_HPMS_FIDX_Pos 8UL +#define CANFD_CH_M_TTCAN_HPMS_FIDX_Msk 0x7F00UL +#define CANFD_CH_M_TTCAN_HPMS_FLST_Pos 15UL +#define CANFD_CH_M_TTCAN_HPMS_FLST_Msk 0x8000UL +/* CANFD_CH_M_TTCAN.NDAT1 */ +#define CANFD_CH_M_TTCAN_NDAT1_ND_Pos 0UL +#define CANFD_CH_M_TTCAN_NDAT1_ND_Msk 0xFFFFFFFFUL +/* CANFD_CH_M_TTCAN.NDAT2 */ +#define CANFD_CH_M_TTCAN_NDAT2_ND_Pos 0UL +#define CANFD_CH_M_TTCAN_NDAT2_ND_Msk 0xFFFFFFFFUL +/* CANFD_CH_M_TTCAN.RXF0C */ +#define CANFD_CH_M_TTCAN_RXF0C_F0SA_Pos 2UL +#define CANFD_CH_M_TTCAN_RXF0C_F0SA_Msk 0xFFFCUL +#define CANFD_CH_M_TTCAN_RXF0C_F0S_Pos 16UL +#define CANFD_CH_M_TTCAN_RXF0C_F0S_Msk 0x7F0000UL +#define CANFD_CH_M_TTCAN_RXF0C_F0WM_Pos 24UL +#define CANFD_CH_M_TTCAN_RXF0C_F0WM_Msk 0x7F000000UL +#define CANFD_CH_M_TTCAN_RXF0C_F0OM_Pos 31UL +#define CANFD_CH_M_TTCAN_RXF0C_F0OM_Msk 0x80000000UL +/* CANFD_CH_M_TTCAN.RXF0S */ +#define CANFD_CH_M_TTCAN_RXF0S_F0FL_Pos 0UL +#define CANFD_CH_M_TTCAN_RXF0S_F0FL_Msk 0x7FUL +#define CANFD_CH_M_TTCAN_RXF0S_F0GI_Pos 8UL +#define CANFD_CH_M_TTCAN_RXF0S_F0GI_Msk 0x3F00UL +#define CANFD_CH_M_TTCAN_RXF0S_F0PI_Pos 16UL +#define CANFD_CH_M_TTCAN_RXF0S_F0PI_Msk 0x3F0000UL +#define CANFD_CH_M_TTCAN_RXF0S_F0F_Pos 24UL +#define CANFD_CH_M_TTCAN_RXF0S_F0F_Msk 0x1000000UL +#define CANFD_CH_M_TTCAN_RXF0S_RF0L_Pos 25UL +#define CANFD_CH_M_TTCAN_RXF0S_RF0L_Msk 0x2000000UL +/* CANFD_CH_M_TTCAN.RXF0A */ +#define CANFD_CH_M_TTCAN_RXF0A_F0AI_Pos 0UL +#define CANFD_CH_M_TTCAN_RXF0A_F0AI_Msk 0x3FUL +/* CANFD_CH_M_TTCAN.RXBC */ +#define CANFD_CH_M_TTCAN_RXBC_RBSA_Pos 2UL +#define CANFD_CH_M_TTCAN_RXBC_RBSA_Msk 0xFFFCUL +/* CANFD_CH_M_TTCAN.RXF1C */ +#define CANFD_CH_M_TTCAN_RXF1C_F1SA_Pos 2UL +#define CANFD_CH_M_TTCAN_RXF1C_F1SA_Msk 0xFFFCUL +#define CANFD_CH_M_TTCAN_RXF1C_F1S_Pos 16UL +#define CANFD_CH_M_TTCAN_RXF1C_F1S_Msk 0x7F0000UL +#define CANFD_CH_M_TTCAN_RXF1C_F1WM_Pos 24UL +#define CANFD_CH_M_TTCAN_RXF1C_F1WM_Msk 0x7F000000UL +#define CANFD_CH_M_TTCAN_RXF1C_F1OM_Pos 31UL +#define CANFD_CH_M_TTCAN_RXF1C_F1OM_Msk 0x80000000UL +/* CANFD_CH_M_TTCAN.RXF1S */ +#define CANFD_CH_M_TTCAN_RXF1S_F1FL_Pos 0UL +#define CANFD_CH_M_TTCAN_RXF1S_F1FL_Msk 0x7FUL +#define CANFD_CH_M_TTCAN_RXF1S_F1GI_Pos 8UL +#define CANFD_CH_M_TTCAN_RXF1S_F1GI_Msk 0x3F00UL +#define CANFD_CH_M_TTCAN_RXF1S_F1PI_Pos 16UL +#define CANFD_CH_M_TTCAN_RXF1S_F1PI_Msk 0x3F0000UL +#define CANFD_CH_M_TTCAN_RXF1S_F1F_Pos 24UL +#define CANFD_CH_M_TTCAN_RXF1S_F1F_Msk 0x1000000UL +#define CANFD_CH_M_TTCAN_RXF1S_RF1L_Pos 25UL +#define CANFD_CH_M_TTCAN_RXF1S_RF1L_Msk 0x2000000UL +#define CANFD_CH_M_TTCAN_RXF1S_DMS_Pos 30UL +#define CANFD_CH_M_TTCAN_RXF1S_DMS_Msk 0xC0000000UL +/* CANFD_CH_M_TTCAN.RXF1A */ +#define CANFD_CH_M_TTCAN_RXF1A_F1AI_Pos 0UL +#define CANFD_CH_M_TTCAN_RXF1A_F1AI_Msk 0x3FUL +/* CANFD_CH_M_TTCAN.RXESC */ +#define CANFD_CH_M_TTCAN_RXESC_F0DS_Pos 0UL +#define CANFD_CH_M_TTCAN_RXESC_F0DS_Msk 0x7UL +#define CANFD_CH_M_TTCAN_RXESC_F1DS_Pos 4UL +#define CANFD_CH_M_TTCAN_RXESC_F1DS_Msk 0x70UL +#define CANFD_CH_M_TTCAN_RXESC_RBDS_Pos 8UL +#define CANFD_CH_M_TTCAN_RXESC_RBDS_Msk 0x700UL +/* CANFD_CH_M_TTCAN.TXBC */ +#define CANFD_CH_M_TTCAN_TXBC_TBSA_Pos 2UL +#define CANFD_CH_M_TTCAN_TXBC_TBSA_Msk 0xFFFCUL +#define CANFD_CH_M_TTCAN_TXBC_NDTB_Pos 16UL +#define CANFD_CH_M_TTCAN_TXBC_NDTB_Msk 0x3F0000UL +#define CANFD_CH_M_TTCAN_TXBC_TFQS_Pos 24UL +#define CANFD_CH_M_TTCAN_TXBC_TFQS_Msk 0x3F000000UL +#define CANFD_CH_M_TTCAN_TXBC_TFQM_Pos 30UL +#define CANFD_CH_M_TTCAN_TXBC_TFQM_Msk 0x40000000UL +/* CANFD_CH_M_TTCAN.TXFQS */ +#define CANFD_CH_M_TTCAN_TXFQS_TFFL_Pos 0UL +#define CANFD_CH_M_TTCAN_TXFQS_TFFL_Msk 0x3FUL +#define CANFD_CH_M_TTCAN_TXFQS_TFGI_Pos 8UL +#define CANFD_CH_M_TTCAN_TXFQS_TFGI_Msk 0x1F00UL +#define CANFD_CH_M_TTCAN_TXFQS_TFQPI_Pos 16UL +#define CANFD_CH_M_TTCAN_TXFQS_TFQPI_Msk 0x1F0000UL +#define CANFD_CH_M_TTCAN_TXFQS_TFQF_Pos 21UL +#define CANFD_CH_M_TTCAN_TXFQS_TFQF_Msk 0x200000UL +/* CANFD_CH_M_TTCAN.TXESC */ +#define CANFD_CH_M_TTCAN_TXESC_TBDS_Pos 0UL +#define CANFD_CH_M_TTCAN_TXESC_TBDS_Msk 0x7UL +/* CANFD_CH_M_TTCAN.TXBRP */ +#define CANFD_CH_M_TTCAN_TXBRP_TRP_Pos 0UL +#define CANFD_CH_M_TTCAN_TXBRP_TRP_Msk 0xFFFFFFFFUL +/* CANFD_CH_M_TTCAN.TXBAR */ +#define CANFD_CH_M_TTCAN_TXBAR_AR_Pos 0UL +#define CANFD_CH_M_TTCAN_TXBAR_AR_Msk 0xFFFFFFFFUL +/* CANFD_CH_M_TTCAN.TXBCR */ +#define CANFD_CH_M_TTCAN_TXBCR_CR_Pos 0UL +#define CANFD_CH_M_TTCAN_TXBCR_CR_Msk 0xFFFFFFFFUL +/* CANFD_CH_M_TTCAN.TXBTO */ +#define CANFD_CH_M_TTCAN_TXBTO_TO_Pos 0UL +#define CANFD_CH_M_TTCAN_TXBTO_TO_Msk 0xFFFFFFFFUL +/* CANFD_CH_M_TTCAN.TXBCF */ +#define CANFD_CH_M_TTCAN_TXBCF_CF_Pos 0UL +#define CANFD_CH_M_TTCAN_TXBCF_CF_Msk 0xFFFFFFFFUL +/* CANFD_CH_M_TTCAN.TXBTIE */ +#define CANFD_CH_M_TTCAN_TXBTIE_TIE_Pos 0UL +#define CANFD_CH_M_TTCAN_TXBTIE_TIE_Msk 0xFFFFFFFFUL +/* CANFD_CH_M_TTCAN.TXBCIE */ +#define CANFD_CH_M_TTCAN_TXBCIE_CFIE_Pos 0UL +#define CANFD_CH_M_TTCAN_TXBCIE_CFIE_Msk 0xFFFFFFFFUL +/* CANFD_CH_M_TTCAN.TXEFC */ +#define CANFD_CH_M_TTCAN_TXEFC_EFSA_Pos 2UL +#define CANFD_CH_M_TTCAN_TXEFC_EFSA_Msk 0xFFFCUL +#define CANFD_CH_M_TTCAN_TXEFC_EFS_Pos 16UL +#define CANFD_CH_M_TTCAN_TXEFC_EFS_Msk 0x3F0000UL +#define CANFD_CH_M_TTCAN_TXEFC_EFWM_Pos 24UL +#define CANFD_CH_M_TTCAN_TXEFC_EFWM_Msk 0x3F000000UL +/* CANFD_CH_M_TTCAN.TXEFS */ +#define CANFD_CH_M_TTCAN_TXEFS_EFFL_Pos 0UL +#define CANFD_CH_M_TTCAN_TXEFS_EFFL_Msk 0x3FUL +#define CANFD_CH_M_TTCAN_TXEFS_EFGI_Pos 8UL +#define CANFD_CH_M_TTCAN_TXEFS_EFGI_Msk 0x1F00UL +#define CANFD_CH_M_TTCAN_TXEFS_EFPI_Pos 16UL +#define CANFD_CH_M_TTCAN_TXEFS_EFPI_Msk 0x1F0000UL +#define CANFD_CH_M_TTCAN_TXEFS_EFF_Pos 24UL +#define CANFD_CH_M_TTCAN_TXEFS_EFF_Msk 0x1000000UL +#define CANFD_CH_M_TTCAN_TXEFS_TEFL_Pos 25UL +#define CANFD_CH_M_TTCAN_TXEFS_TEFL_Msk 0x2000000UL +/* CANFD_CH_M_TTCAN.TXEFA */ +#define CANFD_CH_M_TTCAN_TXEFA_EFAI_Pos 0UL +#define CANFD_CH_M_TTCAN_TXEFA_EFAI_Msk 0x1FUL +/* CANFD_CH_M_TTCAN.TTTMC */ +#define CANFD_CH_M_TTCAN_TTTMC_TMSA_Pos 2UL +#define CANFD_CH_M_TTCAN_TTTMC_TMSA_Msk 0xFFFCUL +#define CANFD_CH_M_TTCAN_TTTMC_TME_Pos 16UL +#define CANFD_CH_M_TTCAN_TTTMC_TME_Msk 0x7F0000UL +/* CANFD_CH_M_TTCAN.TTRMC */ +#define CANFD_CH_M_TTCAN_TTRMC_RID_Pos 0UL +#define CANFD_CH_M_TTCAN_TTRMC_RID_Msk 0x1FFFFFFFUL +#define CANFD_CH_M_TTCAN_TTRMC_XTD_Pos 30UL +#define CANFD_CH_M_TTCAN_TTRMC_XTD_Msk 0x40000000UL +#define CANFD_CH_M_TTCAN_TTRMC_RMPS_Pos 31UL +#define CANFD_CH_M_TTCAN_TTRMC_RMPS_Msk 0x80000000UL +/* CANFD_CH_M_TTCAN.TTOCF */ +#define CANFD_CH_M_TTCAN_TTOCF_OM_Pos 0UL +#define CANFD_CH_M_TTCAN_TTOCF_OM_Msk 0x3UL +#define CANFD_CH_M_TTCAN_TTOCF_GEN_Pos 3UL +#define CANFD_CH_M_TTCAN_TTOCF_GEN_Msk 0x8UL +#define CANFD_CH_M_TTCAN_TTOCF_TM_Pos 4UL +#define CANFD_CH_M_TTCAN_TTOCF_TM_Msk 0x10UL +#define CANFD_CH_M_TTCAN_TTOCF_LDSDL_Pos 5UL +#define CANFD_CH_M_TTCAN_TTOCF_LDSDL_Msk 0xE0UL +#define CANFD_CH_M_TTCAN_TTOCF_IRTO_Pos 8UL +#define CANFD_CH_M_TTCAN_TTOCF_IRTO_Msk 0x7F00UL +#define CANFD_CH_M_TTCAN_TTOCF_EECS_Pos 15UL +#define CANFD_CH_M_TTCAN_TTOCF_EECS_Msk 0x8000UL +#define CANFD_CH_M_TTCAN_TTOCF_AWL_Pos 16UL +#define CANFD_CH_M_TTCAN_TTOCF_AWL_Msk 0xFF0000UL +#define CANFD_CH_M_TTCAN_TTOCF_EGTF_Pos 24UL +#define CANFD_CH_M_TTCAN_TTOCF_EGTF_Msk 0x1000000UL +#define CANFD_CH_M_TTCAN_TTOCF_ECC_Pos 25UL +#define CANFD_CH_M_TTCAN_TTOCF_ECC_Msk 0x2000000UL +#define CANFD_CH_M_TTCAN_TTOCF_EVTP_Pos 26UL +#define CANFD_CH_M_TTCAN_TTOCF_EVTP_Msk 0x4000000UL +/* CANFD_CH_M_TTCAN.TTMLM */ +#define CANFD_CH_M_TTCAN_TTMLM_CCM_Pos 0UL +#define CANFD_CH_M_TTCAN_TTMLM_CCM_Msk 0x3FUL +#define CANFD_CH_M_TTCAN_TTMLM_CSS_Pos 6UL +#define CANFD_CH_M_TTCAN_TTMLM_CSS_Msk 0xC0UL +#define CANFD_CH_M_TTCAN_TTMLM_TXEW_Pos 8UL +#define CANFD_CH_M_TTCAN_TTMLM_TXEW_Msk 0xF00UL +#define CANFD_CH_M_TTCAN_TTMLM_ENTT_Pos 16UL +#define CANFD_CH_M_TTCAN_TTMLM_ENTT_Msk 0xFFF0000UL +/* CANFD_CH_M_TTCAN.TURCF */ +#define CANFD_CH_M_TTCAN_TURCF_NCL_Pos 0UL +#define CANFD_CH_M_TTCAN_TURCF_NCL_Msk 0xFFFFUL +#define CANFD_CH_M_TTCAN_TURCF_DC_Pos 16UL +#define CANFD_CH_M_TTCAN_TURCF_DC_Msk 0x3FFF0000UL +#define CANFD_CH_M_TTCAN_TURCF_ELT_Pos 31UL +#define CANFD_CH_M_TTCAN_TURCF_ELT_Msk 0x80000000UL +/* CANFD_CH_M_TTCAN.TTOCN */ +#define CANFD_CH_M_TTCAN_TTOCN_SGT_Pos 0UL +#define CANFD_CH_M_TTCAN_TTOCN_SGT_Msk 0x1UL +#define CANFD_CH_M_TTCAN_TTOCN_ECS_Pos 1UL +#define CANFD_CH_M_TTCAN_TTOCN_ECS_Msk 0x2UL +#define CANFD_CH_M_TTCAN_TTOCN_SWP_Pos 2UL +#define CANFD_CH_M_TTCAN_TTOCN_SWP_Msk 0x4UL +#define CANFD_CH_M_TTCAN_TTOCN_SWS_Pos 3UL +#define CANFD_CH_M_TTCAN_TTOCN_SWS_Msk 0x18UL +#define CANFD_CH_M_TTCAN_TTOCN_RTIE_Pos 5UL +#define CANFD_CH_M_TTCAN_TTOCN_RTIE_Msk 0x20UL +#define CANFD_CH_M_TTCAN_TTOCN_TMC_Pos 6UL +#define CANFD_CH_M_TTCAN_TTOCN_TMC_Msk 0xC0UL +#define CANFD_CH_M_TTCAN_TTOCN_TTIE_Pos 8UL +#define CANFD_CH_M_TTCAN_TTOCN_TTIE_Msk 0x100UL +#define CANFD_CH_M_TTCAN_TTOCN_GCS_Pos 9UL +#define CANFD_CH_M_TTCAN_TTOCN_GCS_Msk 0x200UL +#define CANFD_CH_M_TTCAN_TTOCN_FGP_Pos 10UL +#define CANFD_CH_M_TTCAN_TTOCN_FGP_Msk 0x400UL +#define CANFD_CH_M_TTCAN_TTOCN_TMG_Pos 11UL +#define CANFD_CH_M_TTCAN_TTOCN_TMG_Msk 0x800UL +#define CANFD_CH_M_TTCAN_TTOCN_NIG_Pos 12UL +#define CANFD_CH_M_TTCAN_TTOCN_NIG_Msk 0x1000UL +#define CANFD_CH_M_TTCAN_TTOCN_ESCN_Pos 13UL +#define CANFD_CH_M_TTCAN_TTOCN_ESCN_Msk 0x2000UL +#define CANFD_CH_M_TTCAN_TTOCN_LCKC_Pos 15UL +#define CANFD_CH_M_TTCAN_TTOCN_LCKC_Msk 0x8000UL +/* CANFD_CH_M_TTCAN.TTGTP */ +#define CANFD_CH_M_TTCAN_TTGTP_TP_Pos 0UL +#define CANFD_CH_M_TTCAN_TTGTP_TP_Msk 0xFFFFUL +#define CANFD_CH_M_TTCAN_TTGTP_CTP_Pos 16UL +#define CANFD_CH_M_TTCAN_TTGTP_CTP_Msk 0xFFFF0000UL +/* CANFD_CH_M_TTCAN.TTTMK */ +#define CANFD_CH_M_TTCAN_TTTMK_TM__Pos 0UL +#define CANFD_CH_M_TTCAN_TTTMK_TM__Msk 0xFFFFUL +#define CANFD_CH_M_TTCAN_TTTMK_TICC_Pos 16UL +#define CANFD_CH_M_TTCAN_TTTMK_TICC_Msk 0x7F0000UL +#define CANFD_CH_M_TTCAN_TTTMK_LCKM_Pos 31UL +#define CANFD_CH_M_TTCAN_TTTMK_LCKM_Msk 0x80000000UL +/* CANFD_CH_M_TTCAN.TTIR */ +#define CANFD_CH_M_TTCAN_TTIR_SBC_Pos 0UL +#define CANFD_CH_M_TTCAN_TTIR_SBC_Msk 0x1UL +#define CANFD_CH_M_TTCAN_TTIR_SMC_Pos 1UL +#define CANFD_CH_M_TTCAN_TTIR_SMC_Msk 0x2UL +#define CANFD_CH_M_TTCAN_TTIR_CSM__Pos 2UL +#define CANFD_CH_M_TTCAN_TTIR_CSM__Msk 0x4UL +#define CANFD_CH_M_TTCAN_TTIR_SOG_Pos 3UL +#define CANFD_CH_M_TTCAN_TTIR_SOG_Msk 0x8UL +#define CANFD_CH_M_TTCAN_TTIR_RTMI_Pos 4UL +#define CANFD_CH_M_TTCAN_TTIR_RTMI_Msk 0x10UL +#define CANFD_CH_M_TTCAN_TTIR_TTMI_Pos 5UL +#define CANFD_CH_M_TTCAN_TTIR_TTMI_Msk 0x20UL +#define CANFD_CH_M_TTCAN_TTIR_SWE_Pos 6UL +#define CANFD_CH_M_TTCAN_TTIR_SWE_Msk 0x40UL +#define CANFD_CH_M_TTCAN_TTIR_GTW_Pos 7UL +#define CANFD_CH_M_TTCAN_TTIR_GTW_Msk 0x80UL +#define CANFD_CH_M_TTCAN_TTIR_GTD_Pos 8UL +#define CANFD_CH_M_TTCAN_TTIR_GTD_Msk 0x100UL +#define CANFD_CH_M_TTCAN_TTIR_GTE_Pos 9UL +#define CANFD_CH_M_TTCAN_TTIR_GTE_Msk 0x200UL +#define CANFD_CH_M_TTCAN_TTIR_TXU_Pos 10UL +#define CANFD_CH_M_TTCAN_TTIR_TXU_Msk 0x400UL +#define CANFD_CH_M_TTCAN_TTIR_TXO_Pos 11UL +#define CANFD_CH_M_TTCAN_TTIR_TXO_Msk 0x800UL +#define CANFD_CH_M_TTCAN_TTIR_SE1_Pos 12UL +#define CANFD_CH_M_TTCAN_TTIR_SE1_Msk 0x1000UL +#define CANFD_CH_M_TTCAN_TTIR_SE2_Pos 13UL +#define CANFD_CH_M_TTCAN_TTIR_SE2_Msk 0x2000UL +#define CANFD_CH_M_TTCAN_TTIR_ELC_Pos 14UL +#define CANFD_CH_M_TTCAN_TTIR_ELC_Msk 0x4000UL +#define CANFD_CH_M_TTCAN_TTIR_IWT_Pos 15UL +#define CANFD_CH_M_TTCAN_TTIR_IWT_Msk 0x8000UL +#define CANFD_CH_M_TTCAN_TTIR_WT_Pos 16UL +#define CANFD_CH_M_TTCAN_TTIR_WT_Msk 0x10000UL +#define CANFD_CH_M_TTCAN_TTIR_AW_Pos 17UL +#define CANFD_CH_M_TTCAN_TTIR_AW_Msk 0x20000UL +#define CANFD_CH_M_TTCAN_TTIR_CER_Pos 18UL +#define CANFD_CH_M_TTCAN_TTIR_CER_Msk 0x40000UL +/* CANFD_CH_M_TTCAN.TTIE */ +#define CANFD_CH_M_TTCAN_TTIE_SBCE_Pos 0UL +#define CANFD_CH_M_TTCAN_TTIE_SBCE_Msk 0x1UL +#define CANFD_CH_M_TTCAN_TTIE_SMCE_Pos 1UL +#define CANFD_CH_M_TTCAN_TTIE_SMCE_Msk 0x2UL +#define CANFD_CH_M_TTCAN_TTIE_CSME_Pos 2UL +#define CANFD_CH_M_TTCAN_TTIE_CSME_Msk 0x4UL +#define CANFD_CH_M_TTCAN_TTIE_SOGE_Pos 3UL +#define CANFD_CH_M_TTCAN_TTIE_SOGE_Msk 0x8UL +#define CANFD_CH_M_TTCAN_TTIE_RTMIE_Pos 4UL +#define CANFD_CH_M_TTCAN_TTIE_RTMIE_Msk 0x10UL +#define CANFD_CH_M_TTCAN_TTIE_TTMIE_Pos 5UL +#define CANFD_CH_M_TTCAN_TTIE_TTMIE_Msk 0x20UL +#define CANFD_CH_M_TTCAN_TTIE_SWEE_Pos 6UL +#define CANFD_CH_M_TTCAN_TTIE_SWEE_Msk 0x40UL +#define CANFD_CH_M_TTCAN_TTIE_GTWE_Pos 7UL +#define CANFD_CH_M_TTCAN_TTIE_GTWE_Msk 0x80UL +#define CANFD_CH_M_TTCAN_TTIE_GTDE_Pos 8UL +#define CANFD_CH_M_TTCAN_TTIE_GTDE_Msk 0x100UL +#define CANFD_CH_M_TTCAN_TTIE_GTEE_Pos 9UL +#define CANFD_CH_M_TTCAN_TTIE_GTEE_Msk 0x200UL +#define CANFD_CH_M_TTCAN_TTIE_TXUE_Pos 10UL +#define CANFD_CH_M_TTCAN_TTIE_TXUE_Msk 0x400UL +#define CANFD_CH_M_TTCAN_TTIE_TXOE_Pos 11UL +#define CANFD_CH_M_TTCAN_TTIE_TXOE_Msk 0x800UL +#define CANFD_CH_M_TTCAN_TTIE_SE1E_Pos 12UL +#define CANFD_CH_M_TTCAN_TTIE_SE1E_Msk 0x1000UL +#define CANFD_CH_M_TTCAN_TTIE_SE2E_Pos 13UL +#define CANFD_CH_M_TTCAN_TTIE_SE2E_Msk 0x2000UL +#define CANFD_CH_M_TTCAN_TTIE_ELCE_Pos 14UL +#define CANFD_CH_M_TTCAN_TTIE_ELCE_Msk 0x4000UL +#define CANFD_CH_M_TTCAN_TTIE_IWTE_Pos 15UL +#define CANFD_CH_M_TTCAN_TTIE_IWTE_Msk 0x8000UL +#define CANFD_CH_M_TTCAN_TTIE_WTE_Pos 16UL +#define CANFD_CH_M_TTCAN_TTIE_WTE_Msk 0x10000UL +#define CANFD_CH_M_TTCAN_TTIE_AWE__Pos 17UL +#define CANFD_CH_M_TTCAN_TTIE_AWE__Msk 0x20000UL +#define CANFD_CH_M_TTCAN_TTIE_CERE_Pos 18UL +#define CANFD_CH_M_TTCAN_TTIE_CERE_Msk 0x40000UL +/* CANFD_CH_M_TTCAN.TTILS */ +#define CANFD_CH_M_TTCAN_TTILS_SBCL_Pos 0UL +#define CANFD_CH_M_TTCAN_TTILS_SBCL_Msk 0x1UL +#define CANFD_CH_M_TTCAN_TTILS_SMCL_Pos 1UL +#define CANFD_CH_M_TTCAN_TTILS_SMCL_Msk 0x2UL +#define CANFD_CH_M_TTCAN_TTILS_CSML_Pos 2UL +#define CANFD_CH_M_TTCAN_TTILS_CSML_Msk 0x4UL +#define CANFD_CH_M_TTCAN_TTILS_SOGL_Pos 3UL +#define CANFD_CH_M_TTCAN_TTILS_SOGL_Msk 0x8UL +#define CANFD_CH_M_TTCAN_TTILS_RTMIL_Pos 4UL +#define CANFD_CH_M_TTCAN_TTILS_RTMIL_Msk 0x10UL +#define CANFD_CH_M_TTCAN_TTILS_TTMIL_Pos 5UL +#define CANFD_CH_M_TTCAN_TTILS_TTMIL_Msk 0x20UL +#define CANFD_CH_M_TTCAN_TTILS_SWEL_Pos 6UL +#define CANFD_CH_M_TTCAN_TTILS_SWEL_Msk 0x40UL +#define CANFD_CH_M_TTCAN_TTILS_GTWL_Pos 7UL +#define CANFD_CH_M_TTCAN_TTILS_GTWL_Msk 0x80UL +#define CANFD_CH_M_TTCAN_TTILS_GTDL_Pos 8UL +#define CANFD_CH_M_TTCAN_TTILS_GTDL_Msk 0x100UL +#define CANFD_CH_M_TTCAN_TTILS_GTEL_Pos 9UL +#define CANFD_CH_M_TTCAN_TTILS_GTEL_Msk 0x200UL +#define CANFD_CH_M_TTCAN_TTILS_TXUL_Pos 10UL +#define CANFD_CH_M_TTCAN_TTILS_TXUL_Msk 0x400UL +#define CANFD_CH_M_TTCAN_TTILS_TXOL_Pos 11UL +#define CANFD_CH_M_TTCAN_TTILS_TXOL_Msk 0x800UL +#define CANFD_CH_M_TTCAN_TTILS_SE1L_Pos 12UL +#define CANFD_CH_M_TTCAN_TTILS_SE1L_Msk 0x1000UL +#define CANFD_CH_M_TTCAN_TTILS_SE2L_Pos 13UL +#define CANFD_CH_M_TTCAN_TTILS_SE2L_Msk 0x2000UL +#define CANFD_CH_M_TTCAN_TTILS_ELCL_Pos 14UL +#define CANFD_CH_M_TTCAN_TTILS_ELCL_Msk 0x4000UL +#define CANFD_CH_M_TTCAN_TTILS_IWTL_Pos 15UL +#define CANFD_CH_M_TTCAN_TTILS_IWTL_Msk 0x8000UL +#define CANFD_CH_M_TTCAN_TTILS_WTL_Pos 16UL +#define CANFD_CH_M_TTCAN_TTILS_WTL_Msk 0x10000UL +#define CANFD_CH_M_TTCAN_TTILS_AWL__Pos 17UL +#define CANFD_CH_M_TTCAN_TTILS_AWL__Msk 0x20000UL +#define CANFD_CH_M_TTCAN_TTILS_CERL_Pos 18UL +#define CANFD_CH_M_TTCAN_TTILS_CERL_Msk 0x40000UL +/* CANFD_CH_M_TTCAN.TTOST */ +#define CANFD_CH_M_TTCAN_TTOST_EL_Pos 0UL +#define CANFD_CH_M_TTCAN_TTOST_EL_Msk 0x3UL +#define CANFD_CH_M_TTCAN_TTOST_MS_Pos 2UL +#define CANFD_CH_M_TTCAN_TTOST_MS_Msk 0xCUL +#define CANFD_CH_M_TTCAN_TTOST_SYS_Pos 4UL +#define CANFD_CH_M_TTCAN_TTOST_SYS_Msk 0x30UL +#define CANFD_CH_M_TTCAN_TTOST_QGTP_Pos 6UL +#define CANFD_CH_M_TTCAN_TTOST_QGTP_Msk 0x40UL +#define CANFD_CH_M_TTCAN_TTOST_QCS_Pos 7UL +#define CANFD_CH_M_TTCAN_TTOST_QCS_Msk 0x80UL +#define CANFD_CH_M_TTCAN_TTOST_RTO_Pos 8UL +#define CANFD_CH_M_TTCAN_TTOST_RTO_Msk 0xFF00UL +#define CANFD_CH_M_TTCAN_TTOST_WGTD_Pos 22UL +#define CANFD_CH_M_TTCAN_TTOST_WGTD_Msk 0x400000UL +#define CANFD_CH_M_TTCAN_TTOST_GFI_Pos 23UL +#define CANFD_CH_M_TTCAN_TTOST_GFI_Msk 0x800000UL +#define CANFD_CH_M_TTCAN_TTOST_TMP_Pos 24UL +#define CANFD_CH_M_TTCAN_TTOST_TMP_Msk 0x7000000UL +#define CANFD_CH_M_TTCAN_TTOST_GSI_Pos 27UL +#define CANFD_CH_M_TTCAN_TTOST_GSI_Msk 0x8000000UL +#define CANFD_CH_M_TTCAN_TTOST_WFE_Pos 28UL +#define CANFD_CH_M_TTCAN_TTOST_WFE_Msk 0x10000000UL +#define CANFD_CH_M_TTCAN_TTOST_AWE_Pos 29UL +#define CANFD_CH_M_TTCAN_TTOST_AWE_Msk 0x20000000UL +#define CANFD_CH_M_TTCAN_TTOST_WECS_Pos 30UL +#define CANFD_CH_M_TTCAN_TTOST_WECS_Msk 0x40000000UL +#define CANFD_CH_M_TTCAN_TTOST_SPL_Pos 31UL +#define CANFD_CH_M_TTCAN_TTOST_SPL_Msk 0x80000000UL +/* CANFD_CH_M_TTCAN.TURNA */ +#define CANFD_CH_M_TTCAN_TURNA_NAV_Pos 0UL +#define CANFD_CH_M_TTCAN_TURNA_NAV_Msk 0x3FFFFUL +/* CANFD_CH_M_TTCAN.TTLGT */ +#define CANFD_CH_M_TTCAN_TTLGT_LT_Pos 0UL +#define CANFD_CH_M_TTCAN_TTLGT_LT_Msk 0xFFFFUL +#define CANFD_CH_M_TTCAN_TTLGT_GT_Pos 16UL +#define CANFD_CH_M_TTCAN_TTLGT_GT_Msk 0xFFFF0000UL +/* CANFD_CH_M_TTCAN.TTCTC */ +#define CANFD_CH_M_TTCAN_TTCTC_CT_Pos 0UL +#define CANFD_CH_M_TTCAN_TTCTC_CT_Msk 0xFFFFUL +#define CANFD_CH_M_TTCAN_TTCTC_CC_Pos 16UL +#define CANFD_CH_M_TTCAN_TTCTC_CC_Msk 0x3F0000UL +/* CANFD_CH_M_TTCAN.TTCPT */ +#define CANFD_CH_M_TTCAN_TTCPT_CCV_Pos 0UL +#define CANFD_CH_M_TTCAN_TTCPT_CCV_Msk 0x3FUL +#define CANFD_CH_M_TTCAN_TTCPT_SWV_Pos 16UL +#define CANFD_CH_M_TTCAN_TTCPT_SWV_Msk 0xFFFF0000UL +/* CANFD_CH_M_TTCAN.TTCSM */ +#define CANFD_CH_M_TTCAN_TTCSM_CSM_Pos 0UL +#define CANFD_CH_M_TTCAN_TTCSM_CSM_Msk 0xFFFFUL + + +/* CANFD_CH.RXFTOP_CTL */ +#define CANFD_CH_RXFTOP_CTL_F0TPE_Pos 0UL +#define CANFD_CH_RXFTOP_CTL_F0TPE_Msk 0x1UL +#define CANFD_CH_RXFTOP_CTL_F1TPE_Pos 1UL +#define CANFD_CH_RXFTOP_CTL_F1TPE_Msk 0x2UL +/* CANFD_CH.RXFTOP0_STAT */ +#define CANFD_CH_RXFTOP0_STAT_F0TA_Pos 0UL +#define CANFD_CH_RXFTOP0_STAT_F0TA_Msk 0xFFFFUL +/* CANFD_CH.RXFTOP0_DATA */ +#define CANFD_CH_RXFTOP0_DATA_F0TD_Pos 0UL +#define CANFD_CH_RXFTOP0_DATA_F0TD_Msk 0xFFFFFFFFUL +/* CANFD_CH.RXFTOP1_STAT */ +#define CANFD_CH_RXFTOP1_STAT_F1TA_Pos 0UL +#define CANFD_CH_RXFTOP1_STAT_F1TA_Msk 0xFFFFUL +/* CANFD_CH.RXFTOP1_DATA */ +#define CANFD_CH_RXFTOP1_DATA_F1TD_Pos 0UL +#define CANFD_CH_RXFTOP1_DATA_F1TD_Msk 0xFFFFFFFFUL + + +/* CANFD.CTL */ +#define CANFD_CTL_STOP_REQ_Pos 0UL +#define CANFD_CTL_STOP_REQ_Msk 0xFFUL +#define CANFD_CTL_MRAM_OFF_Pos 31UL +#define CANFD_CTL_MRAM_OFF_Msk 0x80000000UL +/* CANFD.STATUS */ +#define CANFD_STATUS_STOP_ACK_Pos 0UL +#define CANFD_STATUS_STOP_ACK_Msk 0xFFUL +/* CANFD.INTR0_CAUSE */ +#define CANFD_INTR0_CAUSE_INT0_Pos 0UL +#define CANFD_INTR0_CAUSE_INT0_Msk 0xFFUL +/* CANFD.INTR1_CAUSE */ +#define CANFD_INTR1_CAUSE_INT1_Pos 0UL +#define CANFD_INTR1_CAUSE_INT1_Msk 0xFFUL +/* CANFD.TS_CTL */ +#define CANFD_TS_CTL_PRESCALE_Pos 0UL +#define CANFD_TS_CTL_PRESCALE_Msk 0xFFFFUL +#define CANFD_TS_CTL_ENABLED_Pos 31UL +#define CANFD_TS_CTL_ENABLED_Msk 0x80000000UL +/* CANFD.TS_CNT */ +#define CANFD_TS_CNT_VALUE_Pos 0UL +#define CANFD_TS_CNT_VALUE_Msk 0xFFFFUL +/* CANFD.ECC_CTL */ +#define CANFD_ECC_CTL_ECC_EN_Pos 16UL +#define CANFD_ECC_CTL_ECC_EN_Msk 0x10000UL +/* CANFD.ECC_ERR_INJ */ +#define CANFD_ECC_ERR_INJ_ERR_ADDR_Pos 2UL +#define CANFD_ECC_ERR_INJ_ERR_ADDR_Msk 0xFFFCUL +#define CANFD_ECC_ERR_INJ_ERR_EN_Pos 20UL +#define CANFD_ECC_ERR_INJ_ERR_EN_Msk 0x100000UL +#define CANFD_ECC_ERR_INJ_ERR_PAR_Pos 24UL +#define CANFD_ECC_ERR_INJ_ERR_PAR_Msk 0x7F000000UL + + +#endif /* _CYIP_CANFD_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_cpuss.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_cpuss.h index 39104ec286..9eedb89bfe 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_cpuss.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_cpuss.h @@ -5,7 +5,7 @@ * CPUSS IP definitions * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -100,9 +100,11 @@ typedef struct { __IOM uint32_t PROTECTION; /*!< 0x00000500 Protection status */ __IM uint32_t RESERVED23[7]; __IOM uint32_t CM0_NMI_CTL; /*!< 0x00000520 CM0+ NMI control */ - __IM uint32_t RESERVED24[31]; + __IM uint32_t RESERVED24[7]; + __IOM uint32_t AP_CTL; /*!< 0x00000540 Access port control */ + __IM uint32_t RESERVED25[23]; __IM uint32_t MBIST_STAT; /*!< 0x000005A0 Memory BIST status */ - __IM uint32_t RESERVED25[14999]; + __IM uint32_t RESERVED26[14999]; __IOM uint32_t TRIM_ROM_CTL; /*!< 0x0000F000 ROM trim control */ __IOM uint32_t TRIM_RAM_CTL; /*!< 0x0000F004 RAM trim control */ } CPUSS_V1_Type; /*!< Size = 61448 (0xF008) */ @@ -312,6 +314,19 @@ typedef struct { /* CPUSS.CM0_NMI_CTL */ #define CPUSS_CM0_NMI_CTL_MUX0_SEL_Pos 0UL #define CPUSS_CM0_NMI_CTL_MUX0_SEL_Msk 0xFFUL +/* CPUSS.AP_CTL */ +#define CPUSS_AP_CTL_CM0_ENABLE_Pos 0UL +#define CPUSS_AP_CTL_CM0_ENABLE_Msk 0x1UL +#define CPUSS_AP_CTL_CM4_ENABLE_Pos 1UL +#define CPUSS_AP_CTL_CM4_ENABLE_Msk 0x2UL +#define CPUSS_AP_CTL_SYS_ENABLE_Pos 2UL +#define CPUSS_AP_CTL_SYS_ENABLE_Msk 0x4UL +#define CPUSS_AP_CTL_CM0_DISABLE_Pos 16UL +#define CPUSS_AP_CTL_CM0_DISABLE_Msk 0x10000UL +#define CPUSS_AP_CTL_CM4_DISABLE_Pos 17UL +#define CPUSS_AP_CTL_CM4_DISABLE_Msk 0x20000UL +#define CPUSS_AP_CTL_SYS_DISABLE_Pos 18UL +#define CPUSS_AP_CTL_SYS_DISABLE_Msk 0x40000UL /* CPUSS.MBIST_STAT */ #define CPUSS_MBIST_STAT_SFP_READY_Pos 0UL #define CPUSS_MBIST_STAT_SFP_READY_Msk 0x1UL diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_cpuss_v2.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_cpuss_v2.h index f2e0ff5ad0..1c585e7ec5 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_cpuss_v2.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_cpuss_v2.h @@ -5,7 +5,7 @@ * CPUSS IP definitions * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_crypto.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_crypto.h index 770a051ce4..6d406dae6f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_crypto.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_crypto.h @@ -5,7 +5,7 @@ * CRYPTO IP definitions * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_crypto_v2.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_crypto_v2.h index 36ba2ff95a..40d3cbad10 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_crypto_v2.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_crypto_v2.h @@ -5,7 +5,7 @@ * CRYPTO IP definitions * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_csd.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_csd.h index 2d065364fc..0cb92178a3 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_csd.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_csd.h @@ -5,7 +5,7 @@ * CSD IP definitions * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_ctbm.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_ctbm.h index 44a089958f..8dc5ac007d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_ctbm.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_ctbm.h @@ -5,7 +5,7 @@ * CTBM IP definitions * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_ctdac.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_ctdac.h index 99a8c1461c..9fb4ebb27f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_ctdac.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_ctdac.h @@ -5,7 +5,7 @@ * CTDAC IP definitions * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_dmac_v2.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_dmac_v2.h index 23cfb7e710..22da5d6c06 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_dmac_v2.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_dmac_v2.h @@ -5,7 +5,7 @@ * DMAC IP definitions * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_dw.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_dw.h index d3764fd474..d228993380 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_dw.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_dw.h @@ -5,7 +5,7 @@ * DW IP definitions * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_dw_v2.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_dw_v2.h index ae73aaa838..0f598ae5e7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_dw_v2.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_dw_v2.h @@ -5,7 +5,7 @@ * DW IP definitions * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_efuse.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_efuse.h index f2d599df17..3dce6a269c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_efuse.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_efuse.h @@ -5,7 +5,7 @@ * EFUSE IP definitions * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_efuse_data_psoc6_01.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_efuse_data_psoc6_01.h index 580f43b39e..2f37fe85bb 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_efuse_data_psoc6_01.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_efuse_data_psoc6_01.h @@ -5,7 +5,7 @@ * EFUSE_DATA IP definitions * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_efuse_data_psoc6_02.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_efuse_data_psoc6_02.h index e735b9fa80..8d0851dee7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_efuse_data_psoc6_02.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_efuse_data_psoc6_02.h @@ -5,7 +5,7 @@ * EFUSE_DATA IP definitions * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_efuse_data_psoc6_03.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_efuse_data_psoc6_03.h new file mode 100644 index 0000000000..f3545aca4e --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_efuse_data_psoc6_03.h @@ -0,0 +1,250 @@ +/***************************************************************************//** +* \file cyip_efuse_data_psoc6_03.h +* +* \brief +* EFUSE_DATA IP definitions +* +* \note +* Generator version: 1.5.0.1274 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CYIP_EFUSE_DATA_PSOC6_03_H_ +#define _CYIP_EFUSE_DATA_PSOC6_03_H_ + +#include "cyip_headers.h" + +/** + * \brief Access restrictions for DEAD life cycle stage (DEAD_ACCESS_RESTRICT0) + */ +typedef struct { + uint8_t CM0_DISABLE; + uint8_t CM4_DISABLE; + uint8_t SYS_DISABLE; + uint8_t SYS_AP_MPU_ENABLE; + uint8_t SFLASH_ALLOWED[2]; + uint8_t MMIO_ALLOWED[2]; +} cy_stc_dead_access_restrict0_t; + +/** + * \brief Access restrictions for DEAD life cycle stage (DEAD_ACCESS_RESTRICT1) + */ +typedef struct { + uint8_t FLASH_ALLOWED[3]; + uint8_t SRAM_ALLOWED[3]; + uint8_t UNUSED; + uint8_t DIRECT_EXECUTE_DISABLE; +} cy_stc_dead_access_restrict1_t; + +/** + * \brief Access restrictions for SECURE life cycle stage (SECURE_ACCESS_RESTRICT0) + */ +typedef struct { + uint8_t CM0_DISABLE; + uint8_t CM4_DISABLE; + uint8_t SYS_DISABLE; + uint8_t SYS_AP_MPU_ENABLE; + uint8_t SFLASH_ALLOWED[2]; + uint8_t MMIO_ALLOWED[2]; +} cy_stc_secure_access_restrict0_t; + +/** + * \brief Access restrictions for SECURE life cycle stage (SECURE_ACCESS_RESTRICT1) + */ +typedef struct { + uint8_t FLASH_ALLOWED[3]; + uint8_t SRAM_ALLOWED[3]; + uint8_t UNUSED; + uint8_t DIRECT_EXECUTE_DISABLE; +} cy_stc_secure_access_restrict1_t; + +/** + * \brief NORMAL, SECURE_WITH_DEBUG, SECURE, and RMA fuse bits (LIFECYCLE_STAGE) + */ +typedef struct { + uint8_t NORMAL; + uint8_t SECURE_WITH_DEBUG; + uint8_t SECURE; + uint8_t RMA; + uint8_t RESERVED[4]; +} cy_stc_lifecycle_stage_t; + +/** + * \brief Cypress asset hash byte 0 (CY_ASSET_HASH0) + */ +typedef struct { + uint8_t HASH_BYTE[8]; +} cy_stc_cy_asset_hash0_t; + +/** + * \brief Cypress asset hash byte 1 (CY_ASSET_HASH1) + */ +typedef struct { + uint8_t HASH_BYTE[8]; +} cy_stc_cy_asset_hash1_t; + +/** + * \brief Cypress asset hash byte 2 (CY_ASSET_HASH2) + */ +typedef struct { + uint8_t HASH_BYTE[8]; +} cy_stc_cy_asset_hash2_t; + +/** + * \brief Cypress asset hash byte 3 (CY_ASSET_HASH3) + */ +typedef struct { + uint8_t HASH_BYTE[8]; +} cy_stc_cy_asset_hash3_t; + +/** + * \brief Cypress asset hash byte 4 (CY_ASSET_HASH4) + */ +typedef struct { + uint8_t HASH_BYTE[8]; +} cy_stc_cy_asset_hash4_t; + +/** + * \brief Cypress asset hash byte 5 (CY_ASSET_HASH5) + */ +typedef struct { + uint8_t HASH_BYTE[8]; +} cy_stc_cy_asset_hash5_t; + +/** + * \brief Cypress asset hash byte 6 (CY_ASSET_HASH6) + */ +typedef struct { + uint8_t CY_ASSET_HASH[8]; +} cy_stc_cy_asset_hash6_t; + +/** + * \brief Cypress asset hash byte 7 (CY_ASSET_HASH7) + */ +typedef struct { + uint8_t HASH_BYTE[8]; +} cy_stc_cy_asset_hash7_t; + +/** + * \brief Cypress asset hash byte 8 (CY_ASSET_HASH8) + */ +typedef struct { + uint8_t HASH_BYTE[8]; +} cy_stc_cy_asset_hash8_t; + +/** + * \brief Cypress asset hash byte 9 (CY_ASSET_HASH9) + */ +typedef struct { + uint8_t HASH_BYTE[8]; +} cy_stc_cy_asset_hash9_t; + +/** + * \brief Cypress asset hash byte 10 (CY_ASSET_HASH10) + */ +typedef struct { + uint8_t HASH_BYTE[8]; +} cy_stc_cy_asset_hash10_t; + +/** + * \brief Cypress asset hash byte 11 (CY_ASSET_HASH11) + */ +typedef struct { + uint8_t CY_ASSET_HASH[8]; +} cy_stc_cy_asset_hash11_t; + +/** + * \brief Cypress asset hash byte 12 (CY_ASSET_HASH12) + */ +typedef struct { + uint8_t HASH_BYTE[8]; +} cy_stc_cy_asset_hash12_t; + +/** + * \brief Cypress asset hash byte 13 (CY_ASSET_HASH13) + */ +typedef struct { + uint8_t CY_ASSET_HASH[8]; +} cy_stc_cy_asset_hash13_t; + +/** + * \brief Cypress asset hash byte 14 (CY_ASSET_HASH14) + */ +typedef struct { + uint8_t HASH_BYTE[8]; +} cy_stc_cy_asset_hash14_t; + +/** + * \brief Cypress asset hash byte 15 (CY_ASSET_HASH15) + */ +typedef struct { + uint8_t HASH_BYTE[8]; +} cy_stc_cy_asset_hash15_t; + +/** + * \brief Number of zeros in Cypress asset hash (CY_ASSET_HASH_ZEROS) + */ +typedef struct { + uint8_t HASH_BYTE[8]; +} cy_stc_cy_asset_hash_zeros_t; + +/** + * \brief Customer data (CUSTOMER_DATA) + */ +typedef struct { + uint8_t CUSTOMER_USE[8]; +} cy_stc_customer_data_t; + + +/** + * \brief eFUSE memory (EFUSE_DATA) + */ +typedef struct { + uint8_t RESERVED[312]; + cy_stc_dead_access_restrict0_t DEAD_ACCESS_RESTRICT0; + cy_stc_dead_access_restrict1_t DEAD_ACCESS_RESTRICT1; + cy_stc_secure_access_restrict0_t SECURE_ACCESS_RESTRICT0; + cy_stc_secure_access_restrict1_t SECURE_ACCESS_RESTRICT1; + cy_stc_lifecycle_stage_t LIFECYCLE_STAGE; + uint8_t RESERVED1[160]; + cy_stc_cy_asset_hash0_t CY_ASSET_HASH0; + cy_stc_cy_asset_hash1_t CY_ASSET_HASH1; + cy_stc_cy_asset_hash2_t CY_ASSET_HASH2; + cy_stc_cy_asset_hash3_t CY_ASSET_HASH3; + cy_stc_cy_asset_hash4_t CY_ASSET_HASH4; + cy_stc_cy_asset_hash5_t CY_ASSET_HASH5; + cy_stc_cy_asset_hash6_t CY_ASSET_HASH6; + cy_stc_cy_asset_hash7_t CY_ASSET_HASH7; + cy_stc_cy_asset_hash8_t CY_ASSET_HASH8; + cy_stc_cy_asset_hash9_t CY_ASSET_HASH9; + cy_stc_cy_asset_hash10_t CY_ASSET_HASH10; + cy_stc_cy_asset_hash11_t CY_ASSET_HASH11; + cy_stc_cy_asset_hash12_t CY_ASSET_HASH12; + cy_stc_cy_asset_hash13_t CY_ASSET_HASH13; + cy_stc_cy_asset_hash14_t CY_ASSET_HASH14; + cy_stc_cy_asset_hash15_t CY_ASSET_HASH15; + cy_stc_cy_asset_hash_zeros_t CY_ASSET_HASH_ZEROS; + cy_stc_customer_data_t CUSTOMER_DATA[47]; +} cy_stc_efuse_data_t; + + +#endif /* _CYIP_EFUSE_DATA_PSOC6_03_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_fault.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_fault.h index 1bc284d4fb..de1aed29df 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_fault.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_fault.h @@ -5,7 +5,7 @@ * FAULT IP definitions * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_fault_v2.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_fault_v2.h index df3434a237..02d39c4b86 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_fault_v2.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_fault_v2.h @@ -5,7 +5,7 @@ * FAULT IP definitions * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_flashc.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_flashc.h index a1716ff413..a304c8262a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_flashc.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_flashc.h @@ -5,7 +5,7 @@ * FLASHC IP definitions * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_flashc_v2.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_flashc_v2.h index 8639987988..2ef2360ff4 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_flashc_v2.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_flashc_v2.h @@ -5,7 +5,7 @@ * FLASHC IP definitions * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_gpio.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_gpio.h index 1f701ad662..5ce8ed2cc1 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_gpio.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_gpio.h @@ -5,7 +5,7 @@ * GPIO IP definitions * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_gpio_v2.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_gpio_v2.h index 79b52438f6..f2e978cd2a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_gpio_v2.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_gpio_v2.h @@ -5,7 +5,7 @@ * GPIO IP definitions * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_hsiom.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_hsiom.h index 8f6cbcc99a..66d223f472 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_hsiom.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_hsiom.h @@ -5,7 +5,7 @@ * HSIOM IP definitions * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_hsiom_v2.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_hsiom_v2.h index 69f373e29a..000123b1ad 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_hsiom_v2.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_hsiom_v2.h @@ -5,7 +5,7 @@ * HSIOM IP definitions * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_i2s.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_i2s.h index 220de6a426..0f87f8181c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_i2s.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_i2s.h @@ -5,7 +5,7 @@ * I2S IP definitions * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_ipc.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_ipc.h index 3c9de860ed..ea33d1fc98 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_ipc.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_ipc.h @@ -5,7 +5,7 @@ * IPC IP definitions * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_ipc_v2.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_ipc_v2.h index 6d97a7dd2e..cdcfd9988a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_ipc_v2.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_ipc_v2.h @@ -5,7 +5,7 @@ * IPC IP definitions * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_lcd.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_lcd.h index 57ffce75a4..33704501da 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_lcd.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_lcd.h @@ -5,7 +5,7 @@ * LCD IP definitions * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_lcd_v2.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_lcd_v2.h new file mode 100644 index 0000000000..baf7559b68 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_lcd_v2.h @@ -0,0 +1,103 @@ +/***************************************************************************//** +* \file cyip_lcd_v2.h +* +* \brief +* LCD IP definitions +* +* \note +* Generator version: 1.5.0.1274 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CYIP_LCD_V2_H_ +#define _CYIP_LCD_V2_H_ + +#include "cyip_headers.h" + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD_V2_SECTION_SIZE 0x00010000UL + +/** + * \brief LCD Controller Block (LCD) + */ +typedef struct { + __IM uint32_t ID; /*!< 0x00000000 ID & Revision */ + __IOM uint32_t DIVIDER; /*!< 0x00000004 LCD Divider Register */ + __IOM uint32_t CONTROL; /*!< 0x00000008 LCD Configuration Register */ + __IM uint32_t RESERVED[61]; + __IOM uint32_t DATA0[8]; /*!< 0x00000100 LCD Pin Data Registers */ + __IM uint32_t RESERVED1[56]; + __IOM uint32_t DATA1[8]; /*!< 0x00000200 LCD Pin Data Registers */ + __IM uint32_t RESERVED2[56]; + __IOM uint32_t DATA2[8]; /*!< 0x00000300 LCD Pin Data Registers */ + __IM uint32_t RESERVED3[56]; + __IOM uint32_t DATA3[8]; /*!< 0x00000400 LCD Pin Data Registers */ +} LCD_V2_Type; /*!< Size = 1056 (0x420) */ + + +/* LCD.ID */ +#define LCD_V2_ID_ID_Pos 0UL +#define LCD_V2_ID_ID_Msk 0xFFFFUL +#define LCD_V2_ID_REVISION_Pos 16UL +#define LCD_V2_ID_REVISION_Msk 0xFFFF0000UL +/* LCD.DIVIDER */ +#define LCD_V2_DIVIDER_SUBFR_DIV_Pos 0UL +#define LCD_V2_DIVIDER_SUBFR_DIV_Msk 0xFFFFUL +#define LCD_V2_DIVIDER_DEAD_DIV_Pos 16UL +#define LCD_V2_DIVIDER_DEAD_DIV_Msk 0xFFFF0000UL +/* LCD.CONTROL */ +#define LCD_V2_CONTROL_LS_EN_Pos 0UL +#define LCD_V2_CONTROL_LS_EN_Msk 0x1UL +#define LCD_V2_CONTROL_HS_EN_Pos 1UL +#define LCD_V2_CONTROL_HS_EN_Msk 0x2UL +#define LCD_V2_CONTROL_LCD_MODE_Pos 2UL +#define LCD_V2_CONTROL_LCD_MODE_Msk 0x4UL +#define LCD_V2_CONTROL_TYPE_Pos 3UL +#define LCD_V2_CONTROL_TYPE_Msk 0x8UL +#define LCD_V2_CONTROL_OP_MODE_Pos 4UL +#define LCD_V2_CONTROL_OP_MODE_Msk 0x10UL +#define LCD_V2_CONTROL_BIAS_Pos 5UL +#define LCD_V2_CONTROL_BIAS_Msk 0x60UL +#define LCD_V2_CONTROL_CLOCK_LS_SEL_Pos 7UL +#define LCD_V2_CONTROL_CLOCK_LS_SEL_Msk 0x80UL +#define LCD_V2_CONTROL_COM_NUM_Pos 8UL +#define LCD_V2_CONTROL_COM_NUM_Msk 0xF00UL +#define LCD_V2_CONTROL_LS_EN_STAT_Pos 31UL +#define LCD_V2_CONTROL_LS_EN_STAT_Msk 0x80000000UL +/* LCD.DATA0 */ +#define LCD_V2_DATA0_DATA_Pos 0UL +#define LCD_V2_DATA0_DATA_Msk 0xFFFFFFFFUL +/* LCD.DATA1 */ +#define LCD_V2_DATA1_DATA_Pos 0UL +#define LCD_V2_DATA1_DATA_Msk 0xFFFFFFFFUL +/* LCD.DATA2 */ +#define LCD_V2_DATA2_DATA_Pos 0UL +#define LCD_V2_DATA2_DATA_Msk 0xFFFFFFFFUL +/* LCD.DATA3 */ +#define LCD_V2_DATA3_DATA_Pos 0UL +#define LCD_V2_DATA3_DATA_Msk 0xFFFFFFFFUL + + +#endif /* _CYIP_LCD_V2_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_lpcomp.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_lpcomp.h index 48710051c8..93134b82db 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_lpcomp.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_lpcomp.h @@ -5,7 +5,7 @@ * LPCOMP IP definitions * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_pass.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_pass.h index 000206db2b..992dcae631 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_pass.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_pass.h @@ -5,7 +5,7 @@ * PASS IP definitions * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_pdm.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_pdm.h index 45bff05e83..f7758f9345 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_pdm.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_pdm.h @@ -5,7 +5,7 @@ * PDM IP definitions * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_peri.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_peri.h index 41678c4b25..5dc3fbaeed 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_peri.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_peri.h @@ -5,7 +5,7 @@ * PERI IP definitions * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_peri_ms_v2.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_peri_ms_v2.h index 3390ba4e4e..a964140df4 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_peri_ms_v2.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_peri_ms_v2.h @@ -5,7 +5,7 @@ * PERI_MS IP definitions * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_peri_v2.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_peri_v2.h index c0786e8047..6f3ac9d46f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_peri_v2.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_peri_v2.h @@ -5,7 +5,7 @@ * PERI IP definitions * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_profile.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_profile.h index 00125d9043..d11abb374e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_profile.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_profile.h @@ -5,7 +5,7 @@ * PROFILE IP definitions * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_prot.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_prot.h index dd4e1d578a..69dfc355f7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_prot.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_prot.h @@ -5,7 +5,7 @@ * PROT IP definitions * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_prot_v2.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_prot_v2.h index 068081bb9e..e00466dec8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_prot_v2.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_prot_v2.h @@ -5,7 +5,7 @@ * PROT IP definitions * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -91,7 +91,7 @@ typedef struct { */ typedef struct { __IOM uint32_t MS_CTL; /*!< 0x00000000 Master control */ - __IM uint32_t RESERVED[127]; + __IM uint32_t MS_CTL_READ_MIR[127]; /*!< 0x00000004 Master control read mirror */ PROT_MPU_MPU_STRUCT_V2_Type MPU_STRUCT[16]; /*!< 0x00000200 MPU structure */ } PROT_MPU_V2_Type; /*!< Size = 1024 (0x400) */ @@ -375,6 +375,11 @@ typedef struct { #define PROT_MPU_V2_MS_CTL_PC_Msk 0xFUL #define PROT_MPU_V2_MS_CTL_PC_SAVED_Pos 16UL #define PROT_MPU_V2_MS_CTL_PC_SAVED_Msk 0xF0000UL +/* PROT_MPU.MS_CTL_READ_MIR */ +#define PROT_MPU_V2_MS_CTL_READ_MIR_PC_Pos 0UL +#define PROT_MPU_V2_MS_CTL_READ_MIR_PC_Msk 0xFUL +#define PROT_MPU_V2_MS_CTL_READ_MIR_PC_SAVED_Pos 16UL +#define PROT_MPU_V2_MS_CTL_READ_MIR_PC_SAVED_Msk 0xF0000UL #endif /* _CYIP_PROT_V2_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_sar.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_sar.h index 82f85ee007..44fd7a2cce 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_sar.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_sar.h @@ -5,7 +5,7 @@ * SAR IP definitions * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_scb.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_scb.h index cf796869d0..565271a7bd 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_scb.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_scb.h @@ -5,7 +5,7 @@ * SCB IP definitions * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -59,53 +59,51 @@ typedef struct { __IOM uint32_t I2C_M_CMD; /*!< 0x00000068 I2C master command */ __IOM uint32_t I2C_S_CMD; /*!< 0x0000006C I2C slave command */ __IOM uint32_t I2C_CFG; /*!< 0x00000070 I2C configuration */ - __IM uint32_t RESERVED3[35]; - __IOM uint32_t DDFT_CTRL; /*!< 0x00000100 Digital DfT control */ - __IM uint32_t RESERVED4[63]; + __IM uint32_t RESERVED3[99]; __IOM uint32_t TX_CTRL; /*!< 0x00000200 Transmitter control */ __IOM uint32_t TX_FIFO_CTRL; /*!< 0x00000204 Transmitter FIFO control */ __IM uint32_t TX_FIFO_STATUS; /*!< 0x00000208 Transmitter FIFO status */ - __IM uint32_t RESERVED5[13]; + __IM uint32_t RESERVED4[13]; __OM uint32_t TX_FIFO_WR; /*!< 0x00000240 Transmitter FIFO write */ - __IM uint32_t RESERVED6[47]; + __IM uint32_t RESERVED5[47]; __IOM uint32_t RX_CTRL; /*!< 0x00000300 Receiver control */ __IOM uint32_t RX_FIFO_CTRL; /*!< 0x00000304 Receiver FIFO control */ __IM uint32_t RX_FIFO_STATUS; /*!< 0x00000308 Receiver FIFO status */ - __IM uint32_t RESERVED7; + __IM uint32_t RESERVED6; __IOM uint32_t RX_MATCH; /*!< 0x00000310 Slave address and mask */ - __IM uint32_t RESERVED8[11]; + __IM uint32_t RESERVED7[11]; __IM uint32_t RX_FIFO_RD; /*!< 0x00000340 Receiver FIFO read */ __IM uint32_t RX_FIFO_RD_SILENT; /*!< 0x00000344 Receiver FIFO read silent */ - __IM uint32_t RESERVED9[46]; + __IM uint32_t RESERVED8[46]; __IOM uint32_t EZ_DATA[512]; /*!< 0x00000400 Memory buffer */ - __IM uint32_t RESERVED10[128]; + __IM uint32_t RESERVED9[128]; __IM uint32_t INTR_CAUSE; /*!< 0x00000E00 Active clocked interrupt signal */ - __IM uint32_t RESERVED11[31]; + __IM uint32_t RESERVED10[31]; __IOM uint32_t INTR_I2C_EC; /*!< 0x00000E80 Externally clocked I2C interrupt request */ - __IM uint32_t RESERVED12; + __IM uint32_t RESERVED11; __IOM uint32_t INTR_I2C_EC_MASK; /*!< 0x00000E88 Externally clocked I2C interrupt mask */ __IM uint32_t INTR_I2C_EC_MASKED; /*!< 0x00000E8C Externally clocked I2C interrupt masked */ - __IM uint32_t RESERVED13[12]; + __IM uint32_t RESERVED12[12]; __IOM uint32_t INTR_SPI_EC; /*!< 0x00000EC0 Externally clocked SPI interrupt request */ - __IM uint32_t RESERVED14; + __IM uint32_t RESERVED13; __IOM uint32_t INTR_SPI_EC_MASK; /*!< 0x00000EC8 Externally clocked SPI interrupt mask */ __IM uint32_t INTR_SPI_EC_MASKED; /*!< 0x00000ECC Externally clocked SPI interrupt masked */ - __IM uint32_t RESERVED15[12]; + __IM uint32_t RESERVED14[12]; __IOM uint32_t INTR_M; /*!< 0x00000F00 Master interrupt request */ __IOM uint32_t INTR_M_SET; /*!< 0x00000F04 Master interrupt set request */ __IOM uint32_t INTR_M_MASK; /*!< 0x00000F08 Master interrupt mask */ __IM uint32_t INTR_M_MASKED; /*!< 0x00000F0C Master interrupt masked request */ - __IM uint32_t RESERVED16[12]; + __IM uint32_t RESERVED15[12]; __IOM uint32_t INTR_S; /*!< 0x00000F40 Slave interrupt request */ __IOM uint32_t INTR_S_SET; /*!< 0x00000F44 Slave interrupt set request */ __IOM uint32_t INTR_S_MASK; /*!< 0x00000F48 Slave interrupt mask */ __IM uint32_t INTR_S_MASKED; /*!< 0x00000F4C Slave interrupt masked request */ - __IM uint32_t RESERVED17[12]; + __IM uint32_t RESERVED16[12]; __IOM uint32_t INTR_TX; /*!< 0x00000F80 Transmitter interrupt request */ __IOM uint32_t INTR_TX_SET; /*!< 0x00000F84 Transmitter interrupt set request */ __IOM uint32_t INTR_TX_MASK; /*!< 0x00000F88 Transmitter interrupt mask */ __IM uint32_t INTR_TX_MASKED; /*!< 0x00000F8C Transmitter interrupt masked request */ - __IM uint32_t RESERVED18[12]; + __IM uint32_t RESERVED17[12]; __IOM uint32_t INTR_RX; /*!< 0x00000FC0 Receiver interrupt request */ __IOM uint32_t INTR_RX_SET; /*!< 0x00000FC4 Receiver interrupt set request */ __IOM uint32_t INTR_RX_MASK; /*!< 0x00000FC8 Receiver interrupt mask */ @@ -307,15 +305,6 @@ typedef struct { #define SCB_I2C_CFG_SDA_OUT_FILT2_TRIM_Msk 0x300000UL #define SCB_I2C_CFG_SDA_OUT_FILT_SEL_Pos 28UL #define SCB_I2C_CFG_SDA_OUT_FILT_SEL_Msk 0x30000000UL -/* SCB.DDFT_CTRL */ -#define SCB_DDFT_CTRL_DDFT_IN0_SEL_Pos 0UL -#define SCB_DDFT_CTRL_DDFT_IN0_SEL_Msk 0x1UL -#define SCB_DDFT_CTRL_DDFT_IN1_SEL_Pos 4UL -#define SCB_DDFT_CTRL_DDFT_IN1_SEL_Msk 0x10UL -#define SCB_DDFT_CTRL_DDFT_OUT0_SEL_Pos 16UL -#define SCB_DDFT_CTRL_DDFT_OUT0_SEL_Msk 0x70000UL -#define SCB_DDFT_CTRL_DDFT_OUT1_SEL_Pos 20UL -#define SCB_DDFT_CTRL_DDFT_OUT1_SEL_Msk 0x700000UL /* SCB.TX_CTRL */ #define SCB_TX_CTRL_DATA_WIDTH_Pos 0UL #define SCB_TX_CTRL_DATA_WIDTH_Msk 0xFUL diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_sdhc.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_sdhc.h index d16d4839c2..7700cccc4e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_sdhc.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_sdhc.h @@ -5,7 +5,7 @@ * SDHC IP definitions * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_sflash.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_sflash.h index f44269e524..633f2517b0 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_sflash.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_sflash.h @@ -5,7 +5,7 @@ * SFLASH IP definitions * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -45,10 +45,7 @@ typedef struct { __IOM uint16_t SILICON_ID; /*!< 0x00000002 Indicates Silicon ID of the device */ __IM uint32_t RESERVED1[2]; __IOM uint16_t FAMILY_ID; /*!< 0x0000000C Indicates Family ID of the device */ - __IOM uint8_t FB_HARDFAULT; /*!< 0x0000000E Flash boot Hard fault */ - __IM uint8_t RESERVED2; - __IOM uint32_t FLASHC_GEOMETRY; /*!< 0x00000010 Contains Flash Memory Geomerty structure, Format and data shall - be equal to FLASHC_GEOMETRY MMIO register */ + __IM uint16_t RESERVED2[3]; __IOM uint32_t CPUSS_WOUNDING; /*!< 0x00000014 CPUSS Wounding */ __IM uint32_t RESERVED3[378]; __IOM uint8_t DIE_LOT[3]; /*!< 0x00000600 Lot Number (3 bytes) */ @@ -116,11 +113,11 @@ typedef struct { __IOM uint32_t TOC1_MAGIC_NUMBER; /*!< 0x00007804 Magic number(0x01211219) */ __IOM uint32_t TOC1_FHASH_OBJECTS; /*!< 0x00007808 Number of objects starting from offset 0xC to be verified for FACTORY_HASH */ - __IOM uint32_t TOC1_SFLASH_GENERAL_TRIM_ADDR; /*!< 0x0000780C Address of trims stored in SFLASH */ + __IOM uint32_t TOC1_GENERAL_TRIM_ADDR_UNUSED; /*!< 0x0000780C Unused (Address is Hardcoded in ROM) */ __IOM uint32_t TOC1_UNIQUE_ID_ADDR; /*!< 0x00007810 Address of Unique ID stored in SFLASH */ __IOM uint32_t TOC1_FB_OBJECT_ADDR; /*!< 0x00007814 Addresss of FLASH Boot(FB) object that include FLASH patch also */ - __IOM uint32_t TOC1_SYSCALL_TABLE_ADDR; /*!< 0x00007818 Address of SYSCALL_TABLE entry in SFLASH */ - __IOM uint32_t TOC1_BOOT_PROTECTION_ADDR; /*!< 0x0000781C Address of boot protection object */ + __IOM uint32_t TOC1_SYSCALL_TABLE_ADDR_UNUSED; /*!< 0x00007818 Unused (Address is Hardcoded in ROM) */ + __IOM uint32_t TOC1_OBJECT_ADDR_UNUSED; /*!< 0x0000781C Unused (Address is Hardcoded in ROM) */ __IM uint32_t RESERVED16[119]; __IOM uint32_t TOC1_CRC_ADDR; /*!< 0x000079FC Upper 2 bytes contain CRC16-CCITT and lower 2 bytes are 0 */ __IOM uint32_t RTOC1_OBJECT_SIZE; /*!< 0x00007A00 Redundant Object size in bytes for CRC calculation starting @@ -128,12 +125,13 @@ typedef struct { __IOM uint32_t RTOC1_MAGIC_NUMBER; /*!< 0x00007A04 Redundant Magic number(0x01211219) */ __IOM uint32_t RTOC1_FHASH_OBJECTS; /*!< 0x00007A08 Redundant Number of objects starting from offset 0xC to be verified for FACTORY_HASH */ - __IOM uint32_t RTOC1_SFLASH_GENERAL_TRIM_ADDR; /*!< 0x00007A0C Redundant Address of trims stored in SFLASH */ + __IOM uint32_t RTOC1_GENERAL_TRIM_ADDR_UNUSED; /*!< 0x00007A0C Redundant Unused (Address is Hardcoded in ROM) */ __IOM uint32_t RTOC1_UNIQUE_ID_ADDR; /*!< 0x00007A10 Redundant Address of Unique ID stored in SFLASH */ __IOM uint32_t RTOC1_FB_OBJECT_ADDR; /*!< 0x00007A14 Redundant Addresss of FLASH Boot(FB) object that include FLASH patch also */ - __IOM uint32_t RTOC1_SYSCALL_TABLE_ADDR; /*!< 0x00007A18 Redundant Address of SYSCALL_TABLE entry in SFLASH */ - __IM uint32_t RESERVED17[120]; + __IOM uint32_t RTOC1_SYSCALL_TABLE_ADDR_UNUSED; /*!< 0x00007A18 Redundant Unused (Address is Hardcoded in ROM) */ + __IOM uint32_t RTOC1_OBJECT_ADDR_UNUSED; /*!< 0x00007A1C Redundant Unused (Address is Hardcoded in ROM) */ + __IM uint32_t RESERVED17[119]; __IOM uint32_t RTOC1_CRC_ADDR; /*!< 0x00007BFC Redundant CRC,Upper 2 bytes contain CRC16-CCITT and lower 2 bytes are 0 */ __IOM uint32_t TOC2_OBJECT_SIZE; /*!< 0x00007C00 Object size in bytes for CRC calculation starting from offset @@ -153,8 +151,7 @@ typedef struct { SECURE_HASH(SHASH) */ __IOM uint32_t TOC2_SIGNATURE_VERIF_KEY; /*!< 0x00007C24 Address of signature verification key (0 if none).The object is signature specific key. It is the public key in case of RSA */ - __IM uint32_t RESERVED18[115]; - __IOM uint32_t TOC2_FB_HARDFAULT; /*!< 0x00007DF4 TOC2 Flash Boot Hard fault */ + __IM uint32_t RESERVED18[116]; __IOM uint32_t TOC2_FLAGS; /*!< 0x00007DF8 TOC2_FLAGS */ __IOM uint32_t TOC2_CRC_ADDR; /*!< 0x00007DFC CRC,Upper 2 bytes contain CRC16-CCITT and lower 2 bytes are 0 */ __IOM uint32_t RTOC2_OBJECT_SIZE; /*!< 0x00007E00 Redundant Object size in bytes for CRC calculation starting @@ -191,12 +188,6 @@ typedef struct { /* SFLASH.FAMILY_ID */ #define SFLASH_FAMILY_ID_FAMILY_ID_Pos 0UL #define SFLASH_FAMILY_ID_FAMILY_ID_Msk 0xFFFFUL -/* SFLASH.FB_HARDFAULT */ -#define SFLASH_FB_HARDFAULT_FB_HARDFAULT_Pos 0UL -#define SFLASH_FB_HARDFAULT_FB_HARDFAULT_Msk 0xFFUL -/* SFLASH.FLASHC_GEOMETRY */ -#define SFLASH_FLASHC_GEOMETRY_FLASHC_GEOMETRY_Pos 0UL -#define SFLASH_FLASHC_GEOMETRY_FLASHC_GEOMETRY_Msk 0xFFFFFFFFUL /* SFLASH.CPUSS_WOUNDING */ #define SFLASH_CPUSS_WOUNDING_CPUSS_WOUNDING_Pos 0UL #define SFLASH_CPUSS_WOUNDING_CPUSS_WOUNDING_Msk 0xFFFFFFFFUL @@ -377,21 +368,21 @@ typedef struct { /* SFLASH.TOC1_FHASH_OBJECTS */ #define SFLASH_TOC1_FHASH_OBJECTS_DATA32_Pos 0UL #define SFLASH_TOC1_FHASH_OBJECTS_DATA32_Msk 0xFFFFFFFFUL -/* SFLASH.TOC1_SFLASH_GENERAL_TRIM_ADDR */ -#define SFLASH_TOC1_SFLASH_GENERAL_TRIM_ADDR_DATA32_Pos 0UL -#define SFLASH_TOC1_SFLASH_GENERAL_TRIM_ADDR_DATA32_Msk 0xFFFFFFFFUL +/* SFLASH.TOC1_GENERAL_TRIM_ADDR_UNUSED */ +#define SFLASH_TOC1_GENERAL_TRIM_ADDR_UNUSED_DATA32_Pos 0UL +#define SFLASH_TOC1_GENERAL_TRIM_ADDR_UNUSED_DATA32_Msk 0xFFFFFFFFUL /* SFLASH.TOC1_UNIQUE_ID_ADDR */ #define SFLASH_TOC1_UNIQUE_ID_ADDR_DATA32_Pos 0UL #define SFLASH_TOC1_UNIQUE_ID_ADDR_DATA32_Msk 0xFFFFFFFFUL /* SFLASH.TOC1_FB_OBJECT_ADDR */ #define SFLASH_TOC1_FB_OBJECT_ADDR_DATA32_Pos 0UL #define SFLASH_TOC1_FB_OBJECT_ADDR_DATA32_Msk 0xFFFFFFFFUL -/* SFLASH.TOC1_SYSCALL_TABLE_ADDR */ -#define SFLASH_TOC1_SYSCALL_TABLE_ADDR_DATA32_Pos 0UL -#define SFLASH_TOC1_SYSCALL_TABLE_ADDR_DATA32_Msk 0xFFFFFFFFUL -/* SFLASH.TOC1_BOOT_PROTECTION_ADDR */ -#define SFLASH_TOC1_BOOT_PROTECTION_ADDR_DATA32_Pos 0UL -#define SFLASH_TOC1_BOOT_PROTECTION_ADDR_DATA32_Msk 0xFFFFFFFFUL +/* SFLASH.TOC1_SYSCALL_TABLE_ADDR_UNUSED */ +#define SFLASH_TOC1_SYSCALL_TABLE_ADDR_UNUSED_DATA32_Pos 0UL +#define SFLASH_TOC1_SYSCALL_TABLE_ADDR_UNUSED_DATA32_Msk 0xFFFFFFFFUL +/* SFLASH.TOC1_OBJECT_ADDR_UNUSED */ +#define SFLASH_TOC1_OBJECT_ADDR_UNUSED_DATA32_Pos 0UL +#define SFLASH_TOC1_OBJECT_ADDR_UNUSED_DATA32_Msk 0xFFFFFFFFUL /* SFLASH.TOC1_CRC_ADDR */ #define SFLASH_TOC1_CRC_ADDR_DATA32_Pos 0UL #define SFLASH_TOC1_CRC_ADDR_DATA32_Msk 0xFFFFFFFFUL @@ -404,18 +395,21 @@ typedef struct { /* SFLASH.RTOC1_FHASH_OBJECTS */ #define SFLASH_RTOC1_FHASH_OBJECTS_DATA32_Pos 0UL #define SFLASH_RTOC1_FHASH_OBJECTS_DATA32_Msk 0xFFFFFFFFUL -/* SFLASH.RTOC1_SFLASH_GENERAL_TRIM_ADDR */ -#define SFLASH_RTOC1_SFLASH_GENERAL_TRIM_ADDR_DATA32_Pos 0UL -#define SFLASH_RTOC1_SFLASH_GENERAL_TRIM_ADDR_DATA32_Msk 0xFFFFFFFFUL +/* SFLASH.RTOC1_GENERAL_TRIM_ADDR_UNUSED */ +#define SFLASH_RTOC1_GENERAL_TRIM_ADDR_UNUSED_DATA32_Pos 0UL +#define SFLASH_RTOC1_GENERAL_TRIM_ADDR_UNUSED_DATA32_Msk 0xFFFFFFFFUL /* SFLASH.RTOC1_UNIQUE_ID_ADDR */ #define SFLASH_RTOC1_UNIQUE_ID_ADDR_DATA32_Pos 0UL #define SFLASH_RTOC1_UNIQUE_ID_ADDR_DATA32_Msk 0xFFFFFFFFUL /* SFLASH.RTOC1_FB_OBJECT_ADDR */ #define SFLASH_RTOC1_FB_OBJECT_ADDR_DATA32_Pos 0UL #define SFLASH_RTOC1_FB_OBJECT_ADDR_DATA32_Msk 0xFFFFFFFFUL -/* SFLASH.RTOC1_SYSCALL_TABLE_ADDR */ -#define SFLASH_RTOC1_SYSCALL_TABLE_ADDR_DATA32_Pos 0UL -#define SFLASH_RTOC1_SYSCALL_TABLE_ADDR_DATA32_Msk 0xFFFFFFFFUL +/* SFLASH.RTOC1_SYSCALL_TABLE_ADDR_UNUSED */ +#define SFLASH_RTOC1_SYSCALL_TABLE_ADDR_UNUSED_DATA32_Pos 0UL +#define SFLASH_RTOC1_SYSCALL_TABLE_ADDR_UNUSED_DATA32_Msk 0xFFFFFFFFUL +/* SFLASH.RTOC1_OBJECT_ADDR_UNUSED */ +#define SFLASH_RTOC1_OBJECT_ADDR_UNUSED_DATA32_Pos 0UL +#define SFLASH_RTOC1_OBJECT_ADDR_UNUSED_DATA32_Msk 0xFFFFFFFFUL /* SFLASH.RTOC1_CRC_ADDR */ #define SFLASH_RTOC1_CRC_ADDR_DATA32_Pos 0UL #define SFLASH_RTOC1_CRC_ADDR_DATA32_Msk 0xFFFFFFFFUL @@ -449,9 +443,6 @@ typedef struct { /* SFLASH.TOC2_SIGNATURE_VERIF_KEY */ #define SFLASH_TOC2_SIGNATURE_VERIF_KEY_DATA32_Pos 0UL #define SFLASH_TOC2_SIGNATURE_VERIF_KEY_DATA32_Msk 0xFFFFFFFFUL -/* SFLASH.TOC2_FB_HARDFAULT */ -#define SFLASH_TOC2_FB_HARDFAULT_DATA32_Pos 0UL -#define SFLASH_TOC2_FB_HARDFAULT_DATA32_Msk 0xFFFFFFFFUL /* SFLASH.TOC2_FLAGS */ #define SFLASH_TOC2_FLAGS_CLOCK_CONFIG_Pos 0UL #define SFLASH_TOC2_FLAGS_CLOCK_CONFIG_Msk 0x3UL diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_smartio.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_smartio.h index 7e01fc990c..97cea6df7c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_smartio.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_smartio.h @@ -5,7 +5,7 @@ * SMARTIO IP definitions * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_smartio_v2.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_smartio_v2.h index 2d6b9708fe..40d2d5cab2 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_smartio_v2.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_smartio_v2.h @@ -5,7 +5,7 @@ * SMARTIO IP definitions * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_smif.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_smif.h index c29dac5fa2..2ec627f056 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_smif.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_smif.h @@ -5,7 +5,7 @@ * SMIF IP definitions * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_srss.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_srss.h index 103d24f955..38e58ba7dc 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_srss.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_srss.h @@ -5,7 +5,7 @@ * SRSS IP definitions * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -92,35 +92,38 @@ typedef struct { __IM uint32_t CLK_ECO_STATUS; /*!< 0x00000530 ECO Status Register */ __IM uint32_t RESERVED7[2]; __IOM uint32_t CLK_PILO_CONFIG; /*!< 0x0000053C Precision ILO Configuration Register */ - __IM uint32_t RESERVED8[16]; + __IM uint32_t RESERVED8; + __IOM uint32_t CLK_MF_SELECT; /*!< 0x00000544 Medium Frequency Clock Select Register */ + __IOM uint32_t CLK_MFO_CONFIG; /*!< 0x00000548 MFO Configuration Register */ + __IM uint32_t RESERVED9[13]; __IOM uint32_t CLK_FLL_CONFIG; /*!< 0x00000580 FLL Configuration Register */ __IOM uint32_t CLK_FLL_CONFIG2; /*!< 0x00000584 FLL Configuration Register 2 */ __IOM uint32_t CLK_FLL_CONFIG3; /*!< 0x00000588 FLL Configuration Register 3 */ __IOM uint32_t CLK_FLL_CONFIG4; /*!< 0x0000058C FLL Configuration Register 4 */ __IOM uint32_t CLK_FLL_STATUS; /*!< 0x00000590 FLL Status Register */ - __IM uint32_t RESERVED9[27]; + __IM uint32_t RESERVED10[27]; __IOM uint32_t CLK_PLL_CONFIG[15]; /*!< 0x00000600 PLL Configuration Register */ - __IM uint32_t RESERVED10; + __IM uint32_t RESERVED11; __IOM uint32_t CLK_PLL_STATUS[15]; /*!< 0x00000640 PLL Status Register */ - __IM uint32_t RESERVED11[33]; + __IM uint32_t RESERVED12[33]; __IOM uint32_t SRSS_INTR; /*!< 0x00000700 SRSS Interrupt Register */ __IOM uint32_t SRSS_INTR_SET; /*!< 0x00000704 SRSS Interrupt Set Register */ __IOM uint32_t SRSS_INTR_MASK; /*!< 0x00000708 SRSS Interrupt Mask Register */ __IM uint32_t SRSS_INTR_MASKED; /*!< 0x0000070C SRSS Interrupt Masked Register */ __IOM uint32_t SRSS_INTR_CFG; /*!< 0x00000710 SRSS Interrupt Configuration Register */ - __IM uint32_t RESERVED12[59]; + __IM uint32_t RESERVED13[59]; __IOM uint32_t RES_CAUSE; /*!< 0x00000800 Reset Cause Observation Register */ __IOM uint32_t RES_CAUSE2; /*!< 0x00000804 Reset Cause Observation Register 2 */ - __IM uint32_t RESERVED13[7614]; + __IM uint32_t RESERVED14[7614]; __IOM uint32_t PWR_TRIM_REF_CTL; /*!< 0x00007F00 Reference Trim Register */ __IOM uint32_t PWR_TRIM_BODOVP_CTL; /*!< 0x00007F04 BOD/OVP Trim Register */ __IOM uint32_t CLK_TRIM_CCO_CTL; /*!< 0x00007F08 CCO Trim Register */ __IOM uint32_t CLK_TRIM_CCO_CTL2; /*!< 0x00007F0C CCO Trim Register 2 */ - __IM uint32_t RESERVED14[8]; + __IM uint32_t RESERVED15[8]; __IOM uint32_t PWR_TRIM_WAKE_CTL; /*!< 0x00007F30 Wakeup Trim Register */ - __IM uint32_t RESERVED15[8183]; + __IM uint32_t RESERVED16[8183]; __IOM uint32_t PWR_TRIM_LVD_CTL; /*!< 0x0000FF10 LVD Trim Register */ - __IM uint32_t RESERVED16; + __IM uint32_t RESERVED17; __IOM uint32_t CLK_TRIM_ILO_CTL; /*!< 0x0000FF18 ILO Trim Register */ __IOM uint32_t PWR_TRIM_PWRSYS_CTL; /*!< 0x0000FF1C Power System Trim Register */ __IOM uint32_t CLK_TRIM_ECO_CTL; /*!< 0x0000FF20 ECO Trim Register */ @@ -390,6 +393,18 @@ typedef struct { #define SRSS_CLK_PILO_CONFIG_PILO_RESET_N_Msk 0x40000000UL #define SRSS_CLK_PILO_CONFIG_PILO_EN_Pos 31UL #define SRSS_CLK_PILO_CONFIG_PILO_EN_Msk 0x80000000UL +/* SRSS.CLK_MF_SELECT */ +#define SRSS_CLK_MF_SELECT_MFCLK_SEL_Pos 0UL +#define SRSS_CLK_MF_SELECT_MFCLK_SEL_Msk 0x7UL +#define SRSS_CLK_MF_SELECT_MFCLK_DIV_Pos 8UL +#define SRSS_CLK_MF_SELECT_MFCLK_DIV_Msk 0xFF00UL +#define SRSS_CLK_MF_SELECT_ENABLE_Pos 31UL +#define SRSS_CLK_MF_SELECT_ENABLE_Msk 0x80000000UL +/* SRSS.CLK_MFO_CONFIG */ +#define SRSS_CLK_MFO_CONFIG_DPSLP_ENABLE_Pos 30UL +#define SRSS_CLK_MFO_CONFIG_DPSLP_ENABLE_Msk 0x40000000UL +#define SRSS_CLK_MFO_CONFIG_ENABLE_Pos 31UL +#define SRSS_CLK_MFO_CONFIG_ENABLE_Msk 0x80000000UL /* SRSS.CLK_FLL_CONFIG */ #define SRSS_CLK_FLL_CONFIG_FLL_MULT_Pos 0UL #define SRSS_CLK_FLL_CONFIG_FLL_MULT_Msk 0x3FFFFUL diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_tcpwm.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_tcpwm.h index 59dad62a9b..af38677976 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_tcpwm.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_tcpwm.h @@ -5,7 +5,7 @@ * TCPWM IP definitions * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_udb.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_udb.h index 4f8dff4a34..86c3c734c4 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_udb.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_udb.h @@ -5,7 +5,7 @@ * UDB IP definitions * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_usbfs.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_usbfs.h index d80a95c4b2..06e5bf9e04 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_usbfs.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_usbfs.h @@ -5,7 +5,7 @@ * USBFS IP definitions * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/psoc6_01_config.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/psoc6_01_config.h index 0ef4286aaf..bd57b1f796 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/psoc6_01_config.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/psoc6_01_config.h @@ -5,7 +5,7 @@ * PSoC6_01 device configuration header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/psoc6_02_config.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/psoc6_02_config.h index ac3d8d9594..3b917735fe 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/psoc6_02_config.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/psoc6_02_config.h @@ -5,7 +5,7 @@ * PSoC6_02 device configuration header * * \note -* Generator version: 1.4.0.1232 +* Generator version: 1.5.0.1274 * ******************************************************************************** * \copyright @@ -1444,86 +1444,86 @@ typedef enum /* Trigger Output Group 0 - SCB PDMA0 Triggers (OneToOne) */ typedef enum { - TRIG_OUT_1TO1_0_SCB0_TX_TO_PDMA0_TR_IN16 = 0x40001000u, /* cpuss.dw0_tr_in[16] */ - TRIG_OUT_1TO1_0_SCB0_RX_TO_PDMA0_TR_IN17 = 0x40001001u, /* cpuss.dw0_tr_in[17] */ - TRIG_OUT_1TO1_0_SCB1_TX_TO_PDMA0_TR_IN18 = 0x40001002u, /* cpuss.dw0_tr_in[18] */ - TRIG_OUT_1TO1_0_SCB1_RX_TO_PDMA0_TR_IN19 = 0x40001003u, /* cpuss.dw0_tr_in[19] */ - TRIG_OUT_1TO1_0_SCB2_TX_TO_PDMA0_TR_IN20 = 0x40001004u, /* cpuss.dw0_tr_in[20] */ - TRIG_OUT_1TO1_0_SCB2_RX_TO_PDMA0_TR_IN21 = 0x40001005u, /* cpuss.dw0_tr_in[21] */ - TRIG_OUT_1TO1_0_SCB3_TX_TO_PDMA0_TR_IN22 = 0x40001006u, /* cpuss.dw0_tr_in[22] */ - TRIG_OUT_1TO1_0_SCB3_RX_TO_PDMA0_TR_IN23 = 0x40001007u, /* cpuss.dw0_tr_in[23] */ - TRIG_OUT_1TO1_0_SCB4_TX_TO_PDMA0_TR_IN24 = 0x40001008u, /* cpuss.dw0_tr_in[24] */ - TRIG_OUT_1TO1_0_SCB4_RX_TO_PDMA0_TR_IN25 = 0x40001009u, /* cpuss.dw0_tr_in[25] */ - TRIG_OUT_1TO1_0_SCB5_TX_TO_PDMA0_TR_IN26 = 0x4000100Au, /* cpuss.dw0_tr_in[26] */ - TRIG_OUT_1TO1_0_SCB5_RX_TO_PDMA0_TR_IN27 = 0x4000100Bu /* cpuss.dw0_tr_in[27] */ + TRIG_OUT_1TO1_0_SCB0_TX_TO_PDMA0_TR_IN16 = 0x40001000u, /* From scb[0].tr_tx_req to cpuss.dw0_tr_in[16] */ + TRIG_OUT_1TO1_0_SCB0_RX_TO_PDMA0_TR_IN17 = 0x40001001u, /* From scb[0].tr_rx_req to cpuss.dw0_tr_in[17] */ + TRIG_OUT_1TO1_0_SCB1_TX_TO_PDMA0_TR_IN18 = 0x40001002u, /* From scb[1].tr_tx_req to cpuss.dw0_tr_in[18] */ + TRIG_OUT_1TO1_0_SCB1_RX_TO_PDMA0_TR_IN19 = 0x40001003u, /* From scb[1].tr_rx_req to cpuss.dw0_tr_in[19] */ + TRIG_OUT_1TO1_0_SCB2_TX_TO_PDMA0_TR_IN20 = 0x40001004u, /* From scb[2].tr_tx_req to cpuss.dw0_tr_in[20] */ + TRIG_OUT_1TO1_0_SCB2_RX_TO_PDMA0_TR_IN21 = 0x40001005u, /* From scb[2].tr_rx_req to cpuss.dw0_tr_in[21] */ + TRIG_OUT_1TO1_0_SCB3_TX_TO_PDMA0_TR_IN22 = 0x40001006u, /* From scb[3].tr_tx_req to cpuss.dw0_tr_in[22] */ + TRIG_OUT_1TO1_0_SCB3_RX_TO_PDMA0_TR_IN23 = 0x40001007u, /* From scb[3].tr_rx_req to cpuss.dw0_tr_in[23] */ + TRIG_OUT_1TO1_0_SCB4_TX_TO_PDMA0_TR_IN24 = 0x40001008u, /* From scb[4].tr_tx_req to cpuss.dw0_tr_in[24] */ + TRIG_OUT_1TO1_0_SCB4_RX_TO_PDMA0_TR_IN25 = 0x40001009u, /* From scb[4].tr_rx_req to cpuss.dw0_tr_in[25] */ + TRIG_OUT_1TO1_0_SCB5_TX_TO_PDMA0_TR_IN26 = 0x4000100Au, /* From scb[5].tr_tx_req to cpuss.dw0_tr_in[26] */ + TRIG_OUT_1TO1_0_SCB5_RX_TO_PDMA0_TR_IN27 = 0x4000100Bu /* From scb[5].tr_rx_req to cpuss.dw0_tr_in[27] */ } en_trig_output_1to1_scb_pdma0_tr_t; /* Trigger Output Group 1 - SCB PDMA1 Triggers (OneToOne) */ typedef enum { - TRIG_OUT_1TO1_1_SCB6_TX_TO_PDMA1_TR_IN8 = 0x40001100u, /* cpuss.dw1_tr_in[8] */ - TRIG_OUT_1TO1_1_SCB6_RX_TO_PDMA1_TR_IN9 = 0x40001101u, /* cpuss.dw1_tr_in[9] */ - TRIG_OUT_1TO1_1_SCB7_TX_TO_PDMA1_TR_IN10 = 0x40001102u, /* cpuss.dw1_tr_in[10] */ - TRIG_OUT_1TO1_1_SCB7_RX_TO_PDMA1_TR_IN11 = 0x40001103u, /* cpuss.dw1_tr_in[11] */ - TRIG_OUT_1TO1_1_SCB8_TX_TO_PDMA1_TR_IN12 = 0x40001104u, /* cpuss.dw1_tr_in[12] */ - TRIG_OUT_1TO1_1_SCB8_RX_TO_PDMA1_TR_IN13 = 0x40001105u, /* cpuss.dw1_tr_in[13] */ - TRIG_OUT_1TO1_1_SCB9_TX_TO_PDMA1_TR_IN14 = 0x40001106u, /* cpuss.dw1_tr_in[14] */ - TRIG_OUT_1TO1_1_SCB9_RX_TO_PDMA1_TR_IN15 = 0x40001107u, /* cpuss.dw1_tr_in[15] */ - TRIG_OUT_1TO1_1_SCB10_TX_TO_PDMA1_TR_IN16 = 0x40001108u, /* cpuss.dw1_tr_in[16] */ - TRIG_OUT_1TO1_1_SCB10_RX_TO_PDMA1_TR_IN17 = 0x40001109u, /* cpuss.dw1_tr_in[17] */ - TRIG_OUT_1TO1_1_SCB11_TX_TO_PDMA1_TR_IN18 = 0x4000110Au, /* cpuss.dw1_tr_in[18] */ - TRIG_OUT_1TO1_1_SCB11_RX_TO_PDMA1_TR_IN19 = 0x4000110Bu, /* cpuss.dw1_tr_in[19] */ - TRIG_OUT_1TO1_1_SCB12_TX_TO_PDMA1_TR_IN20 = 0x4000110Cu, /* cpuss.dw1_tr_in[20] */ - TRIG_OUT_1TO1_1_SCB12_RX_TO_PDMA1_TR_IN21 = 0x4000110Du /* cpuss.dw1_tr_in[21] */ + TRIG_OUT_1TO1_1_SCB6_TX_TO_PDMA1_TR_IN8 = 0x40001100u, /* From scb[6].tr_tx_req to cpuss.dw1_tr_in[8] */ + TRIG_OUT_1TO1_1_SCB6_RX_TO_PDMA1_TR_IN9 = 0x40001101u, /* From scb[6].tr_rx_req to cpuss.dw1_tr_in[9] */ + TRIG_OUT_1TO1_1_SCB7_TX_TO_PDMA1_TR_IN10 = 0x40001102u, /* From scb[7].tr_tx_req to cpuss.dw1_tr_in[10] */ + TRIG_OUT_1TO1_1_SCB7_RX_TO_PDMA1_TR_IN11 = 0x40001103u, /* From scb[7].tr_rx_req to cpuss.dw1_tr_in[11] */ + TRIG_OUT_1TO1_1_SCB8_TX_TO_PDMA1_TR_IN12 = 0x40001104u, /* From scb[8].tr_tx_req to cpuss.dw1_tr_in[12] */ + TRIG_OUT_1TO1_1_SCB8_RX_TO_PDMA1_TR_IN13 = 0x40001105u, /* From scb[8].tr_rx_req to cpuss.dw1_tr_in[13] */ + TRIG_OUT_1TO1_1_SCB9_TX_TO_PDMA1_TR_IN14 = 0x40001106u, /* From scb[9].tr_tx_req to cpuss.dw1_tr_in[14] */ + TRIG_OUT_1TO1_1_SCB9_RX_TO_PDMA1_TR_IN15 = 0x40001107u, /* From scb[9].tr_rx_req to cpuss.dw1_tr_in[15] */ + TRIG_OUT_1TO1_1_SCB10_TX_TO_PDMA1_TR_IN16 = 0x40001108u, /* From scb[10].tr_tx_req to cpuss.dw1_tr_in[16] */ + TRIG_OUT_1TO1_1_SCB10_RX_TO_PDMA1_TR_IN17 = 0x40001109u, /* From scb[10].tr_rx_req to cpuss.dw1_tr_in[17] */ + TRIG_OUT_1TO1_1_SCB11_TX_TO_PDMA1_TR_IN18 = 0x4000110Au, /* From scb[11].tr_tx_req to cpuss.dw1_tr_in[18] */ + TRIG_OUT_1TO1_1_SCB11_RX_TO_PDMA1_TR_IN19 = 0x4000110Bu, /* From scb[11].tr_rx_req to cpuss.dw1_tr_in[19] */ + TRIG_OUT_1TO1_1_SCB12_TX_TO_PDMA1_TR_IN20 = 0x4000110Cu, /* From scb[12].tr_tx_req to cpuss.dw1_tr_in[20] */ + TRIG_OUT_1TO1_1_SCB12_RX_TO_PDMA1_TR_IN21 = 0x4000110Du /* From scb[12].tr_rx_req to cpuss.dw1_tr_in[21] */ } en_trig_output_1to1_scb_pdma1_tr_t; /* Trigger Output Group 2 - PASS to PDMA0 direct connect (OneToOne) */ typedef enum { - TRIG_OUT_1TO1_2_PASS_SAR_DONE_TO_PDMA0_TR_IN28 = 0x40001200u /* cpuss.dw0_tr_in[28] */ + TRIG_OUT_1TO1_2_PASS_SAR_DONE_TO_PDMA0_TR_IN28 = 0x40001200u /* From pass.tr_sar_out to cpuss.dw0_tr_in[28] */ } en_trig_output_1to1_sar_to_pdma0_t; /* Trigger Output Group 3 - (OneToOne) */ typedef enum { - TRIG_OUT_1TO1_3_SMIF_TX_TO_PDMA1_TR_IN22 = 0x40001300u, /* cpuss.dw1_tr_in[22] */ - TRIG_OUT_1TO1_3_SMIF_RX_TO_PDMA1_TR_IN23 = 0x40001301u /* cpuss.dw1_tr_in[23] */ + TRIG_OUT_1TO1_3_SMIF_TX_TO_PDMA1_TR_IN22 = 0x40001300u, /* From smif.tr_tx_req to cpuss.dw1_tr_in[22] */ + TRIG_OUT_1TO1_3_SMIF_RX_TO_PDMA1_TR_IN23 = 0x40001301u /* From smif.tr_rx_req to cpuss.dw1_tr_in[23] */ } en_trig_output_1to1_smif_to_pdma1_t; /* Trigger Output Group 4 - I2S and PDM PDMA triggers (OneToOne) */ typedef enum { - TRIG_OUT_1TO1_4_I2S0_TX_TO_PDMA1_TR_IN24 = 0x40001400u, /* cpuss.dw1_tr_in[24] */ - TRIG_OUT_1TO1_4_I2S0_RX_TO_PDMA1_TR_IN25 = 0x40001401u, /* cpuss.dw1_tr_in[25] */ - TRIG_OUT_1TO1_4_PDM0_RX_TO_PDMA1_TR_IN26 = 0x40001402u, /* cpuss.dw1_tr_in[26] */ - TRIG_OUT_1TO1_4_I2S1_TX_TO_PDMA1_TR_IN27 = 0x40001403u, /* cpuss.dw1_tr_in[27] */ - TRIG_OUT_1TO1_4_I2S1_RX_TO_PDMA1_TR_IN28 = 0x40001404u /* cpuss.dw1_tr_in[28] */ + TRIG_OUT_1TO1_4_I2S0_TX_TO_PDMA1_TR_IN24 = 0x40001400u, /* From audioss[0].tr_i2s_tx_req to cpuss.dw1_tr_in[24] */ + TRIG_OUT_1TO1_4_I2S0_RX_TO_PDMA1_TR_IN25 = 0x40001401u, /* From audioss[0].tr_i2s_rx_req to cpuss.dw1_tr_in[25] */ + TRIG_OUT_1TO1_4_PDM0_RX_TO_PDMA1_TR_IN26 = 0x40001402u, /* From audioss[0].tr_pdm_rx_req to cpuss.dw1_tr_in[26] */ + TRIG_OUT_1TO1_4_I2S1_TX_TO_PDMA1_TR_IN27 = 0x40001403u, /* From audioss[1].tr_i2s_tx_req to cpuss.dw1_tr_in[27] */ + TRIG_OUT_1TO1_4_I2S1_RX_TO_PDMA1_TR_IN28 = 0x40001404u /* From audioss[1].tr_i2s_rx_req to cpuss.dw1_tr_in[28] */ } en_trig_output_1to1_audioss_pdma1_tr_t; /* Trigger Output Group 5 - USB PDMA0 Triggers (OneToOne) */ typedef enum { - TRIG_OUT_1TO1_5_USB_DMA0_TO_PDMA0_TR_IN8 = 0x40001500u, /* cpuss.dw0_tr_in[8] */ - TRIG_OUT_1TO1_5_USB_DMA1_TO_PDMA0_TR_IN9 = 0x40001501u, /* cpuss.dw0_tr_in[9] */ - TRIG_OUT_1TO1_5_USB_DMA2_TO_PDMA0_TR_IN10 = 0x40001502u, /* cpuss.dw0_tr_in[10] */ - TRIG_OUT_1TO1_5_USB_DMA3_TO_PDMA0_TR_IN11 = 0x40001503u, /* cpuss.dw0_tr_in[11] */ - TRIG_OUT_1TO1_5_USB_DMA4_TO_PDMA0_TR_IN12 = 0x40001504u, /* cpuss.dw0_tr_in[12] */ - TRIG_OUT_1TO1_5_USB_DMA5_TO_PDMA0_TR_IN13 = 0x40001505u, /* cpuss.dw0_tr_in[13] */ - TRIG_OUT_1TO1_5_USB_DMA6_TO_PDMA0_TR_IN14 = 0x40001506u, /* cpuss.dw0_tr_in[14] */ - TRIG_OUT_1TO1_5_USB_DMA7_TO_PDMA0_TR_IN15 = 0x40001507u /* cpuss.dw0_tr_in[15] */ + TRIG_OUT_1TO1_5_USB_DMA0_TO_PDMA0_TR_IN8 = 0x40001500u, /* From usb.dma_req[0] to cpuss.dw0_tr_in[8] */ + TRIG_OUT_1TO1_5_USB_DMA1_TO_PDMA0_TR_IN9 = 0x40001501u, /* From usb.dma_req[1] to cpuss.dw0_tr_in[9] */ + TRIG_OUT_1TO1_5_USB_DMA2_TO_PDMA0_TR_IN10 = 0x40001502u, /* From usb.dma_req[2] to cpuss.dw0_tr_in[10] */ + TRIG_OUT_1TO1_5_USB_DMA3_TO_PDMA0_TR_IN11 = 0x40001503u, /* From usb.dma_req[3] to cpuss.dw0_tr_in[11] */ + TRIG_OUT_1TO1_5_USB_DMA4_TO_PDMA0_TR_IN12 = 0x40001504u, /* From usb.dma_req[4] to cpuss.dw0_tr_in[12] */ + TRIG_OUT_1TO1_5_USB_DMA5_TO_PDMA0_TR_IN13 = 0x40001505u, /* From usb.dma_req[5] to cpuss.dw0_tr_in[13] */ + TRIG_OUT_1TO1_5_USB_DMA6_TO_PDMA0_TR_IN14 = 0x40001506u, /* From usb.dma_req[6] to cpuss.dw0_tr_in[14] */ + TRIG_OUT_1TO1_5_USB_DMA7_TO_PDMA0_TR_IN15 = 0x40001507u /* From usb.dma_req[7] to cpuss.dw0_tr_in[15] */ } en_trig_output_1to1_usb_pdma0_tr_t; /* Trigger Output Group 6 - USB PDMA0 Acknowledge Triggers (OneToOne) */ typedef enum { - TRIG_OUT_1TO1_6_PDMA0_TR_OUT8_TO_USB_ACK0 = 0x40001600u, /* usb.dma_burstend[0] */ - TRIG_OUT_1TO1_6_PDMA0_TR_OUT9_TO_USB_ACK1 = 0x40001601u, /* usb.dma_burstend[1] */ - TRIG_OUT_1TO1_6_PDMA0_TR_OUT10_TO_USB_ACK2 = 0x40001602u, /* usb.dma_burstend[2] */ - TRIG_OUT_1TO1_6_PDMA0_TR_OUT11_TO_USB_ACK3 = 0x40001603u, /* usb.dma_burstend[3] */ - TRIG_OUT_1TO1_6_PDMA0_TR_OUT12_TO_USB_ACK4 = 0x40001604u, /* usb.dma_burstend[4] */ - TRIG_OUT_1TO1_6_PDMA0_TR_OUT13_TO_USB_ACK5 = 0x40001605u, /* usb.dma_burstend[5] */ - TRIG_OUT_1TO1_6_PDMA0_TR_OUT14_TO_USB_ACK6 = 0x40001606u, /* usb.dma_burstend[6] */ - TRIG_OUT_1TO1_6_PDMA0_TR_OUT15_TO_USB_ACK7 = 0x40001607u /* usb.dma_burstend[7] */ + TRIG_OUT_1TO1_6_PDMA0_TR_OUT8_TO_USB_ACK0 = 0x40001600u, /* From cpuss.dw0_tr_out[8] to usb.dma_burstend[0] */ + TRIG_OUT_1TO1_6_PDMA0_TR_OUT9_TO_USB_ACK1 = 0x40001601u, /* From cpuss.dw0_tr_out[9] to usb.dma_burstend[1] */ + TRIG_OUT_1TO1_6_PDMA0_TR_OUT10_TO_USB_ACK2 = 0x40001602u, /* From cpuss.dw0_tr_out[10] to usb.dma_burstend[2] */ + TRIG_OUT_1TO1_6_PDMA0_TR_OUT11_TO_USB_ACK3 = 0x40001603u, /* From cpuss.dw0_tr_out[11] to usb.dma_burstend[3] */ + TRIG_OUT_1TO1_6_PDMA0_TR_OUT12_TO_USB_ACK4 = 0x40001604u, /* From cpuss.dw0_tr_out[12] to usb.dma_burstend[4] */ + TRIG_OUT_1TO1_6_PDMA0_TR_OUT13_TO_USB_ACK5 = 0x40001605u, /* From cpuss.dw0_tr_out[13] to usb.dma_burstend[5] */ + TRIG_OUT_1TO1_6_PDMA0_TR_OUT14_TO_USB_ACK6 = 0x40001606u, /* From cpuss.dw0_tr_out[14] to usb.dma_burstend[6] */ + TRIG_OUT_1TO1_6_PDMA0_TR_OUT15_TO_USB_ACK7 = 0x40001607u /* From cpuss.dw0_tr_out[15] to usb.dma_burstend[7] */ } en_trig_output_1to1_usb_pdma0_ack_tr_t; /* Level or edge detection setting for a trigger mux */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/psoc6_03_config.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/psoc6_03_config.h new file mode 100644 index 0000000000..9afc1ad61e --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/psoc6_03_config.h @@ -0,0 +1,3116 @@ +/***************************************************************************//** +* \file psoc6_03_config.h +* +* \brief +* PSoC6_03 device configuration header +* +* \note +* Generator version: 1.5.0.1274 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _PSOC6_03_CONFIG_H_ +#define _PSOC6_03_CONFIG_H_ + +/* Clock Connections */ +typedef enum +{ + PCLK_SCB0_CLOCK = 0x0000u, /* scb[0].clock */ + PCLK_SCB1_CLOCK = 0x0001u, /* scb[1].clock */ + PCLK_SCB2_CLOCK = 0x0002u, /* scb[2].clock */ + PCLK_SCB3_CLOCK = 0x0003u, /* scb[3].clock */ + PCLK_SCB4_CLOCK = 0x0004u, /* scb[4].clock */ + PCLK_SCB5_CLOCK = 0x0005u, /* scb[5].clock */ + PCLK_SCB6_CLOCK = 0x0006u, /* scb[6].clock */ + PCLK_SMARTIO8_CLOCK = 0x0007u, /* smartio[8].clock */ + PCLK_SMARTIO9_CLOCK = 0x0008u, /* smartio[9].clock */ + PCLK_TCPWM0_CLOCKS0 = 0x0009u, /* tcpwm[0].clocks[0] */ + PCLK_TCPWM0_CLOCKS1 = 0x000Au, /* tcpwm[0].clocks[1] */ + PCLK_TCPWM0_CLOCKS2 = 0x000Bu, /* tcpwm[0].clocks[2] */ + PCLK_TCPWM0_CLOCKS3 = 0x000Cu, /* tcpwm[0].clocks[3] */ + PCLK_TCPWM1_CLOCKS0 = 0x000Du, /* tcpwm[1].clocks[0] */ + PCLK_TCPWM1_CLOCKS1 = 0x000Eu, /* tcpwm[1].clocks[1] */ + PCLK_TCPWM1_CLOCKS2 = 0x000Fu, /* tcpwm[1].clocks[2] */ + PCLK_TCPWM1_CLOCKS3 = 0x0010u, /* tcpwm[1].clocks[3] */ + PCLK_TCPWM1_CLOCKS4 = 0x0011u, /* tcpwm[1].clocks[4] */ + PCLK_TCPWM1_CLOCKS5 = 0x0012u, /* tcpwm[1].clocks[5] */ + PCLK_TCPWM1_CLOCKS6 = 0x0013u, /* tcpwm[1].clocks[6] */ + PCLK_TCPWM1_CLOCKS7 = 0x0014u, /* tcpwm[1].clocks[7] */ + PCLK_CSD_CLOCK = 0x0015u, /* csd.clock */ + PCLK_LCD_CLOCK = 0x0016u, /* lcd.clock */ + PCLK_CPUSS_CLOCK_TRACE_IN = 0x0017u, /* cpuss.clock_trace_in */ + PCLK_PASS_CLOCK_PUMP_PERI = 0x0018u, /* pass.clock_pump_peri */ + PCLK_PASS_CLOCK_SAR = 0x0019u, /* pass.clock_sar */ + PCLK_CANFD0_CLOCK_CAN0 = 0x001Au, /* canfd[0].clock_can[0] */ + PCLK_USB_CLOCK_DEV_BRS = 0x001Bu /* usb.clock_dev_brs */ +} en_clk_dst_t; + +/* Trigger Group */ +/* This section contains the enums related to the Trigger multiplexer (TrigMux) driver. +* Refer to the Cypress Peripheral Driver Library Documentation, section Trigger multiplexer (TrigMux) -> Enumerated Types for details. +*/ +/* Trigger Group Inputs */ +/* Trigger Input Group 0 - PDMA0 Request Assignments */ +typedef enum +{ + TRIG_IN_MUX_0_PDMA0_TR_OUT0 = 0x00000001u, /* cpuss.dw0_tr_out[0] */ + TRIG_IN_MUX_0_PDMA0_TR_OUT1 = 0x00000002u, /* cpuss.dw0_tr_out[1] */ + TRIG_IN_MUX_0_PDMA0_TR_OUT2 = 0x00000003u, /* cpuss.dw0_tr_out[2] */ + TRIG_IN_MUX_0_PDMA0_TR_OUT3 = 0x00000004u, /* cpuss.dw0_tr_out[3] */ + TRIG_IN_MUX_0_PDMA0_TR_OUT4 = 0x00000005u, /* cpuss.dw0_tr_out[4] */ + TRIG_IN_MUX_0_PDMA0_TR_OUT5 = 0x00000006u, /* cpuss.dw0_tr_out[5] */ + TRIG_IN_MUX_0_PDMA0_TR_OUT6 = 0x00000007u, /* cpuss.dw0_tr_out[6] */ + TRIG_IN_MUX_0_PDMA0_TR_OUT7 = 0x00000008u, /* cpuss.dw0_tr_out[7] */ + TRIG_IN_MUX_0_PDMA1_TR_OUT0 = 0x00000009u, /* cpuss.dw1_tr_out[0] */ + TRIG_IN_MUX_0_PDMA1_TR_OUT1 = 0x0000000Au, /* cpuss.dw1_tr_out[1] */ + TRIG_IN_MUX_0_PDMA1_TR_OUT2 = 0x0000000Bu, /* cpuss.dw1_tr_out[2] */ + TRIG_IN_MUX_0_PDMA1_TR_OUT3 = 0x0000000Cu, /* cpuss.dw1_tr_out[3] */ + TRIG_IN_MUX_0_PDMA1_TR_OUT4 = 0x0000000Du, /* cpuss.dw1_tr_out[4] */ + TRIG_IN_MUX_0_PDMA1_TR_OUT5 = 0x0000000Eu, /* cpuss.dw1_tr_out[5] */ + TRIG_IN_MUX_0_PDMA1_TR_OUT6 = 0x0000000Fu, /* cpuss.dw1_tr_out[6] */ + TRIG_IN_MUX_0_PDMA1_TR_OUT7 = 0x00000010u, /* cpuss.dw1_tr_out[7] */ + TRIG_IN_MUX_0_TCPWM0_TR_OVERFLOW0 = 0x00000011u, /* tcpwm[0].tr_overflow[0] */ + TRIG_IN_MUX_0_TCPWM0_TR_COMPARE_MATCH0 = 0x00000012u, /* tcpwm[0].tr_compare_match[0] */ + TRIG_IN_MUX_0_TCPWM0_TR_UNDERFLOW0 = 0x00000013u, /* tcpwm[0].tr_underflow[0] */ + TRIG_IN_MUX_0_TCPWM0_TR_OVERFLOW1 = 0x00000014u, /* tcpwm[0].tr_overflow[1] */ + TRIG_IN_MUX_0_TCPWM0_TR_COMPARE_MATCH1 = 0x00000015u, /* tcpwm[0].tr_compare_match[1] */ + TRIG_IN_MUX_0_TCPWM0_TR_UNDERFLOW1 = 0x00000016u, /* tcpwm[0].tr_underflow[1] */ + TRIG_IN_MUX_0_TCPWM0_TR_OVERFLOW2 = 0x00000017u, /* tcpwm[0].tr_overflow[2] */ + TRIG_IN_MUX_0_TCPWM0_TR_COMPARE_MATCH2 = 0x00000018u, /* tcpwm[0].tr_compare_match[2] */ + TRIG_IN_MUX_0_TCPWM0_TR_UNDERFLOW2 = 0x00000019u, /* tcpwm[0].tr_underflow[2] */ + TRIG_IN_MUX_0_TCPWM0_TR_OVERFLOW3 = 0x0000001Au, /* tcpwm[0].tr_overflow[3] */ + TRIG_IN_MUX_0_TCPWM0_TR_COMPARE_MATCH3 = 0x0000001Bu, /* tcpwm[0].tr_compare_match[3] */ + TRIG_IN_MUX_0_TCPWM0_TR_UNDERFLOW3 = 0x0000001Cu, /* tcpwm[0].tr_underflow[3] */ + TRIG_IN_MUX_0_TCPWM1_TR_OVERFLOW0 = 0x0000001Du, /* tcpwm[1].tr_overflow[0] */ + TRIG_IN_MUX_0_TCPWM1_TR_COMPARE_MATCH0 = 0x0000001Eu, /* tcpwm[1].tr_compare_match[0] */ + TRIG_IN_MUX_0_TCPWM1_TR_UNDERFLOW0 = 0x0000001Fu, /* tcpwm[1].tr_underflow[0] */ + TRIG_IN_MUX_0_TCPWM1_TR_OVERFLOW1 = 0x00000020u, /* tcpwm[1].tr_overflow[1] */ + TRIG_IN_MUX_0_TCPWM1_TR_COMPARE_MATCH1 = 0x00000021u, /* tcpwm[1].tr_compare_match[1] */ + TRIG_IN_MUX_0_TCPWM1_TR_UNDERFLOW1 = 0x00000022u, /* tcpwm[1].tr_underflow[1] */ + TRIG_IN_MUX_0_TCPWM1_TR_OVERFLOW2 = 0x00000023u, /* tcpwm[1].tr_overflow[2] */ + TRIG_IN_MUX_0_TCPWM1_TR_COMPARE_MATCH2 = 0x00000024u, /* tcpwm[1].tr_compare_match[2] */ + TRIG_IN_MUX_0_TCPWM1_TR_UNDERFLOW2 = 0x00000025u, /* tcpwm[1].tr_underflow[2] */ + TRIG_IN_MUX_0_TCPWM1_TR_OVERFLOW3 = 0x00000026u, /* tcpwm[1].tr_overflow[3] */ + TRIG_IN_MUX_0_TCPWM1_TR_COMPARE_MATCH3 = 0x00000027u, /* tcpwm[1].tr_compare_match[3] */ + TRIG_IN_MUX_0_TCPWM1_TR_UNDERFLOW3 = 0x00000028u, /* tcpwm[1].tr_underflow[3] */ + TRIG_IN_MUX_0_TCPWM1_TR_OVERFLOW4 = 0x00000029u, /* tcpwm[1].tr_overflow[4] */ + TRIG_IN_MUX_0_TCPWM1_TR_COMPARE_MATCH4 = 0x0000002Au, /* tcpwm[1].tr_compare_match[4] */ + TRIG_IN_MUX_0_TCPWM1_TR_UNDERFLOW4 = 0x0000002Bu, /* tcpwm[1].tr_underflow[4] */ + TRIG_IN_MUX_0_TCPWM1_TR_OVERFLOW5 = 0x0000002Cu, /* tcpwm[1].tr_overflow[5] */ + TRIG_IN_MUX_0_TCPWM1_TR_COMPARE_MATCH5 = 0x0000002Du, /* tcpwm[1].tr_compare_match[5] */ + TRIG_IN_MUX_0_TCPWM1_TR_UNDERFLOW5 = 0x0000002Eu, /* tcpwm[1].tr_underflow[5] */ + TRIG_IN_MUX_0_TCPWM1_TR_OVERFLOW6 = 0x0000002Fu, /* tcpwm[1].tr_overflow[6] */ + TRIG_IN_MUX_0_TCPWM1_TR_COMPARE_MATCH6 = 0x00000030u, /* tcpwm[1].tr_compare_match[6] */ + TRIG_IN_MUX_0_TCPWM1_TR_UNDERFLOW6 = 0x00000031u, /* tcpwm[1].tr_underflow[6] */ + TRIG_IN_MUX_0_TCPWM1_TR_OVERFLOW7 = 0x00000032u, /* tcpwm[1].tr_overflow[7] */ + TRIG_IN_MUX_0_TCPWM1_TR_COMPARE_MATCH7 = 0x00000033u, /* tcpwm[1].tr_compare_match[7] */ + TRIG_IN_MUX_0_TCPWM1_TR_UNDERFLOW7 = 0x00000034u, /* tcpwm[1].tr_underflow[7] */ + TRIG_IN_MUX_0_MDMA_TR_OUT0 = 0x00000041u, /* cpuss.dmac_tr_out[0] */ + TRIG_IN_MUX_0_MDMA_TR_OUT1 = 0x00000042u, /* cpuss.dmac_tr_out[1] */ + TRIG_IN_MUX_0_HSIOM_TR_OUT0 = 0x00000045u, /* peri.tr_io_input[0] */ + TRIG_IN_MUX_0_HSIOM_TR_OUT1 = 0x00000046u, /* peri.tr_io_input[1] */ + TRIG_IN_MUX_0_HSIOM_TR_OUT2 = 0x00000047u, /* peri.tr_io_input[2] */ + TRIG_IN_MUX_0_HSIOM_TR_OUT3 = 0x00000048u, /* peri.tr_io_input[3] */ + TRIG_IN_MUX_0_HSIOM_TR_OUT4 = 0x00000049u, /* peri.tr_io_input[4] */ + TRIG_IN_MUX_0_HSIOM_TR_OUT5 = 0x0000004Au, /* peri.tr_io_input[5] */ + TRIG_IN_MUX_0_HSIOM_TR_OUT6 = 0x0000004Bu, /* peri.tr_io_input[6] */ + TRIG_IN_MUX_0_HSIOM_TR_OUT7 = 0x0000004Cu, /* peri.tr_io_input[7] */ + TRIG_IN_MUX_0_HSIOM_TR_OUT8 = 0x0000004Du, /* peri.tr_io_input[8] */ + TRIG_IN_MUX_0_HSIOM_TR_OUT9 = 0x0000004Eu, /* peri.tr_io_input[9] */ + TRIG_IN_MUX_0_HSIOM_TR_OUT10 = 0x0000004Fu, /* peri.tr_io_input[10] */ + TRIG_IN_MUX_0_HSIOM_TR_OUT11 = 0x00000050u, /* peri.tr_io_input[11] */ + TRIG_IN_MUX_0_HSIOM_TR_OUT12 = 0x00000051u, /* peri.tr_io_input[12] */ + TRIG_IN_MUX_0_HSIOM_TR_OUT13 = 0x00000052u, /* peri.tr_io_input[13] */ + TRIG_IN_MUX_0_CTI_TR_OUT0 = 0x00000053u, /* cpuss.cti_tr_out[0] */ + TRIG_IN_MUX_0_CTI_TR_OUT1 = 0x00000054u, /* cpuss.cti_tr_out[1] */ + TRIG_IN_MUX_0_FAULT_TR_OUT0 = 0x00000055u, /* cpuss.tr_fault[0] */ + TRIG_IN_MUX_0_FAULT_TR_OUT1 = 0x00000056u /* cpuss.tr_fault[1] */ +} en_trig_input_pdma0_tr_t; + +/* Trigger Input Group 1 - PDMA1 Request Assignments */ +typedef enum +{ + TRIG_IN_MUX_1_PDMA0_TR_OUT0 = 0x00000101u, /* cpuss.dw0_tr_out[0] */ + TRIG_IN_MUX_1_PDMA0_TR_OUT1 = 0x00000102u, /* cpuss.dw0_tr_out[1] */ + TRIG_IN_MUX_1_PDMA0_TR_OUT2 = 0x00000103u, /* cpuss.dw0_tr_out[2] */ + TRIG_IN_MUX_1_PDMA0_TR_OUT3 = 0x00000104u, /* cpuss.dw0_tr_out[3] */ + TRIG_IN_MUX_1_PDMA0_TR_OUT4 = 0x00000105u, /* cpuss.dw0_tr_out[4] */ + TRIG_IN_MUX_1_PDMA0_TR_OUT5 = 0x00000106u, /* cpuss.dw0_tr_out[5] */ + TRIG_IN_MUX_1_PDMA0_TR_OUT6 = 0x00000107u, /* cpuss.dw0_tr_out[6] */ + TRIG_IN_MUX_1_PDMA0_TR_OUT7 = 0x00000108u, /* cpuss.dw0_tr_out[7] */ + TRIG_IN_MUX_1_PDMA1_TR_OUT0 = 0x00000109u, /* cpuss.dw1_tr_out[0] */ + TRIG_IN_MUX_1_PDMA1_TR_OUT1 = 0x0000010Au, /* cpuss.dw1_tr_out[1] */ + TRIG_IN_MUX_1_PDMA1_TR_OUT2 = 0x0000010Bu, /* cpuss.dw1_tr_out[2] */ + TRIG_IN_MUX_1_PDMA1_TR_OUT3 = 0x0000010Cu, /* cpuss.dw1_tr_out[3] */ + TRIG_IN_MUX_1_PDMA1_TR_OUT4 = 0x0000010Du, /* cpuss.dw1_tr_out[4] */ + TRIG_IN_MUX_1_PDMA1_TR_OUT5 = 0x0000010Eu, /* cpuss.dw1_tr_out[5] */ + TRIG_IN_MUX_1_PDMA1_TR_OUT6 = 0x0000010Fu, /* cpuss.dw1_tr_out[6] */ + TRIG_IN_MUX_1_PDMA1_TR_OUT7 = 0x00000110u, /* cpuss.dw1_tr_out[7] */ + TRIG_IN_MUX_1_MDMA_TR_OUT0 = 0x00000141u, /* cpuss.dmac_tr_out[0] */ + TRIG_IN_MUX_1_MDMA_TR_OUT1 = 0x00000142u, /* cpuss.dmac_tr_out[1] */ + TRIG_IN_MUX_1_CSD_ADC_DONE = 0x00000145u, /* csd.tr_adc_done */ + TRIG_IN_MUX_1_HSIOM_TR_OUT14 = 0x00000146u, /* peri.tr_io_input[14] */ + TRIG_IN_MUX_1_HSIOM_TR_OUT15 = 0x00000147u, /* peri.tr_io_input[15] */ + TRIG_IN_MUX_1_HSIOM_TR_OUT16 = 0x00000148u, /* peri.tr_io_input[16] */ + TRIG_IN_MUX_1_HSIOM_TR_OUT17 = 0x00000149u, /* peri.tr_io_input[17] */ + TRIG_IN_MUX_1_HSIOM_TR_OUT18 = 0x0000014Au, /* peri.tr_io_input[18] */ + TRIG_IN_MUX_1_HSIOM_TR_OUT19 = 0x0000014Bu, /* peri.tr_io_input[19] */ + TRIG_IN_MUX_1_HSIOM_TR_OUT20 = 0x0000014Cu, /* peri.tr_io_input[20] */ + TRIG_IN_MUX_1_HSIOM_TR_OUT21 = 0x0000014Du, /* peri.tr_io_input[21] */ + TRIG_IN_MUX_1_HSIOM_TR_OUT22 = 0x0000014Eu, /* peri.tr_io_input[22] */ + TRIG_IN_MUX_1_HSIOM_TR_OUT23 = 0x0000014Fu, /* peri.tr_io_input[23] */ + TRIG_IN_MUX_1_HSIOM_TR_OUT24 = 0x00000150u, /* peri.tr_io_input[24] */ + TRIG_IN_MUX_1_HSIOM_TR_OUT25 = 0x00000151u, /* peri.tr_io_input[25] */ + TRIG_IN_MUX_1_LPCOMP_DSI_COMP0 = 0x00000154u, /* lpcomp.dsi_comp0 */ + TRIG_IN_MUX_1_LPCOMP_DSI_COMP1 = 0x00000155u, /* lpcomp.dsi_comp1 */ + TRIG_IN_MUX_1_CANFD_TT_TR_OUT0 = 0x00000156u /* canfd[0].tr_tmp_rtp_out[0] */ +} en_trig_input_pdma1_tr_t; + +/* Trigger Input Group 2 - TCPWM0 trigger multiplexer */ +typedef enum +{ + TRIG_IN_MUX_2_PDMA0_TR_OUT0 = 0x00000201u, /* cpuss.dw0_tr_out[0] */ + TRIG_IN_MUX_2_PDMA0_TR_OUT1 = 0x00000202u, /* cpuss.dw0_tr_out[1] */ + TRIG_IN_MUX_2_PDMA0_TR_OUT2 = 0x00000203u, /* cpuss.dw0_tr_out[2] */ + TRIG_IN_MUX_2_PDMA0_TR_OUT3 = 0x00000204u, /* cpuss.dw0_tr_out[3] */ + TRIG_IN_MUX_2_PDMA0_TR_OUT4 = 0x00000205u, /* cpuss.dw0_tr_out[4] */ + TRIG_IN_MUX_2_PDMA0_TR_OUT5 = 0x00000206u, /* cpuss.dw0_tr_out[5] */ + TRIG_IN_MUX_2_PDMA0_TR_OUT6 = 0x00000207u, /* cpuss.dw0_tr_out[6] */ + TRIG_IN_MUX_2_PDMA0_TR_OUT7 = 0x00000208u, /* cpuss.dw0_tr_out[7] */ + TRIG_IN_MUX_2_TCPWM0_TR_OVERFLOW0 = 0x00000209u, /* tcpwm[0].tr_overflow[0] */ + TRIG_IN_MUX_2_TCPWM0_TR_COMPARE_MATCH0 = 0x0000020Au, /* tcpwm[0].tr_compare_match[0] */ + TRIG_IN_MUX_2_TCPWM0_TR_UNDERFLOW0 = 0x0000020Bu, /* tcpwm[0].tr_underflow[0] */ + TRIG_IN_MUX_2_TCPWM0_TR_OVERFLOW1 = 0x0000020Cu, /* tcpwm[0].tr_overflow[1] */ + TRIG_IN_MUX_2_TCPWM0_TR_COMPARE_MATCH1 = 0x0000020Du, /* tcpwm[0].tr_compare_match[1] */ + TRIG_IN_MUX_2_TCPWM0_TR_UNDERFLOW1 = 0x0000020Eu, /* tcpwm[0].tr_underflow[1] */ + TRIG_IN_MUX_2_TCPWM0_TR_OVERFLOW2 = 0x0000020Fu, /* tcpwm[0].tr_overflow[2] */ + TRIG_IN_MUX_2_TCPWM0_TR_COMPARE_MATCH2 = 0x00000210u, /* tcpwm[0].tr_compare_match[2] */ + TRIG_IN_MUX_2_TCPWM0_TR_UNDERFLOW2 = 0x00000211u, /* tcpwm[0].tr_underflow[2] */ + TRIG_IN_MUX_2_TCPWM0_TR_OVERFLOW3 = 0x00000212u, /* tcpwm[0].tr_overflow[3] */ + TRIG_IN_MUX_2_TCPWM0_TR_COMPARE_MATCH3 = 0x00000213u, /* tcpwm[0].tr_compare_match[3] */ + TRIG_IN_MUX_2_TCPWM0_TR_UNDERFLOW3 = 0x00000214u, /* tcpwm[0].tr_underflow[3] */ + TRIG_IN_MUX_2_TCPWM1_TR_OVERFLOW0 = 0x00000221u, /* tcpwm[1].tr_overflow[0] */ + TRIG_IN_MUX_2_TCPWM1_TR_COMPARE_MATCH0 = 0x00000222u, /* tcpwm[1].tr_compare_match[0] */ + TRIG_IN_MUX_2_TCPWM1_TR_UNDERFLOW0 = 0x00000223u, /* tcpwm[1].tr_underflow[0] */ + TRIG_IN_MUX_2_TCPWM1_TR_OVERFLOW1 = 0x00000224u, /* tcpwm[1].tr_overflow[1] */ + TRIG_IN_MUX_2_TCPWM1_TR_COMPARE_MATCH1 = 0x00000225u, /* tcpwm[1].tr_compare_match[1] */ + TRIG_IN_MUX_2_TCPWM1_TR_UNDERFLOW1 = 0x00000226u, /* tcpwm[1].tr_underflow[1] */ + TRIG_IN_MUX_2_TCPWM1_TR_OVERFLOW2 = 0x00000227u, /* tcpwm[1].tr_overflow[2] */ + TRIG_IN_MUX_2_TCPWM1_TR_COMPARE_MATCH2 = 0x00000228u, /* tcpwm[1].tr_compare_match[2] */ + TRIG_IN_MUX_2_TCPWM1_TR_UNDERFLOW2 = 0x00000229u, /* tcpwm[1].tr_underflow[2] */ + TRIG_IN_MUX_2_TCPWM1_TR_OVERFLOW3 = 0x0000022Au, /* tcpwm[1].tr_overflow[3] */ + TRIG_IN_MUX_2_TCPWM1_TR_COMPARE_MATCH3 = 0x0000022Bu, /* tcpwm[1].tr_compare_match[3] */ + TRIG_IN_MUX_2_TCPWM1_TR_UNDERFLOW3 = 0x0000022Cu, /* tcpwm[1].tr_underflow[3] */ + TRIG_IN_MUX_2_TCPWM1_TR_OVERFLOW4 = 0x0000022Du, /* tcpwm[1].tr_overflow[4] */ + TRIG_IN_MUX_2_TCPWM1_TR_COMPARE_MATCH4 = 0x0000022Eu, /* tcpwm[1].tr_compare_match[4] */ + TRIG_IN_MUX_2_TCPWM1_TR_UNDERFLOW4 = 0x0000022Fu, /* tcpwm[1].tr_underflow[4] */ + TRIG_IN_MUX_2_TCPWM1_TR_OVERFLOW5 = 0x00000230u, /* tcpwm[1].tr_overflow[5] */ + TRIG_IN_MUX_2_TCPWM1_TR_COMPARE_MATCH5 = 0x00000231u, /* tcpwm[1].tr_compare_match[5] */ + TRIG_IN_MUX_2_TCPWM1_TR_UNDERFLOW5 = 0x00000232u, /* tcpwm[1].tr_underflow[5] */ + TRIG_IN_MUX_2_TCPWM1_TR_OVERFLOW6 = 0x00000233u, /* tcpwm[1].tr_overflow[6] */ + TRIG_IN_MUX_2_TCPWM1_TR_COMPARE_MATCH6 = 0x00000234u, /* tcpwm[1].tr_compare_match[6] */ + TRIG_IN_MUX_2_TCPWM1_TR_UNDERFLOW6 = 0x00000235u, /* tcpwm[1].tr_underflow[6] */ + TRIG_IN_MUX_2_TCPWM1_TR_OVERFLOW7 = 0x00000236u, /* tcpwm[1].tr_overflow[7] */ + TRIG_IN_MUX_2_TCPWM1_TR_COMPARE_MATCH7 = 0x00000237u, /* tcpwm[1].tr_compare_match[7] */ + TRIG_IN_MUX_2_TCPWM1_TR_UNDERFLOW7 = 0x00000238u, /* tcpwm[1].tr_underflow[7] */ + TRIG_IN_MUX_2_MDMA_TR_OUT0 = 0x00000239u, /* cpuss.dmac_tr_out[0] */ + TRIG_IN_MUX_2_MDMA_TR_OUT1 = 0x0000023Au, /* cpuss.dmac_tr_out[1] */ + TRIG_IN_MUX_2_SCB_I2C_SCL0 = 0x0000023Du, /* scb[0].tr_i2c_scl_filtered */ + TRIG_IN_MUX_2_SCB_TX0 = 0x0000023Eu, /* scb[0].tr_tx_req */ + TRIG_IN_MUX_2_SCB_RX0 = 0x0000023Fu, /* scb[0].tr_rx_req */ + TRIG_IN_MUX_2_SCB_I2C_SCL1 = 0x00000240u, /* scb[1].tr_i2c_scl_filtered */ + TRIG_IN_MUX_2_SCB_TX1 = 0x00000241u, /* scb[1].tr_tx_req */ + TRIG_IN_MUX_2_SCB_RX1 = 0x00000242u, /* scb[1].tr_rx_req */ + TRIG_IN_MUX_2_SCB_I2C_SCL2 = 0x00000243u, /* scb[2].tr_i2c_scl_filtered */ + TRIG_IN_MUX_2_SCB_TX2 = 0x00000244u, /* scb[2].tr_tx_req */ + TRIG_IN_MUX_2_SCB_RX2 = 0x00000245u, /* scb[2].tr_rx_req */ + TRIG_IN_MUX_2_SCB_I2C_SCL3 = 0x00000246u, /* scb[3].tr_i2c_scl_filtered */ + TRIG_IN_MUX_2_SCB_TX3 = 0x00000247u, /* scb[3].tr_tx_req */ + TRIG_IN_MUX_2_SCB_RX3 = 0x00000248u, /* scb[3].tr_rx_req */ + TRIG_IN_MUX_2_SCB_I2C_SCL4 = 0x00000249u, /* scb[4].tr_i2c_scl_filtered */ + TRIG_IN_MUX_2_SCB_TX4 = 0x0000024Au, /* scb[4].tr_tx_req */ + TRIG_IN_MUX_2_SCB_RX4 = 0x0000024Bu, /* scb[4].tr_rx_req */ + TRIG_IN_MUX_2_SCB_I2C_SCL5 = 0x0000024Cu, /* scb[5].tr_i2c_scl_filtered */ + TRIG_IN_MUX_2_SCB_TX5 = 0x0000024Du, /* scb[5].tr_tx_req */ + TRIG_IN_MUX_2_SCB_RX5 = 0x0000024Eu, /* scb[5].tr_rx_req */ + TRIG_IN_MUX_2_SCB_I2C_SCL6 = 0x0000024Fu, /* scb[6].tr_i2c_scl_filtered */ + TRIG_IN_MUX_2_SCB_TX6 = 0x00000250u, /* scb[6].tr_tx_req */ + TRIG_IN_MUX_2_SCB_RX6 = 0x00000251u, /* scb[6].tr_rx_req */ + TRIG_IN_MUX_2_SMIF_TX = 0x00000264u, /* smif.tr_tx_req */ + TRIG_IN_MUX_2_SMIF_RX = 0x00000265u, /* smif.tr_rx_req */ + TRIG_IN_MUX_2_USB_DMA0 = 0x00000266u, /* usb.dma_req[0] */ + TRIG_IN_MUX_2_USB_DMA1 = 0x00000267u, /* usb.dma_req[1] */ + TRIG_IN_MUX_2_USB_DMA2 = 0x00000268u, /* usb.dma_req[2] */ + TRIG_IN_MUX_2_USB_DMA3 = 0x00000269u, /* usb.dma_req[3] */ + TRIG_IN_MUX_2_USB_DMA4 = 0x0000026Au, /* usb.dma_req[4] */ + TRIG_IN_MUX_2_USB_DMA5 = 0x0000026Bu, /* usb.dma_req[5] */ + TRIG_IN_MUX_2_USB_DMA6 = 0x0000026Cu, /* usb.dma_req[6] */ + TRIG_IN_MUX_2_USB_DMA7 = 0x0000026Du, /* usb.dma_req[7] */ + TRIG_IN_MUX_2_PASS_SAR_DONE = 0x00000273u, /* pass.tr_sar_out */ + TRIG_IN_MUX_2_CSD_SENSE = 0x00000274u, /* csd.dsi_sense_out */ + TRIG_IN_MUX_2_HSIOM_TR_OUT0 = 0x00000275u, /* peri.tr_io_input[0] */ + TRIG_IN_MUX_2_HSIOM_TR_OUT1 = 0x00000276u, /* peri.tr_io_input[1] */ + TRIG_IN_MUX_2_HSIOM_TR_OUT2 = 0x00000277u, /* peri.tr_io_input[2] */ + TRIG_IN_MUX_2_HSIOM_TR_OUT3 = 0x00000278u, /* peri.tr_io_input[3] */ + TRIG_IN_MUX_2_HSIOM_TR_OUT4 = 0x00000279u, /* peri.tr_io_input[4] */ + TRIG_IN_MUX_2_HSIOM_TR_OUT5 = 0x0000027Au, /* peri.tr_io_input[5] */ + TRIG_IN_MUX_2_HSIOM_TR_OUT6 = 0x0000027Bu, /* peri.tr_io_input[6] */ + TRIG_IN_MUX_2_HSIOM_TR_OUT7 = 0x0000027Cu, /* peri.tr_io_input[7] */ + TRIG_IN_MUX_2_HSIOM_TR_OUT8 = 0x0000027Du, /* peri.tr_io_input[8] */ + TRIG_IN_MUX_2_HSIOM_TR_OUT9 = 0x0000027Eu, /* peri.tr_io_input[9] */ + TRIG_IN_MUX_2_HSIOM_TR_OUT10 = 0x0000027Fu, /* peri.tr_io_input[10] */ + TRIG_IN_MUX_2_HSIOM_TR_OUT11 = 0x00000280u, /* peri.tr_io_input[11] */ + TRIG_IN_MUX_2_HSIOM_TR_OUT12 = 0x00000281u, /* peri.tr_io_input[12] */ + TRIG_IN_MUX_2_HSIOM_TR_OUT13 = 0x00000282u, /* peri.tr_io_input[13] */ + TRIG_IN_MUX_2_CTI_TR_OUT0 = 0x00000283u, /* cpuss.cti_tr_out[0] */ + TRIG_IN_MUX_2_CTI_TR_OUT1 = 0x00000284u, /* cpuss.cti_tr_out[1] */ + TRIG_IN_MUX_2_LPCOMP_DSI_COMP0 = 0x00000285u, /* lpcomp.dsi_comp0 */ + TRIG_IN_MUX_2_LPCOMP_DSI_COMP1 = 0x00000286u, /* lpcomp.dsi_comp1 */ + TRIG_IN_MUX_2_CANFD_TT_TR_OUT0 = 0x00000287u /* canfd[0].tr_tmp_rtp_out[0] */ +} en_trig_input_tcpwm0_t; + +/* Trigger Input Group 3 - TCPWM1 trigger multiplexer */ +typedef enum +{ + TRIG_IN_MUX_3_PDMA1_TR_OUT0 = 0x00000301u, /* cpuss.dw1_tr_out[0] */ + TRIG_IN_MUX_3_PDMA1_TR_OUT1 = 0x00000302u, /* cpuss.dw1_tr_out[1] */ + TRIG_IN_MUX_3_PDMA1_TR_OUT2 = 0x00000303u, /* cpuss.dw1_tr_out[2] */ + TRIG_IN_MUX_3_PDMA1_TR_OUT3 = 0x00000304u, /* cpuss.dw1_tr_out[3] */ + TRIG_IN_MUX_3_PDMA1_TR_OUT4 = 0x00000305u, /* cpuss.dw1_tr_out[4] */ + TRIG_IN_MUX_3_PDMA1_TR_OUT5 = 0x00000306u, /* cpuss.dw1_tr_out[5] */ + TRIG_IN_MUX_3_PDMA1_TR_OUT6 = 0x00000307u, /* cpuss.dw1_tr_out[6] */ + TRIG_IN_MUX_3_PDMA1_TR_OUT7 = 0x00000308u, /* cpuss.dw1_tr_out[7] */ + TRIG_IN_MUX_3_TCPWM0_TR_OVERFLOW0 = 0x00000309u, /* tcpwm[0].tr_overflow[0] */ + TRIG_IN_MUX_3_TCPWM0_TR_COMPARE_MATCH0 = 0x0000030Au, /* tcpwm[0].tr_compare_match[0] */ + TRIG_IN_MUX_3_TCPWM0_TR_UNDERFLOW0 = 0x0000030Bu, /* tcpwm[0].tr_underflow[0] */ + TRIG_IN_MUX_3_TCPWM0_TR_OVERFLOW1 = 0x0000030Cu, /* tcpwm[0].tr_overflow[1] */ + TRIG_IN_MUX_3_TCPWM0_TR_COMPARE_MATCH1 = 0x0000030Du, /* tcpwm[0].tr_compare_match[1] */ + TRIG_IN_MUX_3_TCPWM0_TR_UNDERFLOW1 = 0x0000030Eu, /* tcpwm[0].tr_underflow[1] */ + TRIG_IN_MUX_3_TCPWM0_TR_OVERFLOW2 = 0x0000030Fu, /* tcpwm[0].tr_overflow[2] */ + TRIG_IN_MUX_3_TCPWM0_TR_COMPARE_MATCH2 = 0x00000310u, /* tcpwm[0].tr_compare_match[2] */ + TRIG_IN_MUX_3_TCPWM0_TR_UNDERFLOW2 = 0x00000311u, /* tcpwm[0].tr_underflow[2] */ + TRIG_IN_MUX_3_TCPWM0_TR_OVERFLOW3 = 0x00000312u, /* tcpwm[0].tr_overflow[3] */ + TRIG_IN_MUX_3_TCPWM0_TR_COMPARE_MATCH3 = 0x00000313u, /* tcpwm[0].tr_compare_match[3] */ + TRIG_IN_MUX_3_TCPWM0_TR_UNDERFLOW3 = 0x00000314u, /* tcpwm[0].tr_underflow[3] */ + TRIG_IN_MUX_3_TCPWM1_TR_OVERFLOW0 = 0x00000321u, /* tcpwm[1].tr_overflow[0] */ + TRIG_IN_MUX_3_TCPWM1_TR_COMPARE_MATCH0 = 0x00000322u, /* tcpwm[1].tr_compare_match[0] */ + TRIG_IN_MUX_3_TCPWM1_TR_UNDERFLOW0 = 0x00000323u, /* tcpwm[1].tr_underflow[0] */ + TRIG_IN_MUX_3_TCPWM1_TR_OVERFLOW1 = 0x00000324u, /* tcpwm[1].tr_overflow[1] */ + TRIG_IN_MUX_3_TCPWM1_TR_COMPARE_MATCH1 = 0x00000325u, /* tcpwm[1].tr_compare_match[1] */ + TRIG_IN_MUX_3_TCPWM1_TR_UNDERFLOW1 = 0x00000326u, /* tcpwm[1].tr_underflow[1] */ + TRIG_IN_MUX_3_TCPWM1_TR_OVERFLOW2 = 0x00000327u, /* tcpwm[1].tr_overflow[2] */ + TRIG_IN_MUX_3_TCPWM1_TR_COMPARE_MATCH2 = 0x00000328u, /* tcpwm[1].tr_compare_match[2] */ + TRIG_IN_MUX_3_TCPWM1_TR_UNDERFLOW2 = 0x00000329u, /* tcpwm[1].tr_underflow[2] */ + TRIG_IN_MUX_3_TCPWM1_TR_OVERFLOW3 = 0x0000032Au, /* tcpwm[1].tr_overflow[3] */ + TRIG_IN_MUX_3_TCPWM1_TR_COMPARE_MATCH3 = 0x0000032Bu, /* tcpwm[1].tr_compare_match[3] */ + TRIG_IN_MUX_3_TCPWM1_TR_UNDERFLOW3 = 0x0000032Cu, /* tcpwm[1].tr_underflow[3] */ + TRIG_IN_MUX_3_TCPWM1_TR_OVERFLOW4 = 0x0000032Du, /* tcpwm[1].tr_overflow[4] */ + TRIG_IN_MUX_3_TCPWM1_TR_COMPARE_MATCH4 = 0x0000032Eu, /* tcpwm[1].tr_compare_match[4] */ + TRIG_IN_MUX_3_TCPWM1_TR_UNDERFLOW4 = 0x0000032Fu, /* tcpwm[1].tr_underflow[4] */ + TRIG_IN_MUX_3_TCPWM1_TR_OVERFLOW5 = 0x00000330u, /* tcpwm[1].tr_overflow[5] */ + TRIG_IN_MUX_3_TCPWM1_TR_COMPARE_MATCH5 = 0x00000331u, /* tcpwm[1].tr_compare_match[5] */ + TRIG_IN_MUX_3_TCPWM1_TR_UNDERFLOW5 = 0x00000332u, /* tcpwm[1].tr_underflow[5] */ + TRIG_IN_MUX_3_TCPWM1_TR_OVERFLOW6 = 0x00000333u, /* tcpwm[1].tr_overflow[6] */ + TRIG_IN_MUX_3_TCPWM1_TR_COMPARE_MATCH6 = 0x00000334u, /* tcpwm[1].tr_compare_match[6] */ + TRIG_IN_MUX_3_TCPWM1_TR_UNDERFLOW6 = 0x00000335u, /* tcpwm[1].tr_underflow[6] */ + TRIG_IN_MUX_3_TCPWM1_TR_OVERFLOW7 = 0x00000336u, /* tcpwm[1].tr_overflow[7] */ + TRIG_IN_MUX_3_TCPWM1_TR_COMPARE_MATCH7 = 0x00000337u, /* tcpwm[1].tr_compare_match[7] */ + TRIG_IN_MUX_3_TCPWM1_TR_UNDERFLOW7 = 0x00000338u, /* tcpwm[1].tr_underflow[7] */ + TRIG_IN_MUX_3_MDMA_TR_OUT0 = 0x00000339u, /* cpuss.dmac_tr_out[0] */ + TRIG_IN_MUX_3_MDMA_TR_OUT1 = 0x0000033Au, /* cpuss.dmac_tr_out[1] */ + TRIG_IN_MUX_3_SCB_I2C_SCL0 = 0x0000033Du, /* scb[0].tr_i2c_scl_filtered */ + TRIG_IN_MUX_3_SCB_TX0 = 0x0000033Eu, /* scb[0].tr_tx_req */ + TRIG_IN_MUX_3_SCB_RX0 = 0x0000033Fu, /* scb[0].tr_rx_req */ + TRIG_IN_MUX_3_SCB_I2C_SCL1 = 0x00000340u, /* scb[1].tr_i2c_scl_filtered */ + TRIG_IN_MUX_3_SCB_TX1 = 0x00000341u, /* scb[1].tr_tx_req */ + TRIG_IN_MUX_3_SCB_RX1 = 0x00000342u, /* scb[1].tr_rx_req */ + TRIG_IN_MUX_3_SCB_I2C_SCL2 = 0x00000343u, /* scb[2].tr_i2c_scl_filtered */ + TRIG_IN_MUX_3_SCB_TX2 = 0x00000344u, /* scb[2].tr_tx_req */ + TRIG_IN_MUX_3_SCB_RX2 = 0x00000345u, /* scb[2].tr_rx_req */ + TRIG_IN_MUX_3_SCB_I2C_SCL3 = 0x00000346u, /* scb[3].tr_i2c_scl_filtered */ + TRIG_IN_MUX_3_SCB_TX3 = 0x00000347u, /* scb[3].tr_tx_req */ + TRIG_IN_MUX_3_SCB_RX3 = 0x00000348u, /* scb[3].tr_rx_req */ + TRIG_IN_MUX_3_SCB_I2C_SCL4 = 0x00000349u, /* scb[4].tr_i2c_scl_filtered */ + TRIG_IN_MUX_3_SCB_TX4 = 0x0000034Au, /* scb[4].tr_tx_req */ + TRIG_IN_MUX_3_SCB_RX4 = 0x0000034Bu, /* scb[4].tr_rx_req */ + TRIG_IN_MUX_3_SCB_I2C_SCL5 = 0x0000034Cu, /* scb[5].tr_i2c_scl_filtered */ + TRIG_IN_MUX_3_SCB_TX5 = 0x0000034Du, /* scb[5].tr_tx_req */ + TRIG_IN_MUX_3_SCB_RX5 = 0x0000034Eu, /* scb[5].tr_rx_req */ + TRIG_IN_MUX_3_SCB_I2C_SCL6 = 0x0000034Fu, /* scb[6].tr_i2c_scl_filtered */ + TRIG_IN_MUX_3_SCB_TX6 = 0x00000350u, /* scb[6].tr_tx_req */ + TRIG_IN_MUX_3_SCB_RX6 = 0x00000351u, /* scb[6].tr_rx_req */ + TRIG_IN_MUX_3_SMIF_TX = 0x00000364u, /* smif.tr_tx_req */ + TRIG_IN_MUX_3_SMIF_RX = 0x00000365u, /* smif.tr_rx_req */ + TRIG_IN_MUX_3_USB_DMA0 = 0x00000366u, /* usb.dma_req[0] */ + TRIG_IN_MUX_3_USB_DMA1 = 0x00000367u, /* usb.dma_req[1] */ + TRIG_IN_MUX_3_USB_DMA2 = 0x00000368u, /* usb.dma_req[2] */ + TRIG_IN_MUX_3_USB_DMA3 = 0x00000369u, /* usb.dma_req[3] */ + TRIG_IN_MUX_3_USB_DMA4 = 0x0000036Au, /* usb.dma_req[4] */ + TRIG_IN_MUX_3_USB_DMA5 = 0x0000036Bu, /* usb.dma_req[5] */ + TRIG_IN_MUX_3_USB_DMA6 = 0x0000036Cu, /* usb.dma_req[6] */ + TRIG_IN_MUX_3_USB_DMA7 = 0x0000036Du, /* usb.dma_req[7] */ + TRIG_IN_MUX_3_PASS_SAR_DONE = 0x00000373u, /* pass.tr_sar_out */ + TRIG_IN_MUX_3_CSD_SENSE = 0x00000374u, /* csd.dsi_sense_out */ + TRIG_IN_MUX_3_HSIOM_TR_OUT14 = 0x00000375u, /* peri.tr_io_input[14] */ + TRIG_IN_MUX_3_HSIOM_TR_OUT15 = 0x00000376u, /* peri.tr_io_input[15] */ + TRIG_IN_MUX_3_HSIOM_TR_OUT16 = 0x00000377u, /* peri.tr_io_input[16] */ + TRIG_IN_MUX_3_HSIOM_TR_OUT17 = 0x00000378u, /* peri.tr_io_input[17] */ + TRIG_IN_MUX_3_HSIOM_TR_OUT18 = 0x00000379u, /* peri.tr_io_input[18] */ + TRIG_IN_MUX_3_HSIOM_TR_OUT19 = 0x0000037Au, /* peri.tr_io_input[19] */ + TRIG_IN_MUX_3_HSIOM_TR_OUT20 = 0x0000037Bu, /* peri.tr_io_input[20] */ + TRIG_IN_MUX_3_HSIOM_TR_OUT21 = 0x0000037Cu, /* peri.tr_io_input[21] */ + TRIG_IN_MUX_3_HSIOM_TR_OUT22 = 0x0000037Du, /* peri.tr_io_input[22] */ + TRIG_IN_MUX_3_HSIOM_TR_OUT23 = 0x0000037Eu, /* peri.tr_io_input[23] */ + TRIG_IN_MUX_3_HSIOM_TR_OUT24 = 0x0000037Fu, /* peri.tr_io_input[24] */ + TRIG_IN_MUX_3_HSIOM_TR_OUT25 = 0x00000380u, /* peri.tr_io_input[25] */ + TRIG_IN_MUX_3_FAULT_TR_OUT0 = 0x00000383u, /* cpuss.tr_fault[0] */ + TRIG_IN_MUX_3_FAULT_TR_OUT1 = 0x00000384u, /* cpuss.tr_fault[1] */ + TRIG_IN_MUX_3_LPCOMP_DSI_COMP0 = 0x00000385u, /* lpcomp.dsi_comp0 */ + TRIG_IN_MUX_3_LPCOMP_DSI_COMP1 = 0x00000386u, /* lpcomp.dsi_comp1 */ + TRIG_IN_MUX_3_CANFD_TT_TR_OUT0 = 0x00000387u /* canfd[0].tr_tmp_rtp_out[0] */ +} en_trig_input_tcpwm1_t; + +/* Trigger Input Group 4 - HSIOM trigger multiplexer */ +typedef enum +{ + TRIG_IN_MUX_4_PDMA0_TR_OUT0 = 0x00000401u, /* cpuss.dw0_tr_out[0] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT1 = 0x00000402u, /* cpuss.dw0_tr_out[1] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT2 = 0x00000403u, /* cpuss.dw0_tr_out[2] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT3 = 0x00000404u, /* cpuss.dw0_tr_out[3] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT4 = 0x00000405u, /* cpuss.dw0_tr_out[4] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT5 = 0x00000406u, /* cpuss.dw0_tr_out[5] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT6 = 0x00000407u, /* cpuss.dw0_tr_out[6] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT7 = 0x00000408u, /* cpuss.dw0_tr_out[7] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT8 = 0x00000409u, /* cpuss.dw0_tr_out[8] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT9 = 0x0000040Au, /* cpuss.dw0_tr_out[9] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT10 = 0x0000040Bu, /* cpuss.dw0_tr_out[10] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT11 = 0x0000040Cu, /* cpuss.dw0_tr_out[11] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT12 = 0x0000040Du, /* cpuss.dw0_tr_out[12] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT13 = 0x0000040Eu, /* cpuss.dw0_tr_out[13] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT14 = 0x0000040Fu, /* cpuss.dw0_tr_out[14] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT15 = 0x00000410u, /* cpuss.dw0_tr_out[15] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT16 = 0x00000411u, /* cpuss.dw0_tr_out[16] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT17 = 0x00000412u, /* cpuss.dw0_tr_out[17] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT18 = 0x00000413u, /* cpuss.dw0_tr_out[18] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT19 = 0x00000414u, /* cpuss.dw0_tr_out[19] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT20 = 0x00000415u, /* cpuss.dw0_tr_out[20] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT21 = 0x00000416u, /* cpuss.dw0_tr_out[21] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT22 = 0x00000417u, /* cpuss.dw0_tr_out[22] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT23 = 0x00000418u, /* cpuss.dw0_tr_out[23] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT24 = 0x00000419u, /* cpuss.dw0_tr_out[24] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT25 = 0x0000041Au, /* cpuss.dw0_tr_out[25] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT26 = 0x0000041Bu, /* cpuss.dw0_tr_out[26] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT27 = 0x0000041Cu, /* cpuss.dw0_tr_out[27] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT28 = 0x0000041Du, /* cpuss.dw0_tr_out[28] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT0 = 0x0000041Eu, /* cpuss.dw1_tr_out[0] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT1 = 0x0000041Fu, /* cpuss.dw1_tr_out[1] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT2 = 0x00000420u, /* cpuss.dw1_tr_out[2] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT3 = 0x00000421u, /* cpuss.dw1_tr_out[3] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT4 = 0x00000422u, /* cpuss.dw1_tr_out[4] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT5 = 0x00000423u, /* cpuss.dw1_tr_out[5] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT6 = 0x00000424u, /* cpuss.dw1_tr_out[6] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT7 = 0x00000425u, /* cpuss.dw1_tr_out[7] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT8 = 0x00000426u, /* cpuss.dw1_tr_out[8] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT9 = 0x00000427u, /* cpuss.dw1_tr_out[9] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT10 = 0x00000428u, /* cpuss.dw1_tr_out[10] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT11 = 0x00000429u, /* cpuss.dw1_tr_out[11] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT12 = 0x0000042Au, /* cpuss.dw1_tr_out[12] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT13 = 0x0000042Bu, /* cpuss.dw1_tr_out[13] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT14 = 0x0000042Cu, /* cpuss.dw1_tr_out[14] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT15 = 0x0000042Du, /* cpuss.dw1_tr_out[15] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT16 = 0x0000042Eu, /* cpuss.dw1_tr_out[16] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT17 = 0x0000042Fu, /* cpuss.dw1_tr_out[17] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT18 = 0x00000430u, /* cpuss.dw1_tr_out[18] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT19 = 0x00000431u, /* cpuss.dw1_tr_out[19] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT20 = 0x00000432u, /* cpuss.dw1_tr_out[20] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT21 = 0x00000433u, /* cpuss.dw1_tr_out[21] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT22 = 0x00000434u, /* cpuss.dw1_tr_out[22] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT23 = 0x00000435u, /* cpuss.dw1_tr_out[23] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT24 = 0x00000436u, /* cpuss.dw1_tr_out[24] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT25 = 0x00000437u, /* cpuss.dw1_tr_out[25] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT26 = 0x00000438u, /* cpuss.dw1_tr_out[26] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT27 = 0x00000439u, /* cpuss.dw1_tr_out[27] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT28 = 0x0000043Au, /* cpuss.dw1_tr_out[28] */ + TRIG_IN_MUX_4_TCPWM0_TR_OVERFLOW0 = 0x0000043Bu, /* tcpwm[0].tr_overflow[0] */ + TRIG_IN_MUX_4_TCPWM0_TR_COMPARE_MATCH0 = 0x0000043Cu, /* tcpwm[0].tr_compare_match[0] */ + TRIG_IN_MUX_4_TCPWM0_TR_UNDERFLOW0 = 0x0000043Du, /* tcpwm[0].tr_underflow[0] */ + TRIG_IN_MUX_4_TCPWM0_TR_OVERFLOW1 = 0x0000043Eu, /* tcpwm[0].tr_overflow[1] */ + TRIG_IN_MUX_4_TCPWM0_TR_COMPARE_MATCH1 = 0x0000043Fu, /* tcpwm[0].tr_compare_match[1] */ + TRIG_IN_MUX_4_TCPWM0_TR_UNDERFLOW1 = 0x00000440u, /* tcpwm[0].tr_underflow[1] */ + TRIG_IN_MUX_4_TCPWM0_TR_OVERFLOW2 = 0x00000441u, /* tcpwm[0].tr_overflow[2] */ + TRIG_IN_MUX_4_TCPWM0_TR_COMPARE_MATCH2 = 0x00000442u, /* tcpwm[0].tr_compare_match[2] */ + TRIG_IN_MUX_4_TCPWM0_TR_UNDERFLOW2 = 0x00000443u, /* tcpwm[0].tr_underflow[2] */ + TRIG_IN_MUX_4_TCPWM0_TR_OVERFLOW3 = 0x00000444u, /* tcpwm[0].tr_overflow[3] */ + TRIG_IN_MUX_4_TCPWM0_TR_COMPARE_MATCH3 = 0x00000445u, /* tcpwm[0].tr_compare_match[3] */ + TRIG_IN_MUX_4_TCPWM0_TR_UNDERFLOW3 = 0x00000446u, /* tcpwm[0].tr_underflow[3] */ + TRIG_IN_MUX_4_TCPWM1_TR_OVERFLOW0 = 0x00000453u, /* tcpwm[1].tr_overflow[0] */ + TRIG_IN_MUX_4_TCPWM1_TR_COMPARE_MATCH0 = 0x00000454u, /* tcpwm[1].tr_compare_match[0] */ + TRIG_IN_MUX_4_TCPWM1_TR_UNDERFLOW0 = 0x00000455u, /* tcpwm[1].tr_underflow[0] */ + TRIG_IN_MUX_4_TCPWM1_TR_OVERFLOW1 = 0x00000456u, /* tcpwm[1].tr_overflow[1] */ + TRIG_IN_MUX_4_TCPWM1_TR_COMPARE_MATCH1 = 0x00000457u, /* tcpwm[1].tr_compare_match[1] */ + TRIG_IN_MUX_4_TCPWM1_TR_UNDERFLOW1 = 0x00000458u, /* tcpwm[1].tr_underflow[1] */ + TRIG_IN_MUX_4_TCPWM1_TR_OVERFLOW2 = 0x00000459u, /* tcpwm[1].tr_overflow[2] */ + TRIG_IN_MUX_4_TCPWM1_TR_COMPARE_MATCH2 = 0x0000045Au, /* tcpwm[1].tr_compare_match[2] */ + TRIG_IN_MUX_4_TCPWM1_TR_UNDERFLOW2 = 0x0000045Bu, /* tcpwm[1].tr_underflow[2] */ + TRIG_IN_MUX_4_TCPWM1_TR_OVERFLOW3 = 0x0000045Cu, /* tcpwm[1].tr_overflow[3] */ + TRIG_IN_MUX_4_TCPWM1_TR_COMPARE_MATCH3 = 0x0000045Du, /* tcpwm[1].tr_compare_match[3] */ + TRIG_IN_MUX_4_TCPWM1_TR_UNDERFLOW3 = 0x0000045Eu, /* tcpwm[1].tr_underflow[3] */ + TRIG_IN_MUX_4_TCPWM1_TR_OVERFLOW4 = 0x0000045Fu, /* tcpwm[1].tr_overflow[4] */ + TRIG_IN_MUX_4_TCPWM1_TR_COMPARE_MATCH4 = 0x00000460u, /* tcpwm[1].tr_compare_match[4] */ + TRIG_IN_MUX_4_TCPWM1_TR_UNDERFLOW4 = 0x00000461u, /* tcpwm[1].tr_underflow[4] */ + TRIG_IN_MUX_4_TCPWM1_TR_OVERFLOW5 = 0x00000462u, /* tcpwm[1].tr_overflow[5] */ + TRIG_IN_MUX_4_TCPWM1_TR_COMPARE_MATCH5 = 0x00000463u, /* tcpwm[1].tr_compare_match[5] */ + TRIG_IN_MUX_4_TCPWM1_TR_UNDERFLOW5 = 0x00000464u, /* tcpwm[1].tr_underflow[5] */ + TRIG_IN_MUX_4_TCPWM1_TR_OVERFLOW6 = 0x00000465u, /* tcpwm[1].tr_overflow[6] */ + TRIG_IN_MUX_4_TCPWM1_TR_COMPARE_MATCH6 = 0x00000466u, /* tcpwm[1].tr_compare_match[6] */ + TRIG_IN_MUX_4_TCPWM1_TR_UNDERFLOW6 = 0x00000467u, /* tcpwm[1].tr_underflow[6] */ + TRIG_IN_MUX_4_TCPWM1_TR_OVERFLOW7 = 0x00000468u, /* tcpwm[1].tr_overflow[7] */ + TRIG_IN_MUX_4_TCPWM1_TR_COMPARE_MATCH7 = 0x00000469u, /* tcpwm[1].tr_compare_match[7] */ + TRIG_IN_MUX_4_TCPWM1_TR_UNDERFLOW7 = 0x0000046Au, /* tcpwm[1].tr_underflow[7] */ + TRIG_IN_MUX_4_MDMA_TR_OUT0 = 0x0000049Bu, /* cpuss.dmac_tr_out[0] */ + TRIG_IN_MUX_4_MDMA_TR_OUT1 = 0x0000049Cu, /* cpuss.dmac_tr_out[1] */ + TRIG_IN_MUX_4_SCB_I2C_SCL0 = 0x0000049Fu, /* scb[0].tr_i2c_scl_filtered */ + TRIG_IN_MUX_4_SCB_TX0 = 0x000004A0u, /* scb[0].tr_tx_req */ + TRIG_IN_MUX_4_SCB_RX0 = 0x000004A1u, /* scb[0].tr_rx_req */ + TRIG_IN_MUX_4_SCB_I2C_SCL1 = 0x000004A2u, /* scb[1].tr_i2c_scl_filtered */ + TRIG_IN_MUX_4_SCB_TX1 = 0x000004A3u, /* scb[1].tr_tx_req */ + TRIG_IN_MUX_4_SCB_RX1 = 0x000004A4u, /* scb[1].tr_rx_req */ + TRIG_IN_MUX_4_SCB_I2C_SCL2 = 0x000004A5u, /* scb[2].tr_i2c_scl_filtered */ + TRIG_IN_MUX_4_SCB_TX2 = 0x000004A6u, /* scb[2].tr_tx_req */ + TRIG_IN_MUX_4_SCB_RX2 = 0x000004A7u, /* scb[2].tr_rx_req */ + TRIG_IN_MUX_4_SCB_I2C_SCL3 = 0x000004A8u, /* scb[3].tr_i2c_scl_filtered */ + TRIG_IN_MUX_4_SCB_TX3 = 0x000004A9u, /* scb[3].tr_tx_req */ + TRIG_IN_MUX_4_SCB_RX3 = 0x000004AAu, /* scb[3].tr_rx_req */ + TRIG_IN_MUX_4_SCB_I2C_SCL4 = 0x000004ABu, /* scb[4].tr_i2c_scl_filtered */ + TRIG_IN_MUX_4_SCB_TX4 = 0x000004ACu, /* scb[4].tr_tx_req */ + TRIG_IN_MUX_4_SCB_RX4 = 0x000004ADu, /* scb[4].tr_rx_req */ + TRIG_IN_MUX_4_SCB_I2C_SCL5 = 0x000004AEu, /* scb[5].tr_i2c_scl_filtered */ + TRIG_IN_MUX_4_SCB_TX5 = 0x000004AFu, /* scb[5].tr_tx_req */ + TRIG_IN_MUX_4_SCB_RX5 = 0x000004B0u, /* scb[5].tr_rx_req */ + TRIG_IN_MUX_4_SCB_I2C_SCL6 = 0x000004B1u, /* scb[6].tr_i2c_scl_filtered */ + TRIG_IN_MUX_4_SCB_TX6 = 0x000004B2u, /* scb[6].tr_tx_req */ + TRIG_IN_MUX_4_SCB_RX6 = 0x000004B3u, /* scb[6].tr_rx_req */ + TRIG_IN_MUX_4_SMIF_TX = 0x000004C6u, /* smif.tr_tx_req */ + TRIG_IN_MUX_4_SMIF_RX = 0x000004C7u, /* smif.tr_rx_req */ + TRIG_IN_MUX_4_USB_DMA0 = 0x000004C8u, /* usb.dma_req[0] */ + TRIG_IN_MUX_4_USB_DMA1 = 0x000004C9u, /* usb.dma_req[1] */ + TRIG_IN_MUX_4_USB_DMA2 = 0x000004CAu, /* usb.dma_req[2] */ + TRIG_IN_MUX_4_USB_DMA3 = 0x000004CBu, /* usb.dma_req[3] */ + TRIG_IN_MUX_4_USB_DMA4 = 0x000004CCu, /* usb.dma_req[4] */ + TRIG_IN_MUX_4_USB_DMA5 = 0x000004CDu, /* usb.dma_req[5] */ + TRIG_IN_MUX_4_USB_DMA6 = 0x000004CEu, /* usb.dma_req[6] */ + TRIG_IN_MUX_4_USB_DMA7 = 0x000004CFu, /* usb.dma_req[7] */ + TRIG_IN_MUX_4_CSD_SENSE = 0x000004D5u, /* csd.dsi_sense_out */ + TRIG_IN_MUX_4_CSD_SAMPLE = 0x000004D6u, /* csd.dsi_sample_out */ + TRIG_IN_MUX_4_CSD_ADC_DONE = 0x000004D7u, /* csd.tr_adc_done */ + TRIG_IN_MUX_4_PASS_SAR_DONE = 0x000004D8u, /* pass.tr_sar_out */ + TRIG_IN_MUX_4_FAULT_TR_OUT0 = 0x000004D9u, /* cpuss.tr_fault[0] */ + TRIG_IN_MUX_4_FAULT_TR_OUT1 = 0x000004DAu, /* cpuss.tr_fault[1] */ + TRIG_IN_MUX_4_CTI_TR_OUT0 = 0x000004DBu, /* cpuss.cti_tr_out[0] */ + TRIG_IN_MUX_4_CTI_TR_OUT1 = 0x000004DCu, /* cpuss.cti_tr_out[1] */ + TRIG_IN_MUX_4_LPCOMP_DSI_COMP0 = 0x000004DDu, /* lpcomp.dsi_comp0 */ + TRIG_IN_MUX_4_LPCOMP_DSI_COMP1 = 0x000004DEu, /* lpcomp.dsi_comp1 */ + TRIG_IN_MUX_4_CANFD_TT_TR_OUT0 = 0x000004DFu, /* canfd[0].tr_tmp_rtp_out[0] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT29 = 0x000004E0u, /* cpuss.dw1_tr_out[29] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT30 = 0x000004E1u, /* cpuss.dw1_tr_out[30] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT31 = 0x000004E2u /* cpuss.dw1_tr_out[31] */ +} en_trig_input_hsiom_t; + +/* Trigger Input Group 5 - CPUSS Debug trigger multiplexer */ +typedef enum +{ + TRIG_IN_MUX_5_PDMA0_TR_OUT0 = 0x00000501u, /* cpuss.dw0_tr_out[0] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT1 = 0x00000502u, /* cpuss.dw0_tr_out[1] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT2 = 0x00000503u, /* cpuss.dw0_tr_out[2] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT3 = 0x00000504u, /* cpuss.dw0_tr_out[3] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT4 = 0x00000505u, /* cpuss.dw0_tr_out[4] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT5 = 0x00000506u, /* cpuss.dw0_tr_out[5] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT6 = 0x00000507u, /* cpuss.dw0_tr_out[6] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT7 = 0x00000508u, /* cpuss.dw0_tr_out[7] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT8 = 0x00000509u, /* cpuss.dw0_tr_out[8] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT9 = 0x0000050Au, /* cpuss.dw0_tr_out[9] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT10 = 0x0000050Bu, /* cpuss.dw0_tr_out[10] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT11 = 0x0000050Cu, /* cpuss.dw0_tr_out[11] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT12 = 0x0000050Du, /* cpuss.dw0_tr_out[12] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT13 = 0x0000050Eu, /* cpuss.dw0_tr_out[13] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT14 = 0x0000050Fu, /* cpuss.dw0_tr_out[14] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT15 = 0x00000510u, /* cpuss.dw0_tr_out[15] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT16 = 0x00000511u, /* cpuss.dw0_tr_out[16] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT17 = 0x00000512u, /* cpuss.dw0_tr_out[17] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT18 = 0x00000513u, /* cpuss.dw0_tr_out[18] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT19 = 0x00000514u, /* cpuss.dw0_tr_out[19] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT20 = 0x00000515u, /* cpuss.dw0_tr_out[20] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT21 = 0x00000516u, /* cpuss.dw0_tr_out[21] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT22 = 0x00000517u, /* cpuss.dw0_tr_out[22] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT23 = 0x00000518u, /* cpuss.dw0_tr_out[23] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT24 = 0x00000519u, /* cpuss.dw0_tr_out[24] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT25 = 0x0000051Au, /* cpuss.dw0_tr_out[25] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT26 = 0x0000051Bu, /* cpuss.dw0_tr_out[26] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT27 = 0x0000051Cu, /* cpuss.dw0_tr_out[27] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT28 = 0x0000051Du, /* cpuss.dw0_tr_out[28] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT0 = 0x0000051Eu, /* cpuss.dw1_tr_out[0] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT1 = 0x0000051Fu, /* cpuss.dw1_tr_out[1] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT2 = 0x00000520u, /* cpuss.dw1_tr_out[2] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT3 = 0x00000521u, /* cpuss.dw1_tr_out[3] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT4 = 0x00000522u, /* cpuss.dw1_tr_out[4] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT5 = 0x00000523u, /* cpuss.dw1_tr_out[5] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT6 = 0x00000524u, /* cpuss.dw1_tr_out[6] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT7 = 0x00000525u, /* cpuss.dw1_tr_out[7] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT8 = 0x00000526u, /* cpuss.dw1_tr_out[8] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT9 = 0x00000527u, /* cpuss.dw1_tr_out[9] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT10 = 0x00000528u, /* cpuss.dw1_tr_out[10] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT11 = 0x00000529u, /* cpuss.dw1_tr_out[11] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT12 = 0x0000052Au, /* cpuss.dw1_tr_out[12] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT13 = 0x0000052Bu, /* cpuss.dw1_tr_out[13] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT14 = 0x0000052Cu, /* cpuss.dw1_tr_out[14] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT15 = 0x0000052Du, /* cpuss.dw1_tr_out[15] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT16 = 0x0000052Eu, /* cpuss.dw1_tr_out[16] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT17 = 0x0000052Fu, /* cpuss.dw1_tr_out[17] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT18 = 0x00000530u, /* cpuss.dw1_tr_out[18] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT19 = 0x00000531u, /* cpuss.dw1_tr_out[19] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT20 = 0x00000532u, /* cpuss.dw1_tr_out[20] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT21 = 0x00000533u, /* cpuss.dw1_tr_out[21] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT22 = 0x00000534u, /* cpuss.dw1_tr_out[22] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT23 = 0x00000535u, /* cpuss.dw1_tr_out[23] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT24 = 0x00000536u, /* cpuss.dw1_tr_out[24] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT25 = 0x00000537u, /* cpuss.dw1_tr_out[25] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT26 = 0x00000538u, /* cpuss.dw1_tr_out[26] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT27 = 0x00000539u, /* cpuss.dw1_tr_out[27] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT28 = 0x0000053Au, /* cpuss.dw1_tr_out[28] */ + TRIG_IN_MUX_5_TCPWM0_TR_OVERFLOW0 = 0x0000053Bu, /* tcpwm[0].tr_overflow[0] */ + TRIG_IN_MUX_5_TCPWM0_TR_COMPARE_MATCH0 = 0x0000053Cu, /* tcpwm[0].tr_compare_match[0] */ + TRIG_IN_MUX_5_TCPWM0_TR_UNDERFLOW0 = 0x0000053Du, /* tcpwm[0].tr_underflow[0] */ + TRIG_IN_MUX_5_TCPWM0_TR_OVERFLOW1 = 0x0000053Eu, /* tcpwm[0].tr_overflow[1] */ + TRIG_IN_MUX_5_TCPWM0_TR_COMPARE_MATCH1 = 0x0000053Fu, /* tcpwm[0].tr_compare_match[1] */ + TRIG_IN_MUX_5_TCPWM0_TR_UNDERFLOW1 = 0x00000540u, /* tcpwm[0].tr_underflow[1] */ + TRIG_IN_MUX_5_TCPWM0_TR_OVERFLOW2 = 0x00000541u, /* tcpwm[0].tr_overflow[2] */ + TRIG_IN_MUX_5_TCPWM0_TR_COMPARE_MATCH2 = 0x00000542u, /* tcpwm[0].tr_compare_match[2] */ + TRIG_IN_MUX_5_TCPWM0_TR_UNDERFLOW2 = 0x00000543u, /* tcpwm[0].tr_underflow[2] */ + TRIG_IN_MUX_5_TCPWM0_TR_OVERFLOW3 = 0x00000544u, /* tcpwm[0].tr_overflow[3] */ + TRIG_IN_MUX_5_TCPWM0_TR_COMPARE_MATCH3 = 0x00000545u, /* tcpwm[0].tr_compare_match[3] */ + TRIG_IN_MUX_5_TCPWM0_TR_UNDERFLOW3 = 0x00000546u, /* tcpwm[0].tr_underflow[3] */ + TRIG_IN_MUX_5_TCPWM1_TR_OVERFLOW0 = 0x00000553u, /* tcpwm[1].tr_overflow[0] */ + TRIG_IN_MUX_5_TCPWM1_TR_COMPARE_MATCH0 = 0x00000554u, /* tcpwm[1].tr_compare_match[0] */ + TRIG_IN_MUX_5_TCPWM1_TR_UNDERFLOW0 = 0x00000555u, /* tcpwm[1].tr_underflow[0] */ + TRIG_IN_MUX_5_TCPWM1_TR_OVERFLOW1 = 0x00000556u, /* tcpwm[1].tr_overflow[1] */ + TRIG_IN_MUX_5_TCPWM1_TR_COMPARE_MATCH1 = 0x00000557u, /* tcpwm[1].tr_compare_match[1] */ + TRIG_IN_MUX_5_TCPWM1_TR_UNDERFLOW1 = 0x00000558u, /* tcpwm[1].tr_underflow[1] */ + TRIG_IN_MUX_5_TCPWM1_TR_OVERFLOW2 = 0x00000559u, /* tcpwm[1].tr_overflow[2] */ + TRIG_IN_MUX_5_TCPWM1_TR_COMPARE_MATCH2 = 0x0000055Au, /* tcpwm[1].tr_compare_match[2] */ + TRIG_IN_MUX_5_TCPWM1_TR_UNDERFLOW2 = 0x0000055Bu, /* tcpwm[1].tr_underflow[2] */ + TRIG_IN_MUX_5_TCPWM1_TR_OVERFLOW3 = 0x0000055Cu, /* tcpwm[1].tr_overflow[3] */ + TRIG_IN_MUX_5_TCPWM1_TR_COMPARE_MATCH3 = 0x0000055Du, /* tcpwm[1].tr_compare_match[3] */ + TRIG_IN_MUX_5_TCPWM1_TR_UNDERFLOW3 = 0x0000055Eu, /* tcpwm[1].tr_underflow[3] */ + TRIG_IN_MUX_5_TCPWM1_TR_OVERFLOW4 = 0x0000055Fu, /* tcpwm[1].tr_overflow[4] */ + TRIG_IN_MUX_5_TCPWM1_TR_COMPARE_MATCH4 = 0x00000560u, /* tcpwm[1].tr_compare_match[4] */ + TRIG_IN_MUX_5_TCPWM1_TR_UNDERFLOW4 = 0x00000561u, /* tcpwm[1].tr_underflow[4] */ + TRIG_IN_MUX_5_TCPWM1_TR_OVERFLOW5 = 0x00000562u, /* tcpwm[1].tr_overflow[5] */ + TRIG_IN_MUX_5_TCPWM1_TR_COMPARE_MATCH5 = 0x00000563u, /* tcpwm[1].tr_compare_match[5] */ + TRIG_IN_MUX_5_TCPWM1_TR_UNDERFLOW5 = 0x00000564u, /* tcpwm[1].tr_underflow[5] */ + TRIG_IN_MUX_5_TCPWM1_TR_OVERFLOW6 = 0x00000565u, /* tcpwm[1].tr_overflow[6] */ + TRIG_IN_MUX_5_TCPWM1_TR_COMPARE_MATCH6 = 0x00000566u, /* tcpwm[1].tr_compare_match[6] */ + TRIG_IN_MUX_5_TCPWM1_TR_UNDERFLOW6 = 0x00000567u, /* tcpwm[1].tr_underflow[6] */ + TRIG_IN_MUX_5_TCPWM1_TR_OVERFLOW7 = 0x00000568u, /* tcpwm[1].tr_overflow[7] */ + TRIG_IN_MUX_5_TCPWM1_TR_COMPARE_MATCH7 = 0x00000569u, /* tcpwm[1].tr_compare_match[7] */ + TRIG_IN_MUX_5_TCPWM1_TR_UNDERFLOW7 = 0x0000056Au, /* tcpwm[1].tr_underflow[7] */ + TRIG_IN_MUX_5_MDMA_TR_OUT0 = 0x0000059Bu, /* cpuss.dmac_tr_out[0] */ + TRIG_IN_MUX_5_MDMA_TR_OUT1 = 0x0000059Cu, /* cpuss.dmac_tr_out[1] */ + TRIG_IN_MUX_5_SCB_I2C_SCL0 = 0x0000059Fu, /* scb[0].tr_i2c_scl_filtered */ + TRIG_IN_MUX_5_SCB_TX0 = 0x000005A0u, /* scb[0].tr_tx_req */ + TRIG_IN_MUX_5_SCB_RX0 = 0x000005A1u, /* scb[0].tr_rx_req */ + TRIG_IN_MUX_5_SCB_I2C_SCL1 = 0x000005A2u, /* scb[1].tr_i2c_scl_filtered */ + TRIG_IN_MUX_5_SCB_TX1 = 0x000005A3u, /* scb[1].tr_tx_req */ + TRIG_IN_MUX_5_SCB_RX1 = 0x000005A4u, /* scb[1].tr_rx_req */ + TRIG_IN_MUX_5_SCB_I2C_SCL2 = 0x000005A5u, /* scb[2].tr_i2c_scl_filtered */ + TRIG_IN_MUX_5_SCB_TX2 = 0x000005A6u, /* scb[2].tr_tx_req */ + TRIG_IN_MUX_5_SCB_RX2 = 0x000005A7u, /* scb[2].tr_rx_req */ + TRIG_IN_MUX_5_SCB_I2C_SCL3 = 0x000005A8u, /* scb[3].tr_i2c_scl_filtered */ + TRIG_IN_MUX_5_SCB_TX3 = 0x000005A9u, /* scb[3].tr_tx_req */ + TRIG_IN_MUX_5_SCB_RX3 = 0x000005AAu, /* scb[3].tr_rx_req */ + TRIG_IN_MUX_5_SCB_I2C_SCL4 = 0x000005ABu, /* scb[4].tr_i2c_scl_filtered */ + TRIG_IN_MUX_5_SCB_TX4 = 0x000005ACu, /* scb[4].tr_tx_req */ + TRIG_IN_MUX_5_SCB_RX4 = 0x000005ADu, /* scb[4].tr_rx_req */ + TRIG_IN_MUX_5_SCB_I2C_SCL5 = 0x000005AEu, /* scb[5].tr_i2c_scl_filtered */ + TRIG_IN_MUX_5_SCB_TX5 = 0x000005AFu, /* scb[5].tr_tx_req */ + TRIG_IN_MUX_5_SCB_RX5 = 0x000005B0u, /* scb[5].tr_rx_req */ + TRIG_IN_MUX_5_SCB_I2C_SCL6 = 0x000005B1u, /* scb[6].tr_i2c_scl_filtered */ + TRIG_IN_MUX_5_SCB_TX6 = 0x000005B2u, /* scb[6].tr_tx_req */ + TRIG_IN_MUX_5_SCB_RX6 = 0x000005B3u, /* scb[6].tr_rx_req */ + TRIG_IN_MUX_5_SMIF_TX = 0x000005C6u, /* smif.tr_tx_req */ + TRIG_IN_MUX_5_SMIF_RX = 0x000005C7u, /* smif.tr_rx_req */ + TRIG_IN_MUX_5_USB_DMA0 = 0x000005C8u, /* usb.dma_req[0] */ + TRIG_IN_MUX_5_USB_DMA1 = 0x000005C9u, /* usb.dma_req[1] */ + TRIG_IN_MUX_5_USB_DMA2 = 0x000005CAu, /* usb.dma_req[2] */ + TRIG_IN_MUX_5_USB_DMA3 = 0x000005CBu, /* usb.dma_req[3] */ + TRIG_IN_MUX_5_USB_DMA4 = 0x000005CCu, /* usb.dma_req[4] */ + TRIG_IN_MUX_5_USB_DMA5 = 0x000005CDu, /* usb.dma_req[5] */ + TRIG_IN_MUX_5_USB_DMA6 = 0x000005CEu, /* usb.dma_req[6] */ + TRIG_IN_MUX_5_USB_DMA7 = 0x000005CFu, /* usb.dma_req[7] */ + TRIG_IN_MUX_5_CSD_SENSE = 0x000005D5u, /* csd.dsi_sense_out */ + TRIG_IN_MUX_5_CSD_SAMPLE = 0x000005D6u, /* csd.dsi_sample_out */ + TRIG_IN_MUX_5_CSD_ADC_DONE = 0x000005D7u, /* csd.tr_adc_done */ + TRIG_IN_MUX_5_PASS_SAR_DONE = 0x000005D8u, /* pass.tr_sar_out */ + TRIG_IN_MUX_5_HSIOM_TR_OUT0 = 0x000005D9u, /* peri.tr_io_input[0] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT1 = 0x000005DAu, /* peri.tr_io_input[1] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT2 = 0x000005DBu, /* peri.tr_io_input[2] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT3 = 0x000005DCu, /* peri.tr_io_input[3] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT4 = 0x000005DDu, /* peri.tr_io_input[4] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT5 = 0x000005DEu, /* peri.tr_io_input[5] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT6 = 0x000005DFu, /* peri.tr_io_input[6] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT7 = 0x000005E0u, /* peri.tr_io_input[7] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT8 = 0x000005E1u, /* peri.tr_io_input[8] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT9 = 0x000005E2u, /* peri.tr_io_input[9] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT10 = 0x000005E3u, /* peri.tr_io_input[10] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT11 = 0x000005E4u, /* peri.tr_io_input[11] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT12 = 0x000005E5u, /* peri.tr_io_input[12] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT13 = 0x000005E6u, /* peri.tr_io_input[13] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT14 = 0x000005E7u, /* peri.tr_io_input[14] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT15 = 0x000005E8u, /* peri.tr_io_input[15] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT16 = 0x000005E9u, /* peri.tr_io_input[16] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT17 = 0x000005EAu, /* peri.tr_io_input[17] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT18 = 0x000005EBu, /* peri.tr_io_input[18] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT19 = 0x000005ECu, /* peri.tr_io_input[19] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT20 = 0x000005EDu, /* peri.tr_io_input[20] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT21 = 0x000005EEu, /* peri.tr_io_input[21] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT22 = 0x000005EFu, /* peri.tr_io_input[22] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT23 = 0x000005F0u, /* peri.tr_io_input[23] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT24 = 0x000005F1u, /* peri.tr_io_input[24] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT25 = 0x000005F2u, /* peri.tr_io_input[25] */ + TRIG_IN_MUX_5_FAULT_TR_OUT0 = 0x000005F5u, /* cpuss.tr_fault[0] */ + TRIG_IN_MUX_5_FAULT_TR_OUT1 = 0x000005F6u, /* cpuss.tr_fault[1] */ + TRIG_IN_MUX_5_CTI_TR_OUT0 = 0x000005F7u, /* cpuss.cti_tr_out[0] */ + TRIG_IN_MUX_5_CTI_TR_OUT1 = 0x000005F8u, /* cpuss.cti_tr_out[1] */ + TRIG_IN_MUX_5_LPCOMP_DSI_COMP0 = 0x000005F9u, /* lpcomp.dsi_comp0 */ + TRIG_IN_MUX_5_LPCOMP_DSI_COMP1 = 0x000005FAu, /* lpcomp.dsi_comp1 */ + TRIG_IN_MUX_5_CANFD_TT_TR_OUT0 = 0x000005FBu, /* canfd[0].tr_tmp_rtp_out[0] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT29 = 0x000005FCu, /* cpuss.dw1_tr_out[29] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT30 = 0x000005FDu, /* cpuss.dw1_tr_out[30] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT31 = 0x000005FEu /* cpuss.dw1_tr_out[31] */ +} en_trig_input_cpuss_cti_t; + +/* Trigger Input Group 6 - MDMA trigger multiplexer */ +typedef enum +{ + TRIG_IN_MUX_6_TCPWM1_TR_OVERFLOW0 = 0x00000601u, /* tcpwm[1].tr_overflow[0] */ + TRIG_IN_MUX_6_TCPWM1_TR_COMPARE_MATCH0 = 0x00000602u, /* tcpwm[1].tr_compare_match[0] */ + TRIG_IN_MUX_6_TCPWM1_TR_UNDERFLOW0 = 0x00000603u, /* tcpwm[1].tr_underflow[0] */ + TRIG_IN_MUX_6_TCPWM1_TR_OVERFLOW1 = 0x00000604u, /* tcpwm[1].tr_overflow[1] */ + TRIG_IN_MUX_6_TCPWM1_TR_COMPARE_MATCH1 = 0x00000605u, /* tcpwm[1].tr_compare_match[1] */ + TRIG_IN_MUX_6_TCPWM1_TR_UNDERFLOW1 = 0x00000606u, /* tcpwm[1].tr_underflow[1] */ + TRIG_IN_MUX_6_TCPWM1_TR_OVERFLOW2 = 0x00000607u, /* tcpwm[1].tr_overflow[2] */ + TRIG_IN_MUX_6_TCPWM1_TR_COMPARE_MATCH2 = 0x00000608u, /* tcpwm[1].tr_compare_match[2] */ + TRIG_IN_MUX_6_TCPWM1_TR_UNDERFLOW2 = 0x00000609u, /* tcpwm[1].tr_underflow[2] */ + TRIG_IN_MUX_6_TCPWM1_TR_OVERFLOW3 = 0x0000060Au, /* tcpwm[1].tr_overflow[3] */ + TRIG_IN_MUX_6_TCPWM1_TR_COMPARE_MATCH3 = 0x0000060Bu, /* tcpwm[1].tr_compare_match[3] */ + TRIG_IN_MUX_6_TCPWM1_TR_UNDERFLOW3 = 0x0000060Cu, /* tcpwm[1].tr_underflow[3] */ + TRIG_IN_MUX_6_TCPWM1_TR_OVERFLOW4 = 0x0000060Du, /* tcpwm[1].tr_overflow[4] */ + TRIG_IN_MUX_6_TCPWM1_TR_COMPARE_MATCH4 = 0x0000060Eu, /* tcpwm[1].tr_compare_match[4] */ + TRIG_IN_MUX_6_TCPWM1_TR_UNDERFLOW4 = 0x0000060Fu, /* tcpwm[1].tr_underflow[4] */ + TRIG_IN_MUX_6_TCPWM1_TR_OVERFLOW5 = 0x00000610u, /* tcpwm[1].tr_overflow[5] */ + TRIG_IN_MUX_6_TCPWM1_TR_COMPARE_MATCH5 = 0x00000611u, /* tcpwm[1].tr_compare_match[5] */ + TRIG_IN_MUX_6_TCPWM1_TR_UNDERFLOW5 = 0x00000612u, /* tcpwm[1].tr_underflow[5] */ + TRIG_IN_MUX_6_TCPWM1_TR_OVERFLOW6 = 0x00000613u, /* tcpwm[1].tr_overflow[6] */ + TRIG_IN_MUX_6_TCPWM1_TR_COMPARE_MATCH6 = 0x00000614u, /* tcpwm[1].tr_compare_match[6] */ + TRIG_IN_MUX_6_TCPWM1_TR_UNDERFLOW6 = 0x00000615u, /* tcpwm[1].tr_underflow[6] */ + TRIG_IN_MUX_6_TCPWM1_TR_OVERFLOW7 = 0x00000616u, /* tcpwm[1].tr_overflow[7] */ + TRIG_IN_MUX_6_TCPWM1_TR_COMPARE_MATCH7 = 0x00000617u, /* tcpwm[1].tr_compare_match[7] */ + TRIG_IN_MUX_6_TCPWM1_TR_UNDERFLOW7 = 0x00000618u, /* tcpwm[1].tr_underflow[7] */ + TRIG_IN_MUX_6_SMIF_TX = 0x00000619u, /* smif.tr_tx_req */ + TRIG_IN_MUX_6_SMIF_RX = 0x0000061Au /* smif.tr_rx_req */ +} en_trig_input_mdma_t; + +/* Trigger Input Group 7 - PERI Freeze trigger multiplexer */ +typedef enum +{ + TRIG_IN_MUX_7_CTI_TR_OUT0 = 0x00000701u, /* cpuss.cti_tr_out[0] */ + TRIG_IN_MUX_7_CTI_TR_OUT1 = 0x00000702u /* cpuss.cti_tr_out[1] */ +} en_trig_input_peri_freeze_t; + +/* Trigger Input Group 8 - Capsense trigger multiplexer */ +typedef enum +{ + TRIG_IN_MUX_8_TCPWM0_TR_OVERFLOW0 = 0x00000801u, /* tcpwm[0].tr_overflow[0] */ + TRIG_IN_MUX_8_TCPWM0_TR_COMPARE_MATCH0 = 0x00000802u, /* tcpwm[0].tr_compare_match[0] */ + TRIG_IN_MUX_8_TCPWM0_TR_UNDERFLOW0 = 0x00000803u, /* tcpwm[0].tr_underflow[0] */ + TRIG_IN_MUX_8_TCPWM0_TR_OVERFLOW1 = 0x00000804u, /* tcpwm[0].tr_overflow[1] */ + TRIG_IN_MUX_8_TCPWM0_TR_COMPARE_MATCH1 = 0x00000805u, /* tcpwm[0].tr_compare_match[1] */ + TRIG_IN_MUX_8_TCPWM0_TR_UNDERFLOW1 = 0x00000806u, /* tcpwm[0].tr_underflow[1] */ + TRIG_IN_MUX_8_TCPWM0_TR_OVERFLOW2 = 0x00000807u, /* tcpwm[0].tr_overflow[2] */ + TRIG_IN_MUX_8_TCPWM0_TR_COMPARE_MATCH2 = 0x00000808u, /* tcpwm[0].tr_compare_match[2] */ + TRIG_IN_MUX_8_TCPWM0_TR_UNDERFLOW2 = 0x00000809u, /* tcpwm[0].tr_underflow[2] */ + TRIG_IN_MUX_8_TCPWM0_TR_OVERFLOW3 = 0x0000080Au, /* tcpwm[0].tr_overflow[3] */ + TRIG_IN_MUX_8_TCPWM0_TR_COMPARE_MATCH3 = 0x0000080Bu, /* tcpwm[0].tr_compare_match[3] */ + TRIG_IN_MUX_8_TCPWM0_TR_UNDERFLOW3 = 0x0000080Cu, /* tcpwm[0].tr_underflow[3] */ + TRIG_IN_MUX_8_TCPWM1_TR_OVERFLOW0 = 0x00000819u, /* tcpwm[1].tr_overflow[0] */ + TRIG_IN_MUX_8_TCPWM1_TR_COMPARE_MATCH0 = 0x0000081Au, /* tcpwm[1].tr_compare_match[0] */ + TRIG_IN_MUX_8_TCPWM1_TR_UNDERFLOW0 = 0x0000081Bu, /* tcpwm[1].tr_underflow[0] */ + TRIG_IN_MUX_8_TCPWM1_TR_OVERFLOW1 = 0x0000081Cu, /* tcpwm[1].tr_overflow[1] */ + TRIG_IN_MUX_8_TCPWM1_TR_COMPARE_MATCH1 = 0x0000081Du, /* tcpwm[1].tr_compare_match[1] */ + TRIG_IN_MUX_8_TCPWM1_TR_UNDERFLOW1 = 0x0000081Eu, /* tcpwm[1].tr_underflow[1] */ + TRIG_IN_MUX_8_TCPWM1_TR_OVERFLOW2 = 0x0000081Fu, /* tcpwm[1].tr_overflow[2] */ + TRIG_IN_MUX_8_TCPWM1_TR_COMPARE_MATCH2 = 0x00000820u, /* tcpwm[1].tr_compare_match[2] */ + TRIG_IN_MUX_8_TCPWM1_TR_UNDERFLOW2 = 0x00000821u, /* tcpwm[1].tr_underflow[2] */ + TRIG_IN_MUX_8_TCPWM1_TR_OVERFLOW3 = 0x00000822u, /* tcpwm[1].tr_overflow[3] */ + TRIG_IN_MUX_8_TCPWM1_TR_COMPARE_MATCH3 = 0x00000823u, /* tcpwm[1].tr_compare_match[3] */ + TRIG_IN_MUX_8_TCPWM1_TR_UNDERFLOW3 = 0x00000824u, /* tcpwm[1].tr_underflow[3] */ + TRIG_IN_MUX_8_TCPWM1_TR_OVERFLOW4 = 0x00000825u, /* tcpwm[1].tr_overflow[4] */ + TRIG_IN_MUX_8_TCPWM1_TR_COMPARE_MATCH4 = 0x00000826u, /* tcpwm[1].tr_compare_match[4] */ + TRIG_IN_MUX_8_TCPWM1_TR_UNDERFLOW4 = 0x00000827u, /* tcpwm[1].tr_underflow[4] */ + TRIG_IN_MUX_8_TCPWM1_TR_OVERFLOW5 = 0x00000828u, /* tcpwm[1].tr_overflow[5] */ + TRIG_IN_MUX_8_TCPWM1_TR_COMPARE_MATCH5 = 0x00000829u, /* tcpwm[1].tr_compare_match[5] */ + TRIG_IN_MUX_8_TCPWM1_TR_UNDERFLOW5 = 0x0000082Au, /* tcpwm[1].tr_underflow[5] */ + TRIG_IN_MUX_8_TCPWM1_TR_OVERFLOW6 = 0x0000082Bu, /* tcpwm[1].tr_overflow[6] */ + TRIG_IN_MUX_8_TCPWM1_TR_COMPARE_MATCH6 = 0x0000082Cu, /* tcpwm[1].tr_compare_match[6] */ + TRIG_IN_MUX_8_TCPWM1_TR_UNDERFLOW6 = 0x0000082Du, /* tcpwm[1].tr_underflow[6] */ + TRIG_IN_MUX_8_TCPWM1_TR_OVERFLOW7 = 0x0000082Eu, /* tcpwm[1].tr_overflow[7] */ + TRIG_IN_MUX_8_TCPWM1_TR_COMPARE_MATCH7 = 0x0000082Fu, /* tcpwm[1].tr_compare_match[7] */ + TRIG_IN_MUX_8_TCPWM1_TR_UNDERFLOW7 = 0x00000830u, /* tcpwm[1].tr_underflow[7] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT0 = 0x0000086Du, /* peri.tr_io_input[0] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT1 = 0x0000086Eu, /* peri.tr_io_input[1] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT2 = 0x0000086Fu, /* peri.tr_io_input[2] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT3 = 0x00000870u, /* peri.tr_io_input[3] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT4 = 0x00000871u, /* peri.tr_io_input[4] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT5 = 0x00000872u, /* peri.tr_io_input[5] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT6 = 0x00000873u, /* peri.tr_io_input[6] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT7 = 0x00000874u, /* peri.tr_io_input[7] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT8 = 0x00000875u, /* peri.tr_io_input[8] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT9 = 0x00000876u, /* peri.tr_io_input[9] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT10 = 0x00000877u, /* peri.tr_io_input[10] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT11 = 0x00000878u, /* peri.tr_io_input[11] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT12 = 0x00000879u, /* peri.tr_io_input[12] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT13 = 0x0000087Au, /* peri.tr_io_input[13] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT14 = 0x0000087Bu, /* peri.tr_io_input[14] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT15 = 0x0000087Cu, /* peri.tr_io_input[15] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT16 = 0x0000087Du, /* peri.tr_io_input[16] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT17 = 0x0000087Eu, /* peri.tr_io_input[17] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT18 = 0x0000087Fu, /* peri.tr_io_input[18] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT19 = 0x00000880u, /* peri.tr_io_input[19] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT20 = 0x00000881u, /* peri.tr_io_input[20] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT21 = 0x00000882u, /* peri.tr_io_input[21] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT22 = 0x00000883u, /* peri.tr_io_input[22] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT23 = 0x00000884u, /* peri.tr_io_input[23] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT24 = 0x00000885u, /* peri.tr_io_input[24] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT25 = 0x00000886u, /* peri.tr_io_input[25] */ + TRIG_IN_MUX_8_LPCOMP_DSI_COMP0 = 0x00000889u, /* lpcomp.dsi_comp0 */ + TRIG_IN_MUX_8_LPCOMP_DSI_COMP1 = 0x0000088Au /* lpcomp.dsi_comp1 */ +} en_trig_input_csd_t; + +/* Trigger Input Group 9 - ADC trigger multiplexer */ +typedef enum +{ + TRIG_IN_MUX_9_TCPWM0_TR_OVERFLOW0 = 0x00000901u, /* tcpwm[0].tr_overflow[0] */ + TRIG_IN_MUX_9_TCPWM0_TR_COMPARE_MATCH0 = 0x00000902u, /* tcpwm[0].tr_compare_match[0] */ + TRIG_IN_MUX_9_TCPWM0_TR_UNDERFLOW0 = 0x00000903u, /* tcpwm[0].tr_underflow[0] */ + TRIG_IN_MUX_9_TCPWM0_TR_OVERFLOW1 = 0x00000904u, /* tcpwm[0].tr_overflow[1] */ + TRIG_IN_MUX_9_TCPWM0_TR_COMPARE_MATCH1 = 0x00000905u, /* tcpwm[0].tr_compare_match[1] */ + TRIG_IN_MUX_9_TCPWM0_TR_UNDERFLOW1 = 0x00000906u, /* tcpwm[0].tr_underflow[1] */ + TRIG_IN_MUX_9_TCPWM0_TR_OVERFLOW2 = 0x00000907u, /* tcpwm[0].tr_overflow[2] */ + TRIG_IN_MUX_9_TCPWM0_TR_COMPARE_MATCH2 = 0x00000908u, /* tcpwm[0].tr_compare_match[2] */ + TRIG_IN_MUX_9_TCPWM0_TR_UNDERFLOW2 = 0x00000909u, /* tcpwm[0].tr_underflow[2] */ + TRIG_IN_MUX_9_TCPWM0_TR_OVERFLOW3 = 0x0000090Au, /* tcpwm[0].tr_overflow[3] */ + TRIG_IN_MUX_9_TCPWM0_TR_COMPARE_MATCH3 = 0x0000090Bu, /* tcpwm[0].tr_compare_match[3] */ + TRIG_IN_MUX_9_TCPWM0_TR_UNDERFLOW3 = 0x0000090Cu, /* tcpwm[0].tr_underflow[3] */ + TRIG_IN_MUX_9_TCPWM1_TR_OVERFLOW0 = 0x00000919u, /* tcpwm[1].tr_overflow[0] */ + TRIG_IN_MUX_9_TCPWM1_TR_COMPARE_MATCH0 = 0x0000091Au, /* tcpwm[1].tr_compare_match[0] */ + TRIG_IN_MUX_9_TCPWM1_TR_UNDERFLOW0 = 0x0000091Bu, /* tcpwm[1].tr_underflow[0] */ + TRIG_IN_MUX_9_TCPWM1_TR_OVERFLOW1 = 0x0000091Cu, /* tcpwm[1].tr_overflow[1] */ + TRIG_IN_MUX_9_TCPWM1_TR_COMPARE_MATCH1 = 0x0000091Du, /* tcpwm[1].tr_compare_match[1] */ + TRIG_IN_MUX_9_TCPWM1_TR_UNDERFLOW1 = 0x0000091Eu, /* tcpwm[1].tr_underflow[1] */ + TRIG_IN_MUX_9_TCPWM1_TR_OVERFLOW2 = 0x0000091Fu, /* tcpwm[1].tr_overflow[2] */ + TRIG_IN_MUX_9_TCPWM1_TR_COMPARE_MATCH2 = 0x00000920u, /* tcpwm[1].tr_compare_match[2] */ + TRIG_IN_MUX_9_TCPWM1_TR_UNDERFLOW2 = 0x00000921u, /* tcpwm[1].tr_underflow[2] */ + TRIG_IN_MUX_9_TCPWM1_TR_OVERFLOW3 = 0x00000922u, /* tcpwm[1].tr_overflow[3] */ + TRIG_IN_MUX_9_TCPWM1_TR_COMPARE_MATCH3 = 0x00000923u, /* tcpwm[1].tr_compare_match[3] */ + TRIG_IN_MUX_9_TCPWM1_TR_UNDERFLOW3 = 0x00000924u, /* tcpwm[1].tr_underflow[3] */ + TRIG_IN_MUX_9_TCPWM1_TR_OVERFLOW4 = 0x00000925u, /* tcpwm[1].tr_overflow[4] */ + TRIG_IN_MUX_9_TCPWM1_TR_COMPARE_MATCH4 = 0x00000926u, /* tcpwm[1].tr_compare_match[4] */ + TRIG_IN_MUX_9_TCPWM1_TR_UNDERFLOW4 = 0x00000927u, /* tcpwm[1].tr_underflow[4] */ + TRIG_IN_MUX_9_TCPWM1_TR_OVERFLOW5 = 0x00000928u, /* tcpwm[1].tr_overflow[5] */ + TRIG_IN_MUX_9_TCPWM1_TR_COMPARE_MATCH5 = 0x00000929u, /* tcpwm[1].tr_compare_match[5] */ + TRIG_IN_MUX_9_TCPWM1_TR_UNDERFLOW5 = 0x0000092Au, /* tcpwm[1].tr_underflow[5] */ + TRIG_IN_MUX_9_TCPWM1_TR_OVERFLOW6 = 0x0000092Bu, /* tcpwm[1].tr_overflow[6] */ + TRIG_IN_MUX_9_TCPWM1_TR_COMPARE_MATCH6 = 0x0000092Cu, /* tcpwm[1].tr_compare_match[6] */ + TRIG_IN_MUX_9_TCPWM1_TR_UNDERFLOW6 = 0x0000092Du, /* tcpwm[1].tr_underflow[6] */ + TRIG_IN_MUX_9_TCPWM1_TR_OVERFLOW7 = 0x0000092Eu, /* tcpwm[1].tr_overflow[7] */ + TRIG_IN_MUX_9_TCPWM1_TR_COMPARE_MATCH7 = 0x0000092Fu, /* tcpwm[1].tr_compare_match[7] */ + TRIG_IN_MUX_9_TCPWM1_TR_UNDERFLOW7 = 0x00000930u, /* tcpwm[1].tr_underflow[7] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT0 = 0x00000961u, /* peri.tr_io_input[0] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT1 = 0x00000962u, /* peri.tr_io_input[1] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT2 = 0x00000963u, /* peri.tr_io_input[2] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT3 = 0x00000964u, /* peri.tr_io_input[3] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT4 = 0x00000965u, /* peri.tr_io_input[4] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT5 = 0x00000966u, /* peri.tr_io_input[5] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT6 = 0x00000967u, /* peri.tr_io_input[6] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT7 = 0x00000968u, /* peri.tr_io_input[7] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT8 = 0x00000969u, /* peri.tr_io_input[8] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT9 = 0x0000096Au, /* peri.tr_io_input[9] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT10 = 0x0000096Bu, /* peri.tr_io_input[10] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT11 = 0x0000096Cu, /* peri.tr_io_input[11] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT12 = 0x0000096Du, /* peri.tr_io_input[12] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT13 = 0x0000096Eu, /* peri.tr_io_input[13] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT14 = 0x0000096Fu, /* peri.tr_io_input[14] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT15 = 0x00000970u, /* peri.tr_io_input[15] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT16 = 0x00000971u, /* peri.tr_io_input[16] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT17 = 0x00000972u, /* peri.tr_io_input[17] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT18 = 0x00000973u, /* peri.tr_io_input[18] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT19 = 0x00000974u, /* peri.tr_io_input[19] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT20 = 0x00000975u, /* peri.tr_io_input[20] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT21 = 0x00000976u, /* peri.tr_io_input[21] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT22 = 0x00000977u, /* peri.tr_io_input[22] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT23 = 0x00000978u, /* peri.tr_io_input[23] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT24 = 0x00000979u, /* peri.tr_io_input[24] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT25 = 0x0000097Au, /* peri.tr_io_input[25] */ + TRIG_IN_MUX_9_LPCOMP_DSI_COMP0 = 0x0000097Du, /* lpcomp.dsi_comp0 */ + TRIG_IN_MUX_9_LPCOMP_DSI_COMP1 = 0x0000097Eu /* lpcomp.dsi_comp1 */ +} en_trig_input_sar_adc_start_t; + +/* Trigger Input Group 10 - CAN TT Synchronization triggers */ +typedef enum +{ + TRIG_IN_MUX_10_CAN_TT_TR_OUT0 = 0x00000A01u /* canfd[0].tr_tmp_rtp_out[0] */ +} en_trig_input_cantt_t; + +/* Trigger Group Outputs */ +/* Trigger Output Group 0 - PDMA0 Request Assignments */ +typedef enum +{ + TRIG_OUT_MUX_0_PDMA0_TR_IN0 = 0x40000000u, /* cpuss.dw0_tr_in[0] */ + TRIG_OUT_MUX_0_PDMA0_TR_IN1 = 0x40000001u, /* cpuss.dw0_tr_in[1] */ + TRIG_OUT_MUX_0_PDMA0_TR_IN2 = 0x40000002u, /* cpuss.dw0_tr_in[2] */ + TRIG_OUT_MUX_0_PDMA0_TR_IN3 = 0x40000003u, /* cpuss.dw0_tr_in[3] */ + TRIG_OUT_MUX_0_PDMA0_TR_IN4 = 0x40000004u, /* cpuss.dw0_tr_in[4] */ + TRIG_OUT_MUX_0_PDMA0_TR_IN5 = 0x40000005u, /* cpuss.dw0_tr_in[5] */ + TRIG_OUT_MUX_0_PDMA0_TR_IN6 = 0x40000006u, /* cpuss.dw0_tr_in[6] */ + TRIG_OUT_MUX_0_PDMA0_TR_IN7 = 0x40000007u /* cpuss.dw0_tr_in[7] */ +} en_trig_output_pdma0_tr_t; + +/* Trigger Output Group 1 - PDMA1 Request Assignments */ +typedef enum +{ + TRIG_OUT_MUX_1_PDMA1_TR_IN0 = 0x40000100u, /* cpuss.dw1_tr_in[0] */ + TRIG_OUT_MUX_1_PDMA1_TR_IN1 = 0x40000101u, /* cpuss.dw1_tr_in[1] */ + TRIG_OUT_MUX_1_PDMA1_TR_IN2 = 0x40000102u, /* cpuss.dw1_tr_in[2] */ + TRIG_OUT_MUX_1_PDMA1_TR_IN3 = 0x40000103u, /* cpuss.dw1_tr_in[3] */ + TRIG_OUT_MUX_1_PDMA1_TR_IN4 = 0x40000104u, /* cpuss.dw1_tr_in[4] */ + TRIG_OUT_MUX_1_PDMA1_TR_IN5 = 0x40000105u, /* cpuss.dw1_tr_in[5] */ + TRIG_OUT_MUX_1_PDMA1_TR_IN6 = 0x40000106u, /* cpuss.dw1_tr_in[6] */ + TRIG_OUT_MUX_1_PDMA1_TR_IN7 = 0x40000107u /* cpuss.dw1_tr_in[7] */ +} en_trig_output_pdma1_tr_t; + +/* Trigger Output Group 2 - TCPWM0 trigger multiplexer */ +typedef enum +{ + TRIG_OUT_MUX_2_TCPWM0_TR_IN0 = 0x40000200u, /* tcpwm[0].tr_in[0] */ + TRIG_OUT_MUX_2_TCPWM0_TR_IN1 = 0x40000201u, /* tcpwm[0].tr_in[1] */ + TRIG_OUT_MUX_2_TCPWM0_TR_IN2 = 0x40000202u, /* tcpwm[0].tr_in[2] */ + TRIG_OUT_MUX_2_TCPWM0_TR_IN3 = 0x40000203u, /* tcpwm[0].tr_in[3] */ + TRIG_OUT_MUX_2_TCPWM0_TR_IN4 = 0x40000204u, /* tcpwm[0].tr_in[4] */ + TRIG_OUT_MUX_2_TCPWM0_TR_IN5 = 0x40000205u, /* tcpwm[0].tr_in[5] */ + TRIG_OUT_MUX_2_TCPWM0_TR_IN6 = 0x40000206u, /* tcpwm[0].tr_in[6] */ + TRIG_OUT_MUX_2_TCPWM0_TR_IN7 = 0x40000207u, /* tcpwm[0].tr_in[7] */ + TRIG_OUT_MUX_2_TCPWM0_TR_IN8 = 0x40000208u, /* tcpwm[0].tr_in[8] */ + TRIG_OUT_MUX_2_TCPWM0_TR_IN9 = 0x40000209u, /* tcpwm[0].tr_in[9] */ + TRIG_OUT_MUX_2_TCPWM0_TR_IN10 = 0x4000020Au, /* tcpwm[0].tr_in[10] */ + TRIG_OUT_MUX_2_TCPWM0_TR_IN11 = 0x4000020Bu, /* tcpwm[0].tr_in[11] */ + TRIG_OUT_MUX_2_TCPWM0_TR_IN12 = 0x4000020Cu, /* tcpwm[0].tr_in[12] */ + TRIG_OUT_MUX_2_TCPWM0_TR_IN13 = 0x4000020Du /* tcpwm[0].tr_in[13] */ +} en_trig_output_tcpwm0_t; + +/* Trigger Output Group 3 - TCPWM1 trigger multiplexer */ +typedef enum +{ + TRIG_OUT_MUX_3_TCPWM1_TR_IN0 = 0x40000300u, /* tcpwm[1].tr_in[0] */ + TRIG_OUT_MUX_3_TCPWM1_TR_IN1 = 0x40000301u, /* tcpwm[1].tr_in[1] */ + TRIG_OUT_MUX_3_TCPWM1_TR_IN2 = 0x40000302u, /* tcpwm[1].tr_in[2] */ + TRIG_OUT_MUX_3_TCPWM1_TR_IN3 = 0x40000303u, /* tcpwm[1].tr_in[3] */ + TRIG_OUT_MUX_3_TCPWM1_TR_IN4 = 0x40000304u, /* tcpwm[1].tr_in[4] */ + TRIG_OUT_MUX_3_TCPWM1_TR_IN5 = 0x40000305u, /* tcpwm[1].tr_in[5] */ + TRIG_OUT_MUX_3_TCPWM1_TR_IN6 = 0x40000306u, /* tcpwm[1].tr_in[6] */ + TRIG_OUT_MUX_3_TCPWM1_TR_IN7 = 0x40000307u, /* tcpwm[1].tr_in[7] */ + TRIG_OUT_MUX_3_TCPWM1_TR_IN8 = 0x40000308u, /* tcpwm[1].tr_in[8] */ + TRIG_OUT_MUX_3_TCPWM1_TR_IN9 = 0x40000309u, /* tcpwm[1].tr_in[9] */ + TRIG_OUT_MUX_3_TCPWM1_TR_IN10 = 0x4000030Au, /* tcpwm[1].tr_in[10] */ + TRIG_OUT_MUX_3_TCPWM1_TR_IN11 = 0x4000030Bu, /* tcpwm[1].tr_in[11] */ + TRIG_OUT_MUX_3_TCPWM1_TR_IN12 = 0x4000030Cu, /* tcpwm[1].tr_in[12] */ + TRIG_OUT_MUX_3_TCPWM1_TR_IN13 = 0x4000030Du /* tcpwm[1].tr_in[13] */ +} en_trig_output_tcpwm1_t; + +/* Trigger Output Group 4 - HSIOM trigger multiplexer */ +typedef enum +{ + TRIG_OUT_MUX_4_HSIOM_TR_IO_OUTPUT0 = 0x40000400u, /* peri.tr_io_output[0] */ + TRIG_OUT_MUX_4_HSIOM_TR_IO_OUTPUT1 = 0x40000401u /* peri.tr_io_output[1] */ +} en_trig_output_hsiom_t; + +/* Trigger Output Group 5 - CPUSS Debug trigger multiplexer */ +typedef enum +{ + TRIG_OUT_MUX_5_CPUSS_CTI_TR_IN0 = 0x40000500u, /* cpuss.cti_tr_in[0] */ + TRIG_OUT_MUX_5_CPUSS_CTI_TR_IN1 = 0x40000501u /* cpuss.cti_tr_in[1] */ +} en_trig_output_cpuss_cti_t; + +/* Trigger Output Group 6 - MDMA trigger multiplexer */ +typedef enum +{ + TRIG_OUT_MUX_6_MDMA_TR_IN0 = 0x40000600u, /* cpuss.dmac_tr_in[0] */ + TRIG_OUT_MUX_6_MDMA_TR_IN1 = 0x40000601u /* cpuss.dmac_tr_in[1] */ +} en_trig_output_mdma_t; + +/* Trigger Output Group 7 - PERI Freeze trigger multiplexer */ +typedef enum +{ + TRIG_OUT_MUX_7_DEBUG_FREEZE_TR_IN = 0x40000700u /* peri.tr_dbg_freeze */ +} en_trig_output_peri_freeze_t; + +/* Trigger Output Group 8 - Capsense trigger multiplexer */ +typedef enum +{ + TRIG_OUT_MUX_8_CSD_DSI_START = 0x40000800u /* csd.dsi_start */ +} en_trig_output_csd_t; + +/* Trigger Output Group 9 - ADC trigger multiplexer */ +typedef enum +{ + TRIG_OUT_MUX_9_PASS_TR_SAR_IN = 0x40000900u /* pass.tr_sar_in */ +} en_trig_output_sar_adc_start_t; + +/* Trigger Output Group 10 - CAN TT Synchronization triggers */ +typedef enum +{ + TRIG_OUT_MUX_10_CAN_TT_TR_IN0 = 0x40000A00u /* canfd[0].tr_evt_swt_in[0] */ +} en_trig_output_cantt_t; + +/* Trigger Output Group 0 - SCB PDMA0 Triggers (OneToOne) */ +typedef enum +{ + TRIG_OUT_1TO1_0_SCB0_TX_TO_PDMA0_TR_IN16 = 0x40001000u, /* From scb[0].tr_tx_req to cpuss.dw0_tr_in[16] */ + TRIG_OUT_1TO1_0_SCB0_RX_TO_PDMA0_TR_IN17 = 0x40001001u, /* From scb[0].tr_rx_req to cpuss.dw0_tr_in[17] */ + TRIG_OUT_1TO1_0_SCB1_TX_TO_PDMA0_TR_IN18 = 0x40001002u, /* From scb[1].tr_tx_req to cpuss.dw0_tr_in[18] */ + TRIG_OUT_1TO1_0_SCB1_RX_TO_PDMA0_TR_IN19 = 0x40001003u, /* From scb[1].tr_rx_req to cpuss.dw0_tr_in[19] */ + TRIG_OUT_1TO1_0_SCB2_TX_TO_PDMA0_TR_IN20 = 0x40001004u, /* From scb[2].tr_tx_req to cpuss.dw0_tr_in[20] */ + TRIG_OUT_1TO1_0_SCB2_RX_TO_PDMA0_TR_IN21 = 0x40001005u, /* From scb[2].tr_rx_req to cpuss.dw0_tr_in[21] */ + TRIG_OUT_1TO1_0_SCB3_TX_TO_PDMA0_TR_IN22 = 0x40001006u, /* From scb[3].tr_tx_req to cpuss.dw0_tr_in[22] */ + TRIG_OUT_1TO1_0_SCB3_RX_TO_PDMA0_TR_IN23 = 0x40001007u, /* From scb[3].tr_rx_req to cpuss.dw0_tr_in[23] */ + TRIG_OUT_1TO1_0_SCB4_TX_TO_PDMA0_TR_IN24 = 0x40001008u, /* From scb[4].tr_tx_req to cpuss.dw0_tr_in[24] */ + TRIG_OUT_1TO1_0_SCB4_RX_TO_PDMA0_TR_IN25 = 0x40001009u, /* From scb[4].tr_rx_req to cpuss.dw0_tr_in[25] */ + TRIG_OUT_1TO1_0_SCB5_TX_TO_PDMA0_TR_IN26 = 0x4000100Au, /* From scb[5].tr_tx_req to cpuss.dw0_tr_in[26] */ + TRIG_OUT_1TO1_0_SCB5_RX_TO_PDMA0_TR_IN27 = 0x4000100Bu /* From scb[5].tr_rx_req to cpuss.dw0_tr_in[27] */ +} en_trig_output_1to1_scb_pdma0_tr_t; + +/* Trigger Output Group 1 - SCB PDMA1 Triggers (OneToOne) */ +typedef enum +{ + TRIG_OUT_1TO1_1_SCB6_TX_TO_PDMA1_TR_IN8 = 0x40001100u, /* From scb[6].tr_tx_req to cpuss.dw1_tr_in[8] */ + TRIG_OUT_1TO1_1_SCB6_RX_TO_PDMA1_TR_IN9 = 0x40001101u, /* From scb[6].tr_rx_req to cpuss.dw1_tr_in[9] */ + TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN10 = 0x40001102u, /* From cpuss.zero to cpuss.dw1_tr_in[10] */ + TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN11 = 0x40001103u, /* From cpuss.zero to cpuss.dw1_tr_in[11] */ + TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN12 = 0x40001104u, /* From cpuss.zero to cpuss.dw1_tr_in[12] */ + TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN13 = 0x40001105u, /* From cpuss.zero to cpuss.dw1_tr_in[13] */ + TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN14 = 0x40001106u, /* From cpuss.zero to cpuss.dw1_tr_in[14] */ + TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN15 = 0x40001107u, /* From cpuss.zero to cpuss.dw1_tr_in[15] */ + TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN16 = 0x40001108u, /* From cpuss.zero to cpuss.dw1_tr_in[16] */ + TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN17 = 0x40001109u, /* From cpuss.zero to cpuss.dw1_tr_in[17] */ + TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN18 = 0x4000110Au, /* From cpuss.zero to cpuss.dw1_tr_in[18] */ + TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN19 = 0x4000110Bu, /* From cpuss.zero to cpuss.dw1_tr_in[19] */ + TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN20 = 0x4000110Cu, /* From cpuss.zero to cpuss.dw1_tr_in[20] */ + TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN21 = 0x4000110Du /* From cpuss.zero to cpuss.dw1_tr_in[21] */ +} en_trig_output_1to1_scb_pdma1_tr_t; + +/* Trigger Output Group 2 - PASS to PDMA0 direct connect (OneToOne) */ +typedef enum +{ + TRIG_OUT_1TO1_2_PASS_SAR_DONE_TO_PDMA0_TR_IN28 = 0x40001200u /* From pass.tr_sar_out to cpuss.dw0_tr_in[28] */ +} en_trig_output_1to1_sar_to_pdma1_t; + +/* Trigger Output Group 3 - (OneToOne) */ +typedef enum +{ + TRIG_OUT_1TO1_3_SMIF_TX_TO_PDMA1_TR_IN22 = 0x40001300u, /* From smif.tr_tx_req to cpuss.dw1_tr_in[22] */ + TRIG_OUT_1TO1_3_SMIF_RX_TO_PDMA1_TR_IN23 = 0x40001301u, /* From smif.tr_rx_req to cpuss.dw1_tr_in[23] */ + TRIG3_OUT_1TO1_CPUSS_DW1_TR_IN24 = 0x40001302u, /* From cpuss.zero to cpuss.dw1_tr_in[24] */ + TRIG3_OUT_1TO1_CPUSS_DW1_TR_IN25 = 0x40001303u, /* From cpuss.zero to cpuss.dw1_tr_in[25] */ + TRIG3_OUT_1TO1_CPUSS_DW1_TR_IN26 = 0x40001304u, /* From cpuss.zero to cpuss.dw1_tr_in[26] */ + TRIG3_OUT_1TO1_CPUSS_DW1_TR_IN27 = 0x40001305u, /* From cpuss.zero to cpuss.dw1_tr_in[27] */ + TRIG3_OUT_1TO1_CPUSS_DW1_TR_IN28 = 0x40001306u /* From cpuss.zero to cpuss.dw1_tr_in[28] */ +} en_trig_output_1to1_smif_to_pdma1_t; + +/* Trigger Output Group 4 - CAN DW triggers (OneToOne) */ +typedef enum +{ + TRIG_OUT_1TO1_4_CAN_DBG_TO_PDMA1_TR_IN29 = 0x40001400u, /* From canfd[0].tr_dbg_dma_req[0] to cpuss.dw1_tr_in[29] */ + TRIG_OUT_1TO1_4_CAN_FIFO0_TO_PDMA1_TR_IN30 = 0x40001401u, /* From canfd[0].tr_fifo0[0] to cpuss.dw1_tr_in[30] */ + TRIG_OUT_1TO1_4_CAN_FIFO1_TO_PDMA1_TR_IN31 = 0x40001402u /* From canfd[0].tr_fifo1[0] to cpuss.dw1_tr_in[31] */ +} en_trig_output_1to1_can_dw_tr_t; + +/* Trigger Output Group 7 - Acknowledge dma request triggers from DW0 to CAN (OneToOne) */ +typedef enum +{ + TRIG_OUT_1TO1_7_PDMA1_TR_OUT29_ACK_TO_CAN_0 = 0x40001700u /* From cpuss.dw1_tr_out[29] to canfd[0].tr_dbg_dma_ack[0] */ +} en_trig_output_1to1_can0_dw_ack_t; + +/* Trigger Output Group 5 - USB PDMA0 Triggers (OneToOne) */ +typedef enum +{ + TRIG_OUT_1TO1_5_USB_DMA0_TO_PDMA0_TR_IN8 = 0x40001500u, /* From usb.dma_req[0] to cpuss.dw0_tr_in[8] */ + TRIG_OUT_1TO1_5_USB_DMA1_TO_PDMA0_TR_IN9 = 0x40001501u, /* From usb.dma_req[1] to cpuss.dw0_tr_in[9] */ + TRIG_OUT_1TO1_5_USB_DMA2_TO_PDMA0_TR_IN10 = 0x40001502u, /* From usb.dma_req[2] to cpuss.dw0_tr_in[10] */ + TRIG_OUT_1TO1_5_USB_DMA3_TO_PDMA0_TR_IN11 = 0x40001503u, /* From usb.dma_req[3] to cpuss.dw0_tr_in[11] */ + TRIG_OUT_1TO1_5_USB_DMA4_TO_PDMA0_TR_IN12 = 0x40001504u, /* From usb.dma_req[4] to cpuss.dw0_tr_in[12] */ + TRIG_OUT_1TO1_5_USB_DMA5_TO_PDMA0_TR_IN13 = 0x40001505u, /* From usb.dma_req[5] to cpuss.dw0_tr_in[13] */ + TRIG_OUT_1TO1_5_USB_DMA6_TO_PDMA0_TR_IN14 = 0x40001506u, /* From usb.dma_req[6] to cpuss.dw0_tr_in[14] */ + TRIG_OUT_1TO1_5_USB_DMA7_TO_PDMA0_TR_IN15 = 0x40001507u /* From usb.dma_req[7] to cpuss.dw0_tr_in[15] */ +} en_trig_output_1to1_usb_pdma0_tr_t; + +/* Trigger Output Group 6 - USB PDMA0 Acknowledge Triggers (OneToOne) */ +typedef enum +{ + TRIG_OUT_1TO1_6_PDMA0_TR_OUT8_TO_USB_ACK0 = 0x40001600u, /* From cpuss.dw0_tr_out[8] to usb.dma_burstend[0] */ + TRIG_OUT_1TO1_6_PDMA0_TR_OUT9_TO_USB_ACK1 = 0x40001601u, /* From cpuss.dw0_tr_out[9] to usb.dma_burstend[1] */ + TRIG_OUT_1TO1_6_PDMA0_TR_OUT10_TO_USB_ACK2 = 0x40001602u, /* From cpuss.dw0_tr_out[10] to usb.dma_burstend[2] */ + TRIG_OUT_1TO1_6_PDMA0_TR_OUT11_TO_USB_ACK3 = 0x40001603u, /* From cpuss.dw0_tr_out[11] to usb.dma_burstend[3] */ + TRIG_OUT_1TO1_6_PDMA0_TR_OUT12_TO_USB_ACK4 = 0x40001604u, /* From cpuss.dw0_tr_out[12] to usb.dma_burstend[4] */ + TRIG_OUT_1TO1_6_PDMA0_TR_OUT13_TO_USB_ACK5 = 0x40001605u, /* From cpuss.dw0_tr_out[13] to usb.dma_burstend[5] */ + TRIG_OUT_1TO1_6_PDMA0_TR_OUT14_TO_USB_ACK6 = 0x40001606u, /* From cpuss.dw0_tr_out[14] to usb.dma_burstend[6] */ + TRIG_OUT_1TO1_6_PDMA0_TR_OUT15_TO_USB_ACK7 = 0x40001607u /* From cpuss.dw0_tr_out[15] to usb.dma_burstend[7] */ +} en_trig_output_1to1_usb_pdma0_ack_tr_t; + +/* Level or edge detection setting for a trigger mux */ +typedef enum +{ + /* The trigger is a simple level output */ + TRIGGER_TYPE_LEVEL = 0u, + /* The trigger is synchronized to the consumer blocks clock + and a two cycle pulse is generated on this clock */ + TRIGGER_TYPE_EDGE = 1u +} en_trig_type_t; + +/* Trigger Type Defines */ +/* TCPWM Trigger Types */ +#define TRIGGER_TYPE_TCPWM_LINE TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_TCPWM_LINE_COMPL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_TCPWM_TR_OVERFLOW TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_TCPWM_TR_COMPARE_MATCH TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_TCPWM_TR_UNDERFLOW TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_TCPWM_TR_IN__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_TCPWM_TR_IN__EDGE TRIGGER_TYPE_EDGE +/* CSD Trigger Types */ +#define TRIGGER_TYPE_CSD_DSI_SAMPLE_OUT TRIGGER_TYPE_EDGE +/* SCB Trigger Types */ +#define TRIGGER_TYPE_SCB_TR_I2C_SCL_FILTERED TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_SCB_TR_TX_REQ TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_SCB_TR_RX_REQ TRIGGER_TYPE_LEVEL +/* PERI Trigger Types */ +#define TRIGGER_TYPE_PERI_TR_IO_INPUT__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_PERI_TR_IO_INPUT__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_PERI_TR_IO_OUTPUT__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_PERI_TR_IO_OUTPUT__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_PERI_TR_DBG_FREEZE TRIGGER_TYPE_LEVEL +/* CPUSS Trigger Types */ +#define TRIGGER_TYPE_CPUSS_DW0_TR_IN__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_CPUSS_DW0_TR_IN__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_DW1_TR_IN__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_CPUSS_DW1_TR_IN__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_DMAC_TR_IN__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_CPUSS_DMAC_TR_IN__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_DW0_TR_OUT TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_DW1_TR_OUT TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_DMAC_TR_OUT TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_CTI_TR_OUT TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_TR_FAULT TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_CTI_TR_IN TRIGGER_TYPE_EDGE +/* CANFD Trigger Types */ +#define TRIGGER_TYPE_CANFD_TR_TMP_RTP_OUT TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CANFD_TR_EVT_SWT_IN TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CANFD_TR_DBG_DMA_REQ TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_CANFD_TR_FIFO0 TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_CANFD_TR_FIFO1 TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_CANFD_TR_DBG_DMA_ACK TRIGGER_TYPE_EDGE +/* LPCOMP Trigger Types */ +#define TRIGGER_TYPE_LPCOMP_DSI_COMP0 TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_LPCOMP_DSI_COMP1 TRIGGER_TYPE_LEVEL +/* SMIF Trigger Types */ +#define TRIGGER_TYPE_SMIF_TR_TX_REQ TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_SMIF_TR_RX_REQ TRIGGER_TYPE_LEVEL +/* USB Trigger Types */ +#define TRIGGER_TYPE_USB_DMA_REQ TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_USB_DMA_BURSTEND TRIGGER_TYPE_EDGE +/* PASS Trigger Types */ +#define TRIGGER_TYPE_PASS_TR_SAR_OUT TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_PASS_TR_SAR_IN__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_PASS_TR_SAR_IN__EDGE TRIGGER_TYPE_EDGE + +/* Bus masters */ +typedef enum +{ + CPUSS_MS_ID_CM0 = 0, + CPUSS_MS_ID_CRYPTO = 1, + CPUSS_MS_ID_DW0 = 2, + CPUSS_MS_ID_DW1 = 3, + CPUSS_MS_ID_DMAC = 4, + CPUSS_MS_ID_SLOW0 = 5, + CPUSS_MS_ID_SLOW1 = 6, + CPUSS_MS_ID_CM4 = 14, + CPUSS_MS_ID_TC = 15 +} en_prot_master_t; + +/* Pointer to device configuration structure */ +#define CY_DEVICE_CFG (&cy_deviceIpBlockCfgPSoC6_03) + +/* Include IP definitions */ +#include "ip/cyip_sflash.h" +#include "ip/cyip_peri_v2.h" +#include "ip/cyip_peri_ms_v2.h" +#include "ip/cyip_crypto_v2.h" +#include "ip/cyip_cpuss_v2.h" +#include "ip/cyip_fault_v2.h" +#include "ip/cyip_ipc_v2.h" +#include "ip/cyip_prot_v2.h" +#include "ip/cyip_flashc_v2.h" +#include "ip/cyip_srss.h" +#include "ip/cyip_backup.h" +#include "ip/cyip_dw_v2.h" +#include "ip/cyip_dmac_v2.h" +#include "ip/cyip_efuse.h" +#include "ip/cyip_efuse_data_psoc6_03.h" +#include "ip/cyip_hsiom_v2.h" +#include "ip/cyip_gpio_v2.h" +#include "ip/cyip_smartio_v2.h" +#include "ip/cyip_lpcomp.h" +#include "ip/cyip_csd.h" +#include "ip/cyip_tcpwm.h" +#include "ip/cyip_lcd_v2.h" +#include "ip/cyip_usbfs.h" +#include "ip/cyip_smif.h" +#include "ip/cyip_sdhc.h" +#include "ip/cyip_canfd.h" +#include "ip/cyip_scb.h" +#include "ip/cyip_ctbm.h" +#include "ip/cyip_ctdac.h" +#include "ip/cyip_sar.h" +#include "ip/cyip_pass.h" + +/* IP type definitions */ +typedef SFLASH_V1_Type SFLASH_Type; +typedef PERI_GR_V2_Type PERI_GR_Type; +typedef PERI_TR_GR_V2_Type PERI_TR_GR_Type; +typedef PERI_TR_1TO1_GR_V2_Type PERI_TR_1TO1_GR_Type; +typedef PERI_V2_Type PERI_Type; +typedef PERI_MS_PPU_PR_V2_Type PERI_MS_PPU_PR_Type; +typedef PERI_MS_PPU_FX_V2_Type PERI_MS_PPU_FX_Type; +typedef PERI_MS_V2_Type PERI_MS_Type; +typedef CRYPTO_V2_Type CRYPTO_Type; +typedef CPUSS_V2_Type CPUSS_Type; +typedef FAULT_STRUCT_V2_Type FAULT_STRUCT_Type; +typedef FAULT_V2_Type FAULT_Type; +typedef IPC_STRUCT_V2_Type IPC_STRUCT_Type; +typedef IPC_INTR_STRUCT_V2_Type IPC_INTR_STRUCT_Type; +typedef IPC_V2_Type IPC_Type; +typedef PROT_SMPU_SMPU_STRUCT_V2_Type PROT_SMPU_SMPU_STRUCT_Type; +typedef PROT_SMPU_V2_Type PROT_SMPU_Type; +typedef PROT_MPU_MPU_STRUCT_V2_Type PROT_MPU_MPU_STRUCT_Type; +typedef PROT_MPU_V2_Type PROT_MPU_Type; +typedef PROT_V2_Type PROT_Type; +typedef FLASHC_FM_CTL_V2_Type FLASHC_FM_CTL_Type; +typedef FLASHC_V2_Type FLASHC_Type; +typedef MCWDT_STRUCT_V1_Type MCWDT_STRUCT_Type; +typedef SRSS_V1_Type SRSS_Type; +typedef BACKUP_V1_Type BACKUP_Type; +typedef DW_CH_STRUCT_V2_Type DW_CH_STRUCT_Type; +typedef DW_V2_Type DW_Type; +typedef DMAC_CH_V2_Type DMAC_CH_Type; +typedef DMAC_V2_Type DMAC_Type; +typedef EFUSE_V1_Type EFUSE_Type; +typedef HSIOM_PRT_V2_Type HSIOM_PRT_Type; +typedef HSIOM_V2_Type HSIOM_Type; +typedef GPIO_PRT_V2_Type GPIO_PRT_Type; +typedef GPIO_V2_Type GPIO_Type; +typedef SMARTIO_PRT_V2_Type SMARTIO_PRT_Type; +typedef SMARTIO_V2_Type SMARTIO_Type; +typedef LPCOMP_V1_Type LPCOMP_Type; +typedef CSD_V1_Type CSD_Type; +typedef TCPWM_CNT_V1_Type TCPWM_CNT_Type; +typedef TCPWM_V1_Type TCPWM_Type; +typedef LCD_V2_Type LCD_Type; +typedef USBFS_USBDEV_V1_Type USBFS_USBDEV_Type; +typedef USBFS_USBLPM_V1_Type USBFS_USBLPM_Type; +typedef USBFS_USBHOST_V1_Type USBFS_USBHOST_Type; +typedef USBFS_V1_Type USBFS_Type; +typedef SMIF_DEVICE_V1_Type SMIF_DEVICE_Type; +typedef SMIF_V1_Type SMIF_Type; +typedef SDHC_WRAP_V1_Type SDHC_WRAP_Type; +typedef SDHC_CORE_V1_Type SDHC_CORE_Type; +typedef SDHC_V1_Type SDHC_Type; +typedef CANFD_CH_M_TTCAN_V1_Type CANFD_CH_M_TTCAN_Type; +typedef CANFD_CH_V1_Type CANFD_CH_Type; +typedef CANFD_V1_Type CANFD_Type; +typedef CySCB_V1_Type CySCB_Type; +typedef CTBM_V1_Type CTBM_Type; +typedef CTDAC_V1_Type CTDAC_Type; +typedef SAR_V1_Type SAR_Type; +typedef PASS_AREF_V1_Type PASS_AREF_Type; +typedef PASS_V1_Type PASS_Type; + +/* Parameter Defines */ +/* Number of regulator modules instantiated within SRSS, start with estimate, + update after CMR feedback */ +#define SRSS_NUM_ACTREG_PWRMOD 2u +/* Number of shorting switches between vccd and vccact (target dynamic voltage + drop < 10mV) */ +#define SRSS_NUM_ACTIVE_SWITCH 3u +/* ULP linear regulator system is present */ +#define SRSS_ULPLINREG_PRESENT 1u +/* HT linear regulator system is present */ +#define SRSS_HTLINREG_PRESENT 0u +/* Low-current buck regulator present. Can be derived from S40S_SISOBUCKLC_PRESENT + or SIMOBUCK_PRESENT. */ +#define SRSS_BUCKCTL_PRESENT 1u +/* Low-current SISO buck core regulator is present. Only compatible with ULP + linear regulator system (ULPLINREG_PRESENT==1). */ +#define SRSS_S40S_SISOBUCKLC_PRESENT 1u +/* SIMO buck core regulator is present. Only compatible with ULP linear regulator + system (ULPLINREG_PRESENT==1). */ +#define SRSS_SIMOBUCK_PRESENT 0u +/* Precision ILO (PILO) is present */ +#define SRSS_PILO_PRESENT 0u +/* External Crystal Oscillator is present (high frequency) */ +#define SRSS_ECO_PRESENT 1u +/* System Buck-Boost is present */ +#define SRSS_SYSBB_PRESENT 0u +/* Number of clock paths. Must be > 0 */ +#define SRSS_NUM_CLKPATH 5u +/* Number of PLLs present. Must be <= NUM_CLKPATH */ +#define SRSS_NUM_PLL 1u +/* Number of HFCLK roots present. Must be > 0 */ +#define SRSS_NUM_HFROOT 5u +/* Number of PWR_HIB_DATA registers, should not be needed if BACKUP_PRESENT */ +#define SRSS_NUM_HIBDATA 1u +/* Backup domain is present (includes RTC and WCO) */ +#define SRSS_BACKUP_PRESENT 1u +/* Mask of HFCLK root clock supervisors (CSV). For each clock root i, bit[i] of + mask indicates presence of a CSV. */ +#define SRSS_MASK_HFCSV 0u +/* Clock supervisor is present on WCO. Must be 0 if BACKUP_PRESENT==0. */ +#define SRSS_WCOCSV_PRESENT 0u +/* Number of software watchdog timers. */ +#define SRSS_NUM_MCWDT 2u +/* Number of DSI inputs into clock muxes. This is used for logic optimization. */ +#define SRSS_NUM_DSI 0u +/* Alternate high-frequency clock is present. This is used for logic optimization. */ +#define SRSS_ALTHF_PRESENT 0u +/* Alternate low-frequency clock is present. This is used for logic optimization. */ +#define SRSS_ALTLF_PRESENT 0u +/* Use the hardened clkactfllmux block */ +#define SRSS_USE_HARD_CLKACTFLLMUX 1u +/* Number of clock paths, including direct paths in hardened clkactfllmux block + (Must be >= NUM_CLKPATH) */ +#define SRSS_HARD_CLKPATH 6u +/* Number of clock paths with muxes in hardened clkactfllmux block (Must be >= + NUM_PLL+1) */ +#define SRSS_HARD_CLKPATHMUX 6u +/* Number of HFCLKS present in hardened clkactfllmux block (Must be >= NUM_HFROOT) */ +#define SRSS_HARD_HFROOT 6u +/* ECO mux is present in hardened clkactfllmux block (Must be >= ECO_PRESENT) */ +#define SRSS_HARD_ECOMUX_PRESENT 1u +/* ALTHF mux is present in hardened clkactfllmux block (Must be >= ALTHF_PRESENT) */ +#define SRSS_HARD_ALTHFMUX_PRESENT 1u +/* SRSS version is at least SRSS_VER1P3. Set to 1 for new products. Set to 0 for + PSoC6ABLE2, PSoC6A2M. */ +#define SRSS_SRSS_VER1P3 1u +/* Backup memory is present (only used when BACKUP_PRESENT==1) */ +#define SRSS_BACKUP_BMEM_PRESENT 0u +/* Number of Backup registers to include (each is 32b). Only used when + BACKUP_PRESENT==1. */ +#define SRSS_BACKUP_NUM_BREG 16u +/* Number of AMUX splitter cells */ +#define IOSS_HSIOM_AMUX_SPLIT_NR 6u +/* Number of HSIOM ports in device (same as GPIO.GPIO_PRT_NR) */ +#define IOSS_HSIOM_HSIOM_PORT_NR 15u +/* Number of PWR/GND MONITOR CELLs in the device */ +#define IOSS_HSIOM_MONITOR_NR 0u +/* Number of PWR/GND MONITOR CELLs in range 0..31 */ +#define IOSS_HSIOM_MONITOR_NR_0_31 0u +/* Number of PWR/GND MONITOR CELLs in range 32..63 */ +#define IOSS_HSIOM_MONITOR_NR_32_63 0u +/* Number of PWR/GND MONITOR CELLs in range 64..95 */ +#define IOSS_HSIOM_MONITOR_NR_64_95 0u +/* Number of PWR/GND MONITOR CELLs in range 96..127 */ +#define IOSS_HSIOM_MONITOR_NR_96_127 0u +/* Indicates the presence of alternate JTAG interface */ +#define IOSS_HSIOM_ALTJTAG_PRESENT 0u +/* Number of GPIO ports in range 0..31 */ +#define IOSS_GPIO_GPIO_PORT_NR_0_31 15u +/* Number of GPIO ports in range 32..63 */ +#define IOSS_GPIO_GPIO_PORT_NR_32_63 0u +/* Number of GPIO ports in range 64..95 */ +#define IOSS_GPIO_GPIO_PORT_NR_64_95 0u +/* Number of GPIO ports in range 96..127 */ +#define IOSS_GPIO_GPIO_PORT_NR_96_127 0u +/* Number of ports in device */ +#define IOSS_GPIO_GPIO_PORT_NR 15u +/* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_GPIO 1u +/* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SIO 0u +/* Indicates port is a GPIO port including the "AUTO" input threshold */ +#define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_AUTOLVL 0u +/* Indicates that pin #0 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO0 1u +/* Indicates that pin #1 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO1 1u +/* Indicates that pin #2 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO2 1u +/* Indicates that pin #3 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO3 1u +/* Indicates that pin #4 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO4 1u +/* Indicates that pin #5 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO5 1u +/* Indicates that pin #6 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO6 0u +/* Indicates that pin #7 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO7 0u +/* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_GPIO 0u +/* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SIO 0u +/* Indicates port is a GPIO port including the "AUTO" input threshold */ +#define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_AUTOLVL 0u +/* Indicates that pin #0 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO0 0u +/* Indicates that pin #1 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO1 0u +/* Indicates that pin #2 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO2 0u +/* Indicates that pin #3 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO3 0u +/* Indicates that pin #4 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO4 0u +/* Indicates that pin #5 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO5 0u +/* Indicates that pin #6 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO6 0u +/* Indicates that pin #7 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO7 0u +/* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_GPIO 1u +/* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SIO 0u +/* Indicates port is a GPIO port including the "AUTO" input threshold */ +#define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_AUTOLVL 0u +/* Indicates that pin #0 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO0 1u +/* Indicates that pin #1 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO1 1u +/* Indicates that pin #2 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO2 1u +/* Indicates that pin #3 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO3 1u +/* Indicates that pin #4 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO4 1u +/* Indicates that pin #5 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO5 1u +/* Indicates that pin #6 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO6 1u +/* Indicates that pin #7 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO7 1u +/* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_GPIO 1u +/* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SIO 0u +/* Indicates port is a GPIO port including the "AUTO" input threshold */ +#define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_AUTOLVL 0u +/* Indicates that pin #0 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO0 1u +/* Indicates that pin #1 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO1 1u +/* Indicates that pin #2 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO2 0u +/* Indicates that pin #3 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO3 0u +/* Indicates that pin #4 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO4 0u +/* Indicates that pin #5 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO5 0u +/* Indicates that pin #6 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO6 0u +/* Indicates that pin #7 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO7 0u +/* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_GPIO 0u +/* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SIO 0u +/* Indicates port is a GPIO port including the "AUTO" input threshold */ +#define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_AUTOLVL 0u +/* Indicates that pin #0 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO0 0u +/* Indicates that pin #1 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO1 0u +/* Indicates that pin #2 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO2 0u +/* Indicates that pin #3 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO3 0u +/* Indicates that pin #4 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO4 0u +/* Indicates that pin #5 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO5 0u +/* Indicates that pin #6 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO6 0u +/* Indicates that pin #7 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO7 0u +/* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_GPIO 1u +/* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SIO 0u +/* Indicates port is a GPIO port including the "AUTO" input threshold */ +#define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_AUTOLVL 0u +/* Indicates that pin #0 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO0 1u +/* Indicates that pin #1 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO1 1u +/* Indicates that pin #2 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO2 0u +/* Indicates that pin #3 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO3 0u +/* Indicates that pin #4 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO4 0u +/* Indicates that pin #5 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO5 0u +/* Indicates that pin #6 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO6 1u +/* Indicates that pin #7 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO7 1u +/* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_GPIO 1u +/* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SIO 0u +/* Indicates port is a GPIO port including the "AUTO" input threshold */ +#define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_AUTOLVL 0u +/* Indicates that pin #0 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO0 1u +/* Indicates that pin #1 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO1 1u +/* Indicates that pin #2 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO2 1u +/* Indicates that pin #3 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO3 1u +/* Indicates that pin #4 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO4 1u +/* Indicates that pin #5 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO5 1u +/* Indicates that pin #6 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO6 1u +/* Indicates that pin #7 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO7 1u +/* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_GPIO 1u +/* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SIO 0u +/* Indicates port is a GPIO port including the "AUTO" input threshold */ +#define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_AUTOLVL 0u +/* Indicates that pin #0 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO0 1u +/* Indicates that pin #1 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO1 1u +/* Indicates that pin #2 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO2 1u +/* Indicates that pin #3 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO3 1u +/* Indicates that pin #4 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO4 1u +/* Indicates that pin #5 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO5 1u +/* Indicates that pin #6 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO6 1u +/* Indicates that pin #7 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO7 1u +/* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_GPIO 1u +/* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SIO 0u +/* Indicates port is a GPIO port including the "AUTO" input threshold */ +#define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_AUTOLVL 0u +/* Indicates that pin #0 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO0 1u +/* Indicates that pin #1 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO1 1u +/* Indicates that pin #2 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO2 1u +/* Indicates that pin #3 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO3 1u +/* Indicates that pin #4 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO4 0u +/* Indicates that pin #5 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO5 0u +/* Indicates that pin #6 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO6 0u +/* Indicates that pin #7 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO7 0u +/* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_GPIO 1u +/* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SIO 0u +/* Indicates port is a GPIO port including the "AUTO" input threshold */ +#define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_AUTOLVL 0u +/* Indicates that pin #0 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO0 1u +/* Indicates that pin #1 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO1 1u +/* Indicates that pin #2 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO2 1u +/* Indicates that pin #3 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO3 1u +/* Indicates that pin #4 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO4 0u +/* Indicates that pin #5 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO5 0u +/* Indicates that pin #6 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO6 0u +/* Indicates that pin #7 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO7 0u +/* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_GPIO 1u +/* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SIO 0u +/* Indicates port is a GPIO port including the "AUTO" input threshold */ +#define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_AUTOLVL 0u +/* Indicates that pin #0 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO0 1u +/* Indicates that pin #1 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO1 1u +/* Indicates that pin #2 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO2 1u +/* Indicates that pin #3 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO3 1u +/* Indicates that pin #4 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO4 1u +/* Indicates that pin #5 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO5 1u +/* Indicates that pin #6 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO6 1u +/* Indicates that pin #7 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO7 1u +/* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_GPIO 1u +/* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SIO 0u +/* Indicates port is a GPIO port including the "AUTO" input threshold */ +#define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_AUTOLVL 0u +/* Indicates that pin #0 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO0 1u +/* Indicates that pin #1 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO1 1u +/* Indicates that pin #2 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO2 1u +/* Indicates that pin #3 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO3 1u +/* Indicates that pin #4 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO4 1u +/* Indicates that pin #5 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO5 1u +/* Indicates that pin #6 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO6 1u +/* Indicates that pin #7 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO7 1u +/* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_GPIO 1u +/* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SIO 0u +/* Indicates port is a GPIO port including the "AUTO" input threshold */ +#define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_AUTOLVL 0u +/* Indicates that pin #0 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO0 1u +/* Indicates that pin #1 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO1 1u +/* Indicates that pin #2 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO2 0u +/* Indicates that pin #3 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO3 0u +/* Indicates that pin #4 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO4 0u +/* Indicates that pin #5 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO5 0u +/* Indicates that pin #6 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO6 1u +/* Indicates that pin #7 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO7 1u +/* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_GPIO 0u +/* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SIO 0u +/* Indicates port is a GPIO port including the "AUTO" input threshold */ +#define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_AUTOLVL 0u +/* Indicates that pin #0 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO0 0u +/* Indicates that pin #1 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO1 0u +/* Indicates that pin #2 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO2 0u +/* Indicates that pin #3 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO3 0u +/* Indicates that pin #4 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO4 0u +/* Indicates that pin #5 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO5 0u +/* Indicates that pin #6 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO6 0u +/* Indicates that pin #7 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO7 0u +/* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_GPIO 0u +/* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SIO 0u +/* Indicates port is a GPIO port including the "AUTO" input threshold */ +#define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_AUTOLVL 0u +/* Indicates that pin #0 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO0 1u +/* Indicates that pin #1 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO1 1u +/* Indicates that pin #2 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO2 0u +/* Indicates that pin #3 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO3 0u +/* Indicates that pin #4 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO4 0u +/* Indicates that pin #5 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO5 0u +/* Indicates that pin #6 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO6 0u +/* Indicates that pin #7 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO7 0u +/* Mask of SMARTIO instances presence */ +#define IOSS_SMARTIO_SMARTIO_MASK 768u +/* The number of protection contexts ([2, 16]). */ +#define PERI_PC_NR 8u +/* Master interface presence mask (4 bits) */ +#define PERI_MS_PRESENT 15u +/* Protection structures SRAM ECC present or not ('0': no, '1': yes) */ +#define PERI_ECC_PRESENT 0u +/* Protection structures SRAM address ECC present or not ('0': no, '1': yes) */ +#define PERI_ECC_ADDR_PRESENT 0u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL0_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL1_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL2_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL0_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL1_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL2_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL0_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL1_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL2_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL3_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL4_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL6_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL7_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL8_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL9_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL10_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL12_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL0_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL1_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL2_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL5_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL6_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL8_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL9_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL11_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL15_PRESENT 1u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL0_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL1_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL2_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL6_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL0_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL1_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL2_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL0_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL1_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL2_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL3_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL4_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL5_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL6_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL0_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL1_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL2_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL0_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL1_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL2_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL0_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL1_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL2_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL0_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL1_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL2_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL0_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL1_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL2_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL0_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL1_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL2_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL0_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL1_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL2_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL0_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL1_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL2_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL0_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL1_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL2_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Number of programmable clocks (outputs) */ +#define PERI_CLOCK_NR 28u +/* Number of 8.0 dividers */ +#define PERI_DIV_8_NR 4u +/* Number of 16.0 dividers */ +#define PERI_DIV_16_NR 8u +/* Number of 16.5 (fractional) dividers */ +#define PERI_DIV_16_5_NR 2u +/* Number of 24.5 (fractional) dividers */ +#define PERI_DIV_24_5_NR 1u +/* Divider number width: max(1,roundup(log2(max(DIV_*_NR))) */ +#define PERI_DIV_ADDR_WIDTH 3u +/* Timeout functionality present ('0': no, '1': yes) */ +#define PERI_TIMEOUT_PRESENT 1u +/* Trigger module present (0=No, 1=Yes) */ +#define PERI_TR 1u +/* Number of trigger groups */ +#define PERI_TR_GROUP_NR 11u +/* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_GROUP_NR0_TR_GROUP_TR_MANIPULATION_PRESENT 1u +/* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_GROUP_NR1_TR_GROUP_TR_MANIPULATION_PRESENT 1u +/* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_GROUP_NR2_TR_GROUP_TR_MANIPULATION_PRESENT 1u +/* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_GROUP_NR3_TR_GROUP_TR_MANIPULATION_PRESENT 1u +/* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_GROUP_NR4_TR_GROUP_TR_MANIPULATION_PRESENT 1u +/* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_GROUP_NR5_TR_GROUP_TR_MANIPULATION_PRESENT 1u +/* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_GROUP_NR6_TR_GROUP_TR_MANIPULATION_PRESENT 1u +/* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_GROUP_NR7_TR_GROUP_TR_MANIPULATION_PRESENT 1u +/* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_GROUP_NR8_TR_GROUP_TR_MANIPULATION_PRESENT 1u +/* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_GROUP_NR9_TR_GROUP_TR_MANIPULATION_PRESENT 1u +/* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_GROUP_NR10_TR_GROUP_TR_MANIPULATION_PRESENT 1u +/* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_1TO1_GROUP_NR0_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u +/* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_1TO1_GROUP_NR1_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u +/* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_1TO1_GROUP_NR2_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u +/* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_1TO1_GROUP_NR3_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u +/* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_1TO1_GROUP_NR4_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u +/* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_1TO1_GROUP_NR5_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u +/* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_1TO1_GROUP_NR6_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u +/* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_1TO1_GROUP_NR7_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u +/* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ +#define PERI_MASTER_WIDTH 8u +/* UDB present or not ('0': no, '1': yes) */ +#define CPUSS_UDB_PRESENT 0u +/* MBIST MMIO for Synopsys MBIST ('0': no, '1': yes). Set this to '1' only for the + chips which doesn't use mxdft. */ +#define CPUSS_MBIST_MMIO_PRESENT 1u +/* System RAM 0 size in kilobytes */ +#define CPUSS_SRAM0_SIZE 256u +/* Number of macros used to implement System RAM 0. Example: 8 if 256 KB System + SRAM0 is implemented with 8 32KB macros. */ +#define CPUSS_RAMC0_MACRO_NR 8u +/* System RAM 1 present or not (0=No, 1=Yes) */ +#define CPUSS_RAMC1_PRESENT 0u +/* System RAM 1 size in kilobytes */ +#define CPUSS_SRAM1_SIZE 1u +/* Number of macros used to implement System RAM 1. Example: 8 if 256 KB System + RAM 1 is implemented with 8 32KB macros. */ +#define CPUSS_RAMC1_MACRO_NR 1u +/* System RAM 2 present or not (0=No, 1=Yes) */ +#define CPUSS_RAMC2_PRESENT 0u +/* System RAM 2 size in kilobytes */ +#define CPUSS_SRAM2_SIZE 1u +/* Number of macros used to implement System RAM 2. Example: 8 if 256 KB System + RAM 2 is implemented with 8 32KB macros. */ +#define CPUSS_RAMC2_MACRO_NR 1u +/* System SRAM(s) ECC present or not ('0': no, '1': yes) */ +#define CPUSS_RAMC_ECC_PRESENT 0u +/* System SRAM(s) address ECC present or not ('0': no, '1': yes) */ +#define CPUSS_RAMC_ECC_ADDR_PRESENT 0u +/* ECC present in either system RAM or interrupt handler (RAMC_ECC_PRESENT) */ +#define CPUSS_ECC_PRESENT 0u +/* DataWire SRAMs ECC present or not ('0': no, '1': yes) */ +#define CPUSS_DW_ECC_PRESENT 0u +/* DataWire SRAMs address ECC present or not ('0': no, '1': yes) */ +#define CPUSS_DW_ECC_ADDR_PRESENT 0u +/* System ROM size in KB */ +#define CPUSS_ROM_SIZE 64u +/* Number of macros used to implement system ROM. Example: 4 if 512 KB system ROM + is implemented with 4 128KB macros. */ +#define CPUSS_ROMC_MACRO_NR 1u +/* Flash memory type ('0' : SONOS, '1': ECT) */ +#define CPUSS_FLASHC_ECT 0u +/* Flash main region size in KB */ +#define CPUSS_FLASH_SIZE 512u +/* Flash work region size in KB (EEPROM emulation, data) */ +#define CPUSS_WFLASH_SIZE 32u +/* Flash supervisory region size in KB */ +#define CPUSS_SFLASH_SIZE 32u +/* Flash data output word size (in Bytes) */ +#define CPUSS_FLASHC_MAIN_DATA_WIDTH 16u +/* SONOS Flash RWW present or not ('0': no, '1': yes) When RWW is '0', No special + sectors present in Flash. Part of main sector 0 is allowcated for Supervisory + Flash, and no Work Flash present. */ +#define CPUSS_FLASHC_SONOS_RWW 1u +/* SONOS Flash, number of main sectors. */ +#define CPUSS_FLASHC_SONOS_MAIN_SECTORS 2u +/* SONOS Flash, number of rows per main sector. */ +#define CPUSS_FLASHC_SONOS_MAIN_ROWS 512u +/* SONOS Flash, number of words per row of main sector. */ +#define CPUSS_FLASHC_SONOS_MAIN_WORDS 128u +/* SONOS Flash, number of special sectors. */ +#define CPUSS_FLASHC_SONOS_SPL_SECTORS 2u +/* SONOS Flash, number of rows per special sector. */ +#define CPUSS_FLASHC_SONOS_SPL_ROWS 64u +/* Flash memory ECC present or not ('0': no, '1': yes) */ +#define CPUSS_FLASHC_FLASH_ECC_PRESENT 0u +/* Flash cache SRAM(s) ECC present or not ('0': no, '1': yes) */ +#define CPUSS_FLASHC_RAM_ECC_PRESENT 0u +/* Number of external slaves directly connected to slow AHB-Lite infrastructure. + Maximum nubmer of slave supported is 4. Width of this parameter is 4-bits. + 1-bit mask for each slave indicating present or not. Example: 4'b0011 - slave + 0 and slave 1 are present. Note: The SLOW_SLx_ADDR and SLOW_SLx_MASK + parameters (for the slaves present) should be derived from the Memory Map. */ +#define CPUSS_SLOW_SL_PRESENT 1u +/* Number of external slaves directly connected to fast AHB-Lite infrastructure. + Maximum nubmer of slave supported is 4. Width of this parameter is 4-bits. + 1-bit mask for each slave indicating present or not. Example: 4'b0011 - slave + 0 and slave 1 are present. Note: The FAST_SLx_ADDR and FAST_SLx_MASK + parameters (for the slaves present) should be derived from the Memory Map. */ +#define CPUSS_FAST_SL_PRESENT 1u +/* Number of external masters driving the slow AHB-Lite infrastructure. Maximum + number of masters supported is 2. Width of this parameter is 2-bits. 1-bit + mask for each master indicating present or not. Example: 2'b01 - master 0 is + present. */ +#define CPUSS_SLOW_MS_PRESENT 1u +/* System interrupt functionality present or not ('0': no; '1': yes). Not used for + CM0+ PCU, which always uses system interrupt functionality. */ +#define CPUSS_SYSTEM_IRQ_PRESENT 0u +/* Number of total interrupt request inputs to CPUSS */ +#define CPUSS_SYSTEM_INT_NR 174u +/* Number of DeepSleep wakeup interrupt inputs to CPUSS */ +#define CPUSS_SYSTEM_DPSLP_INT_NR 39u +/* Width of the CM4 interrupt priority bits. Legal range [3,8] Example: 3 = 8 + levels of priority 8 = 256 levels of priority */ +#define CPUSS_CM4_LVL_WIDTH 3u +/* CM4 Floating point unit present or not (0=No, 1=Yes) */ +#define CPUSS_CM4_FPU_PRESENT 1u +/* Debug level. Legal range [0,3] (0= No support, 1= Minimum: CM0/4 both 2 + breakpoints +1 watchpoint, 2= Full debug: CM0/4 have 4/6 breakpoints, 2/4 + watchpoints and 0/2 literal compare, 3= Full debug + data matching) */ +#define CPUSS_DEBUG_LVL 3u +/* Trace level. Legal range [0,2] (0= No tracing, 1= ITM + TPIU + SWO, 2= ITM + + ETM + TPIU + SWO) Note: CM4 HTM is not supported. Hence vaule 3 for trace + level is not supported in CPUSS. */ +#define CPUSS_TRACE_LVL 2u +/* Embedded Trace Buffer present or not (0=No, 1=Yes) */ +#define CPUSS_ETB_PRESENT 0u +/* CM0+ MTB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */ +#define CPUSS_MTB_SRAM_SIZE 4u +/* CM4 ETB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */ +#define CPUSS_ETB_SRAM_SIZE 8u +/* PTM interface present (0=No, 1=Yes) */ +#define CPUSS_PTM_PRESENT 0u +/* Width of the PTM interface in bits ([2,32]) */ +#define CPUSS_PTM_WIDTH 1u +/* Width of the TPIU interface in bits ([1,4]) */ +#define CPUSS_TPIU_WIDTH 4u +/* CoreSight Part Identification Number */ +#define CPUSS_JEPID 52u +/* CoreSight Part Identification Number */ +#define CPUSS_JEPCONTINUATION 0u +/* CoreSight Part Identification Number */ +#define CPUSS_FAMILYID 261u +/* ROM trim register width (for ARM 3, for Synopsys 5) */ +#define CPUSS_ROM_TRIM_WIDTH 5u +/* ROM trim register default (for both ARM and Synopsys 0x0000_0012) */ +#define CPUSS_ROM_TRIM_DEFAULT 18u +/* RAM trim register width (for ARM 8, for Synopsys 15) */ +#define CPUSS_RAM_TRIM_WIDTH 15u +/* RAM trim register default (for ARM 0x0000_0062 and for Synopsys 0x0000_6012) */ +#define CPUSS_RAM_TRIM_DEFAULT 24594u +/* Cryptography IP present or not (0=No, 1=Yes) */ +#define CPUSS_CRYPTO_PRESENT 1u +/* DataWire and DMAC SW trigger per channel present or not ('0': no, '1': yes) */ +#define CPUSS_SW_TR_PRESENT 0u +/* DataWire 0 present or not (0=No, 1=Yes) */ +#define CPUSS_DW0_PRESENT 1u +/* Number of DataWire 0 channels (8, 16 or 32) */ +#define CPUSS_DW0_CH_NR 29u +/* DataWire 1 present or not (0=No, 1=Yes) */ +#define CPUSS_DW1_PRESENT 1u +/* Number of DataWire 1 channels (8, 16 or 32) */ +#define CPUSS_DW1_CH_NR 32u +/* DMA controller present or not ('0': no, '1': yes) */ +#define CPUSS_DMAC_PRESENT 1u +/* Number of DMA controller channels ([1, 8]) */ +#define CPUSS_DMAC_CH_NR 2u +/* Number of Flash BIST_DATA registers */ +#define CPUSS_FLASHC_FLASHC_BIST_DATA_NR 4u +/* Page size in # of 32-bit words (1: 4 bytes, 2: 8 bytes, ... */ +#define CPUSS_FLASHC_PA_SIZE 128u +/* SONOS Flash is used or not ('0': no, '1': yes) */ +#define CPUSS_FLASHC_FLASHC_IS_SONOS 1u +/* eCT Flash is used or not ('0': no, '1': yes) */ +#define CPUSS_FLASHC_FLASHC_IS_ECT 0u +/* Cryptography SRAMs ECC present or not ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_ECC_PRESENT 0u +/* Cryptography SRAMs address ECC present or not ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_ECC_ADDR_PRESENT 0u +/* AES cipher support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_AES 1u +/* (Tripple) DES cipher support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_DES 1u +/* Chacha support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_CHACHA 1u +/* Pseudo random number generation support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_PR 1u +/* SHA1 hash support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_SHA1 1u +/* SHA2 hash support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_SHA2 1u +/* SHA3 hash support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_SHA3 1u +/* Cyclic Redundancy Check support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_CRC 1u +/* True random number generation support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_TR 1u +/* Vector unit support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_VU 1u +/* Galios/Counter Mode (GCM) support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_GCM 1u +/* Number of 32-bit words in the IP internal memory buffer (from the set [64, 128, + 256, 512, 1024, 2048, 4096], to allow for a 256 B, 512 B, 1 kB, 2 kB, 4 kB, 8 + kB and 16 kB memory buffer) */ +#define CPUSS_CRYPTO_BUFF_SIZE 1024u +/* Number of fault structures. Legal range [1, 4] */ +#define CPUSS_FAULT_FAULT_NR 2u +/* Number of IPC structures. Legal range [1, 16] */ +#define CPUSS_IPC_IPC_NR 16u +/* Number of IPC interrupt structures. Legal range [1, 16] */ +#define CPUSS_IPC_IPC_IRQ_NR 16u +/* Master 0 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS0_PC_NR_MINUS1 7u +/* Master 1 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS1_PC_NR_MINUS1 0u +/* Master 2 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS2_PC_NR_MINUS1 0u +/* Master 3 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS3_PC_NR_MINUS1 0u +/* Master 4 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS4_PC_NR_MINUS1 0u +/* Master 5 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS5_PC_NR_MINUS1 7u +/* Master 6 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS6_PC_NR_MINUS1 0u +/* Master 7 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS7_PC_NR_MINUS1 0u +/* Master 8 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS8_PC_NR_MINUS1 0u +/* Master 9 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS9_PC_NR_MINUS1 0u +/* Master 10 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS10_PC_NR_MINUS1 0u +/* Master 11 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS11_PC_NR_MINUS1 0u +/* Master 12 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS12_PC_NR_MINUS1 0u +/* Master 13 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS13_PC_NR_MINUS1 0u +/* Master 14 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS14_PC_NR_MINUS1 7u +/* Master 15 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS15_PC_NR_MINUS1 7u +/* Number of SMPU protection structures */ +#define CPUSS_PROT_SMPU_STRUCT_NR 16u +/* Number of protection contexts supported minus 1. Legal range [1,16] */ +#define CPUSS_SMPU_STRUCT_PC_NR_MINUS1 7u +/* Number of DataWire controllers present (max 2) */ +#define CPUSS_DW_NR 2u +/* DataWire SRAMs ECC present or not ('0': no, '1': yes) */ +#define CPUSS_DW_ECC_PRESENT 0u +/* DataWire SW trigger per channel present or not ('0': no, '1': yes) */ +#define CPUSS_CH_STRUCT_SW_TR_PRESENT 0u +/* Number of DataWire controllers present (max 2) (same as DW.NR above) */ +#define CPUSS_CPUSS_DW_DW_NR 2u +/* Number of channels in each DataWire controller */ +#define CPUSS_CPUSS_DW_DW_NR0_DW_CH_NR 29u +/* Width of a channel number in bits */ +#define CPUSS_CPUSS_DW_DW_NR0_DW_CH_NR_WIDTH 5u +/* Number of channels in each DataWire controller */ +#define CPUSS_CPUSS_DW_DW_NR1_DW_CH_NR 32u +/* Width of a channel number in bits */ +#define CPUSS_CPUSS_DW_DW_NR1_DW_CH_NR_WIDTH 5u +/* Number of DMA controller channels ([1, 8]) */ +#define CPUSS_DMAC_CH_NR 2u +/* DMAC SW trigger per channel present or not ('0': no, '1': yes) */ +#define CPUSS_CH_SW_TR_PRESENT 0u +/* Copy value from Globals */ +#define CPUSS_CHIP_TOP_PROFILER_PRESENT 0u +/* ETAS Calibration support pin out present (automotive only) */ +#define CPUSS_CHIP_TOP_CAL_SUP_NZ_PRESENT 0u +/* TRACE_LVL>0 */ +#define CPUSS_CHIP_TOP_TRACE_PRESENT 1u +/* Number of instantiated eFUSE macros (256 bit macros). Legal range [1, 16] */ +#define EFUSE_EFUSE_NR 4u +/* SONOS Flash is used or not ('0': no, '1': yes) */ +#define SFLASH_FLASHC_IS_SONOS 1u +/* CPUSS_WOUNDING_PRESENT or not ('0': no, '1': yes) */ +#define SFLASH_CPUSS_WOUNDING_PRESENT 0u +/* DeepSleep support ('0':no, '1': yes) */ +#define SCB0_DEEPSLEEP 0u +/* Externally clocked support? ('0': no, '1': yes) */ +#define SCB0_EC 0u +/* I2C master support? ('0': no, '1': yes) */ +#define SCB0_I2C_M 1u +/* I2C slave support? ('0': no, '1': yes) */ +#define SCB0_I2C_S 1u +/* I2C support? (I2C_M | I2C_S) */ +#define SCB0_I2C 1u +/* I2C glitch filters present? ('0': no, '1': yes) */ +#define SCB0_I2C_GLITCH 1u +/* I2C externally clocked support? ('0': no, '1': yes) */ +#define SCB0_I2C_EC 0u +/* I2C master and slave support? (I2C_M & I2C_S) */ +#define SCB0_I2C_M_S 1u +/* I2C slave with EC? (I2C_S & I2C_EC) */ +#define SCB0_I2C_S_EC 0u +/* SPI master support? ('0': no, '1': yes) */ +#define SCB0_SPI_M 1u +/* SPI slave support? ('0': no, '1': yes) */ +#define SCB0_SPI_S 1u +/* SPI support? (SPI_M | SPI_S) */ +#define SCB0_SPI 1u +/* SPI externally clocked support? ('0': no, '1': yes) */ +#define SCB0_SPI_EC 0u +/* SPI slave with EC? (SPI_S & SPI_EC) */ +#define SCB0_SPI_S_EC 0u +/* UART support? ('0': no, '1': yes) */ +#define SCB0_UART 1u +/* SPI or UART (SPI | UART) */ +#define SCB0_SPI_UART 1u +/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, + CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only + 256 B are used. This is because the EZ mode uses 8-bit addresses. */ +#define SCB0_EZ_DATA_NR 256u +/* Command/response mode support? ('0': no, '1': yes) */ +#define SCB0_CMD_RESP 0u +/* EZ mode support? ('0': no, '1': yes) */ +#define SCB0_EZ 0u +/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ +#define SCB0_EZ_CMD_RESP 0u +/* I2C slave with EZ mode (I2C_S & EZ) */ +#define SCB0_I2C_S_EZ 0u +/* SPI slave with EZ mode (SPI_S & EZ) */ +#define SCB0_SPI_S_EZ 0u +/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ +#define SCB0_I2C_FAST_PLUS 1u +/* Number of used spi_select signals (max 4) */ +#define SCB0_CHIP_TOP_SPI_SEL_NR 3u +/* DeepSleep support ('0':no, '1': yes) */ +#define SCB1_DEEPSLEEP 0u +/* Externally clocked support? ('0': no, '1': yes) */ +#define SCB1_EC 0u +/* I2C master support? ('0': no, '1': yes) */ +#define SCB1_I2C_M 1u +/* I2C slave support? ('0': no, '1': yes) */ +#define SCB1_I2C_S 1u +/* I2C support? (I2C_M | I2C_S) */ +#define SCB1_I2C 1u +/* I2C glitch filters present? ('0': no, '1': yes) */ +#define SCB1_I2C_GLITCH 1u +/* I2C externally clocked support? ('0': no, '1': yes) */ +#define SCB1_I2C_EC 0u +/* I2C master and slave support? (I2C_M & I2C_S) */ +#define SCB1_I2C_M_S 1u +/* I2C slave with EC? (I2C_S & I2C_EC) */ +#define SCB1_I2C_S_EC 0u +/* SPI master support? ('0': no, '1': yes) */ +#define SCB1_SPI_M 1u +/* SPI slave support? ('0': no, '1': yes) */ +#define SCB1_SPI_S 1u +/* SPI support? (SPI_M | SPI_S) */ +#define SCB1_SPI 1u +/* SPI externally clocked support? ('0': no, '1': yes) */ +#define SCB1_SPI_EC 0u +/* SPI slave with EC? (SPI_S & SPI_EC) */ +#define SCB1_SPI_S_EC 0u +/* UART support? ('0': no, '1': yes) */ +#define SCB1_UART 1u +/* SPI or UART (SPI | UART) */ +#define SCB1_SPI_UART 1u +/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, + CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only + 256 B are used. This is because the EZ mode uses 8-bit addresses. */ +#define SCB1_EZ_DATA_NR 256u +/* Command/response mode support? ('0': no, '1': yes) */ +#define SCB1_CMD_RESP 0u +/* EZ mode support? ('0': no, '1': yes) */ +#define SCB1_EZ 0u +/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ +#define SCB1_EZ_CMD_RESP 0u +/* I2C slave with EZ mode (I2C_S & EZ) */ +#define SCB1_I2C_S_EZ 0u +/* SPI slave with EZ mode (SPI_S & EZ) */ +#define SCB1_SPI_S_EZ 0u +/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ +#define SCB1_I2C_FAST_PLUS 1u +/* Number of used spi_select signals (max 4) */ +#define SCB1_CHIP_TOP_SPI_SEL_NR 4u +/* DeepSleep support ('0':no, '1': yes) */ +#define SCB2_DEEPSLEEP 0u +/* Externally clocked support? ('0': no, '1': yes) */ +#define SCB2_EC 0u +/* I2C master support? ('0': no, '1': yes) */ +#define SCB2_I2C_M 1u +/* I2C slave support? ('0': no, '1': yes) */ +#define SCB2_I2C_S 1u +/* I2C support? (I2C_M | I2C_S) */ +#define SCB2_I2C 1u +/* I2C glitch filters present? ('0': no, '1': yes) */ +#define SCB2_I2C_GLITCH 1u +/* I2C externally clocked support? ('0': no, '1': yes) */ +#define SCB2_I2C_EC 0u +/* I2C master and slave support? (I2C_M & I2C_S) */ +#define SCB2_I2C_M_S 1u +/* I2C slave with EC? (I2C_S & I2C_EC) */ +#define SCB2_I2C_S_EC 0u +/* SPI master support? ('0': no, '1': yes) */ +#define SCB2_SPI_M 1u +/* SPI slave support? ('0': no, '1': yes) */ +#define SCB2_SPI_S 1u +/* SPI support? (SPI_M | SPI_S) */ +#define SCB2_SPI 1u +/* SPI externally clocked support? ('0': no, '1': yes) */ +#define SCB2_SPI_EC 0u +/* SPI slave with EC? (SPI_S & SPI_EC) */ +#define SCB2_SPI_S_EC 0u +/* UART support? ('0': no, '1': yes) */ +#define SCB2_UART 1u +/* SPI or UART (SPI | UART) */ +#define SCB2_SPI_UART 1u +/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, + CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only + 256 B are used. This is because the EZ mode uses 8-bit addresses. */ +#define SCB2_EZ_DATA_NR 256u +/* Command/response mode support? ('0': no, '1': yes) */ +#define SCB2_CMD_RESP 0u +/* EZ mode support? ('0': no, '1': yes) */ +#define SCB2_EZ 0u +/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ +#define SCB2_EZ_CMD_RESP 0u +/* I2C slave with EZ mode (I2C_S & EZ) */ +#define SCB2_I2C_S_EZ 0u +/* SPI slave with EZ mode (SPI_S & EZ) */ +#define SCB2_SPI_S_EZ 0u +/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ +#define SCB2_I2C_FAST_PLUS 1u +/* Number of used spi_select signals (max 4) */ +#define SCB2_CHIP_TOP_SPI_SEL_NR 1u +/* DeepSleep support ('0':no, '1': yes) */ +#define SCB3_DEEPSLEEP 0u +/* Externally clocked support? ('0': no, '1': yes) */ +#define SCB3_EC 0u +/* I2C master support? ('0': no, '1': yes) */ +#define SCB3_I2C_M 1u +/* I2C slave support? ('0': no, '1': yes) */ +#define SCB3_I2C_S 1u +/* I2C support? (I2C_M | I2C_S) */ +#define SCB3_I2C 1u +/* I2C glitch filters present? ('0': no, '1': yes) */ +#define SCB3_I2C_GLITCH 1u +/* I2C externally clocked support? ('0': no, '1': yes) */ +#define SCB3_I2C_EC 0u +/* I2C master and slave support? (I2C_M & I2C_S) */ +#define SCB3_I2C_M_S 1u +/* I2C slave with EC? (I2C_S & I2C_EC) */ +#define SCB3_I2C_S_EC 0u +/* SPI master support? ('0': no, '1': yes) */ +#define SCB3_SPI_M 1u +/* SPI slave support? ('0': no, '1': yes) */ +#define SCB3_SPI_S 1u +/* SPI support? (SPI_M | SPI_S) */ +#define SCB3_SPI 1u +/* SPI externally clocked support? ('0': no, '1': yes) */ +#define SCB3_SPI_EC 0u +/* SPI slave with EC? (SPI_S & SPI_EC) */ +#define SCB3_SPI_S_EC 0u +/* UART support? ('0': no, '1': yes) */ +#define SCB3_UART 1u +/* SPI or UART (SPI | UART) */ +#define SCB3_SPI_UART 1u +/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, + CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only + 256 B are used. This is because the EZ mode uses 8-bit addresses. */ +#define SCB3_EZ_DATA_NR 256u +/* Command/response mode support? ('0': no, '1': yes) */ +#define SCB3_CMD_RESP 0u +/* EZ mode support? ('0': no, '1': yes) */ +#define SCB3_EZ 0u +/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ +#define SCB3_EZ_CMD_RESP 0u +/* I2C slave with EZ mode (I2C_S & EZ) */ +#define SCB3_I2C_S_EZ 0u +/* SPI slave with EZ mode (SPI_S & EZ) */ +#define SCB3_SPI_S_EZ 0u +/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ +#define SCB3_I2C_FAST_PLUS 1u +/* Number of used spi_select signals (max 4) */ +#define SCB3_CHIP_TOP_SPI_SEL_NR 1u +/* DeepSleep support ('0':no, '1': yes) */ +#define SCB4_DEEPSLEEP 0u +/* Externally clocked support? ('0': no, '1': yes) */ +#define SCB4_EC 0u +/* I2C master support? ('0': no, '1': yes) */ +#define SCB4_I2C_M 1u +/* I2C slave support? ('0': no, '1': yes) */ +#define SCB4_I2C_S 1u +/* I2C support? (I2C_M | I2C_S) */ +#define SCB4_I2C 1u +/* I2C glitch filters present? ('0': no, '1': yes) */ +#define SCB4_I2C_GLITCH 1u +/* I2C externally clocked support? ('0': no, '1': yes) */ +#define SCB4_I2C_EC 0u +/* I2C master and slave support? (I2C_M & I2C_S) */ +#define SCB4_I2C_M_S 1u +/* I2C slave with EC? (I2C_S & I2C_EC) */ +#define SCB4_I2C_S_EC 0u +/* SPI master support? ('0': no, '1': yes) */ +#define SCB4_SPI_M 1u +/* SPI slave support? ('0': no, '1': yes) */ +#define SCB4_SPI_S 1u +/* SPI support? (SPI_M | SPI_S) */ +#define SCB4_SPI 1u +/* SPI externally clocked support? ('0': no, '1': yes) */ +#define SCB4_SPI_EC 0u +/* SPI slave with EC? (SPI_S & SPI_EC) */ +#define SCB4_SPI_S_EC 0u +/* UART support? ('0': no, '1': yes) */ +#define SCB4_UART 1u +/* SPI or UART (SPI | UART) */ +#define SCB4_SPI_UART 1u +/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, + CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only + 256 B are used. This is because the EZ mode uses 8-bit addresses. */ +#define SCB4_EZ_DATA_NR 256u +/* Command/response mode support? ('0': no, '1': yes) */ +#define SCB4_CMD_RESP 0u +/* EZ mode support? ('0': no, '1': yes) */ +#define SCB4_EZ 0u +/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ +#define SCB4_EZ_CMD_RESP 0u +/* I2C slave with EZ mode (I2C_S & EZ) */ +#define SCB4_I2C_S_EZ 0u +/* SPI slave with EZ mode (SPI_S & EZ) */ +#define SCB4_SPI_S_EZ 0u +/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ +#define SCB4_I2C_FAST_PLUS 1u +/* Number of used spi_select signals (max 4) */ +#define SCB4_CHIP_TOP_SPI_SEL_NR 4u +/* DeepSleep support ('0':no, '1': yes) */ +#define SCB5_DEEPSLEEP 0u +/* Externally clocked support? ('0': no, '1': yes) */ +#define SCB5_EC 0u +/* I2C master support? ('0': no, '1': yes) */ +#define SCB5_I2C_M 1u +/* I2C slave support? ('0': no, '1': yes) */ +#define SCB5_I2C_S 1u +/* I2C support? (I2C_M | I2C_S) */ +#define SCB5_I2C 1u +/* I2C glitch filters present? ('0': no, '1': yes) */ +#define SCB5_I2C_GLITCH 1u +/* I2C externally clocked support? ('0': no, '1': yes) */ +#define SCB5_I2C_EC 0u +/* I2C master and slave support? (I2C_M & I2C_S) */ +#define SCB5_I2C_M_S 1u +/* I2C slave with EC? (I2C_S & I2C_EC) */ +#define SCB5_I2C_S_EC 0u +/* SPI master support? ('0': no, '1': yes) */ +#define SCB5_SPI_M 1u +/* SPI slave support? ('0': no, '1': yes) */ +#define SCB5_SPI_S 1u +/* SPI support? (SPI_M | SPI_S) */ +#define SCB5_SPI 1u +/* SPI externally clocked support? ('0': no, '1': yes) */ +#define SCB5_SPI_EC 0u +/* SPI slave with EC? (SPI_S & SPI_EC) */ +#define SCB5_SPI_S_EC 0u +/* UART support? ('0': no, '1': yes) */ +#define SCB5_UART 1u +/* SPI or UART (SPI | UART) */ +#define SCB5_SPI_UART 1u +/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, + CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only + 256 B are used. This is because the EZ mode uses 8-bit addresses. */ +#define SCB5_EZ_DATA_NR 256u +/* Command/response mode support? ('0': no, '1': yes) */ +#define SCB5_CMD_RESP 0u +/* EZ mode support? ('0': no, '1': yes) */ +#define SCB5_EZ 0u +/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ +#define SCB5_EZ_CMD_RESP 0u +/* I2C slave with EZ mode (I2C_S & EZ) */ +#define SCB5_I2C_S_EZ 0u +/* SPI slave with EZ mode (SPI_S & EZ) */ +#define SCB5_SPI_S_EZ 0u +/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ +#define SCB5_I2C_FAST_PLUS 1u +/* Number of used spi_select signals (max 4) */ +#define SCB5_CHIP_TOP_SPI_SEL_NR 4u +/* DeepSleep support ('0':no, '1': yes) */ +#define SCB6_DEEPSLEEP 1u +/* Externally clocked support? ('0': no, '1': yes) */ +#define SCB6_EC 1u +/* I2C master support? ('0': no, '1': yes) */ +#define SCB6_I2C_M 1u +/* I2C slave support? ('0': no, '1': yes) */ +#define SCB6_I2C_S 1u +/* I2C support? (I2C_M | I2C_S) */ +#define SCB6_I2C 1u +/* I2C glitch filters present? ('0': no, '1': yes) */ +#define SCB6_I2C_GLITCH 1u +/* I2C externally clocked support? ('0': no, '1': yes) */ +#define SCB6_I2C_EC 1u +/* I2C master and slave support? (I2C_M & I2C_S) */ +#define SCB6_I2C_M_S 1u +/* I2C slave with EC? (I2C_S & I2C_EC) */ +#define SCB6_I2C_S_EC 1u +/* SPI master support? ('0': no, '1': yes) */ +#define SCB6_SPI_M 1u +/* SPI slave support? ('0': no, '1': yes) */ +#define SCB6_SPI_S 1u +/* SPI support? (SPI_M | SPI_S) */ +#define SCB6_SPI 1u +/* SPI externally clocked support? ('0': no, '1': yes) */ +#define SCB6_SPI_EC 1u +/* SPI slave with EC? (SPI_S & SPI_EC) */ +#define SCB6_SPI_S_EC 1u +/* UART support? ('0': no, '1': yes) */ +#define SCB6_UART 0u +/* SPI or UART (SPI | UART) */ +#define SCB6_SPI_UART 1u +/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, + CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only + 256 B are used. This is because the EZ mode uses 8-bit addresses. */ +#define SCB6_EZ_DATA_NR 256u +/* Command/response mode support? ('0': no, '1': yes) */ +#define SCB6_CMD_RESP 1u +/* EZ mode support? ('0': no, '1': yes) */ +#define SCB6_EZ 1u +/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ +#define SCB6_EZ_CMD_RESP 1u +/* I2C slave with EZ mode (I2C_S & EZ) */ +#define SCB6_I2C_S_EZ 1u +/* SPI slave with EZ mode (SPI_S & EZ) */ +#define SCB6_SPI_S_EZ 1u +/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ +#define SCB6_I2C_FAST_PLUS 1u +/* Number of used spi_select signals (max 4) */ +#define SCB6_CHIP_TOP_SPI_SEL_NR 1u +/* Number of counters per IP (1..32) */ +#define TCPWM0_CNT_NR 4u +/* Counter width (in number of bits) */ +#define TCPWM0_CNT_CNT_WIDTH 32u +/* Number of counters per IP (1..32) */ +#define TCPWM1_CNT_NR 8u +/* Counter width (in number of bits) */ +#define TCPWM1_CNT_CNT_WIDTH 16u +/* Number of ports supoprting up to 4 COMs */ +#define LCD_NUMPORTS 8u +/* Number of ports supporting up to 8 COMs */ +#define LCD_NUMPORTS8 8u +/* Number of ports supporting up to 16 COMs */ +#define LCD_NUMPORTS16 0u +/* Max number of LCD commons supported */ +#define LCD_CHIP_TOP_COM_NR 8u +/* Max number of LCD pins (total) supported */ +#define LCD_CHIP_TOP_PIN_NR 60u +/* Number of IREF outputs from AREF */ +#define PASS_NR_IREFS 4u +/* Number of CTBs in the Subsystem */ +#define PASS_NR_CTBS 0u +/* Number of CTDACs in the Subsystem */ +#define PASS_NR_CTDACS 0u +/* CTB0 Exists */ +#define PASS_CTB0_EXISTS 0u +/* CTB1 Exists */ +#define PASS_CTB1_EXISTS 0u +/* CTB2 Exists */ +#define PASS_CTB2_EXISTS 0u +/* CTB3 Exists */ +#define PASS_CTB3_EXISTS 0u +/* CTDAC0 Exists */ +#define PASS_CTDAC0_EXISTS 0u +/* CTDAC1 Exists */ +#define PASS_CTDAC1_EXISTS 0u +/* CTDAC2 Exists */ +#define PASS_CTDAC2_EXISTS 0u +/* CTDAC3 Exists */ +#define PASS_CTDAC3_EXISTS 0u +/* Number of SAR channels */ +#define PASS_SAR_SAR_CHANNELS 16u +/* Averaging logic present in SAR */ +#define PASS_SAR_SAR_AVERAGE 1u +/* Range detect logic present in SAR */ +#define PASS_SAR_SAR_RANGEDET 1u +/* Support for UAB sampling */ +#define PASS_SAR_SAR_UAB 0u +#define PASS_CTBM_CTDAC_PRESENT 0u +/* Base address of the SMIF XIP memory region. This address must be a multiple of + the SMIF XIP memory capacity. This address must be a multiple of 64 KB. This + address must be in the [0x0000:0000, 0x1fff:ffff] memory region. The XIP + memory region should NOT overlap with other memory regions. */ +#define SMIF_SMIF_XIP_ADDR 402653184u +/* Capacity of the SMIF XIP memory region. The more significant bits of this + parameter must be '1' and the lesser significant bits of this paramter must + be '0'. E.g., 0xfff0:0000 specifies a 1 MB memory region. Legal values are + {0xffff:0000, 0xfffe:0000, 0xfffc:0000, 0xfff8:0000, 0xfff0:0000, + 0xffe0:0000, ..., 0xe000:0000}. */ +#define SMIF_SMIF_XIP_MASK 4160749568u +/* Cryptography (AES) support ('0' = no support, '1' = support) */ +#define SMIF_CRYPTO 1u +/* Number of external devices supported ([1,4]) */ +#define SMIF_DEVICE_NR 3u +/* External device write support. This is a 4-bit field. Each external device has + a dedicated bit. E.g., if bit 2 is '1', external device 2 has write support. */ +#define SMIF_DEVICE_WR_EN 15u +/* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ +#define SMIF_MASTER_WIDTH 8u +/* Chip top connect all 8 data pins (0= connect 4 or 6 data pins based on + DATA6_PRESENT, 1= connect 8 data pins) */ +#define SMIF_CHIP_TOP_DATA8_PRESENT 0u +/* Number of used spi_select signals (max 4) */ +#define SMIF_CHIP_TOP_SPI_SEL_NR 3u +/* Basically the max packet size, which gets double buffered in RAM 0: 512B + (implies 1KB of RAM space for data) 1: 1KB (implies 2KB of RAM space for + data) */ +#define SDHC_MAX_BLK_SIZE 0u +/* 0: No Command Queuing Engine present 1: Command Queuing Engine present; this + adds 288 bytes of space to the RAM for this purpose. */ +#define SDHC_CQE_PRESENT 0u +/* 0: no retention of any SDHC_CORE regs 1: retention of SDHC_CORE regs that have + the Retention flag (Note, CTL.ENABLE is always retained irrespective of this + parameter) */ +#define SDHC_RETENTION_PRESENT 1u +/* Basically the max packet size, which gets double buffered in RAM 0: 512B + (implies 1KB of RAM space for data) 1: 1KB (implies 2KB of RAM space for + data) */ +#define SDHC_CORE_MAX_BLK_SIZE 0u +/* 0: No Command Queuing Engine present 1: Command Queuing Engine present; this + adds 288 bytes of space to the RAM for this purpose. */ +#define SDHC_CORE_CQE_PRESENT 0u +/* 0: no retention of any SDHC_CORE regs 1: retention of SDHC_CORE regs that have + the Retention flag (Note, CTL.ENABLE is always retained irrespective of this + parameter) */ +#define SDHC_CORE_RETENTION_PRESENT 1u +/* Chip top connect all 8 data pins (0= connect 4 data pins, 1= connect 8 data + pins) */ +#define SDHC_CHIP_TOP_DATA8_PRESENT 0u +/* Chip top connect card_detect */ +#define SDHC_CHIP_TOP_CARD_DETECT_PRESENT 1u +/* Chip top connect card_mech_write_prot_in */ +#define SDHC_CHIP_TOP_CARD_WRITE_PROT_PRESENT 1u +/* Chip top connect led_ctrl_out and led_ctrl_out_en */ +#define SDHC_CHIP_TOP_LED_CTRL_PRESENT 0u +/* Chip top connect io_volt_sel_out and io_volt_sel_out_en */ +#define SDHC_CHIP_TOP_IO_VOLT_SEL_PRESENT 1u +/* Chip top connect io_drive_strength_out and io_drive_strength_out_en */ +#define SDHC_CHIP_TOP_IO_DRIVE_STRENGTH_PRESENT 0u +/* Chip top connect card_if_pwr_en_out and card_if_pwr_en_out_en */ +#define SDHC_CHIP_TOP_CARD_IF_PWR_EN_PRESENT 1u +/* Chip top connect card_emmc_reset_n_out and card_emmc_reset_n_out_en */ +#define SDHC_CHIP_TOP_CARD_EMMC_RESET_PRESENT 0u +/* Chip top connect interrupt_wakeup (not used for eMMC) */ +#define SDHC_CHIP_TOP_INTERRUPT_WAKEUP_PRESENT 1u +/* Number of TTCAN instances */ +#define CANFD_CAN_NR 1u +/* ECC logic present or not */ +#define CANFD_ECC_PRESENT 0u +/* address included in ECC logic or not */ +#define CANFD_ECC_ADDR_PRESENT 0u +/* Time Stamp counter present or not (required for instance 0, otherwise not + allowed) */ +#define CANFD_TS_PRESENT 1u +/* Message RAM size in KB */ +#define CANFD_MRAM_SIZE 4u +/* Message RAM address width */ +#define CANFD_MRAM_ADDR_WIDTH 10u + +/* MMIO Targets Defines */ +#define CY_MMIO_CRYPTO_GROUP_NR 1u +#define CY_MMIO_CRYPTO_SLAVE_NR 0u +#define CY_MMIO_CPUSS_GROUP_NR 2u +#define CY_MMIO_CPUSS_SLAVE_NR 0u +#define CY_MMIO_FAULT_GROUP_NR 2u +#define CY_MMIO_FAULT_SLAVE_NR 1u +#define CY_MMIO_IPC_GROUP_NR 2u +#define CY_MMIO_IPC_SLAVE_NR 2u +#define CY_MMIO_PROT_GROUP_NR 2u +#define CY_MMIO_PROT_SLAVE_NR 3u +#define CY_MMIO_FLASHC_GROUP_NR 2u +#define CY_MMIO_FLASHC_SLAVE_NR 4u +#define CY_MMIO_SRSS_GROUP_NR 2u +#define CY_MMIO_SRSS_SLAVE_NR 6u +#define CY_MMIO_BACKUP_GROUP_NR 2u +#define CY_MMIO_BACKUP_SLAVE_NR 7u +#define CY_MMIO_DW_GROUP_NR 2u +#define CY_MMIO_DW_SLAVE_NR 8u +#define CY_MMIO_DMAC_GROUP_NR 2u +#define CY_MMIO_DMAC_SLAVE_NR 10u +#define CY_MMIO_EFUSE_GROUP_NR 2u +#define CY_MMIO_EFUSE_SLAVE_NR 12u +#define CY_MMIO_HSIOM_GROUP_NR 3u +#define CY_MMIO_HSIOM_SLAVE_NR 0u +#define CY_MMIO_GPIO_GROUP_NR 3u +#define CY_MMIO_GPIO_SLAVE_NR 1u +#define CY_MMIO_SMARTIO_GROUP_NR 3u +#define CY_MMIO_SMARTIO_SLAVE_NR 2u +#define CY_MMIO_LPCOMP_GROUP_NR 3u +#define CY_MMIO_LPCOMP_SLAVE_NR 5u +#define CY_MMIO_CSD0_GROUP_NR 3u +#define CY_MMIO_CSD0_SLAVE_NR 6u +#define CY_MMIO_TCPWM0_GROUP_NR 3u +#define CY_MMIO_TCPWM0_SLAVE_NR 8u +#define CY_MMIO_TCPWM1_GROUP_NR 3u +#define CY_MMIO_TCPWM1_SLAVE_NR 9u +#define CY_MMIO_LCD0_GROUP_NR 3u +#define CY_MMIO_LCD0_SLAVE_NR 11u +#define CY_MMIO_USBFS0_GROUP_NR 3u +#define CY_MMIO_USBFS0_SLAVE_NR 15u +#define CY_MMIO_SMIF0_GROUP_NR 4u +#define CY_MMIO_SMIF0_SLAVE_NR 2u +#define CY_MMIO_SDHC0_GROUP_NR 4u +#define CY_MMIO_SDHC0_SLAVE_NR 6u +#define CY_MMIO_CANFD0_GROUP_NR 5u +#define CY_MMIO_CANFD0_SLAVE_NR 2u +#define CY_MMIO_SCB0_GROUP_NR 6u +#define CY_MMIO_SCB0_SLAVE_NR 0u +#define CY_MMIO_SCB1_GROUP_NR 6u +#define CY_MMIO_SCB1_SLAVE_NR 1u +#define CY_MMIO_SCB2_GROUP_NR 6u +#define CY_MMIO_SCB2_SLAVE_NR 2u +#define CY_MMIO_SCB3_GROUP_NR 6u +#define CY_MMIO_SCB3_SLAVE_NR 3u +#define CY_MMIO_SCB4_GROUP_NR 6u +#define CY_MMIO_SCB4_SLAVE_NR 4u +#define CY_MMIO_SCB5_GROUP_NR 6u +#define CY_MMIO_SCB5_SLAVE_NR 5u +#define CY_MMIO_SCB6_GROUP_NR 6u +#define CY_MMIO_SCB6_SLAVE_NR 6u +#define CY_MMIO_PASS_GROUP_NR 9u +#define CY_MMIO_PASS_SLAVE_NR 0u + +/* Backward compatibility definitions */ +#define CPUSS_IRQ_NR CPUSS_SYSTEM_INT_NR +#define CPUSS_DPSLP_IRQ_NR CPUSS_SYSTEM_DPSLP_INT_NR + +#endif /* _PSOC6_03_CONFIG_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_ble_clk.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_ble_clk.h index 47bd9b8793..c540486d6d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_ble_clk.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_ble_clk.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_ble_clk.h -* \version 3.10 +* \version 3.20 * * The header file of the BLE ECO clock driver. * @@ -41,7 +41,7 @@ * To configure the BLE ECO clock, call Cy_BLE_EcoConfigure(). * * The following code shows how to configure the BLE ECO clock: -* \snippet bleclk\3.0\snippet\main.c BLE ECO clock API: Cy_BLE_EcoConfigure() +* \snippet bleclk/snippet/main.c BLE ECO clock API: Cy_BLE_EcoConfigure() * * \section group_ble_clk_more_information More Information * See the BLE chapter of the device technical reference manual (TRM). @@ -70,6 +70,11 @@ * * * +* +* +* +* +* * * @@ -117,7 +122,7 @@ extern "C" { #define CY_BLE_CLK_DRV_VERSION_MAJOR (3) /** Driver minor version */ -#define CY_BLE_CLK_DRV_VERSION_MINOR (0) +#define CY_BLE_CLK_DRV_VERSION_MINOR (20) /** Driver ID */ #define CY_BLE_CLK_ID (0x05UL << 18U) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto.h index af3a29cd77..63df227059 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto.h -* \version 2.20 +* \version 2.30 * * \brief * This file provides the public interface for the Crypto driver. @@ -279,12 +279,34 @@ * scenarios, it brings little benefit in adding this to the affected * functions. * +* +* +* +* +* +* *
VersionChangesReason of Change
3.20Updated the Cy_BLE_EcoConfigure(): it stores the ECO frequency for possible frequency calculation by the Cy_SysClk_ClkHfGetFrequency().API enhancement.
3.10Updated the Cy_BLE_EcoConfigure() use case, when the voltageReg parameter is CY_BLE_ECO_VOLTAGE_REG_BLESSLDO * and the Buck core regulator is enabled.
20.6RThe macro offsetof, in library , shall not be used.The only HW block register offsets are defined using this macro.
* * \section group_crypto_changelog Changelog * * * +* +* +* +* +* * *
VersionChangesReason for Change
2.30 +*
    +*
  • Added a multi-instance support for AES and SHA.
    • +*
  • Added a small chunks mode for SHA with any chunk size (from one +* byte).
    • +*
  • Added the operation memory buffer management (set a new address, +* get a size).
    • +*
  • Added a support for ARM Compiler 6.
    • +*
+* 		Integration with mbedOS/mbedTLS, restructured the implementation of +* AES and SHA for the Crypto ALT interface. +*
2.20 *
    @@ -549,7 +571,7 @@ * to the server context (cy_stc_crypto_server_context_t) that will be used to * store all temporary data. * -* \snippet crypto/2.10/snippet/main.c snippet_myCryptoServerStartBase +* \snippet crypto/snippet/main.c snippet_myCryptoServerStartBase * * Because the two cores operate asynchronously, ensure that server * initialization is complete before initializing the client. @@ -577,7 +599,7 @@ * These calls must be made on the client side. * Firmware can implement the client on either core. * -* \snippet crypto/2.10/snippet/main.c snippet_myCryptoInit +* \snippet crypto/snippet/main.c snippet_myCryptoInit * * \section group_crypto_common_use_cases Common Use Cases * @@ -588,7 +610,7 @@ * - Call \ref Cy_Crypto_Crc_Run to calculate CRC for a data image. * * Code example: -* \snippet crypto/2.10/snippet/main.c snippet_myCryptoCrcUse +* \snippet crypto/snippet/main.c snippet_myCryptoCrcUse * * \subsection group_crypto_Use_PRNG Pseudo Random Number Generation * @@ -597,7 +619,7 @@ * - Call \ref Cy_Crypto_Prng_Generate. * * Code example: -* \snippet crypto/2.10/snippet/main.c snippet_myCryptoPrngUse +* \snippet crypto/snippet/main.c snippet_myCryptoPrngUse * * \subsection group_crypto_Use_TRNG True Random Number Generation * @@ -605,7 +627,7 @@ * - Call \ref Cy_Crypto_Trng_Generate with needed parameters. * * Code example: -* \snippet crypto/2.10/snippet/main.c snippet_myCryptoTrngUse +* \snippet crypto/snippet/main.c snippet_myCryptoTrngUse * * \subsection group_crypto_Use_DES DES encryption * @@ -615,7 +637,7 @@ * array * * Code example: -* \snippet crypto/2.10/snippet/main.c snippet_myCryptoDesUse +* \snippet crypto/snippet/main.c snippet_myCryptoDesUse * * \subsection group_crypto_Use_TDES TDES encryption * @@ -625,7 +647,7 @@ * of keys * * Code example: -* \snippet crypto/2.10/snippet/main.c snippet_myCryptoTdesUse +* \snippet crypto/snippet/main.c snippet_myCryptoTdesUse * * \subsection group_crypto_Use_AES AES encryption * @@ -640,7 +662,7 @@ * parameters to make an operation * * Code example: -* \snippet crypto/2.10/snippet/main.c snippet_myCryptoAesEcbUse +* \snippet crypto/snippet/main.c snippet_myCryptoAesEcbUse * * \subsection group_crypto_Use_SHA SHA digest calculation * @@ -649,7 +671,7 @@ * operation * * Code example: -* \snippet crypto/2.10/snippet/main.c snippet_myCryptoSha256Use +* \snippet crypto/snippet/main.c snippet_myCryptoSha256Use * * \subsection group_crypto_Use_CMAC CMAC calculation * @@ -660,7 +682,7 @@ * operation * * Code example: -* \snippet crypto/2.10/snippet/main.c snippet_myCryptoCmacUse +* \snippet crypto/snippet/main.c snippet_myCryptoCmacUse * * \subsection group_crypto_Use_HMAC HMAC calculation * @@ -670,7 +692,7 @@ * operation * * Code example: -* \snippet crypto/2.10/snippet/main.c snippet_myCryptoHmacUse +* \snippet crypto/snippet/main.c snippet_myCryptoHmacUse * * \subsection group_crypto_Use_RSA_VER RSA signature verification * @@ -682,7 +704,7 @@ * calculated SHA digest * * Code example: -* \snippet crypto/2.10/snippet/main.c snippet_myCryptoRsaVerUse +* \snippet crypto/snippet/main.c snippet_myCryptoRsaVerUse * * \section group_crypto_rsa_considerations RSA Usage Considerations * @@ -699,7 +721,7 @@ * * \note The modulus and exponent values in the * \ref cy_stc_crypto_rsa_pub_key_t must be in little-endian order.
    -* Use the \ref Cy_Crypto_Rsa_InvertEndianness function to convert to or from +* Use the \ref Cy_Crypto_InvertEndianness function to convert to or from * little-endian order. * * The remaining fields represent three pre-calculated coefficients that can @@ -722,11 +744,11 @@ * -# Calculate the SHA digest of the data to be verified with * \ref Cy_Crypto_Sha_Run. * -# Ensure that the RSA signature is in little-endian format. -* Use \ref Cy_Crypto_Rsa_InvertEndianness. +* Use \ref Cy_Crypto_InvertEndianness. * -# Decrypt the RSA signature with a public key, by calling * \ref Cy_Crypto_Rsa_Proc. * -# Invert the byte order of the output, to return to big-endian format. -* Use \ref Cy_Crypto_Rsa_InvertEndianness. +* Use \ref Cy_Crypto_InvertEndianness. * -# Call \ref Cy_Crypto_Rsa_Verify (which requires data in big-endian format). * * \section group_crypto_irq_implements Implementing Crypto Interrupts @@ -830,7 +852,7 @@ cy_en_crypto_status_t Cy_Crypto_GetLibraryInfo(cy_en_crypto_lib_info_t *cryptoIn * \ref cy_en_crypto_status_t * * \funcusage -* \snippet crypto/2.10/snippet/main.c snippet_myCryptoInit +* \snippet crypto/snippet/main.c snippet_myCryptoInit * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Init(cy_stc_crypto_config_t const *config, cy_stc_crypto_context_t *context); @@ -934,7 +956,7 @@ cy_en_crypto_status_t Cy_Crypto_GetErrorStatus(cy_stc_crypto_hw_error_t *hwError * \ref cy_en_crypto_status_t * * \funcusage -* \snippet crypto/2.10/snippet/main.c snippet_myCryptoPrngUse +* \snippet crypto/snippet/main.c snippet_myCryptoPrngUse * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Prng_Init(uint32_t lfsr32InitState, @@ -964,7 +986,7 @@ cy_en_crypto_status_t Cy_Crypto_Prng_Init(uint32_t lfsr32InitState, * \ref cy_en_crypto_status_t * * \funcusage -* \snippet crypto/2.10/snippet/main.c snippet_myCryptoPrngUse +* \snippet crypto/snippet/main.c snippet_myCryptoPrngUse * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Prng_Generate(uint32_t max, @@ -997,7 +1019,7 @@ cy_en_crypto_status_t Cy_Crypto_Prng_Generate(uint32_t max, * \ref cy_en_crypto_status_t * * \funcusage -* \snippet crypto/2.10/snippet/main.c snippet_myCryptoAesEcbUse +* \snippet crypto/snippet/main.c snippet_myCryptoAesEcbUse * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Aes_Init(uint32_t *key, @@ -1030,7 +1052,7 @@ cy_en_crypto_status_t Cy_Crypto_Aes_Init(uint32_t *key, * \ref cy_en_crypto_status_t * * \funcusage -* \snippet crypto/2.10/snippet/main.c snippet_myCryptoAesEcbUse +* \snippet crypto/snippet/main.c snippet_myCryptoAesEcbUse * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Aes_Ecb_Run(cy_en_crypto_dir_mode_t dirMode, @@ -1197,7 +1219,7 @@ cy_en_crypto_status_t Cy_Crypto_Aes_Ctr_Run(cy_en_crypto_dir_mode_t dirMode, * \ref cy_en_crypto_status_t * * \funcusage -* \snippet crypto/2.10/snippet/main.c snippet_myCryptoCmacUse +* \snippet crypto/snippet/main.c snippet_myCryptoCmacUse * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Aes_Cmac_Run(uint32_t *src, @@ -1242,7 +1264,7 @@ cy_en_crypto_status_t Cy_Crypto_Aes_Cmac_Run(uint32_t *src, * \ref cy_en_crypto_status_t * * \funcusage -* \snippet crypto/2.10/snippet/main.c snippet_myCryptoSha256Use +* \snippet crypto/snippet/main.c snippet_myCryptoSha256Use * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Sha_Run(uint32_t *message, @@ -1290,7 +1312,7 @@ cy_en_crypto_status_t Cy_Crypto_Sha_Run(uint32_t *message, * \ref cy_en_crypto_status_t * * \funcusage -* \snippet crypto/2.10/snippet/main.c snippet_myCryptoHmacUse +* \snippet crypto/snippet/main.c snippet_myCryptoHmacUse * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Hmac_Run(uint32_t *hmac, @@ -1558,7 +1580,7 @@ cy_en_crypto_status_t Cy_Crypto_Str_MemXor(void const *src0, * Calculated CRC value is MSB aligned only when dataReverse is zero. * * \funcusage -* \snippet crypto/2.10/snippet/main.c snippet_myCryptoCrcUse +* \snippet crypto/snippet/main.c snippet_myCryptoCrcUse * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Crc_Init(uint32_t polynomial, @@ -1601,7 +1623,7 @@ cy_en_crypto_status_t Cy_Crypto_Crc_Init(uint32_t polynomial, * Calculated CRC value is MSB aligned only when dataReverse is zero. * * \funcusage -* \snippet crypto/2.10/snippet/main.c snippet_myCryptoCrcUse +* \snippet crypto/snippet/main.c snippet_myCryptoCrcUse * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Crc_Run(void *data, @@ -1638,7 +1660,7 @@ cy_en_crypto_status_t Cy_Crypto_Crc_Run(void *data, * \ref cy_en_crypto_status_t * * \funcusage -* \snippet crypto/2.10/snippet/main.c snippet_myCryptoTrngUse +* \snippet crypto/snippet/main.c snippet_myCryptoTrngUse * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Trng_Generate(uint32_t GAROPol, @@ -1717,7 +1739,7 @@ cy_en_crypto_status_t Cy_Crypto_Des_Run(cy_en_crypto_dir_mode_t dirMode, * \ref cy_en_crypto_status_t * * \funcusage -* \snippet crypto/2.10/snippet/main.c snippet_myCryptoTdesUse +* \snippet crypto/snippet/main.c snippet_myCryptoTdesUse * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Tdes_Run(cy_en_crypto_dir_mode_t dirMode, @@ -1755,7 +1777,7 @@ cy_en_crypto_status_t Cy_Crypto_Tdes_Run(cy_en_crypto_dir_mode_t dirMode, * little-endian order.
    * The modulus and exponent values in the \ref cy_stc_crypto_rsa_pub_key_t * must also be in little-endian order.
    -* Use \ref Cy_Crypto_Rsa_InvertEndianness function to convert to or from +* Use \ref Cy_Crypto_InvertEndianness function to convert to or from * little-endian order. * * \param pubKey @@ -1870,10 +1892,145 @@ cy_en_crypto_status_t Cy_Crypto_Rsa_Verify(cy_en_crypto_rsa_ver_result_t *verRes cy_stc_crypto_context_rsa_ver_t *cfContext); #endif /* #if (CPUSS_CRYPTO_SHA == 1) */ +/******************************************************************************* +* Function Name: Cy_Crypto_ECDSA_SignHash +****************************************************************************//** +* +* Sign a message digest. +* +* \param hash +* The message digest to sign. Provided as is in data buffer. +* +* \param hashlen +* The length of the digest in bytes. +* +* \param sig +* [out] The destination for the signature, 'R' followed by 'S'. +* +* \param key +* Key used for signature generation. See \ref cy_stc_crypto_ecc_key. +* +* \param messageKey +* Message key. +* +* \param cfContext +* The pointer to the \ref cy_stc_crypto_context_ecc_t structure that stores +* the ECC operation context. +* +* \return status code. See \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_ECDSA_SignHash(const uint8_t *hash, + uint32_t hashlen, + uint8_t *sig, + const cy_stc_crypto_ecc_key *key, + const uint8_t *messageKey, + cy_stc_crypto_context_ecc_t *cfContext); + +/******************************************************************************* +* Function Name: Cy_Crypto_ECDSA_VerifyHash +****************************************************************************//** +* +* Verify an ECC signature. +* +* \param sig +* The signature to verify, 'R' followed by 'S'. +* +* \param hash +* The message digest that was signed. Provided as is in data buffer. +* +* \param hashlen +* The length of the digest in bytes. +* +* \param stat +* Result of signature, 1==valid, 0==invalid. +* +* \param key +* The corresponding public ECC key. See \ref cy_stc_crypto_ecc_key. +* +* \param cfContext +* The pointer to the \ref cy_stc_crypto_context_ecc_t structure that stores +* the ECC operation context. +* +* \return status code. See \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_ECDSA_VerifyHash(const uint8_t *sig, + const uint8_t *hash, + uint32_t hashlen, + uint8_t *stat, + const cy_stc_crypto_ecc_key *key, + cy_stc_crypto_context_ecc_t *cfContext); + #endif /* #if (CPUSS_CRYPTO_VU == 1) */ /******************************************************************************* -* Function Name: Cy_Crypto_Rsa_InvertEndianness +* Function Name: Cy_Crypto_SetMemBufAddress +****************************************************************************//** +* +* This function sets a new operation memory buffer. +* +* \param newMembufAddress +* The pointer to the new operation memory buffer. +* __Must be 4-byte aligned.__ +* +* \param newMembufSize +* The size of the new memory buffer (in bytes) +* +* \param cfContext +* The pointer to the \ref cy_stc_crypto_context_str_t structure that stores +* the data context. +* +* \return +* \ref cy_en_crypto_status_t +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_SetMemBufAddress(uint32_t const *newMembufAddress, + uint32_t newMembufSize, + cy_stc_crypto_context_str_t *cfContext); + +/******************************************************************************* +* Function Name: Cy_Crypto_GetMemBufAddress +****************************************************************************//** +* +* This function gets an operation memory buffer location. +* +* \param membufAddress +* The pointer of the operation memory buffer. +* +* \param cfContext +* The pointer to the \ref cy_stc_crypto_context_str_t structure that stores +* the data context. +* +* \return +* \ref cy_en_crypto_status_t +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_GetMemBufAddress(uint32_t **membufAddress, + cy_stc_crypto_context_str_t *cfContext); + +/******************************************************************************* +* Function Name: Cy_Crypto_GetMemBufSize +****************************************************************************//** +* +* This function gets an operation memory buffer size. +* +* \param membufSize +* The size of the memory buffer (in bytes) +* +* \param cfContext +* The pointer to the \ref cy_stc_crypto_context_str_t structure that stores +* the data context. +* +* \return +* \ref cy_en_crypto_status_t +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_GetMemBufSize(uint32_t *membufSize, + cy_stc_crypto_context_str_t *cfContext); + +/******************************************************************************* +* Function Name: Cy_Crypto_InvertEndianness ****************************************************************************//** * * This function reverts byte-array memory block, like:
    @@ -1892,7 +2049,12 @@ cy_en_crypto_status_t Cy_Crypto_Rsa_Verify(cy_en_crypto_rsa_ver_result_t *verRes * The length of the memory array whose endianness is to be inverted (in bytes) * *******************************************************************************/ -void Cy_Crypto_Rsa_InvertEndianness(void *inArrPtr, uint32_t byteSize); +void Cy_Crypto_InvertEndianness(void *inArrPtr, uint32_t byteSize); + +/** \cond INTERNAL */ +/* For backward compatibility */ +#define Cy_Crypto_Rsa_InvertEndianness(p, s) Cy_Crypto_InvertEndianness((p), (s)) +/** \endcond */ /** \} group_crypto_cli_functions */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_common.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_common.h index 1fe68ef5e2..1217015b94 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_common.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_common.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_common.h -* \version 2.20 +* \version 2.30 * * \brief * This file provides common constants and parameters @@ -57,7 +57,7 @@ #define CY_CRYPTO_DRV_VERSION_MAJOR 2 /** Driver minor version */ -#define CY_CRYPTO_DRV_VERSION_MINOR 20 +#define CY_CRYPTO_DRV_VERSION_MINOR 30 /** * \addtogroup group_crypto_cli_srv_macros @@ -91,8 +91,11 @@ /** Defines the Crypto AES_256 key maximum size (in bytes) */ #define CY_CRYPTO_AES_256_KEY_SIZE (32u) +/** Defines the Crypto AES key maximum size (in bytes) */ +#define CY_CRYPTO_AES_MAX_KEY_SIZE (CY_CRYPTO_AES_256_KEY_SIZE) + /** Defines the Crypto AES_256 key maximum size (in four-byte words) */ -#define CY_CRYPTO_AES_256_KEY_SIZE_U32 (32u) +#define CY_CRYPTO_AES_MAX_KEY_SIZE_U32 (uint32_t)(CY_CRYPTO_AES_MAX_KEY_SIZE / 4ul) /** Defines size of the AES block, in four-byte words */ #define CY_CRYPTO_AES_BLOCK_SIZE_U32 (uint32_t)(CY_CRYPTO_AES_BLOCK_SIZE / 4ul) @@ -144,6 +147,12 @@ /* The width of the Crypto hardware registers values in bits. */ #define CY_CRYPTO_HW_REGS_WIDTH (32UL) +/* Calculates the actual size in bytes of the bits value */ +#define CY_CRYPTO_BYTE_SIZE_OF_BITS(x) (uint32_t)(((uint32_t)(x) + 7u) >> 3u) + +/* Calculates the actual size in 32-bit words of the bits value */ +#define CY_CRYPTO_WORD_SIZE_OF_BITS(x) (uint32_t)(((uint32_t)(x) + 31u) >> 5u) + /** \endcond */ #endif /* #if (CPUSS_CRYPTO_SHA == 1) */ @@ -152,11 +161,15 @@ #if (CPUSS_CRYPTO_VU == 1) /** Processed message size for the RSA 1024Bit mode (in bytes) */ -#define CY_CRYPTO_RSA1024_MESSAGE_SIZE (128) +#define CY_CRYPTO_RSA1024_MESSAGE_SIZE CY_CRYPTO_BYTE_SIZE_OF_BITS(1024u) /** Processed message size for the RSA 1536Bit mode (in bytes) */ -#define CY_CRYPTO_RSA1536_MESSAGE_SIZE (192) +#define CY_CRYPTO_RSA1536_MESSAGE_SIZE CY_CRYPTO_BYTE_SIZE_OF_BITS(1536u) /** Processed message size for the RSA 2048Bit mode (in bytes) */ -#define CY_CRYPTO_RSA2048_MESSAGE_SIZE (256) +#define CY_CRYPTO_RSA2048_MESSAGE_SIZE CY_CRYPTO_BYTE_SIZE_OF_BITS(2048u) +/** Processed message size for the RSA 3072Bit mode (in bytes) */ +#define CY_CRYPTO_RSA3072_MESSAGE_SIZE CY_CRYPTO_BYTE_SIZE_OF_BITS(3072u) +/** Processed message size for the RSA 4096Bit mode (in bytes) */ +#define CY_CRYPTO_RSA4096_MESSAGE_SIZE CY_CRYPTO_BYTE_SIZE_OF_BITS(4096u) #endif /* #if (CPUSS_CRYPTO_VU == 1) */ @@ -261,7 +274,7 @@ typedef struct * * \note The modulus and exponent values in the * \ref cy_stc_crypto_rsa_pub_key_t must also be in little-endian order.
    -* Use \ref Cy_Crypto_Rsa_InvertEndianness function to convert to or from +* Use \ref Cy_Crypto_InvertEndianness function to convert to or from * little-endian order. */ typedef struct @@ -434,6 +447,25 @@ typedef enum /** \} group_crypto_enums */ +/** +* \addtogroup group_crypto_lld_asymmetric_enums +* \{ +*/ + +/** List of supported elliptic curve IDs */ +typedef enum { + CY_CRYPTO_ECC_ECP_NONE = 0, + CY_CRYPTO_ECC_ECP_SECP192R1, + CY_CRYPTO_ECC_ECP_SECP224R1, + CY_CRYPTO_ECC_ECP_SECP256R1, + CY_CRYPTO_ECC_ECP_SECP384R1, + CY_CRYPTO_ECC_ECP_SECP521R1, + /* Count of supported curves */ + CY_CRYPTO_ECC_ECP_CURVES_CNT +} cy_en_crypto_ecc_curve_id_t; + +/** \} group_crypto_lld_asymmetric_enums */ + /** \cond INTERNAL */ /** Instruction to communicate between Client and Server */ @@ -496,7 +528,22 @@ typedef enum CY_CRYPTO_INSTR_RSA_VER = 0x19u, #endif /* #if (CPUSS_CRYPTO_SHA == 1) */ - CY_CRYPTO_INSTR_SRV_INFO = 0x55u + CY_CRYPTO_INSTR_SRV_INFO = 0x55u, + +#if (CPUSS_CRYPTO_VU == 1) + CY_CRYPTO_INSTR_MEMBUF_SET = 0x56u, + CY_CRYPTO_INSTR_MEMBUF_ADDR = 0x57u, + CY_CRYPTO_INSTR_MEMBUF_SIZE = 0x58u, + + CY_CRYPTO_INSTR_ECC_GET_DP = 0x59u, + CY_CRYPTO_INSTR_ECC_ECP_MUL = 0x5Au, + CY_CRYPTO_INSTR_ECP_GEN_PRIK = 0x5Bu, + CY_CRYPTO_INSTR_ECP_GEN_PUBK = 0x5Cu, + + CY_CRYPTO_INSTR_ECDSA_SIGN = 0x5Du, + CY_CRYPTO_INSTR_ECDSA_VER = 0x5Eu +#endif /* #if (CPUSS_CRYPTO_VU == 1) */ + } cy_en_crypto_comm_instr_t; /** \endcond */ @@ -515,17 +562,26 @@ typedef enum * ensure that the defined instance of this structure remains in scope * while the drive is in use. */ + +/* The structure to define used memory buffers */ +typedef struct +{ + /** \cond INTERNAL */ + uint32_t key[CY_CRYPTO_AES_MAX_KEY_SIZE_U32]; + uint32_t keyInv[CY_CRYPTO_AES_MAX_KEY_SIZE_U32]; + uint32_t block0[CY_CRYPTO_AES_BLOCK_SIZE_U32]; + uint32_t block1[CY_CRYPTO_AES_BLOCK_SIZE_U32]; + uint32_t block2[CY_CRYPTO_AES_BLOCK_SIZE_U32]; + /** \endcond */ +} cy_stc_crypto_aes_buffers_t; + typedef struct { /** \cond INTERNAL */ - /** Pointer to AES key */ - uint8_t *key; - /** Pointer to AES inverse key */ - uint8_t *invKey; /** AES key length */ cy_en_crypto_aes_key_length_t keyLength; /** Pointer to AES work buffers */ - uint32_t *buffers; + cy_stc_crypto_aes_buffers_t *buffers; /** AES processed block index (for CMAC, SHA operations) */ uint32_t blockIdx; /** \endcond */ @@ -545,6 +601,7 @@ typedef struct { /** \cond INTERNAL */ uint32_t mode; + uint32_t modeHw; uint8_t *block; uint32_t blockSize; uint8_t *hash; @@ -560,6 +617,32 @@ typedef struct #endif /* (CPUSS_CRYPTO_SHA == 1) */ +/** A point on a ECC curve */ +typedef struct { + /** The x co-ordinate */ + void *x; + /** The y co-ordinate */ + void *y; +} cy_stc_crypto_ecc_point; + +/** An ECC key type */ +typedef enum cy_en_crypto_ecc_key_type { + PK_PUBLIC = 0u, + PK_PRIVATE = 1u +} cy_en_crypto_ecc_key_type_t; + +/** An ECC key */ +typedef struct { + /** Type of key, PK_PRIVATE or PK_PUBLIC */ + cy_en_crypto_ecc_key_type_t type; + /** See \ref cy_en_crypto_ecc_curve_id_t */ + cy_en_crypto_ecc_curve_id_t curveID; + /** The public key */ + cy_stc_crypto_ecc_point pubkey; + /** The private key */ + void *k; +} cy_stc_crypto_ecc_key; + /** \} group_crypto_data_structures */ /************************************************************* @@ -872,6 +955,35 @@ typedef struct uint32_t *result; /** \endcond */ } cy_stc_crypto_context_rsa_t; + +/** The structure for storing the ECC operations context. +* All fields for the context structure are internal. Firmware never reads or +* writes these values. Firmware allocates the structure and provides the +* address of the structure to the driver in function calls. Firmware must +* ensure that the defined instance of this structure remains in scope +* while the drive is in use. +*/ +typedef struct +{ + /** \cond INTERNAL */ + /** Elliptic curve ID */ + cy_en_crypto_ecc_curve_id_t curveID; + /** Pointer to key data */ + const cy_stc_crypto_ecc_key *key; + /** Operation data length */ + uint32_t datalen; + /** Pointer to the first source data block */ + const uint8_t *src0; + /** Pointer to the second source data block */ + const uint8_t *src1; + /** Pointer to the third source data block */ + const uint8_t *src2; + /** Pointer to the first destination data block */ + uint8_t *dst0; + /** Pointer to the second destination data block */ + uint8_t *dst1; + /** \endcond */ +} cy_stc_crypto_context_ecc_t; #endif /* #if (CPUSS_CRYPTO_VU == 1) */ /** \} group_crypto_cli_data_structures */ @@ -880,4 +992,5 @@ typedef struct #endif /* #if !defined(CY_CRYPTO_COMMON_H) */ + /* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core.h index 31c67a5bfb..bc91323b6f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core.h -* \version 2.20 +* \version 2.30 * * \brief * This file provides common constants and parameters diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_aes.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_aes.h index 0f6e960941..b2acf7ada0 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_aes.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_aes.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_aes.h -* \version 2.20 +* \version 2.30 * * \brief * This file provides constant and parameters for the API for the AES method @@ -35,11 +35,13 @@ #include "cy_crypto_core_aes_v1.h" #include "cy_crypto_core_aes_v2.h" +#include "cy_crypto_core_hw.h" typedef cy_en_crypto_status_t (*cy_crypto_aes_init_func_t)(CRYPTO_Type *base, uint8_t const *key, cy_en_crypto_aes_key_length_t keyLength, - cy_stc_crypto_aes_state_t *aesState); + cy_stc_crypto_aes_state_t *aesState, + cy_stc_crypto_aes_buffers_t *aesBuffers); typedef cy_en_crypto_status_t (*cy_crypto_aes_ecb_func_t)(CRYPTO_Type *base, cy_en_crypto_dir_mode_t dirMode, @@ -50,7 +52,7 @@ typedef cy_en_crypto_status_t (*cy_crypto_aes_ecb_func_t)(CRYPTO_Type *base, typedef cy_en_crypto_status_t (*cy_crypto_aes_cbc_func_t)(CRYPTO_Type *base, cy_en_crypto_dir_mode_t dirMode, uint32_t srcSize, - uint8_t const *ivPtr, + uint8_t *ivPtr, uint8_t *dst, uint8_t const *src, cy_stc_crypto_aes_state_t *aesState); @@ -58,7 +60,7 @@ typedef cy_en_crypto_status_t (*cy_crypto_aes_cbc_func_t)(CRYPTO_Type *base, typedef cy_en_crypto_status_t (*cy_crypto_aes_cfb_func_t)(CRYPTO_Type *base, cy_en_crypto_dir_mode_t dirMode, uint32_t srcSize, - uint8_t const *ivPtr, + uint8_t *ivPtr, uint8_t *dst, uint8_t const *src, cy_stc_crypto_aes_state_t *aesState); @@ -107,13 +109,95 @@ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Aes_Init(CRYPTO_Type *base, { cy_en_crypto_status_t tmpResult; - if (CY_CRYPTO_HW_V1) + cy_stc_crypto_aes_buffers_t *aesBuffers = (cy_stc_crypto_aes_buffers_t *)Cy_Crypto_Core_GetVuMemoryAddress(base); + + if (CY_CRYPTO_V1) { - tmpResult = Cy_Crypto_Core_V1_Aes_Init(base, key, keyLength, aesState); + tmpResult = Cy_Crypto_Core_V1_Aes_Init(base, key, keyLength, aesState, aesBuffers); } else { - tmpResult = Cy_Crypto_Core_V2_Aes_Init(base, key, keyLength, aesState); + tmpResult = Cy_Crypto_Core_V2_Aes_Init(base, key, keyLength, aesState, aesBuffers); + } + + return tmpResult; +} + +/******************************************************************************* +* Function Name: Cy_Crypto_Core_Aes_InitContext +****************************************************************************//** +* +* Initializes AES mode of operation and prepares an inverse key. +* +* \param base +* The pointer to the CRYPTO instance. +* +* \param key +* The pointer to the encryption/decryption key. +* +* \param keyLength +* \ref cy_en_crypto_aes_key_length_t +* +* \param aesState +* The pointer to the AES state structure allocated by the user. The user +* must not modify anything in this structure. +* +* \param aesBuffers +* The pointer to the memory buffers storage. +* +* \return +* \ref cy_en_crypto_status_t +* +*******************************************************************************/ +__STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Aes_InitContext(CRYPTO_Type *base, + uint8_t const *key, + cy_en_crypto_aes_key_length_t keyLength, + cy_stc_crypto_aes_state_t *aesState, + cy_stc_crypto_aes_buffers_t *aesBuffers) +{ + cy_en_crypto_status_t tmpResult; + + if (CY_CRYPTO_V1) + { + tmpResult = Cy_Crypto_Core_V1_Aes_Init(base, key, keyLength, aesState, aesBuffers); + } + else + { + tmpResult = Cy_Crypto_Core_V2_Aes_Init(base, key, keyLength, aesState, aesBuffers); + } + + return tmpResult; +} + +/******************************************************************************* +* Function Name: Cy_Crypto_Core_Aes_Free +****************************************************************************//** +* +* Clears AES operation context. +* +* \param base +* The pointer to the CRYPTO instance. +* +* \param aesState +* The pointer to the AES state structure allocated by the user. The user +* must not modify anything in this structure. +* +* \return +* \ref cy_en_crypto_status_t +* +*******************************************************************************/ +__STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Aes_Free(CRYPTO_Type *base, + cy_stc_crypto_aes_state_t *aesState) +{ + cy_en_crypto_status_t tmpResult; + + if (CY_CRYPTO_V1) + { + tmpResult = Cy_Crypto_Core_V1_Aes_Free(base, aesState); + } + else + { + tmpResult = Cy_Crypto_Core_V2_Aes_Free(base, aesState); } return tmpResult; @@ -154,7 +238,7 @@ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Aes_Ecb(CRYPTO_Type *base, { cy_en_crypto_status_t tmpResult; - if (CY_CRYPTO_HW_V1) + if (CY_CRYPTO_V1) { tmpResult = Cy_Crypto_Core_V1_Aes_Ecb(base, dirMode, dst, src, aesState); } @@ -203,14 +287,14 @@ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Aes_Ecb(CRYPTO_Type *base, __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Aes_Cbc(CRYPTO_Type *base, cy_en_crypto_dir_mode_t dirMode, uint32_t srcSize, - uint8_t const *ivPtr, + uint8_t *ivPtr, uint8_t *dst, uint8_t const *src, cy_stc_crypto_aes_state_t *aesState) { cy_en_crypto_status_t tmpResult; - if (CY_CRYPTO_HW_V1) + if (CY_CRYPTO_V1) { tmpResult = Cy_Crypto_Core_V1_Aes_Cbc(base, dirMode, srcSize, ivPtr, dst, src, aesState); } @@ -259,14 +343,14 @@ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Aes_Cbc(CRYPTO_Type *base, __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Aes_Cfb(CRYPTO_Type *base, cy_en_crypto_dir_mode_t dirMode, uint32_t srcSize, - uint8_t const *ivPtr, + uint8_t *ivPtr, uint8_t *dst, uint8_t const *src, cy_stc_crypto_aes_state_t *aesState) { cy_en_crypto_status_t tmpResult; - if (CY_CRYPTO_HW_V1) + if (CY_CRYPTO_V1) { tmpResult = Cy_Crypto_Core_V1_Aes_Cfb(base, dirMode, srcSize, ivPtr, dst, src, aesState); } @@ -295,7 +379,7 @@ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Aes_Cfb(CRYPTO_Type *base, * current cipher stream. * * \param ivPtr -* The 128-bit nonce and counter. +* The 128-bit initial vector that contains a 64-bit nonce and 64-bit counter. * * \param streamBlock * The saved stream-block for resuming. Is over-written by the function. @@ -325,7 +409,7 @@ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Aes_Ctr(CRYPTO_Type *base, { cy_en_crypto_status_t tmpResult; - if (CY_CRYPTO_HW_V1) + if (CY_CRYPTO_V1) { tmpResult = Cy_Crypto_Core_V1_Aes_Ctr(base, srcSize, srcOffset, ivPtr, streamBlock, dst, src, aesState); } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_aes_v1.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_aes_v1.h index c170a613b5..aacfbab358 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_aes_v1.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_aes_v1.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_aes_v1.h -* \version 2.20 +* \version 2.30 * * \brief * This file provides constant and parameters for the API for the AES method @@ -35,21 +35,6 @@ #include "cy_syslib.h" -/** \cond INTERNAL */ - -/* The structure to define used memory buffers */ -typedef struct -{ - uint32_t key[CY_CRYPTO_AES_256_KEY_SIZE_U32]; - uint32_t keyInv[CY_CRYPTO_AES_256_KEY_SIZE_U32]; - uint32_t block0[CY_CRYPTO_AES_BLOCK_SIZE_U32]; - uint32_t block1[CY_CRYPTO_AES_BLOCK_SIZE_U32]; - uint32_t block2[CY_CRYPTO_AES_BLOCK_SIZE_U32]; - uint32_t iv[CY_CRYPTO_AES_BLOCK_SIZE_U32]; -} cy_stc_crypto_aes_buffers_t; - -/** \endcond */ - void Cy_Crypto_Core_V1_Aes_ProcessBlock(CRYPTO_Type *base, cy_stc_crypto_aes_state_t const *aesState, cy_en_crypto_dir_mode_t dirMode, @@ -62,12 +47,13 @@ void Cy_Crypto_Core_V1_Aes_Xor(CRYPTO_Type *base, uint32_t const *src0Block, uint32_t const *src1Block); -void Cy_Crypto_Core_V1_Aes_Free(CRYPTO_Type *base); +cy_en_crypto_status_t Cy_Crypto_Core_V1_Aes_Free(CRYPTO_Type *base, cy_stc_crypto_aes_state_t *aesState); cy_en_crypto_status_t Cy_Crypto_Core_V1_Aes_Init(CRYPTO_Type *base, uint8_t const *key, cy_en_crypto_aes_key_length_t keyLength, - cy_stc_crypto_aes_state_t *aesState); + cy_stc_crypto_aes_state_t *aesState, + cy_stc_crypto_aes_buffers_t *aesBuffers); cy_en_crypto_status_t Cy_Crypto_Core_V1_Aes_Ecb(CRYPTO_Type *base, cy_en_crypto_dir_mode_t dirMode, @@ -78,7 +64,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Aes_Ecb(CRYPTO_Type *base, cy_en_crypto_status_t Cy_Crypto_Core_V1_Aes_Cbc(CRYPTO_Type *base, cy_en_crypto_dir_mode_t dirMode, uint32_t srcSize, - uint8_t const *ivPtr, + uint8_t *ivPtr, uint8_t *dst, uint8_t const *src, cy_stc_crypto_aes_state_t *aesState); @@ -87,7 +73,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Aes_Cbc(CRYPTO_Type *base, cy_en_crypto_status_t Cy_Crypto_Core_V1_Aes_Cfb(CRYPTO_Type *base, cy_en_crypto_dir_mode_t dirMode, uint32_t srcSize, - uint8_t const *ivPtr, + uint8_t *ivPtr, uint8_t *dst, uint8_t const *src, cy_stc_crypto_aes_state_t *aesState); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_aes_v2.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_aes_v2.h index 5d4ce25186..696e68517d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_aes_v2.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_aes_v2.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_aes_v2.h -* \version 2.20 +* \version 2.30 * * \brief * This file provides constant and parameters for the API for the AES method @@ -39,10 +39,13 @@ void Cy_Crypto_Core_V2_Aes_LoadEncKey(CRYPTO_Type *base, void Cy_Crypto_Core_V2_Aes_LoadDecKey(CRYPTO_Type *base, cy_stc_crypto_aes_state_t const *aesState); +cy_en_crypto_status_t Cy_Crypto_Core_V2_Aes_Free(CRYPTO_Type *base, cy_stc_crypto_aes_state_t *aesState); + cy_en_crypto_status_t Cy_Crypto_Core_V2_Aes_Init(CRYPTO_Type *base, uint8_t const *key, cy_en_crypto_aes_key_length_t keyLength, - cy_stc_crypto_aes_state_t *aesState); + cy_stc_crypto_aes_state_t *aesState, + cy_stc_crypto_aes_buffers_t *aesBuffers); cy_en_crypto_status_t Cy_Crypto_Core_V2_Aes_Ecb(CRYPTO_Type *base, cy_en_crypto_dir_mode_t dirMode, @@ -53,7 +56,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Aes_Ecb(CRYPTO_Type *base, cy_en_crypto_status_t Cy_Crypto_Core_V2_Aes_Cbc(CRYPTO_Type *base, cy_en_crypto_dir_mode_t dirMode, uint32_t srcSize, - uint8_t const *ivPtr, + uint8_t *ivPtr, uint8_t *dst, uint8_t const *src, cy_stc_crypto_aes_state_t *aesState); @@ -61,7 +64,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Aes_Cbc(CRYPTO_Type *base, cy_en_crypto_status_t Cy_Crypto_Core_V2_Aes_Cfb(CRYPTO_Type *base, cy_en_crypto_dir_mode_t dirMode, uint32_t srcSize, - uint8_t const *ivPtr, + uint8_t *ivPtr, uint8_t *dst, uint8_t const *src, cy_stc_crypto_aes_state_t *aesState); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_cmac.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_cmac.h index c4e908c068..683fa0c92b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_cmac.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_cmac.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_cmac.h -* \version 2.20 +* \version 2.30 * * \brief * This file provides constants and function prototypes @@ -95,7 +95,7 @@ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Cmac(CRYPTO_Type *base, { cy_en_crypto_status_t tmpResult; - if (CY_CRYPTO_HW_V1) + if (CY_CRYPTO_V1) { tmpResult = Cy_Crypto_Core_V1_Cmac(base, message, messageSize, key, keyLength, cmac, aesState); } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_cmac_v1.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_cmac_v1.h index 21b8956c91..7a95eb23c7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_cmac_v1.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_cmac_v1.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_cmac_v1.h -* \version 2.20 +* \version 2.30 * * \brief * This file provides constants and function prototypes diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_cmac_v2.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_cmac_v2.h index f480559871..3515d09c08 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_cmac_v2.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_cmac_v2.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_cmac_v2.h -* \version 2.20 +* \version 2.30 * * \brief * This file provides constants and function prototypes diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_crc.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_crc.h index 6890e6654b..2a46e75623 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_crc.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_crc.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_crc.h -* \version 2.20 +* \version 2.30 * * \brief * This file provides the headers for CRC API @@ -91,7 +91,7 @@ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Crc_Init(CRYPTO_Type *base, { cy_en_crypto_status_t tmpResult; - if (CY_CRYPTO_HW_V1) + if (CY_CRYPTO_V1) { tmpResult = Cy_Crypto_Core_V1_Crc_Init(base, polynomial, dataReverse, dataXor, remReverse, remXor); } @@ -136,7 +136,7 @@ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Crc(CRYPTO_Type *base, { cy_en_crypto_status_t tmpResult; - if (CY_CRYPTO_HW_V1) + if (CY_CRYPTO_V1) { tmpResult = Cy_Crypto_Core_V1_Crc(base, crc, data, dataSize, lfsrInitState); } @@ -193,7 +193,7 @@ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Crc_CalcInit(CRYPTO_Type *b { cy_en_crypto_status_t tmpResult; - if (CY_CRYPTO_HW_V1) + if (CY_CRYPTO_V1) { tmpResult = Cy_Crypto_Core_V1_Crc_CalcInit(base, width, polynomial, dataReverse, dataXor, remReverse, remXor, lfsrInitState); @@ -231,7 +231,7 @@ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Crc_CalcStart(CRYPTO_Type * { cy_en_crypto_status_t tmpResult; - if (CY_CRYPTO_HW_V1) + if (CY_CRYPTO_V1) { tmpResult = Cy_Crypto_Core_V1_Crc_CalcStart(base, width, lfsrInitState); } @@ -267,7 +267,7 @@ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Crc_CalcPartial(CRYPTO_Type { cy_en_crypto_status_t tmpResult; - if (CY_CRYPTO_HW_V1) + if (CY_CRYPTO_V1) { tmpResult = Cy_Crypto_Core_V1_Crc_CalcPartial(base, data, dataSize); } @@ -302,7 +302,7 @@ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Crc_CalcFinish(CRYPTO_Type { cy_en_crypto_status_t tmpResult; - if (CY_CRYPTO_HW_V1) + if (CY_CRYPTO_V1) { tmpResult = Cy_Crypto_Core_V1_Crc_CalcFinish(base, width, crc); } @@ -345,7 +345,7 @@ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Crc_Calc(CRYPTO_Type *base, { cy_en_crypto_status_t tmpResult; - if (CY_CRYPTO_HW_V1) + if (CY_CRYPTO_V1) { tmpResult = Cy_Crypto_Core_V1_Crc_Calc(base, width, crc, data, dataSize); } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_crc_v1.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_crc_v1.h index f9f17ec657..a3397447a2 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_crc_v1.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_crc_v1.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_crc_v1.h -* \version 2.20 +* \version 2.30 * * \brief * This file provides the headers for CRC API diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_crc_v2.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_crc_v2.h index 58c4b7de92..0fa44f0672 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_crc_v2.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_crc_v2.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_crc_v2.h -* \version 2.20 +* \version 2.30 * * \brief * This file provides the headers for CRC API diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_des.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_des.h index 4acf65c0ad..3d9065a293 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_des.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_des.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_des.h -* \version 2.20 +* \version 2.30 * * \brief * This file provides constant and parameters for the API for the DES method @@ -83,7 +83,7 @@ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Des(CRYPTO_Type *base, { cy_en_crypto_status_t tmpResult; - if (CY_CRYPTO_HW_V1) + if (CY_CRYPTO_V1) { tmpResult = Cy_Crypto_Core_V1_Des(base, dirMode, key, dst, src); } @@ -131,7 +131,7 @@ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Tdes(CRYPTO_Type *base, { cy_en_crypto_status_t tmpResult; - if (CY_CRYPTO_HW_V1) + if (CY_CRYPTO_V1) { tmpResult = Cy_Crypto_Core_V1_Tdes(base, dirMode, key, dst, src); } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_des_v1.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_des_v1.h index 91dbf35e02..452587980b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_des_v1.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_des_v1.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_des.h -* \version 2.20 +* \version 2.30 * * \brief * This file provides constant and parameters for the API for the DES method diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_des_v2.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_des_v2.h index c34ed9122f..7dbeda4152 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_des_v2.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_des_v2.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_des_v2.h -* \version 2.20 +* \version 2.30 * * \brief * This file provides constant and parameters for the API for the DES method diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_ecc.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_ecc.h index fb98ccb491..dcca176b4f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_ecc.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_ecc.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_ecc.h -* \version 2.20 +* \version 2.30 * * \brief * This file provides constant and parameters for the API for the ECC @@ -34,25 +34,6 @@ #if (CPUSS_CRYPTO_VU == 1) -/** -* \addtogroup group_crypto_lld_asymmetric_enums -* \{ -*/ - -/** List of supported elliptic curve IDs */ -typedef enum { - CY_CRYPTO_ECC_ECP_NONE = 0, - CY_CRYPTO_ECC_ECP_SECP192R1, - CY_CRYPTO_ECC_ECP_SECP224R1, - CY_CRYPTO_ECC_ECP_SECP256R1, - CY_CRYPTO_ECC_ECP_SECP384R1, - CY_CRYPTO_ECC_ECP_SECP521R1, - /* Count of supported curves */ - CY_CRYPTO_ECC_ECP_CURVES_CNT -} cy_en_crypto_ecc_curve_id_t; - -/** \} group_crypto_lld_asymmetric_enums */ - typedef enum cy_en_red_mul_algs { CY_CRYPTO_NIST_P_CURVE_SPECIFIC_RED_ALG = 0, CY_CRYPTO_NIST_P_SHIFT_MUL_RED_ALG, @@ -63,69 +44,29 @@ typedef enum cy_en_red_mul_algs { typedef struct { /** The curve ID */ cy_en_crypto_ecc_curve_id_t id; - /** The size of the curve in bits */ uint32_t size; - /** name of curve */ const char_t *name; - /** ECC calculation default algorithm */ cy_en_crypto_ecc_red_mul_algs_t algo; - /** The prime that defines the field the curve is in (encoded in hex) */ const uint8_t *prime; - /** Barrett coefficient for reduction modulo ECC prime (hex) */ const uint8_t *barrett_p; - /** The order of the curve (hex) */ const uint8_t *order; - /** Barrett coefficient for reduction modulo ECC order (hex) */ const uint8_t *barrett_o; - /** The x co-ordinate of the base point on the curve (hex) */ const uint8_t *Gx; - /** The y co-ordinate of the base point on the curve (hex) */ const uint8_t *Gy; } cy_stc_crypto_ecc_dp_type; -/** A point on a ECC curve */ -typedef struct { - /** The x co-ordinate */ - void *x; - /** The y co-ordinate */ - void *y; -} cy_stc_crypto_ecc_point; - cy_stc_crypto_ecc_dp_type *Cy_Crypto_Core_ECC_GetCurveParams(cy_en_crypto_ecc_curve_id_t curveId); - -typedef enum cy_en_crypto_ecc_key_type { - PK_PUBLIC = 0u, - PK_PRIVATE = 1u -} cy_en_crypto_ecc_key_type_t; - -/** An ECC key */ -typedef struct { - /** Type of key, PK_PRIVATE or PK_PUBLIC */ - cy_en_crypto_ecc_key_type_t type; - - /** pointer to domain parameters */ - - cy_en_crypto_ecc_curve_id_t curveID; - - /** The public key */ - cy_stc_crypto_ecc_point pubkey; - - /** The private key */ - void *k; -} cy_stc_crypto_ecc_key; - - /** * \addtogroup group_crypto_lld_asymmetric_functions * \{ @@ -150,19 +91,16 @@ cy_en_crypto_status_t Cy_Crypto_Core_ECC_VerifyHash(CRYPTO_Type *base, uint32_t hashlen, uint8_t *stat, const cy_stc_crypto_ecc_key *key); + cy_en_crypto_status_t Cy_Crypto_Core_ECC_MakePrivateKey(CRYPTO_Type *base, cy_en_crypto_ecc_curve_id_t curveID, uint8_t *key, cy_func_get_random_data_t GetRandomDataFunc, void *randomDataInfo); cy_en_crypto_status_t Cy_Crypto_Core_ECC_MakePublicKey(CRYPTO_Type *base, cy_en_crypto_ecc_curve_id_t curveID, - const uint8_t *privateKey, - cy_stc_crypto_ecc_key *publicKey); + const uint8_t *privateKey, cy_stc_crypto_ecc_key *publicKey); /** \} group_crypto_lld_asymmetric_functions */ -/** Calculates the actual size in bytes of the bits value */ -#define CY_CRYPTO_BYTE_SIZE_OF_BITS(x) (uint32_t)(((x) + 7u) >> 3u) - /* Sizes for NIST P-curves */ #define CY_CRYPTO_ECC_P192_SIZE (192u) /* 2^192 - 2^64 - 1 */ #define CY_CRYPTO_ECC_P192_BYTE_SIZE CY_CRYPTO_BYTE_SIZE_OF_BITS(CY_CRYPTO_ECC_P192_SIZE) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_ecc_nist_p.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_ecc_nist_p.h index 33e5b3a824..6f48354d67 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_ecc_nist_p.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_ecc_nist_p.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_ecc_nist_p.h -* \version 2.20 +* \version 2.30 * * \brief * This file provides constant and parameters for the API for the ECC diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hmac.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hmac.h index d920990cf9..13334545e4 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hmac.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hmac.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_hmac.h -* \version 2.20 +* \version 2.30 * * \brief * This file provides constants and function prototypes @@ -90,7 +90,7 @@ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Hmac(CRYPTO_Type *base, { cy_en_crypto_status_t tmpResult; - if (CY_CRYPTO_HW_V1) + if (CY_CRYPTO_V1) { tmpResult = Cy_Crypto_Core_V1_Hmac(base, hmac, message, messageSize, key, keyLength, mode); } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hmac_v1.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hmac_v1.h index 7b24e9eb4c..af2825e129 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hmac_v1.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hmac_v1.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_hmac_v1.h -* \version 2.20 +* \version 2.30 * * \brief * This file provides constants and function prototypes diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hmac_v2.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hmac_v2.h index 5c34c14cc3..d10cf93bb1 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hmac_v2.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hmac_v2.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_hmac_v2.h -* \version 2.20 +* \version 2.30 * * \brief * This file provides constants and function prototypes diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hw.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hw.h index ff2ddf9c86..df758cc9f0 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hw.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hw.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_hw.h -* \version 2.20 +* \version 2.30 * * \brief * This file provides the headers to the API for the utils @@ -108,10 +108,10 @@ #define REG_CRYPTO_DEV_KEY_CTL0(base) (((CRYPTO_V2_Type*)(base))->DEV_KEY_CTL0) #define REG_CRYPTO_DEV_KEY_CTL1(base) (((CRYPTO_V2_Type*)(base))->DEV_KEY_CTL1) -/* The CRYPTO internal-memory buffer-size in bytes. */ -#define CY_CRYPTO_MEM_BUFF_SIZE ((cy_device->cryptoMemSize) * 4u) /* The CRYPTO internal-memory buffer-size in 32-bit words. */ #define CY_CRYPTO_MEM_BUFF_SIZE_U32 (cy_device->cryptoMemSize) +/* The CRYPTO internal-memory buffer-size in bytes. */ +#define CY_CRYPTO_MEM_BUFF_SIZE (CY_CRYPTO_MEM_BUFF_SIZE_U32 * 4u) /* Device Crypto IP descriptor type */ typedef struct @@ -206,9 +206,14 @@ extern const cy_stc_cryptoIP_t *cy_cryptoIP; CRYPTO_INTR_MASKED_TR_AP_DETECT_ERROR_Msk | \ CRYPTO_INTR_MASKED_TR_RC_DETECT_ERROR_Msk)) +#define CY_CRYPTO_INSTR_FIFODEPTH (8u) #define CY_CRYPTO_V1_DATA_FIFODEPTH (8u) #define CY_CRYPTO_V2_DATA_FIFODEPTH (16u) +#define CY_CRYPTO_INSTR_SINGLE (1u) +#define CY_CRYPTO_INSTR_DOUBLE (2u) +#define CY_CRYPTO_INSTR_TRIPLE (3u) + #define CY_CRYPTO_MIN(a,b) (((a) < (b)) ? (a) : (b)) #define CY_CRYPTO_MAX(a,b) (((a) > (b)) ? (a) : (b)) @@ -220,20 +225,28 @@ typedef enum /** \endcond */ +void Cy_Crypto_Core_HwInit(void); + +void Cy_Crypto_Core_ClearVuRegisters(CRYPTO_Type *base); + +void Cy_Crypto_Core_Vu_RunInstr(CRYPTO_Type *base, bool blockingMode, uint32_t instr, uint32_t params); + /** * \addtogroup group_crypto_lld_hw_functions * \{ */ -void Cy_Crypto_Core_HwInit(void); - cy_en_crypto_status_t Cy_Crypto_Core_Enable(CRYPTO_Type *base); cy_en_crypto_status_t Cy_Crypto_Core_Disable(CRYPTO_Type *base); cy_en_crypto_status_t Cy_Crypto_Core_GetLibInfo(cy_en_crypto_lib_info_t *libInfo); -void Cy_Crypto_Core_ClearVuRegisters(CRYPTO_Type *base); +cy_en_crypto_status_t Cy_Crypto_Core_SetVuMemoryAddress(CRYPTO_Type *base, uint32_t const *vuMemoryAddr, uint32_t vuMemorySize); + +__STATIC_INLINE uint32_t * Cy_Crypto_Core_GetVuMemoryAddress(CRYPTO_Type *base); + +uint32_t Cy_Crypto_Core_GetVuMemorySize(CRYPTO_Type *base); void Cy_Crypto_Core_InvertEndianness(void *inArrPtr, uint32_t byteSize); @@ -265,9 +278,6 @@ __STATIC_INLINE bool Cy_Crypto_Core_IsEnabled(CRYPTO_Type *base) ****************************************************************************//** * * Returns the total available number of instructions in the instruction FIFO. -* The value of this field ranges: -* - from 0 to 8 for MXCRYPTO_ver1 IP block and -* - from 0 to 16 for MXCRYPTO_ver2 IP block * * \param base * The pointer to the CRYPTO instance. @@ -275,7 +285,7 @@ __STATIC_INLINE bool Cy_Crypto_Core_IsEnabled(CRYPTO_Type *base) *******************************************************************************/ __STATIC_INLINE uint8_t Cy_Crypto_Core_GetFIFODepth(CRYPTO_Type *base) { - return (cy_device->cryptoVersion == 1u) ? (CY_CRYPTO_V1_DATA_FIFODEPTH) : (CY_CRYPTO_V2_DATA_FIFODEPTH); + return (CY_CRYPTO_INSTR_FIFODEPTH); } /******************************************************************************* @@ -294,6 +304,27 @@ __STATIC_INLINE uint8_t Cy_Crypto_Core_GetFIFOUsed(CRYPTO_Type *base) return((uint8_t)_FLD2VAL(CRYPTO_INSTR_FF_STATUS_USED, REG_CRYPTO_INSTR_FF_STATUS(base))); } +/******************************************************************************* +* Function Name: Cy_Crypto_Core_WaitForInstrFifoAvailable +*****************************************************************************//** +* +* Waits until number of entries in the instruction FIFO is less than +* specified number. +* +* \param base +* The pointer to the CRYPTO instance. +* +* \param instr +* The number of needed available space in the instruction FIFO. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_Crypto_Core_WaitForInstrFifoAvailable(CRYPTO_Type *base, uint32_t instr) +{ + while((uint32_t)(_FLD2VAL(CRYPTO_INSTR_FF_STATUS_USED, REG_CRYPTO_INSTR_FF_STATUS(base))) >= (CY_CRYPTO_INSTR_FIFODEPTH - instr)) + { + } +} + /******************************************************************************* * Function Name: Cy_Crypto_Core_WaitForFifoAvailable *****************************************************************************//** @@ -331,6 +362,33 @@ __STATIC_INLINE void Cy_Crypto_Core_WaitForReady(CRYPTO_Type *base) } } +/******************************************************************************* +* Function Name: Cy_Crypto_Wait_Vu_ForComplete +****************************************************************************//** +* +* Waits until VU instruction will be completed +* +* \param base +* The pointer to the CRYPTO instance. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_Crypto_Core_Vu_WaitForComplete(CRYPTO_Type *base) +{ + /* Wait until the VU instruction is complete */ + if (CY_CRYPTO_V1) + { + while (0uL != _FLD2VAL(CRYPTO_STATUS_VU_BUSY, REG_CRYPTO_STATUS(base))) + { + } + } + else + { + while (0uL != REG_CRYPTO_STATUS(base)) + { + } + } +} + /****************************************************************************** * Function Name: Cy_Crypto_Core_SetInterruptMask ***************************************************************************//** @@ -440,8 +498,28 @@ __STATIC_INLINE void Cy_Crypto_Core_ClearInterrupt(CRYPTO_Type *base, uint32_t (void) REG_CRYPTO_INTR(base); } +/******************************************************************************* +* Function Name: Cy_Crypto_Core_GetVuMemoryAddress +****************************************************************************//** +* +* Gets Crypto memory buffer address +* +* \param base +* The pointer to the CRYPTO instance. +* +* \return +* Current Crypto MEM_BUFF location address or NULL if Crypto IP is not enabled. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t * Cy_Crypto_Core_GetVuMemoryAddress(CRYPTO_Type *base) +{ + return (cy_cryptoIP != NULL) ? (uint32_t *)REG_CRYPTO_VU_CTL1(base) : (uint32_t *)NULL; +} + + /** \} group_crypto_lld_hw_functions */ + #endif /* CY_IP_MXCRYPTO */ #endif /* #if !defined(CY_CRYPTO_CORE_HW_H) */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hw_v1.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hw_v1.h index 8ba1823b74..7b6cbf7a4b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hw_v1.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hw_v1.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_hw_v1.h -* \version 2.20 +* \version 2.30 * * \brief * This file provides constants and function prototypes diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hw_v2.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hw_v2.h index 33eef6dad5..468857ca46 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hw_v2.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hw_v2.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_hw_v2.h -* \version 2.20 +* \version 2.30 * * \brief * This file provides constants and function prototypes @@ -147,7 +147,7 @@ __STATIC_INLINE void Cy_Crypto_Core_V2_FFStart(CRYPTO_Type *base, uint32_t ff_idx, const uint8_t* p_mem, uint32_t size) { /* Check whether FIFO has enough space for 1 instruction */ - while(Cy_Crypto_Core_GetFIFOUsed(base) >= (CY_CRYPTO_V2_DATA_FIFODEPTH - 3u)) + while(Cy_Crypto_Core_GetFIFOUsed(base) >= (CY_CRYPTO_INSTR_FIFODEPTH - 3u)) { } @@ -161,7 +161,7 @@ __STATIC_INLINE void Cy_Crypto_Core_V2_FFContinue(CRYPTO_Type *base, uint32_t ff_idx, const uint8_t* p_mem, uint32_t size) { /* Check whether FIFO has enough space for 1 instruction */ - while(Cy_Crypto_Core_GetFIFOUsed(base) >= (CY_CRYPTO_V2_DATA_FIFODEPTH - 3u)) + while(Cy_Crypto_Core_GetFIFOUsed(base) >= (CY_CRYPTO_INSTR_FIFODEPTH - 3u)) { } @@ -177,7 +177,7 @@ __STATIC_INLINE void Cy_Crypto_Core_V2_FFContinue(CRYPTO_Type *base, __STATIC_INLINE void Cy_Crypto_Core_V2_FFStop(CRYPTO_Type *base, uint32_t ff_idx) { /* Check whether FIFO has enough space for 1 instruction */ - while(Cy_Crypto_Core_GetFIFOUsed(base) >= (CY_CRYPTO_V2_DATA_FIFODEPTH - 1u)) + while(Cy_Crypto_Core_GetFIFOUsed(base) >= (CY_CRYPTO_INSTR_FIFODEPTH - 1u)) { } @@ -189,7 +189,7 @@ __STATIC_INLINE void Cy_Crypto_Core_V2_BlockMov(CRYPTO_Type *base, uint32_t dst_idx, uint32_t src_idx, uint32_t size) { /* Check whether FIFO has enough space for 1 instruction */ - while(Cy_Crypto_Core_GetFIFOUsed(base) >= (CY_CRYPTO_V2_DATA_FIFODEPTH - 1u)) + while(Cy_Crypto_Core_GetFIFOUsed(base) >= (CY_CRYPTO_INSTR_FIFODEPTH - 1u)) { } @@ -203,7 +203,7 @@ __STATIC_INLINE void Cy_Crypto_Core_V2_BlockMov_Reflect(CRYPTO_Type *base, uint32_t dst_idx, uint32_t src_idx, uint32_t size) { /* Check whether FIFO has enough space for 1 instruction */ - while(Cy_Crypto_Core_GetFIFOUsed(base) >= (CY_CRYPTO_V2_DATA_FIFODEPTH - 1u)) + while(Cy_Crypto_Core_GetFIFOUsed(base) >= (CY_CRYPTO_INSTR_FIFODEPTH - 1u)) { } @@ -218,7 +218,7 @@ __STATIC_INLINE void Cy_Crypto_Core_V2_BlockSet(CRYPTO_Type *base, uint32_t dst_idx, uint8_t data, uint32_t size) { /* Check whether FIFO has enough space for 1 instruction */ - while(Cy_Crypto_Core_GetFIFOUsed(base) >= (CY_CRYPTO_V2_DATA_FIFODEPTH - 1u)) + while(Cy_Crypto_Core_GetFIFOUsed(base) >= (CY_CRYPTO_INSTR_FIFODEPTH - 1u)) { } @@ -232,7 +232,7 @@ __STATIC_INLINE void Cy_Crypto_Core_V2_BlockCmp(CRYPTO_Type *base, uint32_t src0_idx, uint32_t src1_idx, uint32_t size) { /* Check whether FIFO has enough space for 1 instruction */ - while(Cy_Crypto_Core_GetFIFOUsed(base) >= (CY_CRYPTO_V2_DATA_FIFODEPTH - 1u)) + while(Cy_Crypto_Core_GetFIFOUsed(base) >= (CY_CRYPTO_INSTR_FIFODEPTH - 1u)) { } @@ -246,7 +246,7 @@ __STATIC_INLINE void Cy_Crypto_Core_V2_BlockXor(CRYPTO_Type *base, uint32_t dst_idx, uint32_t src0_idx, uint32_t src1_idx, uint32_t size) { /* Check whether FIFO has enough space for 1 instruction */ - while(Cy_Crypto_Core_GetFIFOUsed(base) >= (CY_CRYPTO_V2_DATA_FIFODEPTH - 1u)) + while(Cy_Crypto_Core_GetFIFOUsed(base) >= (CY_CRYPTO_INSTR_FIFODEPTH - 1u)) { } @@ -260,7 +260,7 @@ __STATIC_INLINE void Cy_Crypto_Core_V2_BlockXor(CRYPTO_Type *base, __STATIC_INLINE void Cy_Crypto_Core_V2_BlockGcm(CRYPTO_Type *base) { /* Check whether FIFO has enough space for 1 instruction */ - while(Cy_Crypto_Core_GetFIFOUsed(base) >= (CY_CRYPTO_V2_DATA_FIFODEPTH - 1u)) + while(Cy_Crypto_Core_GetFIFOUsed(base) >= (CY_CRYPTO_INSTR_FIFODEPTH - 1u)) { } @@ -270,7 +270,7 @@ __STATIC_INLINE void Cy_Crypto_Core_V2_BlockGcm(CRYPTO_Type *base) __STATIC_INLINE void Cy_Crypto_Core_V2_Run(CRYPTO_Type *base, uint32_t opc) { /* Check whether FIFO has enough space for 1 instruction */ - while(Cy_Crypto_Core_GetFIFOUsed(base) >= (CY_CRYPTO_V2_DATA_FIFODEPTH - 1u)) + while(Cy_Crypto_Core_GetFIFOUsed(base) >= (CY_CRYPTO_INSTR_FIFODEPTH - 1u)) { } @@ -280,7 +280,7 @@ __STATIC_INLINE void Cy_Crypto_Core_V2_Run(CRYPTO_Type *base, uint32_t opc) __STATIC_INLINE void Cy_Crypto_Core_V2_RBClear(CRYPTO_Type *base) { /* Check whether FIFO has enough space for 1 instruction */ - while(Cy_Crypto_Core_GetFIFOUsed(base) >= (CY_CRYPTO_V2_DATA_FIFODEPTH - 1u)) + while(Cy_Crypto_Core_GetFIFOUsed(base) >= (CY_CRYPTO_INSTR_FIFODEPTH - 1u)) { } @@ -290,7 +290,7 @@ __STATIC_INLINE void Cy_Crypto_Core_V2_RBClear(CRYPTO_Type *base) __STATIC_INLINE void Cy_Crypto_Core_V2_RBSwap(CRYPTO_Type *base) { /* Check whether FIFO has enough space for 1 instruction */ - while(Cy_Crypto_Core_GetFIFOUsed(base) >= (CY_CRYPTO_V2_DATA_FIFODEPTH - 1u)) + while(Cy_Crypto_Core_GetFIFOUsed(base) >= (CY_CRYPTO_INSTR_FIFODEPTH - 1u)) { } @@ -300,7 +300,7 @@ __STATIC_INLINE void Cy_Crypto_Core_V2_RBSwap(CRYPTO_Type *base) __STATIC_INLINE void Cy_Crypto_Core_V2_RBXor(CRYPTO_Type *base, uint32_t offset, uint32_t size) { /* Check whether FIFO has enough space for 1 instruction */ - while(Cy_Crypto_Core_GetFIFOUsed(base) >= (CY_CRYPTO_V2_DATA_FIFODEPTH - 1u)) + while(Cy_Crypto_Core_GetFIFOUsed(base) >= (CY_CRYPTO_INSTR_FIFODEPTH - 1u)) { } @@ -312,7 +312,7 @@ __STATIC_INLINE void Cy_Crypto_Core_V2_RBXor(CRYPTO_Type *base, uint32_t offset, __STATIC_INLINE void Cy_Crypto_Core_V2_RBStore(CRYPTO_Type *base, uint32_t offset, uint32_t size) { /* Check whether FIFO has enough space for 1 instruction */ - while(Cy_Crypto_Core_GetFIFOUsed(base) >= (CY_CRYPTO_V2_DATA_FIFODEPTH - 1u)) + while(Cy_Crypto_Core_GetFIFOUsed(base) >= (CY_CRYPTO_INSTR_FIFODEPTH - 1u)) { } @@ -323,7 +323,7 @@ __STATIC_INLINE void Cy_Crypto_Core_V2_RBStore(CRYPTO_Type *base, uint32_t offse __STATIC_INLINE void Cy_Crypto_Core_V2_RBSetByte(CRYPTO_Type *base, uint32_t offset, uint8_t byte) { /* Check whether FIFO has enough space for 1 instruction */ - while(Cy_Crypto_Core_GetFIFOUsed(base) >= (CY_CRYPTO_V2_DATA_FIFODEPTH - 1u)) + while(Cy_Crypto_Core_GetFIFOUsed(base) >= (CY_CRYPTO_INSTR_FIFODEPTH - 1u)) { } @@ -335,7 +335,7 @@ __STATIC_INLINE void Cy_Crypto_Core_V2_RBSetByte(CRYPTO_Type *base, uint32_t off __STATIC_INLINE void Cy_Crypto_Core_V2_RunAes(CRYPTO_Type *base) { /* Check whether FIFO has enough space for 1 instruction */ - while(Cy_Crypto_Core_GetFIFOUsed(base) >= (CY_CRYPTO_V2_DATA_FIFODEPTH - 1u)) + while(Cy_Crypto_Core_GetFIFOUsed(base) >= (CY_CRYPTO_INSTR_FIFODEPTH - 1u)) { } @@ -345,7 +345,7 @@ __STATIC_INLINE void Cy_Crypto_Core_V2_RunAes(CRYPTO_Type *base) __STATIC_INLINE void Cy_Crypto_Core_V2_RunAesInv(CRYPTO_Type *base) { /* Check whether FIFO has enough space for 1 instruction */ - while(Cy_Crypto_Core_GetFIFOUsed(base) >= (CY_CRYPTO_V2_DATA_FIFODEPTH - 1u)) + while(Cy_Crypto_Core_GetFIFOUsed(base) >= (CY_CRYPTO_INSTR_FIFODEPTH - 1u)) { } @@ -355,7 +355,7 @@ __STATIC_INLINE void Cy_Crypto_Core_V2_RunAesInv(CRYPTO_Type *base) __STATIC_INLINE void Cy_Crypto_Core_V2_RunChacha(CRYPTO_Type *base, uint8_t roundNum) { /* Check whether FIFO has enough space for 1 instruction */ - while(Cy_Crypto_Core_GetFIFOUsed(base) >= (CY_CRYPTO_V2_DATA_FIFODEPTH - 1u)) + while(Cy_Crypto_Core_GetFIFOUsed(base) >= (CY_CRYPTO_INSTR_FIFODEPTH - 1u)) { } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hw_vu.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hw_vu.h index 7780982475..2df6f8535c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hw_vu.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hw_vu.h @@ -1,8 +1,8 @@ /***************************************************************************//** -* file cy_crypto_core_hw_vu.h -* version 2.20 +* \file cy_crypto_core_hw_vu.h +* \version 2.30 * -* brief +* \brief * This file provides constants and function prototypes * for the Vector Unit functions in the Crypto block driver. * @@ -87,6 +87,10 @@ #define CY_CRYPTO_VU_GET_REG_DATA(data) (((data) >> 16U) & 0x00003fffUL) #define CY_CRYPTO_VU_GET_REG_SIZE(data) ((data) & 0x00000fffUL) +#define CY_CRYPTO_VU_SIZE_FLD_MASK (0x00001fffuL) +#define CY_CRYPTO_VU_DATA_FLD_MASK (0x00003fffuL) +#define CY_CRYPTO_VU_DATA_FLD_POS (16u) + /* Vector Unit instructions */ #define CY_CRYPTO_VU_ALLOC_MEM_OPC (0x12u) #define CY_CRYPTO_VU_FREE_MEM_OPC (0x13u) @@ -107,7 +111,7 @@ /* Instructions with register operand only, category V */ #define CY_CRYPTO_VU_MOV_STATUS_TO_REG_OPC (0x05u) -#define CY_CRYPTO_VU2_MOV_IMM_TO_STATUS (0x0Fu) +#define CY_CRYPTO_VU2_MOV_IMM_TO_STATUS_OPC (0x0Fu) /* Instructions with register operand only, category VI */ #define CY_CRYPTO_VU_PUSH_REG_OPC (0x10u) @@ -190,6 +194,8 @@ #define CY_CRYPTO_VU2_CLR_BIT_IMM_OPC (0x2Du) #define CY_CRYPTO_VU2_INV_BIT_IMM_OPC (0x2Eu) +#define CY_CRYPTO_VU1_WAIT_FOR_COMPLETE(base) do { ; } while (0uL != _FLD2VAL(CRYPTO_STATUS_VU_BUSY, REG_CRYPTO_STATUS(base))) +#define CY_CRYPTO_VU_READ_SP_REG(base) CY_CRYPTO_VU_GET_REG_DATA(REG_CRYPTO_VU_RF_DATA(base, 15u)) __STATIC_INLINE void CY_CRYPTO_VU_SAVE_REG (CRYPTO_Type *base, uint32_t rsrc, uint32_t *data); __STATIC_INLINE void CY_CRYPTO_VU_RESTORE_REG (CRYPTO_Type *base, uint32_t rdst, uint32_t data); @@ -198,7 +204,8 @@ __STATIC_INLINE void CY_CRYPTO_VU_SET_REG (CRYPTO_Type *base, uint32_t rdst, uin __STATIC_INLINE void CY_CRYPTO_VU_COND_MOV_REG_TO_STATUS (CRYPTO_Type *base, uint32_t cc, uint32_t rsrc) { - REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)CY_CRYPTO_VU_MOV_REG_TO_STATUS_OPC << CY_CRYPTO_OPCODE_POS) | + Cy_Crypto_Core_Vu_RunInstr(base, CY_CRYPTO_SYNC_NON_BLOCKING, + (uint32_t)CY_CRYPTO_VU_MOV_REG_TO_STATUS_OPC, ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rsrc)); } @@ -210,7 +217,8 @@ __STATIC_INLINE void CY_CRYPTO_VU_MOV_REG_TO_STATUS (CRYPTO_Type *base, uint32_t __STATIC_INLINE void CY_CRYPTO_VU_COND_MOV_STATUS_TO_REG (CRYPTO_Type *base, uint32_t cc, uint32_t rdst) { - REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)CY_CRYPTO_VU_MOV_STATUS_TO_REG_OPC << CY_CRYPTO_OPCODE_POS) | + Cy_Crypto_Core_Vu_RunInstr(base, CY_CRYPTO_SYNC_NON_BLOCKING, + (uint32_t)CY_CRYPTO_VU_MOV_STATUS_TO_REG_OPC, ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT)); } @@ -222,7 +230,7 @@ __STATIC_INLINE void CY_CRYPTO_VU_MOV_STATUS_TO_REG (CRYPTO_Type *base, uint32_t __STATIC_INLINE void CY_CRYPTO_VU_COND_MOV_IMM_TO_STATUS (CRYPTO_Type *base, uint32_t cc, uint32_t imm4) { - if (CY_CRYPTO_HW_V1) + if (CY_CRYPTO_V1) { /******* V1 *********/ uint32_t tmpReg = CY_CRYPTO_VU_HW_REG14; @@ -234,12 +242,15 @@ __STATIC_INLINE void CY_CRYPTO_VU_COND_MOV_IMM_TO_STATUS (CRYPTO_Type *base, uin CY_CRYPTO_VU_SET_REG(base, tmpReg, imm4, 4u); CY_CRYPTO_VU_COND_MOV_REG_TO_STATUS(base, cc, tmpReg); + CY_CRYPTO_VU1_WAIT_FOR_COMPLETE(base); + CY_CRYPTO_VU_RESTORE_REG(base, tmpReg, tmpData); } else { /******* V2 *********/ - REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)CY_CRYPTO_VU2_MOV_IMM_TO_STATUS << CY_CRYPTO_OPCODE_POS) | + Cy_Crypto_Core_Vu_RunInstr(base, CY_CRYPTO_SYNC_NON_BLOCKING, + (uint32_t)CY_CRYPTO_VU2_MOV_IMM_TO_STATUS_OPC, ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)imm4 << CY_CRYPTO_RSRC0_SHIFT)); } @@ -250,19 +261,20 @@ __STATIC_INLINE void CY_CRYPTO_VU_MOV_IMM_TO_STATUS (CRYPTO_Type *base, uint32_t CY_CRYPTO_VU_COND_MOV_IMM_TO_STATUS (base, CY_CRYPTO_VU_COND_ALWAYS, imm4); } - /*******************************************************************************/ __STATIC_INLINE void CY_CRYPTO_VU_SET_REG (CRYPTO_Type *base, uint32_t rdst, uint32_t data, uint32_t size) { - REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)CY_CRYPTO_VU_SET_REG_OPC << CY_CRYPTO_OPCODE_POS) | + Cy_Crypto_Core_Vu_RunInstr(base, CY_CRYPTO_SYNC_NON_BLOCKING, + (uint32_t)CY_CRYPTO_VU_SET_REG_OPC, ((uint32_t)rdst << CY_CRYPTO_RSRC26_SHIFT) | - ((uint32_t)data << ((CY_CRYPTO_HW_V1) ? CY_CRYPTO_RSRC12_SHIFT : CY_CRYPTO_RSRC13_SHIFT)) | + ((uint32_t)data << ((CY_CRYPTO_V1) ? CY_CRYPTO_RSRC12_SHIFT : CY_CRYPTO_RSRC13_SHIFT)) | (((uint32_t)size - 1u) << CY_CRYPTO_RSRC0_SHIFT)); } __STATIC_INLINE void CY_CRYPTO_VU_COND_LD_REG (CRYPTO_Type *base, uint32_t cc, uint32_t rdst, uint32_t rsrc) { - REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)CY_CRYPTO_VU_LD_REG_OPC << CY_CRYPTO_OPCODE_POS) | + Cy_Crypto_Core_Vu_RunInstr(base, CY_CRYPTO_SYNC_NON_BLOCKING, + (uint32_t)CY_CRYPTO_VU_LD_REG_OPC, ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)rsrc << CY_CRYPTO_RSRC0_SHIFT)); @@ -275,7 +287,8 @@ __STATIC_INLINE void CY_CRYPTO_VU_LD_REG (CRYPTO_Type *base, uint32_t rdst, uint __STATIC_INLINE void CY_CRYPTO_VU_COND_ST_REG (CRYPTO_Type *base, uint32_t cc, uint32_t rdst, uint32_t rsrc) { - REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)CY_CRYPTO_VU_ST_REG_OPC << CY_CRYPTO_OPCODE_POS) | + Cy_Crypto_Core_Vu_RunInstr(base, CY_CRYPTO_SYNC_NON_BLOCKING, + (uint32_t)CY_CRYPTO_VU_ST_REG_OPC, ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)rsrc << CY_CRYPTO_RSRC0_SHIFT)); @@ -288,7 +301,8 @@ __STATIC_INLINE void CY_CRYPTO_VU_ST_REG (CRYPTO_Type *base, uint32_t rdst, uint __STATIC_INLINE void CY_CRYPTO_VU_COND_MOV_REG (CRYPTO_Type *base, uint32_t cc, uint32_t rdst, uint32_t rsrc) { - REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)CY_CRYPTO_VU_MOV_REG_TO_STATUS_OPC << CY_CRYPTO_OPCODE_POS) | + Cy_Crypto_Core_Vu_RunInstr(base, CY_CRYPTO_SYNC_NON_BLOCKING, + (uint32_t)CY_CRYPTO_VU_MOV_REG_TO_STATUS_OPC, ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)rsrc << CY_CRYPTO_RSRC0_SHIFT)); @@ -301,7 +315,8 @@ __STATIC_INLINE void CY_CRYPTO_VU_MOV_REG (CRYPTO_Type *base, uint32_t rdst, uin __STATIC_INLINE void CY_CRYPTO_VU_COND_SWAP_REG (CRYPTO_Type *base, uint32_t cc, uint32_t rsrc1, uint32_t rsrc0) { - REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)CY_CRYPTO_VU_SWAP_REG_OPC << CY_CRYPTO_OPCODE_POS) | + Cy_Crypto_Core_Vu_RunInstr(base, CY_CRYPTO_SYNC_NON_BLOCKING, + (uint32_t)CY_CRYPTO_VU_SWAP_REG_OPC, ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rsrc1 << CY_CRYPTO_RSRC4_SHIFT) | ((uint32_t)rsrc0 << CY_CRYPTO_RSRC0_SHIFT)); @@ -314,7 +329,8 @@ __STATIC_INLINE void CY_CRYPTO_VU_SWAP_REG (CRYPTO_Type *base, uint32_t rsrc1, u __STATIC_INLINE void CY_CRYPTO_VU_COND_ADD_REG (CRYPTO_Type *base, uint32_t cc, uint32_t rdst, uint32_t rsrc1, uint32_t rsrc0) { - REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)CY_CRYPTO_VU_ADD_REG_OPC << CY_CRYPTO_OPCODE_POS) | + Cy_Crypto_Core_Vu_RunInstr(base, CY_CRYPTO_SYNC_NON_BLOCKING, + (uint32_t)CY_CRYPTO_VU_ADD_REG_OPC, ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)rsrc1 << CY_CRYPTO_RSRC4_SHIFT) | @@ -328,7 +344,8 @@ __STATIC_INLINE void CY_CRYPTO_VU_ADD_REG (CRYPTO_Type *base, uint32_t rdst, uin __STATIC_INLINE void CY_CRYPTO_VU_COND_SUB_REG (CRYPTO_Type *base, uint32_t cc, uint32_t rdst, uint32_t rsrc1, uint32_t rsrc0) { - REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)CY_CRYPTO_VU_SUB_REG_OPC << CY_CRYPTO_OPCODE_POS) | + Cy_Crypto_Core_Vu_RunInstr(base, CY_CRYPTO_SYNC_NON_BLOCKING, + (uint32_t)CY_CRYPTO_VU_SUB_REG_OPC, ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)rsrc1 << CY_CRYPTO_RSRC4_SHIFT) | @@ -342,7 +359,8 @@ __STATIC_INLINE void CY_CRYPTO_VU_SUB_REG (CRYPTO_Type *base, uint32_t rdst, uin __STATIC_INLINE void CY_CRYPTO_VU_COND_OR_REG (CRYPTO_Type *base, uint32_t cc, uint32_t rdst, uint32_t rsrc1, uint32_t rsrc0) { - REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)CY_CRYPTO_VU_OR_REG_OPC << CY_CRYPTO_OPCODE_POS) | + Cy_Crypto_Core_Vu_RunInstr(base, CY_CRYPTO_SYNC_NON_BLOCKING, + (uint32_t)CY_CRYPTO_VU_OR_REG_OPC, ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)rsrc1 << CY_CRYPTO_RSRC4_SHIFT) | @@ -356,7 +374,8 @@ __STATIC_INLINE void CY_CRYPTO_VU_OR_REG (CRYPTO_Type *base, uint32_t rdst, uint __STATIC_INLINE void CY_CRYPTO_VU_COND_AND_REG (CRYPTO_Type *base, uint32_t cc, uint32_t rdst, uint32_t rsrc1, uint32_t rsrc0) { - REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)CY_CRYPTO_VU_AND_REG_OPC << CY_CRYPTO_OPCODE_POS) | + Cy_Crypto_Core_Vu_RunInstr(base, CY_CRYPTO_SYNC_NON_BLOCKING, + (uint32_t)CY_CRYPTO_VU_AND_REG_OPC, ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)rsrc1 << CY_CRYPTO_RSRC4_SHIFT) | @@ -370,7 +389,8 @@ __STATIC_INLINE void CY_CRYPTO_VU_AND_REG (CRYPTO_Type *base, uint32_t rdst, uin __STATIC_INLINE void CY_CRYPTO_VU_COND_XOR_REG (CRYPTO_Type *base, uint32_t cc, uint32_t rdst, uint32_t rsrc1, uint32_t rsrc0) { - REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)CY_CRYPTO_VU_XOR_REG_OPC << CY_CRYPTO_OPCODE_POS) | + Cy_Crypto_Core_Vu_RunInstr(base, CY_CRYPTO_SYNC_NON_BLOCKING, + (uint32_t)CY_CRYPTO_VU_XOR_REG_OPC, ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)rsrc1 << CY_CRYPTO_RSRC4_SHIFT) | @@ -384,7 +404,8 @@ __STATIC_INLINE void CY_CRYPTO_VU_XOR_REG (CRYPTO_Type *base, uint32_t rdst, uin __STATIC_INLINE void CY_CRYPTO_VU_COND_NOR_REG (CRYPTO_Type *base, uint32_t cc, uint32_t rdst, uint32_t rsrc1, uint32_t rsrc0) { - REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)CY_CRYPTO_VU_NOR_REG_OPC << CY_CRYPTO_OPCODE_POS) | + Cy_Crypto_Core_Vu_RunInstr(base, CY_CRYPTO_SYNC_NON_BLOCKING, + (uint32_t)CY_CRYPTO_VU_NOR_REG_OPC, ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)rsrc1 << CY_CRYPTO_RSRC4_SHIFT) | @@ -398,7 +419,8 @@ __STATIC_INLINE void CY_CRYPTO_VU_NOR_REG (CRYPTO_Type *base, uint32_t rdst, uin __STATIC_INLINE void CY_CRYPTO_VU_COND_NAND_REG (CRYPTO_Type *base, uint32_t cc, uint32_t rdst, uint32_t rsrc1, uint32_t rsrc0) { - REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)CY_CRYPTO_VU_NAND_REG_OPC << CY_CRYPTO_OPCODE_POS) | + Cy_Crypto_Core_Vu_RunInstr(base, CY_CRYPTO_SYNC_NON_BLOCKING, + (uint32_t)CY_CRYPTO_VU_NAND_REG_OPC, ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)rsrc1 << CY_CRYPTO_RSRC4_SHIFT) | @@ -412,7 +434,8 @@ __STATIC_INLINE void CY_CRYPTO_VU_NAND_REG (CRYPTO_Type *base, uint32_t rdst, ui __STATIC_INLINE void CY_CRYPTO_VU_COND_MIN_REG (CRYPTO_Type *base, uint32_t cc, uint32_t rdst, uint32_t rsrc1, uint32_t rsrc0) { - REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)CY_CRYPTO_VU_MIN_REG_OPC << CY_CRYPTO_OPCODE_POS) | + Cy_Crypto_Core_Vu_RunInstr(base, CY_CRYPTO_SYNC_NON_BLOCKING, + (uint32_t)CY_CRYPTO_VU_MIN_REG_OPC, ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)rsrc1 << CY_CRYPTO_RSRC4_SHIFT) | @@ -426,7 +449,8 @@ __STATIC_INLINE void CY_CRYPTO_VU_MIN_REG (CRYPTO_Type *base, uint32_t rdst, uin __STATIC_INLINE void CY_CRYPTO_VU_COND_MAX_REG (CRYPTO_Type *base, uint32_t cc, uint32_t rdst, uint32_t rsrc1, uint32_t rsrc0) { - REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)CY_CRYPTO_VU_MAX_REG_OPC << CY_CRYPTO_OPCODE_POS) | + Cy_Crypto_Core_Vu_RunInstr(base, CY_CRYPTO_SYNC_NON_BLOCKING, + (uint32_t)CY_CRYPTO_VU_MAX_REG_OPC, ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)rsrc1 << CY_CRYPTO_RSRC4_SHIFT) | @@ -440,8 +464,9 @@ __STATIC_INLINE void CY_CRYPTO_VU_MAX_REG (CRYPTO_Type *base, uint32_t rdst, uin __STATIC_INLINE void CY_CRYPTO_VU_COND_PUSH_REG (CRYPTO_Type *base, uint32_t cc) { - REG_CRYPTO_INSTR_FF_WR(base) = ((uint32_t)CY_CRYPTO_VU_PUSH_REG_OPC << CY_CRYPTO_OPCODE_POS) | - ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT); + Cy_Crypto_Core_Vu_RunInstr(base, CY_CRYPTO_SYNC_NON_BLOCKING, + (uint32_t)CY_CRYPTO_VU_PUSH_REG_OPC, + ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT)); } __STATIC_INLINE void CY_CRYPTO_VU_PUSH_REG (CRYPTO_Type *base) @@ -451,8 +476,9 @@ __STATIC_INLINE void CY_CRYPTO_VU_PUSH_REG (CRYPTO_Type *base) __STATIC_INLINE void CY_CRYPTO_VU_COND_POP_REG (CRYPTO_Type *base, uint32_t cc) { - REG_CRYPTO_INSTR_FF_WR(base) = ((uint32_t)CY_CRYPTO_VU_POP_REG_OPC << CY_CRYPTO_OPCODE_POS) | - ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT); + Cy_Crypto_Core_Vu_RunInstr(base, CY_CRYPTO_SYNC_NON_BLOCKING, + (uint32_t)CY_CRYPTO_VU_POP_REG_OPC, + ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT)); } __STATIC_INLINE void CY_CRYPTO_VU_POP_REG (CRYPTO_Type *base) @@ -462,10 +488,12 @@ __STATIC_INLINE void CY_CRYPTO_VU_POP_REG (CRYPTO_Type *base) __STATIC_INLINE void CY_CRYPTO_VU_COND_ALLOC_MEM (CRYPTO_Type *base, uint32_t cc, uint32_t rdst, uint32_t size) { - REG_CRYPTO_INSTR_FF_WR(base) = - (((uint32_t)CY_CRYPTO_VU_ALLOC_MEM_OPC << CY_CRYPTO_OPCODE_POS) | + CY_ASSERT_L1( (uint32_t)(CY_CRYPTO_VU_READ_SP_REG(base) * 4u) >= CY_CRYPTO_BYTE_SIZE_OF_BITS(size) ); + + Cy_Crypto_Core_Vu_RunInstr(base, CY_CRYPTO_SYNC_NON_BLOCKING, + (uint32_t)CY_CRYPTO_VU_ALLOC_MEM_OPC, ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | - ((uint32_t)rdst << ((CY_CRYPTO_HW_V1) ? CY_CRYPTO_RSRC12_SHIFT : CY_CRYPTO_RSRC16_SHIFT)) | + ((uint32_t)rdst << ((CY_CRYPTO_V1) ? CY_CRYPTO_RSRC12_SHIFT : CY_CRYPTO_RSRC16_SHIFT)) | (((uint32_t)size - 1u) << CY_CRYPTO_RSRC0_SHIFT)); } @@ -476,7 +504,8 @@ __STATIC_INLINE void CY_CRYPTO_VU_ALLOC_MEM (CRYPTO_Type *base, uint32_t rdst, u __STATIC_INLINE void CY_CRYPTO_VU_COND_FREE_MEM (CRYPTO_Type *base, uint32_t cc, uint32_t reg_mask) { - REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)CY_CRYPTO_VU_FREE_MEM_OPC << CY_CRYPTO_OPCODE_POS) | + Cy_Crypto_Core_Vu_RunInstr(base, CY_CRYPTO_SYNC_NON_BLOCKING, + (uint32_t)CY_CRYPTO_VU_FREE_MEM_OPC, ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)reg_mask)); } @@ -488,7 +517,8 @@ __STATIC_INLINE void CY_CRYPTO_VU_FREE_MEM (CRYPTO_Type *base, uint32_t reg_mask __STATIC_INLINE void CY_CRYPTO_VU_COND_LSL (CRYPTO_Type *base, uint32_t cc, uint32_t rdst, uint32_t rsrc1, uint32_t rsrc0) { - REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)CY_CRYPTO_VU_LSL_OPC << CY_CRYPTO_OPCODE_POS) | + Cy_Crypto_Core_Vu_RunInstr(base, CY_CRYPTO_SYNC_NON_BLOCKING, + (uint32_t)CY_CRYPTO_VU_LSL_OPC, ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)rsrc1 << CY_CRYPTO_RSRC4_SHIFT) | @@ -502,10 +532,11 @@ __STATIC_INLINE void CY_CRYPTO_VU_LSL (CRYPTO_Type *base, uint32_t rdst, uint32_ __STATIC_INLINE void CY_CRYPTO_VU_COND_LSL1 (CRYPTO_Type *base, uint32_t cc, uint32_t rdst, uint32_t rsrc1) { - if (CY_CRYPTO_HW_V1) + if (CY_CRYPTO_V1) { /******* V1 *********/ - REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)CY_CRYPTO_VU_LSL1_OPC << CY_CRYPTO_OPCODE_POS) | + Cy_Crypto_Core_Vu_RunInstr(base, CY_CRYPTO_SYNC_NON_BLOCKING, + (uint32_t)CY_CRYPTO_VU_LSL1_OPC, ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)rsrc1 << CY_CRYPTO_RSRC4_SHIFT)); @@ -513,7 +544,8 @@ __STATIC_INLINE void CY_CRYPTO_VU_COND_LSL1 (CRYPTO_Type *base, uint32_t cc, uin else { /******* V2 *********/ - REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)CY_CRYPTO_VU_LSL1_OPC << CY_CRYPTO_OPCODE_POS) | + Cy_Crypto_Core_Vu_RunInstr(base, CY_CRYPTO_SYNC_NON_BLOCKING, + (uint32_t)CY_CRYPTO_VU_LSL1_OPC, ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)rsrc1 << CY_CRYPTO_RSRC4_SHIFT) | @@ -528,10 +560,11 @@ __STATIC_INLINE void CY_CRYPTO_VU_LSL1 (CRYPTO_Type *base, uint32_t rdst, uint32 __STATIC_INLINE void CY_CRYPTO_VU_COND_LSL1_WITH_CARRY (CRYPTO_Type *base, uint32_t cc, uint32_t rdst, uint32_t rsrc1) { - if (CY_CRYPTO_HW_V1) + if (CY_CRYPTO_V1) { /******* V1 *********/ - REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)CY_CRYPTO_VU_LSL1_WITH_CARRY_OPC << CY_CRYPTO_OPCODE_POS) | + Cy_Crypto_Core_Vu_RunInstr(base, CY_CRYPTO_SYNC_NON_BLOCKING, + (uint32_t)CY_CRYPTO_VU_LSL1_WITH_CARRY_OPC, ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)rsrc1 << CY_CRYPTO_RSRC4_SHIFT)); @@ -539,7 +572,8 @@ __STATIC_INLINE void CY_CRYPTO_VU_COND_LSL1_WITH_CARRY (CRYPTO_Type *base, uint3 else { /******* V2 *********/ - REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)CY_CRYPTO_VU_LSL1_WITH_CARRY_OPC << CY_CRYPTO_OPCODE_POS) | + Cy_Crypto_Core_Vu_RunInstr(base, CY_CRYPTO_SYNC_NON_BLOCKING, + (uint32_t)CY_CRYPTO_VU_LSL1_WITH_CARRY_OPC, ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)rsrc1 << CY_CRYPTO_RSRC4_SHIFT) | @@ -554,7 +588,8 @@ __STATIC_INLINE void CY_CRYPTO_VU_LSL1_WITH_CARRY (CRYPTO_Type *base, uint32_t r __STATIC_INLINE void CY_CRYPTO_VU_COND_LSR (CRYPTO_Type *base, uint32_t cc, uint32_t rdst, uint32_t rsrc1, uint32_t rsrc0) { - REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)((CY_CRYPTO_HW_V1) ? CY_CRYPTO_VU1_LSR_OPC : CY_CRYPTO_VU2_LSR_OPC) << CY_CRYPTO_OPCODE_POS) | + Cy_Crypto_Core_Vu_RunInstr(base, CY_CRYPTO_SYNC_NON_BLOCKING, + (uint32_t)((CY_CRYPTO_V1) ? CY_CRYPTO_VU1_LSR_OPC : CY_CRYPTO_VU2_LSR_OPC), ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)rsrc1 << CY_CRYPTO_RSRC4_SHIFT) | @@ -568,10 +603,11 @@ __STATIC_INLINE void CY_CRYPTO_VU_LSR (CRYPTO_Type *base, uint32_t rdst, uint32_ __STATIC_INLINE void CY_CRYPTO_VU_COND_LSR1 (CRYPTO_Type *base, uint32_t cc, uint32_t rdst, uint32_t rsrc1) { - if (CY_CRYPTO_HW_V1) + if (CY_CRYPTO_V1) { /******* V1 *********/ - REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)(CY_CRYPTO_VU1_LSR1_OPC) << CY_CRYPTO_OPCODE_POS) | + Cy_Crypto_Core_Vu_RunInstr(base, CY_CRYPTO_SYNC_NON_BLOCKING, + (uint32_t)CY_CRYPTO_VU1_LSR1_OPC, ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)rsrc1 << CY_CRYPTO_RSRC4_SHIFT)); @@ -579,7 +615,8 @@ __STATIC_INLINE void CY_CRYPTO_VU_COND_LSR1 (CRYPTO_Type *base, uint32_t cc, uin else { /******* V2 *********/ - REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)(CY_CRYPTO_VU2_LSR1_OPC) << CY_CRYPTO_OPCODE_POS) | + Cy_Crypto_Core_Vu_RunInstr(base, CY_CRYPTO_SYNC_NON_BLOCKING, + (uint32_t)CY_CRYPTO_VU2_LSR1_OPC, ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)rsrc1 << CY_CRYPTO_RSRC4_SHIFT) | @@ -594,10 +631,11 @@ __STATIC_INLINE void CY_CRYPTO_VU_LSR1 (CRYPTO_Type *base, uint32_t rdst, uint32 __STATIC_INLINE void CY_CRYPTO_VU_COND_LSR1_WITH_CARRY (CRYPTO_Type *base, uint32_t cc, uint32_t rdst, uint32_t rsrc1) { - if (CY_CRYPTO_HW_V1) + if (CY_CRYPTO_V1) { /******* V1 *********/ - REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)(CY_CRYPTO_VU1_LSR1_WITH_CARRY_OPC) << CY_CRYPTO_OPCODE_POS) | + Cy_Crypto_Core_Vu_RunInstr(base, CY_CRYPTO_SYNC_NON_BLOCKING, + (uint32_t)CY_CRYPTO_VU1_LSR1_WITH_CARRY_OPC, ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)rsrc1 << CY_CRYPTO_RSRC4_SHIFT)); @@ -605,7 +643,8 @@ __STATIC_INLINE void CY_CRYPTO_VU_COND_LSR1_WITH_CARRY (CRYPTO_Type *base, uint3 else { /******* V2 *********/ - REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)(CY_CRYPTO_VU2_LSR1_WITH_CARRY_OPC) << CY_CRYPTO_OPCODE_POS) | + Cy_Crypto_Core_Vu_RunInstr(base, CY_CRYPTO_SYNC_NON_BLOCKING, + (uint32_t)CY_CRYPTO_VU2_LSR1_WITH_CARRY_OPC, ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)rsrc1 << CY_CRYPTO_RSRC4_SHIFT) | @@ -620,7 +659,8 @@ __STATIC_INLINE void CY_CRYPTO_VU_LSR1_WITH_CARRY (CRYPTO_Type *base, uint32_t r __STATIC_INLINE void CY_CRYPTO_VU_COND_CLSAME (CRYPTO_Type *base, uint32_t cc, uint32_t rdst, uint32_t rsrc1, uint32_t rsrc0) { - REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)((CY_CRYPTO_HW_V1) ? CY_CRYPTO_VU1_CLSAME_OPC : CY_CRYPTO_VU2_CLSAME_OPC) << CY_CRYPTO_OPCODE_POS) | + Cy_Crypto_Core_Vu_RunInstr(base, CY_CRYPTO_SYNC_NON_BLOCKING, + (uint32_t)((CY_CRYPTO_V1) ? CY_CRYPTO_VU1_CLSAME_OPC : CY_CRYPTO_VU2_CLSAME_OPC), ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)rsrc1 << CY_CRYPTO_RSRC4_SHIFT) | @@ -634,7 +674,8 @@ __STATIC_INLINE void CY_CRYPTO_VU_CLSAME (CRYPTO_Type *base, uint32_t rdst, uint __STATIC_INLINE void CY_CRYPTO_VU_COND_CTSAME (CRYPTO_Type *base, uint32_t cc, uint32_t rdst, uint32_t rsrc1, uint32_t rsrc0) { - REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)((CY_CRYPTO_HW_V1) ? CY_CRYPTO_VU1_CTSAME_OPC : CY_CRYPTO_VU2_CTSAME_OPC) << CY_CRYPTO_OPCODE_POS) | + Cy_Crypto_Core_Vu_RunInstr(base, CY_CRYPTO_SYNC_NON_BLOCKING, + (uint32_t)((CY_CRYPTO_V1) ? CY_CRYPTO_VU1_CTSAME_OPC : CY_CRYPTO_VU2_CTSAME_OPC), ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)rsrc1 << CY_CRYPTO_RSRC4_SHIFT) | @@ -646,9 +687,10 @@ __STATIC_INLINE void CY_CRYPTO_VU_CTSAME (CRYPTO_Type *base, uint32_t rdst, uint CY_CRYPTO_VU_COND_CTSAME (base, CY_CRYPTO_VU_COND_ALWAYS, rdst, rsrc1, rsrc0); } - __STATIC_INLINE void CY_CRYPTO_VU_COND_SET_BIT (CRYPTO_Type *base, uint32_t cc, uint32_t rdst, uint32_t rsrc) - { - REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)((CY_CRYPTO_HW_V1) ? CY_CRYPTO_VU1_SET_BIT_OPC : CY_CRYPTO_VU2_SET_BIT_OPC) << CY_CRYPTO_OPCODE_POS) | +__STATIC_INLINE void CY_CRYPTO_VU_COND_SET_BIT (CRYPTO_Type *base, uint32_t cc, uint32_t rdst, uint32_t rsrc) +{ + Cy_Crypto_Core_Vu_RunInstr(base, CY_CRYPTO_SYNC_NON_BLOCKING, + (uint32_t)((CY_CRYPTO_V1) ? CY_CRYPTO_VU1_SET_BIT_OPC : CY_CRYPTO_VU2_SET_BIT_OPC), ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)rsrc << CY_CRYPTO_RSRC0_SHIFT)); @@ -661,7 +703,8 @@ __STATIC_INLINE void CY_CRYPTO_VU_SET_BIT (CRYPTO_Type *base, uint32_t rdst, uin __STATIC_INLINE void CY_CRYPTO_VU_COND_CLR_BIT (CRYPTO_Type *base, uint32_t cc, uint32_t rdst, uint32_t rsrc) { - REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)((CY_CRYPTO_HW_V1) ? CY_CRYPTO_VU1_CLR_BIT_OPC : CY_CRYPTO_VU2_CLR_BIT_OPC) << CY_CRYPTO_OPCODE_POS) | + Cy_Crypto_Core_Vu_RunInstr(base, CY_CRYPTO_SYNC_NON_BLOCKING, + (uint32_t)((CY_CRYPTO_V1) ? CY_CRYPTO_VU1_CLR_BIT_OPC : CY_CRYPTO_VU2_CLR_BIT_OPC), ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)rsrc << CY_CRYPTO_RSRC0_SHIFT)); @@ -674,7 +717,8 @@ __STATIC_INLINE void CY_CRYPTO_VU_CLR_BIT (CRYPTO_Type *base, uint32_t rdst, uin __STATIC_INLINE void CY_CRYPTO_VU_COND_INV_BIT (CRYPTO_Type *base, uint32_t cc, uint32_t rdst, uint32_t rsrc) { - REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)((CY_CRYPTO_HW_V1) ? CY_CRYPTO_VU1_INV_BIT_OPC : CY_CRYPTO_VU2_INV_BIT_OPC) << CY_CRYPTO_OPCODE_POS) | + Cy_Crypto_Core_Vu_RunInstr(base, CY_CRYPTO_SYNC_NON_BLOCKING, + (uint32_t)((CY_CRYPTO_V1) ? CY_CRYPTO_VU1_INV_BIT_OPC : CY_CRYPTO_VU2_INV_BIT_OPC), ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)rsrc << CY_CRYPTO_RSRC0_SHIFT)); @@ -687,7 +731,8 @@ __STATIC_INLINE void CY_CRYPTO_VU_INV_BIT (CRYPTO_Type *base, uint32_t rdst, uin __STATIC_INLINE void CY_CRYPTO_VU_COND_GET_BIT (CRYPTO_Type *base, uint32_t cc, uint32_t rdst, uint32_t rsrc1, uint32_t rsrc0) { - REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)((CY_CRYPTO_HW_V1) ? CY_CRYPTO_VU1_GET_BIT_OPC : CY_CRYPTO_VU2_GET_BIT_OPC) << CY_CRYPTO_OPCODE_POS) | + Cy_Crypto_Core_Vu_RunInstr(base, CY_CRYPTO_SYNC_NON_BLOCKING, + (uint32_t)((CY_CRYPTO_V1) ? CY_CRYPTO_VU1_GET_BIT_OPC : CY_CRYPTO_VU2_GET_BIT_OPC), ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)rsrc1 << CY_CRYPTO_RSRC4_SHIFT) | @@ -702,7 +747,7 @@ __STATIC_INLINE void CY_CRYPTO_VU_GET_BIT (CRYPTO_Type *base, uint32_t rdst, uin /******************************************************************************/ __STATIC_INLINE void CY_CRYPTO_VU_COND_SET_BIT_IMM (CRYPTO_Type *base, uint32_t cc, uint32_t rdst, uint32_t imm13) { - if (CY_CRYPTO_HW_V1) + if (CY_CRYPTO_V1) { /******** V1 ********/ uint32_t tmpReg = (rdst != CY_CRYPTO_VU_HW_REG14) ? CY_CRYPTO_VU_HW_REG14 : CY_CRYPTO_VU_HW_REG13; @@ -713,12 +758,15 @@ __STATIC_INLINE void CY_CRYPTO_VU_COND_SET_BIT_IMM (CRYPTO_Type *base, uint32_t CY_CRYPTO_VU_SET_REG(base, tmpReg, imm13, 13u); CY_CRYPTO_VU_COND_SET_BIT(base, cc, rdst, tmpReg); + CY_CRYPTO_VU1_WAIT_FOR_COMPLETE(base); + CY_CRYPTO_VU_RESTORE_REG(base, tmpReg, tmpData); } else { /******** V2 ********/ - REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)CY_CRYPTO_VU2_SET_BIT_IMM_OPC << CY_CRYPTO_OPCODE_POS) | + Cy_Crypto_Core_Vu_RunInstr(base, CY_CRYPTO_SYNC_NON_BLOCKING, + (uint32_t)CY_CRYPTO_VU2_SET_BIT_IMM_OPC, ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC16_SHIFT) | ((uint32_t)imm13 << CY_CRYPTO_RSRC0_SHIFT)); @@ -732,7 +780,7 @@ __STATIC_INLINE void CY_CRYPTO_VU_SET_BIT_IMM (CRYPTO_Type *base, uint32_t rdst, __STATIC_INLINE void CY_CRYPTO_VU_COND_CLR_BIT_IMM (CRYPTO_Type *base, uint32_t cc, uint32_t rdst, uint32_t imm13) { - if (CY_CRYPTO_HW_V1) + if (CY_CRYPTO_V1) { /******** V1 ********/ uint32_t tmpReg = (rdst != CY_CRYPTO_VU_HW_REG14) ? CY_CRYPTO_VU_HW_REG14 : CY_CRYPTO_VU_HW_REG13; @@ -743,12 +791,15 @@ __STATIC_INLINE void CY_CRYPTO_VU_COND_CLR_BIT_IMM (CRYPTO_Type *base, uint32_t CY_CRYPTO_VU_SET_REG(base, tmpReg, imm13, 13u); CY_CRYPTO_VU_COND_CLR_BIT(base, cc, rdst, tmpReg); + CY_CRYPTO_VU1_WAIT_FOR_COMPLETE(base); + CY_CRYPTO_VU_RESTORE_REG(base, tmpReg, tmpData); } else { /******** V2 ********/ - REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)CY_CRYPTO_VU2_CLR_BIT_IMM_OPC << CY_CRYPTO_OPCODE_POS) | + Cy_Crypto_Core_Vu_RunInstr(base, CY_CRYPTO_SYNC_NON_BLOCKING, + (uint32_t)CY_CRYPTO_VU2_CLR_BIT_IMM_OPC, ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC16_SHIFT) | ((uint32_t)imm13 << CY_CRYPTO_RSRC0_SHIFT)); @@ -762,7 +813,7 @@ __STATIC_INLINE void CY_CRYPTO_VU_CLR_BIT_IMM (CRYPTO_Type *base, uint32_t rdst, __STATIC_INLINE void CY_CRYPTO_VU_COND_INV_BIT_IMM (CRYPTO_Type *base, uint32_t cc, uint32_t rdst, uint32_t imm13) { - if (CY_CRYPTO_HW_V1) + if (CY_CRYPTO_V1) { /******** V1 ********/ uint32_t tmpReg = (rdst != CY_CRYPTO_VU_HW_REG14) ? CY_CRYPTO_VU_HW_REG14 : CY_CRYPTO_VU_HW_REG13; @@ -773,12 +824,15 @@ __STATIC_INLINE void CY_CRYPTO_VU_COND_INV_BIT_IMM (CRYPTO_Type *base, uint32_t CY_CRYPTO_VU_SET_REG(base, tmpReg, imm13, 13u); CY_CRYPTO_VU_COND_INV_BIT(base, cc, rdst, tmpReg); + CY_CRYPTO_VU1_WAIT_FOR_COMPLETE(base); + CY_CRYPTO_VU_RESTORE_REG(base, tmpReg, tmpData); } else { /******** V2 ********/ - REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)CY_CRYPTO_VU2_INV_BIT_IMM_OPC << CY_CRYPTO_OPCODE_POS) | + Cy_Crypto_Core_Vu_RunInstr(base, CY_CRYPTO_SYNC_NON_BLOCKING, + (uint32_t)CY_CRYPTO_VU2_INV_BIT_IMM_OPC, ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC16_SHIFT) | ((uint32_t)imm13 << CY_CRYPTO_RSRC0_SHIFT)); @@ -793,7 +847,8 @@ __STATIC_INLINE void CY_CRYPTO_VU_INV_BIT_IMM (CRYPTO_Type *base, uint32_t rdst, /******************************************************************************/ __STATIC_INLINE void CY_CRYPTO_VU_COND_TST (CRYPTO_Type *base, uint32_t cc, uint32_t rsrc) { - REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)CY_CRYPTO_VU_TST_OPC << CY_CRYPTO_OPCODE_POS) | + Cy_Crypto_Core_Vu_RunInstr(base, CY_CRYPTO_SYNC_NON_BLOCKING, + (uint32_t)CY_CRYPTO_VU_TST_OPC, ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rsrc << CY_CRYPTO_RSRC0_SHIFT)); } @@ -805,7 +860,8 @@ __STATIC_INLINE void CY_CRYPTO_VU_TST (CRYPTO_Type *base, uint32_t rsrc) __STATIC_INLINE void CY_CRYPTO_VU_COND_MOV (CRYPTO_Type *base, uint32_t cc, uint32_t rdst, uint32_t rsrc) { - REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)CY_CRYPTO_VU_MOV_OPC << CY_CRYPTO_OPCODE_POS) | + Cy_Crypto_Core_Vu_RunInstr(base, CY_CRYPTO_SYNC_NON_BLOCKING, + (uint32_t)CY_CRYPTO_VU_MOV_OPC, ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)rsrc << CY_CRYPTO_RSRC0_SHIFT)); @@ -818,7 +874,8 @@ __STATIC_INLINE void CY_CRYPTO_VU_MOV (CRYPTO_Type *base, uint32_t rdst, uint32_ __STATIC_INLINE void CY_CRYPTO_VU_COND_XSQUARE (CRYPTO_Type *base, uint32_t cc, uint32_t rdst, uint32_t rsrc) { - REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)CY_CRYPTO_VU_XSQUARE_OPC << CY_CRYPTO_OPCODE_POS) | + Cy_Crypto_Core_Vu_RunInstr(base, CY_CRYPTO_SYNC_NON_BLOCKING, + (uint32_t)CY_CRYPTO_VU_XSQUARE_OPC, ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)rsrc << CY_CRYPTO_RSRC0_SHIFT)); @@ -831,7 +888,8 @@ __STATIC_INLINE void CY_CRYPTO_VU_XSQUARE (CRYPTO_Type *base, uint32_t rdst, uin __STATIC_INLINE void CY_CRYPTO_VU_COND_XMUL (CRYPTO_Type *base, uint32_t cc, uint32_t rdst, uint32_t rsrc1, uint32_t rsrc0) { - REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)CY_CRYPTO_VU_XMUL_OPC << CY_CRYPTO_OPCODE_POS) | + Cy_Crypto_Core_Vu_RunInstr(base, CY_CRYPTO_SYNC_NON_BLOCKING, + (uint32_t)CY_CRYPTO_VU_XMUL_OPC, ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)rsrc1 << CY_CRYPTO_RSRC4_SHIFT) | @@ -846,7 +904,8 @@ __STATIC_INLINE void CY_CRYPTO_VU_XMUL (CRYPTO_Type *base, uint32_t rdst, uint32 __STATIC_INLINE void CY_CRYPTO_VU_COND_UMUL (CRYPTO_Type *base, uint32_t cc, uint32_t rdst, uint32_t rsrc1, uint32_t rsrc0) { - REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)CY_CRYPTO_VU_UMUL_OPC << CY_CRYPTO_OPCODE_POS) | + Cy_Crypto_Core_Vu_RunInstr(base, CY_CRYPTO_SYNC_NON_BLOCKING, + (uint32_t)CY_CRYPTO_VU_UMUL_OPC, ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)rsrc1 << CY_CRYPTO_RSRC4_SHIFT) | @@ -860,7 +919,7 @@ __STATIC_INLINE void CY_CRYPTO_VU_UMUL (CRYPTO_Type *base, uint32_t rdst, uint32 __STATIC_INLINE void CY_CRYPTO_VU_COND_USQUARE (CRYPTO_Type *base, uint32_t cc, uint32_t rdst, uint32_t rsrc) { - if (CY_CRYPTO_HW_V1) + if (CY_CRYPTO_V1) { /***** V1 *******/ CY_CRYPTO_VU_COND_UMUL(base, cc, rdst, rsrc, rsrc); @@ -868,7 +927,8 @@ __STATIC_INLINE void CY_CRYPTO_VU_COND_USQUARE (CRYPTO_Type *base, uint32_t cc, else { /***** V2 *******/ - REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)CY_CRYPTO_VU2_USQUARE_OPC << CY_CRYPTO_OPCODE_POS) | + Cy_Crypto_Core_Vu_RunInstr(base, CY_CRYPTO_SYNC_NON_BLOCKING, + (uint32_t)CY_CRYPTO_VU2_USQUARE_OPC, ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)rsrc << CY_CRYPTO_RSRC0_SHIFT)); @@ -882,7 +942,8 @@ __STATIC_INLINE void CY_CRYPTO_VU_USQUARE (CRYPTO_Type *base, uint32_t rdst, uin __STATIC_INLINE void CY_CRYPTO_VU_COND_SET_TO_ZERO (CRYPTO_Type *base, uint32_t cc, uint32_t rdst) { - REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)CY_CRYPTO_VU_SET_TO_ZERO_OPC << CY_CRYPTO_OPCODE_POS) | + Cy_Crypto_Core_Vu_RunInstr(base, CY_CRYPTO_SYNC_NON_BLOCKING, + (uint32_t)CY_CRYPTO_VU_SET_TO_ZERO_OPC, ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT)); } @@ -894,7 +955,8 @@ __STATIC_INLINE void CY_CRYPTO_VU_SET_TO_ZERO (CRYPTO_Type *base, uint32_t rdst) __STATIC_INLINE void CY_CRYPTO_VU_COND_SET_TO_ONE (CRYPTO_Type *base, uint32_t cc, uint32_t rdst) { - REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)CY_CRYPTO_VU_SET_TO_ONE_OPC << CY_CRYPTO_OPCODE_POS) | + Cy_Crypto_Core_Vu_RunInstr(base, CY_CRYPTO_SYNC_NON_BLOCKING, + (uint32_t)CY_CRYPTO_VU_SET_TO_ONE_OPC, ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT)); } @@ -906,7 +968,8 @@ __STATIC_INLINE void CY_CRYPTO_VU_SET_TO_ONE (CRYPTO_Type *base, uint32_t rdst) __STATIC_INLINE void CY_CRYPTO_VU_COND_ADD (CRYPTO_Type *base, uint32_t cc, uint32_t rdst, uint32_t rsrc1, uint32_t rsrc0) { - REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)CY_CRYPTO_VU_ADD_OPC << CY_CRYPTO_OPCODE_POS) | + Cy_Crypto_Core_Vu_RunInstr(base, CY_CRYPTO_SYNC_NON_BLOCKING, + (uint32_t)CY_CRYPTO_VU_ADD_OPC, ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)rsrc1 << CY_CRYPTO_RSRC4_SHIFT) | @@ -920,7 +983,7 @@ __STATIC_INLINE void CY_CRYPTO_VU_ADD (CRYPTO_Type *base, uint32_t rdst, uint32_ __STATIC_INLINE void CY_CRYPTO_VU_COND_SUB (CRYPTO_Type *base, uint32_t cc, uint32_t rdst, uint32_t rsrc1, uint32_t rsrc0) { - REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)CY_CRYPTO_VU_SUB_OPC << CY_CRYPTO_OPCODE_POS) | + Cy_Crypto_Core_Vu_RunInstr(base, CY_CRYPTO_SYNC_NON_BLOCKING, (uint32_t)CY_CRYPTO_VU_SUB_OPC, ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)rsrc1 << CY_CRYPTO_RSRC4_SHIFT) | @@ -934,7 +997,8 @@ __STATIC_INLINE void CY_CRYPTO_VU_SUB (CRYPTO_Type *base, uint32_t rdst, uint32_ __STATIC_INLINE void CY_CRYPTO_VU_COND_OR (CRYPTO_Type *base, uint32_t cc, uint32_t rdst, uint32_t rsrc1, uint32_t rsrc0) { - REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)CY_CRYPTO_VU_OR_OPC << CY_CRYPTO_OPCODE_POS) | + Cy_Crypto_Core_Vu_RunInstr(base, CY_CRYPTO_SYNC_NON_BLOCKING, + (uint32_t)CY_CRYPTO_VU_OR_OPC, ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)rsrc1 << CY_CRYPTO_RSRC4_SHIFT) | @@ -948,7 +1012,8 @@ __STATIC_INLINE void CY_CRYPTO_VU_OR (CRYPTO_Type *base, uint32_t rdst, uint32_t __STATIC_INLINE void CY_CRYPTO_VU_COND_AND (CRYPTO_Type *base, uint32_t cc, uint32_t rdst, uint32_t rsrc1, uint32_t rsrc0) { - REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)CY_CRYPTO_VU_AND_OPC << CY_CRYPTO_OPCODE_POS) | + Cy_Crypto_Core_Vu_RunInstr(base, CY_CRYPTO_SYNC_NON_BLOCKING, + (uint32_t)CY_CRYPTO_VU_AND_OPC, ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)rsrc1 << CY_CRYPTO_RSRC4_SHIFT) | @@ -962,7 +1027,7 @@ __STATIC_INLINE void CY_CRYPTO_VU_AND (CRYPTO_Type *base, uint32_t rdst, uint32_ __STATIC_INLINE void CY_CRYPTO_VU_COND_XOR (CRYPTO_Type *base, uint32_t cc, uint32_t rdst, uint32_t rsrc1, uint32_t rsrc0) { - REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)CY_CRYPTO_VU_XOR_OPC << CY_CRYPTO_OPCODE_POS) | + Cy_Crypto_Core_Vu_RunInstr(base, CY_CRYPTO_SYNC_NON_BLOCKING, (uint32_t)CY_CRYPTO_VU_XOR_OPC, ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)rsrc1 << CY_CRYPTO_RSRC4_SHIFT) | @@ -976,7 +1041,8 @@ __STATIC_INLINE void CY_CRYPTO_VU_XOR (CRYPTO_Type *base, uint32_t rdst, uint32_ __STATIC_INLINE void CY_CRYPTO_VU_COND_NOR (CRYPTO_Type *base, uint32_t cc, uint32_t rdst, uint32_t rsrc1, uint32_t rsrc0) { - REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)CY_CRYPTO_VU_NOR_OPC << CY_CRYPTO_OPCODE_POS) | + Cy_Crypto_Core_Vu_RunInstr(base, CY_CRYPTO_SYNC_NON_BLOCKING, + (uint32_t)CY_CRYPTO_VU_NOR_OPC, ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)rsrc1 << CY_CRYPTO_RSRC4_SHIFT) | @@ -990,7 +1056,8 @@ __STATIC_INLINE void CY_CRYPTO_VU_NOR (CRYPTO_Type *base, uint32_t rdst, uint32_ __STATIC_INLINE void CY_CRYPTO_VU_COND_NAND (CRYPTO_Type *base, uint32_t cc, uint32_t rdst, uint32_t rsrc1, uint32_t rsrc0) { - REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)CY_CRYPTO_VU_NAND_OPC << CY_CRYPTO_OPCODE_POS) | + Cy_Crypto_Core_Vu_RunInstr(base, CY_CRYPTO_SYNC_NON_BLOCKING, + (uint32_t)CY_CRYPTO_VU_NAND_OPC, ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)rsrc1 << CY_CRYPTO_RSRC4_SHIFT) | @@ -1004,7 +1071,8 @@ __STATIC_INLINE void CY_CRYPTO_VU_NAND (CRYPTO_Type *base, uint32_t rdst, uint32 __STATIC_INLINE void CY_CRYPTO_VU_COND_CMP_SUB (CRYPTO_Type *base, uint32_t cc, uint32_t rsrc1, uint32_t rsrc0) { - REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)CY_CRYPTO_VU_CMP_SUB_OPC << CY_CRYPTO_OPCODE_POS) | + Cy_Crypto_Core_Vu_RunInstr(base, CY_CRYPTO_SYNC_NON_BLOCKING, + (uint32_t)CY_CRYPTO_VU_CMP_SUB_OPC, ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rsrc1 << CY_CRYPTO_RSRC4_SHIFT) | ((uint32_t)rsrc0 << CY_CRYPTO_RSRC0_SHIFT)); @@ -1017,7 +1085,8 @@ __STATIC_INLINE void CY_CRYPTO_VU_CMP_SUB (CRYPTO_Type *base, uint32_t rsrc1, ui __STATIC_INLINE void CY_CRYPTO_VU_COND_CMP_DEGREE (CRYPTO_Type *base, uint32_t cc, uint32_t rsrc1, uint32_t rsrc0) { - REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)CY_CRYPTO_VU_CMP_DEGREE_OPC << CY_CRYPTO_OPCODE_POS) | + Cy_Crypto_Core_Vu_RunInstr(base, CY_CRYPTO_SYNC_NON_BLOCKING, + (uint32_t)CY_CRYPTO_VU_CMP_DEGREE_OPC, ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rsrc1 << CY_CRYPTO_RSRC4_SHIFT) | ((uint32_t)rsrc0 << CY_CRYPTO_RSRC0_SHIFT)); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_mem.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_mem.h index f779b43e4c..d082ba4962 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_mem.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_mem.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_mem.h -* \version 2.20 +* \version 2.30 * * \brief * This file provides the headers for the memory management API @@ -72,7 +72,7 @@ typedef void (*cy_crypto_memxor_func_t)(CRYPTO_Type *base, void* dst, *******************************************************************************/ __STATIC_INLINE void Cy_Crypto_Core_MemCpy(CRYPTO_Type *base, void* dst, void const *src, uint16_t size) { - if (CY_CRYPTO_HW_V1) + if (CY_CRYPTO_V1) { Cy_Crypto_Core_V1_MemCpy(base, dst, src, size); } @@ -104,7 +104,7 @@ __STATIC_INLINE void Cy_Crypto_Core_MemCpy(CRYPTO_Type *base, void* dst, void co *******************************************************************************/ __STATIC_INLINE void Cy_Crypto_Core_MemSet(CRYPTO_Type *base, void* dst, uint8_t data, uint16_t size) { - if (CY_CRYPTO_HW_V1) + if (CY_CRYPTO_V1) { Cy_Crypto_Core_V1_MemSet(base, dst, data, size); } @@ -140,7 +140,7 @@ __STATIC_INLINE void Cy_Crypto_Core_MemSet(CRYPTO_Type *base, void* dst, uint8_t __STATIC_INLINE uint32_t Cy_Crypto_Core_MemCmp(CRYPTO_Type *base, void const *src0, void const *src1, uint16_t size) { uint32_t tmpResult; - if (CY_CRYPTO_HW_V1) + if (CY_CRYPTO_V1) { tmpResult = Cy_Crypto_Core_V1_MemCmp(base, src0, src1, size); } @@ -179,7 +179,7 @@ __STATIC_INLINE uint32_t Cy_Crypto_Core_MemCmp(CRYPTO_Type *base, void const *sr __STATIC_INLINE void Cy_Crypto_Core_MemXor(CRYPTO_Type *base, void* dst, void const *src0, void const *src1, uint16_t size) { - if (CY_CRYPTO_HW_V1) + if (CY_CRYPTO_V1) { Cy_Crypto_Core_V1_MemXor(base, dst, src0, src1, size); } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_mem_v1.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_mem_v1.h index bd6941a9fc..4b4e049b5c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_mem_v1.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_mem_v1.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_mem_v1.h -* \version 2.20 +* \version 2.30 * * \brief * This file provides the headers for the string management API diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_mem_v2.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_mem_v2.h index a6d38da6ef..44a183d61d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_mem_v2.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_mem_v2.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_mem_v2.h -* \version 2.20 +* \version 2.30 * * \brief * This file provides the headers for the string management API diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_prng.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_prng.h index fcdf41a24b..2013dbdbd6 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_prng.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_prng.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_prng.h -* \version 2.20 +* \version 2.30 * * \brief * This file provides provides constant and parameters for the API of the PRNG @@ -80,7 +80,7 @@ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Prng_Init(CRYPTO_Type *base { cy_en_crypto_status_t tmpResult; - if (CY_CRYPTO_HW_V1) + if (CY_CRYPTO_V1) { tmpResult = Cy_Crypto_Core_V1_Prng_Init(base, lfsr32InitState, lfsr31InitState, lfsr29InitState); } @@ -117,7 +117,7 @@ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Prng(CRYPTO_Type *base, { cy_en_crypto_status_t tmpResult; - if (CY_CRYPTO_HW_V1) + if (CY_CRYPTO_V1) { tmpResult = Cy_Crypto_Core_V1_Prng(base, max, randomNum); } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_prng_v1.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_prng_v1.h index 0c00a627eb..df55388704 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_prng_v1.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_prng_v1.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_prng.h -* \version 2.20 +* \version 2.30 * * \brief * This file provides provides constant and parameters for the API of the PRNG diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_prng_v2.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_prng_v2.h index 8860350f85..b7c8a561ac 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_prng_v2.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_prng_v2.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_prng_v2.h -* \version 2.20 +* \version 2.30 * * \brief * This file provides provides constant and parameters for the API of the PRNG diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_rsa.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_rsa.h index ea20f4f1da..a7115a323e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_rsa.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_rsa.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_rsa.h -* \version 2.20 +* \version 2.30 * * \brief * This file provides provides constant and parameters diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_sha.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_sha.h index caf2e587fe..9067f23177 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_sha.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_sha.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_sha.h -* \version 2.20 +* \version 2.30 * * \brief * This file provides constants and function prototypes @@ -80,7 +80,7 @@ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Sha(CRYPTO_Type *base, { cy_en_crypto_status_t tmpResult; - if (CY_CRYPTO_HW_V1) + if (CY_CRYPTO_V1) { tmpResult = Cy_Crypto_Core_V1_Sha(base, message, messageSize, digest, mode); } @@ -122,7 +122,7 @@ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Sha_Init(CRYPTO_Type *base, { cy_en_crypto_status_t tmpResult; - if (CY_CRYPTO_HW_V1) + if (CY_CRYPTO_V1) { tmpResult = Cy_Crypto_Core_V1_Sha_Init(base, shaHashState, mode, shaBuffers); } @@ -154,7 +154,7 @@ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Sha_Start(CRYPTO_Type *base { cy_en_crypto_status_t tmpResult; - if (CY_CRYPTO_HW_V1) + if (CY_CRYPTO_V1) { tmpResult = Cy_Crypto_Core_V1_Sha_Start(base, hashState); } @@ -200,7 +200,7 @@ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Sha_Update(CRYPTO_Type *bas { cy_en_crypto_status_t tmpResult; - if (CY_CRYPTO_HW_V1) + if (CY_CRYPTO_V1) { tmpResult = Cy_Crypto_Core_V1_Sha_Update(base, hashState, message, messageSize); } @@ -237,7 +237,7 @@ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Sha_Finish(CRYPTO_Type *bas { cy_en_crypto_status_t tmpResult; - if (CY_CRYPTO_HW_V1) + if (CY_CRYPTO_V1) { tmpResult = Cy_Crypto_Core_V1_Sha_Finish(base, hashState, digest); } @@ -269,7 +269,7 @@ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Sha_Free(CRYPTO_Type *base, { cy_en_crypto_status_t tmpResult; - if (CY_CRYPTO_HW_V1) + if (CY_CRYPTO_V1) { tmpResult = Cy_Crypto_Core_V1_Sha_Free(base, hashState); } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_sha_v1.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_sha_v1.h index 621272f47e..679e2a64e7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_sha_v1.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_sha_v1.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_sha.h -* \version 2.20 +* \version 2.30 * * \brief * This file provides constants and function prototypes diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_sha_v2.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_sha_v2.h index 11e842b0e0..b39360e3c6 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_sha_v2.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_sha_v2.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_sha_v2.h -* \version 2.20 +* \version 2.30 * * \brief * This file provides constants and function prototypes @@ -37,6 +37,33 @@ /** \cond INTERNAL */ +typedef struct +{ + /* Allocates CRYPTO_MAX_BLOCK_SIZE Bytes for the block. */ + uint32_t block[CY_CRYPTO_SHA1_BLOCK_SIZE / 4u]; + + /* Allocates CRYPTO_MAX_HASH_SIZE Bytes for the hash. */ + uint32_t hash[CY_CRYPTO_SHA1_HASH_SIZE / 4u]; +} cy_stc_crypto_v2_sha1_buffers_t; + +typedef struct +{ + /* Allocates CRYPTO_MAX_BLOCK_SIZE Bytes for the block. */ + uint32_t block[CY_CRYPTO_SHA256_BLOCK_SIZE / 4u]; + + /* Allocates CRYPTO_MAX_HASH_SIZE Bytes for the hash. */ + uint32_t hash[CY_CRYPTO_SHA256_HASH_SIZE / 4u]; +} cy_stc_crypto_v2_sha256_buffers_t; + +typedef struct +{ + /* Allocates CRYPTO_MAX_BLOCK_SIZE Bytes for the block. */ + uint32_t block[CY_CRYPTO_SHA512_BLOCK_SIZE / 4u]; + + /* Allocates CRYPTO_MAX_HASH_SIZE Bytes for the hash. */ + uint32_t hash[CY_CRYPTO_SHA512_HASH_SIZE / 4u]; +} cy_stc_crypto_v2_sha512_buffers_t; + cy_en_crypto_status_t Cy_Crypto_Core_V2_Sha_Init(CRYPTO_Type *base, cy_stc_crypto_sha_state_t *hashState, cy_en_crypto_sha_mode_t mode, diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_trng.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_trng.h index def797749e..0004ec0542 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_trng.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_trng.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_trng.h -* \version 2.20 +* \version 2.30 * * \brief * This file provides provides constant and parameters @@ -79,7 +79,7 @@ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Trng(CRYPTO_Type *base, uint32_t *randomNum) { cy_en_crypto_status_t tmpResult; - if (CY_CRYPTO_HW_V1) + if (CY_CRYPTO_V1) { tmpResult = Cy_Crypto_Core_V1_Trng(base, GAROPol, FIROPol, max, randomNum); } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_trng_config_v1.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_trng_config_v1.h index 0eb516b9b3..f69a4e4c6f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_trng_config_v1.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_trng_config_v1.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_trng_config_v1.h -* \version 2.20 +* \version 2.30 * * \brief * This file provides internal (not public) constants and parameters diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_trng_config_v2.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_trng_config_v2.h index 165b12aeb7..8f87f692b2 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_trng_config_v2.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_trng_config_v2.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_trng_config_v2.h -* \version 2.20 +* \version 2.30 * * \brief * This file provides internal (not public) constants and parameters diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_trng_v1.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_trng_v1.h index b4d79349ec..291c3dec64 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_trng_v1.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_trng_v1.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_trng_v1.h -* \version 2.20 +* \version 2.30 * * \brief * This file provides provides constant and parameters diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_trng_v2.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_trng_v2.h index ad15318b04..87fa46c770 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_trng_v2.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_trng_v2.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_trng_v2.h -* \version 2.20 +* \version 2.30 * * \brief * This file provides provides constant and parameters diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_vu.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_vu.h index c0741a4a27..bb3a9d748a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_vu.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_vu.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_hw.h -* \version 2.20 +* \version 2.30 * * \brief * This file provides the headers to the API for the utils @@ -37,9 +37,6 @@ #include "cy_crypto_core_hw_vu.h" #include -#define CY_CRYPTO_VU_SIZE_FLD_MASK (0x00001fffuL) -#define CY_CRYPTO_VU_DATA_FLD_MASK (0x00003fffuL) -#define CY_CRYPTO_VU_DATA_FLD_POS (16u) /** * \addtogroup group_crypto_lld_vu_functions @@ -293,34 +290,7 @@ __STATIC_INLINE uint16_t Cy_Crypto_Core_Vu_RegDataPtrRead(CRYPTO_Type *base, uin *******************************************************************************/ __STATIC_INLINE uint32_t * Cy_Crypto_Core_Vu_RegMemPointer(CRYPTO_Type *base, uint32_t srcReg) { - return (uint32_t *)((uint32_t)REG_CRYPTO_MEM_BUFF(base) + (4u * (uint32_t)Cy_Crypto_Core_Vu_RegDataPtrRead(base, srcReg))); -} - -/******************************************************************************* -* Function Name: Cy_Crypto_Wait_Vu_ForComplete -****************************************************************************//** -* -* Waits until VU instruction will be completed -* -* \param base -* The pointer to the CRYPTO instance. -* -*******************************************************************************/ -__STATIC_INLINE void Cy_Crypto_Core_Vu_WaitForComplete(CRYPTO_Type *base) -{ - /* Wait until the VU instruction is complete */ - if (CY_CRYPTO_HW_V1) - { - while (0uL != _FLD2VAL(CRYPTO_STATUS_VU_BUSY, REG_CRYPTO_STATUS(base))) - { - } - } - else - { - while (0uL != _FLD2VAL(CRYPTO_V2_STATUS_BUSY, REG_CRYPTO_STATUS(base))) - { - } - } + return (uint32_t *)((uint32_t)REG_CRYPTO_VU_CTL1(base) + (4u * (uint32_t)Cy_Crypto_Core_Vu_RegDataPtrRead(base, srcReg))); } /******************************************************************************* @@ -340,6 +310,21 @@ __STATIC_INLINE uint32_t Cy_Crypto_Core_Vu_StatusRead(CRYPTO_Type *base) return((uint32_t)REG_CRYPTO_VU_STATUS(base)); } +/******************************************************************************* +* Function Name: Cy_Crypto_Core_VU_RegInvertEndianness +****************************************************************************//** +* +* Reverts the memory data block pointed in given register. +* +* \param base +* The pointer to the CRYPTO instance. +* +* \param srcReg +* The source vector unit register. +* +*******************************************************************************/ +void Cy_Crypto_Core_VU_RegInvertEndianness(CRYPTO_Type *base, uint32_t srcReg); + /** \} group_crypto_lld_vu_functions */ #endif /* #if (CPUSS_CRYPTO_VU == 1) */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_server.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_server.h index 99d9ce5996..5502d59a87 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_server.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_server.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_server.h -* \version 2.20 +* \version 2.30 * * \brief * This file provides the prototypes for common API @@ -66,7 +66,7 @@ extern "C" { * \ref cy_en_crypto_status_t * * \funcusage -* \snippet crypto/2.10/snippet/main.c snippet_myCryptoServerStartBase +* \snippet crypto/snippet/main.c snippet_myCryptoServerStartBase * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Server_Start_Base(cy_stc_crypto_config_t const *config, diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_csd.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_csd.h index e6a1abe160..24922529c8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_csd.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_csd.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_csd.h -* \version 1.0.1 +* \version 1.10 * * The header file of the CSD driver. * @@ -105,7 +105,7 @@ * The following code snippet demonstrates how to capture the CSD HW block for * custom implementation: * -* \snippet csd/1.0/snippet/main.c snippet_Cy_CSD_Conversion +* \snippet csd/snippet/main.c snippet_Cy_CSD_Conversion * * The entire solution, either CapSense or CSDADC, in addition to * the CSD HW block, incorporates the following instances: @@ -199,12 +199,12 @@ * The following code snippet demonstrates how to implement a routine to handle * the interrupt. The routine is called when a CSD interrupt is triggered. * -* \snippet csd/1.0/snippet/main.c snippet_Cy_CSD_IntHandler +* \snippet csd/snippet/main.c snippet_Cy_CSD_IntHandler * * The following code snippet demonstrates how to configure and enable * the CSD interrupt: * -* \snippet csd/1.0/snippet/main.c snippet_Cy_CSD_IntEnabling +* \snippet csd/snippet/main.c snippet_Cy_CSD_IntEnabling * * For more information, refer to the \ref group_sysint driver. * @@ -300,15 +300,26 @@ * * * -* -* -* +* +* +* +* +* +* +* * * * -* +* * * +* +* +* +* +* *
    VersionChangesReason for Change
    1.0The initial version.1.10The CSD driver sources are enclosed with the conditional compilation +* to ensure a successful compilation for non-CapSense-capable devices +* Compilation for non-CapSense-capable devices
    Changed the Cy_CSD_GetConversionStatus() function implementationFixed defect
    1.0.1Documentation updates.Documentation updatesImprove user's experience
    1.0The initial version
    */ @@ -334,9 +345,7 @@ #include "cy_device_headers.h" #include "cy_syslib.h" -#ifndef CY_IP_MXCSDV2 - #error "The CSD driver is not supported on this device" -#endif +#if defined(CY_IP_MXCSDV2) #if defined(__cplusplus) extern "C" { @@ -351,7 +360,7 @@ extern "C" { #define CY_CSD_DRV_VERSION_MAJOR (1) /** Driver minor version */ -#define CY_CSD_DRV_VERSION_MINOR (0) +#define CY_CSD_DRV_VERSION_MINOR (10) /****************************************************************************** @@ -782,7 +791,7 @@ __STATIC_INLINE void Cy_CSD_WriteBits(CSD_Type * base, uint32_t offset, uint32_t * * \funcusage * -* \snippet csd/1.0/snippet/main.c snippet_Cy_CSD_CheckKey +* \snippet csd/snippet/main.c snippet_Cy_CSD_CheckKey * *******************************************************************************/ __STATIC_INLINE cy_en_csd_key_t Cy_CSD_GetLockStatus(const CSD_Type * base, const cy_stc_csd_context_t * context) @@ -810,7 +819,7 @@ __STATIC_INLINE cy_en_csd_key_t Cy_CSD_GetLockStatus(const CSD_Type * base, cons * * \funcusage * -* \snippet csd/1.0/snippet/main.c snippet_Cy_CSD_CheckStatus +* \snippet csd/snippet/main.c snippet_Cy_CSD_CheckStatus * *******************************************************************************/ __STATIC_INLINE cy_en_csd_status_t Cy_CSD_GetConversionStatus(const CSD_Type * base, const cy_stc_csd_context_t * context) @@ -818,7 +827,8 @@ __STATIC_INLINE cy_en_csd_status_t Cy_CSD_GetConversionStatus(const CSD_Type * b cy_en_csd_status_t csdStatus = CY_CSD_BUSY; (void)context; - if ((base->SEQ_START & CSD_SEQ_START_START_Msk) == 0u) + if (((base->SEQ_START & CSD_SEQ_START_START_Msk) == 0u) && + ((base->STAT_SEQ & (CSD_STAT_SEQ_SEQ_STATE_Msk | CSD_STAT_SEQ_ADC_STATE_Msk)) == 0u)) { csdStatus = CY_CSD_SUCCESS; } @@ -833,6 +843,8 @@ __STATIC_INLINE cy_en_csd_status_t Cy_CSD_GetConversionStatus(const CSD_Type * b } #endif +#endif /* CY_IP_MXCSDV2 */ + #endif /* CY_CSD_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_device.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_device.h index f60560f49c..6703353340 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_device.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_device.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_device.h -* \version 1.10 +* \version 2.0 * * This file specifies the structure for core and peripheral block HW base * addresses, versions, and parameters. @@ -22,6 +22,31 @@ * See the License for the specific language governing permissions and * limitations under the License. *******************************************************************************/ +/** +* \section group_device_MISRA MISRA-C Compliance +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
    MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
    10.1RThe value of an expression of integer type shall not be implicitly converted to a different underlying type +* under some circumstances.An operand of essentially enum type is being converted to unsigned type as a result of an arithmetic or +* conditional operation. The conversion does not have any unintended effect.
    20.6RThe macro offsetof, in library , shall not be used.The only HW block register offsets are defined using this macro.
    +*/ #ifndef CY_DEVICE_H_ #define CY_DEVICE_H_ @@ -55,7 +80,9 @@ #include "ip/cyip_i2s.h" #include "ip/cyip_pdm.h" #include "ip/cyip_lcd.h" +#include "ip/cyip_lcd_v2.h" #include "ip/cyip_sdhc.h" +#include "ip/cyip_canfd.h" #include "ip/cyip_smartio.h" /* Device descriptor type */ @@ -73,21 +100,19 @@ typedef struct uint32_t ipcBase; uint32_t cryptoBase; - /* IP block versions */ + /* IP block versions: [7:4] major, [3:0] minor */ uint8_t cpussVersion; uint8_t cryptoVersion; uint8_t dwVersion; - uint8_t flashcVersion; - uint8_t gpioVersion; - uint8_t hsiomVersion; uint8_t ipcVersion; uint8_t periVersion; - uint8_t protVersion; + uint8_t srssVersion; /* Parameters */ uint8_t cpussIpcNr; uint8_t cpussIpcIrqNr; - uint8_t cpussDwChNr; + uint8_t cpussDw0ChNr; + uint8_t cpussDw1ChNr; uint8_t cpussFlashPaSize; int16_t cpussIpc0Irq; int16_t cpussFmIrq; @@ -189,7 +214,10 @@ void Cy_PDL_Init(const cy_stc_device_t * device); * Register Access Helper Macros *******************************************************************************/ -#define CY_CRYPTO_HW_V1 (1U == cy_device->cryptoVersion) /* true if the mxcrypto version is 1 */ +#define CY_CRYPTO_V1 (0x20U > cy_device->cryptoVersion) /* true if the mxcrypto version is 1.x */ + +#define CY_SRSS_V1_3 (0x13U == cy_device->srssVersion) +#define CY_SRSS_MFO_PRESENT (CY_SRSS_V1_3) #define CY_SRSS_NUM_CLKPATH ((uint32_t)(cy_device->srssNumClkpath)) #define CY_SRSS_NUM_PLL ((uint32_t)(cy_device->srssNumPll)) @@ -222,6 +250,8 @@ void Cy_PDL_Init(const cy_stc_device_t * device); #define SRSS_CLK_ECO_CONFIG (((SRSS_V1_Type *) SRSS)->CLK_ECO_CONFIG) #define SRSS_CLK_ECO_STATUS (((SRSS_V1_Type *) SRSS)->CLK_ECO_STATUS) #define SRSS_CLK_PILO_CONFIG (((SRSS_V1_Type *) SRSS)->CLK_PILO_CONFIG) +#define SRSS_CLK_MF_SELECT (((SRSS_V1_Type *) SRSS)->CLK_MF_SELECT) /* for CY_SRSS_V1_3 only */ +#define SRSS_CLK_MFO_CONFIG (((SRSS_V1_Type *) SRSS)->CLK_MFO_CONFIG) /* for CY_SRSS_V1_3 only */ #define SRSS_CLK_FLL_CONFIG (((SRSS_V1_Type *) SRSS)->CLK_FLL_CONFIG) #define SRSS_CLK_FLL_CONFIG2 (((SRSS_V1_Type *) SRSS)->CLK_FLL_CONFIG2) #define SRSS_CLK_FLL_CONFIG3 (((SRSS_V1_Type *) SRSS)->CLK_FLL_CONFIG3) @@ -266,6 +296,7 @@ void Cy_PDL_Init(const cy_stc_device_t * device); #define BACKUP_INTR_MASKED (((BACKUP_V1_Type *) BACKUP)->INTR_MASKED) #define BACKUP_RESET (((BACKUP_V1_Type *) BACKUP)->RESET) + /******************************************************************************* * FLASHC *******************************************************************************/ @@ -317,7 +348,7 @@ void Cy_PDL_Init(const cy_stc_device_t * device); * CPUSS *******************************************************************************/ -#define CY_CPUSS_V1 (1U == cy_device->cpussVersion) +#define CY_CPUSS_V1 (0x20U > cy_device->cpussVersion) #define CY_CPUSS_NOT_CONNECTED_IRQN ((uint32_t)(cy_device->cpussNotConnectedIrq)) #define CY_CPUSS_DISCONNECTED_IRQN ((cy_en_intr_t)CY_CPUSS_NOT_CONNECTED_IRQN) @@ -593,9 +624,11 @@ void Cy_PDL_Init(const cy_stc_device_t * device); * DW *******************************************************************************/ -#define CY_DW_V1 (1U == cy_device->dwVersion) -#define CY_DW_CRC (1U < cy_device->dwVersion) -#define CY_DW_CH_NR (cy_device->cpussDwChNr) +#define CY_DW_V1 (0x20U > cy_device->dwVersion) +#define CY_DW_CRC (0x20U <= cy_device->dwVersion) +#define CY_DW0_BASE ((DW_Type*) 0x40280000UL) +#define CY_DW0_CH_NR (cy_device->cpussDw0ChNr) +#define CY_DW1_CH_NR (cy_device->cpussDw1ChNr) #define CY_DW_CH_CTL_PRIO_Pos ((uint32_t)(cy_device->dwChCtlPrioPos)) #define CY_DW_CH_CTL_PRIO_Msk ((uint32_t)(0x3UL << CY_DW_CH_CTL_PRIO_Pos)) @@ -651,7 +684,7 @@ void Cy_PDL_Init(const cy_stc_device_t * device); *******************************************************************************/ #define CY_PERI_BASE ((PERI_V1_Type *) cy_device->periBase) -#define CY_PERI_V1 (1U == cy_device->periVersion) /* true if the mxperi version is 1 */ +#define CY_PERI_V1 (0x20U > cy_device->periVersion) /* true if the mxperi version is 1.x */ #define CY_PERI_V2_TR_GR_SIZE (sizeof(PERI_TR_GR_V2_Type)) #define CY_PERI_TR_CTL_NUM (cy_device->periTrGrSize / sizeof(uint32_t)) #define CY_PERI_TR_CTL_SEL_Pos (0UL) @@ -827,8 +860,10 @@ void Cy_PDL_Init(const cy_stc_device_t * device); * LCD *******************************************************************************/ -#define LCD_OCTET_NUM (8U) /* number of octets */ -#define LCD_COM_NUM (8U) /* maximum number of commons */ +#define LCD_OCTET_NUM (8U) /* LCD_NUMPORTS - number of octets supporting up to 4 COMs */ +#define LCD_OCTET_NUM_8 (8U) /* LCD_NUMPORTS8 - number of octets supporting up to 8 COMs */ +#define LCD_OCTET_NUM_16 (0U) /* LCD_NUMPORTS16 - number of octets supporting up to 16 COMs */ +#define LCD_COM_NUM (8U) /* LCD_CHIP_TOP_COM_NR - maximum number of commons */ #define LCD_ID(base) (((LCD_V1_Type*)(base))->ID) #define LCD_CONTROL(base) (((LCD_V1_Type*)(base))->CONTROL) @@ -843,6 +878,8 @@ void Cy_PDL_Init(const cy_stc_device_t * device); * IPC *******************************************************************************/ +#define CY_IPC_V1 (0x20u > cy_device->ipcVersion) /* true if the IPC version is 1.x */ + #define REG_IPC_STRUCT_ACQUIRE(base) (((IPC_STRUCT_V1_Type*)(base))->ACQUIRE) #define REG_IPC_STRUCT_RELEASE(base) (((IPC_STRUCT_V1_Type*)(base))->RELEASE) #define REG_IPC_STRUCT_NOTIFY(base) (((IPC_STRUCT_V1_Type*)(base))->NOTIFY) @@ -864,7 +901,7 @@ void Cy_PDL_Init(const cy_stc_device_t * device); #define CY_IPC_CHAN_SYSCALL_CM0 (0U) /* System calls for the CM0 processor */ #define CY_IPC_CHAN_SYSCALL_CM4 (1U) /* System calls for the 1st non-CM0 processor */ #define CY_IPC_CHAN_SYSCALL_DAP (2UL) /* System calls for the DAP */ -#define CY_IPC_CHAN_SEMA (4UL) /* IPC data channel for the Semaphores */ +#define CY_IPC_CHAN_SEMA (3UL) /* IPC data channel for the Semaphores */ #define CY_IPC_CHAN_CYPIPE_EP0 (5UL) /* IPC data channel for CYPIPE EP0 */ #define CY_IPC_CHAN_CYPIPE_EP1 (6UL) /* IPC data channel for CYPIPE EP1 */ #define CY_IPC_CHAN_DDFT (7UL) /* IPC data channel for DDFT */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_dma.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_dma.h index 6263528e8e..514ba7b8ee 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_dma.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_dma.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_dma.h -* \version 2.10 +* \version 2.20 * * \brief * The header file of the DMA driver. @@ -81,7 +81,7 @@ * function for each DMA channel. * * For example: -* \snippet dma\2.10\snippet\main.c snippet_Cy_DMA_Enable +* \snippet dma/snippet/main.c snippet_Cy_DMA_Enable * * \section group_dma_more_information More Information. * See: the DMA chapter of the device technical reference manual (TRM); @@ -121,6 +121,11 @@ * * * +* +* +* +* +* * * * @@ -203,7 +208,7 @@ extern "C" { #define CY_DMA_DRV_VERSION_MAJOR 2 /** The driver minor version */ -#define CY_DMA_DRV_VERSION_MINOR 10 +#define CY_DMA_DRV_VERSION_MINOR 20 /** The DMA driver identifier */ #define CY_DMA_ID (CY_PDL_DRV_ID(0x13U)) @@ -341,8 +346,8 @@ typedef enum (CY_DMA_2D_TRANSFER == (descrType)) || \ (CY_DMA_CRC_TRANSFER == (descrType))) -#define CY_DMA_IS_CH_NR_VALID(chNr) ((chNr) < CY_DW_CH_NR) - +#define CY_DMA_IS_CH_NR_VALID(base, chNr) ((CY_DW0_BASE == (base)) ? ((chNr) < CY_DW0_CH_NR) : \ + ((chNr) < CY_DW1_CH_NR)) /* The descriptor structure bit field definitions */ #define CY_DMA_CTL_RETRIG_Pos (0UL) @@ -592,7 +597,7 @@ __STATIC_INLINE cy_en_dma_channel_state_t Cy_DMA_Descriptor_GetChannelState * The pointer to the hardware DMA block. * * \funcusage -* \snippet dma\2.10\snippet\main.c snippet_Cy_DMA_Enable +* \snippet dma/snippet/main.c snippet_Cy_DMA_Enable * *******************************************************************************/ __STATIC_INLINE void Cy_DMA_Enable(DW_Type * base) @@ -611,7 +616,7 @@ __STATIC_INLINE void Cy_DMA_Enable(DW_Type * base) * The pointer to the hardware DMA block. * * \funcusage -* \snippet dma\2.10\snippet\main.c snippet_Cy_DMA_Disable +* \snippet dma/snippet/main.c snippet_Cy_DMA_Disable * *******************************************************************************/ __STATIC_INLINE void Cy_DMA_Disable(DW_Type * base) @@ -635,7 +640,7 @@ __STATIC_INLINE void Cy_DMA_Disable(DW_Type * base) * DMA block. * * \funcusage -* \snippet dma\2.10\snippet\main.c snippet_Cy_DMA_Disable +* \snippet dma/snippet/main.c snippet_Cy_DMA_Disable * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_DMA_GetActiveChannel(DW_Type const * base) @@ -657,7 +662,7 @@ __STATIC_INLINE uint32_t Cy_DMA_GetActiveChannel(DW_Type const * base) * Returns the pointer to the source of transfer. * * \funcusage -* \snippet dma\2.10\snippet\main.c snippet_Cy_DMA_GetActiveSrcAddress +* \snippet dma/snippet/main.c snippet_Cy_DMA_GetActiveSrcAddress * *******************************************************************************/ __STATIC_INLINE void * Cy_DMA_GetActiveSrcAddress(DW_Type * base) @@ -679,7 +684,7 @@ __STATIC_INLINE void * Cy_DMA_GetActiveSrcAddress(DW_Type * base) * Returns the pointer to the destination of transfer. * * \funcusage -* \snippet dma\2.10\snippet\main.c snippet_Cy_DMA_GetActiveSrcAddress +* \snippet dma/snippet/main.c snippet_Cy_DMA_GetActiveSrcAddress * *******************************************************************************/ __STATIC_INLINE void * Cy_DMA_GetActiveDstAddress(DW_Type * base) @@ -708,7 +713,7 @@ __STATIC_INLINE void * Cy_DMA_GetActiveDstAddress(DW_Type * base) * The source address value for the descriptor. * * \funcusage -* \snippet dma\2.10\snippet\main.c snippet_Cy_DMA_Descriptor_SetterFunctions +* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions * *******************************************************************************/ __STATIC_INLINE void Cy_DMA_Descriptor_SetSrcAddress(cy_stc_dma_descriptor_t * descriptor, void const * srcAddress) @@ -730,7 +735,7 @@ __STATIC_INLINE void Cy_DMA_Descriptor_SetSrcAddress(cy_stc_dma_descriptor_t * d * The source address value of the descriptor. * * \funcusage -* \snippet dma\2.10\snippet\main.c snippet_Cy_DMA_Descriptor_GetterFunctions +* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions * *******************************************************************************/ __STATIC_INLINE void * Cy_DMA_Descriptor_GetSrcAddress(cy_stc_dma_descriptor_t const * descriptor) @@ -752,7 +757,7 @@ __STATIC_INLINE void * Cy_DMA_Descriptor_GetSrcAddress(cy_stc_dma_descriptor_t c * The destination address value for the descriptor. * * \funcusage -* \snippet dma\2.10\snippet\main.c snippet_Cy_DMA_Descriptor_SetterFunctions +* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions * *******************************************************************************/ __STATIC_INLINE void Cy_DMA_Descriptor_SetDstAddress(cy_stc_dma_descriptor_t * descriptor, void const * dstAddress) @@ -774,7 +779,7 @@ __STATIC_INLINE void Cy_DMA_Descriptor_SetDstAddress(cy_stc_dma_descriptor_t * d * The destination address value of the descriptor. * * \funcusage -* \snippet dma\2.10\snippet\main.c snippet_Cy_DMA_Descriptor_GetterFunctions +* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions * *******************************************************************************/ __STATIC_INLINE void * Cy_DMA_Descriptor_GetDstAddress(cy_stc_dma_descriptor_t const * descriptor) @@ -796,7 +801,7 @@ __STATIC_INLINE void * Cy_DMA_Descriptor_GetDstAddress(cy_stc_dma_descriptor_t c * The interrupt type set for the descriptor. \ref cy_en_dma_trigger_type_t * * \funcusage -* \snippet dma\2.10\snippet\main.c snippet_Cy_DMA_Descriptor_SetterFunctions +* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions * *******************************************************************************/ __STATIC_INLINE void Cy_DMA_Descriptor_SetInterruptType(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_trigger_type_t interruptType) @@ -820,7 +825,7 @@ __STATIC_INLINE void Cy_DMA_Descriptor_SetInterruptType(cy_stc_dma_descriptor_t * The Interrupt-Type \ref cy_en_dma_trigger_type_t. * * \funcusage -* \snippet dma\2.10\snippet\main.c snippet_Cy_DMA_Descriptor_GetterFunctions +* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions * *******************************************************************************/ __STATIC_INLINE cy_en_dma_trigger_type_t Cy_DMA_Descriptor_GetInterruptType(cy_stc_dma_descriptor_t const * descriptor) @@ -842,7 +847,7 @@ __STATIC_INLINE cy_en_dma_trigger_type_t Cy_DMA_Descriptor_GetInterruptType(cy_s * The Trigger In Type parameter \ref cy_en_dma_trigger_type_t * * \funcusage -* \snippet dma\2.10\snippet\main.c snippet_Cy_DMA_Descriptor_SetterFunctions +* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions * *******************************************************************************/ __STATIC_INLINE void Cy_DMA_Descriptor_SetTriggerInType(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_trigger_type_t triggerInType) @@ -866,7 +871,7 @@ __STATIC_INLINE void Cy_DMA_Descriptor_SetTriggerInType(cy_stc_dma_descriptor_t * The Trigger-In-Type \ref cy_en_dma_trigger_type_t * * \funcusage -* \snippet dma\2.10\snippet\main.c snippet_Cy_DMA_Descriptor_GetterFunctions +* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions * *******************************************************************************/ __STATIC_INLINE cy_en_dma_trigger_type_t Cy_DMA_Descriptor_GetTriggerInType(cy_stc_dma_descriptor_t const * descriptor) @@ -888,7 +893,7 @@ __STATIC_INLINE cy_en_dma_trigger_type_t Cy_DMA_Descriptor_GetTriggerInType(cy_s * The Trigger-Out-Type set for the descriptor. \ref cy_en_dma_trigger_type_t * * \funcusage -* \snippet dma\2.10\snippet\main.c snippet_Cy_DMA_Descriptor_SetterFunctions +* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions * *******************************************************************************/ __STATIC_INLINE void Cy_DMA_Descriptor_SetTriggerOutType(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_trigger_type_t triggerOutType) @@ -912,7 +917,7 @@ __STATIC_INLINE void Cy_DMA_Descriptor_SetTriggerOutType(cy_stc_dma_descriptor_t * The Trigger-Out-Type parameter \ref cy_en_dma_trigger_type_t. * * \funcusage -* \snippet dma\2.10\snippet\main.c snippet_Cy_DMA_Descriptor_GetterFunctions +* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions * *******************************************************************************/ __STATIC_INLINE cy_en_dma_trigger_type_t Cy_DMA_Descriptor_GetTriggerOutType(cy_stc_dma_descriptor_t const * descriptor) @@ -934,7 +939,7 @@ __STATIC_INLINE cy_en_dma_trigger_type_t Cy_DMA_Descriptor_GetTriggerOutType(cy_ * The Data Element Size \ref cy_en_dma_data_size_t * * \funcusage -* \snippet dma\2.10\snippet\main.c snippet_Cy_DMA_Descriptor_SetterFunctions +* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions * *******************************************************************************/ __STATIC_INLINE void Cy_DMA_Descriptor_SetDataSize(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_data_size_t dataSize) @@ -958,7 +963,7 @@ __STATIC_INLINE void Cy_DMA_Descriptor_SetDataSize(cy_stc_dma_descriptor_t * des * The Data Element Size \ref cy_en_dma_data_size_t. * * \funcusage -* \snippet dma\2.10\snippet\main.c snippet_Cy_DMA_Descriptor_GetterFunctions +* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions * *******************************************************************************/ __STATIC_INLINE cy_en_dma_data_size_t Cy_DMA_Descriptor_GetDataSize(cy_stc_dma_descriptor_t const * descriptor) @@ -980,7 +985,7 @@ __STATIC_INLINE cy_en_dma_data_size_t Cy_DMA_Descriptor_GetDataSize(cy_stc_dma_d * The Source Transfer Size \ref cy_en_dma_transfer_size_t. * * \funcusage -* \snippet dma\2.10\snippet\main.c snippet_Cy_DMA_Descriptor_SetterFunctions +* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions * *******************************************************************************/ __STATIC_INLINE void Cy_DMA_Descriptor_SetSrcTransferSize(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_transfer_size_t srcTransferSize) @@ -1004,7 +1009,7 @@ __STATIC_INLINE void Cy_DMA_Descriptor_SetSrcTransferSize(cy_stc_dma_descriptor_ * The Source Transfer Size \ref cy_en_dma_transfer_size_t. * * \funcusage -* \snippet dma\2.10\snippet\main.c snippet_Cy_DMA_Descriptor_GetterFunctions +* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions * *******************************************************************************/ __STATIC_INLINE cy_en_dma_transfer_size_t Cy_DMA_Descriptor_GetSrcTransferSize(cy_stc_dma_descriptor_t const * descriptor) @@ -1026,7 +1031,7 @@ __STATIC_INLINE cy_en_dma_transfer_size_t Cy_DMA_Descriptor_GetSrcTransferSize(c * The Destination Transfer Size \ref cy_en_dma_transfer_size_t. * * \funcusage -* \snippet dma\2.10\snippet\main.c snippet_Cy_DMA_Descriptor_SetterFunctions +* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions * *******************************************************************************/ __STATIC_INLINE void Cy_DMA_Descriptor_SetDstTransferSize(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_transfer_size_t dstTransferSize) @@ -1050,7 +1055,7 @@ __STATIC_INLINE void Cy_DMA_Descriptor_SetDstTransferSize(cy_stc_dma_descriptor_ * The Destination Transfer Size \ref cy_en_dma_transfer_size_t. * * \funcusage -* \snippet dma\2.10\snippet\main.c snippet_Cy_DMA_Descriptor_GetterFunctions +* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions * *******************************************************************************/ __STATIC_INLINE cy_en_dma_transfer_size_t Cy_DMA_Descriptor_GetDstTransferSize(cy_stc_dma_descriptor_t const * descriptor) @@ -1074,7 +1079,7 @@ __STATIC_INLINE cy_en_dma_transfer_size_t Cy_DMA_Descriptor_GetDstTransferSize(c * should wait for the input trigger to be deactivated. * * \funcusage -* \snippet dma\2.10\snippet\main.c snippet_Cy_DMA_Descriptor_SetterFunctions +* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions * *******************************************************************************/ __STATIC_INLINE void Cy_DMA_Descriptor_SetRetrigger(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_retrigger_t retrigger) @@ -1099,7 +1104,7 @@ __STATIC_INLINE void Cy_DMA_Descriptor_SetRetrigger(cy_stc_dma_descriptor_t * de * The Retrigger setting \ref cy_en_dma_retrigger_t. * * \funcusage -* \snippet dma\2.10\snippet\main.c snippet_Cy_DMA_Descriptor_GetterFunctions +* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions * *******************************************************************************/ __STATIC_INLINE cy_en_dma_retrigger_t Cy_DMA_Descriptor_GetRetrigger(cy_stc_dma_descriptor_t const * descriptor) @@ -1121,7 +1126,7 @@ __STATIC_INLINE cy_en_dma_retrigger_t Cy_DMA_Descriptor_GetRetrigger(cy_stc_dma_ * The descriptor type \ref cy_en_dma_descriptor_type_t. * * \funcusage -* \snippet dma\2.10\snippet\main.c snippet_Cy_DMA_Descriptor_GetterFunctions +* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions * *******************************************************************************/ __STATIC_INLINE cy_en_dma_descriptor_type_t Cy_DMA_Descriptor_GetDescriptorType(cy_stc_dma_descriptor_t const * descriptor) @@ -1143,7 +1148,7 @@ __STATIC_INLINE cy_en_dma_descriptor_type_t Cy_DMA_Descriptor_GetDescriptorType( * The channel state \ref cy_en_dma_channel_state_t. * * \funcusage -* \snippet dma\2.10\snippet\main.c snippet_Cy_DMA_Descriptor_SetterFunctions +* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions * *******************************************************************************/ __STATIC_INLINE void Cy_DMA_Descriptor_SetChannelState(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_channel_state_t channelState) @@ -1167,7 +1172,7 @@ __STATIC_INLINE void Cy_DMA_Descriptor_SetChannelState(cy_stc_dma_descriptor_t * * The Channel State setting \ref cy_en_dma_channel_state_t. * * \funcusage -* \snippet dma\2.10\snippet\main.c snippet_Cy_DMA_Descriptor_GetterFunctions +* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions * *******************************************************************************/ __STATIC_INLINE cy_en_dma_channel_state_t Cy_DMA_Descriptor_GetChannelState(cy_stc_dma_descriptor_t const * descriptor) @@ -1190,7 +1195,7 @@ __STATIC_INLINE cy_en_dma_channel_state_t Cy_DMA_Descriptor_GetChannelState(cy_s * The number of data elements to transfer in the X loop. Valid range is 1 ... 256. * * \funcusage -* \snippet dma\2.10\snippet\main.c snippet_Cy_DMA_Descriptor_SetterFunctions +* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions * *******************************************************************************/ __STATIC_INLINE void Cy_DMA_Descriptor_SetXloopDataCount(cy_stc_dma_descriptor_t * descriptor, uint32_t xCount) @@ -1216,7 +1221,7 @@ __STATIC_INLINE void Cy_DMA_Descriptor_SetXloopDataCount(cy_stc_dma_descriptor_t * The number of data elements to transfer in the X loop. The range is 1 ... 256. * * \funcusage -* \snippet dma\2.10\snippet\main.c snippet_Cy_DMA_Descriptor_GetterFunctions +* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_DMA_Descriptor_GetXloopDataCount(cy_stc_dma_descriptor_t const * descriptor) @@ -1241,7 +1246,7 @@ __STATIC_INLINE uint32_t Cy_DMA_Descriptor_GetXloopDataCount(cy_stc_dma_descript * The value of the source increment. The valid range is -2048 ... 2047. * * \funcusage -* \snippet dma\2.10\snippet\main.c snippet_Cy_DMA_Descriptor_SetterFunctions +* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions * *******************************************************************************/ __STATIC_INLINE void Cy_DMA_Descriptor_SetXloopSrcIncrement(cy_stc_dma_descriptor_t * descriptor, int32_t srcXincrement) @@ -1267,7 +1272,7 @@ __STATIC_INLINE void Cy_DMA_Descriptor_SetXloopSrcIncrement(cy_stc_dma_descripto * The value of the source increment. The range is -2048 ... 2047. * * \funcusage -* \snippet dma\2.10\snippet\main.c snippet_Cy_DMA_Descriptor_GetterFunctions +* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions * *******************************************************************************/ __STATIC_INLINE int32_t Cy_DMA_Descriptor_GetXloopSrcIncrement(cy_stc_dma_descriptor_t const * descriptor) @@ -1292,7 +1297,7 @@ __STATIC_INLINE int32_t Cy_DMA_Descriptor_GetXloopSrcIncrement(cy_stc_dma_descri * The value of the destination increment. The valid range is -2048 ... 2047. * * \funcusage -* \snippet dma\2.10\snippet\main.c snippet_Cy_DMA_Descriptor_SetterFunctions +* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions * *******************************************************************************/ __STATIC_INLINE void Cy_DMA_Descriptor_SetXloopDstIncrement(cy_stc_dma_descriptor_t * descriptor, int32_t dstXincrement) @@ -1318,7 +1323,7 @@ __STATIC_INLINE void Cy_DMA_Descriptor_SetXloopDstIncrement(cy_stc_dma_descripto * The value of the destination increment. The range is -2048 ... 2047. * * \funcusage -* \snippet dma\2.10\snippet\main.c snippet_Cy_DMA_Descriptor_GetterFunctions +* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions * *******************************************************************************/ __STATIC_INLINE int32_t Cy_DMA_Descriptor_GetXloopDstIncrement(cy_stc_dma_descriptor_t const * descriptor) @@ -1343,7 +1348,7 @@ __STATIC_INLINE int32_t Cy_DMA_Descriptor_GetXloopDstIncrement(cy_stc_dma_descri * The number of X loops to execute in the Y loop. The valid range is 1 ... 256. * * \funcusage -* \snippet dma\2.10\snippet\main.c snippet_Cy_DMA_Descriptor_SetterFunctions +* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions * *******************************************************************************/ __STATIC_INLINE void Cy_DMA_Descriptor_SetYloopDataCount(cy_stc_dma_descriptor_t * descriptor, uint32_t yCount) @@ -1369,7 +1374,7 @@ __STATIC_INLINE void Cy_DMA_Descriptor_SetYloopDataCount(cy_stc_dma_descriptor_t * The number of X loops to execute in the Y loop. The range is 1 ... 256. * * \funcusage -* \snippet dma\2.10\snippet\main.c snippet_Cy_DMA_Descriptor_GetterFunctions +* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_DMA_Descriptor_GetYloopDataCount(cy_stc_dma_descriptor_t const * descriptor) @@ -1394,7 +1399,7 @@ __STATIC_INLINE uint32_t Cy_DMA_Descriptor_GetYloopDataCount(cy_stc_dma_descript * The value of the source increment. The valid range is -2048 ... 2047. * * \funcusage -* \snippet dma\2.10\snippet\main.c snippet_Cy_DMA_Descriptor_SetterFunctions +* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions * *******************************************************************************/ __STATIC_INLINE void Cy_DMA_Descriptor_SetYloopSrcIncrement(cy_stc_dma_descriptor_t * descriptor, int32_t srcYincrement) @@ -1420,7 +1425,7 @@ __STATIC_INLINE void Cy_DMA_Descriptor_SetYloopSrcIncrement(cy_stc_dma_descripto * The value of the source increment. The range is -2048 ... 2047. * * \funcusage -* \snippet dma\2.10\snippet\main.c snippet_Cy_DMA_Descriptor_GetterFunctions +* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions * *******************************************************************************/ __STATIC_INLINE int32_t Cy_DMA_Descriptor_GetYloopSrcIncrement(cy_stc_dma_descriptor_t const * descriptor) @@ -1445,7 +1450,7 @@ __STATIC_INLINE int32_t Cy_DMA_Descriptor_GetYloopSrcIncrement(cy_stc_dma_descri * The value of the destination increment. The valid range is -2048 ... 2047. * * \funcusage -* \snippet dma\2.10\snippet\main.c snippet_Cy_DMA_Descriptor_SetterFunctions +* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions * *******************************************************************************/ __STATIC_INLINE void Cy_DMA_Descriptor_SetYloopDstIncrement(cy_stc_dma_descriptor_t * descriptor, int32_t dstYincrement) @@ -1471,7 +1476,7 @@ __STATIC_INLINE void Cy_DMA_Descriptor_SetYloopDstIncrement(cy_stc_dma_descripto * The value of the destination increment. The range is -2048 ... 2047. * * \funcusage -* \snippet dma\2.10\snippet\main.c snippet_Cy_DMA_Descriptor_GetterFunctions +* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions * *******************************************************************************/ __STATIC_INLINE int32_t Cy_DMA_Descriptor_GetYloopDstIncrement(cy_stc_dma_descriptor_t const * descriptor) @@ -1507,12 +1512,12 @@ __STATIC_INLINE int32_t Cy_DMA_Descriptor_GetYloopDstIncrement(cy_stc_dma_descri * This is the descriptor to be associated with the channel. * * \funcusage -* \snippet dma\2.10\snippet\main.c snippet_Cy_DMA_Enable +* \snippet dma/snippet/main.c snippet_Cy_DMA_Enable * *******************************************************************************/ __STATIC_INLINE void Cy_DMA_Channel_SetDescriptor(DW_Type * base, uint32_t channel, cy_stc_dma_descriptor_t const * descriptor) { - CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(channel)); + CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel)); DW_CH_CURR_PTR(base, channel) = (uint32_t)descriptor; DW_CH_IDX(base, channel) &= (uint32_t) ~(DW_CH_STRUCT_CH_IDX_X_IDX_Msk | DW_CH_STRUCT_CH_IDX_Y_IDX_Msk); @@ -1532,12 +1537,12 @@ __STATIC_INLINE void Cy_DMA_Channel_SetDescriptor(DW_Type * base, uint32_t chann * The channel number. * * \funcusage -* \snippet dma\2.10\snippet\main.c snippet_Cy_DMA_Enable +* \snippet dma/snippet/main.c snippet_Cy_DMA_Enable * *******************************************************************************/ __STATIC_INLINE void Cy_DMA_Channel_Enable(DW_Type * base, uint32_t channel) { - CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(channel)); + CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel)); DW_CH_CTL(base, channel) |= DW_CH_STRUCT_CH_CTL_ENABLED_Msk; } @@ -1556,12 +1561,12 @@ __STATIC_INLINE void Cy_DMA_Channel_Enable(DW_Type * base, uint32_t channel) * The channel number. * * \funcusage -* \snippet dma\2.10\snippet\main.c snippet_Cy_DMA_Disable +* \snippet dma/snippet/main.c snippet_Cy_DMA_Disable * *******************************************************************************/ __STATIC_INLINE void Cy_DMA_Channel_Disable(DW_Type * base, uint32_t channel) { - CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(channel)); + CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel)); DW_CH_CTL(base, channel) &= (uint32_t) ~DW_CH_STRUCT_CH_CTL_ENABLED_Msk; } @@ -1583,12 +1588,12 @@ __STATIC_INLINE void Cy_DMA_Channel_Disable(DW_Type * base, uint32_t channel) * The priority to be set for the DMA channel. The allowed values are 0,1,2,3. * * \funcusage -* \snippet dma\2.10\snippet\main.c snippet_Cy_DMA_Enable +* \snippet dma/snippet/main.c snippet_Cy_DMA_Enable * *******************************************************************************/ __STATIC_INLINE void Cy_DMA_Channel_SetPriority(DW_Type * base, uint32_t channel, uint32_t priority) { - CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(channel)); + CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel)); CY_ASSERT_L2(CY_DMA_IS_PRIORITY_VALID(priority)); CY_REG32_CLR_SET(DW_CH_CTL(base, channel), CY_DW_CH_CTL_PRIO, priority); @@ -1611,12 +1616,12 @@ __STATIC_INLINE void Cy_DMA_Channel_SetPriority(DW_Type * base, uint32_t channel * The priority of the channel. * * \funcusage -* \snippet dma\2.10\snippet\main.c snippet_Cy_DMA_Disable +* \snippet dma/snippet/main.c snippet_Cy_DMA_Disable * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_DMA_Channel_GetPriority(DW_Type const * base, uint32_t channel) { - CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(channel)); + CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel)); return ((uint32_t) _FLD2VAL(CY_DW_CH_CTL_PRIO, DW_CH_CTL(base, channel))); } @@ -1638,12 +1643,12 @@ __STATIC_INLINE uint32_t Cy_DMA_Channel_GetPriority(DW_Type const * base, uint32 * The pointer to the descriptor associated with the channel. * * \funcusage -* \snippet dma\2.10\snippet\main.c snippet_Cy_DMA_Descriptor_Deinit +* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_Deinit * *******************************************************************************/ __STATIC_INLINE cy_stc_dma_descriptor_t * Cy_DMA_Channel_GetCurrentDescriptor(DW_Type const * base, uint32_t channel) { - CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(channel)); + CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel)); return ((cy_stc_dma_descriptor_t*)(DW_CH_CURR_PTR(base, channel))); } @@ -1666,12 +1671,12 @@ __STATIC_INLINE cy_stc_dma_descriptor_t * Cy_DMA_Channel_GetCurrentDescriptor(DW * The status of an interrupt for the specified channel. * * \funcusage -* \snippet dma\2.10\snippet\main.c snippet_Cy_DMA_GetInterruptStatus +* \snippet dma/snippet/main.c snippet_Cy_DMA_GetInterruptStatus * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_DMA_Channel_GetInterruptStatus(DW_Type const * base, uint32_t channel) { - CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(channel)); + CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel)); return (DW_CH_INTR(base, channel)); } @@ -1693,12 +1698,12 @@ __STATIC_INLINE uint32_t Cy_DMA_Channel_GetInterruptStatus(DW_Type const * base, * The cause \ref cy_en_dma_intr_cause_t of the interrupt. * * \funcusage -* \snippet dma\2.10\snippet\main.c snippet_Cy_DMA_ClearInterrupt +* \snippet dma/snippet/main.c snippet_Cy_DMA_ClearInterrupt * *******************************************************************************/ __STATIC_INLINE cy_en_dma_intr_cause_t Cy_DMA_Channel_GetStatus(DW_Type const * base, uint32_t channel) { - CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(channel)); + CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel)); return ((cy_en_dma_intr_cause_t) _FLD2VAL(DW_CH_STRUCT_CH_STATUS_INTR_CAUSE, DW_CH_STATUS(base, channel))); } @@ -1717,12 +1722,12 @@ __STATIC_INLINE cy_en_dma_intr_cause_t Cy_DMA_Channel_GetStatus(DW_Type const * * The channel number. * * \funcusage -* \snippet dma\2.10\snippet\main.c snippet_Cy_DMA_ClearInterrupt +* \snippet dma/snippet/main.c snippet_Cy_DMA_ClearInterrupt * *******************************************************************************/ __STATIC_INLINE void Cy_DMA_Channel_ClearInterrupt(DW_Type * base, uint32_t channel) { - CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(channel)); + CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel)); DW_CH_INTR(base, channel) = CY_DMA_INTR_MASK; (void) DW_CH_INTR(base, channel); @@ -1742,12 +1747,12 @@ __STATIC_INLINE void Cy_DMA_Channel_ClearInterrupt(DW_Type * base, uint32_t chan * The channel number. * * \funcusage -* \snippet dma\2.10\snippet\main.c snippet_Cy_DMA_SetInterruptMask +* \snippet dma/snippet/main.c snippet_Cy_DMA_SetInterruptMask * *******************************************************************************/ __STATIC_INLINE void Cy_DMA_Channel_SetInterrupt(DW_Type * base, uint32_t channel) { - CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(channel)); + CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel)); DW_CH_INTR_SET(base, channel) = CY_DMA_INTR_MASK; } @@ -1769,12 +1774,12 @@ __STATIC_INLINE void Cy_DMA_Channel_SetInterrupt(DW_Type * base, uint32_t channe * The interrupt mask value. * * \funcusage -* \snippet dma\2.10\snippet\main.c snippet_Cy_DMA_SetInterruptMask +* \snippet dma/snippet/main.c snippet_Cy_DMA_SetInterruptMask * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_DMA_Channel_GetInterruptMask(DW_Type const * base, uint32_t channel) { - CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(channel)); + CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel)); return (DW_CH_INTR_MASK(base, channel)); } @@ -1797,12 +1802,12 @@ __STATIC_INLINE uint32_t Cy_DMA_Channel_GetInterruptMask(DW_Type const * base, u * CY_DMA_INTR_MASK to enable the interrupt or 0UL to disable the interrupt. * * \funcusage -* \snippet dma\2.10\snippet\main.c snippet_Cy_DMA_SetInterruptMask +* \snippet dma/snippet/main.c snippet_Cy_DMA_SetInterruptMask * *******************************************************************************/ __STATIC_INLINE void Cy_DMA_Channel_SetInterruptMask(DW_Type * base, uint32_t channel, uint32_t interrupt) { - CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(channel)); + CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel)); CY_ASSERT_L2(CY_DMA_IS_INTR_MASK_VALID(interrupt)); DW_CH_INTR_MASK(base, channel) = interrupt; } @@ -1822,12 +1827,12 @@ __STATIC_INLINE void Cy_DMA_Channel_SetInterruptMask(DW_Type * base, uint32_t ch * The channel number. * * \funcusage -* \snippet dma\2.10\snippet\main.c snippet_Cy_DMA_ClearInterrupt +* \snippet dma/snippet/main.c snippet_Cy_DMA_ClearInterrupt * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_DMA_Channel_GetInterruptStatusMasked(DW_Type const * base, uint32_t channel) { - CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(channel)); + CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel)); return (DW_CH_INTR_MASKED(base, channel)); } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_dmac.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_dmac.h index f65453a75a..54c8416a2b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_dmac.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_dmac.h @@ -82,7 +82,7 @@ * function for each DMAC channel. * * For example: -* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_Enable +* \snippet dmac/snippet/main.c snippet_Cy_DMAC_Enable * * \section group_dmac_more_information More Information. * See the DMAC chapter of the device technical reference manual (TRM). @@ -555,7 +555,7 @@ __STATIC_INLINE cy_en_dmac_channel_state_t Cy_DMAC_Descriptor_GetChannelState * The pointer to the hardware DMAC block. * * \funcusage -* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_Enable +* \snippet dmac/snippet/main.c snippet_Cy_DMAC_Enable * *******************************************************************************/ __STATIC_INLINE void Cy_DMAC_Enable(DMAC_Type * base) @@ -574,7 +574,7 @@ __STATIC_INLINE void Cy_DMAC_Enable(DMAC_Type * base) * The pointer to the hardware DMAC block. * * \funcusage -* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_Disable +* \snippet dmac/snippet/main.c snippet_Cy_DMAC_Disable * *******************************************************************************/ __STATIC_INLINE void Cy_DMAC_Disable(DMAC_Type * base) @@ -597,7 +597,7 @@ __STATIC_INLINE void Cy_DMAC_Disable(DMAC_Type * base) * DMAC block. * * \funcusage -* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_Disable +* \snippet dmac/snippet/main.c snippet_Cy_DMAC_Disable * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_DMAC_GetActiveChannel(DMAC_Type const * base) @@ -627,7 +627,7 @@ __STATIC_INLINE uint32_t Cy_DMAC_GetActiveChannel(DMAC_Type const * base) * The source address value for the descriptor. * * \funcusage -* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_Descriptor_SetterFunctions +* \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_SetterFunctions * *******************************************************************************/ __STATIC_INLINE void Cy_DMAC_Descriptor_SetSrcAddress(cy_stc_dmac_descriptor_t * descriptor, void const * srcAddress) @@ -649,7 +649,7 @@ __STATIC_INLINE void Cy_DMAC_Descriptor_SetSrcAddress(cy_stc_dmac_descriptor_t * * The source address value of the descriptor. * * \funcusage -* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_Descriptor_GetterFunctions +* \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_GetterFunctions * *******************************************************************************/ __STATIC_INLINE void * Cy_DMAC_Descriptor_GetSrcAddress(cy_stc_dmac_descriptor_t const * descriptor) @@ -671,7 +671,7 @@ __STATIC_INLINE void * Cy_DMAC_Descriptor_GetSrcAddress(cy_stc_dmac_descriptor_t * The destination address value for the descriptor. * * \funcusage -* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_Descriptor_SetterFunctions +* \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_SetterFunctions * *******************************************************************************/ __STATIC_INLINE void Cy_DMAC_Descriptor_SetDstAddress(cy_stc_dmac_descriptor_t * descriptor, void const * dstAddress) @@ -695,7 +695,7 @@ __STATIC_INLINE void Cy_DMAC_Descriptor_SetDstAddress(cy_stc_dmac_descriptor_t * * The destination address value of the descriptor. * * \funcusage -* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_Descriptor_GetterFunctions +* \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_GetterFunctions * *******************************************************************************/ __STATIC_INLINE void * Cy_DMAC_Descriptor_GetDstAddress(cy_stc_dmac_descriptor_t const * descriptor) @@ -719,7 +719,7 @@ __STATIC_INLINE void * Cy_DMAC_Descriptor_GetDstAddress(cy_stc_dmac_descriptor_t * The interrupt type set for the descriptor. \ref cy_en_dmac_trigger_type_t * * \funcusage -* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_Descriptor_SetterFunctions +* \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_SetterFunctions * *******************************************************************************/ __STATIC_INLINE void Cy_DMAC_Descriptor_SetInterruptType(cy_stc_dmac_descriptor_t * descriptor, cy_en_dmac_trigger_type_t interruptType) @@ -743,7 +743,7 @@ __STATIC_INLINE void Cy_DMAC_Descriptor_SetInterruptType(cy_stc_dmac_descriptor_ * The Interrupt-Type \ref cy_en_dmac_trigger_type_t. * * \funcusage -* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_Descriptor_GetterFunctions +* \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_GetterFunctions * *******************************************************************************/ __STATIC_INLINE cy_en_dmac_trigger_type_t Cy_DMAC_Descriptor_GetInterruptType(cy_stc_dmac_descriptor_t const * descriptor) @@ -765,7 +765,7 @@ __STATIC_INLINE cy_en_dmac_trigger_type_t Cy_DMAC_Descriptor_GetInterruptType(cy * The Trigger In Type parameter \ref cy_en_dmac_trigger_type_t * * \funcusage -* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_Descriptor_SetterFunctions +* \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_SetterFunctions * *******************************************************************************/ __STATIC_INLINE void Cy_DMAC_Descriptor_SetTriggerInType(cy_stc_dmac_descriptor_t * descriptor, cy_en_dmac_trigger_type_t triggerInType) @@ -789,7 +789,7 @@ __STATIC_INLINE void Cy_DMAC_Descriptor_SetTriggerInType(cy_stc_dmac_descriptor_ * The Trigger In Type \ref cy_en_dmac_trigger_type_t * * \funcusage -* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_Descriptor_GetterFunctions +* \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_GetterFunctions * *******************************************************************************/ __STATIC_INLINE cy_en_dmac_trigger_type_t Cy_DMAC_Descriptor_GetTriggerInType(cy_stc_dmac_descriptor_t const * descriptor) @@ -811,7 +811,7 @@ __STATIC_INLINE cy_en_dmac_trigger_type_t Cy_DMAC_Descriptor_GetTriggerInType(cy * The Trigger Out Type set for the descriptor. \ref cy_en_dmac_trigger_type_t * * \funcusage -* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_Descriptor_SetterFunctions +* \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_SetterFunctions * *******************************************************************************/ __STATIC_INLINE void Cy_DMAC_Descriptor_SetTriggerOutType(cy_stc_dmac_descriptor_t * descriptor, cy_en_dmac_trigger_type_t triggerOutType) @@ -835,7 +835,7 @@ __STATIC_INLINE void Cy_DMAC_Descriptor_SetTriggerOutType(cy_stc_dmac_descriptor * The Trigger Out Type parameter \ref cy_en_dmac_trigger_type_t. * * \funcusage -* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_Descriptor_GetterFunctions +* \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_GetterFunctions * *******************************************************************************/ __STATIC_INLINE cy_en_dmac_trigger_type_t Cy_DMAC_Descriptor_GetTriggerOutType(cy_stc_dmac_descriptor_t const * descriptor) @@ -857,7 +857,7 @@ __STATIC_INLINE cy_en_dmac_trigger_type_t Cy_DMAC_Descriptor_GetTriggerOutType(c * The Data Element Size \ref cy_en_dmac_data_size_t * * \funcusage -* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_Descriptor_SetterFunctions +* \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_SetterFunctions * *******************************************************************************/ __STATIC_INLINE void Cy_DMAC_Descriptor_SetDataSize(cy_stc_dmac_descriptor_t * descriptor, cy_en_dmac_data_size_t dataSize) @@ -881,7 +881,7 @@ __STATIC_INLINE void Cy_DMAC_Descriptor_SetDataSize(cy_stc_dmac_descriptor_t * d * The Data Element Size \ref cy_en_dmac_data_size_t. * * \funcusage -* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_Descriptor_GetterFunctions +* \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_GetterFunctions * *******************************************************************************/ __STATIC_INLINE cy_en_dmac_data_size_t Cy_DMAC_Descriptor_GetDataSize(cy_stc_dmac_descriptor_t const * descriptor) @@ -903,7 +903,7 @@ __STATIC_INLINE cy_en_dmac_data_size_t Cy_DMAC_Descriptor_GetDataSize(cy_stc_dma * The Source Transfer Size \ref cy_en_dmac_transfer_size_t. * * \funcusage -* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_Descriptor_SetterFunctions +* \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_SetterFunctions *******************************************************************************/ __STATIC_INLINE void Cy_DMAC_Descriptor_SetSrcTransferSize(cy_stc_dmac_descriptor_t * descriptor, cy_en_dmac_transfer_size_t srcTransferSize) { @@ -926,7 +926,7 @@ __STATIC_INLINE void Cy_DMAC_Descriptor_SetSrcTransferSize(cy_stc_dmac_descripto * The Source Transfer Size \ref cy_en_dmac_transfer_size_t. * * \funcusage -* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_Descriptor_GetterFunctions +* \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_GetterFunctions * *******************************************************************************/ __STATIC_INLINE cy_en_dmac_transfer_size_t Cy_DMAC_Descriptor_GetSrcTransferSize(cy_stc_dmac_descriptor_t const * descriptor) @@ -948,7 +948,7 @@ __STATIC_INLINE cy_en_dmac_transfer_size_t Cy_DMAC_Descriptor_GetSrcTransferSize * The Destination Transfer Size \ref cy_en_dmac_transfer_size_t. * * \funcusage -* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_Descriptor_SetterFunctions +* \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_SetterFunctions * *******************************************************************************/ __STATIC_INLINE void Cy_DMAC_Descriptor_SetDstTransferSize(cy_stc_dmac_descriptor_t * descriptor, cy_en_dmac_transfer_size_t dstTransferSize) @@ -972,7 +972,7 @@ __STATIC_INLINE void Cy_DMAC_Descriptor_SetDstTransferSize(cy_stc_dmac_descripto * The Destination Transfer Size \ref cy_en_dmac_transfer_size_t * * \funcusage -* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_Descriptor_GetterFunctions +* \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_GetterFunctions * *******************************************************************************/ __STATIC_INLINE cy_en_dmac_transfer_size_t Cy_DMAC_Descriptor_GetDstTransferSize(cy_stc_dmac_descriptor_t const * descriptor) @@ -996,7 +996,7 @@ __STATIC_INLINE cy_en_dmac_transfer_size_t Cy_DMAC_Descriptor_GetDstTransferSize * should wait for the input trigger to be deactivated. * * \funcusage -* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_Descriptor_SetterFunctions +* \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_SetterFunctions * *******************************************************************************/ __STATIC_INLINE void Cy_DMAC_Descriptor_SetRetrigger(cy_stc_dmac_descriptor_t * descriptor, cy_en_dmac_retrigger_t retrigger) @@ -1021,7 +1021,7 @@ __STATIC_INLINE void Cy_DMAC_Descriptor_SetRetrigger(cy_stc_dmac_descriptor_t * * The Retrigger setting \ref cy_en_dmac_retrigger_t. * * \funcusage -* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_Descriptor_GetterFunctions +* \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_GetterFunctions * *******************************************************************************/ __STATIC_INLINE cy_en_dmac_retrigger_t Cy_DMAC_Descriptor_GetRetrigger(cy_stc_dmac_descriptor_t const * descriptor) @@ -1043,7 +1043,7 @@ __STATIC_INLINE cy_en_dmac_retrigger_t Cy_DMAC_Descriptor_GetRetrigger(cy_stc_dm * The descriptor type \ref cy_en_dmac_descriptor_type_t * * \funcusage -* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_Descriptor_GetterFunctions +* \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_GetterFunctions * *******************************************************************************/ __STATIC_INLINE cy_en_dmac_descriptor_type_t Cy_DMAC_Descriptor_GetDescriptorType(cy_stc_dmac_descriptor_t const * descriptor) @@ -1065,7 +1065,7 @@ __STATIC_INLINE cy_en_dmac_descriptor_type_t Cy_DMAC_Descriptor_GetDescriptorTyp * The channel state \ref cy_en_dmac_channel_state_t. * * \funcusage -* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_Descriptor_SetterFunctions +* \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_SetterFunctions * *******************************************************************************/ __STATIC_INLINE void Cy_DMAC_Descriptor_SetChannelState(cy_stc_dmac_descriptor_t * descriptor, cy_en_dmac_channel_state_t channelState) @@ -1089,7 +1089,7 @@ __STATIC_INLINE void Cy_DMAC_Descriptor_SetChannelState(cy_stc_dmac_descriptor_t * The Channel State setting \ref cy_en_dmac_channel_state_t * * \funcusage -* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_Descriptor_GetterFunctions +* \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_GetterFunctions * *******************************************************************************/ __STATIC_INLINE cy_en_dmac_channel_state_t Cy_DMAC_Descriptor_GetChannelState(cy_stc_dmac_descriptor_t const * descriptor) @@ -1112,7 +1112,7 @@ __STATIC_INLINE cy_en_dmac_channel_state_t Cy_DMAC_Descriptor_GetChannelState(cy * The value of the source increment. The valid range is -32768 ... 32767. * * \funcusage -* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_Descriptor_SetterFunctions +* \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_SetterFunctions * *******************************************************************************/ __STATIC_INLINE void Cy_DMAC_Descriptor_SetXloopSrcIncrement(cy_stc_dmac_descriptor_t * descriptor, int32_t srcXincrement) @@ -1138,7 +1138,7 @@ __STATIC_INLINE void Cy_DMAC_Descriptor_SetXloopSrcIncrement(cy_stc_dmac_descrip * The value of the source increment. The range is -32768 ... 32767. * * \funcusage -* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_Descriptor_GetterFunctions +* \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_GetterFunctions * *******************************************************************************/ __STATIC_INLINE int32_t Cy_DMAC_Descriptor_GetXloopSrcIncrement(cy_stc_dmac_descriptor_t const * descriptor) @@ -1163,7 +1163,7 @@ __STATIC_INLINE int32_t Cy_DMAC_Descriptor_GetXloopSrcIncrement(cy_stc_dmac_desc * The value of the destination increment. The valid range is -32768 ... 32767. * * \funcusage -* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_Descriptor_SetterFunctions +* \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_SetterFunctions * *******************************************************************************/ __STATIC_INLINE void Cy_DMAC_Descriptor_SetXloopDstIncrement(cy_stc_dmac_descriptor_t * descriptor, int32_t dstXincrement) @@ -1189,7 +1189,7 @@ __STATIC_INLINE void Cy_DMAC_Descriptor_SetXloopDstIncrement(cy_stc_dmac_descrip * The value of the destination increment. The range is -32768 ... 32767. * * \funcusage -* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_Descriptor_GetterFunctions +* \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_GetterFunctions * *******************************************************************************/ __STATIC_INLINE int32_t Cy_DMAC_Descriptor_GetXloopDstIncrement(cy_stc_dmac_descriptor_t const * descriptor) @@ -1214,7 +1214,7 @@ __STATIC_INLINE int32_t Cy_DMAC_Descriptor_GetXloopDstIncrement(cy_stc_dmac_desc * The number of X loops to execute in the Y loop. The valid range is 1 ... 65536. * * \funcusage -* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_Descriptor_SetterFunctions +* \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_SetterFunctions * *******************************************************************************/ __STATIC_INLINE void Cy_DMAC_Descriptor_SetYloopDataCount(cy_stc_dmac_descriptor_t * descriptor, uint32_t yCount) @@ -1240,7 +1240,7 @@ __STATIC_INLINE void Cy_DMAC_Descriptor_SetYloopDataCount(cy_stc_dmac_descriptor * The number of X loops to execute in the Y loop. The range is 1 ... 65536. * * \funcusage -* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_Descriptor_GetterFunctions +* \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_GetterFunctions * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_DMAC_Descriptor_GetYloopDataCount(cy_stc_dmac_descriptor_t const * descriptor) @@ -1265,7 +1265,7 @@ __STATIC_INLINE uint32_t Cy_DMAC_Descriptor_GetYloopDataCount(cy_stc_dmac_descri * The value of the source increment. The valid range is -32768 ... 32767. * * \funcusage -* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_Descriptor_SetterFunctions +* \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_SetterFunctions * *******************************************************************************/ __STATIC_INLINE void Cy_DMAC_Descriptor_SetYloopSrcIncrement(cy_stc_dmac_descriptor_t * descriptor, int32_t srcYincrement) @@ -1291,7 +1291,7 @@ __STATIC_INLINE void Cy_DMAC_Descriptor_SetYloopSrcIncrement(cy_stc_dmac_descrip * The value of source increment. The range is -32768 ... 32767. * * \funcusage -* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_Descriptor_GetterFunctions +* \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_GetterFunctions * *******************************************************************************/ __STATIC_INLINE int32_t Cy_DMAC_Descriptor_GetYloopSrcIncrement(cy_stc_dmac_descriptor_t const * descriptor) @@ -1316,7 +1316,7 @@ __STATIC_INLINE int32_t Cy_DMAC_Descriptor_GetYloopSrcIncrement(cy_stc_dmac_desc * The value of the destination increment. The valid range is -32768 ... 32767. * * \funcusage -* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_Descriptor_SetterFunctions +* \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_SetterFunctions * *******************************************************************************/ __STATIC_INLINE void Cy_DMAC_Descriptor_SetYloopDstIncrement(cy_stc_dmac_descriptor_t * descriptor, int32_t dstYincrement) @@ -1342,7 +1342,7 @@ __STATIC_INLINE void Cy_DMAC_Descriptor_SetYloopDstIncrement(cy_stc_dmac_descrip * The value of the destination increment. The range is -32768 ... 32767. * * \funcusage -* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_Descriptor_GetterFunctions +* \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_GetterFunctions * *******************************************************************************/ __STATIC_INLINE int32_t Cy_DMAC_Descriptor_GetYloopDstIncrement(cy_stc_dmac_descriptor_t const * descriptor) @@ -1377,7 +1377,7 @@ __STATIC_INLINE int32_t Cy_DMAC_Descriptor_GetYloopDstIncrement(cy_stc_dmac_desc * This is the descriptor to be associated with the channel. * * \funcusage -* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_Enable +* \snippet dmac/snippet/main.c snippet_Cy_DMAC_Enable * *******************************************************************************/ __STATIC_INLINE void Cy_DMAC_Channel_SetDescriptor(DMAC_Type * base, uint32_t channel, cy_stc_dmac_descriptor_t const * descriptor) @@ -1401,7 +1401,7 @@ __STATIC_INLINE void Cy_DMAC_Channel_SetDescriptor(DMAC_Type * base, uint32_t ch * The channel number. * * \funcusage -* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_Enable +* \snippet dmac/snippet/main.c snippet_Cy_DMAC_Enable * *******************************************************************************/ __STATIC_INLINE void Cy_DMAC_Channel_Enable(DMAC_Type * base, uint32_t channel) @@ -1425,7 +1425,7 @@ __STATIC_INLINE void Cy_DMAC_Channel_Enable(DMAC_Type * base, uint32_t channel) * The channel number. * * \funcusage -* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_Disable +* \snippet dmac/snippet/main.c snippet_Cy_DMAC_Disable * *******************************************************************************/ __STATIC_INLINE void Cy_DMAC_Channel_Disable(DMAC_Type * base, uint32_t channel) @@ -1452,7 +1452,7 @@ __STATIC_INLINE void Cy_DMAC_Channel_Disable(DMAC_Type * base, uint32_t channel) * The priority to be set for the DMAC channel. The allowed values are 0,1,2,3. * * \funcusage -* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_Enable +* \snippet dmac/snippet/main.c snippet_Cy_DMAC_Enable * *******************************************************************************/ __STATIC_INLINE void Cy_DMAC_Channel_SetPriority(DMAC_Type * base, uint32_t channel, uint32_t priority) @@ -1480,7 +1480,7 @@ __STATIC_INLINE void Cy_DMAC_Channel_SetPriority(DMAC_Type * base, uint32_t chan * The priority of the channel. * * \funcusage -* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_Disable +* \snippet dmac/snippet/main.c snippet_Cy_DMAC_Disable * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_DMAC_Channel_GetPriority(DMAC_Type const * base, uint32_t channel) @@ -1507,7 +1507,7 @@ __STATIC_INLINE uint32_t Cy_DMAC_Channel_GetPriority(DMAC_Type const * base, uin * Returns the pointer to the source of transfer. * * \funcusage -* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_Channel_GetCurrentSrcAddress +* \snippet dmac/snippet/main.c snippet_Cy_DMAC_Channel_GetCurrentSrcAddress * *******************************************************************************/ __STATIC_INLINE void * Cy_DMAC_Channel_GetCurrentSrcAddress(DMAC_Type * base, uint32_t channel) @@ -1534,7 +1534,7 @@ __STATIC_INLINE void * Cy_DMAC_Channel_GetCurrentSrcAddress(DMAC_Type * base, ui * Returns the pointer to the destination of transfer. * * \funcusage -* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_Channel_GetCurrentSrcAddress +* \snippet dmac/snippet/main.c snippet_Cy_DMAC_Channel_GetCurrentSrcAddress * *******************************************************************************/ __STATIC_INLINE void * Cy_DMAC_Channel_GetCurrentDstAddress(DMAC_Type * base, uint32_t channel) @@ -1561,7 +1561,7 @@ __STATIC_INLINE void * Cy_DMAC_Channel_GetCurrentDstAddress(DMAC_Type * base, ui * Returns the current transfer X-loop index. * * \funcusage -* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_Channel_GetCurrentloopIndex +* \snippet dmac/snippet/main.c snippet_Cy_DMAC_Channel_GetCurrentloopIndex * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_DMAC_Channel_GetCurrentXloopIndex(DMAC_Type const * base, uint32_t channel) @@ -1588,7 +1588,7 @@ __STATIC_INLINE uint32_t Cy_DMAC_Channel_GetCurrentXloopIndex(DMAC_Type const * * Returns the current transfer X-loop index. * * \funcusage -* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_Channel_GetCurrentloopIndex +* \snippet dmac/snippet/main.c snippet_Cy_DMAC_Channel_GetCurrentloopIndex * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_DMAC_Channel_GetCurrentYloopIndex(DMAC_Type const * base, uint32_t channel) @@ -1615,7 +1615,7 @@ __STATIC_INLINE uint32_t Cy_DMAC_Channel_GetCurrentYloopIndex(DMAC_Type const * * The pointer to the descriptor associated with the channel. * * \funcusage -* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_Descriptor_Deinit +* \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_Deinit * *******************************************************************************/ __STATIC_INLINE cy_stc_dmac_descriptor_t * Cy_DMAC_Channel_GetCurrentDescriptor(DMAC_Type const * base, uint32_t channel) @@ -1642,7 +1642,7 @@ __STATIC_INLINE cy_stc_dmac_descriptor_t * Cy_DMAC_Channel_GetCurrentDescriptor( * The interrupt status, see \ref group_dmac_macros_interrupt_masks. * * \funcusage -* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_GetInterruptStatus +* \snippet dmac/snippet/main.c snippet_Cy_DMAC_GetInterruptStatus * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_DMAC_Channel_GetInterruptStatus(DMAC_Type const * base, uint32_t channel) @@ -1669,7 +1669,7 @@ __STATIC_INLINE uint32_t Cy_DMAC_Channel_GetInterruptStatus(DMAC_Type const * ba * The interrupt mask, see \ref group_dmac_macros_interrupt_masks. * * \funcusage -* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_ClearInterrupt +* \snippet dmac/snippet/main.c snippet_Cy_DMAC_ClearInterrupt * *******************************************************************************/ __STATIC_INLINE void Cy_DMAC_Channel_ClearInterrupt(DMAC_Type * base, uint32_t channel, uint32_t interrupt) @@ -1698,7 +1698,7 @@ __STATIC_INLINE void Cy_DMAC_Channel_ClearInterrupt(DMAC_Type * base, uint32_t c * The interrupt mask. See \ref group_dmac_macros_interrupt_masks. * * \funcusage -* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_SetInterruptMask +* \snippet dmac/snippet/main.c snippet_Cy_DMAC_SetInterruptMask * *******************************************************************************/ __STATIC_INLINE void Cy_DMAC_Channel_SetInterrupt(DMAC_Type * base, uint32_t channel, uint32_t interrupt) @@ -1726,7 +1726,7 @@ __STATIC_INLINE void Cy_DMAC_Channel_SetInterrupt(DMAC_Type * base, uint32_t cha * The interrupt mask value. See \ref group_dmac_macros_interrupt_masks. * * \funcusage -* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_SetInterruptMask +* \snippet dmac/snippet/main.c snippet_Cy_DMAC_SetInterruptMask * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_DMAC_Channel_GetInterruptMask(DMAC_Type const * base, uint32_t channel) @@ -1753,7 +1753,7 @@ __STATIC_INLINE uint32_t Cy_DMAC_Channel_GetInterruptMask(DMAC_Type const * base * The interrupt mask, see \ref group_dmac_macros_interrupt_masks. * * \funcusage -* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_SetInterruptMask +* \snippet dmac/snippet/main.c snippet_Cy_DMAC_SetInterruptMask * *******************************************************************************/ __STATIC_INLINE void Cy_DMAC_Channel_SetInterruptMask(DMAC_Type * base, uint32_t channel, uint32_t interrupt) @@ -1781,7 +1781,7 @@ __STATIC_INLINE void Cy_DMAC_Channel_SetInterruptMask(DMAC_Type * base, uint32_t * The masked interrupt status. See \ref group_dmac_macros_interrupt_masks. * * \funcusage -* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_ClearInterrupt +* \snippet dmac/snippet/main.c snippet_Cy_DMAC_ClearInterrupt * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_DMAC_Channel_GetInterruptStatusMasked(DMAC_Type const * base, uint32_t channel) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_i2s.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_i2s.h index e295c07136..f488fcb4bd 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_i2s.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_i2s.h @@ -70,7 +70,7 @@ * frame. Only clearing RX FIFO is enough. * * For example: -* \snippet i2s\2.10\snippet\main.c snippet_Cy_I2S_Init +* \snippet i2s/snippet/main.c snippet_Cy_I2S_Init * * If you use a DMA, the DMA channel should be previously configured. The I2S interrupts * (if applicable) can be enabled by calling \ref Cy_I2S_SetInterruptMask. @@ -556,7 +556,7 @@ __STATIC_INLINE uint32_t Cy_I2S_GetInterruptStatusMasked(I2S_Type const * base); * \param base The pointer to the I2S instance address. * * \funcusage -* \snippet i2s\2.10\snippet\main.c snippet_Cy_I2S_EnableTx +* \snippet i2s/snippet/main.c snippet_Cy_I2S_EnableTx * *******************************************************************************/ __STATIC_INLINE void Cy_I2S_EnableTx(I2S_Type * base) @@ -574,7 +574,7 @@ __STATIC_INLINE void Cy_I2S_EnableTx(I2S_Type * base) * \param base The pointer to the I2S instance address. * * \funcusage -* \snippet i2s\2.10\snippet\main.c snippet_Cy_I2S_PauseTx +* \snippet i2s/snippet/main.c snippet_Cy_I2S_PauseTx * *******************************************************************************/ __STATIC_INLINE void Cy_I2S_PauseTx(I2S_Type * base) @@ -592,7 +592,7 @@ __STATIC_INLINE void Cy_I2S_PauseTx(I2S_Type * base) * \param base The pointer to the I2S instance address. * * \funcusage -* \snippet i2s\2.10\snippet\main.c snippet_Cy_I2S_ResumeTx +* \snippet i2s/snippet/main.c snippet_Cy_I2S_ResumeTx * *******************************************************************************/ __STATIC_INLINE void Cy_I2S_ResumeTx(I2S_Type * base) @@ -613,7 +613,7 @@ __STATIC_INLINE void Cy_I2S_ResumeTx(I2S_Type * base) * \param base The pointer to the I2S instance address. * * \funcusage -* \snippet i2s\2.10\snippet\main.c snippet_Cy_I2S_DisableTx +* \snippet i2s/snippet/main.c snippet_Cy_I2S_DisableTx * *******************************************************************************/ __STATIC_INLINE void Cy_I2S_DisableTx(I2S_Type * base) @@ -635,7 +635,7 @@ __STATIC_INLINE void Cy_I2S_DisableTx(I2S_Type * base) * \param base The pointer to the I2S instance address. * * \funcusage -* \snippet i2s\2.10\snippet\main.c snippet_Cy_I2S_EnableRx +* \snippet i2s/snippet/main.c snippet_Cy_I2S_EnableRx * *******************************************************************************/ __STATIC_INLINE void Cy_I2S_EnableRx(I2S_Type * base) @@ -656,7 +656,7 @@ __STATIC_INLINE void Cy_I2S_EnableRx(I2S_Type * base) * \param base The pointer to the I2S instance address. * * \funcusage -* \snippet i2s\2.10\snippet\main.c snippet_Cy_I2S_DisableRx +* \snippet i2s/snippet/main.c snippet_Cy_I2S_DisableRx * *******************************************************************************/ __STATIC_INLINE void Cy_I2S_DisableRx(I2S_Type * base) @@ -676,7 +676,7 @@ __STATIC_INLINE void Cy_I2S_DisableRx(I2S_Type * base) * \return The current state \ref group_i2s_macros_current_state. * * \funcusage -* \snippet i2s\2.10\snippet\main.c snippet_Cy_I2S_GetCurrentState +* \snippet i2s/snippet/main.c snippet_Cy_I2S_GetCurrentState * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_I2S_GetCurrentState(I2S_Type const * base) @@ -694,7 +694,7 @@ __STATIC_INLINE uint32_t Cy_I2S_GetCurrentState(I2S_Type const * base) * \param base The pointer to the I2S instance address. * * \funcusage -* \snippet i2s\2.10\snippet\main.c snippet_Cy_I2S_ClearTxFifo +* \snippet i2s/snippet/main.c snippet_Cy_I2S_ClearTxFifo * *******************************************************************************/ __STATIC_INLINE void Cy_I2S_ClearTxFifo(I2S_Type * base) @@ -716,7 +716,7 @@ __STATIC_INLINE void Cy_I2S_ClearTxFifo(I2S_Type * base) * \return The current number of used words in the TX FIFO. * * \funcusage -* \snippet i2s\2.10\snippet\main.c snippet_Cy_I2S_GetNumInTxFifo +* \snippet i2s/snippet/main.c snippet_Cy_I2S_GetNumInTxFifo * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_I2S_GetNumInTxFifo(I2S_Type const * base) @@ -736,7 +736,7 @@ __STATIC_INLINE uint32_t Cy_I2S_GetNumInTxFifo(I2S_Type const * base) * \param data Data to be written to the TX FIFO. * * \funcusage -* \snippet i2s\2.10\snippet\main.c snippet_Cy_I2S_WriteTxData +* \snippet i2s/snippet/main.c snippet_Cy_I2S_WriteTxData * *******************************************************************************/ __STATIC_INLINE void Cy_I2S_WriteTxData(I2S_Type * base, uint32_t data) @@ -756,7 +756,7 @@ __STATIC_INLINE void Cy_I2S_WriteTxData(I2S_Type * base, uint32_t data) * \return The current TX Read pointer value. * * \funcusage -* \snippet i2s\2.10\snippet\main.c snippet_Cy_I2S_GetTxReadPointer +* \snippet i2s/snippet/main.c snippet_Cy_I2S_GetTxReadPointer * *******************************************************************************/ __STATIC_INLINE uint8_t Cy_I2S_GetTxReadPointer(I2S_Type const * base) @@ -776,7 +776,7 @@ __STATIC_INLINE uint8_t Cy_I2S_GetTxReadPointer(I2S_Type const * base) * \return The current TX Write pointer value. * * \funcusage -* \snippet i2s\2.10\snippet\main.c snippet_Cy_I2S_GetTxWritePointer +* \snippet i2s/snippet/main.c snippet_Cy_I2S_GetTxWritePointer * *******************************************************************************/ __STATIC_INLINE uint8_t Cy_I2S_GetTxWritePointer(I2S_Type const * base) @@ -794,7 +794,7 @@ __STATIC_INLINE uint8_t Cy_I2S_GetTxWritePointer(I2S_Type const * base) * \param base The pointer to the I2S instance address. * * \funcusage -* \snippet i2s\2.10\snippet\main.c snippet_Cy_I2S_FreezeTxFifo +* \snippet i2s/snippet/main.c snippet_Cy_I2S_FreezeTxFifo * *******************************************************************************/ __STATIC_INLINE void Cy_I2S_FreezeTxFifo(I2S_Type * base) @@ -812,7 +812,7 @@ __STATIC_INLINE void Cy_I2S_FreezeTxFifo(I2S_Type * base) * \param base The pointer to the I2S instance address. * * \funcusage -* \snippet i2s\2.10\snippet\main.c snippet_Cy_I2S_UnfreezeTxFifo +* \snippet i2s/snippet/main.c snippet_Cy_I2S_UnfreezeTxFifo * *******************************************************************************/ __STATIC_INLINE void Cy_I2S_UnfreezeTxFifo(I2S_Type * base) @@ -830,7 +830,7 @@ __STATIC_INLINE void Cy_I2S_UnfreezeTxFifo(I2S_Type * base) * \param base The pointer to the I2S instance address. * * \funcusage -* \snippet i2s\2.10\snippet\main.c snippet_Cy_I2S_ClearRxFifo +* \snippet i2s/snippet/main.c snippet_Cy_I2S_ClearRxFifo * *******************************************************************************/ __STATIC_INLINE void Cy_I2S_ClearRxFifo(I2S_Type * base) @@ -852,7 +852,7 @@ __STATIC_INLINE void Cy_I2S_ClearRxFifo(I2S_Type * base) * \return The current number of used words in rge RX FIFO. * * \funcusage -* \snippet i2s\2.10\snippet\main.c snippet_Cy_I2S_GetNumInRxFifo +* \snippet i2s/snippet/main.c snippet_Cy_I2S_GetNumInRxFifo * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_I2S_GetNumInRxFifo(I2S_Type const * base) @@ -872,7 +872,7 @@ __STATIC_INLINE uint32_t Cy_I2S_GetNumInRxFifo(I2S_Type const * base) * \return The read data. * * \funcusage -* \snippet i2s\2.10\snippet\main.c snippet_Cy_I2S_ReadRxData +* \snippet i2s/snippet/main.c snippet_Cy_I2S_ReadRxData * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_I2S_ReadRxData(I2S_Type const * base) @@ -893,7 +893,7 @@ __STATIC_INLINE uint32_t Cy_I2S_ReadRxData(I2S_Type const * base) * \return The read data. * * \funcusage -* \snippet i2s\2.10\snippet\main.c snippet_Cy_I2S_ReadRxDataSilent +* \snippet i2s/snippet/main.c snippet_Cy_I2S_ReadRxDataSilent * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_I2S_ReadRxDataSilent(I2S_Type const * base) @@ -913,7 +913,7 @@ __STATIC_INLINE uint32_t Cy_I2S_ReadRxDataSilent(I2S_Type const * base) * \return The current RX Read pointer value. * * \funcusage -* \snippet i2s\2.10\snippet\main.c snippet_Cy_I2S_GetRxReadPointer +* \snippet i2s/snippet/main.c snippet_Cy_I2S_GetRxReadPointer * *******************************************************************************/ __STATIC_INLINE uint8_t Cy_I2S_GetRxReadPointer(I2S_Type const * base) @@ -933,7 +933,7 @@ __STATIC_INLINE uint8_t Cy_I2S_GetRxReadPointer(I2S_Type const * base) * \return The current RX Write pointer value. * * \funcusage -* \snippet i2s\2.10\snippet\main.c snippet_Cy_I2S_GetRxWritePointer +* \snippet i2s/snippet/main.c snippet_Cy_I2S_GetRxWritePointer * *******************************************************************************/ __STATIC_INLINE uint8_t Cy_I2S_GetRxWritePointer(I2S_Type const * base) @@ -951,7 +951,7 @@ __STATIC_INLINE uint8_t Cy_I2S_GetRxWritePointer(I2S_Type const * base) * \param base The pointer to the I2S instance address. * * \funcusage -* \snippet i2s\2.10\snippet\main.c snippet_Cy_I2S_FreezeRxFifo +* \snippet i2s/snippet/main.c snippet_Cy_I2S_FreezeRxFifo * *******************************************************************************/ __STATIC_INLINE void Cy_I2S_FreezeRxFifo(I2S_Type * base) @@ -969,7 +969,7 @@ __STATIC_INLINE void Cy_I2S_FreezeRxFifo(I2S_Type * base) * \param base The pointer to the I2S instance address. * * \funcusage -* \snippet i2s\2.10\snippet\main.c snippet_Cy_I2S_UnfreezeRxFifo +* \snippet i2s/snippet/main.c snippet_Cy_I2S_UnfreezeRxFifo * *******************************************************************************/ __STATIC_INLINE void Cy_I2S_UnfreezeRxFifo(I2S_Type * base) @@ -989,7 +989,7 @@ __STATIC_INLINE void Cy_I2S_UnfreezeRxFifo(I2S_Type * base) * \return The interrupt bit mask \ref group_i2s_macros_interrupt_masks. * * \funcusage -* \snippet i2s\2.10\snippet\main.c snippet_Cy_I2S_GetInterruptStatus +* \snippet i2s/snippet/main.c snippet_Cy_I2S_GetInterruptStatus * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_I2S_GetInterruptStatus(I2S_Type const * base) @@ -1009,7 +1009,7 @@ __STATIC_INLINE uint32_t Cy_I2S_GetInterruptStatus(I2S_Type const * base) * \param interrupt Interrupt bit mask \ref group_i2s_macros_interrupt_masks. * * \funcusage -* \snippet i2s\2.10\snippet\main.c snippet_Cy_I2S_ClearInterrupt +* \snippet i2s/snippet/main.c snippet_Cy_I2S_ClearInterrupt * *******************************************************************************/ __STATIC_INLINE void Cy_I2S_ClearInterrupt(I2S_Type * base, uint32_t interrupt) @@ -1031,7 +1031,7 @@ __STATIC_INLINE void Cy_I2S_ClearInterrupt(I2S_Type * base, uint32_t interrupt) * \param interrupt Interrupt bit mask \ref group_i2s_macros_interrupt_masks. * * \funcusage -* \snippet i2s\2.10\snippet\main.c snippet_Cy_I2S_SetInterrupt +* \snippet i2s/snippet/main.c snippet_Cy_I2S_SetInterrupt * *******************************************************************************/ __STATIC_INLINE void Cy_I2S_SetInterrupt(I2S_Type * base, uint32_t interrupt) @@ -1052,7 +1052,7 @@ __STATIC_INLINE void Cy_I2S_SetInterrupt(I2S_Type * base, uint32_t interrupt) * \return The interrupt bit mask \ref group_i2s_macros_interrupt_masks. * * \funcusage -* \snippet i2s\2.10\snippet\main.c snippet_Cy_I2S_GetInterruptMask +* \snippet i2s/snippet/main.c snippet_Cy_I2S_GetInterruptMask * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_I2S_GetInterruptMask(I2S_Type const * base) @@ -1072,7 +1072,7 @@ __STATIC_INLINE uint32_t Cy_I2S_GetInterruptMask(I2S_Type const * base) * \param interrupt Interrupt bit mask \ref group_i2s_macros_interrupt_masks. * * \funcusage -* \snippet i2s\2.10\snippet\main.c snippet_Cy_I2S_SetInterruptMask +* \snippet i2s/snippet/main.c snippet_Cy_I2S_SetInterruptMask * *******************************************************************************/ __STATIC_INLINE void Cy_I2S_SetInterruptMask(I2S_Type * base, uint32_t interrupt) @@ -1093,7 +1093,7 @@ __STATIC_INLINE void Cy_I2S_SetInterruptMask(I2S_Type * base, uint32_t interrupt * \return The interrupt bit mask(s) \ref group_i2s_macros_interrupt_masks. * * \funcusage -* \snippet i2s\2.10\snippet\main.c snippet_Cy_I2S_ClearInterrupt +* \snippet i2s/snippet/main.c snippet_Cy_I2S_ClearInterrupt * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_I2S_GetInterruptStatusMasked(I2S_Type const * base) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_ipc_drv.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_ipc_drv.h index fbdb1f4e5e..95d3dc8087 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_ipc_drv.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_ipc_drv.h @@ -458,7 +458,7 @@ __STATIC_INLINE void Cy_IPC_Drv_ClearInterrupt (IPC_INTR_STRUCT_Type * base, * Returns a pointer to the base of the IPC registers. * * \funcusage -* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_SendMsgWord +* \snippet ipc/snippet/main.c snippet_Cy_IPC_Drv_SendMsgWord * *******************************************************************************/ __STATIC_INLINE IPC_STRUCT_Type* Cy_IPC_Drv_GetIpcBaseAddress (uint32_t ipcIndex) @@ -486,7 +486,7 @@ __STATIC_INLINE IPC_STRUCT_Type* Cy_IPC_Drv_GetIpcBaseAddress (uint32_t ipcIndex * Returns a pointer to the base of the IPC interrupt registers. * * \funcusage -* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_GetInterruptStatus +* \snippet ipc/snippet/main.c snippet_Cy_IPC_Drv_GetInterruptStatus * *******************************************************************************/ __STATIC_INLINE IPC_INTR_STRUCT_Type* Cy_IPC_Drv_GetIntrBaseAddr (uint32_t ipcIntrIndex) @@ -516,7 +516,7 @@ __STATIC_INLINE IPC_INTR_STRUCT_Type* Cy_IPC_Drv_GetIntrBaseAddr (uint32_t ipcIn * notify event. * * \funcusage -* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_GetInterruptStatusMasked +* \snippet ipc/snippet/main.c snippet_Cy_IPC_Drv_GetInterruptStatusMasked * *******************************************************************************/ __STATIC_INLINE void Cy_IPC_Drv_SetInterruptMask (IPC_INTR_STRUCT_Type* base, @@ -548,7 +548,7 @@ __STATIC_INLINE void Cy_IPC_Drv_SetInterruptMask (IPC_INTR_STRUCT_Type* base, *
    VersionChangesReason for Change
    2.20The channel number validation method is updated.New devices support.
    2.10Flattened the organization of the driver source code into the single source directory and the single include directory.Driver library directory-structure simplification.
    * * \funcusage -* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_GetInterruptStatusMasked +* \snippet ipc/snippet/main.c snippet_Cy_IPC_Drv_GetInterruptStatusMasked * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_IPC_Drv_GetInterruptMask(IPC_INTR_STRUCT_Type const * base) @@ -578,7 +578,7 @@ __STATIC_INLINE uint32_t Cy_IPC_Drv_GetInterruptMask(IPC_INTR_STRUCT_Type const *
* * \funcusage -* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_GetInterruptStatusMasked +* \snippet ipc/snippet/main.c snippet_Cy_IPC_Drv_GetInterruptStatusMasked * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_IPC_Drv_GetInterruptStatusMasked (IPC_INTR_STRUCT_Type const * base) @@ -608,7 +608,7 @@ __STATIC_INLINE uint32_t Cy_IPC_Drv_GetInterruptStatusMasked (IPC_INTR_STRUCT_Ty * * * \funcusage -* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_GetInterruptStatus +* \snippet ipc/snippet/main.c snippet_Cy_IPC_Drv_GetInterruptStatus * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_IPC_Drv_GetInterruptStatus(IPC_INTR_STRUCT_Type const * base) @@ -639,7 +639,7 @@ __STATIC_INLINE uint32_t Cy_IPC_Drv_GetInterruptStatus(IPC_INTR_STRUCT_Type cons * notify event. * * \funcusage -* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_SetInterrupt +* \snippet ipc/snippet/main.c snippet_Cy_IPC_Drv_SetInterrupt * *******************************************************************************/ __STATIC_INLINE void Cy_IPC_Drv_SetInterrupt(IPC_INTR_STRUCT_Type* base, uint32_t ipcReleaseMask, uint32_t ipcAcquireMask) @@ -671,7 +671,7 @@ __STATIC_INLINE void Cy_IPC_Drv_SetInterrupt(IPC_INTR_STRUCT_Type* base, uint32 * notify event. * * \funcusage -* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_GetInterruptStatusMasked +* \snippet ipc/snippet/main.c snippet_Cy_IPC_Drv_GetInterruptStatusMasked * *******************************************************************************/ __STATIC_INLINE void Cy_IPC_Drv_ClearInterrupt(IPC_INTR_STRUCT_Type* base, uint32_t ipcReleaseMask, uint32_t ipcAcquireMask) @@ -706,7 +706,7 @@ __STATIC_INLINE void Cy_IPC_Drv_ClearInterrupt(IPC_INTR_STRUCT_Type* base, uint * structure. * * \funcusage -* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_LockAcquire +* \snippet ipc/snippet/main.c snippet_Cy_IPC_Drv_LockAcquire * *******************************************************************************/ __STATIC_INLINE void Cy_IPC_Drv_AcquireNotify (IPC_STRUCT_Type* base, uint32_t notifyEventIntr) @@ -732,7 +732,7 @@ __STATIC_INLINE void Cy_IPC_Drv_AcquireNotify (IPC_STRUCT_Type* base, uint32_t * Bit encoded list of IPC interrupt lines that are triggered by a notification. * * \funcusage -* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_ReadMsgWord +* \snippet ipc/snippet/main.c snippet_Cy_IPC_Drv_ReadMsgWord * *******************************************************************************/ __STATIC_INLINE void Cy_IPC_Drv_ReleaseNotify (IPC_STRUCT_Type* base, uint32_t notifyEventIntr) @@ -811,7 +811,7 @@ __STATIC_INLINE uint32_t Cy_IPC_Drv_ReadDataValue (IPC_STRUCT_Type const * base) * false: The IPC channel is in the Released state. * * \funcusage -* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_LockAcquire +* \snippet ipc/snippet/main.c snippet_Cy_IPC_Drv_LockAcquire * *******************************************************************************/ __STATIC_INLINE bool Cy_IPC_Drv_IsLockAcquired (IPC_STRUCT_Type const * base) @@ -836,7 +836,7 @@ __STATIC_INLINE bool Cy_IPC_Drv_IsLockAcquired (IPC_STRUCT_Type const * base) * Value from LOCK_STATUS register. * * \funcusage -* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_GetLockStatus +* \snippet ipc/snippet/main.c snippet_Cy_IPC_Drv_GetLockStatus * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_IPC_Drv_GetLockStatus (IPC_STRUCT_Type const * base) @@ -922,7 +922,7 @@ __STATIC_INLINE uint32_t Cy_IPC_Drv_ExtractReleaseMask (uint32_t intMask) * it is already locked. * * \funcusage -* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_SendMsgPtr +* \snippet ipc/snippet/main.c snippet_Cy_IPC_Drv_SendMsgPtr * *******************************************************************************/ __STATIC_INLINE cy_en_ipcdrv_status_t Cy_IPC_Drv_SendMsgPtr(IPC_STRUCT_Type* base, uint32_t notifyEventIntr, void const * msgPtr) @@ -957,7 +957,7 @@ __STATIC_INLINE cy_en_ipcdrv_status_t Cy_IPC_Drv_SendMsgPtr(IPC_STRUCT_Type* ba * in it is invalid. * * \funcusage -* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_ReadMsgPtr +* \snippet ipc/snippet/main.c snippet_Cy_IPC_Drv_ReadMsgPtr * *******************************************************************************/ __STATIC_INLINE cy_en_ipcdrv_status_t Cy_IPC_Drv_ReadMsgPtr (IPC_STRUCT_Type const * base, void ** msgPtr) @@ -985,7 +985,7 @@ __STATIC_INLINE cy_en_ipcdrv_status_t Cy_IPC_Drv_ReadMsgPtr (IPC_STRUCT_Type c * by another master * * \funcusage -* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_LockAcquire +* \snippet ipc/snippet/main.c snippet_Cy_IPC_Drv_LockAcquire * *******************************************************************************/ __STATIC_INLINE cy_en_ipcdrv_status_t Cy_IPC_Drv_LockAcquire (IPC_STRUCT_Type const * base) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_lpcomp.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_lpcomp.h index 8e5e2a7b79..ca6805ad68 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_lpcomp.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_lpcomp.h @@ -101,7 +101,7 @@ * The LED blinks twice after device reset and goes into Hibernate mode. * When the voltage on the positive input great than the local reference * voltage (0.45V - 0.75V) the device wakes up and LED begins blinking. -* \snippet lpcomp\1.20\snippet\main.c LP_COMP_CFG_HIBERNATE +* \snippet lpcomp/snippet/main.c LP_COMP_CFG_HIBERNATE * * \section group_lpcomp_more_information More Information * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_pdl.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_pdl.h index 3ed8b87027..35e5b81b26 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_pdl.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_pdl.h @@ -57,6 +57,7 @@ #include "cy_scb_spi.h" #include "cy_scb_uart.h" #include "cy_sd_host.h" +#include "cy_seglcd.h" #include "cy_smartio.h" #include "cy_smif.h" #include "cy_smif_memslot.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_prot.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_prot.h index cbc9ffa23b..8842e1a735 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_prot.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_prot.h @@ -152,7 +152,7 @@ * and bit 3 - the valid field for CM0_PC3_HANDLER. * * The example of using of the single entry point mechanism is shown below. -* \snippet prot/1.20/snippet/main.c snippet_Cy_Prot_ProtectionContext +* \snippet prot/snippet/main.c snippet_Cy_Prot_ProtectionContext * * \section group_prot_access_evaluation Access Evaluation * @@ -1083,7 +1083,7 @@ cy_en_prot_status_t Cy_Prot_DisablePpuFixedRgSlaveStruct(PERI_GR_PPU_RG_Type* ba * CY_PROT_INVALID_STATE | Function was called on the unsupported PERI IP version * * \funcusage -* \snippet prot/1.20/snippet/main.c snippet_Cy_Prot_DisableSmpuStruct +* \snippet prot/snippet/main.c snippet_Cy_Prot_DisableSmpuStruct * *******************************************************************************/ __STATIC_INLINE cy_en_prot_status_t Cy_Prot_DisableSmpuStruct(PROT_SMPU_SMPU_STRUCT_Type* base) @@ -1127,7 +1127,7 @@ __STATIC_INLINE cy_en_prot_status_t Cy_Prot_DisableSmpuStruct(PROT_SMPU_SMPU_STR * CY_PROT_INVALID_STATE | Function was called on the unsupported PERI IP version * * \funcusage -* \snippet prot/1.20/snippet/main.c snippet_Cy_Prot_DisablePpuProgStruct +* \snippet prot/snippet/main.c snippet_Cy_Prot_DisablePpuProgStruct * *******************************************************************************/ __STATIC_INLINE cy_en_prot_status_t Cy_Prot_DisablePpuProgStruct(PERI_PPU_PR_Type* base) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_common.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_common.h index 0d4d1fc1bc..7630221764 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_common.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_common.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_scb_common.h -* \version 2.20 +* \version 2.30 * * Provides common API declarations of the SCB driver. * @@ -41,6 +41,251 @@ * \defgroup group_scb_uart UART (SCB) * \} */ +/** +* \addtogroup group_scb +* \{ +* +******************************************************************************** +* \section group_scb_more_information More Information +******************************************************************************** +* For more information on the SCB peripheral, refer to the technical reference +* manual (TRM). +* +******************************************************************************* +* \section group_scb_common_MISRA MISRA-C Compliance +******************************************************************************* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
MISRA ruleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
11.4AA cast should not be performed between a pointer to object type and +* a different pointer to object type. +* * The pointer to the buffer memory is void to allow handling of +* different data types: uint8_t (4-8 bits) or uint16_t (9-16 bits). +* The cast operation is safe because the configuration is verified +* before operation is performed. +* * The functions \ref Cy_SCB_I2C_DeepSleepCallback and +* \ref Cy_SCB_I2C_HibernateCallback are callback of +* \ref cy_en_syspm_status_t type. The cast operation safety in these +* functions becomes the user's responsibility because pointers are +* initialized when callback is registered in SysPm driver. +* * The functions \ref Cy_SCB_EZI2C_DeepSleepCallback and +* \ref Cy_SCB_EZI2C_HibernateCallback are callback of +* \ref cy_en_syspm_status_t type. The cast operation safety in these +* functions becomes the user's responsibility because pointers are +* initialized when callback is registered in SysPm driver. +* * The functions \ref Cy_SCB_UART_DeepSleepCallback and +* \ref Cy_SCB_UART_HibernateCallback are callback of +* \ref cy_en_syspm_status_t type. The cast operation safety in these +* functions becomes the user's responsibility because pointers are +* initialized when callback is registered in SysPm driver. +* * The functions \ref Cy_SCB_SPI_DeepSleepCallback and +* \ref Cy_SCB_SPI_HibernateCallback are callback of +* \ref cy_en_syspm_status_t type. The cast operation safety in these +* functions becomes the user's responsibility because pointers are +* initialized when callback is registered in SysPm driver. +*
14.1RThere shall be no unreachable code.The SCB block parameters can be a constant false or true depends on +* the selected device and cause code to be unreachable.
14.2RAll non-null statements shall either: a) have at least one side-effect +* however executed, or b) cause control flow to change.The unused function parameters are cast to void. This statement +* has no side-effect and is used to suppress a compiler warning.
14.7RA function shall have a single point of exit at the end of the +* function.The functions can return from several points. This is done to improve +* code clarity when returning error status code if input parameters +* validation fails.
13.7RBoolean operations whose results are invariant shall not be +* permitted. +* * The SCB block parameters can be a constant false or true depends on +* the selected device and cause this violation. +* * The same condition check is executed before and after callback is +* called because after the callback returns, the condition might be not +* true any more.
+* +******************************************************************************* +* \section group_scb_common_changelog Changelog +******************************************************************************* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
VersionChangesReason for Change
2.30Fixed MISRA violation.MISRA compliance.
Changed values CY_SCB_SPI_CPHA0_CPOL1 and CY_SCB_SPI_CPHA1_CPOL0 in enum \ref cy_en_scb_spi_sclk_mode_t.The incorrect values in \ref cy_en_scb_spi_sclk_mode_t caused incorrect initialization of the combination of +* phases and polarity: "CHPA = 0, CPOL = 1" and "CHPA = 1, CPOL = 0". +*
Added new CY_SCB_UART_RECEIVE_NOT_EMTPY and CY_SCB_UART_TRANSMIT_EMTPY callback events \ref group_scb_uart_macros_callback_events.Extended the driver callback events to support the MBED-OS.
Merged SCB changelogs for each mode into one changelog.Changelog optimization.
Merged SCB MISRA-C Compliance sections for each mode into one section.To optimize the SCB MISRA-C Compliance sections.
2.20.1Documentation of the MISRA rule violation.MISRA compliance.
2.20Flattened the organization of the driver source code into the single +* source directory and the single include directory. +* Driver library directory-structure simplification.
Added register access layer. Use register access macros instead +* of direct register access using dereferenced pointers.Makes register access device-independent, so that the PDL does +* not need to be recompiled for each supported part number.
Added the enableDigitalFilter, highPhaseDutyCycle and lowPhaseDutyCycle +* fields to the \ref cy_stc_scb_i2c_config_t configuration structure. +* Added the I2C master data rate configuration using the configuration structure. +*
Fixed the \ref Cy_SCB_I2C_SetDataRate function to properly configure data rates +* greater than 400 kbps in Master and Master-Slave modes. \n +* Added verification that clk_scb is within the valid range for the desired data rate. +* The analog filter was enabled for all data rates in Master and Master-Slave modes. +* This prevents reaching the maximum supported data rate of 1000 kbps which requires a digital filter. +*
2.10Fixed the ReStart condition generation sequence for a write +* transaction in the \ref Cy_SCB_I2C_MasterWrite function.The driver can notify about a zero length write transaction completion +* before the address byte is sent if the \ref Cy_SCB_I2C_MasterWrite +* function execution was interrupted between setting the restart +* generation command and writing the address byte into the TX FIFO.
Added the slave- and master-specific interrupt functions: +* \ref Cy_SCB_I2C_SlaveInterrupt and \ref Cy_SCB_I2C_MasterInterrupt. +* Improved the interrupt configuration options for the I2C slave and +* master mode configurations.
Updated the Start condition generation sequence in the \ref +* Cy_SCB_I2C_MasterWrite and \ref Cy_SCB_I2C_MasterRead.
Updated the ReStart condition generation sequence for a write +* transaction in the \ref Cy_SCB_I2C_MasterSendReStart function.
2.0Added parameters validation for public API. +*
Fixed functions which return interrupt status to return only defined +* set of interrupt statuses.
Added missing "cy_cb_" to the callback function type names.
Replaced variables that have limited range of values with enumerated +* types.
Added function \ref Cy_SCB_UART_SendBreakBlocking for break condition +* generation.
Fixed low power callbacks \ref Cy_SCB_UART_DeepSleepCallback and +* \ref Cy_SCB_UART_HibernateCallback to prevent the device from entering +* low power mode when RX FIFO is not empty.The callbacks allowed entering device into low power mode when RX FIFO +* had data.
Fixed SPI callback notification when error event occurred.The SPI callback passed incorrect event value if error event occurred.
Fixed the \ref Cy_SCB_I2C_MasterSendReStart function to properly +* generate the ReStart condition when the previous transaction was +* a write.The master interpreted the address byte written into the TX FIFO as a +* data byte and continued a write transaction. The ReStart condition was +* generated after the master completed transferring the data byte. +* The SCL line was stretched by the master waiting for the address byte +* to be written into the TX FIFO after the ReStart condition generation. +* The following timeout detection released the bus from the master +* control.
Fixed the slave operation after the address byte was NACKed by the +* firmware.The observed slave operation failure depends on whether Level 2 assert +* is enabled or not. Enabled: the device stuck in the fault handler due +* to the assert assignment in the \ref Cy_SCB_I2C_Interrupt. Disabled: +* the slave sets the transaction completion status and notifies on the +* transaction completion event after the address was NACKed. The failure +* is observed only when the slave is configured to accept an address in +* the RX FIFO.
1.0Initial version.
+*/ + +/** \} group_scb */ /** * \addtogroup group_scb_common * \{ @@ -64,74 +309,6 @@ ******************************************************************************** * This is not a driver and it does not require configuration. * -******************************************************************************* -* \section group_scb_common_more_information More Information -******************************************************************************* -* Refer to the SCB chapter of the technical reference manual (TRM). -* -******************************************************************************* -* \section group_scb_common_MISRA MISRA-C Compliance -******************************************************************************* -* -* -* -* -* -* -* -* -* -* -* -* -* -*
MISRA ruleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
11.4AA cast should not be performed between a pointer to object type and -* a different pointer to object type.The pointer to the buffer memory is void to allow handling of -* different data types: uint8_t (4-8 bits) or uint16_t (9-16 bits). -* The cast operation is safe because the configuration is verified -* before operation is performed. -*
-* -******************************************************************************* -* \section group_scb_common_changelog Changelog -******************************************************************************* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -*
VersionChangesReason for Change
2.20Flattened the organization of the driver source code into the single -* source directory and the single include directory. -* Driver library directory-structure simplification.
Added register access layer. Use register access macros instead -* of direct register access using dereferenced pointers.Makes register access device-independent, so that the PDL does -* not need to be recompiled for each supported part number.
2.10None.SCB I2C driver updated.
2.0Added parameters validation for public API. -*
Fixed functions which return interrupt status to return only defined -* set of interrupt statuses.
1.0Initial version.
-* * \defgroup group_scb_common_macros Macros * \defgroup group_scb_common_functions Functions * \defgroup group_scb_common_data_structures Data Structures @@ -261,7 +438,7 @@ __STATIC_INLINE uint32_t Cy_SCB_GetRxFifoLevel (CySCB_Type const *base); #define CY_SCB_DRV_VERSION_MAJOR (2) /** Driver minor version */ -#define CY_SCB_DRV_VERSION_MINOR (20) +#define CY_SCB_DRV_VERSION_MINOR (30) /** SCB driver identifier */ #define CY_SCB_ID CY_PDL_DRV_ID(0x2AU) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_ezi2c.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_ezi2c.h index 0283cfc639..c8c77b825a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_ezi2c.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_ezi2c.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_scb_ezi2c.h -* \version 2.20 +* \version 2.30 * * Provides EZI2C API declarations of the SCB driver. * @@ -226,97 +226,6 @@ * source from Deep Sleep mode, the \ref Cy_SCB_EZI2C_DeepSleepCallback must * be copied and modified. Refer to the function description to get the details. * -******************************************************************************** -* \section group_scb_ezi2c_more_information More Information -******************************************************************************** -* For more information on the SCB peripheral, refer to the technical reference -* manual (TRM). -* -******************************************************************************** -* \section group_scb_ezi2c_MISRA MISRA-C Compliance -******************************************************************************** -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -*
MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
11.4AA cast should not be performed between a pointer to object type and -* a different pointer to object type.The functions \ref Cy_SCB_EZI2C_DeepSleepCallback and -* \ref Cy_SCB_EZI2C_HibernateCallback are callback of -* \ref cy_en_syspm_status_t type. The cast operation safety in these -* functions becomes the user's responsibility because pointers are -* initialized when callback is registered in SysPm driver.
14.1RThere shall be no unreachable code.The SCB block parameters can be a constant false or true depending on -* the selected device and cause code to be unreachable.
14.2RAll non-null statements shall either: a) have at least one side-effect -* however executed, or b) cause control flow to change.The unused function parameters are cast to void. This statement -* has no side-effect and is used to suppress a compiler warning.
14.7RA function shall have a single point of exit at the end of the -* function.The functions can return from several points. This is done to improve -* code clarity when returning error status code if input parameter -* validation fails.
-* -* \section group_scb_ezi2c_changelog Changelog -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -*
VersionChangesReason for Change
2.20Flattened the organization of the driver source code into the single -* source directory and the single include directory. -* Driver library directory-structure simplification.
Added register access layer. Use register access macros instead -* of direct register access using dereferenced pointers.Makes register access device-independent, so that the PDL does -* not need to be recompiled for each supported part number.
2.10None.SCB I2C driver updated.
2.0Added parameters validation for public API.
Replaced variables that have limited range of values with enumerated -* types.
1.0Initial version.
-* * \defgroup group_scb_ezi2c_macros Macros * \defgroup group_scb_ezi2c_functions Functions * \{ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_i2c.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_i2c.h index adcd6e74af..11833c7997 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_i2c.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_i2c.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_scb_i2c.h -* \version 2.20 +* \version 2.30 * * Provides I2C API declarations of the SCB driver. * @@ -285,173 +285,6 @@ * source from Deep Sleep mode, the \ref Cy_SCB_I2C_DeepSleepCallback must be * copied and modified. Refer to the function description to get the details. * -******************************************************************************** -* \section group_scb_i2c_more_information More Information -******************************************************************************** -* For more information on the SCB peripheral, refer to the technical reference -* manual (TRM). -* -******************************************************************************** -* \section group_scb_i2c_MISRA MISRA-C Compliance -******************************************************************************** -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -*
MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
11.4AA cast should not be performed between a pointer to object type and -* a different pointer to object type.The functions \ref Cy_SCB_I2C_DeepSleepCallback and -* \ref Cy_SCB_I2C_HibernateCallback are callback of -* \ref cy_en_syspm_status_t type. The cast operation safety in these -* functions becomes the user's responsibility because pointers are -* initialized when callback is registered in SysPm driver.
14.1RThere shall be no unreachable code.The SCB block parameters can be a constant false or true depends on -* the selected device and cause code to be unreachable.
13.7RBoolean operations whose results are invariant shall not be -* permitted. -* * The SCB block parameters can be a constant false or true depends on -* the selected device and cause this violation. -* * The same condition check is executed before and after callback is -* called because after the callback returns, the condition might be not -* true any more.
14.2RAll non-null statements shall either: a) have at least one side-effect -* however executed, or b) cause control flow to change.The unused function parameters are cast to void. This statement -* has no side-effect and is used to suppress a compiler warning.
14.7RA function shall have a single point of exit at the end of the -* function.The functions can return from several points. This is done to improve -* code clarity when returning error status code if input parameters -* validation fails.
-* -* \section group_scb_i2c_changelog Changelog -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -*
VersionChangesReason for Change
2.20Flattened the organization of the driver source code into the single -* source directory and the single include directory. -* Driver library directory-structure simplification.
Added the enableDigitalFilter, highPhaseDutyCycle and lowPhaseDutyCycle -* fields to the \ref cy_stc_scb_i2c_config_t configuration structure. -* Added the I2C master data rate configuration using the configuration structure. -*
Fixed the \ref Cy_SCB_I2C_SetDataRate function to properly configure data rates -* greater than 400 kbps in Master and Master-Slave modes. \n -* Added verification that clk_scb is within the valid range for the desired data rate. -* The analog filter was enabled for all data rates in Master and Master-Slave modes. -* This prevents reaching the maximum supported data rate of 1000 kbps which requires a digital filter. -*
Added register access layer. Use register access macros instead -* of direct register access using dereferenced pointers.Makes register access device-independent, so that the PDL does -* not need to be recompiled for each supported part number.
2.10Fixed the ReStart condition generation sequence for a write -* transaction in the \ref Cy_SCB_I2C_MasterWrite function.The driver can notify about a zero length write transaction completion -* before the address byte is sent if the \ref Cy_SCB_I2C_MasterWrite -* function execution was interrupted between setting the restart -* generation command and writing the address byte into the TX FIFO.
Added the slave- and master-specific interrupt functions: -* \ref Cy_SCB_I2C_SlaveInterrupt and \ref Cy_SCB_I2C_MasterInterrupt. -* Improved the interrupt configuration options for the I2C slave and -* master mode configurations.
Updated the Start condition generation sequence in the \ref -* Cy_SCB_I2C_MasterWrite and \ref Cy_SCB_I2C_MasterRead.
Updated the ReStart condition generation sequence for a write -* transaction in the \ref Cy_SCB_I2C_MasterSendReStart function.
2.0Fixed the \ref Cy_SCB_I2C_MasterSendReStart function to properly -* generate the ReStart condition when the previous transaction was -* a write.The master interpreted the address byte written into the TX FIFO as a -* data byte and continued a write transaction. The ReStart condition was -* generated after the master completed transferring the data byte. -* The SCL line was stretched by the master waiting for the address byte -* to be written into the TX FIFO after the ReStart condition generation. -* The following timeout detection released the bus from the master -* control.
Fixed the slave operation after the address byte was NACKed by the -* firmware.The observed slave operation failure depends on whether Level 2 assert -* is enabled or not. Enabled: the device stuck in the fault handler due -* to the assert assignment in the \ref Cy_SCB_I2C_Interrupt. Disabled: -* the slave sets the transaction completion status and notifies on the -* transaction completion event after the address was NACKed. The failure -* is observed only when the slave is configured to accept an address in -* the RX FIFO.
Added parameters validation for public API.
Replaced variables which have limited range of values with enumerated -* types.
Added missing "cy_cb_" to the callback function type names.
1.0Initial version.
-* * \defgroup group_scb_i2c_macros Macros * \defgroup group_scb_i2c_functions Functions * \{ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_spi.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_spi.h index 119d46be74..30791264b3 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_spi.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_spi.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_scb_spi.h -* \version 2.20 +* \version 2.30 * * Provides SPI API declarations of the SCB driver. * @@ -273,118 +273,6 @@ * source from Deep Sleep mode, the \ref Cy_SCB_SPI_DeepSleepCallback must be * copied and modified. Refer to the function description to get the details. * -******************************************************************************** -* \section group_scb_spi_more_information More Information -******************************************************************************** -* For more information on the SCB peripheral, refer to the technical reference -* manual (TRM). -* -******************************************************************************** -* \section group_scb_spi_MISRA MISRA-C Compliance -******************************************************************************** -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -*
MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
11.4AA cast should not be performed between a pointer to object type and -* a different pointer to object type. -* * The pointer to the buffer memory is void to allow handling -* different data types: uint8_t (4-8 bits) or uint16_t (9-16 bits). -* The cast operation is safe because the configuration is verified -* before operation is performed. -* * The functions \ref Cy_SCB_SPI_DeepSleepCallback and -* \ref Cy_SCB_SPI_HibernateCallback are callback of -* \ref cy_en_syspm_status_t type. The cast operation safety in these -* functions becomes the user's responsibility because pointers are -* initialized when callback is registered in SysPm driver.
13.7RBoolean operations whose results are invariant shall not be -* permitted.The SCB block parameters can be a constant false or true depends on -* the selected device and cause this violation.
14.1RThere shall be no unreachable code.The SCB block parameters can be a constant false or true depends on -* the selected device and cause code to be unreachable.
14.2RAll non-null statements shall either: a) have at least one side-effect -* however executed, or b) cause control flow to change.The unused function parameters are cast to void. This statement -* has no side-effect and is used to suppress a compiler warning.
14.7RA function shall have a single point of exit at the end of the -* function.The functions can return from several points. This is done to improve -* code clarity when returning error status code if input parameters -* validation is failed.
-* -* \section group_scb_spi_changelog Changelog -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -*
VersionChangesReason for Change
2.20Flattened the organization of the driver source code into the single -* source directory and the single include directory. -* Driver library directory-structure simplification.
Added register access layer. Use register access macros instead -* of direct register access using dereferenced pointers.Makes register access device-independent, so that the PDL does -* not need to be recompiled for each supported part number.
2.10None.SCB I2C driver updated.
2.0Fixed SPI callback notification when error event occurred.The SPI callback passed incorrect event value if error event occurred.
Added parameters validation for public API.
Replaced variables that have limited range of values with enumerated -* types.
Added missing "cy_cb_" to the callback function type names.
1.0Initial version.
-* * \defgroup group_scb_spi_macros Macros * \defgroup group_scb_spi_functions Functions * \{ @@ -467,8 +355,8 @@ typedef enum typedef enum { CY_SCB_SPI_CPHA0_CPOL0 = 0U, /**< Clock is active low, data is changed on first edge */ - CY_SCB_SPI_CPHA0_CPOL1 = 1U, /**< Clock is active high, data is changed on first edge */ - CY_SCB_SPI_CPHA1_CPOL0 = 2U, /**< Clock is active low, data is changed on second edge */ + CY_SCB_SPI_CPHA1_CPOL0 = 1U, /**< Clock is active low, data is changed on second edge */ + CY_SCB_SPI_CPHA0_CPOL1 = 2U, /**< Clock is active high, data is changed on first edge */ CY_SCB_SPI_CPHA1_CPOL1 = 3U, /**< Clock is active high, data is changed on second edge */ } cy_en_scb_spi_sclk_mode_t; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_uart.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_uart.h index 4d78eb7cdc..1230065ea1 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_uart.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_uart.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_scb_uart.h -* \version 2.20 +* \version 2.30 * * Provides UART API declarations of the SCB driver. * @@ -273,111 +273,6 @@ * to the appropriate UART lines to keep them inactive during Deep-Sleep or * Hibernate. * -******************************************************************************** -* \section group_scb_uart_more_information More Information -******************************************************************************** -* For more information on the SCB peripheral, refer to the technical reference -* manual (TRM). -* -******************************************************************************** -* \section group_scb_uart_MISRA MISRA-C Compliance -******************************************************************************** -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -*
MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
11.4AA cast should not be performed between a pointer to object type and -* a different pointer to object type. -* * The pointer to the buffer memory is void to allow handling different -* different data types: uint8_t (4-8 bits) or uint16_t (9-16 bits). -* The cast operation is safe because the configuration is verified -* before operation is performed. -* * The functions \ref Cy_SCB_UART_DeepSleepCallback and -* \ref Cy_SCB_UART_HibernateCallback are callback of -* \ref cy_en_syspm_status_t type. The cast operation safety in these -* functions becomes the user's responsibility because pointers are -* initialized when callback is registered in SysPm driver.
14.2RAll non-null statements shall either: a) have at least one side-effect -* however executed, or b) cause control flow to change.The unused function parameters are cast to void. This statement -* has no side-effect and is used to suppress a compiler warning.
14.7RA function shall have a single point of exit at the end of the -* function.The functions can return from several points. This is done to improve -* code clarity when returning error status code if input parameters -* validation fails.
-* -* \section group_scb_uart_changelog Changelog -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -*
VersionChangesReason for Change
2.20Flattened the organization of the driver source code into the single -* source directory and the single include directory. -* Driver library directory-structure simplification.
Added register access layer. Use register access macros instead -* of direct register access using dereferenced pointers.Makes register access device-independent, so that the PDL does -* not need to be recompiled for each supported part number.
2.10None.SCB I2C driver updated.
2.0Added parameters validation for public API.
Replaced variables that have limited range of values with enumerated -* types.
Added missing "cy_cb_" to the callback function type names.
Added function \ref Cy_SCB_UART_SendBreakBlocking for break condition -* generation.
Fixed low power callbacks \ref Cy_SCB_UART_DeepSleepCallback and -* \ref Cy_SCB_UART_HibernateCallback to prevent the device from entering -* low power mode when RX FIFO is not empty.The callbacks allowed entering device into low power mode when RX FIFO -* had data.
1.0Initial version.
-* * \defgroup group_scb_uart_macros Macros * \defgroup group_scb_uart_functions Functions * \{ @@ -955,8 +850,15 @@ cy_en_syspm_status_t Cy_SCB_UART_HibernateCallback(cy_stc_syspm_callback_params_ * the source of the error */ #define CY_SCB_UART_TRANSMIT_ERR_EVENT (0x20UL) + +/** The receive fifo is not empty. To use this event the \ref CY_SCB_RX_INTR_NOT_EMPTY interrupt must be enabled by the user. */ +#define CY_SCB_UART_RECEIVE_NOT_EMTPY (0x40UL) + +/** The transmit fifo is empty. To use this event the \ref CY_SCB_UART_TX_EMPTY interrupt must be enabled by the user. */ +#define CY_SCB_UART_TRANSMIT_EMTPY (0x80UL) /** \} group_scb_uart_macros_callback_events */ + /** Data returned by the hardware when an empty RX FIFO is read */ #define CY_SCB_UART_RX_NO_DATA (0xFFFFFFFFUL) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sd_host.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sd_host.h index fd9b5c43e8..c08d4c95bb 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sd_host.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sd_host.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_sd_host.h -* \version 1.10 +* \version 1.20 * * This file provides constants and parameter values for * the SD Host Controller driver. @@ -107,12 +107,12 @@ * register must be configured to connect the block to the pins. Also, the SD Host * pins must be configured in Strong Drive, Input buffer on: * -* \snippet sd_host\1.0\snippet\main.c SD_HOST_CFG_PINS +* \snippet sd_host/snippet/main.c SD_HOST_CFG_PINS * * \subsection group_sd_host_clock Assign Clock Source * The SD Host is sourced from the CLK_HF clock. The clock must be set to 100 MHz: * -* \snippet sd_host\1.0\snippet\main.c SD_HOST_CFG_ASSIGN_CLOCK +* \snippet sd_host/snippet/main.c SD_HOST_CFG_ASSIGN_CLOCK * * \subsection group_sd_host_intr Configure Interrupt (Optional) * The user can set up the interrupt for SD Host operation. @@ -126,8 +126,8 @@ * To clear the interrupt statuses, use \ref Cy_SD_Host_ClearNormalInterruptStatus * and \ref Cy_SD_Host_ClearErrorInterruptStatus. * -* \snippet sd_host\1.0\snippet\main.c SD_HOST_INTR_A -* \snippet sd_host\1.0\snippet\main.c SD_HOST_INTR_B +* \snippet sd_host/snippet/main.c SD_HOST_INTR_A +* \snippet sd_host/snippet/main.c SD_HOST_INTR_B * * \subsection group_sd_host_config Configure SD Host * To set up the SD Host driver, provide the configuration parameters in the @@ -138,8 +138,8 @@ * function providing a pointer to the filled \ref cy_stc_sd_host_init_config_t * structure and allocated \ref cy_stc_sd_host_context_t. * -* \snippet sd_host\1.0\snippet\main.c SD_HOST_CONTEXT -* \snippet sd_host\1.0\snippet\main.c SD_HOST_CFG +* \snippet sd_host/snippet/main.c SD_HOST_CONTEXT +* \snippet sd_host/snippet/main.c SD_HOST_CFG * * The SD, eMMC or SDIO card can be configured using the \ref Cy_SD_Host_InitCard * function as a pointer to the filled \ref cy_stc_sd_host_sd_card_config_t @@ -149,7 +149,7 @@ * Finally, enable the card operation calling * \ref Cy_SD_Host_InitCard. * -* \snippet sd_host\1.0\snippet\main.c SD_HOST_ENABLE_CARD_INIT +* \snippet sd_host/snippet/main.c SD_HOST_ENABLE_CARD_INIT * * \section group_sd_host_use_cases Common Use Cases * @@ -167,7 +167,7 @@ * the user should check the further data-transaction complete event. * The example below shows sending and reading data in DMA mode. * -* \snippet sd_host\1.0\snippet\main.c SD_HOST_WRITE_READ_ADMA2 +* \snippet sd_host/snippet/main.c SD_HOST_WRITE_READ_ADMA2 * * \subsubsection group_sd_host_master_ll Use Low-Level Functions * Call \ref Cy_SD_Host_InitDataTransfer to initialize the SD block @@ -179,7 +179,7 @@ * ADMA3 mode requires calling \ref Cy_SD_Host_InitDataTransfer to * initialize the DMA transaction. The ADMA3 mode example is shown below. * -* \snippet sd_host\1.0\snippet\main.c SD_HOST_WRITE_READ_ADMA3 +* \snippet sd_host/snippet/main.c SD_HOST_WRITE_READ_ADMA3 * * \subsection group_sd_host_emmc_card_mode eMMC Card Operation * eMMC cards use the same API for writing and reading data. @@ -245,12 +245,45 @@ * a detailed description of the registers. * * \section group_sd_host_MISRA MISRA-C Compliance -* The SD Host driver does not have any driver-specific deviations. +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
11.4AA cast should not be performed between a pointer to object type and +* a different pointer to object type. +* The function \ref Cy_SD_Host_DeepSleepCallback is the callback of +* the \ref cy_en_syspm_status_t type. The cast operation safety in these +* functions becomes the user's responsibility because pointers are +* initialized when the callback is registered in the SysPm driver.
20.3RThe validity of values passed to library functions shall be checked.This violation is not caused by code changes, i.e. is not a regression.
* * \section group_sd_host_Changelog Changelog * * * +* +* +* +* +* +* +* +* +* * *
VersionChangesReason for Change
1.20Documentation of the MISRA rule violation.MISRA compliance.
Added the Cy_SD_Host_DeepSleepCallback() function.Driver maintenance.
1.10The PLL and CLK disable sequence in \ref Cy_SD_Host_DisableSdClk() * is changed to disable CLK first.
@@ -333,6 +366,7 @@ #include "cy_device.h" #include "cy_device_headers.h" #include "cy_syslib.h" +#include "cy_syspm.h" #if defined(CY_IP_MXSDHC) @@ -355,7 +389,7 @@ extern "C" #define CY_SD_HOST_DRV_VERSION_MAJOR 1 /** Driver minor version */ -#define CY_SD_HOST_DRV_VERSION_MINOR 10 +#define CY_SD_HOST_DRV_VERSION_MINOR 20 /****************************************************************************** * API Constants @@ -1477,6 +1511,8 @@ cy_en_sd_host_status_t Cy_SD_Host_GetScr(SDHC_Type *base, uint32_t Cy_SD_Host_GetPresentState(SDHC_Type const *base); bool Cy_SD_Host_IsCardConnected(SDHC_Type const *base); void Cy_SD_Host_SoftwareReset(SDHC_Type *base, cy_en_sd_host_reset_t reset); +cy_en_syspm_status_t Cy_SD_Host_DeepSleepCallback(cy_stc_syspm_callback_params_t *callbackParams, + cy_en_syspm_callback_mode_t mode); /** \} group_sd_host_low_level_functions */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_seglcd.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_seglcd.h new file mode 100644 index 0000000000..6a4b27d291 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_seglcd.h @@ -0,0 +1,651 @@ +/***************************************************************************//** +* \file cy_seglcd.h +* \version 1.0 +* +* \brief +* Provides an API declaration of the Segment LCD driver. +* +******************************************************************************** +* \copyright +* Copyright 2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/** +* \addtogroup group_seglcd +* \{ +* The Segment LCD Driver provides an API to configure and operate the MXLCD hardware block. +* The MXLCD block can be flexibly configured to drive a variety of LCD glass +* at different voltage levels with multiplex ratios. +* +* Features: +* * Digital Correlation and PWM at 1/2, 1/3, 1/4 and at 1/5 bias modes are supported +* * Drives STN/TN LCD-glass with up to eight COMs (device specific) +* * 30 to 150 Hz refresh rate +* * Supports both type A (standard) and type B (low-power) waveforms +* * The display pixel state can be inverted for a negative image +* * Operation in Deep Sleep Mode from ILO/MFO +* * All-digital contrast control using "Dead Period" digital modulation +* * A set of basic standard displays and fonts +* * The customizable display and font structures. +* +* \section group_seglcd_glossary Glossary +* * LCD - Liquid Crystal Display +* * Glass - An LCD glass that may contain a few displays +* (e.g. one 7-segment display and one bar-graph display). +* * TN - A twisted nematic LCD glass. +* * STN - A super-twisted nematic LCD glass. +* * Display - A block of homogeneous symbols on an LCD glass +* intended to indicate a multi-digital number or string. +* A few displays are possible whithin a single LCD glass. +* * Pixel - A unity LCD displaying item with a binary state (on/off). +* It can be a segment of e.g. the 7-segment symbol (therefore may be called "segment"), +* a pixel of the matrix display, or a standalone arbitrarily-shaped display element. +* Each pixel has a unique set of common and segment lines in scope of the LCD glass. +* The API offers pixel identifiers - the 32-bit items of the display pixel map +* (to use in the display structure definition, see \ref cy_stc_seglcd_disp_t), +* created by the \ref CY_SEGLCD_PIXEL macro. +* * Common line (Com/COM for short) - A common wire/signal from the PSoC chip to the LCD glass. +* The API offers common line identifiers - the 32-bit items of the commons array +* (to use in \ref Cy_SegLCD_ClrFrame and \ref Cy_SegLCD_InvFrame), +* created by the \ref CY_SEGLCD_COMMON macro. +* * Segment line (Seg/SEG for short) - A segment wire/signal from the PSoC chip to the LCD glass. +* * Octet - A bunch of subsequent eight MXLCD terminals. Octets may not match GPIO ports. +* * Frame buffer - An array of registers to control the MXLCD signal generation for all the MXLCD terminals. +* +* \section group_seglcd_solution SegLCD Solution +* The Segment LCD Driver can be used either as a standalone library +* to manage the MXLCD hardware or as a part of the more complex software solution +* delivered within ModusToolbox: +* the Device Configurator SegLCD personality and the SegLCD Configurator tools. +* +* The SegLCD solution provides an easy method to configure +* an MXLCD block to drive your standard or custom LCD glass: +* \image html seglcd_solution.png +* The SegLCD solution includes: +* * The SegLCD Configurator tool, which is a display configuration wizard to create and +* configure displays and generate commons array and display structures \ref cy_stc_seglcd_disp_t. +* * The ModusToolbox Device Configurator contains a SegLCD personality, which is an MXLCD block +* configuration wizard. It helps to easily tune all the timing settings, operation modes, +* provides a flexible GPIO pin assignment capability and generates the \ref cy_stc_seglcd_config_t +* structure and the rest of accompanying definitions. +* * The SegLCD Driver API itself, which uses all the mentioned above generated code. +* +* \section group_seglcd_configuration Configuration Considerations +* To start working with an LCD, first initialize the MXLCD block, then initialize +* the frame buffer, and then enable the block: +* \snippet seglcd/snippet/SegLCD_Snpt.c snippet_Cy_SegLCD_Config +* \note If you use ModusToolbox Device Configurator, a SegLCD configuration structure +* is generated automatically into the GeneratedSource/cycfg_peripherals.h/.c files. +* All you need is just to call \ref Cy_SegLCD_Init with a pointer to the structure. +* +* \snippet seglcd/snippet/SegLCD_Snpt.c snippet_Cy_SegLCD_Init +* +* Contrast vs. Frame Rate (\ref cy_stc_seglcd_config_t.contrast vs. \ref cy_stc_seglcd_config_t.frRate)\n +* Some combinations of a frame rate and input frequency can restrict the valid contrast range +* because of the limited dividers size (for Low Speed mode - 8 bit, and for High Speed mode - 16 bit). +* For small values of contrast at small frame rates, the required divider values +* may be beyond permissible limits of the dividers size. +* For large High Speed clock frequencies, certain ratios between the contrast and frame +* rate cannot be achieved due to the limited divider size. The \ref Cy_SegLCD_Init function +* automatically restricts such incorrect combinations (returns \ref CY_SEGLCD_BAD_PARAM). +* +* Speed Mode Switching (\ref cy_stc_seglcd_config_t.speed)\n +* The High Speed and Low Speed generators mostly duplicate each other, +* except that for MXLCD_ver1, the High Speed version has larger frequency dividers to generate +* the frame and sub-frame periods. This is because the clock of the High Speed block +* typically has a frequency 30-100 times bigger than the 32 KHz clock fed to the Low Speed block. +* For MXLCD_ver2, both High Speed and Low Speed generators have similar 16-bit dividers, +* because a possibility exists to source a Low Speed generator with a Medium Frequency clock +* (see \ref group_sysclk_mf_funcs) that may be much higher than 32 KHz ILO. +* Switching between High Speed and Low Speed modes via the \ref Cy_SegLCD_Init function +* causes the dividers to reconfigure. +* Under possible restrictions related to certain ratios between contrast and frame rates +* (see Contrast vs. Frame Rate section above), switching between High Speed and the Low Speed modes +* via the \ref Cy_SegLCD_Init function may set new dividers values that don’t give the same contrast value. +* +* Driving Modes (\ref cy_stc_seglcd_config_t.drive)\n +* SegLCD supports the following operating modes: +* * Digital Correlation - preferred for low clock speeds, low common lines count and low supply voltages. +* * PWM at 1/2, 1/3, 1/4 or 1/5 Bias - preferred for high clock speeds (e.g. over 1MHz), many common lines (e.g. over 4), and high voltages (e.g. 3.3V or higher). +* More precise preferences depend on a certain set of an LCD glass, power modes, the number of terminals, desired contrast/frame rate settings, etc. +* +* Conventional Waveforms (\ref cy_stc_seglcd_config_t.wave)\n +* Conventional LCD drivers apply waveforms to COM and SEG electrodes generated by switching +* between multiple different voltages. The following terms are used to define these waveforms: +* * Duty: A driver operates in the 1/M-th duty when it drives M COM electrodes. Each COM electrode is effectively driven for the 1/M of the frame time. +* * Bias: A driver uses the 1/B-th bias when its waveforms use the voltage steps of (1/B)*VDRV. +* * Frame: A frame is the time length to address all segments. +* During a frame, the driver cycles through the commons in sequence. +* All segments receive 0V DC when measured over the length of an entire frame. +* * Type-A Waveform: The driver structures the frame into M sub-frames. COMi is addressed in sub-frame i. +* * Type-B Waveform: The driver structures the frame into 2M sub-frames. COMi is addressed in sub-frames i and M+i. +* The two sub-frames are inverse of each other. Typically, type-B waveforms are slightly more power-efficient because they contain fewer transitions. +* +* The following figures show the conventional waveforms for COM and SEG electrodes for the 1/3rd bias and 1/4th duty. Only COM0/COM1 and SEG0/SEG1 are drawn. +* Conventional Type-A Waveform Example: +* \image html seglcd_waveA.png +* Conventional Type-B Waveform Example: +* \image html seglcd_waveB.png +* The generalized waveforms for individual sub-frames for any duty and bias are illustrated in the following figure. +* Note that these use 6 different voltages at most(including VSS and VDRV). +* Conventional Waveforms - Generalized: +* \image html seglcd_waveGen.png +* The effective RMS voltage for on and off segments can be calculated using these waveforms: +* \image html seglcd_Voff.png +* \image html seglcd_Von.png +* The resulting Discrimination Ratio (D) for various bias and duty combinations is illustrated in the following table. +* The bias choice (B) for each duty (M) with the highest possible value for D is colored green: +* \image html seglcd_descr.png +* +* Digital Correlation (\ref CY_SEGLCD_CORRELATION)\n +* The principles of operation are illustrated by the example waveforms shown in the following figures. +* Digital Correlation Example – Type-A: +* \image html seglcd_DCA.png +* Digital Correlation Example – Type-B: +* \image html seglcd_DCB.png +* As illustrated, instead of generating bias voltages between the rails, this approach takes advantage of the LCD displays characteristic: +* the LCD segments' on-ness and off-ness degree is determined by the RMS voltage across the segments. In this approach, the correlation +* coefficient between any given pair of COM and SEG signals determines whether the corresponding LCD segment is On or Off. +* Thus, by doubling the base drive frequency of the COM signals in their inactive sub-frame intervals, the phase relationship of the COM and SEG +* drive signals can be varied to turn segments on and off – rather than varying the DC levels of the signals as is used in the conventional approaches. +* +* PWM Drive (\ref CY_SEGLCD_PWM)\n +* This approach duplicates the multi-voltage drive signals of the conventional method with bias B using a PWM output signal together +* with the intrinsic resistance and capacitance of the LCD display to create a simple PWM DAC. +* This is illustrated in the following figure: +* \image html seglcd_PWM.png +* To drive a low-capacitance display with an acceptable ripple and rise/fall time, using a 32-kHz PWM an additional external +* series resistance of 100 k - 1 M ohm is required. External Resistors are not required for PWM frequencies of greater than ~1 MHz. +* The exact frequency depends on the display capacitance, the internal ITO resistance of the ITO routing traces, +* and the drive impedance of the I/O pins. +* The PWM method works for any bias value (B). NOTE As B gets higher, a higher PWM step frequency is required to maintain the +* same PWM output frequency (the RC response of the LCD depends on the PWM output frequency, NOT the step frequency). +* The PWM approach may also be used to drive a 1/2-bias display. This has the advantage that PWM is only required on the COM signals, +* as SEG signals of a 1/2-bias display use only logic levels. Therefore, PWM 1/2-bias can be supported at 32 kHz using just +* four external resistors. +* The power consumption of the approach (even for 1/2 bias) is substantially higher than that of other methods. Therefore, it is recommended +* power-sensitive customers use Digital Correlation drive in Deep Sleep mode, and change to PWM mode to gain the advantage of +* better contrast/viewing angle on TN displays in Active or Sleep mode. +* +* PWM1/2 LCD drive waveform: +* \image html seglcd_PWM2.png +* PWM1/3 LCD drive waveform: +* \image html seglcd_PWM3.png +* +* Digital Contrast Control\n +* In all modes, digital contrast control is available using the duty cycle/dead time method illustrated in the following figure: +* \image html seglcd_contrast.png +* This illustration shows the principle for 1/3 bias and 1/4 duty implementation, but the general approach of reducing contrast +* by reducing the percentage of time the glass is driven can be generalized and applied to any drive method. +* In all cases, during the dead time, all COM and SEG signals are set to a logic "1" state. +* +* When the block is configured, for further work with display, a display structure is needed: +* \snippet seglcd/snippet/SegLCD_Snpt.c snippet_Cy_SegLCD_Display +* \note Using the SegLCD Configurator, display structures and the commons array are generated automatically into the +* GeneratedSource/cycfg_seglcd.h/.c files. All you need is just to include cycfg_seglcd.h into your application code. +* +* And now you can write multi-digit decimal and hexadecimal numbers and strings onto the initiated 7-segment display: +* \snippet seglcd/snippet/SegLCD_Snpt.c snippet_Cy_SegLCD_DecNum +* after which the next image on the glass appears: +* \image html seglcd_12.png +* \snippet seglcd/snippet/SegLCD_Snpt.c snippet_Cy_SegLCD_HexNum +* \image html seglcd_oooc.png +* +* Or even manage separate LCD pixels: +* \snippet seglcd/snippet/SegLCD_Snpt.h snippet_Cy_SegLCD_DefPixel +* \snippet seglcd/snippet/SegLCD_Snpt.c snippet_Cy_SegLCD_SetPixel +* after which the next image on the glass appears: +* \image html seglcd_heart.png +* \snippet seglcd/snippet/SegLCD_Snpt.c snippet_Cy_SegLCD_ClrPixel +* \snippet seglcd/snippet/SegLCD_Snpt.c snippet_Cy_SegLCD_InvPixel +* \snippet seglcd/snippet/SegLCD_Snpt.c snippet_Cy_SegLCD_ActPixel +* +* Also, you can customize basic fonts, for example: +* \snippet seglcd/snippet/SegLCD_Snpt.c snippet_Cy_SegLCD_CustomAsciiFont7seg +* And now you can write characters and strings on a standard 7-segment display: +* \snippet seglcd/snippet/SegLCD_Snpt.c snippet_Cy_SegLCD_Char +* after which the next image on the glass appears: +* \image html seglcd_char.png +* \snippet seglcd/snippet/SegLCD_Snpt.c snippet_Cy_SegLCD_String +* \image html seglcd_font.png +* +* Also, you can customize or create your own displays, for example: +* \snippet seglcd/snippet/SegLCD_Snpt.c snippet_Cy_SegLCD_Custom3x5 +* And also different fonts for them: +* \snippet seglcd/snippet/SegLCD_Snpt.c snippet_Cy_SegLCD_CustomFont3x5 +* And now use all that together: +* \snippet seglcd/snippet/SegLCD_Snpt.c snippet_Cy_SegLCD_Custom3x5_WriteNumber +* \image html seglcd_3x5.png +* +* \section group_seglcd_more_information More Information +* Refer to the technical reference manual (TRM) and the device datasheet. +* +* \section group_seglcd_MISRA MISRA-C Compliance +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
10.3RThe value of a complex expression of integer type shall only be cast to a type of the +* same signedness that is no wider than the underlying type of the expression.The value got from the bitfield physically cannot exceed the enumeration +* that describes this bitfield. So, the code is safe by design.
11.4AA cast should not be performed between a pointer to object type and +* a different pointer to object type.This is a fix for the GCC compiler warning.
14.1RThere shall be no unreachable code.This is the HOBTO parameter reading for future features support.
+* +* \section group_seglcd_changelog Changelog +* +* +* +* +* +* +* +*
VersionChangesReason for Change
1.0Initial version
+* +* \defgroup group_seglcd_macros Macros +* \defgroup group_seglcd_functions Functions +* \{ +* \defgroup group_seglcd_functions_config Block Configuration Functions +* \defgroup group_seglcd_functions_frame Frame/Pixel Management Functions +* \defgroup group_seglcd_functions_display Display/Character Management Functions +* \} +* \defgroup group_seglcd_data_structures Data Structures +* \defgroup group_seglcd_globals Global Data +* \defgroup group_seglcd_enums Enumerated Types +*/ + +#if !defined(CY_SEGLCD_H) +#define CY_SEGLCD_H + +#include "cy_syslib.h" + +#ifdef CY_IP_MXLCD + +#if defined(__cplusplus) +extern "C" { +#endif + +/** \addtogroup group_seglcd_macros +* \{ +*/ + +/** Driver major version */ +#define CY_SEGLCD_DRV_VERSION_MAJOR 1 + +/** Driver minor version */ +#define CY_SEGLCD_DRV_VERSION_MINOR 0 + +/** SegLCD driver ID */ +#define CY_SEGLCD_ID (CY_PDL_DRV_ID(0x40u)) + +/** Specifies the pixel in the display pixel map array which is not connected */ +#define CY_SEGLCD_NOT_CON (0xFFFFFFFFUL) + +/** \cond internal */ +#define CY_SEGLCD_OCTET (8UL) +#define CY_SEGLCD_COM_Pos (16U) +#define CY_SEGLCD_COM_Msk ((uint32_t) 0xFUL << CY_SEGLCD_COM_Pos) +#define CY_SEGLCD_OCT_Pos (8U) +#define CY_SEGLCD_OCT_Msk ((uint32_t) 0x7UL << CY_SEGLCD_OCT_Pos) +#define CY_SEGLCD_NBL_Pos (0U) +#define CY_SEGLCD_NBL_Msk ((uint32_t) 0x7UL << CY_SEGLCD_NBL_Pos) + +#define CY_SEGLCD_ITEM(trmNum, comLine) (_VAL2FLD(CY_SEGLCD_COM, (comLine)) | \ + _VAL2FLD(CY_SEGLCD_OCT, (trmNum) / CY_SEGLCD_OCTET) | \ + _VAL2FLD(CY_SEGLCD_NBL, (trmNum) % CY_SEGLCD_OCTET)) + +/* Extract the LCD common line number from the pixel value */ +#define CY_SEGLCD_EXTR_COM(pixel) (_FLD2VAL(CY_SEGLCD_COM, (pixel))) +/* Extract the LCD terminal octet number from the pixel value */ +#define CY_SEGLCD_EXTR_OCT(pixel) (_FLD2VAL(CY_SEGLCD_OCT, (pixel))) +/* Extract the LCD terminal nibble number from the pixel value */ +#define CY_SEGLCD_EXTR_NBL(pixel) (_FLD2VAL(CY_SEGLCD_NBL, (pixel))) +/* Extract the LCD terminal number from the pixel value */ +#define CY_SEGLCD_EXTR_TRM(pixel) ((CY_SEGLCD_EXTR_OCT(pixel) * CY_SEGLCD_OCTET) + \ + CY_SEGLCD_EXTR_NBL(pixel)) +/* Convert the locComNum from the machine range (0-14) into the natural range (2-16). */ +#define CY_SEGLCD_COM_NUM(base) (_FLD2VAL(LCD_CONTROL_COM_NUM, LCD_CONTROL(base)) + 2UL) +/** \endcond */ + + +/** +* Makes the pixel identifier from the LCD segment terminal number and the user defined common line number. +* It should be used to display pixel map (pixMap) array definitions for \ref cy_stc_seglcd_disp_t. +*/ +#define CY_SEGLCD_PIXEL(segNum, comLine) (CY_SEGLCD_ITEM(segNum, comLine)) + +/** +* Makes the common line identifier from the LCD common terminal number and the user defined common line number. +* It should be used for commons array definitions for \ref Cy_SegLCD_ClrFrame and \ref Cy_SegLCD_InvFrame. +*/ +#define CY_SEGLCD_COMMON(comNum, comLine) (CY_SEGLCD_ITEM(comNum, comLine)) + +/** Space/blank/empty symbol code for the numeric type of fonts */ +#define CY_SEGLCD_NUM_BLANK ((char_t)16) + +/** \} group_seglcd_macros */ + + +/** +* \addtogroup group_seglcd_enums +* \{ +*/ + +/** SegLCD driver error codes */ +typedef enum +{ + CY_SEGLCD_SUCCESS = 0x0UL, /**< Returned successful */ + CY_SEGLCD_BAD_PARAM = CY_SEGLCD_ID | CY_PDL_STATUS_ERROR | 0x01UL, /**< A bad parameter was passed (display/font pointer is NULL, + * position is out of display area, etc.) + */ + CY_SEGLCD_BAD_PIXEL = CY_SEGLCD_ID | CY_PDL_STATUS_ERROR | 0x02UL, /**< The specified pixel value is wrong or the pixel is + * specified as 'not connected' in the display pixMap array. + */ + CY_SEGLCD_BAD_CHAR = CY_SEGLCD_ID | CY_PDL_STATUS_ERROR | 0x04UL, /**< The specified character (or at least one of characters in the + * specified string) is not supported by the specified font. + */ + CY_SEGLCD_EXCEED = CY_SEGLCD_ID | CY_PDL_STATUS_WARNING | 0x08UL, /**< The string (length) or number (amount of dec/hex digits) + * exceeds the display limits. + */ + CY_SEGLCD_CUSTOM = CY_SEGLCD_ID | CY_PDL_STATUS_INFO | 0x10UL, /**< The display/font type is custom + * (not defined by the \ref cy_en_seglcd_disp_t). + */ +} cy_en_seglcd_status_t; + +/** SegLCD block speed mode */ +typedef enum +{ + CY_SEGLCD_SPEED_LOW = 0x0UL, /**< Low Speed mode, works in Active, Sleep and DeepSleep power modes */ + CY_SEGLCD_SPEED_HIGH = 0x1UL /**< High Speed mode, works in Active and Sleep power modes */ +} cy_en_seglcd_speed_t; + +/** SegLCD block low speed mode clock source selection */ +typedef enum +{ + CY_SEGLCD_LSCLK_LF = 0x0UL, /**< Low Frequency source, usually connected to ILO */ + CY_SEGLCD_LSCLK_MF = 0x1UL /**< Middle Frequency source, usually connected to CLK_MF, \ref group_sysclk_mf_funcs */ +} cy_en_seglcd_lsclk_t; + +/** SegLCD driving waveform type */ +typedef enum +{ + CY_SEGLCD_TYPE_A = 0x0UL, /**< Type A - Each frame addresses each COM pin only once with a balanced (DC=0) waveform. */ + CY_SEGLCD_TYPE_B = 0x1UL /**< Type B - Each frame addresses each COM pin twice in a sequence with a positive + * and negative waveform that together are balanced (DC=0). + */ +} cy_en_seglcd_wave_t; + +/** SegLCD driving mode configuration */ +typedef enum +{ + CY_SEGLCD_PWM = 0x0UL, /**< PWM mode. */ + CY_SEGLCD_CORRELATION = 0x1UL /**< Digital Correlation mode. */ +} cy_en_seglcd_drive_t; + +/** SegLCD PWM bias selection */ +typedef enum +{ + CY_SEGLCD_BIAS_HALF = 0x0UL, /**< 1/2 Bias. */ + CY_SEGLCD_BIAS_THIRD = 0x1UL, /**< 1/3 Bias. */ + CY_SEGLCD_BIAS_FOURTH = 0x2UL, /**< 1/4 Bias (not supported for \ref CY_SEGLCD_SPEED_LOW mode in MXLCD_ver1). */ + CY_SEGLCD_BIAS_FIFTH = 0x3UL, /**< 1/5 Bias (not supported for \ref CY_SEGLCD_SPEED_LOW mode in MXLCD_ver1). */ +} cy_en_seglcd_bias_t; + +/** SegLCD segment display types */ +typedef enum +{ + CY_SEGLCD_BAR = 1U, /**< Bar Graph / Dial display */ + CY_SEGLCD_7SEG = 7U, /**< Seven-segment display */ + CY_SEGLCD_14SEG = 14U, /**< Fourteen-segment display */ + CY_SEGLCD_16SEG = 16U, /**< Sixteen-segment display */ + CY_SEGLCD_5X8DM = 40U /**< Five-by-eight dot matrix display */ +} cy_en_seglcd_disp_t; + +/** \} group_seglcd_enums */ + + +/** \addtogroup group_seglcd_macros +* \{ +*/ + +/* Font map array symbol sizes in bytes. Used for the basic font definitions (\ref group_seglcd_globals) and also can be used for custom font definitions */ +#define CY_SEGLCD_14SEG_FONTMAP_SIZE (CY_SYSLIB_DIV_ROUNDUP(CY_SEGLCD_14SEG, CY_SEGLCD_OCTET)) /**< 14-segment fontMap array item size (in bytes) */ +#define CY_SEGLCD_16SEG_FONTMAP_SIZE (CY_SYSLIB_DIV_ROUNDUP(CY_SEGLCD_16SEG, CY_SEGLCD_OCTET)) /**< 16-segment fontMap array item size (in bytes) */ +#define CY_SEGLCD_5X8DM_FONTMAP_SIZE (CY_SYSLIB_DIV_ROUNDUP(CY_SEGLCD_5X8DM, CY_SEGLCD_OCTET)) /**< 5x8 dot matrix fontMap array item size (in bytes) */ + +/** \} group_seglcd_macros */ + + +/*************************************** +* Configuration Structures +***************************************/ + + +/** +* \addtogroup group_seglcd_data_structures +* \{ +*/ + +/** Configuration structure */ +typedef struct +{ + cy_en_seglcd_speed_t speed; /**< Speed mode selection, see: #cy_en_seglcd_speed_t. */ + cy_en_seglcd_wave_t wave; /**< Waveform type configuration, see: #cy_en_seglcd_wave_t. */ + cy_en_seglcd_drive_t drive; /**< Driving mode configuration, see: #cy_en_seglcd_drive_t. */ + cy_en_seglcd_bias_t bias; /**< PWM bias selection, see: #cy_en_seglcd_bias_t. */ + cy_en_seglcd_lsclk_t lsClk; /**< Low Speed Mode clock selection, see: #cy_en_seglcd_lsclk_t. + * This is effective for MXLCD_ver2, + * for MXLCD_ver1 it is ignored. + */ + uint8_t comNum; /**< The number of Common connections, the valid range is 2...16 + * however the maximum is dependent on PSoC device family - + * there could be limitation to 4 or 8 commons, see the device TRM. + */ + uint8_t frRate; /**< The LCD frame rate, the valid range is 30...150 */ + uint8_t contrast; /**< The LCD contrast, the valid range is 0...100 */ + uint32_t clkFreq; /**< The LCD clock frequency (ignored for \ref CY_SEGLCD_SPEED_LOW mode), + * the valid range is 10000...100000000 (Hz) + */ +} cy_stc_seglcd_config_t; + +/** Font structure */ +typedef struct +{ + char_t first; /**< The first character code in the fontMap array */ + char_t last; /**< The last character code in the fontMap array */ + bool ascii; /**< Specifies whether the font map is indexed accordingly to ASCII character codes: + * true - the font is ASCII-coded alphanumeric (e.g. a basic set "space" (ASCII 0x20) - "tilde"(ASCII 0x7E)); + * false - the font is e.g. pure numeric (0x0...0xF only), or any other custom character set. + */ + uint8_t const * fontMap; /**< The pointer to the font segment/pixel map array. */ +} cy_stc_seglcd_font_t; + +/** Display structure */ +typedef struct +{ + uint16_t type; /**< The display type, one of \ref cy_en_seglcd_disp_t or custom. */ + uint16_t symNum; /**< The number of symbols (digits, characters). */ + bool invert; /**< Specifies whether the display is inverted or not. */ + uint32_t const * pixMap; /**< The pointer to the display pixel map array: + * The array dimension is: uint32_t pixMap[symNum][type]. + * Each array item should be made using the \ref CY_SEGLCD_PIXEL macro. + */ + cy_stc_seglcd_font_t const * font; /**< The pointer to the font structure suitable for this display. + * Note that for the \ref CY_SEGLCD_BAR displays font is not used, so can be NULL. + */ +} cy_stc_seglcd_disp_t; + +/** \} group_seglcd_data_structures */ + + +/** \addtogroup group_seglcd_globals +* \{ +*/ + +extern const cy_stc_seglcd_font_t cy_segLCD_7SegFont; /**< Basic 7-segment font */ +extern const cy_stc_seglcd_font_t cy_segLCD_14SegFont; /**< Basic 14-segment font */ +extern const cy_stc_seglcd_font_t cy_segLCD_16SegFont; /**< Basic 16-segment font */ +extern const cy_stc_seglcd_font_t cy_segLCD_5x8DmFont; /**< Basic 5x8 dot matrix font */ + +/** \} group_seglcd_globals */ + + +/*************************************** +* Function Prototypes +***************************************/ + + +/** +* \addtogroup group_seglcd_functions +* \{ +*/ + + +/** +* \addtogroup group_seglcd_functions_config +* \{ +*/ +cy_en_seglcd_status_t Cy_SegLCD_Init (LCD_Type * base, cy_stc_seglcd_config_t const * config); +cy_en_seglcd_status_t Cy_SegLCD_Contrast(LCD_Type * base, uint32_t contrast, cy_stc_seglcd_config_t * config); + void Cy_SegLCD_Deinit (LCD_Type * base); + void Cy_SegLCD_Enable (LCD_Type * base); + void Cy_SegLCD_Disable (LCD_Type * base); +/** \} group_seglcd_functions_config */ + + +/** +* \addtogroup group_seglcd_functions_display +* \{ +*/ +cy_en_seglcd_status_t Cy_SegLCD_WriteChar (LCD_Type * base, char_t character, uint32_t position, cy_stc_seglcd_disp_t const * display); +cy_en_seglcd_status_t Cy_SegLCD_WriteString(LCD_Type * base, char_t const * string, uint32_t position, cy_stc_seglcd_disp_t const * display); +cy_en_seglcd_status_t Cy_SegLCD_WriteNumber(LCD_Type * base, uint32_t value, uint32_t position, cy_stc_seglcd_disp_t const * display, bool zeroes, bool hex); +cy_en_seglcd_status_t Cy_SegLCD_BarGraph (LCD_Type * base, uint32_t value, uint32_t position, cy_stc_seglcd_disp_t const * display); +/** \} group_seglcd_functions_display */ + + +/** +* \addtogroup group_seglcd_functions_frame +* \{ +*/ + cy_en_seglcd_status_t Cy_SegLCD_ClrFrame (LCD_Type * base, uint32_t const * commons); + cy_en_seglcd_status_t Cy_SegLCD_InvFrame (LCD_Type * base, uint32_t const * commons); + cy_en_seglcd_status_t Cy_SegLCD_WritePixel(LCD_Type * base, uint32_t pixel, bool value); + bool Cy_SegLCD_ReadPixel (LCD_Type * base, uint32_t pixel); +__STATIC_INLINE cy_en_seglcd_status_t Cy_SegLCD_SetPixel (LCD_Type * base, uint32_t pixel); +__STATIC_INLINE cy_en_seglcd_status_t Cy_SegLCD_ClrPixel (LCD_Type * base, uint32_t pixel); +__STATIC_INLINE cy_en_seglcd_status_t Cy_SegLCD_InvPixel (LCD_Type * base, uint32_t pixel); + + +/******************************************************************************* +* Function Name: Cy_SegLCD_SetPixel +****************************************************************************//** +* +* Sets (turns on) the specified pixel. +* +* \param base The base pointer to the LCD instance registers. +* \param pixel The predefined packed number that points to the pixel location +* in the frame buffer. +* \return \ref cy_en_seglcd_status_t. +* +* \funcusage +* \snippet seglcd/snippet/SegLCD_Snpt.h snippet_Cy_SegLCD_DefPixel +* \snippet seglcd/snippet/SegLCD_Snpt.c snippet_Cy_SegLCD_SetPixel +* +*******************************************************************************/ +__STATIC_INLINE cy_en_seglcd_status_t Cy_SegLCD_SetPixel(LCD_Type * base, uint32_t pixel) +{ + return (Cy_SegLCD_WritePixel(base, pixel, true)); +} + + +/******************************************************************************* +* Function Name: Cy_SegLCD_ClrPixel +****************************************************************************//** +* +* Clears (turns off) the specified pixel. +* +* \param base The base pointer to the LCD instance registers. +* \param pixel The predefined packed number that points to the pixel location +* in the frame buffer. +* \return \ref cy_en_seglcd_status_t. +* +* \funcusage +* \snippet seglcd/snippet/SegLCD_Snpt.h snippet_Cy_SegLCD_DefPixel +* \snippet seglcd/snippet/SegLCD_Snpt.c snippet_Cy_SegLCD_ClrPixel +* +*******************************************************************************/ +__STATIC_INLINE cy_en_seglcd_status_t Cy_SegLCD_ClrPixel(LCD_Type * base, uint32_t pixel) +{ + return (Cy_SegLCD_WritePixel(base, pixel, false)); +} + + +/******************************************************************************* +* Function Name: Cy_SegLCD_InvPixel +****************************************************************************//** +* +* Inverts the state of the specified pixel. +* +* \param base The base pointer to the LCD instance registers. +* \param pixel The predefined packed number that points to the pixel location +* in the frame buffer. +* \return \ref cy_en_seglcd_status_t. +* +* \funcusage +* \snippet seglcd/snippet/SegLCD_Snpt.h snippet_Cy_SegLCD_DefPixel +* \snippet seglcd/snippet/SegLCD_Snpt.c snippet_Cy_SegLCD_InvPixel +* +*******************************************************************************/ +__STATIC_INLINE cy_en_seglcd_status_t Cy_SegLCD_InvPixel(LCD_Type * base, uint32_t pixel) +{ + return (Cy_SegLCD_WritePixel(base, pixel, !Cy_SegLCD_ReadPixel(base, pixel))); +} + +/** \} group_seglcd_functions_frame */ + +/** \} group_seglcd_functions */ + +#if defined(__cplusplus) +} +#endif + +#endif /* CY_IP_MXLCD */ + +#endif /* CY_SEGLCD_H */ + +/** \} group_seglcd */ + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_smartio.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_smartio.h index 1b0b180325..1d9d7a52ba 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_smartio.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_smartio.h @@ -602,7 +602,7 @@ cy_en_smartio_status_t Cy_SmartIO_SetDataReg(SMARTIO_PRT_Type* base, uint8_t dat * Bypass/Route state of 8 io<->chip channels (bits [7:0]): 1=bypass, 0=routed. * * \funcusage -* \snippet smartio/1.0/snippet/main.c snippet_Cy_SmartIO_GetChBypass +* \snippet smartio/snippet/main.c snippet_Cy_SmartIO_GetChBypass * *******************************************************************************/ __STATIC_INLINE uint8_t Cy_SmartIO_GetChBypass(SMARTIO_PRT_Type* base) @@ -624,7 +624,7 @@ __STATIC_INLINE uint8_t Cy_SmartIO_GetChBypass(SMARTIO_PRT_Type* base) * Clock source * * \funcusage -* \snippet smartio/1.0/snippet/main.c snippet_Cy_SmartIO_GetClock +* \snippet smartio/snippet/main.c snippet_Cy_SmartIO_GetClock * *******************************************************************************/ __STATIC_INLINE cy_en_smartio_clksrc_t Cy_SmartIO_GetClock(SMARTIO_PRT_Type* base) @@ -658,7 +658,7 @@ __STATIC_INLINE cy_en_smartio_clksrc_t Cy_SmartIO_GetClock(SMARTIO_PRT_Type* bas * Sync mode of 8 I/O terminals (bits [7:0]): 1=sync, 0=no sync. * * \funcusage -* \snippet smartio/1.0/snippet/main.c snippet_Cy_SmartIO_GetIoSync +* \snippet smartio/snippet/main.c snippet_Cy_SmartIO_GetIoSync * *******************************************************************************/ __STATIC_INLINE uint8_t Cy_SmartIO_GetIoSync(SMARTIO_PRT_Type* base) @@ -692,7 +692,7 @@ __STATIC_INLINE uint8_t Cy_SmartIO_GetIoSync(SMARTIO_PRT_Type* base) * Sync mode of 8 chip-side terminals (bits [7:0]): 1=sync, 0=no sync. * * \funcusage -* \snippet smartio/1.0/snippet/main.c snippet_Cy_SmartIO_GetChipSync +* \snippet smartio/snippet/main.c snippet_Cy_SmartIO_GetChipSync * *******************************************************************************/ __STATIC_INLINE uint8_t Cy_SmartIO_GetChipSync(SMARTIO_PRT_Type* base) @@ -723,7 +723,7 @@ __STATIC_INLINE uint8_t Cy_SmartIO_GetChipSync(SMARTIO_PRT_Type* base) * LUT opcode * * \funcusage -* \snippet smartio/1.0/snippet/main.c snippet_Cy_SmartIO_GetLutOpcode +* \snippet smartio/snippet/main.c snippet_Cy_SmartIO_GetLutOpcode * *******************************************************************************/ __STATIC_INLINE cy_en_smartio_lutopc_t Cy_SmartIO_GetLutOpcode(SMARTIO_PRT_Type* base, cy_en_smartio_lutnum_t lutNum) @@ -760,7 +760,7 @@ __STATIC_INLINE cy_en_smartio_lutopc_t Cy_SmartIO_GetLutOpcode(SMARTIO_PRT_Type* * Bitfield [7:0] mapping of the 3:1 LUT * * \funcusage -* \snippet smartio/1.0/snippet/main.c snippet_Cy_SmartIO_GetLutMap +* \snippet smartio/snippet/main.c snippet_Cy_SmartIO_GetLutMap * *******************************************************************************/ __STATIC_INLINE uint8_t Cy_SmartIO_GetLutMap(SMARTIO_PRT_Type* base, cy_en_smartio_lutnum_t lutNum) @@ -791,7 +791,7 @@ __STATIC_INLINE uint8_t Cy_SmartIO_GetLutMap(SMARTIO_PRT_Type* base, cy_en_smart * Data unit input trigger source * * \funcusage -* \snippet smartio/1.0/snippet/main.c snippet_Cy_SmartIO_GetDuData +* \snippet smartio/snippet/main.c snippet_Cy_SmartIO_GetDuData * *******************************************************************************/ __STATIC_INLINE cy_en_smartio_dudata_t Cy_SmartIO_GetDuData(SMARTIO_PRT_Type* base, cy_en_smartio_datanum_t dataNum) @@ -815,7 +815,7 @@ __STATIC_INLINE cy_en_smartio_dudata_t Cy_SmartIO_GetDuData(SMARTIO_PRT_Type* ba * Data unit opcode * * \funcusage -* \snippet smartio/1.0/snippet/main.c snippet_Cy_SmartIO_GetDuOpc +* \snippet smartio/snippet/main.c snippet_Cy_SmartIO_GetDuOpc * *******************************************************************************/ __STATIC_INLINE cy_en_smartio_duopc_t Cy_SmartIO_GetDuOpc(SMARTIO_PRT_Type* base) @@ -837,7 +837,7 @@ __STATIC_INLINE cy_en_smartio_duopc_t Cy_SmartIO_GetDuOpc(SMARTIO_PRT_Type* base * Data unit operand bit-width * * \funcusage -* \snippet smartio/1.0/snippet/main.c snippet_Cy_SmartIO_GetDuSize +* \snippet smartio/snippet/main.c snippet_Cy_SmartIO_GetDuSize * *******************************************************************************/ __STATIC_INLINE cy_en_smartio_dusize_t Cy_SmartIO_GetDuSize(SMARTIO_PRT_Type* base) @@ -859,7 +859,7 @@ __STATIC_INLINE cy_en_smartio_dusize_t Cy_SmartIO_GetDuSize(SMARTIO_PRT_Type* ba * DATA register value * * \funcusage -* \snippet smartio/1.0/snippet/main.c snippet_Cy_SmartIO_GetDataReg +* \snippet smartio/snippet/main.c snippet_Cy_SmartIO_GetDataReg * *******************************************************************************/ __STATIC_INLINE uint8_t Cy_SmartIO_GetDataReg(SMARTIO_PRT_Type* base) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_smif.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_smif.h index 70f9cb0765..917f570898 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_smif.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_smif.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_smif.h -* \version 1.20.1 +* \version 1.30 * * Provides an API declaration of the Cypress SMIF driver. * @@ -33,7 +33,7 @@ * * SMIF: Serial Memory Interface: This IP block implements an SPI-based * communication interface for interfacing external memory devices to PSoC. The SMIF -* supports Octal-SPI, Dual Quad-SPI, Quad-SPI, DSPI, and SPI. +* supports Octal-SPI, Dual Quad-SPI, Quad-SPI, Dual-SPI, and SPI. * * Features * - Standard SPI Master interface @@ -43,16 +43,15 @@ * memory devices * - eXecute-In-Place (XIP) operation mode for both read and write accesses * with 4KB XIP read cache and on-the-fly encryption and decryption -* - Supports external serial memory initialization via Serial Flash -* Discoverable Parameters (SFDP) standard -* - Support for SPI clock frequencies up to 80 MHz -* +* - Supports external serial memory initialization via +* +* Serial Flash Discoverable Parameters (SFDP) standard * * The primary usage model for the SMIF is that of an external memory interface. * The SMIF is capable of interfacing with different types of memory, up to four * types. * -* \b SMIF driver is divided in next layers +* \b SMIF driver is divided into three layers * - cy_smif.h API * - cy_smif_memslot.h API * - SMIF configuration structures @@ -63,9 +62,9 @@ * * The memory slot API has functions to implement the basic memory operations such as * program, read, erase etc. These functions are implemented using the memory -* parameters in the memory device configuration data structure. The memory-slot -* initialization API initializes all the memory slots based on the settings in the -* array. +* parameters in the memory device configuration data structure. The +* Cy_SMIF_Memslot_Init() API initializes all the memory slots based on the settings +* in the array. * * \image html smif_1_0_p01_layers.png * @@ -212,6 +211,34 @@ * * * +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* * * * @@ -281,6 +308,14 @@ * * \image html smif_1_0_p03_rw_cmd.png * +* The sequence of the PDL functions required in a read or write transaction is: +* Cy_SMIF_TransmitCommand() -> +* Cy_SMIF_SendDummyCycles() -> +* Cy_SMIF_ReceiveData()/Cy_SMIF_TransmitData() -> +* Cy_SMIF_BusyCheck(). +* The address is sent as part of the Cy_SMIF_TransmitCommand() function. +* No separate function call is required. +* * \} * \defgroup group_smif_mem_slot_functions Memory Slot Functions * \defgroup group_smif_functions_syspm_callback Low Power Callback @@ -328,14 +363,14 @@ extern "C" { #define CY_SMIF_DRV_VERSION_MAJOR 1 /** The driver minor version */ -#define CY_SMIF_DRV_VERSION_MINOR 20 +#define CY_SMIF_DRV_VERSION_MINOR 30 /** One microsecond timeout for Cy_SMIF_TimeoutRun() */ -#define CY_SMIF_WAIT_1_UNIT (1U) +#define CY_SMIF_WAIT_1_UNIT (1U) /** The SMIF driver ID, reported as part of an unsuccessful API return status * \ref cy_en_smif_status_t */ -#define CY_SMIF_ID CY_PDL_DRV_ID(0x2CU) +#define CY_SMIF_ID CY_PDL_DRV_ID(0x2CU) /** @@ -350,7 +385,7 @@ extern "C" { /** Enable TX_DATA_FIFO_OVERFLOW interrupt see TRM for details */ #define CY_SMIF_TX_DATA_FIFO_OVERFLOW (SMIF_INTR_TX_DATA_FIFO_OVERFLOW_Msk) /** Enable TX_CMD_FIFO_OVERFLOW interrupt see TRM for details */ -#define CY_SMIF_TX_COMMAND_FIFO_OVERFLOW (SMIF_INTR_TX_CMD_FIFO_OVERFLOW_Msk) +#define CY_SMIF_TX_COMMAND_FIFO_OVERFLOW (SMIF_INTR_TX_CMD_FIFO_OVERFLOW_Msk) /** Enable TR_TX_REQ interrupt see TRM for details */ #define CY_SMIF_TX_DATA_FIFO_LEVEL_TRIGGER (SMIF_INTR_TR_TX_REQ_Msk) /** Enable TR_RX_REQ interrupt see TRM for details */ @@ -360,48 +395,48 @@ extern "C" { /** \cond INTERNAL */ -#define CY_SMIF_CMD_FIFO_TX_MODE (0UL) -#define CY_SMIF_CMD_FIFO_TX_COUNT_MODE (1UL) -#define CY_SMIF_CMD_FIFO_RX_COUNT_MODE (2UL) -#define CY_SMIF_CMD_FIFO_DUMMY_COUNT_MODE (3UL) +#define CY_SMIF_CMD_FIFO_TX_MODE (0UL) +#define CY_SMIF_CMD_FIFO_TX_COUNT_MODE (1UL) +#define CY_SMIF_CMD_FIFO_RX_COUNT_MODE (2UL) +#define CY_SMIF_CMD_FIFO_DUMMY_COUNT_MODE (3UL) -#define CY_SMIF_TX_CMD_FIFO_STATUS_RANGE (4U) -#define CY_SMIF_TX_DATA_FIFO_STATUS_RANGE (8U) -#define CY_SMIF_RX_DATA_FIFO_STATUS_RANGE (8U) +#define CY_SMIF_TX_CMD_FIFO_STATUS_RANGE (4U) +#define CY_SMIF_TX_DATA_FIFO_STATUS_RANGE (8U) +#define CY_SMIF_RX_DATA_FIFO_STATUS_RANGE (8U) -#define CY_SMIF_ONE_BYTE (1U) -#define CY_SMIF_TWO_BYTES (2U) -#define CY_SMIF_THREE_BYTES (3U) -#define CY_SMIF_FOUR_BYTES (4U) -#define CY_SMIF_FIVE_BYTES (5U) -#define CY_SMIF_SIX_BYTES (6U) -#define CY_SMIF_SEVEN_BYTES (7U) -#define CY_SMIF_EIGHT_BYTES (8U) +#define CY_SMIF_ONE_BYTE (1U) +#define CY_SMIF_TWO_BYTES (2U) +#define CY_SMIF_THREE_BYTES (3U) +#define CY_SMIF_FOUR_BYTES (4U) +#define CY_SMIF_FIVE_BYTES (5U) +#define CY_SMIF_SIX_BYTES (6U) +#define CY_SMIF_SEVEN_BYTES (7U) +#define CY_SMIF_EIGHT_BYTES (8U) -#define CY_SMIF_CRYPTO_FIRST_WORD (0U) -#define CY_SMIF_CRYPTO_SECOND_WORD (4U) -#define CY_SMIF_CRYPTO_THIRD_WORD (8U) -#define CY_SMIF_CRYPTO_FOURTH_WORD (12U) +#define CY_SMIF_CRYPTO_FIRST_WORD (0U) +#define CY_SMIF_CRYPTO_SECOND_WORD (4U) +#define CY_SMIF_CRYPTO_THIRD_WORD (8U) +#define CY_SMIF_CRYPTO_FOURTH_WORD (12U) -#define CY_SMIF_CRYPTO_START (1UL) -#define CY_SMIF_CRYPTO_COMPLETED (0UL) -#define CY_SMIF_CRYPTO_ADDR_MASK (0xFFFFFFF0UL) -#define CY_SMIF_AES128_BYTES (16U) +#define CY_SMIF_CRYPTO_START (1UL) +#define CY_SMIF_CRYPTO_COMPLETED (0UL) +#define CY_SMIF_CRYPTO_ADDR_MASK (0xFFFFFFF0UL) +#define CY_SMIF_AES128_BYTES (16U) -#define CY_SMIF_CTL_REG_DEFAULT (0x00000300U) /* 3 - [13:12] CLOCK_IF_RX_SEL */ +#define CY_SMIF_CTL_REG_DEFAULT (0x00000300U) /* 3 - [13:12] CLOCK_IF_RX_SEL */ -#define CY_SMIF_SFDP_FAIL (0x08U) -#define CY_SMIF_SFDP_FAIL_SS0_POS (0x00U) -#define CY_SMIF_SFDP_FAIL_SS1_POS (0x01U) -#define CY_SMIF_SFDP_FAIL_SS2_POS (0x02U) -#define CY_SMIF_SFDP_FAIL_SS3_POS (0x03U) +#define CY_SMIF_SFDP_FAIL (0x08U) +#define CY_SMIF_SFDP_FAIL_SS0_POS (0x00U) +#define CY_SMIF_SFDP_FAIL_SS1_POS (0x01U) +#define CY_SMIF_SFDP_FAIL_SS2_POS (0x02U) +#define CY_SMIF_SFDP_FAIL_SS3_POS (0x03U) -#define CY_SMIF_MAX_DESELECT_DELAY (7U) -#define CY_SMIF_MAX_TX_TR_LEVEL (8U) -#define CY_SMIF_MAX_RX_TR_LEVEL (8U) +#define CY_SMIF_MAX_DESELECT_DELAY (7U) +#define CY_SMIF_MAX_TX_TR_LEVEL (8U) +#define CY_SMIF_MAX_RX_TR_LEVEL (8U) -#define CY_SMIF_MODE_VALID(mode) ((CY_SMIF_NORMAL == (cy_en_smif_mode_t)(mode)) || \ - (CY_SMIF_MEMORY == (cy_en_smif_mode_t)(mode))) +#define CY_SMIF_MODE_VALID(mode) ((CY_SMIF_NORMAL == (cy_en_smif_mode_t)(mode)) || \ + (CY_SMIF_MEMORY == (cy_en_smif_mode_t)(mode))) #define CY_SMIF_BLOCK_EVENT_VALID(event) ((CY_SMIF_BUS_ERROR == (cy_en_smif_error_event_t)(event)) || \ (CY_SMIF_WAIT_STATES == (cy_en_smif_error_event_t)(event))) #define CY_SMIF_CLOCK_SEL_VALID(clkSel) ((CY_SMIF_SEL_INTERNAL_CLK == (cy_en_smif_clk_select_t)(clkSel)) || \ @@ -409,24 +444,27 @@ extern "C" { (CY_SMIF_SEL_FEEDBACK_CLK == (cy_en_smif_clk_select_t)(clkSel)) || \ (CY_SMIF_SEL_INV_FEEDBACK_CLK == (cy_en_smif_clk_select_t)(clkSel))) -#define CY_SMIF_DESELECT_DELAY_VALID(delay) ((delay) <= CY_SMIF_MAX_DESELECT_DELAY) -#define CY_SMIF_SLAVE_SEL_VALID(ss) ((CY_SMIF_SLAVE_SELECT_0 == (ss)) || \ - (CY_SMIF_SLAVE_SELECT_1 == (ss)) || \ - (CY_SMIF_SLAVE_SELECT_2 == (ss)) || \ - (CY_SMIF_SLAVE_SELECT_3 == (ss))) -#define CY_SMIF_DATA_SEL_VALID(ss) ((CY_SMIF_DATA_SEL0 == (ss)) || \ - (CY_SMIF_DATA_SEL1 == (ss)) || \ - (CY_SMIF_DATA_SEL2 == (ss)) || \ - (CY_SMIF_DATA_SEL3 == (ss))) -#define CY_SMIF_TXFR_WIDTH_VALID(width) ((CY_SMIF_WIDTH_SINGLE == (width)) || \ - (CY_SMIF_WIDTH_DUAL == (width)) || \ - (CY_SMIF_WIDTH_QUAD == (width)) || \ - (CY_SMIF_WIDTH_OCTAL == (width)) || \ - (CY_SMIF_WIDTH_NA == (width))) -#define CY_SMIF_CMD_PARAM_VALID(param, paramSize) (((paramSize) > 0U)? (NULL != (param)) : (true)) +#define CY_SMIF_DESELECT_DELAY_VALID(delay) ((delay) <= CY_SMIF_MAX_DESELECT_DELAY) +#define CY_SMIF_SLAVE_SEL_VALID(ss) ((CY_SMIF_SLAVE_SELECT_0 == (ss)) || \ + (CY_SMIF_SLAVE_SELECT_1 == (ss)) || \ + (CY_SMIF_SLAVE_SELECT_2 == (ss)) || \ + (CY_SMIF_SLAVE_SELECT_3 == (ss))) +#define CY_SMIF_DATA_SEL_VALID(ss) ((CY_SMIF_DATA_SEL0 == (ss)) || \ + (CY_SMIF_DATA_SEL1 == (ss)) || \ + (CY_SMIF_DATA_SEL2 == (ss)) || \ + (CY_SMIF_DATA_SEL3 == (ss))) +#define CY_SMIF_TXFR_WIDTH_VALID(width) ((CY_SMIF_WIDTH_SINGLE == (width)) || \ + (CY_SMIF_WIDTH_DUAL == (width)) || \ + (CY_SMIF_WIDTH_QUAD == (width)) || \ + (CY_SMIF_WIDTH_OCTAL == (width)) || \ + (CY_SMIF_WIDTH_NA == (width))) +#define CY_SMIF_CMD_PARAM_VALID(param, paramSize) (((paramSize) > 0U)? (NULL != (param)) : (true)) -#define CY_SMIF_WIDTH_NA_VALID(paramWidth, paramSize) (((paramSize) > 0U)? \ - (CY_SMIF_WIDTH_NA != (paramWidth)) : (true)) +#define CY_SMIF_WIDTH_NA_VALID(paramWidth, paramSize) (((paramSize) > 0U)? \ + (CY_SMIF_WIDTH_NA != (paramWidth)) : (true)) + +#define CY_SMIF_BUFFER_SIZE_MAX (65536UL) +#define CY_SMIF_BUF_SIZE_VALID(size) (((CY_SMIF_BUFFER_SIZE_MAX) >= (size)) && ((0UL) < (size))) /*************************************** * Command FIFO Register @@ -461,7 +499,7 @@ extern "C" { #define CY_SMIF_CMD_FIFO_WR_DUMMY_Msk (0x0000FFFFUL) /* DATA[15:0] Dummy count */ #define CY_SMIF_CMD_FIFO_WR_TX_COUNT_Msk (0x0000FFFFUL) /* DATA[15:0] TX count */ #define CY_SMIF_CMD_FIFO_WR_TX_COUNT_Pos (0UL) /* [0] TX count */ -#define CY_SMIF_CMD_FIFO_WR_RX_COUNT_Msk (0x0003FFFFUL) /* DATA[17:0] RX count */ +#define CY_SMIF_CMD_FIFO_WR_RX_COUNT_Msk (0x0000FFFFUL) /* DATA[15:0] RX count */ #define CY_SMIF_CMD_FIFO_WR_RX_COUNT_Pos (0UL) /* [0] RX count */ /** \endcond*/ @@ -1341,8 +1379,8 @@ __STATIC_INLINE void Cy_SMIF_PopRxFifo(SMIF_Type *baseaddr, cy_stc_smif_context_ * The byte array to pack. * * \param fourBytes -* - The True pack is for a 32-bit value. -* - The False pack is for a 16-bit value. +* - True: The pack is for a 32-bit value. +* - False: The pack is for a 16-bit value. * * \return * The 4-byte value packed from the byte array. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_smif_memslot.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_smif_memslot.h index 9da70b9a31..220e26ef62 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_smif_memslot.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_smif_memslot.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_smif_memslot.h -* \version 1.20.1 +* \version 1.30 * * \brief * This file provides the constants and parameter values for the memory-level @@ -35,6 +35,8 @@ #include "cy_device_headers.h" #include "cy_smif.h" +#ifdef CY_IP_MXSMIF + #if defined(__cplusplus) extern "C" { #endif @@ -104,7 +106,9 @@ extern "C" { * SFDP constants ****************************************/ #define CY_SMIF_SFDP_ADDRESS_LENGTH (0x03U) /**< The length of the SFDP address */ -#define CY_SMIF_SFDP_LENGTH (0xFFU) /**< The length of the SFDP */ +#define CY_SMIF_SFDP_PARAM_HEADER_LENGTH (0x8U) /**< The length of the Parameter header */ +#define CY_SMIF_SFDP_PARAMETER_TABLE_LENGTH (0x64U) /**< The length of the Parameter table */ +#define CY_SMIF_SFDP_LENGTH (CY_SMIF_SFDP_PARAMETER_TABLE_LENGTH) /**< The length of the SFDP */ #define CY_SMIF_SFDP_SING_BYTE_00 (0x00U) /**< The SFDP Signature byte 0x00. Should be "S" */ #define CY_SMIF_SFDP_SING_BYTE_01 (0x01U) /**< The SFDP Signature byte 0x01. Should be "F" */ #define CY_SMIF_SFDP_SING_BYTE_02 (0x02U) /**< The SFDP Signature byte 0x02. Should be "D" */ @@ -167,6 +171,10 @@ extern "C" { #define CY_SMIF_SFDP_QE_BIT_7_OF_SR_2 (0x80UL) /**< The QE is bit 7 of the status register 2 */ #define CY_SMIF_SFDP_BFPT_BYTE_02 (0x02U) /**< The byte 0x02 of the JEDEC Basic Flash Parameter Table */ #define CY_SMIF_SFDP_BFPT_BYTE_04 (0x04U) /**< The byte 0x04 of the JEDEC Basic Flash Parameter Table */ +#define CY_SMIF_SFDP_BFPT_BYTE_05 (0x05U) /**< The byte 0x05 of the JEDEC Basic Flash Parameter Table */ +#define CY_SMIF_SFDP_BFPT_BYTE_06 (0x06U) /**< The byte 0x06 of the JEDEC Basic Flash Parameter Table: + * number of Parameter Headers (zero based, 05h = 6 parameters) + */ #define CY_SMIF_SFDP_BFPT_BYTE_08 (0x08U) /**< The byte 0x08 of the JEDEC Basic Flash Parameter Table */ #define CY_SMIF_SFDP_BFPT_BYTE_09 (0x09U) /**< The byte 0x09 of the JEDEC Basic Flash Parameter Table */ #define CY_SMIF_SFDP_BFPT_BYTE_0A (0x0AU) /**< The byte 0x0A of the JEDEC Basic Flash Parameter Table */ @@ -177,6 +185,7 @@ extern "C" { #define CY_SMIF_SFDP_BFPT_BYTE_0F (0x0FU) /**< The byte 0x0F of the JEDEC Basic Flash Parameter Table */ #define CY_SMIF_SFDP_BFPT_BYTE_1C (0x1CU) /**< The byte 0x1C of the JEDEC Basic Flash Parameter Table */ #define CY_SMIF_SFDP_BFPT_BYTE_1D (0x1DU) /**< The byte 0x1D of the JEDEC Basic Flash Parameter Table */ +#define CY_SMIF_SFDP_BFPT_BYTE_23 (0x23U) /**< The byte 0x23 of the JEDEC Basic Flash Parameter Table */ #define CY_SMIF_SFDP_BFPT_BYTE_28 (0x28U) /**< The byte 0x28 of the JEDEC Basic Flash Parameter Table */ #define CY_SMIF_SFDP_BFPT_BYTE_3A (0x3AU) /**< The byte 0x3A of the JEDEC Basic Flash Parameter Table */ #define CY_SMIF_SFDP_BFPT_ERASE_BYTE (36U) /**< The byte 36 of the JEDEC Basic Flash Parameter Table */ @@ -248,15 +257,8 @@ extern "C" { /** \cond INTERNAL */ -#define CY_SMIF_BYTES_IN_WORD (4U) -#define CY_SMIF_BITS_IN_BYTE (8U) -#define CY_SMIF_BITS_IN_BYTE_ABOVE_4GB (3U) /** density of memory above 4GBit stored as poser of 2 */ -#define CY_SMIF_MEM_ADDR_VALID(addr, size) (0U == ((addr)%(size))) /* This address must be a multiple of the SMIF XIP memory size */ -#define CY_SMIF_MEM_MAPPED_SIZE_VALID(size) (((size) >= 0x10000U) && (0U == ((size)&((size)-1U))) ) /* must be a power of 2 and greater or equal than 64 KB */ -#define CY_SMIF_MEM_ADDR_SIZE_VALID(addrSize) ((0U < (addrSize)) && ((addrSize) <= 4U)) - /** \endcond*/ /** \} group_smif_macros_sfdp */ @@ -291,7 +293,12 @@ typedef struct { uint32_t numOfAddrBytes; /**< This specifies the number of address bytes used by the * memory slave device, valid values 1-4 */ - uint32_t memSize; /**< The size of the memory */ + uint32_t memSize; /**< The memory size: For densities of 2 gigabits or less - the size in bytes; + * For densities 4 gigabits and above - bit-31 is set to 1b to define that + * this memory is 4 gigabits and above; and other 30:0 bits define N where + * the density is computed as 2^N bytes. + * For example, 0x80000021 corresponds to 2^30 = 1 gigabyte. + */ cy_stc_smif_mem_cmd_t* readCmd; /**< This specifies the Read command */ cy_stc_smif_mem_cmd_t* writeEnCmd; /**< This specifies the Write Enable command */ cy_stc_smif_mem_cmd_t* writeDisCmd; /**< This specifies the Write Disable command */ @@ -428,6 +435,8 @@ cy_en_smif_status_t Cy_SMIF_Memslot_SfdpDetect(SMIF_Type *base, } #endif +#endif /* CY_IP_MXSMIF */ + #endif /* (CY_SMIF_MEMORYSLOT_H) */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sysclk.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sysclk.h index 3c71b78aab..fb6bd4abb7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sysclk.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sysclk.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_sysclk.h -* \version 1.30 +* \version 1.40 * * Provides an API declaration of the sysclk driver. * @@ -104,6 +104,31 @@ *
VersionChangesReason for Change
1.30The CY_SMIF_CMD_FIFO_WR_RX_COUNT_Msk value is changed to 0x0000FFFFUL.Driver maintenance.
Added the check of the size parameter in the Cy_SMIF_TransmitData() function.
Added conditional check for presence of the SMIF hardware IP.
Fixed the wrong erase command in the SFDP protocol for devices with Erase Type 3.
Updated the General Description section with minor changes. +* Updated the ordering of the parameters descriptions for some functions. +* Added the text saying that the Cy_SMIF_Memslot_Init() function is applicable +* to use the external memory as memory-mapped to PSoC (XIP mode). +* Added the snippet for the Cy_SMIF_Encrypt() function to show how to use this function. +* Added below the picture in the Low-Level Functions section the sequence of PDL +* functions required in a Read or Write transaction. +* Added the text below the picture about the address. +* Updated DUMMY COUNT in this picture. +* Added checking of the size parameter in the Cy_SMIF_TransmitData() function. +* Documentation improvement.
1.20.1Added upper limit to size parameter in several functions.Documentation improvement.
* * +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* * * * @@ -194,6 +219,21 @@ * \{ * \defgroup group_sysclk_returns Function return values * \} +* \defgroup group_sysclk_ext External Clock Source (EXTCLK) +* \{ +* The External Clock Source (EXTCLK) is a clock source routed into PSoC +* through a GPIO pin. The EXTCLK is a source clock that can be used to +* source one or more clock paths (Refer to \ref group_sysclk_path_src). +* These clock paths can then source the processors and peripherals in +* the device. +* +* The EXTCLK relies on the presence of an external clock signal applied +* to the GPIO pin. The pin must be configured to operate in Digital +* High-Z drive mode with input buffer on and HSIOM connection +* set to HSIOM_SEL_ACT_4 (P0_0_SRSS_EXT_CLK, P0_5_SRSS_EXT_CLK). +* +* \defgroup group_sysclk_ext_funcs Functions +* \} * \defgroup group_sysclk_eco External Crystal Oscillator (ECO) * \{ * The External Crystal Oscillator (ECO) is a clock source that consists @@ -571,6 +611,14 @@ * \defgroup group_sysclk_clk_bak_funcs Functions * \defgroup group_sysclk_clk_bak_enums Enumerated Types * \} +* \defgroup group_sysclk_mf_funcs Medium Frequency Domain Clock +* \{ +* The Medium Frequency Domain Clock is present only in SRSS_ver1_3. +* Consists of MFO - the Medium Frequency Oscillator, +* and CLK_MF - the Medium Frequency Clock divider. +* This clock chain is designed to source the LCD block +* in Deep Sleep mode, see \ref cy_en_seglcd_lsclk_t. +* \} */ #if !defined(CY_SYSCLK_H) @@ -594,14 +642,21 @@ extern "C" { /** Driver major version */ #define CY_SYSCLK_DRV_VERSION_MAJOR 1 /** Driver minor version */ -#define CY_SYSCLK_DRV_VERSION_MINOR 30 +#define CY_SYSCLK_DRV_VERSION_MINOR 40 /** Sysclk driver identifier */ #define CY_SYSCLK_ID CY_PDL_DRV_ID(0x12U) /** ILO clock frequency */ #define CY_SYSCLK_ILO_FREQ (32768UL) /* Hz */ +/** WCO clock frequency */ +#define CY_SYSCLK_WCO_FREQ (32768UL) /* Hz */ +/** PILO clock frequency */ +#define CY_SYSCLK_PILO_FREQ (32768UL) /* Hz */ + /** IMO clock frequency */ #define CY_SYSCLK_IMO_FREQ (8000000UL) /* Hz */ +/** MFO clock frequency */ +#define CY_SYSCLK_MFO_FREQ (2000000UL) /* Hz */ /** \} group_sysclk_macros */ @@ -619,13 +674,17 @@ typedef enum } cy_en_sysclk_status_t; /** \} group_sysclk_returns */ -/** \cond INTERNAL */ -/* Calculate a / b with rounding to the nearest integer. a and b must have the same sign */ -#define CY_SYSCLK_DIV_ROUND(a, b) (((a) + ((b) / 2u)) / (b)) -/* Calculate a / b with rounding up if remainder != 0. a and b must both be positive */ -#define CY_SYSCLK_DIV_ROUNDUP(a, b) ((((a) - 1U) / (b)) + 1U) -/** \endcond */ +/* ========================================================================== */ +/* =========================== EXT SECTION ============================ */ +/* ========================================================================== */ + +/** +* \addtogroup group_sysclk_ext_funcs +* \{ +*/ +void Cy_SysClk_ExtClkSetFrequency(uint32_t freq); +/** \} group_sysclk_ext_funcs */ /* ========================================================================== */ /* =========================== ECO SECTION ============================ */ @@ -670,7 +729,7 @@ __STATIC_INLINE uint32_t Cy_SysClk_EcoGetStatus(void); * called if the ECO is sourcing clkHf[0]. * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_EcoDisable +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_EcoDisable * *******************************************************************************/ __STATIC_INLINE void Cy_SysClk_EcoDisable(void) @@ -690,7 +749,7 @@ __STATIC_INLINE void Cy_SysClk_EcoDisable(void) * CY_SYSCLK_ECOSTAT_STABLE = ECO has fully stabilized * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_EcoGetStatus +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_EcoGetStatus * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_SysClk_EcoGetStatus(void) @@ -805,8 +864,29 @@ cy_en_sysclk_status_t Cy_SysClk_FllManualConfigure(const cy_stc_fll_manual_confi void Cy_SysClk_FllGetConfiguration(cy_stc_fll_manual_config_t *config); cy_en_sysclk_status_t Cy_SysClk_FllEnable(uint32_t timeoutus); __STATIC_INLINE bool Cy_SysClk_FllLocked(void); +__STATIC_INLINE bool Cy_SysClk_FllIsEnabled(void); __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_FllDisable(void); + +/******************************************************************************* +* Function Name: Cy_SysClk_FllIsEnabled +****************************************************************************//** +* +* Reports whether or not the FLL is enabled. +* +* \return +* false = disabled \n +* true = enabled +* +* \funcusage +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_FllDisable +* +*******************************************************************************/ +__STATIC_INLINE bool Cy_SysClk_FllIsEnabled(void) +{ + return (_FLD2BOOL(SRSS_CLK_FLL_CONFIG_FLL_ENABLE, SRSS_CLK_FLL_CONFIG)); +} + /******************************************************************************* * Function Name: Cy_SysClk_FllLocked ****************************************************************************//** @@ -823,7 +903,7 @@ __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_FllDisable(void); * is not recommended to check the FLL normal operation stability. * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_FllLocked +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_FllLocked * *******************************************************************************/ __STATIC_INLINE bool Cy_SysClk_FllLocked(void) @@ -849,7 +929,7 @@ __STATIC_INLINE bool Cy_SysClk_FllLocked(void) * the FLL is the source of CLK_HF0 and the CLK_HF0 frequency is decreasing. * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_FllDisable +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_FllDisable * *******************************************************************************/ __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_FllDisable(void) @@ -900,9 +980,35 @@ cy_en_sysclk_status_t Cy_SysClk_PllManualConfigure(uint32_t clkPath, const cy_st cy_en_sysclk_status_t Cy_SysClk_PllGetConfiguration(uint32_t clkPath, cy_stc_pll_manual_config_t *config); cy_en_sysclk_status_t Cy_SysClk_PllEnable(uint32_t clkPath, uint32_t timeoutus); __STATIC_INLINE bool Cy_SysClk_PllLocked(uint32_t clkPath); +__STATIC_INLINE bool Cy_SysClk_PllIsEnabled(uint32_t clkPath); __STATIC_INLINE bool Cy_SysClk_PllLostLock(uint32_t clkPath); __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_PllDisable(uint32_t clkPath); + +/******************************************************************************* +* Function Name: Cy_SysClk_PllIsEnabled +****************************************************************************//** +* +* Reports whether or not the selected PLL is enabled. +* +* \param clkPath Selects which PLL to check. 1 is the first PLL; 0 is invalid. +* +* \return +* false = disabled \n +* true = enabled +* +* \funcusage +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PllDisable +* +*******************************************************************************/ +__STATIC_INLINE bool Cy_SysClk_PllIsEnabled(uint32_t clkPath) +{ + clkPath--; /* to correctly access PLL config and status registers structures */ + CY_ASSERT_L1(clkPath < CY_SRSS_NUM_PLL); + return (_FLD2BOOL(SRSS_CLK_PLL_CONFIG_ENABLE, SRSS_CLK_PLL_CONFIG[clkPath])); +} + + /******************************************************************************* * Function Name: Cy_SysClk_PllLocked ****************************************************************************//** @@ -916,7 +1022,7 @@ __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_PllDisable(uint32_t clkPath); * true = locked * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_PllLocked +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PllLocked * *******************************************************************************/ __STATIC_INLINE bool Cy_SysClk_PllLocked(uint32_t clkPath) @@ -940,7 +1046,7 @@ __STATIC_INLINE bool Cy_SysClk_PllLocked(uint32_t clkPath) * true = lost lock * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_PllLostLock +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PllLostLock * *******************************************************************************/ __STATIC_INLINE bool Cy_SysClk_PllLostLock(uint32_t clkPath) @@ -978,7 +1084,7 @@ __STATIC_INLINE bool Cy_SysClk_PllLostLock(uint32_t clkPath) * the PLL is the source of CLK_HF0 and the CLK_HF0 frequency is decreasing. * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_PllDisable +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PllDisable * *******************************************************************************/ __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_PllDisable(uint32_t clkPath) @@ -1020,7 +1126,7 @@ __STATIC_INLINE void Cy_SysClk_IloHibernateOn(bool on); * \note The watchdog timer (WDT) must be unlocked before calling this function. * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_IloEnable +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_IloEnable * *******************************************************************************/ __STATIC_INLINE void Cy_SysClk_IloEnable(void) @@ -1043,7 +1149,7 @@ __STATIC_INLINE void Cy_SysClk_IloEnable(void) * the ILO. * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_IloDisable +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_IloDisable * *******************************************************************************/ __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_IloDisable(void) @@ -1071,7 +1177,7 @@ __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_IloDisable(void) * \note Writes to the register/bit are ignored if the watchdog (WDT) is locked. * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_IloHibernateOn +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_IloHibernateOn * *******************************************************************************/ __STATIC_INLINE void Cy_SysClk_IloHibernateOn(bool on) @@ -1103,7 +1209,7 @@ __STATIC_INLINE uint32_t Cy_SysClk_PiloGetTrim(void); * releasing the PILO reset. * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_PiloEnable +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PiloEnable * *******************************************************************************/ __STATIC_INLINE void Cy_SysClk_PiloEnable(void) @@ -1122,7 +1228,7 @@ __STATIC_INLINE void Cy_SysClk_PiloEnable(void) * Disables the PILO. * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_PiloDisable +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PiloDisable * *******************************************************************************/ __STATIC_INLINE void Cy_SysClk_PiloDisable(void) @@ -1142,7 +1248,7 @@ __STATIC_INLINE void Cy_SysClk_PiloDisable(void) * done after measuring the PILO frequency; see \ref Cy_SysClk_StartClkMeasurementCounters(). * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_PiloSetTrim +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PiloSetTrim * *******************************************************************************/ __STATIC_INLINE void Cy_SysClk_PiloSetTrim(uint32_t trimVal) @@ -1373,7 +1479,7 @@ __STATIC_INLINE void Cy_SysClk_WcoBypass(cy_en_wco_bypass_modes_t bypass); * CY_SYSCLK_TIMEOUT - Timeout waiting for WCO to stabilize * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_WcoEnable +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_WcoEnable * *******************************************************************************/ __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_WcoEnable(uint32_t timeoutus) @@ -1408,7 +1514,7 @@ __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_WcoEnable(uint32_t timeoutus) * false = not okay * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_WcoOkay +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_WcoOkay * *******************************************************************************/ __STATIC_INLINE bool Cy_SysClk_WcoOkay(void) @@ -1423,7 +1529,7 @@ __STATIC_INLINE bool Cy_SysClk_WcoOkay(void) * Disables the WCO. * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_WcoDisable +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_WcoDisable * *******************************************************************************/ __STATIC_INLINE void Cy_SysClk_WcoDisable(void) @@ -1441,7 +1547,7 @@ __STATIC_INLINE void Cy_SysClk_WcoDisable(void) * \param bypass \ref cy_en_wco_bypass_modes_t * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_WcoBypass +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_WcoBypass * *******************************************************************************/ __STATIC_INLINE void Cy_SysClk_WcoBypass(cy_en_wco_bypass_modes_t bypass) @@ -1451,6 +1557,219 @@ __STATIC_INLINE void Cy_SysClk_WcoBypass(cy_en_wco_bypass_modes_t bypass) /** \} group_sysclk_wco_funcs */ +/* ========================================================================== */ +/* ============================ MF SECTION ============================ */ +/* ========================================================================== */ +/** +* \addtogroup group_sysclk_mf_funcs +* \{ +*/ +__STATIC_INLINE void Cy_SysClk_MfoEnable(bool deepSleepEnable); +__STATIC_INLINE bool Cy_SysClk_MfoIsEnabled(void); +__STATIC_INLINE void Cy_SysClk_MfoDisable(void); + + +/******************************************************************************* +* Function Name: Cy_SysClk_MfoEnable +****************************************************************************//** +* +* Enables the MFO. +* +* \param deepSleepEnable enables MFO operation is Deep Sleep low power mode. +* +* \funcusage +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkMfEnable +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SysClk_MfoEnable(bool deepSleepEnable) +{ + if (CY_SRSS_MFO_PRESENT) + { + SRSS_CLK_MFO_CONFIG = SRSS_CLK_MFO_CONFIG_ENABLE_Msk | (deepSleepEnable ? SRSS_CLK_MFO_CONFIG_DPSLP_ENABLE_Msk : 0UL); + } +} + + +/******************************************************************************* +* Function Name: Cy_SysClk_MfoIsEnabled +****************************************************************************//** +* +* Reports whether MFO is enabled or not. +* +* \return +* false - disabled \n +* true - enabled +* +* \funcusage +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkMfDisable +* +*******************************************************************************/ +__STATIC_INLINE bool Cy_SysClk_MfoIsEnabled(void) +{ + return (CY_SRSS_MFO_PRESENT && (0UL != (SRSS_CLK_MFO_CONFIG & SRSS_CLK_MFO_CONFIG_ENABLE_Msk))); +} + + +/******************************************************************************* +* Function Name: Cy_SysClk_MfoDisable +****************************************************************************//** +* +* Disables the MFO. +* +* \funcusage +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkMfDisable +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SysClk_MfoDisable(void) +{ + if (CY_SRSS_MFO_PRESENT) + { + SRSS_CLK_MFO_CONFIG = 0UL; + } +} + + +__STATIC_INLINE void Cy_SysClk_ClkMfEnable(void); +__STATIC_INLINE bool Cy_SysClk_ClkMfIsEnabled(void); +__STATIC_INLINE void Cy_SysClk_ClkMfDisable(void); +__STATIC_INLINE void Cy_SysClk_ClkMfSetDivider(uint32_t divider); +__STATIC_INLINE uint32_t Cy_SysClk_ClkMfGetDivider(void); +__STATIC_INLINE uint32_t Cy_SysClk_ClkMfGetFrequency(void); + + +/******************************************************************************* +* Function Name: Cy_SysClk_ClkMfEnable +****************************************************************************//** +* +* Enables the CLK_MF. +* +* \funcusage +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkMfEnable +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SysClk_ClkMfEnable(void) +{ + if (CY_SRSS_MFO_PRESENT) + { + SRSS_CLK_MF_SELECT |= SRSS_CLK_MF_SELECT_ENABLE_Msk; + } +} + + +/******************************************************************************* +* Function Name: Cy_SysClk_ClkMfIsEnabled +****************************************************************************//** +* +* Reports whether CLK_MF is enabled or not. +* +* \return +* false - disabled \n +* true - enabled +* +* \funcusage +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkMfEnable +* +*******************************************************************************/ +__STATIC_INLINE bool Cy_SysClk_ClkMfIsEnabled(void) +{ + return ((CY_SRSS_MFO_PRESENT) && (0UL != (SRSS_CLK_MF_SELECT & SRSS_CLK_MF_SELECT_ENABLE_Msk))); +} + + +/******************************************************************************* +* Function Name: Cy_SysClk_ClkMfDisable +****************************************************************************//** +* +* Disables the CLK_MF. +* +* \funcusage +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkMfDisable +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SysClk_ClkMfDisable(void) +{ + if (CY_SRSS_MFO_PRESENT) + { + SRSS_CLK_MF_SELECT &= ~SRSS_CLK_MF_SELECT_ENABLE_Msk; + } +} + + +/** \cond internal */ +#define CY_SYSCLK_MF_DIVIDER_MIN (1U) +#define CY_SYSCLK_MF_DIVIDER_MAX (256U) +#define CY_SYSCLK_IS_MF_DIVIDER_VALID(locDiv) ((CY_SYSCLK_MF_DIVIDER_MIN <= (locDiv)) && ((locDiv) <= CY_SYSCLK_MF_DIVIDER_MAX)) +/** \endcond */ + + +/******************************************************************************* +* Function Name: Cy_SysClk_ClkMfSetDivider +****************************************************************************//** +* +* Sets the clock divider for CLK_MF. +* +* \pre If the CLK_MF is already enabled - it should be disabled +* prior to use this function by \ref Cy_SysClk_ClkMfDisable. +* +* \param divider divider value between 1 and 256. +* +* \funcusage +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkMfEnable +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SysClk_ClkMfSetDivider(uint32_t divider) +{ + if ((CY_SRSS_MFO_PRESENT) && CY_SYSCLK_IS_MF_DIVIDER_VALID(divider)) + { + if (!Cy_SysClk_ClkMfIsEnabled()) + { + CY_REG32_CLR_SET(SRSS_CLK_MF_SELECT, SRSS_CLK_MF_SELECT_MFCLK_DIV, divider - 1UL); + } + } +} + + +/******************************************************************************* +* Function Name: Cy_SysClk_ClkMfGetDivider +****************************************************************************//** +* +* Returns the clock divider of CLK_MF. +* +* \return divider value in range 1..256. +* +* \funcusage +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkMfEnable +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SysClk_ClkMfGetDivider(void) +{ + return ((CY_SRSS_MFO_PRESENT) ? (1UL + _FLD2VAL(SRSS_CLK_MF_SELECT_MFCLK_DIV, SRSS_CLK_MF_SELECT)) : 1UL); +} + + +/******************************************************************************* +* Function Name: Cy_SysClk_ClkMfGetFrequency +****************************************************************************//** +* +* Reports the output clock signal frequency of CLK_MF. +* +* \return The frequency, in Hz. +* +* \funcusage +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkMfEnable +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SysClk_ClkMfGetFrequency(void) +{ + uint32_t locFreq = (Cy_SysClk_MfoIsEnabled()) ? CY_SYSCLK_MFO_FREQ : 0UL; /* Get root frequency */ + uint32_t locDiv = Cy_SysClk_ClkMfGetDivider(); /* clkMf prescaler (1-256) */ + + /* Divide the path input frequency down and return the result */ + return (CY_SYSLIB_DIV_ROUND(locFreq, locDiv)); +} +/** \} group_sysclk_mf_funcs */ + + /* ========================================================================== */ /* ========================= clkHf[n] SECTION ========================= */ /* ========================================================================== */ @@ -1528,6 +1847,10 @@ typedef struct } cy_stc_clkhf_csv_config_t; /** \} group_sysclk_clk_hf_structs */ +/** \cond INTERNAL */ +extern uint32_t altHfFreq; /* Internal storage for BLE ECO frequency user setting */ +/** \endcond */ + /** * \addtogroup group_sysclk_clk_hf_funcs * \{ @@ -1538,6 +1861,7 @@ __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_ClkHfSetSource(uint32_t clkHf, c __STATIC_INLINE cy_en_clkhf_in_sources_t Cy_SysClk_ClkHfGetSource(uint32_t clkHf); __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_ClkHfSetDivider(uint32_t clkHf, cy_en_clkhf_dividers_t divider); __STATIC_INLINE cy_en_clkhf_dividers_t Cy_SysClk_ClkHfGetDivider(uint32_t clkHf); + uint32_t Cy_SysClk_ClkHfGetFrequency(uint32_t clkHf); /******************************************************************************* @@ -1551,7 +1875,7 @@ __STATIC_INLINE cy_en_clkhf_dividers_t Cy_SysClk_ClkHfGetDivider(uint32_t clkHf) * \return \ref cy_en_sysclk_status_t * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_ClkHfEnable +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkHfEnable * *******************************************************************************/ __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_ClkHfEnable(uint32_t clkHf) @@ -1578,7 +1902,7 @@ __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_ClkHfEnable(uint32_t clkHf) * \note clkHf[0] cannot be disabled. * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_ClkHfDisable +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkHfDisable * *******************************************************************************/ __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_ClkHfDisable(uint32_t clkHf) @@ -1618,7 +1942,7 @@ __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_ClkHfDisable(uint32_t clkHf) * CLK_HF0 frequency is decreasing. * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_ClkHfSetSource +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkHfSetSource * *******************************************************************************/ __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_ClkHfSetSource(uint32_t clkHf, cy_en_clkhf_in_sources_t source) @@ -1643,7 +1967,7 @@ __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_ClkHfSetSource(uint32_t clkHf, c * \return \ref cy_en_clkhf_in_sources_t * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_ClkHfSetSource +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkHfSetSource * *******************************************************************************/ __STATIC_INLINE cy_en_clkhf_in_sources_t Cy_SysClk_ClkHfGetSource(uint32_t clkHf) @@ -1679,7 +2003,7 @@ __STATIC_INLINE cy_en_clkhf_in_sources_t Cy_SysClk_ClkHfGetSource(uint32_t clkHf * CLK_HF0 frequency is decreasing. * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_ClkHfSetDivider +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkHfSetDivider * *******************************************************************************/ __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_ClkHfSetDivider(uint32_t clkHf, cy_en_clkhf_dividers_t divider) @@ -1704,7 +2028,7 @@ __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_ClkHfSetDivider(uint32_t clkHf, * \return \ref cy_en_clkhf_dividers_t * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_ClkHfSetDivider +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkHfSetDivider * *******************************************************************************/ __STATIC_INLINE cy_en_clkhf_dividers_t Cy_SysClk_ClkHfGetDivider(uint32_t clkHf) @@ -1724,6 +2048,29 @@ __STATIC_INLINE cy_en_clkhf_dividers_t Cy_SysClk_ClkHfGetDivider(uint32_t clkHf) */ __STATIC_INLINE void Cy_SysClk_ClkFastSetDivider(uint8_t divider); __STATIC_INLINE uint8_t Cy_SysClk_ClkFastGetDivider(void); +__STATIC_INLINE uint32_t Cy_SysClk_ClkFastGetFrequency(void); + + +/******************************************************************************* +* Function Name: Cy_SysClk_ClkFastGetFrequency +****************************************************************************//** +* +* Reports the frequency of the fast clock. +* +* \return The frequency, in Hz. +* +* \funcusage +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkFastSetDivider +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SysClk_ClkFastGetFrequency(void) +{ + uint32_t locFreq = Cy_SysClk_ClkHfGetFrequency(0UL); /* Get root frequency */ + uint32_t locDiv = 1UL + (uint32_t)Cy_SysClk_ClkFastGetDivider(); /* fast prescaler (1-256) */ + + /* Divide the path input frequency down and return the result */ + return (CY_SYSLIB_DIV_ROUND(locFreq, locDiv)); +} /******************************************************************************* * Function Name: Cy_SysClk_ClkFastSetDivider @@ -1747,7 +2094,7 @@ __STATIC_INLINE uint8_t Cy_SysClk_ClkFastGetDivider(void); * CLK_FAST frequency is decreasing. * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_ClkFastSetDivider +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkFastSetDivider * *******************************************************************************/ __STATIC_INLINE void Cy_SysClk_ClkFastSetDivider(uint8_t divider) @@ -1765,7 +2112,7 @@ __STATIC_INLINE void Cy_SysClk_ClkFastSetDivider(uint8_t divider) * The integer division done is by (divider value + 1), or division by 1 to 256. * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_ClkFastSetDivider +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkFastSetDivider * *******************************************************************************/ __STATIC_INLINE uint8_t Cy_SysClk_ClkFastGetDivider(void) @@ -1784,6 +2131,29 @@ __STATIC_INLINE uint8_t Cy_SysClk_ClkFastGetDivider(void) */ __STATIC_INLINE void Cy_SysClk_ClkPeriSetDivider(uint8_t divider); __STATIC_INLINE uint8_t Cy_SysClk_ClkPeriGetDivider(void); +__STATIC_INLINE uint32_t Cy_SysClk_ClkPeriGetFrequency(void); + + +/******************************************************************************* +* Function Name: Cy_SysClk_ClkPeriGetFrequency +****************************************************************************//** +* +* Reports the frequency of the peri clock. +* +* \return The frequency, in Hz. +* +* \funcusage +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPeriSetDivider +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SysClk_ClkPeriGetFrequency(void) +{ + uint32_t locFreq = Cy_SysClk_ClkHfGetFrequency(0UL); /* Get root frequency */ + uint32_t locDiv = 1UL + (uint32_t)Cy_SysClk_ClkPeriGetDivider(); /* peri prescaler (1-256) */ + + /* Divide the path input frequency down and return the result */ + return (CY_SYSLIB_DIV_ROUND(locFreq, locDiv)); +} /******************************************************************************* * Function Name: Cy_SysClk_ClkPeriSetDivider @@ -1800,7 +2170,7 @@ __STATIC_INLINE uint8_t Cy_SysClk_ClkPeriGetDivider(void); * Call \ref SystemCoreClockUpdate after this function calling. * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_ClkPeriSetDivider +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPeriSetDivider * *******************************************************************************/ __STATIC_INLINE void Cy_SysClk_ClkPeriSetDivider(uint8_t divider) @@ -1818,7 +2188,7 @@ __STATIC_INLINE void Cy_SysClk_ClkPeriSetDivider(uint8_t divider) * The integer division done is by (divider value + 1), or division by 1 to 256. * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_ClkPeriSetDivider +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPeriSetDivider * *******************************************************************************/ __STATIC_INLINE uint8_t Cy_SysClk_ClkPeriGetDivider(void) @@ -1882,7 +2252,7 @@ uint32_t Cy_SysClk_PeriphGetFrequency(cy_en_divider_types_t dividerType, uint32_ * \return \ref cy_en_sysclk_status_t * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_PeriphSetDivider +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PeriphSetDivider * *******************************************************************************/ __STATIC_INLINE cy_en_sysclk_status_t @@ -1931,7 +2301,7 @@ __STATIC_INLINE cy_en_sysclk_status_t * (8-bit divider) or 1 to 65536 (16-bit divider). * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_PeriphSetDivider +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PeriphSetDivider * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_SysClk_PeriphGetDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum) @@ -1979,7 +2349,7 @@ __STATIC_INLINE uint32_t Cy_SysClk_PeriphGetDivider(cy_en_divider_types_t divide * \return \ref cy_en_sysclk_status_t * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_PeriphSetFracDivider +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PeriphSetFracDivider * *******************************************************************************/ __STATIC_INLINE cy_en_sysclk_status_t @@ -2032,7 +2402,7 @@ __STATIC_INLINE cy_en_sysclk_status_t * \return None. Loads pointed-to variables. * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_PeriphSetFracDivider +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PeriphSetFracDivider * *******************************************************************************/ __STATIC_INLINE void Cy_SysClk_PeriphGetFracDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum, @@ -2070,7 +2440,7 @@ __STATIC_INLINE void Cy_SysClk_PeriphGetFracDivider(cy_en_divider_types_t divide * \return \ref cy_en_sysclk_status_t * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_PeriphAssignDivider +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PeriphAssignDivider * *******************************************************************************/ __STATIC_INLINE cy_en_sysclk_status_t @@ -2105,7 +2475,7 @@ __STATIC_INLINE cy_en_sysclk_status_t * number within that type * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_PeriphAssignDivider +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PeriphAssignDivider * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_SysClk_PeriphGetAssignedDivider(en_clk_dst_t ipBlock) @@ -2129,7 +2499,7 @@ __STATIC_INLINE uint32_t Cy_SysClk_PeriphGetAssignedDivider(en_clk_dst_t ipBlock * for information on how to phase-align a divider after it is enabled. * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_PeriphEnableDivider +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PeriphEnableDivider * *******************************************************************************/ __STATIC_INLINE cy_en_sysclk_status_t @@ -2167,7 +2537,7 @@ __STATIC_INLINE cy_en_sysclk_status_t * \param dividerNum specifies which divider of the selected type to configure. * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_PeriphDisableDivider +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PeriphDisableDivider * *******************************************************************************/ __STATIC_INLINE cy_en_sysclk_status_t @@ -2213,7 +2583,7 @@ __STATIC_INLINE cy_en_sysclk_status_t * to 63. * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_PeriphEnablePhaseAlignDivider +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PeriphEnablePhaseAlignDivider * *******************************************************************************/ __STATIC_INLINE cy_en_sysclk_status_t @@ -2261,7 +2631,7 @@ __STATIC_INLINE cy_en_sysclk_status_t * true = enabled * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_PeriphGetDividerEnabled +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PeriphGetDividerEnabled * *******************************************************************************/ __STATIC_INLINE bool Cy_SysClk_PeriphGetDividerEnabled(cy_en_divider_types_t dividerType, uint32_t dividerNum) @@ -2304,6 +2674,30 @@ __STATIC_INLINE bool Cy_SysClk_PeriphGetDividerEnabled(cy_en_divider_types_t div */ __STATIC_INLINE void Cy_SysClk_ClkSlowSetDivider(uint8_t divider); __STATIC_INLINE uint8_t Cy_SysClk_ClkSlowGetDivider(void); +__STATIC_INLINE uint32_t Cy_SysClk_ClkSlowGetFrequency(void); + + +/******************************************************************************* +* Function Name: Cy_SysClk_ClkSlowGetFrequency +****************************************************************************//** +* +* Reports the frequency of the slow clock. +* +* \return The frequency, in Hz. +* +* \funcusage +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkSlowSetDivider +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SysClk_ClkSlowGetFrequency(void) +{ + uint32_t locFreq = Cy_SysClk_ClkPeriGetFrequency(); /* Get Peri frequency */ + uint32_t locDiv = 1UL + (uint32_t)Cy_SysClk_ClkSlowGetDivider(); /* peri prescaler (1-256) */ + + /* Divide the path input frequency down and return the result */ + return (CY_SYSLIB_DIV_ROUND(locFreq, locDiv)); +} + /******************************************************************************* * Function Name: Cy_SysClk_ClkSlowSetDivider @@ -2319,7 +2713,7 @@ __STATIC_INLINE uint8_t Cy_SysClk_ClkSlowGetDivider(void); * Call \ref SystemCoreClockUpdate after this function calling. * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_ClkSlowSetDivider +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkSlowSetDivider * *******************************************************************************/ __STATIC_INLINE void Cy_SysClk_ClkSlowSetDivider(uint8_t divider) @@ -2337,7 +2731,7 @@ __STATIC_INLINE void Cy_SysClk_ClkSlowSetDivider(uint8_t divider) * The integer division done is by (divider value + 1), or division by 1 to 256. * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_ClkSlowSetDivider +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkSlowSetDivider * *******************************************************************************/ __STATIC_INLINE uint8_t Cy_SysClk_ClkSlowGetDivider(void) @@ -2385,7 +2779,7 @@ __STATIC_INLINE cy_en_clklf_in_sources_t Cy_SysClk_ClkLfGetSource(void); * \note The watchdog timer (WDT) must be unlocked before calling this function. * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_ClkLfSetSource +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkLfSetSource * *******************************************************************************/ __STATIC_INLINE void Cy_SysClk_ClkLfSetSource(cy_en_clklf_in_sources_t source) @@ -2403,7 +2797,7 @@ __STATIC_INLINE void Cy_SysClk_ClkLfSetSource(cy_en_clklf_in_sources_t source) * \return \ref cy_en_clklf_in_sources_t * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_ClkLfSetSource +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkLfSetSource * *******************************************************************************/ __STATIC_INLINE cy_en_clklf_in_sources_t Cy_SysClk_ClkLfGetSource(void) @@ -2462,7 +2856,7 @@ __STATIC_INLINE void Cy_SysClk_ClkTimerDisable(void); * \param source \ref cy_en_clktimer_in_sources_t * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_ClkTimerSetSource +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkTimerSetSource * *******************************************************************************/ __STATIC_INLINE void Cy_SysClk_ClkTimerSetSource(cy_en_clktimer_in_sources_t source) @@ -2481,7 +2875,7 @@ __STATIC_INLINE void Cy_SysClk_ClkTimerSetSource(cy_en_clktimer_in_sources_t sou * \return \ref cy_en_clktimer_in_sources_t * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_ClkTimerSetSource +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkTimerSetSource * *******************************************************************************/ __STATIC_INLINE cy_en_clktimer_in_sources_t Cy_SysClk_ClkTimerGetSource(void) @@ -2503,7 +2897,7 @@ __STATIC_INLINE cy_en_clktimer_in_sources_t Cy_SysClk_ClkTimerGetSource(void) * Do not change the divider value while the timer clock is enabled. * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_ClkTimerSetDivider +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkTimerSetDivider * *******************************************************************************/ __STATIC_INLINE void Cy_SysClk_ClkTimerSetDivider(uint8_t divider) @@ -2520,7 +2914,7 @@ __STATIC_INLINE void Cy_SysClk_ClkTimerSetDivider(uint8_t divider) * \return The divider value * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_ClkTimerSetDivider +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkTimerSetDivider * *******************************************************************************/ __STATIC_INLINE uint8_t Cy_SysClk_ClkTimerGetDivider(void) @@ -2536,7 +2930,7 @@ __STATIC_INLINE uint8_t Cy_SysClk_ClkTimerGetDivider(void) * for SYSTICK and one or more of the energy profiler counters. * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_ClkTimerEnable +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkTimerEnable * *******************************************************************************/ __STATIC_INLINE void Cy_SysClk_ClkTimerEnable(void) @@ -2551,7 +2945,7 @@ __STATIC_INLINE void Cy_SysClk_ClkTimerEnable(void) * Disables the timer clock (clk_timer). * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_ClkTimerDisable +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkTimerDisable * *******************************************************************************/ __STATIC_INLINE void Cy_SysClk_ClkTimerDisable(void) @@ -2640,7 +3034,7 @@ __STATIC_INLINE void Cy_SysClk_ClkPumpDisable(void); * Do not change the source while the pump clock is enabled. * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_ClkPumpSetSource +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPumpSetSource * *******************************************************************************/ __STATIC_INLINE void Cy_SysClk_ClkPumpSetSource(cy_en_clkpump_in_sources_t source) @@ -2658,7 +3052,7 @@ __STATIC_INLINE void Cy_SysClk_ClkPumpSetSource(cy_en_clkpump_in_sources_t sourc * \return \ref cy_en_clkpump_in_sources_t * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_ClkPumpSetSource +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPumpSetSource * *******************************************************************************/ __STATIC_INLINE cy_en_clkpump_in_sources_t Cy_SysClk_ClkPumpGetSource(void) @@ -2678,7 +3072,7 @@ __STATIC_INLINE cy_en_clkpump_in_sources_t Cy_SysClk_ClkPumpGetSource(void) * Do not change the divider value while the pump clock is enabled. * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_ClkPumpSetDivider +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPumpSetDivider * *******************************************************************************/ __STATIC_INLINE void Cy_SysClk_ClkPumpSetDivider(cy_en_clkpump_divide_t divider) @@ -2696,7 +3090,7 @@ __STATIC_INLINE void Cy_SysClk_ClkPumpSetDivider(cy_en_clkpump_divide_t divider) * \return \ref cy_en_clkpump_divide_t * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_ClkPumpSetDivider +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPumpSetDivider * *******************************************************************************/ __STATIC_INLINE cy_en_clkpump_divide_t Cy_SysClk_ClkPumpGetDivider(void) @@ -2712,7 +3106,7 @@ __STATIC_INLINE cy_en_clkpump_divide_t Cy_SysClk_ClkPumpGetDivider(void) * pumps in the CTBm block. * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_ClkPumpEnable +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPumpEnable * *******************************************************************************/ __STATIC_INLINE void Cy_SysClk_ClkPumpEnable(void) @@ -2727,7 +3121,7 @@ __STATIC_INLINE void Cy_SysClk_ClkPumpEnable(void) * Disables the pump clock (clk_pump). * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_ClkPumpDisable +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPumpDisable * *******************************************************************************/ __STATIC_INLINE void Cy_SysClk_ClkPumpDisable(void) @@ -2777,7 +3171,7 @@ __STATIC_INLINE cy_en_clkbak_in_sources_t Cy_SysClk_ClkBakGetSource(void); * (see \ref Cy_SysClk_ClkLfSetSource), select WCO directly - do not select clkLf. * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_ClkBakSetSource +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkBakSetSource * *******************************************************************************/ __STATIC_INLINE void Cy_SysClk_ClkBakSetSource(cy_en_clkbak_in_sources_t source) @@ -2795,7 +3189,7 @@ __STATIC_INLINE void Cy_SysClk_ClkBakSetSource(cy_en_clkbak_in_sources_t source) * \return \ref cy_en_clkbak_in_sources_t * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_ClkBakSetSource +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkBakSetSource * *******************************************************************************/ __STATIC_INLINE cy_en_clkbak_in_sources_t Cy_SysClk_ClkBakGetSource(void) @@ -2804,6 +3198,14 @@ __STATIC_INLINE cy_en_clkbak_in_sources_t Cy_SysClk_ClkBakGetSource(void) } /** \} group_sysclk_clk_bak_funcs */ + +/** \cond */ +/* Deprecated macros */ +#define CY_SYSCLK_DIV_ROUND(a, b) (CY_SYSLIB_DIV_ROUND((a),(b))) +#define CY_SYSCLK_DIV_ROUNDUP(a, b) (CY_SYSLIB_DIV_ROUNDUP((a),(b))) +/** \endcond */ + + #if defined(__cplusplus) } #endif /* __cplusplus */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sysint.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sysint.h index 20480da090..00ed0eb823 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sysint.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sysint.h @@ -56,7 +56,7 @@ * } * \endcode * And can be used like this: -* \snippet sysint\1.20\snippet\main.c snippet_Cy_SysInt_flashVT +* \snippet sysint/snippet/main.c snippet_Cy_SysInt_flashVT * Using this method avoids the need for a RAM vector table. However in this scenario, * interrupt handler re-location at run-time is not possible, unless the vector table is * relocated to RAM. @@ -424,7 +424,7 @@ cy_israddress Cy_SysInt_GetVector(IRQn_Type IRQn); * Hence modification of the NMI source is strongly discouraged for this core. * * \funcusage -* \snippet sysint\1.20\snippet\main.c snippet_Cy_SysInt_SetNmiSource +* \snippet sysint/snippet/main.c snippet_Cy_SysInt_SetNmiSource * *******************************************************************************/ #if (!CY_CPU_CORTEX_M0P) || defined (CY_DOXYGEN) @@ -465,7 +465,7 @@ __STATIC_INLINE void Cy_SysInt_SetNmiSource(cy_en_sysint_nmi_t nmiNum, cy_en_int * based on the selected core. * * \funcusage -* \snippet sysint\1.20\snippet\main.c snippet_Cy_SysInt_SetNmiSource +* \snippet sysint/snippet/main.c snippet_Cy_SysInt_SetNmiSource * *******************************************************************************/ #if (!CY_CPU_CORTEX_M0P) || defined (CY_DOXYGEN) @@ -501,7 +501,7 @@ __STATIC_INLINE cy_en_intr_t Cy_SysInt_GetNmiSource(cy_en_sysint_nmi_t nmiNum) * Interrupt source * * \funcusage -* \snippet sysint\1.20\snippet\main.c snippet_Cy_SysInt_SoftwareTrig +* \snippet sysint/snippet/main.c snippet_Cy_SysInt_SoftwareTrig * * \note Only privileged software can enable unprivileged access to the * Software Trigger Interrupt Register (STIR). diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_syslib.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_syslib.h index e279318c2d..bf1670a65c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_syslib.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_syslib.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_syslib.h -* \version 2.30 +* \version 2.40 * * Provides an API declaration of the SysLib driver. * @@ -159,6 +159,11 @@ *
VersionChangesReason for Change
1.40Updated the following functions implementation: \ref Cy_SysClk_PllConfigure and \ref Cy_SysClk_PllEnable. +* Fixed the \ref Cy_SysClk_PllConfigure API function behaviour when it is called with a bypass mode, \n +* Fixed the \ref Cy_SysClk_PllEnable API function behaviour when it is called with a zero timeout. +*
Added the following functions: \ref Cy_SysClk_MfoEnable, \ref Cy_SysClk_MfoIsEnabled,\n +* \ref Cy_SysClk_MfoDisable, \ref Cy_SysClk_ClkMfEnable, \ref Cy_SysClk_ClkMfIsEnabled,\n +* \ref Cy_SysClk_ClkMfDisable, \ref Cy_SysClk_ClkMfGetDivider, \ref Cy_SysClk_ClkMfSetDivider,\n. +* \ref Cy_SysClk_ClkMfGetFrequencyNew device support.
Added the following new API functions \ref Cy_SysClk_FllIsEnabled, \ref Cy_SysClk_PllIsEnabled,\n +* \ref Cy_SysClk_ExtClkSetFrequency, \ref Cy_SysClk_ClkHfGetFrequency, \ref Cy_SysClk_ClkFastGetFrequency,\n +* \ref Cy_SysClk_ClkPeriGetFrequency and \ref Cy_SysClk_ClkSlowGetFrequencyEnhancement based on usability feedback
Deprecated the following macros: CY_SYSCLK_DIV_ROUND and CY_SYSCLK_DIV_ROUNDUPMacros were moved into \ref group_syslib
1.30Updated the following functions implementation: \ref Cy_SysClk_EcoConfigure and \ref Cy_SysClk_FllConfigure.Math library dependency is removed, the floating-point math is replaced with integer math.
* * +* +* +* +* +* * * * @@ -168,7 +173,7 @@ * * * -* +* * * * @@ -453,7 +458,7 @@ typedef enum #define CY_SYSLIB_DRV_VERSION_MAJOR 2 /** The driver minor version */ -#define CY_SYSLIB_DRV_VERSION_MINOR 30 +#define CY_SYSLIB_DRV_VERSION_MINOR 40 /******************************************************************************* @@ -881,6 +886,28 @@ typedef double float64_t; /**< Specific-length typedef for the basic numerical #define _FLD2BOOL(field, value) (((value) & (field ## _Msk)) != 0UL) +/******************************************************************************* +* Macro Name: CY_SYSLIB_DIV_ROUND +****************************************************************************//** +* +* Calculates a / b with rounding to the nearest integer, +* a and b must have the same sign. +* +*******************************************************************************/ +#define CY_SYSLIB_DIV_ROUND(a, b) (((a) + ((b) / 2U)) / (b)) + + +/******************************************************************************* +* Macro Name: CY_SYSLIB_DIV_ROUNDUP +****************************************************************************//** +* +* Calculates a / b with rounding up if remainder != 0, +* both a and b must be positive. +* +*******************************************************************************/ +#define CY_SYSLIB_DIV_ROUNDUP(a, b) ((((a) - 1U) / (b)) + 1U) + + /****************************************************************************** * Constants *****************************************************************************/ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_syspm.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_syspm.h index 427ed6fd4d..7970055912 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_syspm.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_syspm.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_syspm.h -* \version 4.10 +* \version 4.20 * * Provides the function definitions for the power management API. * @@ -63,6 +63,7 @@ * - \ref group_syspm_cb_structures * - \ref group_syspm_cb_function_implementation * - \ref group_syspm_cb_flow +* - \ref group_syspm_cb_registering * - \ref group_syspm_cb_unregistering * * \ref group_syspm_definitions * @@ -283,7 +284,7 @@ * * Before setting the regulator minimum current mode ensure that current limits * are be met. After current limits are met, call the -* Cy_SysPm_SystemSetNormalRegulatorCurrent() function. +* Cy_SysPm_SystemSetMinRegulatorCurrent() function. * * \subsection group_syspm_system_set_normal_reg_curr_mode Setting Normal System Regulator Current Mode * @@ -381,16 +382,15 @@ * execute when exiting the low power mode. * * The callback structures after registration: -* \image html syspm_2_10_after_registration.png +* \image html syspm_register_eq.png * * Your application must register each callback, so that SysPm can execute it. * Upon registration, the linked list is built by the SysPm driver. Notice * the &myDeepSleep1 address in the myDeepSleep1 -* \ref cy_stc_syspm_callback_t structure. This is filled in by the SysPm driver -* when you register myDeepSleep1. The order in which the callbacks are -* registered in the application defines the order of their execution by the -* SysPm driver. Call \ref Cy_SysPm_RegisterCallback() to register each -* callback function. +* \ref cy_stc_syspm_callback_t structure. This is filled in by the SysPm driver, +* when you register myDeepSleep1. The cy_stc_syspm_callback_t.order element +* defines the order of their execution by the SysPm driver. +* Call \ref Cy_SysPm_RegisterCallback() to register each callback function. * * A callback function is typically associated with a particular driver that * handles the peripheral. So the callback mechanism enables a peripheral to @@ -423,10 +423,10 @@ * We will build the prototype for an application that registers * three callback functions: * -# myDeepSleep1 - Handles CPU Deep Sleep. -* -# myDeepSleep1 - Handles CPU Deep Sleep and is associated with peripheral +* -# myDeepSleep2 - Handles CPU Deep Sleep and is associated with peripheral * HW1_address (see PDL Design * section to learn about the base hardware address). -* -# myDeepSleep2 - Handles entering and exiting system Deep Sleep and is +* -# myDeepSleep3 - Handles entering and exiting system Deep Sleep and is * associated with peripheral HW2_address. * * We set things up so that the myDeepSleep1 and myDeepSleep2 callbacks do @@ -442,43 +442,43 @@ * Let's first declare the callback functions. Each gets the pointer to the * \ref cy_stc_syspm_callback_params_t structure as the argument. * -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_Callback_Func_Declaration +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_Callback_Func_Declaration * * Now we setup the \ref cy_stc_syspm_callback_params_t structures that we will -* pass to the callback functions. Note that for the myDeepSleep1 and -* myDeepSleep2 callbacks we also pass pointers to the peripherals related to +* pass to the callback functions. Note that for the myDeepSleep2 and +* myDeepSleep3 callbacks we also pass pointers to the peripherals related to * that callback (see PDL Design section * to learn about base hardware addresses). * The configuration considerations related to this structure are described * in \ref group_syspm_cb_parameters in \ref group_syspm_cb_config_consideration. * -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_Callback_Params_Declaration +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_Callback_Params_Declaration * * Now we setup the actual callback configuration structures. Each of these * contains, among the other fields, the address of the * \ref cy_stc_syspm_callback_params_t we just set up. We will use the callback * configuration structures later in the code to register the callbacks in the * SysPm driver. Again, we set things up so that the myDeepSleep1 and -* myDeepSleep1 callbacks do nothing while entering the low power mode +* myDeepSleep2 callbacks do nothing while entering the low power mode * (skip on CY_SYSPM_SKIP_BEFORE_TRANSITION) - see * \ref group_syspm_cb_function_implementation in * \ref group_syspm_cb_config_consideration. * -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_Callback_Structure_Declaration +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_Callback_Structure_Declaration * * Note that in each case the last two fields are NULL. These are fields used by * the SysPm driver to set up the linked list of callback functions. * * The callback structures are now defined and allocated in the user's * memory space: -* \image html syspm_2_10_before_registration.png +* \image html syspm_before_registration.png * * Now we implement the callback functions. See * \ref group_syspm_cb_function_implementation in * \ref group_syspm_cb_config_consideration for the instructions on how the * callback functions should be implemented. * -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_Callback_Func_Implementation +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_Callback_Func_Implementation * * Finally, we register the callbacks so that the SysPm driver knows about them. * The order in which the callbacks will be called depends upon the order in @@ -490,7 +490,7 @@ * entering the low power mode, and restore those resources first, as the system * returns from low power mode. * -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_RegisterCallback +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_RegisterCallback * * We are done configuring three callbacks. Now the SysPm driver will execute the * callbacks appropriately whenever there is a call to a power mode transition @@ -532,8 +532,11 @@ * \subsubsection group_syspm_cb_structures Callback Function Structure * For each callback, provide a \ref cy_stc_syspm_callback_t structure. Some * fields in this structure are maintained by the driver. Use NULL for -* prevItm and nextItm. The driver uses these fields to build a -* linked list of callback functions. +* cy_stc_syspm_callback_t.prevItm and cy_stc_syspm_callback_t.nextItm. +* Driver uses these fields to build a linked list of callback functions. +* The value of cy_stc_syspm_callback_t.order element is used to define the order +* how the callbacks are put into linked list, and sequentially, how the +* callbacks are executed. See \ref group_syspm_cb_registering section. * * \warning The Cy_SysPm_RegisterCallback() function stores a pointer to the * cy_stc_syspm_callback_t structure. Do not modify elements of the @@ -588,7 +591,7 @@ * \ref Cy_SysPm_ExecuteCallback() calls each callback with the mode set to * CY_SYSPM_BEFORE_TRANSITION. This triggers execution of the code for that mode * inside each user callback. We then enter the low power mode after all callback -* are executes. +* are executed. * * When exiting the low power mode, the SysPm driver executes * \ref Cy_SysPm_ExecuteCallback() again. This time it calls each callback in @@ -618,14 +621,47 @@ * step before entering the low power mode, and restore those resources first, * as the system returns from low power mode. * +* \subsubsection group_syspm_cb_registering Callback Registering +* While registration the callback is put into the linked list. The +* place where the callback structure is put into the linked list is based on +* cy_stc_syspm_callback_t.order. The callback with the lowest +* cy_stc_syspm_callback_t.order value will be placed at the beginning of linked +* list. The callback with the highest cy_stc_syspm_callback_t.order value will +* be placed at the end of the linked list. +* If there is already a callback structure in the linked list with the same +* cy_stc_syspm_callback_t.order value as you attend to register, then your +* callback will be placed right after such a callback. +* +* Such a registration order defines how the callbacks are executed: +* * Callbacks with the lower cy_stc_syspm_callback_t.order are executed first +* when entering into low power and last when exiting from low power. +* * Callbacks with the higher cy_stc_syspm_callback_t.order are executed last +* when entering into low power and first when exiting from low power. +* +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_RegisterCallback +* +* Callbacks with equal cy_stc_syspm_callback_t.order values are +* registered in the same order as they are registered: +* \image html syspm_register_eq.png + +* Callbacks with a different cy_stc_syspm_callback_t.order value will be +* stored based on the cy_stc_syspm_callback_t.order value, with no matter when +* they when registered: +* +* \image html syspm_register_dif.png +* +* This can be useful to ensure that system resources (clock dividers, etc) are +* changed right before entering low power mode and immediately after exiting +* from low power. +* * \subsubsection group_syspm_cb_unregistering Callback Unregistering * * Unregistering the callback might be useful when you need to dynamically manage * the callbacks. * -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_UnregisterCallback +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_UnregisterCallback * The callback structures after myDeepSleep2 callback is unregistered: -* \image html syspm_2_10_unregistration.png +* \image html syspm_unregistration.png * * \section group_syspm_definitions Definitions * @@ -688,6 +724,35 @@ *
VersionChangesReason for Change
2.40Added new macros CY_SYSLIB_DIV_ROUND and CY_SYSLIB_DIV_ROUNDUP to easy perform integer division with rounding.Improve PDL code base.
2.30Updated implementation of the Cy_SysLib_AsmInfiniteLoop() function to be compatible with ARMC6.Provided support for the ARM Compiler 6.Documentation update and clarification.
Added new macroses CY_RAMFUNC_BEGIN and CY_RAMFUNC_END for convenient placement function in RAM for all supported compilers.Added new macros CY_RAMFUNC_BEGIN and CY_RAMFUNC_END for convenient placement function in RAM for all supported compilers.Improve user experience.
* * +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* * * * * * @@ -618,10 +616,10 @@ * -* * @@ -634,7 +632,34 @@ *
VersionChangesReason for Change
4.20Updated the \ref Cy_SysPm_RegisterCallback() function. +* Added a new element to callback structure - +* cy_stc_syspm_callback_t.orderEnhanced the mechanism of callbacks registration and execution. Now +* callbacks can be ordered during registration. This means the +* execution flow now is based on cy_stc_syspm_callback_t.order. +* For more details, see the \ref group_syspm_cb_registering section.
Updated \ref group_syspm_cb section. +* Added \ref group_syspm_cb_registering sectionAdded explanations how to use updated callbacks registration +* mechanism.
Added new function \ref Cy_SysPm_GetFailedCallback()Added new functionality to support callback debugging
4.10.1 +* Updated the Cy_SysPm_BackupEnableVoltageMeasurement() description +* +* Changed the scale number from 40% to 10% to correctly reflect a real value. +*
4.10Updated the \ref Cy_SysPm_CpuEnterDeepSleep() function. @@ -1127,7 +1192,7 @@ extern "C" { #define CY_SYSPM_DRV_VERSION_MAJOR 4 /** Driver minor version */ -#define CY_SYSPM_DRV_VERSION_MINOR 10 +#define CY_SYSPM_DRV_VERSION_MINOR 20 /** SysPm driver identifier */ #define CY_SYSPM_ID (CY_PDL_DRV_ID(0x10U)) @@ -1587,6 +1652,12 @@ typedef struct cy_stc_syspm_callback link this structure to the previous registered structure. It will be updated during callback registration. Do not modify this element at run-time. */ + uint8_t order; /**< Holds the callback execution order value. Range: 0-255. + While entering low power mode, callbacks with lower order values + are executed first. While exiting low power mode, + the callbacks are executed in the opposite order. + Callbacks with the same order value are executed in the + order they are registered in the application. */ } cy_stc_syspm_callback_t; /** This internal structure stores non-retained registers in the system Deep Sleep @@ -1732,9 +1803,9 @@ bool Cy_SysPm_BuckIsOutputEnabled(cy_en_syspm_buck_out_t output); bool Cy_SysPm_RegisterCallback(cy_stc_syspm_callback_t *handler); bool Cy_SysPm_UnregisterCallback(cy_stc_syspm_callback_t const *handler); cy_en_syspm_status_t Cy_SysPm_ExecuteCallback(cy_en_syspm_callback_type_t type, cy_en_syspm_callback_mode_t mode); +cy_stc_syspm_callback_t* Cy_SysPm_GetFailedCallback(cy_en_syspm_callback_type_t type); /** \} group_syspm_functions_callback */ - /** * \addtogroup group_syspm_functions_power_status * \{ @@ -1750,7 +1821,7 @@ cy_en_syspm_status_t Cy_SysPm_ExecuteCallback(cy_en_syspm_callback_type_t type, * - False if the CM4 is not in CPU Active mode. * * \funcusage -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_Cm4IsActive +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_Cm4IsActive * *******************************************************************************/ __STATIC_INLINE bool Cy_SysPm_Cm4IsActive(void) @@ -1770,7 +1841,7 @@ __STATIC_INLINE bool Cy_SysPm_Cm4IsActive(void) * - False if the CM4 is not in CPU Sleep mode. * * \funcusage -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_Cm4IsSleep +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_Cm4IsSleep * *******************************************************************************/ __STATIC_INLINE bool Cy_SysPm_Cm4IsSleep(void) @@ -1790,7 +1861,7 @@ __STATIC_INLINE bool Cy_SysPm_Cm4IsSleep(void) * - False if the CM4 is not CPU in Deep Sleep mode. * * \funcusage -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_Cm4IsDeepSleep +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_Cm4IsDeepSleep * *******************************************************************************/ __STATIC_INLINE bool Cy_SysPm_Cm4IsDeepSleep(void) @@ -1810,7 +1881,7 @@ __STATIC_INLINE bool Cy_SysPm_Cm4IsDeepSleep(void) * - False if the CM0+ is not in CPU Sleep mode. * * \funcusage -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_Cm0IsActive +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_Cm0IsActive * *******************************************************************************/ __STATIC_INLINE bool Cy_SysPm_Cm0IsActive(void) @@ -1830,7 +1901,7 @@ __STATIC_INLINE bool Cy_SysPm_Cm0IsActive(void) * - False if the CM0+ is not in CPU Sleep mode. * * \funcusage -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_Cm0IsSleep +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_Cm0IsSleep * *******************************************************************************/ __STATIC_INLINE bool Cy_SysPm_Cm0IsSleep(void) @@ -1850,7 +1921,7 @@ __STATIC_INLINE bool Cy_SysPm_Cm0IsSleep(void) * - False if the CM0+ is not in CPU Deep Sleep mode * * \funcusage -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_Cm0IsDeepSleep +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_Cm0IsDeepSleep * *******************************************************************************/ __STATIC_INLINE bool Cy_SysPm_Cm0IsDeepSleep(void) @@ -1870,7 +1941,7 @@ __STATIC_INLINE bool Cy_SysPm_Cm0IsDeepSleep(void) * - False the system is not in LP mode. * * \funcusage -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_IsSystemLp +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_IsSystemLp * *******************************************************************************/ __STATIC_INLINE bool Cy_SysPm_IsSystemLp(void) @@ -1890,7 +1961,7 @@ __STATIC_INLINE bool Cy_SysPm_IsSystemLp(void) * - False the system is is not ULP mode. * * \funcusage -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_IsSystemUlp +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_IsSystemUlp * *******************************************************************************/ __STATIC_INLINE bool Cy_SysPm_IsSystemUlp(void) @@ -1911,7 +1982,7 @@ __STATIC_INLINE bool Cy_SysPm_IsSystemUlp(void) * Sends the SEV (Send Event) ARM instruction to the system. * * \funcusage -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_CpuSendWakeupEvent +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_CpuSendWakeupEvent * *******************************************************************************/ __STATIC_INLINE void Cy_SysPm_CpuSendWakeupEvent(void) @@ -1931,7 +2002,7 @@ __STATIC_INLINE void Cy_SysPm_CpuSendWakeupEvent(void) * - False - system is in normal regulator current mode. * * \funcusage -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_SystemSetNormalRegulatorCurrent +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_SystemSetNormalRegulatorCurrent * *******************************************************************************/ __STATIC_INLINE bool Cy_SysPm_SystemIsMinRegulatorCurrentSet(void) @@ -1958,7 +2029,7 @@ __STATIC_INLINE bool Cy_SysPm_SystemIsMinRegulatorCurrentSet(void) * - False if it is disabled. * * \funcusage -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_VoltageRegulator +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_VoltageRegulator * *******************************************************************************/ __STATIC_INLINE bool Cy_SysPm_BuckIsEnabled(void) @@ -1982,7 +2053,7 @@ __STATIC_INLINE bool Cy_SysPm_BuckIsEnabled(void) * See \ref cy_en_syspm_buck_voltage1_t. * * \funcusage -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_VoltageRegulator +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_VoltageRegulator * *******************************************************************************/ __STATIC_INLINE cy_en_syspm_buck_voltage1_t Cy_SysPm_BuckGetVoltage1(void) @@ -2015,7 +2086,7 @@ __STATIC_INLINE cy_en_syspm_buck_voltage1_t Cy_SysPm_BuckGetVoltage1(void) * a SIMO Buck. * * \funcusage -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_BuckGetVoltage2 +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_BuckGetVoltage2 * *******************************************************************************/ __STATIC_INLINE cy_en_syspm_buck_voltage2_t Cy_SysPm_BuckGetVoltage2(void) @@ -2051,7 +2122,7 @@ __STATIC_INLINE cy_en_syspm_buck_voltage2_t Cy_SysPm_BuckGetVoltage2(void) * contains a SIMO Buck. * * \funcusage -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_BuckDisableVoltage2 +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_BuckDisableVoltage2 * *******************************************************************************/ __STATIC_INLINE void Cy_SysPm_BuckDisableVoltage2(void) @@ -2085,7 +2156,7 @@ __STATIC_INLINE void Cy_SysPm_BuckDisableVoltage2(void) * contains a SIMO Buck. * * \funcusage -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_BuckSetVoltage2HwControl +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_BuckSetVoltage2HwControl * *******************************************************************************/ __STATIC_INLINE void Cy_SysPm_BuckSetVoltage2HwControl(bool hwControl) @@ -2126,7 +2197,7 @@ __STATIC_INLINE void Cy_SysPm_BuckSetVoltage2HwControl(bool hwControl) * SIMO Buck. * * \funcusage -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_BuckIsVoltage2HwControlled +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_BuckIsVoltage2HwControlled * *******************************************************************************/ __STATIC_INLINE bool Cy_SysPm_BuckIsVoltage2HwControlled(void) @@ -2161,7 +2232,7 @@ __STATIC_INLINE bool Cy_SysPm_BuckIsVoltage2HwControlled(void) * The nominal output voltage of the LDO. See \ref cy_en_syspm_ldo_voltage_t. * * \funcusage -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_VoltageRegulator +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_VoltageRegulator * *******************************************************************************/ __STATIC_INLINE cy_en_syspm_ldo_voltage_t Cy_SysPm_LdoGetVoltage(void) @@ -2185,7 +2256,7 @@ __STATIC_INLINE cy_en_syspm_ldo_voltage_t Cy_SysPm_LdoGetVoltage(void) * - False means it is disabled. * * \funcusage -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_VoltageRegulator +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_VoltageRegulator * *******************************************************************************/ __STATIC_INLINE bool Cy_SysPm_LdoIsEnabled(void) @@ -2210,7 +2281,7 @@ __STATIC_INLINE bool Cy_SysPm_LdoIsEnabled(void) * - False if IOs are unfrozen. * * \funcusage -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_IoUnfreeze +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_IoUnfreeze * *******************************************************************************/ __STATIC_INLINE bool Cy_SysPm_IoIsFrozen(void) @@ -2238,7 +2309,7 @@ __STATIC_INLINE bool Cy_SysPm_IoIsFrozen(void) * Cy_SysPm_PmicUnlock() before enabling the PMIC. * * \funcusage -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_PmicEnable +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_PmicEnable * *******************************************************************************/ __STATIC_INLINE void Cy_SysPm_PmicEnable(void) @@ -2294,7 +2365,7 @@ __STATIC_INLINE void Cy_SysPm_PmicEnable(void) * device TRM. * * \funcusage -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_PmicDisable +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_PmicDisable * *******************************************************************************/ __STATIC_INLINE void Cy_SysPm_PmicDisable(cy_en_syspm_pmic_wakeup_polarity_t polarity) @@ -2323,7 +2394,7 @@ __STATIC_INLINE void Cy_SysPm_PmicDisable(cy_en_syspm_pmic_wakeup_polarity_t pol * assignment in the specific devices, refer to the appropriate device TRM. * * \funcusage -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_PmicAlwaysEnable +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_PmicAlwaysEnable * *******************************************************************************/ __STATIC_INLINE void Cy_SysPm_PmicAlwaysEnable(void) @@ -2345,7 +2416,7 @@ __STATIC_INLINE void Cy_SysPm_PmicAlwaysEnable(void) * specific devices, refer to the appropriate device TRM. * * \funcusage -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_PmicEnableOutput +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_PmicEnableOutput * *******************************************************************************/ __STATIC_INLINE void Cy_SysPm_PmicEnableOutput(void) @@ -2383,7 +2454,7 @@ __STATIC_INLINE void Cy_SysPm_PmicEnableOutput(void) * controller must remain unlocked. * * \funcusage -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_PmicDisableOutput +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_PmicDisableOutput * *******************************************************************************/ __STATIC_INLINE void Cy_SysPm_PmicDisableOutput(void) @@ -2411,7 +2482,7 @@ __STATIC_INLINE void Cy_SysPm_PmicDisableOutput(void) * disabled, the PMIC controller must remain unlocked. * * \funcusage -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_PmicLock +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_PmicLock * *******************************************************************************/ __STATIC_INLINE void Cy_SysPm_PmicLock(void) @@ -2434,7 +2505,7 @@ __STATIC_INLINE void Cy_SysPm_PmicLock(void) * disabled, the PMIC must remain unlocked. * * \funcusage -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_PmicEnable +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_PmicEnable * *******************************************************************************/ __STATIC_INLINE void Cy_SysPm_PmicUnlock(void) @@ -2454,7 +2525,7 @@ __STATIC_INLINE void Cy_SysPm_PmicUnlock(void) * - False if the PMIC is disabled. * * \funcusage -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_PmicLock +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_PmicLock * *******************************************************************************/ __STATIC_INLINE bool Cy_SysPm_PmicIsEnabled(void) @@ -2474,7 +2545,7 @@ __STATIC_INLINE bool Cy_SysPm_PmicIsEnabled(void) * - False if the PMIC output is disabled. * * \funcusage -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_PmicDisable +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_PmicDisable * *******************************************************************************/ __STATIC_INLINE bool Cy_SysPm_PmicIsOutputEnabled(void) @@ -2494,7 +2565,7 @@ __STATIC_INLINE bool Cy_SysPm_PmicIsOutputEnabled(void) * - False if the PMIC is unlocked. * * \funcusage -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_PmicLock +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_PmicLock * *******************************************************************************/ __STATIC_INLINE bool Cy_SysPm_PmicIsLocked(void) @@ -2522,7 +2593,7 @@ __STATIC_INLINE bool Cy_SysPm_PmicIsLocked(void) * Refer to device TRM for more detail about backup supply modes. * * \funcusage -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_BackupSetSupply +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_BackupSetSupply * *******************************************************************************/ __STATIC_INLINE void Cy_SysPm_BackupSetSupply(cy_en_syspm_vddbackup_control_t vddBackControl) @@ -2546,7 +2617,7 @@ __STATIC_INLINE void Cy_SysPm_BackupSetSupply(cy_en_syspm_vddbackup_control_t vd * Refer to device TRM for more detail about backup supply modes. * * \funcusage -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_BackupGetSupply +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_BackupGetSupply * *******************************************************************************/ __STATIC_INLINE cy_en_syspm_vddbackup_control_t Cy_SysPm_BackupGetSupply(void) @@ -2564,13 +2635,13 @@ __STATIC_INLINE cy_en_syspm_vddbackup_control_t Cy_SysPm_BackupGetSupply(void) * * This function enables Vbackup supply measurement by the ADC. The function * connects the Vbackup supply to AMuxBusA. The ADC input can then be connected -* to AMuxBusA. Note that the measured signal is scaled by 40% to allow full +* to AMuxBusA. Note that the measured signal is scaled by 10% to allow full * range measurement by the ADC. * * Refer to device TRM for more detail about Vbackup supply measurement. * * \funcusage -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_BackupEnableVoltageMeasurement +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_BackupEnableVoltageMeasurement * *******************************************************************************/ __STATIC_INLINE void Cy_SysPm_BackupEnableVoltageMeasurement(void) @@ -2589,7 +2660,7 @@ __STATIC_INLINE void Cy_SysPm_BackupEnableVoltageMeasurement(void) * Refer to device TRM for more detail about Vbackup supply measurement. * * \funcusage -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_BackupDisableVoltageMeasurement +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_BackupDisableVoltageMeasurement * *******************************************************************************/ __STATIC_INLINE void Cy_SysPm_BackupDisableVoltageMeasurement(void) @@ -2614,7 +2685,7 @@ __STATIC_INLINE void Cy_SysPm_BackupDisableVoltageMeasurement(void) * detail. * * \funcusage -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_BackupSuperCapCharge +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_BackupSuperCapCharge * *******************************************************************************/ __STATIC_INLINE void Cy_SysPm_BackupSuperCapCharge(cy_en_syspm_sc_charge_key_t key) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_tcpwm.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_tcpwm.h index beb393ce24..91f51262e5 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_tcpwm.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_tcpwm.h @@ -162,14 +162,14 @@ * The dedicated TCPWM pins can be used. The HSIOM register must be configured to * connect the block to the pins. Use the \ref group_gpio driver API to do that. * -* \snippet tcpwm\1.10\counter\snippet\main.c snippet_Cy_TCPWM_Pins +* \snippet tcpwm/counter/snippet/main.c snippet_Cy_TCPWM_Pins * * \subsection group_tcpwm_clock Assign Clock Divider * The clock source must be connected to proper working. * Any of the peripheral clock dividers could be used. Use the * \ref group_sysclk driver API to do that. * -* \snippet tcpwm\1.10\counter\snippet\main.c snippet_Cy_TCPWM_Clock +* \snippet tcpwm/counter/snippet/main.c snippet_Cy_TCPWM_Clock * * \section group_tcpwm_more_information More Information * @@ -421,7 +421,7 @@ __STATIC_INLINE uint32_t Cy_TCPWM_GetInterruptStatusMasked(TCPWM_Type const *bas * A bit field representing each counter in the TCPWM block. * * \funcusage -* \snippet tcpwm\1.10\counter\snippet\main.c snippet_Cy_TCPWM_Enable_Multiple +* \snippet tcpwm/counter/snippet/main.c snippet_Cy_TCPWM_Enable_Multiple * *******************************************************************************/ __STATIC_INLINE void Cy_TCPWM_Enable_Multiple(TCPWM_Type *base, uint32_t counters) @@ -444,7 +444,7 @@ __STATIC_INLINE void Cy_TCPWM_Enable_Multiple(TCPWM_Type *base, uint32_t counter * A bit field representing each counter in the TCPWM block. * * \funcusage -* \snippet tcpwm\1.10\counter\snippet\main.c snippet_Cy_TCPWM_Disable_Multiple +* \snippet tcpwm/counter/snippet/main.c snippet_Cy_TCPWM_Disable_Multiple * *******************************************************************************/ __STATIC_INLINE void Cy_TCPWM_Disable_Multiple(TCPWM_Type *base, uint32_t counters) @@ -466,7 +466,7 @@ __STATIC_INLINE void Cy_TCPWM_Disable_Multiple(TCPWM_Type *base, uint32_t counte * A bit field representing each counter in the TCPWM block. * * \funcusage -* \snippet tcpwm\1.10\counter\snippet\main.c snippet_Cy_TCPWM_Enable_Multiple +* \snippet tcpwm/counter/snippet/main.c snippet_Cy_TCPWM_Enable_Multiple * *******************************************************************************/ __STATIC_INLINE void Cy_TCPWM_TriggerStart(TCPWM_Type *base, uint32_t counters) @@ -488,7 +488,7 @@ __STATIC_INLINE void Cy_TCPWM_TriggerStart(TCPWM_Type *base, uint32_t counters) * A bit field representing each counter in the TCPWM block. * * \funcusage -* \snippet tcpwm\1.10\counter\snippet\main.c snippet_Cy_TCPWM_TriggerReloadOrIndex +* \snippet tcpwm/counter/snippet/main.c snippet_Cy_TCPWM_TriggerReloadOrIndex * *******************************************************************************/ __STATIC_INLINE void Cy_TCPWM_TriggerReloadOrIndex(TCPWM_Type *base, uint32_t counters) @@ -510,7 +510,7 @@ __STATIC_INLINE void Cy_TCPWM_TriggerReloadOrIndex(TCPWM_Type *base, uint32_t co * A bit field representing each counter in the TCPWM block. * * \funcusage -* \snippet tcpwm\1.10\counter\snippet\main.c snippet_Cy_TCPWM_TriggerStopOrKill +* \snippet tcpwm/counter/snippet/main.c snippet_Cy_TCPWM_TriggerStopOrKill * *******************************************************************************/ __STATIC_INLINE void Cy_TCPWM_TriggerStopOrKill(TCPWM_Type *base, uint32_t counters) @@ -532,7 +532,7 @@ __STATIC_INLINE void Cy_TCPWM_TriggerStopOrKill(TCPWM_Type *base, uint32_t count * A bit field representing each counter in the TCPWM block. * * \funcusage -* \snippet tcpwm\1.10\counter\snippet\main.c snippet_Cy_TCPWM_Counter_Capture +* \snippet tcpwm/counter/snippet/main.c snippet_Cy_TCPWM_Counter_Capture * *******************************************************************************/ __STATIC_INLINE void Cy_TCPWM_TriggerCaptureOrSwap(TCPWM_Type *base, uint32_t counters) @@ -557,7 +557,7 @@ __STATIC_INLINE void Cy_TCPWM_TriggerCaptureOrSwap(TCPWM_Type *base, uint32_t co * See \ref group_tcpwm_interrupt_sources * * \funcusage -* \snippet tcpwm\1.10\counter\snippet\main.c snippet_Cy_TCPWM_GetInterruptStatus +* \snippet tcpwm/counter/snippet/main.c snippet_Cy_TCPWM_GetInterruptStatus * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_TCPWM_GetInterruptStatus(TCPWM_Type const *base, uint32_t cntNum) @@ -582,7 +582,7 @@ __STATIC_INLINE uint32_t Cy_TCPWM_GetInterruptStatus(TCPWM_Type const *base, uin * source to clear. See \ref group_tcpwm_interrupt_sources * * \funcusage -* \snippet tcpwm\1.10\counter\snippet\main.c snippet_Cy_TCPWM_GetInterruptStatusMasked +* \snippet tcpwm/counter/snippet/main.c snippet_Cy_TCPWM_GetInterruptStatusMasked * *******************************************************************************/ __STATIC_INLINE void Cy_TCPWM_ClearInterrupt(TCPWM_Type *base, uint32_t cntNum, uint32_t source) @@ -608,7 +608,7 @@ __STATIC_INLINE void Cy_TCPWM_ClearInterrupt(TCPWM_Type *base, uint32_t cntNum, * The source to set an interrupt. See \ref group_tcpwm_interrupt_sources. * * \funcusage -* \snippet tcpwm\1.10\counter\snippet\main.c snippet_Cy_TCPWM_SetInterrupt +* \snippet tcpwm/counter/snippet/main.c snippet_Cy_TCPWM_SetInterrupt * *******************************************************************************/ __STATIC_INLINE void Cy_TCPWM_SetInterrupt(TCPWM_Type *base, uint32_t cntNum, uint32_t source) @@ -634,7 +634,7 @@ __STATIC_INLINE void Cy_TCPWM_SetInterrupt(TCPWM_Type *base, uint32_t cntNum, u *. See \ref group_tcpwm_interrupt_sources * * \funcusage -* \snippet tcpwm\1.10\counter\snippet\main.c snippet_Cy_TCPWM_SetInterruptMask +* \snippet tcpwm/counter/snippet/main.c snippet_Cy_TCPWM_SetInterruptMask * *******************************************************************************/ __STATIC_INLINE void Cy_TCPWM_SetInterruptMask(TCPWM_Type *base, uint32_t cntNum, uint32_t mask) @@ -659,7 +659,7 @@ __STATIC_INLINE void Cy_TCPWM_SetInterruptMask(TCPWM_Type *base, uint32_t cntNum * Interrupt Mask. See \ref group_tcpwm_interrupt_sources * * \funcusage -* \snippet tcpwm\1.10\counter\snippet\main.c snippet_Cy_TCPWM_SetInterruptMask +* \snippet tcpwm/counter/snippet/main.c snippet_Cy_TCPWM_SetInterruptMask * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_TCPWM_GetInterruptMask(TCPWM_Type const *base, uint32_t cntNum) @@ -684,7 +684,7 @@ __STATIC_INLINE uint32_t Cy_TCPWM_GetInterruptMask(TCPWM_Type const *base, uint3 * Interrupt Mask. See \ref group_tcpwm_interrupt_sources * * \funcusage -* \snippet tcpwm\1.10\counter\snippet\main.c snippet_Cy_TCPWM_GetInterruptStatusMasked +* \snippet tcpwm/counter/snippet/main.c snippet_Cy_TCPWM_GetInterruptStatusMasked * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_TCPWM_GetInterruptStatusMasked(TCPWM_Type const *base, uint32_t cntNum) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_tcpwm_counter.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_tcpwm_counter.h index c703faf497..667b45f476 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_tcpwm_counter.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_tcpwm_counter.h @@ -184,7 +184,7 @@ __STATIC_INLINE uint32_t Cy_TCPWM_Counter_GetPeriod(TCPWM_Type const *base, uint * The Counter instance number in the selected TCPWM. * * \funcusage -* \snippet tcpwm\1.10\counter\snippet\main.c snippet_Cy_TCPWM_Counter_Init +* \snippet tcpwm/counter/snippet/main.c snippet_Cy_TCPWM_Counter_Init * *******************************************************************************/ __STATIC_INLINE void Cy_TCPWM_Counter_Enable(TCPWM_Type *base, uint32_t cntNum) @@ -206,7 +206,7 @@ __STATIC_INLINE void Cy_TCPWM_Counter_Enable(TCPWM_Type *base, uint32_t cntNum) * The Counter instance number in the selected TCPWM. * * \funcusage -* \snippet tcpwm\1.10\counter\snippet\main.c snippet_Cy_TCPWM_Counter_DeInit +* \snippet tcpwm/counter/snippet/main.c snippet_Cy_TCPWM_Counter_DeInit * *******************************************************************************/ __STATIC_INLINE void Cy_TCPWM_Counter_Disable(TCPWM_Type *base, uint32_t cntNum) @@ -231,7 +231,7 @@ __STATIC_INLINE void Cy_TCPWM_Counter_Disable(TCPWM_Type *base, uint32_t cntNum) * The status. See \ref group_tcpwm_counter_status * * \funcusage -* \snippet tcpwm\1.10\counter\snippet\main.c snippet_Cy_TCPWM_Counter_GetStatus +* \snippet tcpwm/counter/snippet/main.c snippet_Cy_TCPWM_Counter_GetStatus * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_TCPWM_Counter_GetStatus(TCPWM_Type const *base, uint32_t cntNum) @@ -263,7 +263,7 @@ __STATIC_INLINE uint32_t Cy_TCPWM_Counter_GetStatus(TCPWM_Type const *base, uin * The capture value. * * \funcusage -* \snippet tcpwm\1.10\counter\snippet\main.c snippet_Cy_TCPWM_Counter_Capture +* \snippet tcpwm/counter/snippet/main.c snippet_Cy_TCPWM_Counter_Capture * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_TCPWM_Counter_GetCapture(TCPWM_Type const *base, uint32_t cntNum) @@ -288,7 +288,7 @@ __STATIC_INLINE uint32_t Cy_TCPWM_Counter_GetCapture(TCPWM_Type const *base, ui * The buffered capture value. * * \funcusage -* \snippet tcpwm\1.10\counter\snippet\main.c snippet_Cy_TCPWM_Counter_Capture +* \snippet tcpwm/counter/snippet/main.c snippet_Cy_TCPWM_Counter_Capture * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_TCPWM_Counter_GetCaptureBuf(TCPWM_Type const *base, uint32_t cntNum) @@ -313,7 +313,7 @@ __STATIC_INLINE uint32_t Cy_TCPWM_Counter_GetCaptureBuf(TCPWM_Type const *base, * The Compare0 value. * * \funcusage -* \snippet tcpwm\1.10\counter\snippet\main.c snippet_Cy_TCPWM_Counter_SetCompare0 +* \snippet tcpwm/counter/snippet/main.c snippet_Cy_TCPWM_Counter_SetCompare0 * *******************************************************************************/ __STATIC_INLINE void Cy_TCPWM_Counter_SetCompare0(TCPWM_Type *base, uint32_t cntNum, uint32_t compare0) @@ -338,7 +338,7 @@ __STATIC_INLINE void Cy_TCPWM_Counter_SetCompare0(TCPWM_Type *base, uint32_t cnt * Compare value 0. * * \funcusage -* \snippet tcpwm\1.10\counter\snippet\main.c snippet_Cy_TCPWM_Counter_SetCompare0 +* \snippet tcpwm/counter/snippet/main.c snippet_Cy_TCPWM_Counter_SetCompare0 * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_TCPWM_Counter_GetCompare0(TCPWM_Type const *base, uint32_t cntNum) @@ -363,7 +363,7 @@ __STATIC_INLINE uint32_t Cy_TCPWM_Counter_GetCompare0(TCPWM_Type const *base, u * The Compare1 value. * * \funcusage -* \snippet tcpwm\1.10\counter\snippet\main.c snippet_Cy_TCPWM_Counter_SetCompare1 +* \snippet tcpwm/counter/snippet/main.c snippet_Cy_TCPWM_Counter_SetCompare1 * *******************************************************************************/ __STATIC_INLINE void Cy_TCPWM_Counter_SetCompare1(TCPWM_Type *base, uint32_t cntNum, uint32_t compare1) @@ -388,7 +388,7 @@ __STATIC_INLINE void Cy_TCPWM_Counter_SetCompare1(TCPWM_Type *base, uint32_t cnt * Compare value 1. * * \funcusage -* \snippet tcpwm\1.10\counter\snippet\main.c snippet_Cy_TCPWM_Counter_SetCompare1 +* \snippet tcpwm/counter/snippet/main.c snippet_Cy_TCPWM_Counter_SetCompare1 * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_TCPWM_Counter_GetCompare1(TCPWM_Type const *base, uint32_t cntNum) @@ -413,7 +413,7 @@ __STATIC_INLINE uint32_t Cy_TCPWM_Counter_GetCompare1(TCPWM_Type const *base, u * true = swap enabled, false = swap disabled * * \funcusage -* \snippet tcpwm\1.10\counter\snippet\main.c snippet_Cy_TCPWM_Counter_EnableCompareSwap +* \snippet tcpwm/counter/snippet/main.c snippet_Cy_TCPWM_Counter_EnableCompareSwap * *******************************************************************************/ __STATIC_INLINE void Cy_TCPWM_Counter_EnableCompareSwap(TCPWM_Type *base, uint32_t cntNum, bool enable) @@ -445,7 +445,7 @@ __STATIC_INLINE void Cy_TCPWM_Counter_EnableCompareSwap(TCPWM_Type *base, uint32 * The value to write into the counter. * * \funcusage -* \snippet tcpwm\1.10\counter\snippet\main.c snippet_Cy_TCPWM_Counter_SetCounter +* \snippet tcpwm/counter/snippet/main.c snippet_Cy_TCPWM_Counter_SetCounter * *******************************************************************************/ __STATIC_INLINE void Cy_TCPWM_Counter_SetCounter(TCPWM_Type *base, uint32_t cntNum, uint32_t count) @@ -470,7 +470,7 @@ __STATIC_INLINE void Cy_TCPWM_Counter_SetCounter(TCPWM_Type *base, uint32_t cntN * The current counter value. * * \funcusage -* \snippet tcpwm\1.10\counter\snippet\main.c snippet_Cy_TCPWM_Counter_GetCounter +* \snippet tcpwm/counter/snippet/main.c snippet_Cy_TCPWM_Counter_GetCounter * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_TCPWM_Counter_GetCounter(TCPWM_Type const *base, uint32_t cntNum) @@ -495,7 +495,7 @@ __STATIC_INLINE uint32_t Cy_TCPWM_Counter_GetCounter(TCPWM_Type const *base, ui * The value to write into a period. * * \funcusage -* \snippet tcpwm\1.10\counter\snippet\main.c snippet_Cy_TCPWM_Counter_SetPeriod +* \snippet tcpwm/counter/snippet/main.c snippet_Cy_TCPWM_Counter_SetPeriod * *******************************************************************************/ __STATIC_INLINE void Cy_TCPWM_Counter_SetPeriod(TCPWM_Type *base, uint32_t cntNum, uint32_t period) @@ -520,7 +520,7 @@ __STATIC_INLINE void Cy_TCPWM_Counter_SetPeriod(TCPWM_Type *base, uint32_t cntNu * The current period value. * * \funcusage -* \snippet tcpwm\1.10\counter\snippet\main.c snippet_Cy_TCPWM_Counter_SetPeriod +* \snippet tcpwm/counter/snippet/main.c snippet_Cy_TCPWM_Counter_SetPeriod * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_TCPWM_Counter_GetPeriod(TCPWM_Type const *base, uint32_t cntNum) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_tcpwm_pwm.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_tcpwm_pwm.h index c3a123922d..e0f518152e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_tcpwm_pwm.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_tcpwm_pwm.h @@ -241,7 +241,7 @@ __STATIC_INLINE void Cy_TCPWM_PWM_EnablePeriodSwap(TCPWM_Type *base, uint32_t cn * The Counter instance number in the selected TCPWM. * * \funcusage -* \snippet tcpwm\1.10\pwm\snippet\main.c snippet_Cy_TCPWM_PWM_Init +* \snippet tcpwm/pwm/snippet/main.c snippet_Cy_TCPWM_PWM_Init * *******************************************************************************/ __STATIC_INLINE void Cy_TCPWM_PWM_Enable(TCPWM_Type *base, uint32_t cntNum) @@ -262,7 +262,7 @@ __STATIC_INLINE void Cy_TCPWM_PWM_Enable(TCPWM_Type *base, uint32_t cntNum) * The Counter instance number in the selected TCPWM. * * \funcusage -* \snippet tcpwm\1.10\pwm\snippet\main.c snippet_Cy_TCPWM_PWM_DeInit +* \snippet tcpwm/pwm/snippet/main.c snippet_Cy_TCPWM_PWM_DeInit * *******************************************************************************/ __STATIC_INLINE void Cy_TCPWM_PWM_Disable(TCPWM_Type *base, uint32_t cntNum) @@ -287,7 +287,7 @@ __STATIC_INLINE void Cy_TCPWM_PWM_Disable(TCPWM_Type *base, uint32_t cntNum) * The status. See \ref group_tcpwm_pwm_status * * \funcusage -* \snippet tcpwm\1.10\pwm\snippet\main.c snippet_Cy_TCPWM_PWM_GetStatus +* \snippet tcpwm/pwm/snippet/main.c snippet_Cy_TCPWM_PWM_GetStatus * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_TCPWM_PWM_GetStatus(TCPWM_Type const *base, uint32_t cntNum) @@ -319,7 +319,7 @@ __STATIC_INLINE uint32_t Cy_TCPWM_PWM_GetStatus(TCPWM_Type const *base, uint32_t * The Compare0 value. * * \funcusage -* \snippet tcpwm\1.10\pwm\snippet\main.c snippet_Cy_TCPWM_PWM_SetCompare0 +* \snippet tcpwm/pwm/snippet/main.c snippet_Cy_TCPWM_PWM_SetCompare0 * *******************************************************************************/ __STATIC_INLINE void Cy_TCPWM_PWM_SetCompare0(TCPWM_Type *base, uint32_t cntNum, uint32_t compare0) @@ -344,7 +344,7 @@ __STATIC_INLINE void Cy_TCPWM_PWM_SetCompare0(TCPWM_Type *base, uint32_t cntNum, * Compare value 0. * * \funcusage -* \snippet tcpwm\1.10\pwm\snippet\main.c snippet_Cy_TCPWM_PWM_SetCompare0 +* \snippet tcpwm/pwm/snippet/main.c snippet_Cy_TCPWM_PWM_SetCompare0 * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_TCPWM_PWM_GetCompare0(TCPWM_Type const *base, uint32_t cntNum) @@ -369,7 +369,7 @@ __STATIC_INLINE uint32_t Cy_TCPWM_PWM_GetCompare0(TCPWM_Type const *base, uint32 * The Compare1 value. * * \funcusage -* \snippet tcpwm\1.10\pwm\snippet\main.c snippet_Cy_TCPWM_PWM_SetCompare1 +* \snippet tcpwm/pwm/snippet/main.c snippet_Cy_TCPWM_PWM_SetCompare1 * *******************************************************************************/ __STATIC_INLINE void Cy_TCPWM_PWM_SetCompare1(TCPWM_Type *base, uint32_t cntNum, uint32_t compare1) @@ -394,7 +394,7 @@ __STATIC_INLINE void Cy_TCPWM_PWM_SetCompare1(TCPWM_Type *base, uint32_t cntNum, * Compare value 1. * * \funcusage -* \snippet tcpwm\1.10\pwm\snippet\main.c snippet_Cy_TCPWM_PWM_SetCompare1 +* \snippet tcpwm/pwm/snippet/main.c snippet_Cy_TCPWM_PWM_SetCompare1 * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_TCPWM_PWM_GetCompare1(TCPWM_Type const *base, uint32_t cntNum) @@ -419,7 +419,7 @@ __STATIC_INLINE uint32_t Cy_TCPWM_PWM_GetCompare1(TCPWM_Type const *base, uint32 * true = swap enabled; false = swap disabled * * \funcusage -* \snippet tcpwm\1.10\pwm\snippet\main.c snippet_Cy_TCPWM_PWM_EnableCompareSwap +* \snippet tcpwm/pwm/snippet/main.c snippet_Cy_TCPWM_PWM_EnableCompareSwap * *******************************************************************************/ __STATIC_INLINE void Cy_TCPWM_PWM_EnableCompareSwap(TCPWM_Type *base, uint32_t cntNum, bool enable) @@ -451,7 +451,7 @@ __STATIC_INLINE void Cy_TCPWM_PWM_EnableCompareSwap(TCPWM_Type *base, uint32_t c * The value to write into the counter. * * \funcusage -* \snippet tcpwm\1.10\pwm\snippet\main.c snippet_Cy_TCPWM_PWM_SetCounter +* \snippet tcpwm/pwm/snippet/main.c snippet_Cy_TCPWM_PWM_SetCounter * *******************************************************************************/ __STATIC_INLINE void Cy_TCPWM_PWM_SetCounter(TCPWM_Type *base, uint32_t cntNum, uint32_t count) @@ -476,7 +476,7 @@ __STATIC_INLINE void Cy_TCPWM_PWM_SetCounter(TCPWM_Type *base, uint32_t cntNum, * The current counter value. * * \funcusage -* \snippet tcpwm\1.10\pwm\snippet\main.c snippet_Cy_TCPWM_PWM_GetCounter +* \snippet tcpwm/pwm/snippet/main.c snippet_Cy_TCPWM_PWM_GetCounter * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_TCPWM_PWM_GetCounter(TCPWM_Type const *base, uint32_t cntNum) @@ -501,7 +501,7 @@ __STATIC_INLINE uint32_t Cy_TCPWM_PWM_GetCounter(TCPWM_Type const *base, uint32_ * The value to write into a period. * * \funcusage -* \snippet tcpwm\1.10\pwm\snippet\main.c snippet_Cy_TCPWM_PWM_SetPeriod0 +* \snippet tcpwm/pwm/snippet/main.c snippet_Cy_TCPWM_PWM_SetPeriod0 * *******************************************************************************/ __STATIC_INLINE void Cy_TCPWM_PWM_SetPeriod0(TCPWM_Type *base, uint32_t cntNum, uint32_t period0) @@ -526,7 +526,7 @@ __STATIC_INLINE void Cy_TCPWM_PWM_SetPeriod0(TCPWM_Type *base, uint32_t cntNum, * The current period value. * * \funcusage -* \snippet tcpwm\1.10\pwm\snippet\main.c snippet_Cy_TCPWM_PWM_SetPeriod0 +* \snippet tcpwm/pwm/snippet/main.c snippet_Cy_TCPWM_PWM_SetPeriod0 * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_TCPWM_PWM_GetPeriod0(TCPWM_Type const *base, uint32_t cntNum) @@ -551,7 +551,7 @@ __STATIC_INLINE uint32_t Cy_TCPWM_PWM_GetPeriod0(TCPWM_Type const *base, uint32_ * The value to write into a period1. * * \funcusage -* \snippet tcpwm\1.10\pwm\snippet\main.c snippet_Cy_TCPWM_PWM_SetPeriod1 +* \snippet tcpwm/pwm/snippet/main.c snippet_Cy_TCPWM_PWM_SetPeriod1 * *******************************************************************************/ __STATIC_INLINE void Cy_TCPWM_PWM_SetPeriod1(TCPWM_Type *base, uint32_t cntNum, uint32_t period1) @@ -576,7 +576,7 @@ __STATIC_INLINE void Cy_TCPWM_PWM_SetPeriod1(TCPWM_Type *base, uint32_t cntNum, * The current period value. * * \funcusage -* \snippet tcpwm\1.10\pwm\snippet\main.c snippet_Cy_TCPWM_PWM_SetPeriod1 +* \snippet tcpwm/pwm/snippet/main.c snippet_Cy_TCPWM_PWM_SetPeriod1 * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_TCPWM_PWM_GetPeriod1(TCPWM_Type const *base, uint32_t cntNum) @@ -601,7 +601,7 @@ __STATIC_INLINE uint32_t Cy_TCPWM_PWM_GetPeriod1(TCPWM_Type const *base, uint32_ * true = swap enabled; false = swap disabled * * \funcusage -* \snippet tcpwm\1.10\pwm\snippet\main.c snippet_Cy_TCPWM_PWM_EnablePeriodSwap +* \snippet tcpwm/pwm/snippet/main.c snippet_Cy_TCPWM_PWM_EnablePeriodSwap * *******************************************************************************/ __STATIC_INLINE void Cy_TCPWM_PWM_EnablePeriodSwap(TCPWM_Type *base, uint32_t cntNum, bool enable) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_tcpwm_quaddec.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_tcpwm_quaddec.h index c8d0b797ff..476014326b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_tcpwm_quaddec.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_tcpwm_quaddec.h @@ -141,7 +141,7 @@ __STATIC_INLINE uint32_t Cy_TCPWM_QuadDec_GetCounter(TCPWM_Type const *base, uin * The Counter instance number in the selected TCPWM. * * \funcusage -* \snippet tcpwm\1.10\quaddec\snippet\main.c snippet_Cy_TCPWM_QuadDec_Init +* \snippet tcpwm/quaddec/snippet/main.c snippet_Cy_TCPWM_QuadDec_Init * *******************************************************************************/ __STATIC_INLINE void Cy_TCPWM_QuadDec_Enable(TCPWM_Type *base, uint32_t cntNum) @@ -162,7 +162,7 @@ __STATIC_INLINE void Cy_TCPWM_QuadDec_Enable(TCPWM_Type *base, uint32_t cntNum) * The Counter instance number in the selected TCPWM. * * \funcusage -* \snippet tcpwm\1.10\quaddec\snippet\main.c snippet_Cy_TCPWM_QuadDec_DeInit +* \snippet tcpwm/quaddec/snippet/main.c snippet_Cy_TCPWM_QuadDec_DeInit * *******************************************************************************/ __STATIC_INLINE void Cy_TCPWM_QuadDec_Disable(TCPWM_Type *base, uint32_t cntNum) @@ -187,7 +187,7 @@ __STATIC_INLINE void Cy_TCPWM_QuadDec_Disable(TCPWM_Type *base, uint32_t cntNum) * The status. See \ref group_tcpwm_quaddec_status * * \funcusage -* \snippet tcpwm\1.10\quaddec\snippet\main.c snippet_Cy_TCPWM_QuadDec_GetStatus +* \snippet tcpwm/quaddec/snippet/main.c snippet_Cy_TCPWM_QuadDec_GetStatus * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_TCPWM_QuadDec_GetStatus(TCPWM_Type const *base, uint32_t cntNum) @@ -219,7 +219,7 @@ __STATIC_INLINE uint32_t Cy_TCPWM_QuadDec_GetStatus(TCPWM_Type const *base, uint * The capture value. * * \funcusage -* \snippet tcpwm\1.10\quaddec\snippet\main.c snippet_Cy_TCPWM_QuadDec_Capture +* \snippet tcpwm/quaddec/snippet/main.c snippet_Cy_TCPWM_QuadDec_Capture * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_TCPWM_QuadDec_GetCapture(TCPWM_Type const *base, uint32_t cntNum) @@ -244,7 +244,7 @@ __STATIC_INLINE uint32_t Cy_TCPWM_QuadDec_GetCapture(TCPWM_Type const *base, uin * The buffered capture value. * * \funcusage -* \snippet tcpwm\1.10\quaddec\snippet\main.c snippet_Cy_TCPWM_QuadDec_Capture +* \snippet tcpwm/quaddec/snippet/main.c snippet_Cy_TCPWM_QuadDec_Capture * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_TCPWM_QuadDec_GetCaptureBuf(TCPWM_Type const *base, uint32_t cntNum) @@ -269,7 +269,7 @@ __STATIC_INLINE uint32_t Cy_TCPWM_QuadDec_GetCaptureBuf(TCPWM_Type const *base, * The value to write into the counter. * * \funcusage -* \snippet tcpwm\1.10\quaddec\snippet\main.c snippet_Cy_TCPWM_QuadDec_SetCounter +* \snippet tcpwm/quaddec/snippet/main.c snippet_Cy_TCPWM_QuadDec_SetCounter * *******************************************************************************/ __STATIC_INLINE void Cy_TCPWM_QuadDec_SetCounter(TCPWM_Type *base, uint32_t cntNum, uint32_t count) @@ -294,7 +294,7 @@ __STATIC_INLINE void Cy_TCPWM_QuadDec_SetCounter(TCPWM_Type *base, uint32_t cntN * The current counter value. * * \funcusage -* \snippet tcpwm\1.10\quaddec\snippet\main.c snippet_Cy_TCPWM_QuadDec_GetCounter +* \snippet tcpwm/quaddec/snippet/main.c snippet_Cy_TCPWM_QuadDec_GetCounter * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_TCPWM_QuadDec_GetCounter(TCPWM_Type const *base, uint32_t cntNum) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_usbfs_dev_drv.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_usbfs_dev_drv.h index 753e528c56..59c322536a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_usbfs_dev_drv.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_usbfs_dev_drv.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_usbfs_dev_drv.h -* \version 1.10 +* \version 2.0 * * Provides API declarations of the USBFS driver. * @@ -26,7 +26,7 @@ /** * \addtogroup group_usbfs_dev_drv * \{ -* The USBFS driver provides API to interact with a fixed-function USB block. +* The USBFS driver provides an API to interact with a fixed-function USB block. * * The functions and other declarations used in this driver are in cy_usbfs_dev_drv.h. * You can include cy_pdl.h (ModusToolbox only) to get access to all functions @@ -39,22 +39,22 @@ * * Complies with USB Specification 2.0 * * Supports full-speed peripheral device operation with a signaling bit * rate of 12 Mbps. -* * Supports eight data endpoints and one control endpoint -* * Provides shared 512-byte buffer for data endpoints -* * Provides dedicated 8-byte memory for control endpoint (EP0) +* * Supports eight data endpoints and one control endpoint. +* * Provides a shared 512-byte buffer for data endpoints. +* * Provides dedicated 8-byte memory for control endpoint (EP0). * * Supports four types of transfers: bulk, interrupt, isochronous, and control * * Supports bus- and self-powered configurations -* * Supports USB suspend, resume, and remove wakeup +* * Supports USB suspend, resume, and remove wakeup. * * Supports three types of logical transfer modes: * * CPU (No DMA) mode (Mode 1). * * Manual DMA mode (Mode 2). * * Automatic DMA mode (Mode 3). -* * Supports maximum packet size: +* * Supports the maximum packet size: * * 512 bytes using Mode 1 and Mode 2. * * 1023 bytes for isochronous transfer using Mode 3. * * Provides integrated 22 Ohm USB termination resistors on D+ and D- lines, -* and 1.5 kOhm pull-up resistor on the D+ line -* * Supports USB 2.0 Link Power Management (LPM) +* and 1.5 kOhm pull-up resistor on the D+ line. +* * Supports USB 2.0 Link Power Management (LPM). * * ******************************************************************************** @@ -64,7 +64,7 @@ * The primary usage model for the USBFS driver is to provide a defined API * interface to USB Device Middleware * component that works on top of it. \n -* The driver also provides an API interface for the application to implement required +* The driver also provides an API interface for the application to implement the required * functionality: * * \ref group_usbfs_dev_drv_callbacks * * \ref group_usbfs_dev_drv_low_power @@ -75,9 +75,9 @@ * \section group_usbfs_dev_drv_configuration Configuration Considerations ******************************************************************************** * -* This section explains how to configure USBFS driver and system resources to -* enable USB Device operation. The pointers to populated \ref cy_stc_usbfs_dev_drv_config_t configuration -* structure and allocated context are passed in the middleware initialization +* This section explains how to configure the USBFS driver and system resources to +* enable USB Device operation. The pointers to the populated \ref cy_stc_usbfs_dev_drv_config_t configuration +* structure and allocated context are passed in the middleware initialization. * function Cy_USB_Dev_Init. After middleware initialization, it calls * \ref Cy_USBFS_Dev_Drv_Init to initialize the USBFS driver for Device operation. @@ -96,52 +96,52 @@ * \ref group_usbfs_dev_drv_intr to get information about intrLevelSel * configuration. * -* \snippet usbfs/1.0/snippet/main.c snipped_Cy_USBFS_Dev_Drv_CfgCpu +* \snippet usbfs/snippet/main.c snipped_Cy_USBFS_Dev_Drv_CfgCpu * * * \ref CY_USBFS_DEV_DRV_EP_MANAGEMENT_DMA \n -* To enable DMA operation the DMA channels must be assigned for each endpoint -* that will be used. Each DMA channel needs a single DMA descriptor to -* operate. The USBFS driver defines DMA configuration structure -* \ref cy_stc_usbfs_dev_drv_dma_config_t, which must be populated for each DMA +* To enable DMA operation, the DMA channels must be assigned for each endpoint +* to be used. Each DMA channel needs a single DMA descriptor to +* operate. The USBFS driver defines the DMA configuration structure +* \ref cy_stc_usbfs_dev_drv_dma_config_t to be populated for each DMA * channel. -* The code example below provides initialized USBFS driver DMA configuration +* The code example below provides an initialized USBFS driver DMA configuration * structure: * -* \snippet usbfs/1.0/snippet/main.c snipped_Cy_USBFS_Dev_Drv_CfgDma_DmaInit +* \snippet usbfs/snippet/main.c snipped_Cy_USBFS_Dev_Drv_CfgDma_DmaInit * -* The pointers to the DMA configuration structure must provided into the +* The pointers to the DMA configuration structure are required into the * \ref cy_stc_usbfs_dev_drv_config_t USBFS driver configuration structure -* to allow USBFS driver use DMA channels for used endpoints. -* The dmaConfig[0] field expects a pointer to DMA configuration for -* data endpoint 1, the dmaConfig[1] field pointer to DMA configuration +* to allow the USBFS driver to use DMA channels for used endpoints. +* The dmaConfig[0] field expects a pointer to the DMA configuration for +* data endpoint 1, the dmaConfig[1] field pointer to the DMA configuration * for data endpoint 2, and so on up to data endpoint 8. -* The code example below provides initialized USBFS driver configuration -* structure which use endpoint 1: +* The code example below provides an initialized USBFS driver configuration +* structure which uses endpoint 1: * -* \snippet usbfs/1.0/snippet/main.c snipped_Cy_USBFS_Dev_Drv_CfgDma +* \snippet usbfs/snippet/main.c snipped_Cy_USBFS_Dev_Drv_CfgDma * * * \ref CY_USBFS_DEV_DRV_EP_MANAGEMENT_DMA_AUTO \n -* DMA Automatic mode needs the similar DMA channels configuration as described +* DMA Automatic mode needs a DMA channels configuration similar to the described * above. But it also requires one more DMA descriptor for each DMA channel and -* DMA output trigger multiplexer. Find more information about trigger multiplexer -* in the \ref group_usbfs_dev_drv_dma section. -* The code example below provides initialized USBFS driver DMA configuration +* DMA output trigger multiplexer. Refer to the \ref group_usbfs_dev_drv_dma section, +* for more detail about the trigger multiplexer . +* The code example below provides an initialized USBFS driver DMA configuration * structure: * -* \snippet usbfs/1.0/snippet/main.c snipped_Cy_USBFS_Dev_Drv_CfgDmaAuto_DmaInit +* \snippet usbfs/snippet/main.c snipped_Cy_USBFS_Dev_Drv_CfgDmaAuto_DmaInit * * The driver requires a buffer for data endpoints to operate. This buffer must be * allocated by the user. The buffer size is equal to the sum of all used * endpoints maximum packet sizes. If an endpoint belongs to more than * one alternate setting, select the greatest maximum packet size for this * endpoint. The driver configuration structure \ref cy_stc_usbfs_dev_drv_config_t -* parameters have epBuffer and epBufferSize to pass the buffer to the driver. +* parameters epBuffer and epBufferSize pass the buffer to the driver. * -* The code example below provides initialized USBFS driver configuration +* The code example below provides an initialized USBFS driver configuration * structure that uses data endpoint 1 with a maximum packet size of 63 bytes and * set 16-bit access: * -* \snippet usbfs/1.0/snippet/main.c snipped_Cy_USBFS_Dev_Drv_CfgDmaAuto +* \snippet usbfs/snippet/main.c snipped_Cy_USBFS_Dev_Drv_CfgDmaAuto * * * \note @@ -170,15 +170,15 @@ * the IMO must be trimmed with USB SOF signal. Therefore, the driver * \ref Cy_USBFS_Dev_Drv_Init function enables the IMO trim from USB. * -* * Divided Clk_Peri clock (PCLK_USB_CLOCK_DEV_BRS) equal to 100 kHz, which is +* * Divided Clk_Peri clock (PCLK_USB_CLOCK_DEV_BRS) equal to 100 kHz * used to detect a Bus Reset event. Use one of the 8-bit or 16-bit dividers * to provide required clock frequency. * -* The code example below shows connection source path 1 +* The code example below shows the connection source path 1 * (which expected provide 48 MHz -/+ 0.25% clock) to Clk_HF3 and Bus Reset clock * (Clk_Peri assumed to be 50 MHz): * -* \snippet usbfs/1.0/snippet/main.c snipped_Cy_USBFS_Dev_Drv_ClockInit +* \snippet usbfs/snippet/main.c snipped_Cy_USBFS_Dev_Drv_ClockInit * * Refer to \ref group_sysclk driver API for more detail about clock * configuration. @@ -187,41 +187,40 @@ * \subsection group_usbfs_dev_drv_dma Assign and Route DMA Channels ******************************************************************************** * -* The USBFS driver requires the DMA controller to operate in DMA Manual and Automatic modes. +* The USBFS driver requires a DMA controller to operate in DMA Manual and Automatic modes. * The USB hardware block supports the DMA request and feedback lines for each -* data endpoint. Therefore, up to eight DMA channels are needed to service eight data -* endpoints. -* The connection between the USB block and the DMA channels is established using the trigger +* data endpoint. Therefore, up to eight DMA channels serve eight data endpoints. +* The connection between the USB block and the DMA channels is set using the trigger * muxes infrastructure. The USB block output DMA request line is connected to * the DMA channel trigger input. This allows the USB block to request a DMA transfer. * The DMA completion output is connected to the USB block burst end input. -* This allows the USB block get notification that a DMA transfer has been completed -* and next DMA request can be sent. The USBFS driver DMA configuration +* This allows the USB block to get notification that a DMA transfer has been completed +* and a next DMA request can be sent. The USBFS driver DMA configuration * structure requires the outTrigMux field to provide the trigger mux that * performs DMA completion and USB block burst end connection. * -* Refer to \ref group_trigmux to get more information about routing capabilities. +* Refer to \ref group_trigmux for more detail on the routing capabilities. * -* The code examples below shows connection DMA channel and USB block and define -* for outTrigMux field initialization for CY8C6xx6 or CY8C6xx7 devices. +* The code examples below shows a connection DMA channel and USB block and the define +* for outTrigMux field initialization for the CY8C6xx6 or CY8C6xx7 devices. * -* \snippet usbfs/1.0/snippet/main.c snipped_Cy_USBFS_Dev_Drv_DmaConnect +* \snippet usbfs/snippet/main.c snipped_Cy_USBFS_Dev_Drv_DmaConnect * ******************************************************************************** * \subsection group_usbfs_dev_drv_intr Configure Interrupts ******************************************************************************** * * The interrupts are mandatory for the USBFS driver operation. -* The USBFS block provides multiple interrupt sources, which can be assigned to +* The USBFS block provides multiple interrupt sources to be assigned to * trigger one of the three interrupts: Low, Medium, or High. This allows to -* assign different priority for interrupt sources handling. -* The \ref cy_stc_usbfs_dev_drv_config_t structure provides field -* intrLevelSel that initializes the INTR_LVL_SEL -* register that configures to which interrupt is triggered by interrupt source. +* assign different priority to the interrupt sources handling. +* The \ref cy_stc_usbfs_dev_drv_config_t structure provides the +* intrLevelSel field which initializes the INTR_LVL_SEL +* register. This register configures which interrupt the interrupt source will trigger. * * \note * The interrupt name (Low, Medium, or High) does not specify the interrupt -* priority. The interrupt priority is configured in the NVIC. +* priority. The interrupt priority is configured in NVIC. * * The recommended/default configuration is: * * Interrupt Low: Bus Reset, Control Endpoint and SOF. @@ -230,7 +229,7 @@ * * However, the final configuration must be defined by the application. * -* \snippet usbfs/1.0/snippet/main.c snipped_Cy_USBFS_Dev_Drv_UserLvlSel +* \snippet usbfs/snippet/main.c snipped_Cy_USBFS_Dev_Drv_UserLvlSel * * The \ref Cy_USBFS_Dev_Drv_Interrupt function must be called in the interrupt * handler for the selected USB block instance. Note that @@ -240,13 +239,12 @@ * * \ref Cy_USBFS_Dev_Drv_GetInterruptCauseMed * * \ref Cy_USBFS_Dev_Drv_GetInterruptCauseLo * -* \snippet usbfs/1.0/snippet/main.c snipped_Cy_USBFS_Dev_Drv_IntrHandlers +* \snippet usbfs/snippet/main.c snipped_Cy_USBFS_Dev_Drv_IntrHandlers * * Finally, the interrupts must be configured and interrupt handler routines -* hooked up to NVIC. The code below assigns interrupt priorities accordingly -* to interrupt names: High interrupt has the greater priority than Low and -* Medium interrupts, the Medium interrupt has the greater priority that -* Low interrupt and Low interrupt has lowest priority among USBFS interrupts. +* hook up to NVIC. The code below assigns the interrupt priorities accordingly +* to interrupt names. The priorities among the USBFS interrupts are as follows: +* High - the greatest; Medium - the middle; Low - the lowest. * * \note * For proper operation in Manual DMA mode (Mode 2) the Arbiter interrupt source @@ -254,17 +252,17 @@ * triggered by Data Endpoint 1-8 Completion interrupt sources. \n * For Automatic DMA mode (Mode 3) the rule above is recommend to follow. * -* \snippet usbfs/1.0/snippet/main.c snipped_Cy_USBFS_Dev_Drv_IntrCfg -* \snippet usbfs/1.0/snippet/main.c snipped_Cy_USBFS_Dev_Drv_IntrCfgHook +* \snippet usbfs/snippet/main.c snipped_Cy_USBFS_Dev_Drv_IntrCfg +* \snippet usbfs/snippet/main.c snipped_Cy_USBFS_Dev_Drv_IntrCfgHook * ******************************************************************************** * \section group_usbfs_dev_drv_ep_management Endpoint Buffer Management Modes ******************************************************************************** * * The USBFS hardware block supports three endpoint buffer management modes: -* CPU (No DMA) mode (Mode 1), Manual DMA mode (Mode 2) and Automatic DMA mode (Mode 3). +* CPU (No DMA) mode (Mode 1), Manual DMA mode (Mode 2), and Automatic DMA mode (Mode 3). * These modes are listed using enum \ref cy_en_usbfs_dev_drv_ep_management_mode_t. -* The following sub-sections provide more information about endpoint buffer +* The following sub-sections provide more information about the endpoint buffer * management. * ******************************************************************************** @@ -290,18 +288,18 @@ * * * \ref group_usbfs_dev_drv_ep_management_mode3 * Each data endpoint consumes 32 bytes in the hardware buffer (if all eight -* endpoints are used, consumed buffer space is 32 * 8 = 256 byte). -* This buffer is called the dedicated endpoint buffer. It acts as an endpoint +* endpoints are used, the consumed buffer space is 32 * 8 = 256 byte). +* This buffer is called "dedicated endpoint buffer". It acts as an endpoint * FIFO. The remaining space (256 bytes, if all eight endpoints are * used) in the hardware buffer is used by any endpoint that currently -* communicates. This part of the buffer is called the common area. This hardware -* buffer configuration gives sufficient dedicated buffer size for each used +* communicates. This part of the buffer is called "common area". This hardware +* buffer configuration gives a sufficient dedicated buffer size for each used * endpoint and common area for operation. The total space consumed by all -* endpoints is not restricted by the size of hardware buffer. +* endpoints is not restricted by the size of the hardware buffer. * * To access the hardware buffer, the endpoint data register is read or written by -* the CPU or DMA. On each read or write, the buffer pointers are updated to access -* the next data element. +* CPU or DMA. On each read or write, buffer pointers are updated to access +* a next data element. * ******************************************************************************** * \subsection group_usbfs_dev_drv_ep_management_buf_access Hardware Buffer Access @@ -313,31 +311,31 @@ * by the epAccess field of the driver configuration structure * \ref cy_stc_usbfs_dev_drv_config_t. * The endpoint hardware buffer and SRAM buffer must be allocated using the -* rules below when 16-bit access is used: -* * Buffer size must be even. If endpoint maximum packet size is odd +* rules below when the 16-bit access is used: +* * The buffer size must be even. If the endpoint maximum packet size is odd * the allocated buffer size must be equal to (maximum packet size + 1). -* * Buffer must be aligned to 2-byte boundary. +* * The buffer must be aligned to the 2-byte boundary. * * The driver provides the \ref CY_USBFS_DEV_DRV_ALLOC_ENDPOINT_BUFFER macro that -* applying rules above to allocate the SRAM buffer for endpoint. This macro +* applies the rules above to allocate the SRAM buffer for an endpoint. This macro * should be used by application to hide configuration differences. * However, in this case the application must ignore extra bytes in the buffer. -* Alternately, apply rules above only for 16-bits access type configuration. +* Alternately, apply the rules above only for the 16-bits access type configuration. * -* The driver firmware allocates endpoint hardware buffer (dividing hardware buffer +* The driver firmware allocates an endpoint hardware buffer (dividing hardware buffer * between utilized endpoints). Therefore, for \ref group_usbfs_dev_drv_ep_management_mode1 -* and \ref group_usbfs_dev_drv_ep_management_mode2, the endpoints whose -* maximum packet size is odd consumes an extra byte in the hardware buffer -* when 16-bit access is used. This is not applicable for \ref group_usbfs_dev_drv_ep_management_mode3 +* and \ref group_usbfs_dev_drv_ep_management_mode2, an endpoint whose +* maximum packet size is odd, consumes an extra byte in the hardware buffer +* when the 16-bit access is used. This is not applicable for \ref group_usbfs_dev_drv_ep_management_mode3 * because endpoints dedicated buffer are even and aligned. * * In addition, to operate in \ref group_usbfs_dev_drv_ep_management_mode3, * the driver needs an internal SRAM buffer for endpoints. The buffer size is a -* sum of all endpoint buffers. When 16-bit access is used, each endpoint buffer +* sum of all endpoint buffers. When the 16-bit access is used, each endpoint buffer * must be allocated using the rules above. The driver configuration structure * \ref cy_stc_usbfs_dev_drv_config_t has epBuffer and epBufferSize fields * to pass the allocated buffer to the driver. \n -* For example: the USB Device uses three data endpoint whose max packets are +* For example: the USB Device uses three data endpoints whose max packets are * 63 bytes, 63 bytes, and 8 bytes. The endpoints buffer for the driver must be * allocated as follows: * * 8-bits: uint8_t endpointsBuffer[63 + 63 + 8]; @@ -348,8 +346,8 @@ * \subsection group_usbfs_dev_drv_ep_management_mode1 CPU mode (Mode 1) ******************************************************************************** * -* The CPU handles data transfers between the user provided SRAM endpoint buffer -* and the USB block hardware buffer when \ref Cy_USBFS_Dev_Drv_ReadOutEndpoint +* CPU handles data transfers between the user-provided SRAM endpoint-buffer +* and the USB block hardware-buffer when \ref Cy_USBFS_Dev_Drv_ReadOutEndpoint * or \ref Cy_USBFS_Dev_Drv_LoadInEndpoint is called. * * \image html usbfs_ep_mngmnt_mode1.png @@ -358,8 +356,8 @@ * \subsection group_usbfs_dev_drv_ep_management_mode2 Manual DMA mode (Mode 2) ******************************************************************************** * -* The DMA handles data transfers between the user-provided SRAM endpoint -* buffer and the USB block hardware buffer. The DMA request is issued by the CPU +* DMA handles data transfers between the user-provided SRAM endpoint +* buffer and the USB block hardware buffer. The DMA request is issued by CPU * to execute a data transfer when \ref Cy_USBFS_Dev_Drv_ReadOutEndpoint or * \ref Cy_USBFS_Dev_Drv_LoadInEndpoint. * @@ -369,7 +367,7 @@ * \subsection group_usbfs_dev_drv_ep_management_mode3 Automatic DMA mode (Mode 3) ******************************************************************************** * -* The DMA handles data transfers between the driver SRAM endpoints buffer and +* DMA handles data transfers between the driver SRAM endpoints buffer and * the USB block hardware buffer. The USB block generates DMA requests * automatically. When USB transfer starts, the USB block triggers DMA * requests to transfer data between the driver endpoint buffer and the hardware @@ -381,7 +379,7 @@ * and does not issue new DMA request until it receives notification that the * previous DMA transfer completed. * When the \ref Cy_USBFS_Dev_Drv_ReadOutEndpoint or \ref Cy_USBFS_Dev_Drv_LoadInEndpoint -* function is called, the memcpy function is used to copy data from/into +* function is called, the memcpy function is used to copy data from/into the * driver endpoints buffer to the user-provided endpoint buffer. * The driver provides the \ref Cy_USBFS_Dev_Drv_OverwriteMemcpy function to * replace memcpy function by one that has been custom implemented (the DMA can be used for data copy). @@ -389,17 +387,17 @@ * \image html usbfs_ep_mngmnt_mode3.png * * \warning -* When the DMA is not capable of transferring data fast enough, the overflow or -* underflow interrupt triggers for impacted endpoint. This must never happen -* because this error condition indicates system failure with no recovery. -* To fix this, give the DMA channel assigned to this endpoint greater priority or -* increase the clock that the DMA operates. +* When DMA data transfer is not fast enough, an overflow or underflow +* interrupt triggers for the impacted endpoint. This must never happen +* because this error condition indicates a system failure with no recovery. +* To fix this, get the DMA channel assigned to this endpoint greater priority or +* increase the clock the DMA operates at. * ******************************************************************************** * \section group_usbfs_dev_drv_callbacks Callbacks Usage ******************************************************************************** * -* The driver provides following callbacks that can be used by the application: +* The driver provides the following callbacks that can be used by the application: * 1. Data endpoint 1-8 completion. This callback is invoked when the USB Host * completed communication with the endpoint. For IN endpoints, it means that data has * been read by the USB Host. For OUT endpoints, it means that data has been written @@ -414,7 +412,7 @@ * LPM power optimization. Call \ref Cy_USBFS_Dev_Drv_RegisterLpmCallback to * register callback function. * -* Also the driver provides callbacks for a Bus Reset event and Control Endpoint 0 +* Also, the driver provides callbacks for a Bus Reset event and Control Endpoint 0 * communication events (setup packet, in packet, out packet). But these * callbacks are used by middleware and must not be used by the application directly. * The middleware provides appropriate hooks for these events. @@ -425,20 +423,20 @@ * * The USB specification requires that no device supplies current on VBUS at its * upstream facing port at any time. To meet this requirement, the device must -* monitor for the presence or absence of VBUS and remove power from the Dp/Dm +* monitors for the presence or absence of VBUS and removes power from the Dp/Dm * pull-up resistor if VBUS is absent. The USBFS driver does not provide any * support of VBUS monitoring or detection. The application firmware must implement -* required functionality using a VDDUSB power pad or GPIO. Refer to the section -* Universal Serial Bus (USB) Device Mode sub-section VBUS Detection in the technical -* reference manual (TRM). +* the required functionality using a VDDUSB power pad or GPIO. Refer to the +* Universal Serial Bus (USB) Device Mode section, sub-section VBUS Detection +* in the technical reference manual (TRM). * -* Connect the VBUS through the resistive network when the +* Connect the VBUS through a resistive network when the * regular GPIO is used for VBUS detection to save the pin from voltage picks on VBUS, -* or use GPIO that is tolerant over voltage. An example schematic is shown below. +* or use GPIO tolerant over the voltage. An example schematic is shown below. * * \image html usbfs_vbus_connect_schem.png * -* \note The power is removed when the USB cable is removed from the USB Host +* \note Power is removed when the USB cable is removed from the USB Host * for bus-powered USB Device. Therefore, such a USB Device complies with * specification requirement above. * @@ -446,18 +444,18 @@ * \section group_usbfs_dev_drv_low_power Low Power Support ******************************************************************************** * -* The USBFS driver supports USB Suspend, Resume, and Remote Wakeup functionality. +* The USBFS driver supports the USB Suspend, Resume, and Remote Wakeup functionality. * This functionality is tightly related with the user application. The USBFS -* driver provides only the API interface, which helps the user achieve desired +* driver provides only the API interface which helps the user achieve the desired * low-power behavior. The additional processing is required from the user application. * The description of application processing is provided below. * -* Normally, the USB Host sends SOF packet every 1 ms (at full speed), and this is -* what keeps the USB Device awake. The USB Host suspends the USB Device by not +* Normally, the USB Host sends an SOF packet every 1 ms (at full speed), and this +* keeps the USB Device awake. The USB Host suspends the USB Device by not * sending anything to the USB Device for 3 ms. To recognize this condition, the bus * activity must be checked. This can be done using the \ref Cy_USBFS_Dev_Drv_CheckActivity * function or by monitoring the SOF interrupt. A suspended device may draw no -* more than 0.5 mA from VBUS. Therefore, put device into low-power +* more than 0.5 mA from VBUS. Therefore, put the device into low-power * mode to consume less current. * The \ref Cy_USBFS_Dev_Drv_Suspend function must be called before entering * low-power mode. When the USB Host wants to wake the device after a suspend, @@ -471,9 +469,9 @@ * enabled and IN endpoints must be loaded with data. * * \note After entering low-power mode, the data which was left in the IN or OUT -* endpoint buffers is not restored after device wakes up and is lost. Therefore, -* it must be stored in the SRAM for OUT endpoint or read by the Host for IN -* endpoint before entering low-power mode. +* endpoint buffers is not restored after the device's wake-up and is lost. +* Therefore, it must be stored in the SRAM for OUT endpoint or read by the Host for +* the IN endpoint before entering Low-power mode. * * If the USB Device supports remote wakeup functionality, the application has * to use middleware function Cy_USB_Dev_IsRemoteWakeupEnabled to determine whether @@ -519,21 +517,21 @@ * * \image html usbfs_lpm_responses.png * -* After USB Device is initialized the LPM transaction are to acknowledged (ACKed) -* meaning that device is ready to enter requested low-power mode. To override this +* After USB Device is initialized, the LPM transaction is to be acknowledged (ACKed) +* meaning that the device is ready to enter the requested low-power mode. To override this * behavior, use \ref Cy_USBFS_Dev_Drv_Lpm_SetResponse. \n * -* The USB block provides an interrupt source to define that LPM transaction was +* The USB block provides an interrupt source to define that an LPM transaction was * received and acknowledged (ACKed). Use the \ref Cy_USBFS_Dev_Drv_RegisterLpmCallback -* function to register application level callback function to service the LPM +* function to register the application level callback function to serve the LPM * transaction. The callback function can notify the application about an LPM transaction * and can use \ref Cy_USBFS_Dev_Drv_Lpm_GetBeslValue read to read Best Effort Service * Latency (BESL) values provided as part of an LPM transaction. The BESL value * indicates the amount of time from the start of a resume to when the USB Host * attempts to begin issuing transactions to the USB Device. The * application must use the value BESL to decide which low-power mode is entered -* to meet wakeup timing. The LPM transaction also contains the field that allows -* remote wake up. Use \ref Cy_USBFS_Dev_Drv_Lpm_RemoteWakeUpAllowed to get its +* to meet wakeup timing. The LPM transaction also contains the field that allows a +* remote to wake up. Use \ref Cy_USBFS_Dev_Drv_Lpm_RemoteWakeUpAllowed to get its * value. * * LPM related USB 2.0 Extension Descriptor provides attributes fields named @@ -543,18 +541,18 @@ * expected use is the baseline BESL value communicates a nominal power savings * design point and the deep BESL value communicates a significant power saving * design point. -* For example when the received BESL is less than baseline BESL, leave the device in the +* For example, when the received BESL is less than baseline BESL, leave the device in * Active mode. When it is between baseline BESL and deep BESL, put the device into -* the Deep Sleep mode. When it is greater than deep BESL, put the device into +* Deep Sleep mode. When it is greater than deep BESL, put the device into * Hibernate mode. * * \note -* The driver implements the USB Full-Speed device which does not support LPM +* The driver implements the USB Full-Speed device which does not support the LPM * NYET response. * * \note * The device will restart after Hibernate mode and the USB Device must -* be initialized at the application level. Call initialization functions +* be initialized at the application level. Call the initialization functions * instead of \ref Cy_USBFS_Dev_Drv_Resume. The application must ensure that * the device will resume within the time defined in the BESL value of LPM request. * @@ -562,8 +560,8 @@ * \section group_usbfs_drv_more_information More Information ******************************************************************************** * -* For more information on the USB Full-Speed Device peripheral, refer to the -* section Universal Serial Bus (USB) Device Mode in technical reference +* For more detail on the USB Full-Speed Device peripheral, refer to the +* section Universal Serial Bus (USB) Device Mode in the technical reference * manual (TRM). * ******************************************************************************** @@ -595,11 +593,11 @@ * A cast shall not be performed that removes any const or volatile * qualification from the type addressed by a pointer. -* 1. The register access macros cast base pointers to USBFS peripheral -* registers losing const qualification. Despite the qualification being -* lost, the driver ensures proper registers access. +* 1. The register access-macros cast base-pointers to the USBFS peripheral +* registers lose the const qualification. Despite the qualification being +* lost, the driver ensures the proper registers access. * 2. The volatile qualification is lost when a register address is passed -* as source or destination to the DMA channel. This does not cause any +* as a source or destination to the DMA channel. This does not cause any * negative impact because the DMA does not optimize any memory access. *
A pointer parameter in a function prototype should be declared as * pointer to const if the pointer is not used to modify the addressed * object.The middleware and USBFS driver defines general function -* prototypes and pointers to function types but the function's -* implementation depends on configuration. Therefore, -* some functions' implementations require parameters to be pointer to +* The middleware and USBFS driver define the general function +* prototypes and pointers to the function types but the function's +* implementation depends on the configuration. Therefore, +* some functions' implementations require parameters to be a pointer to * const but this is not met because of the generalized implementation * approach.
* * -* +* +* +* +* +* +* * *
VersionChangesReason for Change
1.102.0The list of changes to support the MBED-OS USB Device stack is provided below: +* - Changed the processing of the control transfers. +* - Updated the endpoint 0 service functions to update the endpoint 0 registers +* before the function returns. +* - Moved the set-device-address processing into the driver from the middleware. +* - Changed the flow to configure endpoints after configuration change: +* unconfigure the device or remove all endpoints, add endpoints, configure +* the device. Updated the functions: +* \ref Cy_USBFS_Dev_Drv_UnConfigureDevice, \ref Cy_USBFS_Dev_Drv_AddEndpoint +* and \ref Cy_USBFS_Dev_Drv_ConfigDevice. +* Removed the Cy_USBFS_Dev_Drv_ConfigDeviceComplete function because it is no needed anymore. +* - Added the functions: \ref Cy_USBFS_Dev_Drv_Ep0ReadResult(), \ref Cy_USBFS_Dev_Drv_SetAddress() +* and \ref Cy_USBFS_Dev_Drv_GetEp0MaxPacket(). +* - Changed the function signature \ref Cy_USBFS_Dev_Drv_Ep0Stall(). +* - Obsolete function Cy_USBFS_Dev_Drv_GetEndpointStallState; the \ref +* Cy_USBFS_Dev_Drv_GetEndpointState() updated to be used instead of the obsolete function. +* - Reduced the time required to complete abort operation in function \ref Cy_USBFS_Dev_Drv_Abort. +* Obsolete function Cy_USBFS_Dev_Drv_AbortComplete because entire abort operation is handled by +* \ref Cy_USBFS_Dev_Drv_Abort. +* - Added the endpoint address argument to the \ref cy_cb_usbfs_dev_drv_ep_callback_t to simplify +* endpoint transfer complete event processing for the MBED-OS USB Device stack. +* Updated the driver to support the MBED-OS USB Device stack and Cypress +* USB Device middleware.
1.10Fixed the \ref Cy_USBFS_Dev_Drv_Disable function to not disable DMA * in CPU mode.Calling this function triggers assert because DMA for endpoints is not @@ -699,10 +724,10 @@ extern "C" { */ /** USBFS Driver major version */ -#define CY_USBFS_VERSION_MAJOR (1) +#define CY_USBFS_VERSION_MAJOR (2) /** USBFS Driver minor version */ -#define CY_USBFS_VERSION_MINOR (10) +#define CY_USBFS_VERSION_MINOR (0) /** USBFS Driver identifier */ #define CY_USBFS_ID CY_PDL_DRV_ID(0x3BU) @@ -729,10 +754,10 @@ typedef enum /** Operation completed successfully */ CY_USBFS_DEV_DRV_SUCCESS = 0U, - /** One or more input parameters are invalid */ + /** One or more input parameters are invalid */ CY_USBFS_DEV_DRV_BAD_PARAM = (CY_USBFS_ID | CY_PDL_STATUS_ERROR | CY_USBFS_DEV_DRV_STATUS_CODE | 1U), - /** There is not enough space in the buffer to be allocated for endpoint (hardware or RAM) */ + /** There is not enough space in the buffer to be allocated for the endpoint (hardware or RAM) */ CY_USBFS_DEV_DRV_BUF_ALLOC_FAILED = (CY_USBFS_ID | CY_PDL_STATUS_ERROR | CY_USBFS_DEV_DRV_STATUS_CODE | 2U), /** Failure during DMA configuration */ @@ -741,12 +766,12 @@ typedef enum /** Timeout during dynamic reconfiguration */ CY_USBFS_DEV_DRV_EP_DYN_RECONFIG_TIMEOUT = (CY_USBFS_ID | CY_PDL_STATUS_ERROR | CY_USBFS_DEV_DRV_STATUS_CODE | 4U), - /** Timeout during execution of the DMA read request for OUT endpoint + /** Timeout during execution of the DMA read request for the OUT endpoint * (only applicable in \ref group_usbfs_dev_drv_ep_management_mode2) */ CY_USBFS_DEV_DRV_EP_DMA_READ_TIMEOUT = (CY_USBFS_ID | CY_PDL_STATUS_ERROR | CY_USBFS_DEV_DRV_STATUS_CODE | 5U), - /** Timeout during execution of the DMA read request for OUT endpoint + /** Timeout during execution of the DMA read request for the OUT endpoint * (only applicable in \ref group_usbfs_dev_drv_ep_management_mode2) */ CY_USBFS_DEV_DRV_EP_DMA_WRITE_TIMEOUT = (CY_USBFS_ID | CY_PDL_STATUS_ERROR | CY_USBFS_DEV_DRV_STATUS_CODE | 6U), @@ -757,17 +782,17 @@ typedef enum /** Data Endpoints Buffer Management Mode */ typedef enum { - /** The CPU manages data transfer between the hardware endpoints buffer + /** CPU manages a data transfer between the hardware endpoints buffer * and the user SRAM */ CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU = 0, - /** The DMA manages data transfer between the hardware endpoints buffer and + /** DMA manages data transfer between the hardware endpoints buffer and * the user SRAM */ CY_USBFS_DEV_DRV_EP_MANAGEMENT_DMA = 1, - /** The DMA automatically manages data transfer between the hardware endpoints + /** The DMA automatically manages a data transfer between the hardware endpoints * FIFO buffer and the user SRAM */ CY_USBFS_DEV_DRV_EP_MANAGEMENT_DMA_AUTO = 2, @@ -776,43 +801,43 @@ typedef enum /** Data Endpoint Register Access Type */ typedef enum { - CY_USBFS_DEV_DRV_USE_8_BITS_DR, /**< Use 8-bits registers to access data endpoints */ - CY_USBFS_DEV_DRV_USE_16_BITS_DR, /**< Use 16-bits registers to access data endpoints */ + CY_USBFS_DEV_DRV_USE_8_BITS_DR, /**< Use 8-bits registers to access the data endpoints */ + CY_USBFS_DEV_DRV_USE_16_BITS_DR, /**< Use 16-bits registers to access the data endpoints */ } cy_en_usbfs_dev_ep_access_t; /** Service Callback Events (this enumerated type is used by middleware) */ typedef enum { - CY_USB_DEV_BUS_RESET = 0U, /**< Callback hooked to bus reset interrupt */ - CY_USB_DEV_EP0_SETUP = 1U, /**< Callback hooked to endpoint 0 SETUP packet interrupt */ - CY_USB_DEV_EP0_IN = 2U, /**< Callback hooked to endpoint 0 IN packet interrupt */ - CY_USB_DEV_EP0_OUT = 3U, /**< Callback hooked to endpoint 0 OUT packet interrupt */ + CY_USB_DEV_BUS_RESET = 0U, /**< Callback hooked to the bus reset interrupt */ + CY_USB_DEV_EP0_SETUP = 1U, /**< Callback hooked to the endpoint 0 SETUP packet interrupt */ + CY_USB_DEV_EP0_IN = 2U, /**< Callback hooked to the endpoint 0 IN packet interrupt */ + CY_USB_DEV_EP0_OUT = 3U, /**< Callback hooked to the endpoint 0 OUT packet interrupt */ } cy_en_usb_dev_service_cb_t; /** Callback Sources */ typedef enum { - CY_USBFS_DEV_DRV_EP1 = 0U, /**< Callback hooked to Data Endpoint 1 completion interrupt */ - CY_USBFS_DEV_DRV_EP2 = 1U, /**< Callback hooked to Data Endpoint 2 completion interrupt */ - CY_USBFS_DEV_DRV_EP3 = 2U, /**< Callback hooked to Data Endpoint 3 completion interrupt */ - CY_USBFS_DEV_DRV_EP4 = 3U, /**< Callback hooked to Data Endpoint 4 completion interrupt */ - CY_USBFS_DEV_DRV_EP5 = 4U, /**< Callback hooked to Data Endpoint 5 completion interrupt */ - CY_USBFS_DEV_DRV_EP6 = 5U, /**< Callback hooked to Data Endpoint 6 completion interrupt */ - CY_USBFS_DEV_DRV_EP7 = 6U, /**< Callback hooked to Data Endpoint 7 completion interrupt */ - CY_USBFS_DEV_DRV_EP8 = 7U, /**< Callback hooked to Data Endpoint 8 completion interrupt */ - CY_USBFS_DEV_DRV_SOF = 8U, /**< Callback hooked to SOF packet received interrupt */ - CY_USBFS_DEV_DRV_LPM = 9U, /**< Callback hooked to LPM request received interrupt */ + CY_USBFS_DEV_DRV_EP1 = 0U, /**< Callback hooked to the Data Endpoint 1 completion interrupt */ + CY_USBFS_DEV_DRV_EP2 = 1U, /**< Callback hooked to the Data Endpoint 2 completion interrupt */ + CY_USBFS_DEV_DRV_EP3 = 2U, /**< Callback hooked to the Data Endpoint 3 completion interrupt */ + CY_USBFS_DEV_DRV_EP4 = 3U, /**< Callback hooked to the Data Endpoint 4 completion interrupt */ + CY_USBFS_DEV_DRV_EP5 = 4U, /**< Callback hooked to the Data Endpoint 5 completion interrupt */ + CY_USBFS_DEV_DRV_EP6 = 5U, /**< Callback hooked to the Data Endpoint 6 completion interrupt */ + CY_USBFS_DEV_DRV_EP7 = 6U, /**< Callback hooked to the Data Endpoint 7 completion interrupt */ + CY_USBFS_DEV_DRV_EP8 = 7U, /**< Callback hooked to the Data Endpoint 8 completion interrupt */ + CY_USBFS_DEV_DRV_SOF = 8U, /**< Callback hooked to the SOF packet received interrupt */ + CY_USBFS_DEV_DRV_LPM = 9U, /**< Callback hooked to the LPM request received interrupt */ } cy_en_usbfs_dev_drv_cb_source_t; /** Data Endpoint States (this enumerated type is used by middleware) */ typedef enum { - CY_USB_DEV_EP_IDLE, /**< Endpoint is in idle state after configuration is set */ - CY_USB_DEV_EP_PENDING, /**< Transfer targeted to an endpoint is in progress */ - CY_USB_DEV_EP_COMPLETED, /**< Transfer targeted to an endpoint is completed */ - CY_USB_DEV_EP_STALLED, /**< Endpoint is stalled */ - CY_USB_DEV_EP_DISABLED, /**< Endpoint is disabled (not used in this configuration) */ - CY_USB_DEV_EP_INVALID, /**< Endpoint does not supported by the hardware */ + CY_USB_DEV_EP_IDLE, /**< The endpoint is in an idle state after the configuration is set */ + CY_USB_DEV_EP_PENDING, /**< The transfer targeted at an endpoint is in progress */ + CY_USB_DEV_EP_COMPLETED, /**< The transfer targeted at an endpoint is completed */ + CY_USB_DEV_EP_STALLED, /**< The endpoint is stalled */ + CY_USB_DEV_EP_DISABLED, /**< The endpoint is disabled (not used in this configuration) */ + CY_USB_DEV_EP_INVALID, /**< The endpoint is not supported by the hardware */ } cy_en_usb_dev_ep_state_t; /** USB Lines Control */ @@ -821,7 +846,7 @@ typedef enum CY_USBFS_DEV_DRV_FORCE_STATE_J = 0xA0U, /**< Force a J State onto the USB lines */ CY_USBFS_DEV_DRV_FORCE_STATE_K = 0x80U, /**< Force a K State onto the USB lines */ CY_USBFS_DEV_DRV_FORCE_STATE_SE0 = 0xC0U, /**< Force a Single Ended 0 onto the USB lines */ - CY_USBFS_DEV_DRV_FORCE_STATE_NONE = 0x00U /**< Return bus to SIE control */ + CY_USBFS_DEV_DRV_FORCE_STATE_NONE = 0x00U /**< Return the bus to the SIE control */ } cy_en_usbfs_dev_drv_force_bus_state_t; /** LPM (Link Power Management) Responses */ @@ -833,6 +858,17 @@ typedef enum /** The next LPM request will be responded with ACK */ CY_USBFS_DEV_DRV_LPM_REQ_ACK = 0x1U, } cy_en_usbfs_dev_drv_lpm_req_t; + +/** USB Control EP0 transfer state */ +typedef enum +{ + CY_USBFS_DEV_DRV_EP0_CTRL_STATE_IDLE, + CY_USBFS_DEV_DRV_EP0_CTRL_STATE_SETUP, + CY_USBFS_DEV_DRV_EP0_CTRL_STATE_DATA, + CY_USBFS_DEV_DRV_EP0_CTRL_STATE_STATUS_IN, + CY_USBFS_DEV_DRV_EP0_CTRL_STATE_STATUS_OUT, +} cy_en_usbfs_dev_drv_ep0_ctrl_state_t; + /** \} group_usbfs_dev_drv_enums */ @@ -848,13 +884,13 @@ typedef enum /** Data Endpoint Configuration Structure */ typedef struct { - bool enableEndpoint; /**< Defines if endpoint becomes active after configuration */ - bool allocBuffer; /**< Defines if buffer allocation is need for endpoint */ - uint16_t maxPacketSize; /**< Endpoint max packet size */ - uint16_t bufferSize; /**< Endpoint buffer size (the biggest max packet size + bool enableEndpoint; /**< Defines if the endpoint becomes active after configuration */ + bool allocBuffer; /**< Defines if the endpoint needs buffer allocation */ + uint16_t maxPacketSize; /**< The endpoint max packet size */ + uint16_t bufferSize; /**< The endpoint buffer size (the biggest max packet size across all alternate for this endpoint) */ - uint8_t endpointAddr; /**< Endpoint address (number plus direction bit) */ - uint8_t attributes; /**< Endpoint attributes */ + uint8_t endpointAddr; /**< The endpoint address (number plus direction bit) */ + uint8_t attributes; /**< The endpoint attributes */ } cy_stc_usb_dev_ep_config_t; /** @@ -876,6 +912,7 @@ typedef void (* cy_cb_usbfs_dev_drv_callback_t)(USBFS_Type *base, * completion event. */ typedef void (* cy_cb_usbfs_dev_drv_ep_callback_t)(USBFS_Type *base, + uint32_t endpointAddr, uint32_t errorType, struct cy_stc_usbfs_dev_drv_context *context); @@ -934,10 +971,10 @@ typedef struct */ uint32_t outTrigMux; - /** Pointer to the 1st allocated DMA descriptor (required for DMA operation) */ + /** The pointer to the 1st allocated DMA descriptor (required for DMA operation) */ cy_stc_dma_descriptor_t *descr0; - /** Pointer to the 2nd allocated DMA descriptor (required when mode is + /** The pointer to the 2nd allocated DMA descriptor (required when mode is * \ref CY_USBFS_DEV_DRV_EP_MANAGEMENT_DMA_AUTO) */ cy_stc_dma_descriptor_t *descr1; @@ -951,26 +988,26 @@ typedef struct cy_stc_usbfs_dev_drv_config cy_en_usbfs_dev_drv_ep_management_mode_t mode; /** DMA channels configuration for the endpoints. - * Only DMA channels for active endpoints must be configured. Provide NULL + * Only DMChannels for active endpoints must be configured. Provide NULL * pointer if endpoint is not used. Applicable when \ref mode is * \ref CY_USBFS_DEV_DRV_EP_MANAGEMENT_DMA or \ref CY_USBFS_DEV_DRV_EP_MANAGEMENT_DMA_AUTO. */ const cy_stc_usbfs_dev_drv_dma_config_t *dmaConfig[CY_USBFS_DEV_DRV_NUM_EPS_MAX]; /** - * Pointer to the buffer allocated for OUT endpoints (applicable only when \ref mode + * The pointer to the buffer allocated for the OUT endpoints (applicable only when \ref mode * is \ref CY_USBFS_DEV_DRV_EP_MANAGEMENT_DMA_AUTO) */ - uint8_t *epBuffer; + uint8_t *epBuffer; /** - * The size of the buffer for OUT endpoints (applicable only when \ref mode + * The size of the buffer for the OUT endpoints (applicable only when \ref mode * is \ref CY_USBFS_DEV_DRV_EP_MANAGEMENT_DMA_AUTO) */ uint16_t epBufferSize; - /** Mask that assigns interrupt sources to trigger: Low, Medium, or High interrupt. - * Use macros provided in group_usbfs_dev_drv_macros_intr_level to initialize + /** The mask that assigns interrupt sources to trigger: Low, Medium, or High interrupt. + * Use the macros provided in group_usbfs_dev_drv_macros_intr_level to initialize the * intrLevelSel mask. */ uint32_t intrLevelSel; @@ -990,41 +1027,65 @@ typedef struct volatile uint8_t toggle; /**< Toggle bit in SIE_EP_CNT1 register */ volatile uint8_t sieMode; /**< SIE mode to arm endpoint on the bus */ - uint8_t *buffer; /**< Pointer to the buffer */ + uint8_t *buffer; /**< The pointer to the buffer */ volatile uint16_t bufferSize; /**< Endpoint buffer size */ volatile uint16_t startBuf; /**< Start of the buffer */ - volatile bool isPending; /**< Save pending state before stall endpoint */ + volatile bool isPending; /**< Save the pending state before stall endpoint */ volatile cy_en_usb_dev_ep_state_t state; /**< Endpoint state */ - /** Complete event notification callback */ + /** Completes an event notification callback */ cy_cb_usbfs_dev_drv_ep_callback_t epComplete; - DW_Type *base; /**< Pointer to the DMA base */ + DW_Type *base; /**< The pointer to the DMA base */ uint32_t chNum; /**< DMA Channel number */ uint32_t outTrigMux; /**< Out trigger mux for DMA channel number */ - cy_stc_dma_descriptor_t* descr0; /**< Pointer to the descriptor 0 */ - cy_stc_dma_descriptor_t* descr1; /**< Pointer to the descriptor 1 */ + cy_stc_dma_descriptor_t* descr0; /**< The pointer to the descriptor 0 */ + cy_stc_dma_descriptor_t* descr1; /**< The pointer to the descriptor 1 */ - cy_fn_usbfs_dev_drv_memcpy_ptr_t copyData; /**< Pointer to user memcpy function */ + cy_fn_usbfs_dev_drv_memcpy_ptr_t copyData; /**< The pointer to the user memcpy function */ } cy_stc_usbfs_dev_drv_endpoint_data_t; /** \endcond */ /** USBFS Device context structure. -* All fields for the context structure are internal. Firmware never reads or -* writes these values. Firmware allocates the structure and provides the -* address of the structure to the middleware in HID function calls. Firmware +* All fields for the context structure are internal. The firmware never reads or +* writes these values. The firmware allocates a structure and provides the +* address of the structure to the middleware in HID function calls. The firmware * must ensure that the defined instance of this structure remains in scope while * the middleware is in use. */ typedef struct cy_stc_usbfs_dev_drv_context { /** \cond INTERNAL */ + /** Stores the Endpoint 0 buffer to put the read operation results */ + uint8_t *ep0Buffer; + + /** Stores the Endpoint 0 buffer size */ + uint8_t ep0BufferSize; + + /** Endpoint 0 data toggle bit: 0 or USBFS_USBDEV_EP0_CNT_DATA_TOGGLE_Msk */ + uint8_t ep0DataToggle; + + /** Active endpoint mask */ + uint8_t activeEpMask; + + /** The device address to set */ + uint8_t address; + + /** Defines the list of endpoints that waits for abort completion */ + volatile uint8_t epAbortMask; + /** Endpoints management mode */ cy_en_usbfs_dev_drv_ep_management_mode_t mode; + /** Stores the control transfer state */ + cy_en_usbfs_dev_drv_ep0_ctrl_state_t ep0CtrlState; + + /* Status to set or not the device address after the status state of the control transfer */ + bool setAddress; + /** Defines which endpoint registers to use: 8-bits or 16-bits */ bool useReg16; @@ -1055,9 +1116,6 @@ typedef struct cy_stc_usbfs_dev_drv_context /** Pointer to readOutEndpoint function: depends on operation mode */ cy_fn_usbfs_dev_drv_read_ep_ptr_t readOutEndpoint; - uint32_t ep0ModeReg; /**< Endpoint 0 Mode register */ - uint32_t ep0CntReg; /**< Endpoint 0 Counter register */ - uint8_t *epSharedBuf; /**< Buffer for OUT endpoints */ uint16_t epSharedBufSize; /**< Buffer size */ @@ -1066,10 +1124,9 @@ typedef struct cy_stc_usbfs_dev_drv_context /** Stores endpoints information */ cy_stc_usbfs_dev_drv_endpoint_data_t epPool[CY_USBFS_DEV_DRV_NUM_EPS_MAX]; - /** Pointer to the device context structure */ + /** The pointer to the device context structure */ void *devConext; /** \endcond */ - } cy_stc_usbfs_dev_drv_context_t; /** \} group_usbfs_dev_drv_data_structures */ @@ -1081,7 +1138,7 @@ typedef struct cy_stc_usbfs_dev_drv_context /** * \addtogroup group_usbfs_dev_hal_functions_common * \{ -* The Initialization functions provide the API to begin USBFS driver operation +* The Initialization functions provide an API to begin the USBFS driver operation * (configure and enable) and to stop operation (disable and de-initialize). */ cy_en_usbfs_dev_drv_status_t Cy_USBFS_Dev_Drv_Init(USBFS_Type *base, @@ -1097,6 +1154,8 @@ void Cy_USBFS_Dev_Drv_Enable(USBFS_Type *base, void Cy_USBFS_Dev_Drv_Disable(USBFS_Type *base, cy_stc_usbfs_dev_drv_context_t *context); +__STATIC_INLINE void Cy_USBFS_Dev_Drv_SetAddress(USBFS_Type *base, uint8_t address, + cy_stc_usbfs_dev_drv_context_t *context); __STATIC_INLINE void Cy_USBFS_Dev_Drv_SetDeviceAddress(USBFS_Type *base, uint8_t address); __STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetDeviceAddress(USBFS_Type const *base); @@ -1110,9 +1169,6 @@ __STATIC_INLINE void* Cy_USBFS_Dev_Drv_GetDevContext(USBFS_Type const *base, void Cy_USBFS_Dev_Drv_ConfigDevice(USBFS_Type *base, cy_stc_usbfs_dev_drv_context_t *context); -void Cy_USBFS_Dev_Drv_ConfigDeviceComplete(USBFS_Type *base, - cy_stc_usbfs_dev_drv_context_t const *context); - void Cy_USBFS_Dev_Drv_UnConfigureDevice(USBFS_Type *base, cy_stc_usbfs_dev_drv_context_t *context); /** \} group_usbfs_dev_hal_functions_common */ @@ -1120,33 +1176,37 @@ void Cy_USBFS_Dev_Drv_UnConfigureDevice(USBFS_Type *base, /** * \addtogroup group_usbfs_dev_hal_functions_ep0_service * \{ -* The Endpoint 0 Service functions provides API to establish communication with +* The Endpoint 0 Service functions provide an API to establish communication with * the USB Host using control endpoint 0. */ void Cy_USBFS_Dev_Drv_Ep0GetSetup(USBFS_Type const *base, uint8_t *buffer, cy_stc_usbfs_dev_drv_context_t const *context); -uint32_t Cy_USBFS_Dev_Drv_Ep0Write(USBFS_Type *base, - uint8_t const *buffer, - uint32_t size, +uint32_t Cy_USBFS_Dev_Drv_Ep0Write(USBFS_Type *base, + uint8_t const *buffer, + uint32_t size, cy_stc_usbfs_dev_drv_context_t *context); -uint32_t Cy_USBFS_Dev_Drv_Ep0Read(USBFS_Type const *base, - uint8_t *buffer, - uint32_t size, - cy_stc_usbfs_dev_drv_context_t *context); +void Cy_USBFS_Dev_Drv_Ep0Read(USBFS_Type *base, + uint8_t *buffer, + uint32_t size, + cy_stc_usbfs_dev_drv_context_t *context); -__STATIC_INLINE void Cy_USBFS_Dev_Drv_Ep0Stall(USBFS_Type const *base, - cy_stc_usbfs_dev_drv_context_t *context); +uint32_t Cy_USBFS_Dev_Drv_Ep0ReadResult(USBFS_Type const *base, + cy_stc_usbfs_dev_drv_context_t *context); + +__STATIC_INLINE void Cy_USBFS_Dev_Drv_Ep0Stall(USBFS_Type *base); + +__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetEp0MaxPacket(USBFS_Type const *base); /** \} group_usbfs_dev_hal_functions_ep0_service */ /** * \addtogroup group_usbfs_dev_hal_functions_endpoint_config * \{ -* The Data Endpoint Configuration Functions provide the API to allocate and release -* hardware resources and override the memcpy function for data endpoints. +* The Data Endpoint Configuration Functions provide an API to allocate and release +* hardware resources and override the memcpy function for the data endpoints. */ __STATIC_INLINE cy_en_usbfs_dev_drv_status_t Cy_USBFS_Dev_Drv_AddEndpoint(USBFS_Type *base, cy_stc_usb_dev_ep_config_t const *config, @@ -1164,7 +1224,7 @@ __STATIC_INLINE void Cy_USBFS_Dev_Drv_OverwriteMemcpy(USBFS_Type const *base, /** * \addtogroup group_usbfs_dev_hal_functions_data_xfer -* The Data Endpoint Transfer functions provide the API to establish +* The Data Endpoint Transfer functions provide an API to establish * communication with the USB Host using data endpoint. * \{ */ @@ -1189,22 +1249,13 @@ __STATIC_INLINE cy_en_usbfs_dev_drv_status_t Cy_USBFS_Dev_Drv_ReadOutEndpoint(US uint32_t *actSize, cy_stc_usbfs_dev_drv_context_t *context); -cy_en_usb_dev_ep_state_t Cy_USBFS_Dev_Drv_Abort(USBFS_Type *base, - uint32_t endpoint, - cy_stc_usbfs_dev_drv_context_t const *context); - -cy_en_usbfs_dev_drv_status_t Cy_USBFS_Dev_Drv_AbortComplete(USBFS_Type *base, - uint32_t endpoint, - cy_stc_usbfs_dev_drv_context_t *context); +cy_en_usbfs_dev_drv_status_t Cy_USBFS_Dev_Drv_Abort(USBFS_Type *base, + uint32_t endpoint, + cy_stc_usbfs_dev_drv_context_t *context); __STATIC_INLINE bool Cy_USBFS_Dev_Drv_GetEndpointAckState(USBFS_Type const *base, uint32_t endpoint); __STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetEndpointCount (USBFS_Type const *base, uint32_t endpoint); - -__STATIC_INLINE cy_en_usb_dev_ep_state_t Cy_USBFS_Dev_Drv_GetEndpointStallState(USBFS_Type const *base, - uint32_t endpoint, - cy_stc_usbfs_dev_drv_context_t const *context); - cy_en_usbfs_dev_drv_status_t Cy_USBFS_Dev_Drv_StallEndpoint(USBFS_Type *base, uint32_t endpoint, cy_stc_usbfs_dev_drv_context_t *context); @@ -1217,7 +1268,7 @@ cy_en_usbfs_dev_drv_status_t Cy_USBFS_Dev_Drv_UnStallEndpoint(USBFS_Type *base, /** * \addtogroup group_usbfs_dev_drv_functions_interrupts -* The Functions Interrupt functions provide the API to register callbacks +* The Functions Interrupt functions provide an API to register callbacks * for interrupt events provided by the USB block, interrupt handler, and configuration functions. * \{ */ @@ -1254,7 +1305,7 @@ __STATIC_INLINE void Cy_USBFS_Dev_Drv_EnableEp0Interrupt(USBFS_Type *base); /** * \addtogroup group_usbfs_dev_drv_functions_low_power -* The Low Power functions provide the API to implement Low Power callback on application level. +* The Low-power functions provide an API to implement Low-power callback at the application level. * \{ */ __STATIC_INLINE bool Cy_USBFS_Dev_Drv_CheckActivity(USBFS_Type *base); @@ -1265,7 +1316,7 @@ __STATIC_INLINE void Cy_USBFS_Dev_Drv_Force (USBFS_Type *base, cy_en_usbf /** * \addtogroup group_usbfs_dev_drv_functions_lpm -* The LPM functions provide the API to use the LPM feature available in the USB block. +* The LPM functions provide an API to use the LPM feature available in the USB block. * \{ */ __STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_Lpm_GetBeslValue (USBFS_Type const *base); @@ -1283,12 +1334,11 @@ __STATIC_INLINE cy_en_usbfs_dev_drv_lpm_req_t Cy_USBFS_Dev_Drv_Lpm_GetResponse(U * \addtogroup group_usbfs_dev_drv_macros * \{ */ -/** Allocates static buffer for data endpoint. The size parameter must be a constant. -* The allocated buffer is aligned on a 2 byte boundary. An odd buffer size is -* converted to even consuming 1 extra byte. The application must discard this -* extra byte. This manipulation is needed to support different 8-bit and 16-bit -* hardware buffer access types in the driver (See section -* \ref group_usbfs_dev_drv_ep_management_buf_access for more information). +/** Allocates a static buffer for the data endpoint. The size parameter must be a constant. +* The allocated buffer is aligned to a 2-byte boundary. An odd buffer size is +* converted to even, consuming 1 extra byte. The application must discard this +* extra byte to support different 8-bit and 16-bit hardware buffer access types +* in the driver. For more detail, refer to \ref group_usbfs_dev_drv_ep_management_buf_access. */ #define CY_USBFS_DEV_DRV_ALLOC_ENDPOINT_BUFFER(buf, size) uint8_t buf[(0U != ((size) & 0x1U)) ? ((size) + 1U) : (size)] CY_ALIGN(2) /** \} group_usbfs_dev_drv_macros */ @@ -1297,40 +1347,40 @@ __STATIC_INLINE cy_en_usbfs_dev_drv_lpm_req_t Cy_USBFS_Dev_Drv_Lpm_GetResponse(U * \addtogroup group_usbfs_dev_drv_macros_intr_level * \{ */ -/** Interrupt source is assigned to trigger High interrupt */ +/** The interrupt source is assigned to a trigger High interrupt */ #define CY_USBFS_DEV_DRV_LVL_HIGH (0U) -/** Interrupt source is assigned to trigger Medium interrupt */ +/** The interrupt source is assigned to a trigger Medium interrupt */ #define CY_USBFS_DEV_DRV_LVL_MEDIUM (1U) -/** Interrupt source is assigned to trigger Low interrupt */ +/** The interrupt source is assigned to a trigger Low interrupt */ #define CY_USBFS_DEV_DRV_LVL_LOW (2U) -/** Assigns SOF interrupt source to trigger interrupt Low, Medium, or High */ +/** Assigns the SOF interrupt source to a trigger interrupt: Low, Medium, or High */ #define CY_USBFS_DEV_DRV_SET_SOF_LVL(level) _VAL2FLD(USBFS_USBLPM_INTR_LVL_SEL_SOF_LVL_SEL, level) -/** Assigns Bus Reset interrupt source to trigger interrupt Low, Medium, or High */ +/** Assigns the Bus Reset interrupt source to a trigger interrupt: Low, Medium, or High */ #define CY_USBFS_DEV_DRV_SET_BUS_RESET_LVL(level) _VAL2FLD(USBFS_USBLPM_INTR_LVL_SEL_BUS_RESET_LVL_SEL, level) -/** Assigns Endpoint 0 interrupt source to trigger interrupt Low, Medium, or High */ +/** Assigns the Endpoint 0 interrupt source to a trigger interrupt Low, Medium, or High */ #define CY_USBFS_DEV_DRV_SET_EP0_LVL(level) _VAL2FLD(USBFS_USBLPM_INTR_LVL_SEL_EP0_LVL_SEL, level) -/** Assigns LPM interrupt source to trigger interrupt Low, Medium, or High */ +/** Assigns the LPM interrupt source to a trigger interrupt: Low, Medium, or High */ #define CY_USBFS_DEV_DRV_SET_LPM_LVL(level) _VAL2FLD(USBFS_USBLPM_INTR_LVL_SEL_LPM_LVL_SEL, level) -/** Assigns Resume interrupt source to trigger interrupt Low, Medium, or High */ +/** Assigns the Resume interrupt source to a trigger interrupt: Low, Medium, or High */ #define CY_USBFS_DEV_DRV_SET_RESUME_LVL(level) _VAL2FLD(USBFS_USBLPM_INTR_LVL_SEL_RESUME_LVL_SEL, level) -/** Assigns Arbiter interrupt source to trigger interrupt Low, Medium, or High */ +/** Assigns the Arbiter interrupt source to a trigger interrupt: Low, Medium, or High */ #define CY_USBFS_DEV_DRV_SET_ARB_EP_LVL(level) _VAL2FLD(USBFS_USBLPM_INTR_LVL_SEL_ARB_EP_LVL_SEL, level) -/** Assigns Endpoint 1 interrupt source to trigger interrupt Low, Medium, or High */ +/** Assigns the Endpoint 1 interrupt source to a trigger interrupt: Low, Medium, or High */ #define CY_USBFS_DEV_DRV_SET_EP1_LVL(level) _VAL2FLD(USBFS_USBLPM_INTR_LVL_SEL_EP1_LVL_SEL, level) -/** Assigns Endpoint 2 interrupt source to trigger interrupt Low, Medium, or High */ +/** Assigns the Endpoint 2 interrupt source to a trigger interrupt: Low, Medium, or High */ #define CY_USBFS_DEV_DRV_SET_EP2_LVL(level) _VAL2FLD(USBFS_USBLPM_INTR_LVL_SEL_EP2_LVL_SEL, level) -/** Assigns Endpoint 3 interrupt source to trigger interrupt Low, Medium, or High */ +/** Assigns the Endpoint 3 interrupt source to a trigger interrupt: Low, Medium, or High */ #define CY_USBFS_DEV_DRV_SET_EP3_LVL(level) _VAL2FLD(USBFS_USBLPM_INTR_LVL_SEL_EP3_LVL_SEL, level) -/** Assigns Endpoint 4 interrupt source to trigger interrupt Low, Medium, or High */ +/** Assigns the Endpoint 4 interrupt source to a trigger interrupt: Low, Medium, or High */ #define CY_USBFS_DEV_DRV_SET_EP4_LVL(level) _VAL2FLD(USBFS_USBLPM_INTR_LVL_SEL_EP4_LVL_SEL, level) -/** Assigns Endpoint 5 interrupt source to trigger interrupt Low, Medium, or High */ +/** Assigns the Endpoint 5 interrupt source to a trigger interrupt: Low, Medium, or High */ #define CY_USBFS_DEV_DRV_SET_EP5_LVL(level) _VAL2FLD(USBFS_USBLPM_INTR_LVL_SEL_EP5_LVL_SEL, level) -/** Assigns Endpoint 6 interrupt source to trigger interrupt Low, Medium, or High */ +/** Assigns the Endpoint 6 interrupt source to a trigger interrupt: Low, Medium, or High */ #define CY_USBFS_DEV_DRV_SET_EP6_LVL(level) _VAL2FLD(USBFS_USBLPM_INTR_LVL_SEL_EP6_LVL_SEL, level) -/** Assigns Endpoint 7 interrupt source to trigger interrupt Low, Medium, or High */ +/** Assigns the Endpoint 7 interrupt source to a trigger interrupt: Low, Medium, or High */ #define CY_USBFS_DEV_DRV_SET_EP7_LVL(level) _VAL2FLD(USBFS_USBLPM_INTR_LVL_SEL_EP7_LVL_SEL, level) -/** Assigns Endpoint 8 interrupt source to trigger interrupt Low, Medium, or High */ +/** Assigns the Endpoint 8 interrupt source to a trigger interrupt: Low, Medium, or High */ #define CY_USBFS_DEV_DRV_SET_EP8_LVL(level) _VAL2FLD(USBFS_USBLPM_INTR_LVL_SEL_EP8_LVL_SEL, level) /** \} group_usbfs_dev_drv_macros_intr_level */ @@ -1358,17 +1408,17 @@ __STATIC_INLINE cy_en_usbfs_dev_drv_lpm_req_t Cy_USBFS_Dev_Drv_Lpm_GetResponse(U * \{ */ /** -* Error occurred during USB transfer. -* For an IN transaction, this indicates a no response from HOST scenario. -* For an OUT transaction, this represents a PID or CRC error or bit-stuff error +* An error occurred during a USB transfer. +* For an IN transaction, this indicates a "no response" from the HOST scenario. +* For an OUT transaction, this represents a "PID or CRC error" or the bit-stuff error * scenario. */ #define CY_USBFS_DEV_ENDPOINT_TRANSFER_ERROR (0x1U) /** -* Data toggle bit remained the same. +* The data toggle bit remains the same. * The received OUT packet has the same data toggle bit that the previous -* packet had. This indicates that the Host retransmitted packet. +* packet had. This indicates that the Host retransmitted the packet. */ #define CY_USBFS_DEV_ENDPOINT_SAME_DATA_TOGGLE (0x2U) /** \} group_usbfs_dev_drv_macros_ep_xfer_err */ @@ -1379,7 +1429,7 @@ __STATIC_INLINE cy_en_usbfs_dev_drv_lpm_req_t Cy_USBFS_Dev_Drv_Lpm_GetResponse(U *******************************************************************************/ /** \cond INTERNAL */ -/* Start position of data endpoints SIE interrupt sources */ +/* The start position of the data endpoints SIE interrupt sources */ #define USBFS_USBLPM_INTR_CAUSE_LPM_INTR_Msk USBFS_USBLPM_INTR_CAUSE_HI_LPM_INTR_Msk #define USBFS_USBLPM_INTR_CAUSE_ARB_EP_INTR_Msk USBFS_USBLPM_INTR_CAUSE_HI_ARB_EP_INTR_Msk #define USBFS_USBLPM_INTR_CAUSE_EP0_INTR_Msk USBFS_USBLPM_INTR_CAUSE_HI_EP0_INTR_Msk @@ -1400,6 +1450,9 @@ __STATIC_INLINE cy_en_usbfs_dev_drv_lpm_req_t Cy_USBFS_Dev_Drv_Lpm_GetResponse(U #define CY_USBFS_DEV_DRV_IS_MODE_VALID(mode) (((mode) == CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU) || \ ((mode) == CY_USBFS_DEV_DRV_EP_MANAGEMENT_DMA) || \ ((mode) == CY_USBFS_DEV_DRV_EP_MANAGEMENT_DMA_AUTO)) + +/* Obsolete function */ +#define Cy_USBFS_Dev_Drv_GetEndpointStallState Cy_USBFS_Dev_Drv_GetEndpointState /** \endcond */ /** \} group_usbfs_drv_macros */ @@ -1412,11 +1465,42 @@ __STATIC_INLINE cy_en_usbfs_dev_drv_lpm_req_t Cy_USBFS_Dev_Drv_Lpm_GetResponse(U * \addtogroup group_usbfs_dev_hal_functions_common * \{ */ + +/******************************************************************************* +* Function Name: Cy_USBFS_Dev_Drv_SetAddress +****************************************************************************//** +* +* Posts a request to set the device address after the completion status stage of +* the control transfer. This function must be used if a higher level requests +* to set an address before the status stage of the control transfer. +* +* \param base +* The pointer to the USBFS instance. +* +* \param address +* The device address. +* +* \param context +* The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t +* allocated by the user. The structure is used during the USBFS Device +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_USBFS_Dev_Drv_SetAddress(USBFS_Type *base, uint8_t address, + cy_stc_usbfs_dev_drv_context_t *context) +{ + /* Stores the address to set later after the status stage of setup request completed */ + context->address = address; + context->setAddress = true; +} + + /******************************************************************************* * Function Name: Cy_USBFS_Dev_Drv_SetDeviceAddress ****************************************************************************//** * -* Sets the device address. +* Sets the device address (writes the address directly into the register). * * \param base * The pointer to the USBFS instance. @@ -1435,15 +1519,15 @@ __STATIC_INLINE void Cy_USBFS_Dev_Drv_SetDeviceAddress(USBFS_Type *base, uint8_t * Function Name: Cy_USBFS_Dev_Drv_GetDeviceAddress ****************************************************************************//** * -* Returns the device address. +* Returns the device address (reads the address directly from the register). * * \param base * The pointer to the USBFS instance. * * \return -* Device address. +* The device address. * The device address is assigned by the Host during device enumeration. -* Zero means that device address has not yet been assigned. +* Zero means that the device address is not assigned. * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetDeviceAddress(USBFS_Type const *base) @@ -1456,7 +1540,7 @@ __STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetDeviceAddress(USBFS_Type const *bas * Function Name: Cy_USBFS_Dev_Drv_SetDevContext ****************************************************************************//** * -* Stores pointer to the USB Device context in the driver context. +* Stores a pointer to the USB Device context in the driver context. * * \param base * The pointer to the USBFS instance @@ -1471,14 +1555,14 @@ __STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetDeviceAddress(USBFS_Type const *bas * modify anything in this structure. * * \note -* This function is intended to be used by USB Device middleware for operation. +* This function is intended for the USB Device middleware operation. * *******************************************************************************/ __STATIC_INLINE void Cy_USBFS_Dev_Drv_SetDevContext(USBFS_Type const *base, void *devContext, cy_stc_usbfs_dev_drv_context_t *context) { - /* Suppress a compiler warning about unused variables */ + /* Suppresses a compiler warning about unused variables. */ (void) base; context->devConext = devContext; @@ -1489,14 +1573,14 @@ __STATIC_INLINE void Cy_USBFS_Dev_Drv_SetDevContext(USBFS_Type const *base, * Function Name: Cy_USBFS_Dev_Drv_GetDevContext ****************************************************************************//** * -* Returns pointer to the USB Device context. +* Returns a pointer to the USB Device context. * * \param base * The pointer to the USBFS instance. * * \param context * The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t -* allocated by the user. The structure is used during the USBFS Device +* allocated by the user. The structure is used during USBFS Device * operation for internal configuration and data retention. The user must not * modify anything in this structure. * @@ -1504,13 +1588,13 @@ __STATIC_INLINE void Cy_USBFS_Dev_Drv_SetDevContext(USBFS_Type const *base, * The pointer to the USB Device context. * * \note -* This function is intended to be used by USB Device middleware for operation. +* This function is intended for the USB Device middleware operation. * *******************************************************************************/ __STATIC_INLINE void* Cy_USBFS_Dev_Drv_GetDevContext(USBFS_Type const *base, cy_stc_usbfs_dev_drv_context_t *context) { - /* Suppress a compiler warning about unused variables */ + /* Suppresses a compiler warning about unused variables */ (void) base; return (context->devConext); @@ -1528,8 +1612,8 @@ __STATIC_INLINE void* Cy_USBFS_Dev_Drv_GetDevContext(USBFS_Type const *base, * * Registers a callback function to notify about an SOF event in * \ref Cy_USBFS_Dev_Drv_Interrupt. The SOF interrupt source is enabled after -* registration. To remove callback function pass NULL as function pointer. -* When callback removed the interrupt source is disabled. +* registration. To remove callback function, pass NULL as the function pointer. +* When the callback is removed, the interrupt source is disabled. * * \param base * The pointer to the USBFS instance. @@ -1555,7 +1639,7 @@ __STATIC_INLINE void Cy_USBFS_Dev_Drv_RegisterSofCallback(USBFS_Type *base, context->cbSof = callback; - /* Enable/Disable SOF interrupt */ + /* Enables/Disables SOF interrupt */ mask = Cy_USBFS_Dev_Drv_GetSieInterruptMask(base); if (NULL != callback) @@ -1578,8 +1662,8 @@ __STATIC_INLINE void Cy_USBFS_Dev_Drv_RegisterSofCallback(USBFS_Type *base, * * Registers a callback function to notify about an LPM event in * \ref Cy_USBFS_Dev_Drv_Interrupt. The LPM interrupt source is enabled after -* registration. To remove the callback function, pass NULL as function pointer. -* When the callback has been removed, the interrupt source is disabled. +* registration. To remove the callback function, pass NULL as the function pointer. +* When the callback is removed, the interrupt source is disabled. * * \param base * The pointer to the USBFS instance. @@ -1594,7 +1678,7 @@ __STATIC_INLINE void Cy_USBFS_Dev_Drv_RegisterSofCallback(USBFS_Type *base, * modify anything in this structure. * * \note -* To remove the callback, pass NULL as the pointer to a callback function. +* To remove the callback, pass NULL as the pointer to the callback function. * *******************************************************************************/ __STATIC_INLINE void Cy_USBFS_Dev_Drv_RegisterLpmCallback(USBFS_Type *base, @@ -1606,7 +1690,7 @@ __STATIC_INLINE void Cy_USBFS_Dev_Drv_RegisterLpmCallback(USBFS_Type *base, context->cbLpm = callback; - /* Enable/Disable LPM interrupt source */ + /* Enables/Disables the LPM interrupt source */ mask = Cy_USBFS_Dev_Drv_GetSieInterruptMask(base); if (NULL != callback) @@ -1629,9 +1713,9 @@ __STATIC_INLINE void Cy_USBFS_Dev_Drv_RegisterLpmCallback(USBFS_Type *base, * * Registers a callback function to notify of an endpoint transfer completion * event in \ref Cy_USBFS_Dev_Drv_Interrupt. -* * IN endpoint - the Host read data from the endpoint and new data can be +* * IN endpoint - The Host read data from the endpoint and new data can be * loaded. -* * OUT endpoint - the Host wrote data into the endpoint and the data is +* * OUT endpoint - The Host has written data into the endpoint and the data is * ready to be read. * To remove the callback function, pass NULL as function pointer. * @@ -1651,7 +1735,7 @@ __STATIC_INLINE void Cy_USBFS_Dev_Drv_RegisterLpmCallback(USBFS_Type *base, * modify anything in this structure. * * \note -* To remove the callback, pass NULL as the pointer to a callback function. +* To remove the callback, pass NULL as the pointer to the callback function. * *******************************************************************************/ __STATIC_INLINE void Cy_USBFS_Dev_Drv_RegisterEndpointCallback(USBFS_Type const *base, @@ -1660,7 +1744,7 @@ __STATIC_INLINE void Cy_USBFS_Dev_Drv_RegisterEndpointCallback(USBFS_Type const cy_stc_usbfs_dev_drv_context_t *context) { - /* Suppress a compiler warning about unused variables */ + /* Suppresses a compiler warning about unused variables */ (void) base; CY_ASSERT_L1(CY_USBFS_DEV_DRV_IS_EP_VALID(endpoint)); @@ -1759,13 +1843,13 @@ __STATIC_INLINE void Cy_USBFS_Dev_Drv_SetInterruptsLevel(USBFS_Type *base, uint3 * Function Name: Cy_USBFS_Dev_Drv_GetInterruptsLevel ****************************************************************************//** * -* Returns INTR_LVL_SEL register that contains groups for all interrupt sources. +* Returns the INTR_LVL_SEL register that contains groups for all interrupt sources. * * \param base * The pointer to the USBFS instance. * * \return -* Returns INTR_LVL_SEL register that contains groups for all interrupt sources. +* Returns the INTR_LVL_SEL register that contains groups for all interrupt sources. * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetInterruptsLevel(USBFS_Type const *base) @@ -1774,12 +1858,11 @@ __STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetInterruptsLevel(USBFS_Type const *b } - /******************************************************************************* * Function Name: Cy_USBFS_Dev_Drv_DisableEp0Interrupt ****************************************************************************//** * -* Enables Control Endpoint 0 interrupt source. +* Enables the Control Endpoint 0 interrupt source. * * \param base * The pointer to the USBFS instance. @@ -1796,7 +1879,7 @@ __STATIC_INLINE void Cy_USBFS_Dev_Drv_DisableEp0Interrupt(USBFS_Type *base) * Function Name: Cy_USBFS_Dev_Drv_EnableEp0Interrupt ****************************************************************************//** * -* Enables Control Endpoint 0 interrupt. +* Enables the Control Endpoint 0 interrupt. * * \param base * The pointer to the USBFS instance source. @@ -1818,16 +1901,16 @@ __STATIC_INLINE void Cy_USBFS_Dev_Drv_EnableEp0Interrupt(USBFS_Type *base) ****************************************************************************//** * * Returns the activity status of the bus. -* It clears the hardware status to provide updated status on the next call of +* It clears the hardware status to provide an updated status on the next call of * this function. This function is useful to determine whether there is any USB bus -* activity between function calls. The typical use case is to determine whether +* activity between function calls. A typical use case is to determine whether * the USB suspend conditions are met. * * \param base * The pointer to the USBFS instance. * * \return -* Bus activity since last call. +* The bus activity since the last call. * *******************************************************************************/ __STATIC_INLINE bool Cy_USBFS_Dev_Drv_CheckActivity(USBFS_Type *base) @@ -1847,13 +1930,13 @@ __STATIC_INLINE bool Cy_USBFS_Dev_Drv_CheckActivity(USBFS_Type *base) ****************************************************************************//** * * Forces a USB J, K, or SE0 state on the USB lines. -* The typical use case is to signal a Remote Wakeup condition on the USB bus. +* A typical use case is to signal a Remote Wakeup condition on the USB bus. * * \param base * The pointer to the USBFS instance. * * \param state -* Desired bus state. +* The desired bus state. * See \ref cy_en_usbfs_dev_drv_force_bus_state_t for the set of constants. * *******************************************************************************/ @@ -1962,7 +2045,7 @@ __STATIC_INLINE cy_en_usbfs_dev_drv_lpm_req_t Cy_USBFS_Dev_Drv_Lpm_GetResponse(U * Function Name: Cy_USBFS_Dev_Drv_AddEndpoint ****************************************************************************//** * -* Configures data endpoint for the following operation (allocates hardware +* Configures a data endpoint for the following operation (allocates hardware * resources for data endpoint). * * \param base @@ -1978,14 +2061,24 @@ __STATIC_INLINE cy_en_usbfs_dev_drv_lpm_req_t Cy_USBFS_Dev_Drv_Lpm_GetResponse(U * modify anything in this structure. * * \return -* Status code of the function execution \ref cy_en_usbfs_dev_drv_status_t. +* The status code of the function execution \ref cy_en_usbfs_dev_drv_status_t. * *******************************************************************************/ __STATIC_INLINE cy_en_usbfs_dev_drv_status_t Cy_USBFS_Dev_Drv_AddEndpoint(USBFS_Type *base, cy_stc_usb_dev_ep_config_t const *config, cy_stc_usbfs_dev_drv_context_t *context) { - return context->addEndpoint(base, config, context); + cy_en_usbfs_dev_drv_status_t retStatus = CY_USBFS_DEV_DRV_BAD_PARAM; + + uint32_t endpoint = CY_USBFS_DEV_DRV_EPADDR2EP(config->endpointAddr); + + /* Checks if the endpoint is supported by the driver */ + if (CY_USBFS_DEV_DRV_IS_EP_VALID(endpoint)) + { + retStatus = context->addEndpoint(base, config, context); + } + + return retStatus; } @@ -1993,7 +2086,7 @@ __STATIC_INLINE cy_en_usbfs_dev_drv_status_t Cy_USBFS_Dev_Drv_AddEndpoint(USBFS_ * Function Name: Cy_USBFS_Dev_Drv_OverwriteMemcpy ****************************************************************************//** * -* Overwrites the memory copy (memcpy) function used to copy data with the user +* Overwrites the memory copy (memcpy) function used to copy data with the user- * implemented: * * \ref Cy_USBFS_Dev_Drv_ReadOutEndpoint copies data from from the internal * buffer to the application buffer for OUT endpoint. @@ -2066,12 +2159,14 @@ __STATIC_INLINE cy_en_usb_dev_ep_state_t Cy_USBFS_Dev_Drv_GetEndpointState( cy_stc_usbfs_dev_drv_context_t const *context) { - /* Suppress a compiler warning about unused variables */ - (void) base; - - CY_ASSERT_L1(CY_USBFS_DEV_DRV_IS_EP_VALID(endpoint)); + cy_en_usb_dev_ep_state_t retState = CY_USB_DEV_EP_INVALID; - return context->epPool[CY_USBFS_DEV_DRV_EP2PHY(endpoint)].state; + if (CY_USBFS_DEV_DRV_IS_EP_VALID(endpoint)) + { + retState = context->epPool[CY_USBFS_DEV_DRV_EP2PHY(endpoint)].state; + } + + return retState; } @@ -2102,7 +2197,7 @@ __STATIC_INLINE cy_en_usb_dev_ep_state_t Cy_USBFS_Dev_Drv_GetEndpointState( * modify anything in this structure. * * \return -* Status code of the function execution \ref cy_en_usbfs_dev_drv_status_t. +* The status code of the function execution \ref cy_en_usbfs_dev_drv_status_t. * *******************************************************************************/ __STATIC_INLINE cy_en_usbfs_dev_drv_status_t Cy_USBFS_Dev_Drv_LoadInEndpoint( @@ -2124,7 +2219,7 @@ __STATIC_INLINE cy_en_usbfs_dev_drv_status_t Cy_USBFS_Dev_Drv_LoadInEndpoint( ****************************************************************************//** * * Reads data from the OUT endpoint buffer. -* Before executing the next read, the \ref Cy_USBFS_Dev_Drv_EnableOutEndpoint must be +* Before executing a next read, the \ref Cy_USBFS_Dev_Drv_EnableOutEndpoint must be * called to allow the Host to write data into the endpoint. * * \param base @@ -2134,14 +2229,14 @@ __STATIC_INLINE cy_en_usbfs_dev_drv_status_t Cy_USBFS_Dev_Drv_LoadInEndpoint( * The OUT data endpoint number. * * \param buffer -* Pointer to the buffer that stores data that was read. +* The pointer to the buffer that stores read data. * * \param size -* The number of bytes to read from endpoint. -* This value must be less than or equal to endpoint maximum packet size. +* The number of bytes to read from the endpoint. +* This value must be less than or equal to the endpoint maximum packet size. * * \param actSize -* The number of bytes which were actually read. +* The number of actually read bytes. * * \param context * The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t @@ -2150,7 +2245,7 @@ __STATIC_INLINE cy_en_usbfs_dev_drv_status_t Cy_USBFS_Dev_Drv_LoadInEndpoint( * modify anything in this structure. * * \return -* Status code of the function execution \ref cy_en_usbfs_dev_drv_status_t. +* The status code of the function execution \ref cy_en_usbfs_dev_drv_status_t. * *******************************************************************************/ __STATIC_INLINE cy_en_usbfs_dev_drv_status_t Cy_USBFS_Dev_Drv_ReadOutEndpoint( @@ -2197,12 +2292,12 @@ __STATIC_INLINE bool Cy_USBFS_Dev_Drv_GetEndpointAckState(USBFS_Type const *base * Function Name: Cy_USBFS_Dev_Drv_GetEndpointCount ****************************************************************************//** * -* Return number of data bytes in the transaction for a certain endpoint. -* Before calling this function ensure that the Host wrote data into the +* Returns the number of data bytes in the transaction for a certain endpoint. +* Before calling this function, ensure the Host has written data into the * endpoint. The returned value is updated after the Host access to the * endpoint but remains unchanged after data has been read from the endpoint * buffer. -* The typical use case is to read number of bytes that the Host wrote into the +* A typical use case is to read the number of bytes that the Host wrote into the * OUT endpoint. * * \param base @@ -2221,44 +2316,6 @@ __STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetEndpointCount(USBFS_Type const *bas return Cy_USBFS_Dev_Drv_GetSieEpCount(base, CY_USBFS_DEV_DRV_EP2PHY(endpoint)); } - - -/******************************************************************************* -* Function Name: Cy_USBFS_Dev_Drv_GetEndpointStallState -****************************************************************************//** -* -* This function returns the state of a certain endpoint. -* -* \param base -* The pointer to the USBFS instance. -* -* \param endpoint -* The data endpoint number. -* -* \param context -* The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t -* allocated by the user. The structure is used during the USBFS Device -* operation for internal configuration and data retention. The user must not -* modify anything in this structure. -* -* \return -* Endpoint state \ref cy_en_usb_dev_ep_state_t. -* -*******************************************************************************/ -__STATIC_INLINE cy_en_usb_dev_ep_state_t Cy_USBFS_Dev_Drv_GetEndpointStallState( - USBFS_Type const *base, - uint32_t endpoint, - cy_stc_usbfs_dev_drv_context_t const *context) -{ - if (CY_USBFS_DEV_DRV_IS_EP_VALID(endpoint)) - { - return Cy_USBFS_Dev_Drv_GetEndpointState(base, endpoint, context); - } - else - { - return CY_USB_DEV_EP_INVALID; - } -} /** \} group_usbfs_dev_hal_functions_data_xfer */ @@ -2275,20 +2332,37 @@ __STATIC_INLINE cy_en_usb_dev_ep_state_t Cy_USBFS_Dev_Drv_GetEndpointStallState( * \param base * The pointer to the USBFS instance. * -* \param context -* The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t -* allocated by the user. The structure is used during the USBFS Device -* operation for internal configuration and data retention. The user must not -* modify anything in this structure. +*******************************************************************************/ +__STATIC_INLINE void Cy_USBFS_Dev_Drv_Ep0Stall(USBFS_Type *base) +{ + /* Updates the CR registers to STALL a request (CNT register does not care) */ + Cy_USBFS_Dev_Drv_WriteEp0Mode(base, CY_USBFS_DEV_DRV_EP_CR_STALL_INOUT); +} + + +/******************************************************************************* +* Function Name: Cy_USBFS_Dev_Drv_GetEp0MaxPacket +****************************************************************************//** +* +* Returns the endpoint 0 maximum packet size that can be for read or write from +* the endpoint 0 buffer. +* +* \param base +* The pointer to the USBFS instance. +* +* \return +* The endpoint 0 maximum packet size (endpoint 0 has a dedicated hardware buffer). * *******************************************************************************/ -__STATIC_INLINE void Cy_USBFS_Dev_Drv_Ep0Stall(USBFS_Type const *base, cy_stc_usbfs_dev_drv_context_t *context) +__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetEp0MaxPacket(USBFS_Type const *base) { - /* Suppress a compiler warning about unused variables */ + /* Suppresses a compiler warning about unused variables */ (void) base; - context->ep0ModeReg = CY_USBFS_DEV_DRV_EP_CR_STALL_INOUT; + return (CY_USBFS_DEV_DRV_EP0_BUFFER_SIZE); } + + /** \} group_usbfs_dev_hal_functions_ep0_service */ #if defined(__cplusplus) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_usbfs_dev_drv_pvt.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_usbfs_dev_drv_pvt.h index e2d996d9d3..e2bd84bced 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_usbfs_dev_drv_pvt.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_usbfs_dev_drv_pvt.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_usbfs_dev_drv_pvt.h -* \version 1.10 +* \version 2.0 * * Provides API declarations of the USBFS driver. * @@ -210,7 +210,7 @@ __STATIC_INLINE uint32_t GetEndpointInactiveMode(uint32_t mode) case CY_USBFS_DEV_DRV_EP_CR_ISO_OUT: case CY_USBFS_DEV_DRV_EP_CR_ISO_IN: - /* Ignore traffic to endpoint. Wait for endpoint load or enable. */ + /* Ignore traffic to endpoint. Wait for endpoint load or enable */ mode = CY_USBFS_DEV_DRV_EP_CR_DISABLE; mode = CY_USBFS_DEV_DRV_EP_CR_DISABLE; break; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_usbfs_dev_drv_reg.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_usbfs_dev_drv_reg.h index ee206f3fc4..216795eebf 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_usbfs_dev_drv_reg.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_usbfs_dev_drv_reg.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_usbfs_dev_drv_reg.h -* \version 1.10 +* \version 2.0 * * Provides register access API implementation of the USBFS driver. * @@ -47,6 +47,7 @@ * \defgroup group_usbfs_drv_drv_reg_functions Functions * \{ * \defgroup group_usbfs_drv_drv_reg_interrupt_sources SIE Interrupt Sources Registers Access +* \defgroup group_usbfs_drv_drv_reg_ep0_access Endpoint 0 Registers Access * \defgroup group_usbfs_drv_drv_reg_sie_access SIE Data Endpoint Registers Access * \defgroup group_usbfs_drv_drv_reg_arbiter Arbiter Endpoint Registers Access * \defgroup group_usbfs_drv_drv_reg_arbiter_data Arbiter Endpoint Data Registers Access @@ -110,6 +111,22 @@ __STATIC_INLINE void Cy_USBFS_Dev_Drv_ClearSieInterrupt (USBFS_Type *base __STATIC_INLINE void Cy_USBFS_Dev_Drv_SetSieInterrupt (USBFS_Type *base, uint32_t mask); /** \} group_usbfs_drv_drv_reg_interrupt_sources */ + +/** +* \addtogroup group_usbfs_drv_drv_reg_ep0_access +* \{ +*/ +/* Access control endpoint CR0.Mode registers */ +__STATIC_INLINE void Cy_USBFS_Dev_Drv_WriteEp0Mode(USBFS_Type *base, uint32_t mode); +__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_ReadEp0Mode(USBFS_Type const *base); + +__STATIC_INLINE void Cy_USBFS_Dev_Drv_SetEp0Count(USBFS_Type *base, uint32_t count, uint32_t toggle); +__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetEp0Count(USBFS_Type const *base); + +__STATIC_INLINE void Cy_USBFS_Dev_Drv_WriteEp0Data(USBFS_Type *base, uint32_t idx, uint32_t value); +__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_ReadEp0Data(USBFS_Type const *base, uint32_t idx); +/** \} group_usbfs_drv_drv_reg_ep0_access */ + /** * \addtogroup group_usbfs_drv_drv_reg_sie_access * \{ @@ -154,17 +171,17 @@ __STATIC_INLINE void Cy_USBFS_Dev_Drv_ClearArbCfgEpInReady (USBFS_Type *base, ui __STATIC_INLINE void Cy_USBFS_Dev_Drv_TriggerArbCfgEpDmaReq(USBFS_Type *base, uint32_t endpoint); /* Access Arbiter data endpoints WA (Write Address and RA(Read Address) registers */ -__STATIC_INLINE void Cy_USBFS_Dev_Drv_SetArbWriteAddr (USBFS_Type *base, uint32_t endpoint, uint32_t wa); -__STATIC_INLINE void Cy_USBFS_Dev_Drv_SetArbReadAddr (USBFS_Type *base, uint32_t endpoint, uint32_t ra); -__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetArbWriteAddr (USBFS_Type const *base, uint32_t endpoint); -__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetArbReadAddr (USBFS_Type const *base, uint32_t endpoint); +__STATIC_INLINE void Cy_USBFS_Dev_Drv_SetArbWriteAddr(USBFS_Type *base, uint32_t endpoint, uint32_t wa); +__STATIC_INLINE void Cy_USBFS_Dev_Drv_SetArbReadAddr (USBFS_Type *base, uint32_t endpoint, uint32_t ra); +__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetArbWriteAddr(USBFS_Type const *base, uint32_t endpoint); +__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetArbReadAddr (USBFS_Type const *base, uint32_t endpoint); /** \} group_usbfs_drv_drv_reg_arbiter */ /** * \addtogroup group_usbfs_drv_drv_reg_arbiter_data * \{ */ -/* Access data endpoints data registers. Used to get/put data into endpoint buffer. */ +/* Access data endpoints data registers. Used to get/put data into endpoint buffer */ __STATIC_INLINE void Cy_USBFS_Dev_Drv_WriteData (USBFS_Type *base, uint32_t endpoint, uint8_t byte); __STATIC_INLINE void Cy_USBFS_Dev_Drv_WriteData16(USBFS_Type *base, uint32_t endpoint, uint16_t halfword); __STATIC_INLINE uint8_t Cy_USBFS_Dev_Drv_ReadData (USBFS_Type const *base, uint32_t endpoint); @@ -178,8 +195,8 @@ __STATIC_INLINE void Cy_USBFS_Dev_Drv_FlushInBuffer (USBFS_Type *base, uint3 * \addtogroup group_usbfs_drv_drv_reg_misc * \{ */ -__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetEp0Count(USBFS_Type const *base); __STATIC_INLINE void Cy_USBFS_Dev_Drv_SetEpType (USBFS_Type *base, bool inDirection, uint32_t endpoint); +__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetSofNubmer(USBFS_Type const *base); /** \} group_usbfs_drv_drv_reg_misc */ @@ -424,6 +441,165 @@ __STATIC_INLINE void Cy_USBFS_Dev_Drv_SetSieInterrupt(USBFS_Type *base, uint32_t /** \} group_usbfs_drv_drv_reg_interrupt_sources */ +/** +* \addtogroup group_usbfs_drv_drv_reg_ep0_access +* \{ +*/ +/******************************************************************************* +* Function Name: Cy_USBFS_Dev_Drv_WriteEp0Mode +****************************************************************************//** +* +* Sets a mode in the CR0 register of endpoint 0 (clears all other bits in the +* register). +* +* \param base +* The pointer to the USBFS instance. +* +* \param mode +* SIE mode defines the data endpoint 0 response to a host request. +* See \ref group_usbfs_dev_drv_reg_macros_sie_mode for the set of constants. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_USBFS_Dev_Drv_WriteEp0Mode(USBFS_Type *base, uint32_t mode) +{ + USBFS_DEV_EP0_CR(base) = mode; + (void) USBFS_DEV_EP0_CR(base); +} + +/******************************************************************************* +* Function Name: Cy_USBFS_Dev_Drv_ReadEp0Mode +****************************************************************************//** +* +* Returns a mode in the CR0 register of endpoint 0. +* +* \param base +* The pointer to the USBFS instance. +* +* \return +* SIE mode (defines the endpoint 0 response to a host request). +* See \ref group_usbfs_dev_drv_reg_macros_sie_mode for the set of constants. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_ReadEp0Mode(USBFS_Type const *base) +{ + return USBFS_DEV_EP0_CR(base); +} + + +/******************************************************************************* +* Function Name: Cy_USBFS_Dev_Drv_SetSieEpCount +****************************************************************************//** +* +* Configures the number of bytes and toggle bit to return to a host read request +* to endpoint 0. +* +* \param base +* The pointer to the USBFS instance. +* +* \param count +* The number of bytes to return to a host read request. +* +* \param toggle +* The data toggle bit. +* The range of valid values: 0 and \ref USBFS_USBDEV_SIE_EP_DATA_TOGGLE_Msk. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_USBFS_Dev_Drv_SetEp0Count(USBFS_Type *base, uint32_t count, uint32_t toggle) +{ + count = _VAL2FLD(USBFS_USBDEV_EP0_CNT_BYTE_COUNT, count); + USBFS_DEV_EP0_CNT(base) = CY_USBFS_DEV_DRV_WRITE_ODD(count | toggle); +} + + +/******************************************************************************* +* Function Name: Cy_USBFS_Dev_Drv_GetEp0Count +****************************************************************************//** +* +* Returns the number of data bytes written into endpoint 0 by the host. +* +* \param base +* The pointer to the USBFS instance. +* +* \return +* The number of bytes written by the host into the endpoint. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetEp0Count(USBFS_Type const *base) +{ + uint32_t ep0Cnt = CY_USBFS_DEV_READ_ODD(USBFS_DEV_EP0_CNT(base)); + + /* Excludes the CRC size */ + return (_FLD2VAL(USBFS_USBDEV_EP0_CNT_BYTE_COUNT, ep0Cnt) - CY_USBFS_DEV_DRV_EP_CRC_SIZE); +} + + +/******************************************************************************* +* Function Name: Cy_USBFS_Dev_Drv_WriteEp0Data +****************************************************************************//** +* +* Writes an 8-bit byte into the endpoint 0 hardware buffer. +* +* \param base +* The pointer to the USBFS instance. +* +* \param idx +* The index of the endpoint 0 hardware buffer entry. +* Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_EP0_BUFFER_SIZE - 1 ). +* +* \param value +* The value to be written into the endpoint 0 hardware buffer. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_USBFS_Dev_Drv_WriteEp0Data(USBFS_Type *base, uint32_t idx, uint32_t value) +{ + if (0U == (idx & 0x1U)) + { + USBFS_DEV_EP0_DR(base, idx) = value; + } + else + { + /* Applies a special write for odd offset registers */ + USBFS_DEV_EP0_DR(base, idx) = CY_USBFS_DEV_DRV_WRITE_ODD(value); + } +} + + +/******************************************************************************* +* Function Name: Cy_USBFS_Dev_Drv_ReadEp0Data +****************************************************************************//** +* +* Reads an 8-bit byte from the endpoint 0 hardware buffer. +* +* \param base +* The pointer to the USBFS instance. +* +* \param idx +* The index of the endpoint 0 hardware buffer entry. +* Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_EP0_BUFFER_SIZE - 1 ). +* +* \return +* The byte of data to read from the hardware buffer. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_ReadEp0Data(USBFS_Type const *base, uint32_t idx) +{ + uint32_t value; + + if (0U == (idx & 0x1U)) + { + value = USBFS_DEV_EP0_DR(base, idx); + } + else + { + /* Applies a special write for odd offset registers */ + value = CY_USBFS_DEV_READ_ODD(USBFS_DEV_EP0_DR(base, idx)); + } + + return (value); +} +/** \} group_usbfs_drv_drv_reg_ep0_access */ + + /** * \addtogroup group_usbfs_drv_drv_reg_sie_access * \{ @@ -445,7 +621,7 @@ __STATIC_INLINE void Cy_USBFS_Dev_Drv_SetSieInterrupt(USBFS_Type *base, uint32_t * Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ). * * \param mode -* SIE mode defines data endpoint response to Host request. +* SIE mode defines data endpoint response to host request. * See \ref group_usbfs_dev_drv_reg_macros_sie_mode for the set of constants. * *******************************************************************************/ @@ -648,7 +824,7 @@ __STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetSieEpCount(USBFS_Type const *base, * Function Name: Cy_USBFS_Dev_Drv_SetSieEpCount ****************************************************************************//** * -* Configures number of bytes and toggle bit to return on the Host read request +* Configures number of bytes and toggle bit to return on the host read request * to the IN data endpoint. * * \param base @@ -659,7 +835,7 @@ __STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetSieEpCount(USBFS_Type const *base, * Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ). * * \param count -* The number of bytes to return on the Host read request. +* The number of bytes to return on the host read request. * * \param toggle * The data toggle bit. @@ -1289,27 +1465,6 @@ __STATIC_INLINE void Cy_USBFS_Dev_Drv_FlushInBuffer(USBFS_Type *base, uint32_t e * \addtogroup group_usbfs_drv_drv_reg_misc * \{ */ -/******************************************************************************* -* Function Name: Cy_USBFS_Dev_Drv_GetEp0Count -****************************************************************************//** -* -* Returns the number of data bytes written into the endpoint 0 by the host. -* -* \param base -* The pointer to the USBFS instance. -* -* \return -* Number of bytes written by the Host into the endpoint. -* -*******************************************************************************/ -__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetEp0Count(USBFS_Type const *base) -{ - /* Exclude CRC size */ - uint32_t ep0Cnt = CY_USBFS_DEV_READ_ODD(USBFS_DEV_EP0_CNT(base)); - - return (_FLD2VAL(USBFS_USBDEV_EP0_CNT_BYTE_COUNT, ep0Cnt) - CY_USBFS_DEV_DRV_EP_CRC_SIZE); -} - /******************************************************************************* * Function Name: Cy_USBFS_Dev_Drv_SetEpType @@ -1346,6 +1501,25 @@ __STATIC_INLINE void Cy_USBFS_Dev_Drv_SetEpType(USBFS_Type *base, bool inDirecti USBFS_DEV_EP_TYPE(base) = CY_USBFS_DEV_DRV_WRITE_ODD(regValue); } + + +/******************************************************************************* +* Function Name: Cy_USBFS_Dev_Drv_GetSofNubmer +****************************************************************************//** +* +* Returns the SOF frame number. +* +* \param base +* The pointer to the USBFS instance. +* +* \return +* The SOF frame number. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetSofNubmer(USBFS_Type const *base) +{ + return _FLD2VAL(USBFS_USBDEV_SOF16_FRAME_NUMBER16, USBFS_DEV_SOF16(base)); +} /** \} group_usbfs_drv_drv_reg_misc */ #if defined(__cplusplus) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/TOOLCHAIN_ARM/cy_syslib_mdk.S b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/TOOLCHAIN_ARM/cy_syslib_mdk.S index 6630766025..8bb4a96a3b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/TOOLCHAIN_ARM/cy_syslib_mdk.S +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/TOOLCHAIN_ARM/cy_syslib_mdk.S @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------- ; \file cy_syslib_mdk.s -; \version 2.30 +; \version 2.40 ; ; \brief Assembly routines for ARMCC. ; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/TOOLCHAIN_GCC_ARM/cy_syslib_gcc.S b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/TOOLCHAIN_GCC_ARM/cy_syslib_gcc.S index 9bc6b0660d..de5eb05cb1 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/TOOLCHAIN_GCC_ARM/cy_syslib_gcc.S +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/TOOLCHAIN_GCC_ARM/cy_syslib_gcc.S @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_syslib_gcc.S -* \version 2.20 +* \version 2.40 * * \brief Assembly routines for GNU GCC. * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/TOOLCHAIN_IAR/cy_syslib_iar.S b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/TOOLCHAIN_IAR/cy_syslib_iar.S index 6099843393..37d79a089d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/TOOLCHAIN_IAR/cy_syslib_iar.S +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/TOOLCHAIN_IAR/cy_syslib_iar.S @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_syslib_iar.s -* \version 2.20 +* \version 2.40 * * \brief Assembly routines for IAR Embedded Workbench IDE. * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_ble_clk.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_ble_clk.c index cd2e3a1f8a..8edd588d0b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_ble_clk.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_ble_clk.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_ble_clk.c -* \version 3.10 +* \version 3.20 * * \brief * This driver provides the source code for API BLE ECO clock. @@ -27,6 +27,7 @@ #include "cy_gpio.h" #include "cy_syspm.h" #include "cy_ble_clk.h" +#include "cy_sysclk.h" #if defined(CY_IP_MXBLESS) @@ -50,6 +51,7 @@ static cy_en_ble_eco_status_t Cy_BLE_HAL_MxdRadioEnableClocks(cy_en_ble_eco_freq *******************************************************************************/ /** \cond INTERNAL */ + #define CY_BLE_PORT2_CFG_VAL (0x66666666u) #define CY_BLE_PORT3_CFG_VAL (0x66EEE666u) #define CY_BLE_PORT4_CFG_VAL (0x6666E666u) @@ -201,7 +203,7 @@ static cy_en_ble_eco_status_t Cy_BLE_HAL_MxdRadioEnableClocks(cy_en_ble_eco_freq * CY_BLE_ECO_HARDWARE_ERROR | The RCB or BLE ECO operation failed. * * \funcusage -* \snippet bleclk\3.0\snippet\main.c BLE ECO clock API: Cy_BLE_EcoConfigure() +* \snippet bleclk/snippet/main.c BLE ECO clock API: Cy_BLE_EcoConfigure() * * \sideeffect * The I/O pins will be automatically unfrozen coming out of Hibernate when @@ -411,6 +413,7 @@ void Cy_BLE_EcoReset(void) { /* Initiate Soft Reset */ BLE_BLESS_LL_CLK_EN |= BLE_BLESS_LL_CLK_EN_BLESS_RESET_Msk; + altHfFreq = 0UL; /* Reset the BLE ECO frequency */ } @@ -782,7 +785,7 @@ static cy_en_ble_eco_status_t Cy_BLE_HAL_MxdRadioEnableClocks(cy_en_ble_eco_freq temp |= (uint16_t)(CY_BLE_MXD_RADIO_CLK_BUF_AMP_32M_LARGE << CY_BLE_RF_DCXO_BUF_CFG_REG_BUF_AMP_SEL_SHIFT); /* Update cy_BleEcoClockFreqHz for the proper Cy_SysLib_Delay functionality */ - cy_BleEcoClockFreqHz = CY_BLE_DEFAULT_ECO_CLK_FREQ_32MHZ / (1UL << (uint16_t)sysClkDiv); + altHfFreq = CY_BLE_DEFAULT_ECO_CLK_FREQ_32MHZ / (1UL << (uint16_t)sysClkDiv); } else { @@ -799,7 +802,7 @@ static cy_en_ble_eco_status_t Cy_BLE_HAL_MxdRadioEnableClocks(cy_en_ble_eco_freq temp |= (uint16_t)(CY_BLE_MXD_RADIO_CLK_BUF_AMP_16M_LARGE << CY_BLE_RF_DCXO_BUF_CFG_REG_BUF_AMP_SEL_SHIFT); /* Update cy_BleEcoClockFreqHz for the proper Cy_SysLib_Delay functionality */ - cy_BleEcoClockFreqHz = CY_BLE_DEFAULT_ECO_CLK_FREQ_16MHZ / (1UL << (uint16_t)sysClkDiv); + altHfFreq = CY_BLE_DEFAULT_ECO_CLK_FREQ_16MHZ / (1UL << (uint16_t)sysClkDiv); } temp |= (uint16_t)(blerdDivider << CY_BLE_RF_DCXO_BUF_CFG_REG_CLK_DIV_SHIFT); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto.c index 66bd2e6184..177cbe3c05 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto.c -* \version 2.20 +* \version 2.30 * * \brief * Provides API implementation of the Cypress PDL Crypto driver. @@ -869,9 +869,112 @@ cy_en_crypto_status_t Cy_Crypto_Rsa_Verify(cy_en_crypto_rsa_ver_result_t *verRes } #endif /* #if (CPUSS_CRYPTO_SHA == 1) */ +cy_en_crypto_status_t Cy_Crypto_ECDSA_SignHash(const uint8_t *hash, + uint32_t hashlen, + uint8_t *sig, + const cy_stc_crypto_ecc_key *key, + const uint8_t *messageKey, + cy_stc_crypto_context_ecc_t *cfContext) +{ + cy_en_crypto_status_t err = CY_CRYPTO_NOT_INITIALIZED; + + if (clientContext != NULL) + { + clientContext->instr = CY_CRYPTO_INSTR_ECDSA_SIGN; + clientContext->xdata = cfContext; + + cfContext->datalen = hashlen; + cfContext->src0 = hash; + cfContext->dst0 = sig; + cfContext->key = key; + cfContext->src1 = messageKey; + + err = Cy_Crypto_Client_Send(); + } + return (err); +} + +cy_en_crypto_status_t Cy_Crypto_ECDSA_VerifyHash(const uint8_t *sig, + const uint8_t *hash, + uint32_t hashlen, + uint8_t *stat, + const cy_stc_crypto_ecc_key *key, + cy_stc_crypto_context_ecc_t *cfContext) +{ + cy_en_crypto_status_t err = CY_CRYPTO_NOT_INITIALIZED; + + if (clientContext != NULL) + { + clientContext->instr = CY_CRYPTO_INSTR_ECDSA_VER; + clientContext->xdata = cfContext; + + cfContext->datalen = hashlen; + cfContext->src0 = hash; + cfContext->src1 = sig; + cfContext->dst0 = stat; + cfContext->key = key; + + err = Cy_Crypto_Client_Send(); + } + return (err); +} + #endif /* #if (CPUSS_CRYPTO_VU == 1) */ -void Cy_Crypto_Rsa_InvertEndianness(void *inArrPtr, uint32_t byteSize) +cy_en_crypto_status_t Cy_Crypto_SetMemBufAddress(uint32_t const *newMembufAddress, + uint32_t newMembufSize, + cy_stc_crypto_context_str_t *cfContext) +{ + cy_en_crypto_status_t err = CY_CRYPTO_NOT_INITIALIZED; + + if (clientContext != NULL) + { + clientContext->instr = CY_CRYPTO_INSTR_MEMBUF_SET; + clientContext->xdata = cfContext; + + cfContext->src0 = newMembufAddress; + cfContext->dataSize = newMembufSize; + + err = Cy_Crypto_Client_Send(); + } + return (err); +} + +cy_en_crypto_status_t Cy_Crypto_GetMemBufAddress(uint32_t **membufAddress, + cy_stc_crypto_context_str_t *cfContext) +{ + cy_en_crypto_status_t err = CY_CRYPTO_NOT_INITIALIZED; + + if (clientContext != NULL) + { + clientContext->instr = CY_CRYPTO_INSTR_MEMBUF_ADDR; + clientContext->xdata = cfContext; + + cfContext->dst = (void *)membufAddress; + + err = Cy_Crypto_Client_Send(); + } + return (err); +} + +cy_en_crypto_status_t Cy_Crypto_GetMemBufSize(uint32_t *membufSize, + cy_stc_crypto_context_str_t *cfContext) +{ + cy_en_crypto_status_t err = CY_CRYPTO_NOT_INITIALIZED; + + if (clientContext != NULL) + { + clientContext->instr = CY_CRYPTO_INSTR_MEMBUF_SIZE; + clientContext->xdata = cfContext; + + cfContext->dst = (void *)membufSize; + + err = Cy_Crypto_Client_Send(); + } + return (err); +} + +void Cy_Crypto_InvertEndianness(void *inArrPtr, uint32_t byteSize) { int32_t limit; int32_t i; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_aes_v1.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_aes_v1.c index f7a67e20b5..7c228a6815 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_aes_v1.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_aes_v1.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_aes_v1.c -* \version 2.20 +* \version 2.30 * * \brief * This file provides the source code fro the API for the AES method @@ -66,8 +66,11 @@ void Cy_Crypto_Core_V1_Aes_ProcessBlock(CRYPTO_Type *base, uint32_t *dstBlock, uint32_t const *srcBlock) { + /* Set the key mode: 128, 192 or 256 Bit */ + REG_CRYPTO_AES_CTL(base) = (uint32_t)(_VAL2FLD(CRYPTO_AES_CTL_KEY_SIZE, (uint32_t)(aesState->keyLength))); + Cy_Crypto_SetReg3Instr(base, - (CY_CRYPTO_DECRYPT == dirMode) ? (uint32_t)aesState->invKey : (uint32_t)aesState->key, + (CY_CRYPTO_DECRYPT == dirMode) ? (uint32_t)aesState->buffers->keyInv : (uint32_t)aesState->buffers->key, (uint32_t)srcBlock, (uint32_t)dstBlock); @@ -113,6 +116,9 @@ void Cy_Crypto_Core_V1_Aes_Xor(CRYPTO_Type *base, uint32_t const *src0Block, uint32_t const *src1Block) { + /* Set the key mode: 128, 192 or 256 Bit */ + REG_CRYPTO_AES_CTL(base) = (uint32_t)(_VAL2FLD(CRYPTO_AES_CTL_KEY_SIZE, (uint32_t)(aesState->keyLength))); + Cy_Crypto_SetReg3Instr(base, (uint32_t)src0Block, (uint32_t)src1Block, @@ -147,8 +153,11 @@ void Cy_Crypto_Core_V1_Aes_Xor(CRYPTO_Type *base, *******************************************************************************/ static void Cy_Crypto_Core_V1_Aes_InvKey(CRYPTO_Type *base, cy_stc_crypto_aes_state_t const *aesState) { + /* Set the key mode: 128, 192 or 256 Bit */ + REG_CRYPTO_AES_CTL(base) = (uint32_t)(_VAL2FLD(CRYPTO_AES_CTL_KEY_SIZE, (uint32_t)(aesState->keyLength))); + /* Issue the AES_KEY instruction to prepare the key for decrypt operation */ - Cy_Crypto_SetReg2Instr(base, (uint32_t)aesState->key, (uint32_t)aesState->invKey); + Cy_Crypto_SetReg2Instr(base, (uint32_t)aesState->buffers->key, (uint32_t)aesState->buffers->keyInv); Cy_Crypto_Run2ParamInstr(base, CY_CRYPTO_V1_AES_KEY_OPC, @@ -180,6 +189,9 @@ static void Cy_Crypto_Core_V1_Aes_InvKey(CRYPTO_Type *base, cy_stc_crypto_aes_st * The pointer to the AES state structure allocated by the user. The user * must not modify anything in this structure. * +* \param aesBuffers +* The pointer to the memory buffers storage. +* * \return * \ref cy_en_crypto_status_t * @@ -187,29 +199,44 @@ static void Cy_Crypto_Core_V1_Aes_InvKey(CRYPTO_Type *base, cy_stc_crypto_aes_st cy_en_crypto_status_t Cy_Crypto_Core_V1_Aes_Init(CRYPTO_Type *base, uint8_t const *key, cy_en_crypto_aes_key_length_t keyLength, - cy_stc_crypto_aes_state_t *aesState) + cy_stc_crypto_aes_state_t *aesState, + cy_stc_crypto_aes_buffers_t *aesBuffers) { + uint16_t keySize = CY_CRYPTO_AES_128_KEY_SIZE + ((uint16_t)keyLength * 8u); + aesState->keyLength = keyLength; + aesState->buffers = aesBuffers; - /* Set the key mode: 128, 192 or 256 Bit */ - REG_CRYPTO_AES_CTL(base) = (uint32_t)(_VAL2FLD(CRYPTO_AES_CTL_KEY_SIZE, (uint32_t)(aesState->keyLength))); - - cy_stc_crypto_aes_buffers_t *aesBuffers = (cy_stc_crypto_aes_buffers_t *)(REG_CRYPTO_MEM_BUFF(base)); - - aesState->buffers = (uint32_t*) aesBuffers; - aesState->key = (uint8_t *)(aesBuffers->key); - aesState->invKey = (uint8_t *)(aesBuffers->keyInv); - - Cy_Crypto_Core_V1_MemCpy(base, aesState->key, key, CY_CRYPTO_AES_256_KEY_SIZE); + Cy_Crypto_Core_V1_MemCpy(base, (uint8_t *)(aesState->buffers->key), key, keySize); Cy_Crypto_Core_V1_Aes_InvKey(base, aesState); return (CY_CRYPTO_SUCCESS); } -void Cy_Crypto_Core_V1_Aes_Free(CRYPTO_Type *base) +/******************************************************************************* +* Function Name: Cy_Crypto_Core_V1_Aes_Free +****************************************************************************//** +* +* Clears AES operation context. +* +* \param base +* The pointer to the CRYPTO instance. +* +* \param aesState +* The pointer to the AES state structure allocated by the user. The user +* must not modify anything in this structure. +* +* \return +* \ref cy_en_crypto_status_t +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Core_V1_Aes_Free(CRYPTO_Type *base, cy_stc_crypto_aes_state_t *aesState) { - Cy_Crypto_Core_V1_MemSet(base, REG_CRYPTO_MEM_BUFF(base), 0u, sizeof(cy_stc_crypto_aes_buffers_t)); + Cy_Crypto_Core_V1_MemSet(base, (void *)aesState->buffers, 0u, sizeof(cy_stc_crypto_aes_buffers_t)); + Cy_Crypto_Core_V1_MemSet(base, (void *)aesState, 0u, sizeof(cy_stc_crypto_aes_state_t)); + + return (CY_CRYPTO_SUCCESS); } /******************************************************************************* @@ -292,7 +319,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Aes_Ecb(CRYPTO_Type *base, cy_en_crypto_status_t Cy_Crypto_Core_V1_Aes_Cbc(CRYPTO_Type *base, cy_en_crypto_dir_mode_t dirMode, uint32_t srcSize, - uint8_t const *ivPtr, + uint8_t *ivPtr, uint8_t *dst, uint8_t const *src, cy_stc_crypto_aes_state_t *aesState) @@ -300,9 +327,9 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Aes_Cbc(CRYPTO_Type *base, uint32_t size = srcSize; cy_stc_crypto_aes_buffers_t *aesBuffers = (cy_stc_crypto_aes_buffers_t*)aesState->buffers; - uint32_t *tempBuff = (uint32_t*)(&aesBuffers->iv); uint32_t *srcBuff = (uint32_t*)(&aesBuffers->block0); uint32_t *dstBuff = (uint32_t*)(&aesBuffers->block1); + uint32_t *tempBuff = (uint32_t*)(&aesBuffers->block2); cy_en_crypto_status_t tmpResult = CY_CRYPTO_SIZE_NOT_X16; @@ -355,6 +382,9 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Aes_Cbc(CRYPTO_Type *base, } } + /* Copy the cipher block to the Initialization Vector */ + Cy_Crypto_Core_V1_MemCpy(base, ivPtr, tempBuff, CY_CRYPTO_AES_BLOCK_SIZE); + tmpResult = CY_CRYPTO_SUCCESS; } @@ -397,7 +427,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Aes_Cbc(CRYPTO_Type *base, cy_en_crypto_status_t Cy_Crypto_Core_V1_Aes_Cfb(CRYPTO_Type *base, cy_en_crypto_dir_mode_t dirMode, uint32_t srcSize, - uint8_t const *ivPtr, + uint8_t *ivPtr, uint8_t *dst, uint8_t const *src, cy_stc_crypto_aes_state_t *aesState) @@ -442,6 +472,9 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Aes_Cfb(CRYPTO_Type *base, size -= CY_CRYPTO_AES_BLOCK_SIZE; } + /* Copies the local encode buffer to the Initialization Vector. */ + Cy_Crypto_Core_V1_MemCpy(base, ivPtr, encBuff, CY_CRYPTO_AES_BLOCK_SIZE); + tmpResult = CY_CRYPTO_SUCCESS; } @@ -465,7 +498,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Aes_Cfb(CRYPTO_Type *base, * current cipher stream. * * \param ivPtr -* The 128-bit initial vector and counter. +* The 128-bit initial vector that contains a 64-bit nonce and 64-bit counter. * * \param streamBlock * The saved stream-block for resuming. Is over-written by the function. @@ -494,12 +527,12 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Aes_Ctr(CRYPTO_Type *base, uint8_t const *src, cy_stc_crypto_aes_state_t *aesState) { - uint32_t cnt; uint32_t i; + uint32_t cnt; uint64_t counter; + uint32_t blockCounter[CY_CRYPTO_AES_BLOCK_SIZE_U32] = { 0UL }; cy_stc_crypto_aes_buffers_t *aesBuffers = (cy_stc_crypto_aes_buffers_t*)aesState->buffers; - uint32_t *blockCounter = (uint32_t*)(&aesBuffers->iv); uint32_t *srcBuff = (uint32_t*)(&aesBuffers->block0); uint32_t *dstBuff = (uint32_t*)(&aesBuffers->block1); uint32_t *streamBuff = (uint32_t*)(&aesBuffers->block2); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_aes_v2.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_aes_v2.c index 173e232774..03763844d9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_aes_v2.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_aes_v2.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_aes_v2.c -* \version 2.20 +* \version 2.30 * * \brief * This file provides the source code fro the API for the AES method @@ -58,7 +58,7 @@ void Cy_Crypto_Core_V2_Aes_LoadEncKey(CRYPTO_Type *base, /* Set the key mode: 128, 192 or 256 Bit */ uint32_t keySize = CY_CRYPTO_AES_128_KEY_SIZE + ((uint32_t)aesState->keyLength * 8u); - Cy_Crypto_Core_V2_FFContinue(base, CY_CRYPTO_V2_RB_FF_LOAD0, aesState->key, keySize); + Cy_Crypto_Core_V2_FFContinue(base, CY_CRYPTO_V2_RB_FF_LOAD0, (uint8_t *)aesState->buffers->key, keySize); Cy_Crypto_Core_V2_BlockMov (base, CY_CRYPTO_V2_RB_KEY0, CY_CRYPTO_V2_RB_FF_LOAD0, CY_CRYPTO_AES_128_KEY_SIZE); keySize -= CY_CRYPTO_AES_128_KEY_SIZE; @@ -68,6 +68,8 @@ void Cy_Crypto_Core_V2_Aes_LoadEncKey(CRYPTO_Type *base, Cy_Crypto_Core_V2_BlockMov(base, CY_CRYPTO_V2_RB_KEY1, CY_CRYPTO_V2_RB_FF_LOAD0, keySize); } + REG_CRYPTO_AES_CTL(base) = (uint32_t)(_VAL2FLD(CRYPTO_AES_CTL_KEY_SIZE, aesState->keyLength)); + Cy_Crypto_Core_WaitForReady(base); } @@ -107,6 +109,31 @@ void Cy_Crypto_Core_V2_Aes_LoadDecKey(CRYPTO_Type *base, Cy_Crypto_Core_WaitForReady(base); } +/******************************************************************************* +* Function Name: Cy_Crypto_Core_V2_Aes_Free +****************************************************************************//** +* +* Clears AES operation context. +* +* \param base +* The pointer to the CRYPTO instance. +* +* \param aesState +* The pointer to the AES state structure allocated by the user. The user +* must not modify anything in this structure. +* +* \return +* \ref cy_en_crypto_status_t +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Core_V2_Aes_Free(CRYPTO_Type *base, cy_stc_crypto_aes_state_t *aesState) +{ + Cy_Crypto_Core_V2_MemSet(base, (void *)aesState->buffers, 0u, sizeof(cy_stc_crypto_aes_buffers_t)); + Cy_Crypto_Core_V2_MemSet(base, (void *)aesState, 0u, sizeof(cy_stc_crypto_aes_state_t)); + + return (CY_CRYPTO_SUCCESS); +} + /******************************************************************************* * Function Name: Cy_Crypto_Core_V2_Aes_Init ****************************************************************************//** @@ -126,6 +153,9 @@ void Cy_Crypto_Core_V2_Aes_LoadDecKey(CRYPTO_Type *base, * The pointer to the AES state structure allocated by the user. The user * must not modify anything in this structure. * +* \param aesBuffers +* The pointer to the memory buffers storage. +* * \return * \ref cy_en_crypto_status_t * @@ -133,18 +163,22 @@ void Cy_Crypto_Core_V2_Aes_LoadDecKey(CRYPTO_Type *base, cy_en_crypto_status_t Cy_Crypto_Core_V2_Aes_Init(CRYPTO_Type *base, uint8_t const *key, cy_en_crypto_aes_key_length_t keyLength, - cy_stc_crypto_aes_state_t *aesState) + cy_stc_crypto_aes_state_t *aesState, + cy_stc_crypto_aes_buffers_t *aesBuffers) { CY_ASSERT_L1(NULL != key); CY_ASSERT_L1(NULL != aesState); + CY_ASSERT_L1(NULL != aesBuffers); CY_ASSERT_L3(CY_CRYPTO_IS_KEYLENGTH_VALID(keyLength)); + uint16_t keySize = CY_CRYPTO_AES_128_KEY_SIZE + ((uint16_t)keyLength * 8u); + Cy_Crypto_Core_V2_MemSet(base, aesState, 0u, sizeof(cy_stc_crypto_aes_state_t)); - aesState->key = (uint8_t *)key; + aesState->buffers = (cy_stc_crypto_aes_buffers_t*) aesBuffers; aesState->keyLength = keyLength; - REG_CRYPTO_AES_CTL(base) = (uint32_t)(_VAL2FLD(CRYPTO_AES_CTL_KEY_SIZE, aesState->keyLength)); + Cy_Crypto_Core_V2_MemCpy(base, aesState->buffers->key, key, keySize); return (CY_CRYPTO_SUCCESS); } @@ -235,12 +269,13 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Aes_Ecb(CRYPTO_Type *base, cy_en_crypto_status_t Cy_Crypto_Core_V2_Aes_Cbc(CRYPTO_Type *base, cy_en_crypto_dir_mode_t dirMode, uint32_t srcSize, - uint8_t const *ivPtr, + uint8_t *ivPtr, uint8_t *dst, uint8_t const *src, cy_stc_crypto_aes_state_t *aesState) { uint32_t size = srcSize; + uint32_t ivBlockId = CY_CRYPTO_V2_RB_BLOCK1; cy_en_crypto_status_t tmpResult = CY_CRYPTO_SIZE_NOT_X16; /* Check whether the data size is multiple of CY_CRYPTO_AES_BLOCK_SIZE */ @@ -257,12 +292,15 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Aes_Cbc(CRYPTO_Type *base, if (CY_CRYPTO_ENCRYPT == dirMode) { + ivBlockId = CY_CRYPTO_V2_RB_BLOCK1; + + /* Load the Initialization Vector to the local buffer */ Cy_Crypto_Core_V2_BlockMov(base, CY_CRYPTO_V2_RB_BLOCK1, CY_CRYPTO_V2_RB_FF_LOAD1, CY_CRYPTO_AES_BLOCK_SIZE); while (size != 0U) { - Cy_Crypto_Core_V2_BlockXor(base, CY_CRYPTO_V2_RB_BLOCK0, CY_CRYPTO_V2_RB_FF_LOAD0, - CY_CRYPTO_V2_RB_BLOCK1, CY_CRYPTO_AES_BLOCK_SIZE); + Cy_Crypto_Core_V2_BlockXor(base, CY_CRYPTO_V2_RB_BLOCK0, + CY_CRYPTO_V2_RB_FF_LOAD0, CY_CRYPTO_V2_RB_BLOCK1, CY_CRYPTO_AES_BLOCK_SIZE); Cy_Crypto_Core_V2_RunAes(base); Cy_Crypto_Core_V2_BlockMov(base, CY_CRYPTO_V2_RB_FF_STORE, CY_CRYPTO_V2_RB_BLOCK1, CY_CRYPTO_AES_BLOCK_SIZE); @@ -271,25 +309,36 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Aes_Cbc(CRYPTO_Type *base, } else { + ivBlockId = CY_CRYPTO_V2_RB_BLOCK2; + + /* Load the Initialization Vector to the temporary buffer */ Cy_Crypto_Core_V2_BlockMov(base, CY_CRYPTO_V2_RB_BLOCK2, CY_CRYPTO_V2_RB_FF_LOAD1, CY_CRYPTO_AES_BLOCK_SIZE); while (size != 0U) { Cy_Crypto_Core_V2_BlockMov(base, CY_CRYPTO_V2_RB_BLOCK0, CY_CRYPTO_V2_RB_FF_LOAD0, CY_CRYPTO_AES_BLOCK_SIZE); Cy_Crypto_Core_V2_RunAesInv(base); - Cy_Crypto_Core_V2_BlockXor(base, CY_CRYPTO_V2_RB_FF_STORE, CY_CRYPTO_V2_RB_BLOCK1, - CY_CRYPTO_V2_RB_BLOCK2, CY_CRYPTO_AES_BLOCK_SIZE); + Cy_Crypto_Core_V2_BlockXor(base, CY_CRYPTO_V2_RB_FF_STORE, + CY_CRYPTO_V2_RB_BLOCK1, CY_CRYPTO_V2_RB_BLOCK2, CY_CRYPTO_AES_BLOCK_SIZE); + + /* temporary cipher block */ Cy_Crypto_Core_V2_BlockMov(base, CY_CRYPTO_V2_RB_BLOCK2, CY_CRYPTO_V2_RB_BLOCK0, CY_CRYPTO_AES_BLOCK_SIZE); size -= CY_CRYPTO_AES_BLOCK_SIZE; } } + Cy_Crypto_Core_V2_Sync(base); + + /* Copy the local Initialization Vector to the external Initialization Vector */ + Cy_Crypto_Core_V2_FFStart (base, CY_CRYPTO_V2_RB_FF_STORE, ivPtr, CY_CRYPTO_AES_BLOCK_SIZE); + Cy_Crypto_Core_V2_BlockMov(base, CY_CRYPTO_V2_RB_FF_STORE, ivBlockId, CY_CRYPTO_AES_BLOCK_SIZE); + + Cy_Crypto_Core_V2_Sync(base); + tmpResult = CY_CRYPTO_SUCCESS; } - Cy_Crypto_Core_WaitForReady(base); - return (tmpResult); } @@ -329,7 +378,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Aes_Cbc(CRYPTO_Type *base, cy_en_crypto_status_t Cy_Crypto_Core_V2_Aes_Cfb(CRYPTO_Type *base, cy_en_crypto_dir_mode_t dirMode, uint32_t srcSize, - uint8_t const *ivPtr, + uint8_t *ivPtr, uint8_t *dst, uint8_t const *src, cy_stc_crypto_aes_state_t *aesState) @@ -343,6 +392,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Aes_Cfb(CRYPTO_Type *base, { Cy_Crypto_Core_V2_Aes_LoadEncKey(base, aesState); + /* Load the Initialization Vector to the src buffer */ Cy_Crypto_Core_V2_FFContinue(base, CY_CRYPTO_V2_RB_FF_LOAD1, ivPtr, CY_CRYPTO_AES_BLOCK_SIZE); Cy_Crypto_Core_V2_BlockMov (base, CY_CRYPTO_V2_RB_BLOCK0, CY_CRYPTO_V2_RB_FF_LOAD1, CY_CRYPTO_AES_BLOCK_SIZE); @@ -354,8 +404,8 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Aes_Cfb(CRYPTO_Type *base, while (size != 0U) { Cy_Crypto_Core_V2_RunAes(base); - Cy_Crypto_Core_V2_BlockXor(base, CY_CRYPTO_V2_RB_BLOCK0, CY_CRYPTO_V2_RB_FF_LOAD0, - CY_CRYPTO_V2_RB_BLOCK1, CY_CRYPTO_AES_BLOCK_SIZE); + Cy_Crypto_Core_V2_BlockXor(base, CY_CRYPTO_V2_RB_BLOCK0, + CY_CRYPTO_V2_RB_FF_LOAD0, CY_CRYPTO_V2_RB_BLOCK1, CY_CRYPTO_AES_BLOCK_SIZE); Cy_Crypto_Core_V2_BlockMov(base, CY_CRYPTO_V2_RB_FF_STORE, CY_CRYPTO_V2_RB_BLOCK0, CY_CRYPTO_AES_BLOCK_SIZE); size -= CY_CRYPTO_AES_BLOCK_SIZE; @@ -367,18 +417,24 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Aes_Cfb(CRYPTO_Type *base, { Cy_Crypto_Core_V2_RunAes(base); Cy_Crypto_Core_V2_BlockMov(base, CY_CRYPTO_V2_RB_BLOCK0, CY_CRYPTO_V2_RB_FF_LOAD0, CY_CRYPTO_AES_BLOCK_SIZE); - Cy_Crypto_Core_V2_BlockXor(base, CY_CRYPTO_V2_RB_FF_STORE, CY_CRYPTO_V2_RB_BLOCK1, - CY_CRYPTO_V2_RB_BLOCK0, CY_CRYPTO_AES_BLOCK_SIZE); + Cy_Crypto_Core_V2_BlockXor(base, CY_CRYPTO_V2_RB_FF_STORE, + CY_CRYPTO_V2_RB_BLOCK1, CY_CRYPTO_V2_RB_BLOCK0, CY_CRYPTO_AES_BLOCK_SIZE); size -= CY_CRYPTO_AES_BLOCK_SIZE; } } + Cy_Crypto_Core_V2_Sync(base); + + /* Copy the local Initialization Vector to the external Initialization Vector */ + Cy_Crypto_Core_V2_FFStart (base, CY_CRYPTO_V2_RB_FF_STORE, ivPtr, CY_CRYPTO_AES_BLOCK_SIZE); + Cy_Crypto_Core_V2_BlockMov(base, CY_CRYPTO_V2_RB_FF_STORE, CY_CRYPTO_V2_RB_BLOCK0, CY_CRYPTO_AES_BLOCK_SIZE); + + Cy_Crypto_Core_V2_Sync(base); + tmpResult = CY_CRYPTO_SUCCESS; } - Cy_Crypto_Core_WaitForReady(base); - return (tmpResult); } @@ -399,7 +455,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Aes_Cfb(CRYPTO_Type *base, * current cipher stream. * * \param ivPtr -* The 128-bit nonce and counter (16 bytes). +* The 128-bit initial vector that contains a 64-bit nonce and 64-bit counter. * * \param streamBlock * The saved stream-block for resuming. Is over-written by the function. @@ -428,21 +484,21 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Aes_Ctr(CRYPTO_Type *base, uint8_t const *src, cy_stc_crypto_aes_state_t *aesState) { - uint32_t blockCounter[4]; + uint32_t blockCounter[CY_CRYPTO_AES_BLOCK_SIZE_U32] = { 0UL }; uint64_t counter; uint32_t cnt; uint32_t i; - blockCounter[ 0] = (uint32_t) CY_CRYPTO_MERGE_BYTES(ivPtr[ 3], ivPtr[ 2], ivPtr[ 1], ivPtr[0]); - blockCounter[ 1] = (uint32_t) CY_CRYPTO_MERGE_BYTES(ivPtr[ 7], ivPtr[ 6], ivPtr[ 5], ivPtr[4]); - blockCounter[ 2] = (uint32_t) CY_CRYPTO_MERGE_BYTES(ivPtr[11], ivPtr[10], ivPtr[ 9], ivPtr[8]); + blockCounter[ 0] = (uint32_t) CY_CRYPTO_MERGE_BYTES(ivPtr[ 3], ivPtr[ 2], ivPtr[ 1], ivPtr[ 0]); + blockCounter[ 1] = (uint32_t) CY_CRYPTO_MERGE_BYTES(ivPtr[ 7], ivPtr[ 6], ivPtr[ 5], ivPtr[ 4]); + blockCounter[ 2] = (uint32_t) CY_CRYPTO_MERGE_BYTES(ivPtr[11], ivPtr[10], ivPtr[ 9], ivPtr[ 8]); blockCounter[ 3] = (uint32_t) CY_CRYPTO_MERGE_BYTES(ivPtr[15], ivPtr[14], ivPtr[13], ivPtr[12]); counter = CY_SWAP_ENDIAN64(*(uint64_t*)(blockCounter + CY_CRYPTO_AES_CTR_CNT_POS)); Cy_Crypto_Core_V2_Aes_LoadEncKey(base, aesState); - Cy_Crypto_Core_V2_FFContinue(base, CY_CRYPTO_V2_RB_FF_LOAD1, (const uint8_t *) &blockCounter, CY_CRYPTO_AES_BLOCK_SIZE); + Cy_Crypto_Core_V2_FFContinue(base, CY_CRYPTO_V2_RB_FF_LOAD1, (const uint8_t *) &blockCounter, CY_CRYPTO_AES_BLOCK_SIZE); Cy_Crypto_Core_V2_BlockMov (base, CY_CRYPTO_V2_RB_BLOCK0, CY_CRYPTO_V2_RB_FF_LOAD1, CY_CRYPTO_AES_BLOCK_SIZE); /* CTR counter is placed into last 4 bytes of the Nonce block */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_cmac_v1.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_cmac_v1.c index 59d73f6317..71c02162aa 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_cmac_v1.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_cmac_v1.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_cmac_v1.c -* \version 2.20 +* \version 2.30 * * \brief * This file provides the source code to the API for the CMAC method @@ -283,15 +283,16 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Cmac(CRYPTO_Type *base, uint8_t *cmac, cy_stc_crypto_aes_state_t *aesState) { + cy_stc_crypto_aes_buffers_t *aesBuffers = (cy_stc_crypto_aes_buffers_t *)(Cy_Crypto_Core_GetVuMemoryAddress(base)); cy_stc_crypto_cmac_buffers_t *cmacBuffers = - (cy_stc_crypto_cmac_buffers_t *)((uint8_t*)REG_CRYPTO_MEM_BUFF(base) + sizeof(cy_stc_crypto_aes_buffers_t)); + (cy_stc_crypto_cmac_buffers_t *)((uint8_t*)aesBuffers + sizeof(cy_stc_crypto_aes_buffers_t)); uint32_t *myBlock = (uint32_t*)(&cmacBuffers->block0); uint32_t *myTemp = (uint32_t*)(&cmacBuffers->block1); uint32_t *myK = (uint32_t*)(&cmacBuffers->k); cy_stc_crypto_v1_cmac_state_t *myCmacState = &cmacBuffers->cmacState; - (void)Cy_Crypto_Core_V1_Aes_Init(base, key, keyLength, aesState); + (void)Cy_Crypto_Core_V1_Aes_Init(base, key, keyLength, aesState, aesBuffers); Cy_Crypto_Core_V1_Cmac_Init (myCmacState, myTemp, myBlock, myK); Cy_Crypto_Core_V1_Cmac_Start (base, aesState, myCmacState); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_cmac_v2.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_cmac_v2.c index cd10dde848..233ea76c46 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_cmac_v2.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_cmac_v2.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_cmac_v2.c -* \version 2.20 +* \version 2.30 * * \brief * This file provides the source code to the API for the CMAC method @@ -260,19 +260,18 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Cmac(CRYPTO_Type *base, cy_stc_crypto_aes_state_t *aesState) { /* Allocate space for the structure which stores the CMAC context */ - cy_stc_crypto_v2_cmac_buffers_t cmacBuffersData = { 0 }; - cy_stc_crypto_v2_cmac_buffers_t *cmacBuffers = &cmacBuffersData; + cy_stc_crypto_aes_buffers_t aesBuffersData = {{ 0 }}; + cy_stc_crypto_v2_cmac_buffers_t cmacBuffersData = {{ 0 }}; + cy_stc_crypto_v2_cmac_buffers_t *cmacBuffers = &cmacBuffersData; + cy_stc_crypto_v2_cmac_state_t *cmacStateLoc = &cmacBuffers->cmacState; - uint8_t *myK = cmacBuffers->k; - cy_stc_crypto_v2_cmac_state_t *myCmacState = &cmacBuffers->cmacState; - - (void)Cy_Crypto_Core_V2_Aes_Init(base, key, keyLength, aesState); + (void)Cy_Crypto_Core_V2_Aes_Init(base, key, keyLength, aesState, &aesBuffersData); Cy_Crypto_Core_V2_Aes_LoadEncKey(base, aesState); - Cy_Crypto_Core_V2_Cmac_Init (myCmacState, myK); - Cy_Crypto_Core_V2_Cmac_Start (base, myCmacState); - Cy_Crypto_Core_V2_Cmac_Update(base, myCmacState, message, messageSize); - Cy_Crypto_Core_V2_Cmac_Finish(base, myCmacState, cmac); + Cy_Crypto_Core_V2_Cmac_Init (cmacStateLoc, cmacBuffers->k); + Cy_Crypto_Core_V2_Cmac_Start (base, cmacStateLoc); + Cy_Crypto_Core_V2_Cmac_Update(base, cmacStateLoc, message, messageSize); + Cy_Crypto_Core_V2_Cmac_Finish(base, cmacStateLoc, cmac); return (CY_CRYPTO_SUCCESS); } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_crc_v1.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_crc_v1.c index b661fd2f4b..5febf8fac0 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_crc_v1.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_crc_v1.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_crc_v1.c -* \version 2.20 +* \version 2.30 * * \brief * This file provides the source code for CRC API diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_crc_v2.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_crc_v2.c index a27ce9b677..0bf4f332c9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_crc_v2.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_crc_v2.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_crc_v2.c -* \version 2.20 +* \version 2.30 * * \brief * This file provides the source code for CRC API diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_des_v1.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_des_v1.c index 73c53e78c1..4ee5281ce6 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_des_v1.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_des_v1.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_des_v1.c -* \version 2.20 +* \version 2.30 * * \brief * This file provides the source code fro the API for the DES method @@ -173,7 +173,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Des(CRYPTO_Type *base, uint32_t i; cy_en_crypto_status_t status = CY_CRYPTO_SUCCESS; - cy_stc_crypto_des_buffers_t *desBuffers = (cy_stc_crypto_des_buffers_t *)REG_CRYPTO_MEM_BUFF(base); + cy_stc_crypto_des_buffers_t *desBuffers = (cy_stc_crypto_des_buffers_t *)Cy_Crypto_Core_GetVuMemoryAddress(base); /* Check weak keys */ for (i = 0U; (i < CY_CRYPTO_DES_WEAK_KEY_COUNT) && (CY_CRYPTO_SUCCESS == status); i++) @@ -232,7 +232,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Tdes(CRYPTO_Type *base, uint32_t i; cy_en_crypto_status_t status = CY_CRYPTO_SUCCESS; - cy_stc_crypto_des_buffers_t *desBuffers = (cy_stc_crypto_des_buffers_t *)REG_CRYPTO_MEM_BUFF(base); + cy_stc_crypto_des_buffers_t *desBuffers = (cy_stc_crypto_des_buffers_t *)Cy_Crypto_Core_GetVuMemoryAddress(base); /* Check weak keys */ for (i = 0U; (i < CY_CRYPTO_DES_WEAK_KEY_COUNT) && (CY_CRYPTO_SUCCESS == status); i++) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_des_v2.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_des_v2.c index e1ea2b72d0..625e2f5d99 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_des_v2.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_des_v2.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_des_v2.c -* \version 2.20 +* \version 2.30 * * \brief * This file provides the source code fro the API for the DES method diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_ecc_domain_params.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_ecc_domain_params.c index f0c41ba4eb..84451d957d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_ecc_domain_params.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_ecc_domain_params.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_ecc_domain_params.c -* \version 2.20 +* \version 2.30 * * \brief * This file provides constant and parameters for the API for the ECC @@ -27,6 +27,8 @@ #include "cy_crypto_core_ecc.h" #include "cy_syslib.h" +#if defined(CY_IP_MXCRYPTO) + /******************************************************************************* * Function Name: Cy_Crypto_Core_ECC_GetCurveParams @@ -438,9 +440,7 @@ cy_stc_crypto_ecc_dp_type *Cy_Crypto_Core_ECC_GetCurveParams(cy_en_crypto_ecc_cu CY_CRYPTO_ECC_ECP_SECP521R1, CY_CRYPTO_ECC_P521_SIZE, "NIST P-521", - /* Currently driver uses CY_CRYPTO_NIST_P_BARRETT_RED_ALG algorithm instead of - curve specific CY_CRYPTO_NIST_P_CURVE_SPECIFIC_RED_ALG */ - CY_CRYPTO_NIST_P_BARRETT_RED_ALG, + CY_CRYPTO_NIST_P_CURVE_SPECIFIC_RED_ALG, /* prime: "1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" */ eccP521Polynomial, /* barrett_p: "20000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001" */ @@ -466,5 +466,6 @@ cy_stc_crypto_ecc_dp_type *Cy_Crypto_Core_ECC_GetCurveParams(cy_en_crypto_ecc_cu return tmpResult; } +#endif /* CY_IP_MXCRYPTO */ /* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_ecc_ecdsa.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_ecc_ecdsa.c index 9ab6d7f46b..13cab3e0e8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_ecc_ecdsa.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_ecc_ecdsa.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_ecc_ecdsa.c -* \version 2.20 +* \version 2.30 * * \brief * This file provides constant and parameters for the API for the ECC ECDSA @@ -29,8 +29,7 @@ #include "cy_crypto_core_mem.h" #include "cy_crypto_core_vu.h" -#include - +#if defined(CY_IP_MXCRYPTO) /******************************************************************************* * Function Name: Cy_Crypto_Core_ECC_SignHash @@ -42,7 +41,7 @@ * The pointer to a Crypto instance. * * \param hash -* The message digest to sign. +* The message digest to sign. Provided as is in data buffer. * * \param hashlen * The length of the digest in bytes. @@ -70,7 +69,6 @@ cy_en_crypto_status_t Cy_Crypto_Core_ECC_SignHash(CRYPTO_Type *base, const uint8 const cy_stc_crypto_ecc_dp_type *eccDp; uint32_t mallocMask = 0U; - uint32_t bitsize; /* NULL parameters checking */ if ((hash != NULL) && (sig != NULL) && (key != NULL) && (messageKey != NULL)) @@ -81,7 +79,9 @@ cy_en_crypto_status_t Cy_Crypto_Core_ECC_SignHash(CRYPTO_Type *base, const uint8 if (eccDp != NULL) { - bitsize = eccDp->size; + uint32_t bitsize = eccDp->size; + uint32_t bytesize = CY_CRYPTO_BYTE_SIZE_OF_BITS(eccDp->size); + uint32_t datasize = hashlen; /* make ephemeral key pair */ ephKey.pubkey.x = myKGX; @@ -107,31 +107,29 @@ cy_en_crypto_status_t Cy_Crypto_Core_ECC_SignHash(CRYPTO_Type *base, const uint8 Cy_Crypto_Core_Vu_SetMemValue (base, VR_BARRETT, (uint8_t *)eccDp->barrett_o, bitsize); CY_CRYPTO_VU_ALLOC_MEM (base, p_r, bitsize); + CY_CRYPTO_VU_ALLOC_MEM (base, p_s, bitsize); Cy_Crypto_Core_Vu_SetMemValue (base, p_r, (uint8_t *)ephKey.pubkey.x, bitsize); - mallocMask = CY_CRYPTO_VU_REG_BIT(VR_P) | CY_CRYPTO_VU_REG_BIT(VR_BARRETT) | CY_CRYPTO_VU_REG_BIT(p_r); + mallocMask = CY_CRYPTO_VU_REG_BIT(VR_P) | CY_CRYPTO_VU_REG_BIT(VR_BARRETT) | + CY_CRYPTO_VU_REG_BIT(p_r) | CY_CRYPTO_VU_REG_BIT(p_s); if (!Cy_Crypto_Core_Vu_IsRegZero(base, p_r)) { tmpResult = CY_CRYPTO_SUCCESS; - CY_CRYPTO_VU_ALLOC_MEM (base, p_d, bitsize); - CY_CRYPTO_VU_ALLOC_MEM (base, p_s, bitsize); - - mallocMask |= CY_CRYPTO_VU_REG_BIT(p_d) | CY_CRYPTO_VU_REG_BIT(p_s); + CY_CRYPTO_VU_ALLOC_MEM (base, p_temp, bitsize); + CY_CRYPTO_VU_ALLOC_MEM (base, p_d, datasize * 8u); /* check that x1 is smaller than the order of the base point */ if (!Cy_Crypto_Core_Vu_IsRegLess(base, p_r, VR_P)) { /* x1 >= order, needs reduction */ - CY_CRYPTO_VU_ALLOC_MEM (base, p_temp, bitsize); CY_CRYPTO_VU_MOV(base, p_temp, p_r); + Cy_Crypto_Core_Vu_WaitForComplete(base); /* z = x % mod */ Cy_Crypto_Core_EC_Bar_MulRed(base, p_r, p_temp, bitsize); - CY_CRYPTO_VU_FREE_MEM(base, CY_CRYPTO_VU_REG_BIT(p_temp)); - /* r = x1 mod n */ Cy_Crypto_Core_Vu_GetMemValue (base, sig, p_r, bitsize); @@ -143,36 +141,43 @@ cy_en_crypto_status_t Cy_Crypto_Core_ECC_SignHash(CRYPTO_Type *base, const uint8 } else { - /* carry is clear, i. e. x1 < order */ - /* r = x1 */ - Cy_Crypto_Core_MemCpy(base, sig, ephKey.pubkey.x, (uint16_t)CY_CRYPTO_BYTE_SIZE_OF_BITS(bitsize)); + /* carry is clear, i. e. x1 < order, r = x1 */ + Cy_Crypto_Core_Vu_GetMemValue(base, sig, p_r, bitsize); } if (CY_CRYPTO_SUCCESS == tmpResult) { /* find s = (e + d*r)/k */ - /* load signing private key */ - Cy_Crypto_Core_Vu_SetMemValue (base, p_d, (uint8_t *)key->k, bitsize); + Cy_Crypto_Core_Vu_SetMemValue (base, p_temp, (uint8_t *)key->k, bitsize); /* use Barrett reduction algorithm for operations modulo n (order of the base point) */ Cy_Crypto_Core_EC_NistP_SetRedAlg(CY_CRYPTO_NIST_P_BARRETT_RED_ALG); /* d*r mod n */ - Cy_Crypto_Core_EC_MulMod(base, p_s, p_d, p_r, bitsize); /* z = a * b % mod */ + Cy_Crypto_Core_EC_MulMod(base, p_s, p_temp, p_r, bitsize); /* z = a * b % mod */ - /* load message hash, truncate it if needed */ - CY_CRYPTO_VU_SET_TO_ZERO(base, p_d); + /* load message hash, truncate it if needed. */ + Cy_Crypto_Core_Vu_SetMemValue (base, p_d, (uint8_t *)hash, datasize * 8u); + Cy_Crypto_Core_VU_RegInvertEndianness(base, p_d); - if ((hashlen * 8u) > bitsize) + if ((datasize * 8u) > bitsize) { - Cy_Crypto_Core_Vu_SetMemValue (base, p_d, (uint8_t *)(&hash[hashlen - CY_CRYPTO_BYTE_SIZE_OF_BITS(bitsize)]), bitsize); - } - else - { - Cy_Crypto_Core_Vu_SetMemValue (base, p_d, (uint8_t *)hash, hashlen * 8U); + CY_CRYPTO_VU_SET_REG(base, dividend, (datasize * 8u) - bitsize, 1u); + CY_CRYPTO_VU_LSR(base, p_d, p_d, dividend); } + /* check that the prepared hash value is smaller than the order of base point */ + if (!Cy_Crypto_Core_Vu_IsRegLess(base, p_d, VR_P)) + { + CY_CRYPTO_VU_MOV(base, p_temp, p_d); + Cy_Crypto_Core_Vu_WaitForComplete(base); + + /* z = x % mod */ + Cy_Crypto_Core_EC_Bar_MulRed(base, p_d, p_temp, bitsize); + } + + /* Use p_r as temporary register */ Cy_Crypto_Core_Vu_SetMemValue (base, p_r, messageKey, bitsize); /* e + d*r mod n */ @@ -180,7 +185,9 @@ cy_en_crypto_status_t Cy_Crypto_Core_ECC_SignHash(CRYPTO_Type *base, const uint8 /* (e + d*r)/k mod n */ CY_CRYPTO_VU_ALLOC_MEM (base, dividend, bitsize); + CY_CRYPTO_VU_MOV(base, dividend, p_s); + Cy_Crypto_Core_Vu_WaitForComplete(base); /* z = a / b % mod */ Cy_Crypto_Core_EC_DivMod(base, p_s, dividend, p_r, bitsize); @@ -190,7 +197,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_ECC_SignHash(CRYPTO_Type *base, const uint8 if (!Cy_Crypto_Core_Vu_IsRegZero(base, p_s)) { /* S is not zero!!! */ - Cy_Crypto_Core_Vu_GetMemValue (base, &sig[CY_CRYPTO_BYTE_SIZE_OF_BITS(bitsize)], p_s, bitsize); + Cy_Crypto_Core_Vu_GetMemValue (base, &sig[bytesize], p_s, bitsize); } else { @@ -198,6 +205,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_ECC_SignHash(CRYPTO_Type *base, const uint8 } } + CY_CRYPTO_VU_FREE_MEM(base, CY_CRYPTO_VU_REG_BIT(p_d) | CY_CRYPTO_VU_REG_BIT(p_temp)); } CY_CRYPTO_VU_FREE_MEM(base, mallocMask); @@ -244,7 +252,6 @@ cy_en_crypto_status_t Cy_Crypto_Core_ECC_VerifyHash(CRYPTO_Type *base, const cy_stc_crypto_ecc_dp_type *eccDp; - uint32_t bitsize; uint32_t mallocMask = 0U; /* NULL parameters checking */ @@ -256,10 +263,12 @@ cy_en_crypto_status_t Cy_Crypto_Core_ECC_VerifyHash(CRYPTO_Type *base, if (eccDp != NULL) { - bitsize = eccDp->size; - tmpResult = CY_CRYPTO_SUCCESS; + uint32_t bitsize = eccDp->size; + uint32_t bytesize = CY_CRYPTO_BYTE_SIZE_OF_BITS(eccDp->size); + uint32_t datasize = hashlen; + uint32_t dividend = 0u; /* for whatever reason Crypto_EC_DivMod only works if dividend is in register 0 */ uint32_t p_r = 4U; uint32_t p_s = 5U; @@ -288,7 +297,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_ECC_VerifyHash(CRYPTO_Type *base, CY_CRYPTO_VU_ALLOC_MEM (base, p_r, bitsize); CY_CRYPTO_VU_ALLOC_MEM (base, p_s, bitsize); Cy_Crypto_Core_Vu_SetMemValue (base, p_r, (uint8_t *)sig, bitsize); - Cy_Crypto_Core_Vu_SetMemValue (base, p_s, (uint8_t *)&sig[CY_CRYPTO_BYTE_SIZE_OF_BITS(bitsize)], bitsize); + Cy_Crypto_Core_Vu_SetMemValue (base, p_s, (uint8_t *)&sig[bytesize], bitsize); mallocMask = CY_CRYPTO_VU_REG_BIT(VR_P) | CY_CRYPTO_VU_REG_BIT(VR_BARRETT) | CY_CRYPTO_VU_REG_BIT(p_r) | CY_CRYPTO_VU_REG_BIT(p_s); @@ -317,8 +326,6 @@ cy_en_crypto_status_t Cy_Crypto_Core_ECC_VerifyHash(CRYPTO_Type *base, if (CY_CRYPTO_SUCCESS == tmpResult) { - CY_CRYPTO_VU_ALLOC_MEM (base, dividend, bitsize); - CY_CRYPTO_VU_ALLOC_MEM (base, p_o, bitsize); CY_CRYPTO_VU_ALLOC_MEM (base, p_u1, bitsize); CY_CRYPTO_VU_ALLOC_MEM (base, p_u2, bitsize); @@ -328,20 +335,42 @@ cy_en_crypto_status_t Cy_Crypto_Core_ECC_VerifyHash(CRYPTO_Type *base, CY_CRYPTO_VU_ALLOC_MEM (base, p_qy, bitsize); mallocMask |= CY_CRYPTO_VU_REG_BIT(dividend) | - CY_CRYPTO_VU_REG_BIT(p_o) | CY_CRYPTO_VU_REG_BIT(p_u1) | CY_CRYPTO_VU_REG_BIT(p_u2) | CY_CRYPTO_VU_REG_BIT(p_gx) | CY_CRYPTO_VU_REG_BIT(p_gy) | CY_CRYPTO_VU_REG_BIT(p_qx) | CY_CRYPTO_VU_REG_BIT(p_qy); /* load message hash, truncate it if needed */ CY_CRYPTO_VU_SET_TO_ZERO(base, p_u1); - if ((hashlen * 8u) > bitsize) + + /* load message hash, truncate it if needed. */ + CY_CRYPTO_VU_ALLOC_MEM (base, p_o, datasize * 8u); + + CY_CRYPTO_VU_SET_TO_ZERO(base, p_o); + Cy_Crypto_Core_Vu_SetMemValue (base, p_o, (uint8_t *)hash, datasize * 8u); + Cy_Crypto_Core_VU_RegInvertEndianness(base, p_o); + + if ((datasize * 8u) > bitsize) { - Cy_Crypto_Core_Vu_SetMemValue (base, p_u1, (uint8_t *)(&hash[hashlen - CY_CRYPTO_BYTE_SIZE_OF_BITS(bitsize)]), bitsize); + CY_CRYPTO_VU_SET_REG(base, dividend, (datasize * 8u) - bitsize, 1u); + CY_CRYPTO_VU_LSR(base, p_o, p_o, dividend); } - else + + /* Use p_o as temporary register */ + CY_CRYPTO_VU_MOV(base, p_u1, p_o); + + CY_CRYPTO_VU_FREE_MEM(base, CY_CRYPTO_VU_REG_BIT(p_o)); + CY_CRYPTO_VU_ALLOC_MEM (base, p_o, bitsize); + CY_CRYPTO_VU_ALLOC_MEM (base, dividend, bitsize); + + /* check that the prepared hash value is smaller than the order of base point */ + if (!Cy_Crypto_Core_Vu_IsRegLess(base, p_u1, VR_P)) { - Cy_Crypto_Core_Vu_SetMemValue (base, p_u1, (uint8_t *)hash, hashlen * 8U); + /* Use p_o as temporary register */ + CY_CRYPTO_VU_MOV(base, p_o, p_u1); + Cy_Crypto_Core_Vu_WaitForComplete(base); + + /* z = x % mod */ + Cy_Crypto_Core_EC_Bar_MulRed(base, p_u1, p_o, bitsize); } /* w = s^-1 mod n */ @@ -350,6 +379,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_ECC_VerifyHash(CRYPTO_Type *base, /* u1 = e*w mod n */ Cy_Crypto_Core_EC_MulMod(base, p_u1, p_u1, p_s, bitsize); + /* u2 = r*w mod n */ Cy_Crypto_Core_EC_MulMod(base, p_u2, p_r, p_s, bitsize); @@ -358,7 +388,6 @@ cy_en_crypto_status_t Cy_Crypto_Core_ECC_VerifyHash(CRYPTO_Type *base, /* load prime, order and Barrett coefficient */ Cy_Crypto_Core_Vu_SetMemValue (base, VR_P, (uint8_t *)eccDp->prime, bitsize); - Cy_Crypto_Core_Vu_SetMemValue (base, p_o, (uint8_t *)eccDp->order, bitsize); Cy_Crypto_Core_Vu_SetMemValue (base, VR_BARRETT, (uint8_t *)eccDp->barrett_p, bitsize + 1U); /* load base Point G */ @@ -372,9 +401,6 @@ cy_en_crypto_status_t Cy_Crypto_Core_ECC_VerifyHash(CRYPTO_Type *base, /* u1 * G */ Cy_Crypto_Core_EC_NistP_PointMul(base, p_gx, p_gy, p_u1, p_o, bitsize); - /* reload order since p_o is modified by Crypto_EC_JacobianEcScalarMul_coZ */ - Cy_Crypto_Core_Vu_SetMemValue (base, p_o, (uint8_t *)eccDp->order, bitsize); - /* u2 * Qa */ Cy_Crypto_Core_EC_NistP_PointMul(base, p_qx, p_qy, p_u2, p_o, bitsize); @@ -387,6 +413,8 @@ cy_en_crypto_status_t Cy_Crypto_Core_ECC_VerifyHash(CRYPTO_Type *base, Cy_Crypto_Core_EC_SubMod (base, p_s, p_s, p_gx); /* s^2 - x1 */ Cy_Crypto_Core_EC_SubMod (base, p_s, p_s, p_qx); /* s^2 - x1 - x2 which is Px mod n */ + CY_CRYPTO_VU_FREE_MEM(base, CY_CRYPTO_VU_REG_BIT(p_o)); + if (Cy_Crypto_Core_Vu_IsRegEqual(base, p_s, p_r)) { *stat = 1u; @@ -395,7 +423,6 @@ cy_en_crypto_status_t Cy_Crypto_Core_ECC_VerifyHash(CRYPTO_Type *base, { *stat = 0u; } - } CY_CRYPTO_VU_FREE_MEM(base, mallocMask); @@ -405,5 +432,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_ECC_VerifyHash(CRYPTO_Type *base, return (tmpResult); } +#endif /* CY_IP_MXCRYPTO */ + /* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_ecc_key_gen.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_ecc_key_gen.c index 43a8018b58..b81c2e7ccb 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_ecc_key_gen.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_ecc_key_gen.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_ecc_key_gen.c -* \version 2.20 +* \version 2.30 * * \brief * This file provides constant and parameters for the API for the ECC key @@ -29,10 +29,11 @@ #include "cy_crypto_core_vu.h" #include "cy_crypto_core_trng.h" +#if defined(CY_IP_MXCRYPTO) + #define CY_ECC_CONFIG_TR_GARO_CTL 0x6C740B8DuL #define CY_ECC_CONFIG_TR_FIRO_CTL 0x52D246E1uL - /******************************************************************************* * Function Name: Cy_Crypto_Core_ECC_MakeKeyPair ****************************************************************************//** @@ -62,132 +63,17 @@ cy_en_crypto_status_t Cy_Crypto_Core_ECC_MakeKeyPair(CRYPTO_Type *base, cy_func_get_random_data_t GetRandomDataFunc, void *randomDataInfo) { - cy_en_crypto_status_t tmpResult = CY_CRYPTO_NOT_SUPPORTED; + cy_en_crypto_status_t tmpResult = CY_CRYPTO_BAD_PARAMS; - cy_stc_crypto_ecc_dp_type *eccDp = Cy_Crypto_Core_ECC_GetCurveParams(curveID); - - if ((eccDp != NULL) && (key != NULL)) + if ((key != NULL) && (key->k != NULL) && (key->pubkey.x != NULL) && (key->pubkey.y != NULL)) { - tmpResult = CY_CRYPTO_SUCCESS; + tmpResult = Cy_Crypto_Core_ECC_MakePrivateKey(base, curveID, key->k, GetRandomDataFunc, randomDataInfo); + } - uint32_t bitsize = eccDp->size; - - /* used VU registers. Same values as in crypto_NIST_P.c */ - uint32_t p_temp = 8u; /* temporal values */ - uint32_t p_order = 9u; /* order of the curve */ - uint32_t p_d = 10u; /* private key */ - uint32_t p_x = 11u; /* x coordinate */ - uint32_t p_y = 12u; /* y coordinate */ - - CY_CRYPTO_VU_ALLOC_MEM(base, VR_P, bitsize); - CY_CRYPTO_VU_ALLOC_MEM(base, p_order, bitsize); - CY_CRYPTO_VU_ALLOC_MEM(base, VR_BARRETT, bitsize + 1U); - CY_CRYPTO_VU_ALLOC_MEM(base, p_x, bitsize); - CY_CRYPTO_VU_ALLOC_MEM(base, p_y, bitsize); - - /*************************************************************** - * Apply domain parameters - ***************************************************************/ - /* load prime and order defining the curve as well as the Barrett coefficient. */ - - /* P and BARRETT_U are "globally" defined in cy_crypto_core_ecc.h */ - Cy_Crypto_Core_Vu_SetMemValue (base, VR_P, eccDp->prime, bitsize); - Cy_Crypto_Core_Vu_SetMemValue (base, p_order, eccDp->order, bitsize); - Cy_Crypto_Core_Vu_SetMemValue (base, VR_BARRETT, eccDp->barrett_p, bitsize + 1U); - - /* Base Point, G = (p_x, p_y) */ - Cy_Crypto_Core_Vu_SetMemValue (base, p_x, eccDp->Gx, bitsize); - Cy_Crypto_Core_Vu_SetMemValue (base, p_y, eccDp->Gy, bitsize); - - Cy_Crypto_Core_EC_NistP_SetMode(bitsize); - Cy_Crypto_Core_EC_NistP_SetRedAlg(eccDp->algo); - - /*************************************************************** - * generate random string - ***************************************************************/ - if (GetRandomDataFunc != NULL) - { - (void)GetRandomDataFunc( randomDataInfo, (uint8_t*)key->k, ((bitsize + 7U) >> 3U) ); - } - else - { - uint32_t i = 0U; - int32_t randomsize = (int32_t)bitsize; - cy_en_crypto_status_t status = CY_CRYPTO_SUCCESS; - - while ((randomsize > 0) && (CY_CRYPTO_SUCCESS == status)) - { - uint32_t randombits = (uint32_t)CY_CRYPTO_MIN(randomsize, 32); - - status = Cy_Crypto_Core_Trng(base, CY_ECC_CONFIG_TR_GARO_CTL, CY_ECC_CONFIG_TR_FIRO_CTL, - randombits, &((uint32_t *)key->k)[i]); - randomsize -= 32; - i++; - - if (CY_CRYPTO_SUCCESS != status) - { - tmpResult = CY_CRYPTO_HW_ERROR; - } - } - } - - if (CY_CRYPTO_SUCCESS == tmpResult) - { - /*************************************************************** - * Load random data into VU - ***************************************************************/ - CY_CRYPTO_VU_ALLOC_MEM(base, p_d, bitsize); - Cy_Crypto_Core_Vu_SetMemValue(base, p_d, (uint8_t *)key->k, bitsize); - - /* check that the key is smaller than the order of base point */ - CY_CRYPTO_VU_CMP_SUB (base, p_d, p_order); /* C = (a >= b) */ - uint32_t status = Cy_Crypto_Core_Vu_StatusRead(base); - - if (0u != (status & CY_CRYPTO_VU_STATUS_CARRY_BIT)) - { - /* random data >= order, needs reduction */ - - CY_CRYPTO_VU_PUSH_REG(base); - - /* load values needed for reduction modulo curve order */ - CY_CRYPTO_VU_ALLOC_MEM(base, VR_P, bitsize); - Cy_Crypto_Core_Vu_SetMemValue (base, VR_P, eccDp->order, bitsize); - - CY_CRYPTO_VU_ALLOC_MEM(base, VR_BARRETT, bitsize + 1u); - Cy_Crypto_Core_Vu_SetMemValue (base, VR_BARRETT, eccDp->barrett_o, bitsize + 1u); - - CY_CRYPTO_VU_ALLOC_MEM(base, p_temp, bitsize); - CY_CRYPTO_VU_MOV(base, p_temp, p_d); - - /* z = x % mod */ - Cy_Crypto_Core_EC_Bar_MulRed(base, p_d, p_temp, bitsize); - - CY_CRYPTO_VU_FREE_MEM(base, CY_CRYPTO_VU_REG_BIT(p_temp) | CY_CRYPTO_VU_REG_BIT(VR_P) | CY_CRYPTO_VU_REG_BIT(VR_BARRETT)); - - Cy_Crypto_Core_Vu_GetMemValue(base, (uint8_t *)key->k, p_d, bitsize); - - /* restore previous prime and Barrett values */ - CY_CRYPTO_VU_POP_REG(base); - } - - /* - * Make the public key - * EC scalar multiplication - X,Y-only co-Z arithmetic - */ - Cy_Crypto_Core_EC_NistP_PointMul(base, p_x, p_y, p_d, p_order, bitsize); - - Cy_Crypto_Core_Vu_GetMemValue(base, (uint8_t *)key->pubkey.x, p_x, bitsize); - Cy_Crypto_Core_Vu_GetMemValue(base, (uint8_t *)key->pubkey.y, p_y, bitsize); - - key->type = PK_PRIVATE; - key->curveID = curveID; - - tmpResult = CY_CRYPTO_SUCCESS; - } - - CY_CRYPTO_VU_FREE_MEM(base, CY_CRYPTO_VU_REG_BIT(VR_P) | CY_CRYPTO_VU_REG_BIT(VR_BARRETT) | - CY_CRYPTO_VU_REG_BIT(p_x) | CY_CRYPTO_VU_REG_BIT(p_y) | - CY_CRYPTO_VU_REG_BIT(p_order) | CY_CRYPTO_VU_REG_BIT(p_d)); + if (CY_CRYPTO_SUCCESS == tmpResult) + { + tmpResult = Cy_Crypto_Core_ECC_MakePublicKey(base, curveID, key->k, key); + key->type = PK_PRIVATE; } return (tmpResult); @@ -231,14 +117,24 @@ cy_en_crypto_status_t Cy_Crypto_Core_ECC_MakePrivateKey(CRYPTO_Type *base, tmpResult = CY_CRYPTO_SUCCESS; uint32_t bitsize = eccDp->size; + uint32_t bytesize = CY_CRYPTO_BYTE_SIZE_OF_BITS(bitsize); uint32_t p_temp = 8u; /* temporal values */ - uint32_t p_d = 10u; /* private key */ + uint32_t p_key = 9u; /* private key */ + + /* Load random data into VU */ + CY_CRYPTO_VU_ALLOC_MEM(base, VR_D, bitsize); + CY_CRYPTO_VU_ALLOC_MEM(base, p_key, bytesize * 8u); /* generate random string */ + uint32_t *keyRegPtr = Cy_Crypto_Core_Vu_RegMemPointer(base, p_key); + if (GetRandomDataFunc != NULL) { - (void)GetRandomDataFunc( randomDataInfo, key, ((bitsize + 7U) >> 3U) ); + if (GetRandomDataFunc( randomDataInfo, (uint8_t *)keyRegPtr, bytesize ) != 0) + { + tmpResult = CY_CRYPTO_HW_ERROR; + } } else { @@ -248,11 +144,11 @@ cy_en_crypto_status_t Cy_Crypto_Core_ECC_MakePrivateKey(CRYPTO_Type *base, while ((randomsize > 0) && (CY_CRYPTO_SUCCESS == status)) { - uint32_t randombits = (uint32_t)CY_CRYPTO_MIN(randomsize, 32); + uint32_t randombits = (uint32_t)CY_CRYPTO_MIN(randomsize, (int32_t)CY_CRYPTO_HW_REGS_WIDTH); status = Cy_Crypto_Core_Trng(base, CY_ECC_CONFIG_TR_GARO_CTL, CY_ECC_CONFIG_TR_FIRO_CTL, - randombits, &((uint32_t *)key)[i]); - randomsize -= 32; + randombits, &(keyRegPtr)[i]); + randomsize -= (int32_t)CY_CRYPTO_HW_REGS_WIDTH; i++; if (CY_CRYPTO_SUCCESS != status) @@ -264,43 +160,52 @@ cy_en_crypto_status_t Cy_Crypto_Core_ECC_MakePrivateKey(CRYPTO_Type *base, if (CY_CRYPTO_SUCCESS == tmpResult) { + Cy_Crypto_Core_VU_RegInvertEndianness(base, p_key); + + if ((bytesize * 8u) > bitsize) + { + /* Shift random data right */ + CY_CRYPTO_VU_SET_REG(base, p_temp, (bytesize * 8u) - bitsize, 1u); + CY_CRYPTO_VU_LSR(base, p_key, p_key, p_temp); + } + + CY_CRYPTO_VU_MOV(base, VR_D, p_key); + Cy_Crypto_Core_Vu_WaitForComplete(base); + /* load prime and order defining the curve as well as the barrett coefficient. */ /* P and BARRETT_U are "globally" defined in cy_crypto_core_ecc.h */ CY_CRYPTO_VU_ALLOC_MEM(base, VR_P, bitsize); - CY_CRYPTO_VU_ALLOC_MEM(base, VR_BARRETT, bitsize + 1u); Cy_Crypto_Core_Vu_SetMemValue (base, VR_P, eccDp->order, bitsize); - Cy_Crypto_Core_Vu_SetMemValue (base, VR_BARRETT, eccDp->barrett_o, bitsize + 1u); - /* Load random data into VU */ - CY_CRYPTO_VU_ALLOC_MEM(base, p_d, bitsize); - Cy_Crypto_Core_Vu_SetMemValue(base, p_d, (uint8_t *)key, bitsize); - - CY_CRYPTO_VU_ALLOC_MEM(base, p_temp, bitsize); - CY_CRYPTO_VU_MOV(base, p_temp, p_d); - - /* check that the key is smaller than the order of base point */ - CY_CRYPTO_VU_CMP_SUB (base, p_d, VR_P); /* C = (a >= b) */ - uint32_t status = Cy_Crypto_Core_Vu_StatusRead(base); - - if (0u != (status & CY_CRYPTO_VU_STATUS_CARRY_BIT)) + /* check that key is smaller than the order of the base point */ + if (!Cy_Crypto_Core_Vu_IsRegLess(base, VR_D, VR_P)) { /* private key (random data) >= order, needs reduction */ + CY_CRYPTO_VU_ALLOC_MEM(base, VR_BARRETT, bitsize + 1u); + Cy_Crypto_Core_Vu_SetMemValue (base, VR_BARRETT, eccDp->barrett_o, bitsize + 1u); + + CY_CRYPTO_VU_ALLOC_MEM(base, p_temp, bitsize); + CY_CRYPTO_VU_MOV(base, p_temp, VR_D); /* use Barrett reduction algorithm for operations modulo n (order of the base point) */ Cy_Crypto_Core_EC_NistP_SetRedAlg(eccDp->algo); Cy_Crypto_Core_EC_NistP_SetMode(bitsize); /* z = x % mod */ - Cy_Crypto_Core_EC_Bar_MulRed(base, p_d, p_temp, bitsize); + Cy_Crypto_Core_EC_Bar_MulRed(base, VR_D, p_temp, bitsize); - Cy_Crypto_Core_Vu_GetMemValue(base, (uint8_t *)key, p_d, bitsize); + CY_CRYPTO_VU_FREE_MEM(base, CY_CRYPTO_VU_REG_BIT(VR_BARRETT) | + CY_CRYPTO_VU_REG_BIT(p_temp)); } - CY_CRYPTO_VU_FREE_MEM(base, CY_CRYPTO_VU_REG_BIT(VR_P) | CY_CRYPTO_VU_REG_BIT(VR_BARRETT) | - CY_CRYPTO_VU_REG_BIT(p_d) | CY_CRYPTO_VU_REG_BIT(p_temp)); + CY_CRYPTO_VU_FREE_MEM(base, CY_CRYPTO_VU_REG_BIT(VR_P)); + + Cy_Crypto_Core_Vu_GetMemValue(base, (uint8_t *)key, VR_D, bitsize); tmpResult = CY_CRYPTO_SUCCESS; } + + CY_CRYPTO_VU_FREE_MEM(base, CY_CRYPTO_VU_REG_BIT(VR_D) | CY_CRYPTO_VU_REG_BIT(p_key)); } return (tmpResult); @@ -337,7 +242,8 @@ cy_en_crypto_status_t Cy_Crypto_Core_ECC_MakePublicKey(CRYPTO_Type *base, cy_stc_crypto_ecc_dp_type *eccDp = Cy_Crypto_Core_ECC_GetCurveParams(curveID); - if ((eccDp != NULL) && (privateKey != NULL) && (publicKey != NULL)) + if ((eccDp != NULL) && (privateKey != NULL) && (publicKey != NULL) && + (publicKey->pubkey.x != NULL) && (publicKey->pubkey.y != NULL)) { uint32_t bitsize = eccDp->size; @@ -347,8 +253,8 @@ cy_en_crypto_status_t Cy_Crypto_Core_ECC_MakePublicKey(CRYPTO_Type *base, uint32_t p_y = 12u; /* y coordinate */ /* make the public key - * EC scalar multiplication - X,Y-only co-Z arithmetic - */ + * EC scalar multiplication - X,Y-only co-Z arithmetic + */ CY_CRYPTO_VU_ALLOC_MEM(base, VR_P, bitsize); CY_CRYPTO_VU_ALLOC_MEM(base, p_order, bitsize); CY_CRYPTO_VU_ALLOC_MEM(base, VR_BARRETT, bitsize + 1u); @@ -356,10 +262,8 @@ cy_en_crypto_status_t Cy_Crypto_Core_ECC_MakePublicKey(CRYPTO_Type *base, CY_CRYPTO_VU_ALLOC_MEM(base, p_y, bitsize); /* Apply domain parameters */ - /* load prime and order defining the curve as well as the barrett coefficient. */ - - /* P and BARRETT_U are "globally" defined in cy_crypto_core_ecc.h */ + /* P and BARRETT_U are "globally" defined in cy_crypto_core_ecc.h */ Cy_Crypto_Core_Vu_SetMemValue (base, VR_P, eccDp->prime, bitsize); Cy_Crypto_Core_Vu_SetMemValue (base, p_order, eccDp->order, bitsize); Cy_Crypto_Core_Vu_SetMemValue (base, VR_BARRETT, eccDp->barrett_p, bitsize + 1u); @@ -371,7 +275,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_ECC_MakePublicKey(CRYPTO_Type *base, Cy_Crypto_Core_EC_NistP_SetMode(bitsize); Cy_Crypto_Core_EC_NistP_SetRedAlg(eccDp->algo); - /* Load random data into VU */ + /* Load private key */ CY_CRYPTO_VU_ALLOC_MEM(base, p_d, bitsize); Cy_Crypto_Core_Vu_SetMemValue(base, p_d, (uint8_t *)privateKey, bitsize); @@ -381,10 +285,12 @@ cy_en_crypto_status_t Cy_Crypto_Core_ECC_MakePublicKey(CRYPTO_Type *base, Cy_Crypto_Core_Vu_GetMemValue(base, (uint8_t *)publicKey->pubkey.y, p_y, bitsize); publicKey->type = PK_PUBLIC; - publicKey->curveID = curveID; + publicKey->curveID = curveID; - CY_CRYPTO_VU_FREE_MEM(base, CY_CRYPTO_VU_REG_BIT(VR_P) | CY_CRYPTO_VU_REG_BIT(p_order) | CY_CRYPTO_VU_REG_BIT(VR_BARRETT) | - CY_CRYPTO_VU_REG_BIT(p_x) | CY_CRYPTO_VU_REG_BIT(p_y) | CY_CRYPTO_VU_REG_BIT(p_d)); + CY_CRYPTO_VU_FREE_MEM(base, CY_CRYPTO_VU_REG_BIT(VR_P) | + CY_CRYPTO_VU_REG_BIT(p_order) | CY_CRYPTO_VU_REG_BIT(VR_BARRETT) | + CY_CRYPTO_VU_REG_BIT(p_x) | CY_CRYPTO_VU_REG_BIT(p_y) | + CY_CRYPTO_VU_REG_BIT(p_d)); tmpResult = CY_CRYPTO_SUCCESS; } @@ -392,5 +298,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_ECC_MakePublicKey(CRYPTO_Type *base, return (tmpResult); } +#endif /* CY_IP_MXCRYPTO */ + /* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_ecc_nist_p.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_ecc_nist_p.c index e73f4ddf24..b6fe6221b5 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_ecc_nist_p.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_ecc_nist_p.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_ecc.h -* \version 2.20 +* \version 2.30 * * \brief * This file provides Elliptic Curve (EC) Scalar Multiplication using (X,Y)-only, @@ -28,6 +28,8 @@ #include "cy_crypto_core_ecc.h" #include "cy_crypto_core_vu.h" +#if defined(CY_IP_MXCRYPTO) + /******************************************************************************* * Elliptic Curve (EC) Scalar Multiplication using (X,Y)-only, Co-Z arithmetic * @@ -221,8 +223,8 @@ static void Cy_Crypto_Core_EC_CS_MUL_Red_P224(CRYPTO_Type *base, uint32_t z, uin CY_CRYPTO_VU_COND_CMP_SUB (base, CY_CRYPTO_VU_COND_CC, my_z, VR_P); /* C = (z >= VR_P) */ CY_CRYPTO_VU_COND_SUB (base, CY_CRYPTO_VU_COND_CS, my_z, my_z, VR_P); /* z = z - p, if C==1 (Carry is set) */ - CY_CRYPTO_VU_FREE_MEM (base, CY_CRYPTO_VU_REG_BIT(t1) | CY_CRYPTO_VU_REG_BIT(t2) | CY_CRYPTO_VU_REG_BIT(t3)); + CY_CRYPTO_VU_POP_REG (base); } @@ -412,7 +414,6 @@ static void Cy_Crypto_Core_EC_CS_MUL_Red_P256(CRYPTO_Type *base, uint32_t z, uin CY_CRYPTO_VU_COND_CMP_SUB (base, CY_CRYPTO_VU_COND_CC, my_z, VR_P); /* C = (z >= VR_P) */ CY_CRYPTO_VU_COND_SUB (base, CY_CRYPTO_VU_COND_CS, my_z, my_z, VR_P); /* z = z - p, if C==1 (Carry is set) */ - CY_CRYPTO_VU_FREE_MEM (base, CY_CRYPTO_VU_REG_BIT(t0) | CY_CRYPTO_VU_REG_BIT(t1) | CY_CRYPTO_VU_REG_BIT(t2) | CY_CRYPTO_VU_REG_BIT(t3) | CY_CRYPTO_VU_REG_BIT(t4)); CY_CRYPTO_VU_POP_REG (base); @@ -612,10 +613,9 @@ static void Cy_Crypto_Core_EC_CS_MUL_Red_P521(CRYPTO_Type *base, uint32_t z, uin CY_CRYPTO_VU_COND_CMP_SUB (base, CY_CRYPTO_VU_COND_CC, my_z, VR_P); /* C = (t2 >= VR_P) */ CY_CRYPTO_VU_COND_SUB (base, CY_CRYPTO_VU_COND_CS, my_z, my_z, VR_P); /* t2 = t2 - p, if C==1 (Carry is set) */ - CY_CRYPTO_VU_FREE_MEM (base, CY_CRYPTO_VU_REG_BIT(t0)); - CY_CRYPTO_VU_POP_REG (base); + CY_CRYPTO_VU_POP_REG (base); } @@ -717,7 +717,6 @@ static void Cy_Crypto_Core_EC_SM_MUL_Red_P192(CRYPTO_Type *base, uint32_t z, uin CY_CRYPTO_VU_ADD (base, partial, partial, hi); /* partial = hi*(2^{64}+1) + lo */ - /* Step 3: 2nd round of shift-multiply */ CY_CRYPTO_VU_LSR (base, hi, partial, sh192); /* hi = partial >> CURVE_SIZE = partial[383:192] */ @@ -916,10 +915,10 @@ static void Cy_Crypto_Core_EC_SM_MUL_Red_P256(CRYPTO_Type *base, uint32_t z, uin /* Step 11: Final reduction (compare to P-256 and reduce if necessary, based on CARRY flag) */ CY_CRYPTO_VU_CMP_SUB (base, my_z, VR_P); /* C = (z >= VR_P) */ - CY_CRYPTO_VU_COND_SUB (base, CY_CRYPTO_VU_COND_CS, my_z, my_z, VR_P); + CY_CRYPTO_VU_COND_SUB(base, CY_CRYPTO_VU_COND_CS, my_z, my_z, VR_P); - CY_CRYPTO_VU_FREE_MEM (base, CY_CRYPTO_VU_REG_BIT(partial) | CY_CRYPTO_VU_REG_BIT(hi) | CY_CRYPTO_VU_REG_BIT(coeff)); - CY_CRYPTO_VU_POP_REG (base); + CY_CRYPTO_VU_FREE_MEM(base, CY_CRYPTO_VU_REG_BIT(partial) | CY_CRYPTO_VU_REG_BIT(hi) | CY_CRYPTO_VU_REG_BIT(coeff)); + CY_CRYPTO_VU_POP_REG(base); } @@ -1269,14 +1268,14 @@ void Cy_Crypto_Core_EC_MulMod( CRYPTO_Type *base, CY_CRYPTO_VU_ALLOC_MEM (base, ab_double, 2u * size); CY_CRYPTO_VU_UMUL (base, ab_double, my_a, my_b); + Cy_Crypto_Core_Vu_WaitForComplete(base); /* Modular Reduction: Barrett reduction or curve-specific or shift-multiply */ Cy_Crypto_Core_EC_MulRed(base, my_z, ab_double, size); - CY_CRYPTO_VU_FREE_MEM (base, CY_CRYPTO_VU_REG_BIT(ab_double)); - CY_CRYPTO_VU_POP_REG (base); + CY_CRYPTO_VU_POP_REG (base); } @@ -1333,7 +1332,6 @@ void Cy_Crypto_Core_EC_SubMod( CRYPTO_Type *base, uint32_t z, uint32_t a, uint32 } - /******************************************************************************* * Function Name: Cy_Crypto_Core_EC_HalfMod ****************************************************************************//** @@ -1461,8 +1459,6 @@ void Cy_Crypto_Core_EC_DivMod( CRYPTO_Type *base, CY_CRYPTO_VU_TST (base, my_b); status2 = Cy_Crypto_Core_Vu_StatusRead(base); - Cy_Crypto_Core_WaitForReady(base); - zero = status0 & CY_CRYPTO_VU_STATUS_ZERO_BIT; /* a == b */ carry = status0 & CY_CRYPTO_VU_STATUS_CARRY_BIT; /* a >= b */ a_even = status1 & CY_CRYPTO_VU_STATUS_EVEN_BIT; @@ -1825,11 +1821,11 @@ void Cy_Crypto_Core_JacobianEcScalarMul(CRYPTO_Type *base, uint32_t s_x, uint32_ /* Operation. */ CY_CRYPTO_VU_SET_TO_ZERO (base, clr); CY_CRYPTO_VU_CLSAME (base, t, my_d, clr); + CY_CRYPTO_VU_LSL (base, my_d, my_d, t); /* Get rid of leading '0's */ - Cy_Crypto_Core_Vu_WaitForComplete(base); - clsame = Cy_Crypto_Core_Vu_RegDataPtrRead (base, t); + CY_CRYPTO_VU_LSL1 (base, my_d, my_d); /* Get rid of leading '1' */ /* Binary left-to-right algorithm @@ -1967,22 +1963,22 @@ void Cy_Crypto_Core_EC_NistP_PointMul(CRYPTO_Type *base, uint32_t p_x, uint32_t * The pointer to a Crypto instance. * * \param curveID -* Register index for affine X coordinate of base point. +* See \ref cy_en_crypto_ecc_curve_id_t. * * \param ecpGX -* Register index for affine Y coordinate of base point. +* Register index for affine X coordinate of base point. * * \param ecpGY -* Register index for multiplication value. +* Register index for affine Y coordinate of base point. * * \param ecpD -* Register index for order value. +* Register index for multiplication value. * * \param ecpQX -* Register index for order value. +* Register index for affine X coordinate of result point. * * \param ecpQY -* Register index for order value. +* Register index for affine Y coordinate of result point. * * \return status code. See \ref cy_en_crypto_status_t. * @@ -2069,5 +2065,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_EC_NistP_PointMultiplication(CRYPTO_Type *b return myStatus; } +#endif /* CY_IP_MXCRYPTO */ + /* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_hmac_v1.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_hmac_v1.c index d5a6d3c1ea..9a0a61cedd 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_hmac_v1.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_hmac_v1.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_hmac_v1.c -* \version 2.20 +* \version 2.30 * * \brief * This file provides the source code to the API for the HMAC method @@ -310,7 +310,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Hmac(CRYPTO_Type *base, cy_en_crypto_status_t tmpResult = CY_CRYPTO_SUCCESS; /* Allocating internal variables into the CRYPTO SRAM Buffer */ - cy_stc_crypto_hmac_buffers_t *hmacBuffers = (cy_stc_crypto_hmac_buffers_t *)(REG_CRYPTO_MEM_BUFF(base)); + cy_stc_crypto_hmac_buffers_t *hmacBuffers = (cy_stc_crypto_hmac_buffers_t *)(Cy_Crypto_Core_GetVuMemoryAddress(base)); cy_stc_crypto_v1_hmac_state_t *hmacStateTmp = &hmacBuffers->hmacState; cy_stc_crypto_sha_state_t hashStateLoc = { 0 }; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_hmac_v2.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_hmac_v2.c index d00d3a4100..c7eaf1168f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_hmac_v2.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_hmac_v2.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_hmac_v2.c -* \version 2.20 +* \version 2.30 * * \brief * This file provides the source code to the API for the HMAC method @@ -55,8 +55,8 @@ typedef struct uint8_t ipad[CY_CRYPTO_HMAC_MAX_PAD_SIZE]; uint8_t opad[CY_CRYPTO_HMAC_MAX_PAD_SIZE]; uint8_t m0Key[CY_CRYPTO_SHA_MAX_BLOCK_SIZE]; + cy_stc_crypto_v2_sha512_buffers_t shaBuffers; cy_stc_crypto_v2_hmac_state_t hmacState; - cy_stc_crypto_sha_state_t hashState; } cy_stc_crypto_v2_hmac_buffers_t; /* Static fubctions declarations */ @@ -306,8 +306,8 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Hmac(CRYPTO_Type *base, { cy_en_crypto_status_t tmpResult = CY_CRYPTO_SUCCESS; - /* Allocating internal variables into the CRYPTO SRAM Buffer */ - cy_stc_crypto_v2_hmac_buffers_t hmacBuffersData = { 0 }; + /* Allocating internal variables into the RAM */ + cy_stc_crypto_v2_hmac_buffers_t hmacBuffersData = {{ 0 }}; cy_stc_crypto_v2_hmac_buffers_t *hmacBuffers = &hmacBuffersData; cy_stc_crypto_v2_hmac_state_t *hmacStateTmp = &hmacBuffers->hmacState; @@ -317,8 +317,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Hmac(CRYPTO_Type *base, uint8_t *opadTmp = (uint8_t*)&hmacBuffers->opad; uint8_t *m0KeyTmp = (uint8_t*)&hmacBuffers->m0Key; - /* No any buffers needed for Crypto_ver2 IP block */ - tmpResult = Cy_Crypto_Core_V2_Sha_Init(base, &hashStateLoc, mode, NULL); + tmpResult = Cy_Crypto_Core_V2_Sha_Init(base, &hashStateLoc, mode, &hmacBuffers->shaBuffers); if (CY_CRYPTO_SUCCESS == tmpResult) { diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_hw.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_hw.c index f8fb5f5fbb..6361e7399a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_hw.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_hw.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_hw.c -* \version 2.20 +* \version 2.30 * * \brief * This file provides the source code to the API for the utils @@ -46,6 +46,8 @@ */ const cy_stc_cryptoIP_t * cy_cryptoIP = NULL; +static uint32_t cy_cryptoVuMemSize = 0u; + /* Platform and peripheral crypto block configuration */ const cy_stc_cryptoIP_t cy_cryptoIpBlockCfgPSoC6_01 = { @@ -104,6 +106,37 @@ const cy_stc_cryptoIP_t cy_cryptoIpBlockCfgPSoC6_02 = #define CY_CRYPTO_PWR_MODE_RETAINED (2UL) #define CY_CRYPTO_PWR_MODE_ENABLED (3UL) +/******************************************************************************* +* Function Name: Cy_Crypto_Core_Vu_RunInstr +*****************************************************************************//** +* +* Run the Crypto Vector Unit instruction with one parameter. +* +* \param base +* The pointer to the CRYPTO instance. +* +* \param instr +* The Opcode of the called instruction. +* +* \param params +* The parameters for the instruction operand. +* +*******************************************************************************/ +void Cy_Crypto_Core_Vu_RunInstr(CRYPTO_Type *base, bool blockingMode, uint32_t instr, uint32_t params) +{ + bool isRelocated = Cy_Crypto_Core_GetVuMemoryAddress(base) != REG_CRYPTO_MEM_BUFF(base); + + /* Check whether FIFO has enough space for 1 instruction */ + Cy_Crypto_Core_WaitForInstrFifoAvailable(base, CY_CRYPTO_INSTR_SINGLE); + + REG_CRYPTO_INSTR_FF_WR(base) = (uint32_t)((instr << CY_CRYPTO_OPCODE_POS) | (params)); + + if ( (blockingMode) || (isRelocated) ) + { + Cy_Crypto_Core_WaitForFifoAvailable(base); + Cy_Crypto_Core_Vu_WaitForComplete(base); + } +} /** * \addtogroup group_crypto_lld_hw_functions @@ -138,6 +171,9 @@ void Cy_Crypto_Core_ClearVuRegisters(CRYPTO_Type *base) CY_CRYPTO_VU_SET_REG(base, CY_CRYPTO_VU_HW_REG2, 0u, 1u); CY_CRYPTO_VU_SET_REG(base, CY_CRYPTO_VU_HW_REG1, 0u, 1u); CY_CRYPTO_VU_SET_REG(base, CY_CRYPTO_VU_HW_REG0, 0u, 1u); + + /* Set the stack pointer to the Crypto buff size, in words */ + CY_CRYPTO_VU_SET_REG(base, CY_CRYPTO_VU_HW_REG15, cy_cryptoVuMemSize / 4u, 1u); } /******************************************************************************* @@ -149,7 +185,205 @@ void Cy_Crypto_Core_ClearVuRegisters(CRYPTO_Type *base) *******************************************************************************/ void Cy_Crypto_Core_HwInit(void) { - cy_cryptoIP = (cy_device->cryptoVersion == 1u) ? &cy_cryptoIpBlockCfgPSoC6_01 : &cy_cryptoIpBlockCfgPSoC6_02; + cy_cryptoIP = (CY_CRYPTO_V1) ? &cy_cryptoIpBlockCfgPSoC6_01 : &cy_cryptoIpBlockCfgPSoC6_02; +} + +/******************************************************************************* +* Function Name: Cy_Crypto_Core_SetVuMemoryAddress +****************************************************************************//** +* +* Sets the new memory buffer address and size. +* +* \param base +* The pointer to the CRYPTO instance. +* +* \param vuMemoryAddr +* The memory buffer location that will be used as Crypto MEM_BUFF +* +* \param vuMemorySize +* The provided memory buffer size in bytes. +* +* \return +* \ref cy_en_crypto_status_t +* +* \note This function sets the default device specific values +* when vuMemoryAddr parameter is NULL and vuMemorySize parameter is zero. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Core_SetVuMemoryAddress(CRYPTO_Type *base, + uint32_t const *vuMemoryAddr, uint32_t vuMemorySize) +{ + cy_en_crypto_status_t resultVal = CY_CRYPTO_BAD_PARAMS; + uint32_t *vuMemAddr = (uint32_t *)vuMemoryAddr; + uint32_t vuMemSize = vuMemorySize; + + if (cy_cryptoIP != NULL) + { + if ((vuMemAddr == NULL) && (vuMemSize == 0uL)) + { + vuMemAddr = REG_CRYPTO_MEM_BUFF(base); + vuMemSize = CY_CRYPTO_MEM_BUFF_SIZE; + } + + /* Check for new memory size is less or equal to maximal IP allowed value */ + if ((vuMemAddr != NULL) && (vuMemSize != 0uL) && (vuMemSize <= 32768u)) + { + /* mxcrypto (V1) IP uses MEM_BUF aligned to 16KB */ + uint32_t memAlignMask = 16384uL - 1uL; + + uint32_t memFrameMask = 0xFFFFFFFFuL; + /* + Specifies the size of the vector operand memory region. + Legal values: + "0b0000000": 32 KB memory region (VU_CTL1.ADDR[14:8] ignored). + "0b1000000": 16 KB memory region (VU_CTL1.ADDR[13:8] ignored). + "0b1100000": 8 KB memory region (VU_CTL1.ADDR[12:8] ignored). + "0b1110000": 4 KB memory region (VU_CTL1.ADDR[11:8] ignored). + "0b1111000": 2 KB memory region (VU_CTL1.ADDR[10:8] ignored). + "0b1111100": 1 KB memory region (VU_CTL1.ADDR[9:8] ignored). + "0b1111110": 512 B memory region (VU_CTL1.ADDR[8] ignored). + "0b1111111": 256 B memory region. + */ + switch (vuMemSize) + { + /* "0b0000000": 32 KB memory region (VU_CTL1.ADDR[14:8] ignored). */ + case 32768uL: + memFrameMask = 0x0u; + break; + /* "0b1000000": 16 KB memory region (VU_CTL1.ADDR[13:8] ignored). */ + case 16384uL: + memFrameMask = 0x40u; + break; + /* "0b1100000": 8 KB memory region (VU_CTL1.ADDR[12:8] ignored). */ + case 8192uL: + memFrameMask = 0x60u; + break; + /* "0b1110000": 4 KB memory region (VU_CTL1.ADDR[11:8] ignored). */ + case 4096uL: + memFrameMask = 0x70u; + break; + /* "0b1111000": 2 KB memory region (VU_CTL1.ADDR[10:8] ignored). */ + case 2048uL: + memFrameMask = 0x78u; + break; + /* "0b1111100": 1 KB memory region (VU_CTL1.ADDR[9:8] ignored). */ + case 1024uL: + memFrameMask = 0x7Cu; + break; + /* "0b1111110": 512 B memory region (VU_CTL1.ADDR[8] ignored). */ + case 512uL: + memFrameMask = 0x7Eu; + break; + /* "0b1111111": 256 B memory region (default for HW). */ + case 256uL: + memFrameMask = 0x7Fu; + break; + default: + break; + } + + if (memFrameMask != 0xFFFFFFFFuL) + { + if (!(CY_CRYPTO_V1)) + { + memAlignMask = vuMemSize - 1uL; + } + + /* Use the new address when it aligned to appropriate memory block size */ + if (((uint32_t)vuMemAddr & (memAlignMask)) == 0uL) + { + if (!(CY_CRYPTO_V1)) + { + REG_CRYPTO_VU_CTL2(base) = _VAL2FLD(CRYPTO_V2_VU_CTL2_MASK, memFrameMask); + } + + REG_CRYPTO_VU_CTL1(base) = (uint32_t)vuMemAddr; + + /* Set the stack pointer to the Crypto buff size, in words */ + CY_CRYPTO_VU_SET_REG(base, CY_CRYPTO_VU_HW_REG15, vuMemSize / 4u, 1u); + + cy_cryptoVuMemSize = vuMemSize; + + resultVal = CY_CRYPTO_SUCCESS; + } + } + } + } + + return resultVal; +} + +/******************************************************************************* +* Function Name: Cy_Crypto_Core_GetVuMemorySize +****************************************************************************//** +* +* Get Crypto memory buffer size +* +* \param base +* The pointer to the CRYPTO instance. +* +* \return +* The current MEM_BUFF size in bytes. +* +*******************************************************************************/ +uint32_t Cy_Crypto_Core_GetVuMemorySize(CRYPTO_Type *base) +{ + uint32_t memSize = CY_CRYPTO_MEM_BUFF_SIZE; + + if ( (cy_cryptoIP != NULL) && (cy_cryptoVuMemSize != 0uL)) + { + if (CY_CRYPTO_V1) + { + memSize = cy_cryptoVuMemSize; + } + else + { + uint32_t memFrameMask = _FLD2VAL(CRYPTO_V2_VU_CTL2_MASK, REG_CRYPTO_VU_CTL2(base)); + /* + Specifies the size of the vector operand memory region. + Legal values: + "0b0000000": 32 KB memory region. + "0b1000000": 16 KB memory region. + "0b1100000": 8 KB memory region. + "0b1110000": 4 KB memory region. + "0b1111000": 2 KB memory region. + "0b1111100": 1 KB memory region. + "0b1111110": 512 B memory region. + "0b1111111": 256 B memory region. + */ + switch (memFrameMask) + { + case 0x0u: + memSize = 32768uL; + break; + case 0x40u: + memSize = 16384uL; + break; + case 0x60u: + memSize = 8192uL; + break; + case 0x70u: + memSize = 4096uL; + break; + case 0x78u: + memSize = 2048uL; + break; + case 0x7Cu: + memSize = 1024uL; + break; + case 0x7Eu: + memSize = 512uL; + break; + case 0x7Fu: + memSize = 256uL; + break; + default: + break; + } + } + } + + return memSize; } /******************************************************************************* @@ -169,7 +403,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_Enable(CRYPTO_Type *base) { Cy_Crypto_Core_HwInit(); - if (CY_CRYPTO_HW_V1) + if (CY_CRYPTO_V1) { /* Enable Crypto HW */ REG_CRYPTO_CTL(base) = (uint32_t)(_VAL2FLD(CRYPTO_CTL_PWR_MODE, CY_CRYPTO_PWR_MODE_ENABLED) | @@ -181,27 +415,11 @@ cy_en_crypto_status_t Cy_Crypto_Core_Enable(CRYPTO_Type *base) REG_CRYPTO_INSTR_FF_CTL(base) = (uint32_t)(_VAL2FLD(CRYPTO_V2_INSTR_FF_CTL_BLOCK, 1u) | _VAL2FLD(CRYPTO_V2_INSTR_FF_CTL_CLEAR, 0u) - | _VAL2FLD(CRYPTO_V2_INSTR_FF_CTL_EVENT_LEVEL, 0u)); + | _VAL2FLD(CRYPTO_V2_INSTR_FF_CTL_EVENT_LEVEL, 1u)); REG_CRYPTO_CTL(base) |= _VAL2FLD(CRYPTO_V2_CTL_ENABLED, 1uL); REG_CRYPTO_RAM_PWR_CTL(base) = (uint32_t)(CY_CRYPTO_PWR_MODE_ENABLED); - - /* - Specifies the size of the vector operand memory region. - Legal values: - "0b0000000": 32 KB memory region (VU_VTL1.ADDR[14:8] ignored). - "0b1000000": 16 KB memory region (VU_VTL1.ADDR[13:8] ignored). - "0b1100000": 8 KB memory region (VU_VTL1.ADDR[12:8] ignored). - "0b1110000": 4 KB memory region (VU_VTL1.ADDR[11:8] ignored). - "0b1111000": 2 KB memory region (VU_VTL1.ADDR[10:8] ignored). - "0b1111100": 1 KB memory region (VU_VTL1.ADDR[9:8] ignored). - "0b1111110": 512 B memory region (VU_VTL1.ADDR[8] ignored). - "0b1111111": 256 B memory region. - - Used value: "0b1000000": 16 KB memory region - */ - REG_CRYPTO_VU_CTL2(base) = _VAL2FLD(CRYPTO_V2_VU_CTL2_MASK, 0x40u); } /* @@ -215,10 +433,11 @@ cy_en_crypto_status_t Cy_Crypto_Core_Enable(CRYPTO_Type *base) */ REG_CRYPTO_VU_CTL0(base) = (uint32_t)1u; - REG_CRYPTO_VU_CTL1(base) = (uint32_t)REG_CRYPTO_MEM_BUFF(base); - - /* Set the stack pointer to the Crypto buff size, in words */ - CY_CRYPTO_VU_SET_REG(base, CY_CRYPTO_VU_HW_REG15, cy_device->cryptoMemSize, 1u); + if (0uL == cy_cryptoVuMemSize) + { + /* Set the memory address and set stack pointer to the Crypto buff size, in words */ + (void)Cy_Crypto_Core_SetVuMemoryAddress(base, REG_CRYPTO_MEM_BUFF(base), CY_CRYPTO_MEM_BUFF_SIZE); + } /* Clear whole register file */ Cy_Crypto_Core_ClearVuRegisters(base); @@ -261,7 +480,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_GetLibInfo(cy_en_crypto_lib_info_t *libInfo *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Core_Disable(CRYPTO_Type *base) { - if (CY_CRYPTO_HW_V1) + if (CY_CRYPTO_V1) { /* Disable Crypto HW */ REG_CRYPTO_CTL(base) = (uint32_t)(_VAL2FLD(CRYPTO_CTL_PWR_MODE, CY_CRYPTO_PWR_MODE_OFF) | @@ -273,6 +492,8 @@ cy_en_crypto_status_t Cy_Crypto_Core_Disable(CRYPTO_Type *base) REG_CRYPTO_RAM_PWR_CTL(base) = (uint32_t)(CY_CRYPTO_PWR_MODE_OFF); } + cy_cryptoVuMemSize = 0uL; + return (CY_CRYPTO_SUCCESS); } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_hw_v1.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_hw_v1.c index b6b6946779..150cb15c8c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_hw_v1.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_hw_v1.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_hw_v1.c -* \version 2.20 +* \version 2.30 * * \brief * This file provides the source code for the HAL API for the @@ -30,8 +30,6 @@ #include "cy_syslib.h" -#define CY_CRYPTO_FIFODEPTH (0x08u) - /******************************************************************************* * Function Name: Cy_Crypto_SetReg1Instr ****************************************************************************//** @@ -49,7 +47,7 @@ void Cy_Crypto_SetReg1Instr(CRYPTO_Type *base, uint32_t data0) { /* Check whether FIFO has enough space for 1 instruction */ - while(Cy_Crypto_Core_GetFIFOUsed(base) >= (CY_CRYPTO_FIFODEPTH - 1u)) + while(Cy_Crypto_Core_GetFIFOUsed(base) >= (CY_CRYPTO_INSTR_FIFODEPTH - 1u)) { } @@ -80,7 +78,7 @@ void Cy_Crypto_SetReg1Instr(CRYPTO_Type *base, uint32_t data0) void Cy_Crypto_SetReg2Instr(CRYPTO_Type *base, uint32_t data0, uint32_t data1) { /* Check whether FIFO has enough space for 2 instructions */ - while(Cy_Crypto_Core_GetFIFOUsed(base) >= (CY_CRYPTO_FIFODEPTH - 2u)) + while(Cy_Crypto_Core_GetFIFOUsed(base) >= (CY_CRYPTO_INSTR_FIFODEPTH - 2u)) { } @@ -117,7 +115,7 @@ void Cy_Crypto_SetReg2Instr(CRYPTO_Type *base, uint32_t data0, uint32_t data1) void Cy_Crypto_SetReg3Instr(CRYPTO_Type *base, uint32_t data0, uint32_t data1, uint32_t data2) { /* Check whether FIFO has enough space for 3 instructions */ - while(Cy_Crypto_Core_GetFIFOUsed(base) >= (CY_CRYPTO_FIFODEPTH - 3u)) + while(Cy_Crypto_Core_GetFIFOUsed(base) >= (CY_CRYPTO_INSTR_FIFODEPTH - 3u)) { } @@ -160,7 +158,7 @@ void Cy_Crypto_SetReg3Instr(CRYPTO_Type *base, uint32_t data0, uint32_t data1, u void Cy_Crypto_SetReg4Instr(CRYPTO_Type *base, uint32_t data0, uint32_t data1, uint32_t data2, uint32_t data3) { /* Check whether FIFO has enough space for 4 instructions */ - while(Cy_Crypto_Core_GetFIFOUsed(base) >= (CY_CRYPTO_FIFODEPTH - 4u)) + while(Cy_Crypto_Core_GetFIFOUsed(base) >= (CY_CRYPTO_INSTR_FIFODEPTH - 4u)) { } @@ -192,7 +190,7 @@ void Cy_Crypto_SetReg4Instr(CRYPTO_Type *base, uint32_t data0, uint32_t data1, u void Cy_Crypto_Run0ParamInstr(CRYPTO_Type *base, uint8_t instr) { /* Check whether FIFO has enough space for 1 instruction */ - while(Cy_Crypto_Core_GetFIFOUsed(base) >= CY_CRYPTO_FIFODEPTH) + while(Cy_Crypto_Core_GetFIFOUsed(base) >= CY_CRYPTO_INSTR_FIFODEPTH) { } @@ -219,7 +217,7 @@ void Cy_Crypto_Run0ParamInstr(CRYPTO_Type *base, uint8_t instr) void Cy_Crypto_Run1ParamInstr(CRYPTO_Type *base, uint8_t instr, uint32_t rdst0Shift) { /* Check whether FIFO has enough space for 1 instruction */ - while(Cy_Crypto_Core_GetFIFOUsed(base) >= CY_CRYPTO_FIFODEPTH) + while(Cy_Crypto_Core_GetFIFOUsed(base) >= CY_CRYPTO_INSTR_FIFODEPTH) { } @@ -254,7 +252,7 @@ void Cy_Crypto_Run2ParamInstr(CRYPTO_Type *base, uint32_t rdst1Shift) { /* Check whether FIFO has enough space for 1 instruction */ - while(Cy_Crypto_Core_GetFIFOUsed(base) >= CY_CRYPTO_FIFODEPTH) + while(Cy_Crypto_Core_GetFIFOUsed(base) >= CY_CRYPTO_INSTR_FIFODEPTH) { } @@ -295,7 +293,7 @@ void Cy_Crypto_Run3ParamInstr(CRYPTO_Type *base, uint8_t rdst2Shift) { /* Check whether FIFO has enough space for 1 instruction */ - while(Cy_Crypto_Core_GetFIFOUsed(base) >= CY_CRYPTO_FIFODEPTH) + while(Cy_Crypto_Core_GetFIFOUsed(base) >= CY_CRYPTO_INSTR_FIFODEPTH) { } @@ -342,7 +340,7 @@ void Cy_Crypto_Run4ParamInstr(CRYPTO_Type *base, uint32_t rdst3Shift) { /* Check whether FIFO has enough space for 1 instruction */ - while(Cy_Crypto_Core_GetFIFOUsed(base) >= CY_CRYPTO_FIFODEPTH) + while(Cy_Crypto_Core_GetFIFOUsed(base) >= CY_CRYPTO_INSTR_FIFODEPTH) { } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_mem_v1.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_mem_v1.c index 90c5e07ed4..3d6973d822 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_mem_v1.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_mem_v1.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_mem_v1.c -* \version 2.20 +* \version 2.30 * * \brief * This file provides the source code to the API for the PRNG @@ -58,22 +58,25 @@ *******************************************************************************/ void Cy_Crypto_Core_V1_MemCpy(CRYPTO_Type *base, void* dst, void const *src, uint16_t size) { - /* Prepare data in the register file for next instruction */ - Cy_Crypto_SetReg3Instr(base, - (uint32_t)src, - (uint32_t)dst, - (uint32_t)size); - - /* Issue the STR_MEMCPY instruction */ - Cy_Crypto_Run3ParamInstr(base, - CY_CRYPTO_V1_STR_MEMCPY_OPC, - CY_CRYPTO_RSRC0_SHIFT, - CY_CRYPTO_RSRC4_SHIFT, - CY_CRYPTO_RSRC8_SHIFT); - - /* Wait until the STR instruction is complete */ - while (0uL != _FLD2VAL(CRYPTO_STATUS_STR_BUSY, REG_CRYPTO_STATUS(base))) + if (size != 0U) { + /* Prepare data in the register file for next instruction */ + Cy_Crypto_SetReg3Instr(base, + (uint32_t)src, + (uint32_t)dst, + (uint32_t)size); + + /* Issue the STR_MEMCPY instruction */ + Cy_Crypto_Run3ParamInstr(base, + CY_CRYPTO_V1_STR_MEMCPY_OPC, + CY_CRYPTO_RSRC0_SHIFT, + CY_CRYPTO_RSRC4_SHIFT, + CY_CRYPTO_RSRC8_SHIFT); + + /* Wait until the STR instruction is complete */ + while (0uL != _FLD2VAL(CRYPTO_STATUS_STR_BUSY, REG_CRYPTO_STATUS(base))) + { + } } } @@ -99,21 +102,24 @@ void Cy_Crypto_Core_V1_MemCpy(CRYPTO_Type *base, void* dst, void const *src, uin *******************************************************************************/ void Cy_Crypto_Core_V1_MemSet(CRYPTO_Type *base, void* dst, uint8_t data, uint16_t size) { - Cy_Crypto_SetReg3Instr(base, - (uint32_t)dst, - (uint32_t)size, - (uint32_t)data); - - /* Issue the STR_MEMSET instruction */ - Cy_Crypto_Run3ParamInstr(base, - CY_CRYPTO_V1_STR_MEMSET_OPC, - CY_CRYPTO_RSRC0_SHIFT, - CY_CRYPTO_RSRC8_SHIFT, - CY_CRYPTO_RSRC12_SHIFT); - - /* Wait until the STR instruction is complete */ - while (0uL != _FLD2VAL(CRYPTO_STATUS_STR_BUSY, REG_CRYPTO_STATUS(base))) + if (size != 0U) { + Cy_Crypto_SetReg3Instr(base, + (uint32_t)dst, + (uint32_t)size, + (uint32_t)data); + + /* Issue the STR_MEMSET instruction */ + Cy_Crypto_Run3ParamInstr(base, + CY_CRYPTO_V1_STR_MEMSET_OPC, + CY_CRYPTO_RSRC0_SHIFT, + CY_CRYPTO_RSRC8_SHIFT, + CY_CRYPTO_RSRC12_SHIFT); + + /* Wait until the STR instruction is complete */ + while (0uL != _FLD2VAL(CRYPTO_STATUS_STR_BUSY, REG_CRYPTO_STATUS(base))) + { + } } } @@ -142,24 +148,31 @@ void Cy_Crypto_Core_V1_MemSet(CRYPTO_Type *base, void* dst, uint8_t data, uint16 *******************************************************************************/ uint32_t Cy_Crypto_Core_V1_MemCmp(CRYPTO_Type *base, void const *src0, void const *src1, uint16_t size) { - Cy_Crypto_SetReg3Instr(base, - (uint32_t)src0, - (uint32_t)src1, - (uint32_t)size); + uint32_t memResult = 1U; - /* Issue the STR_MEMCMP instruction */ - Cy_Crypto_Run3ParamInstr(base, - CY_CRYPTO_V1_STR_MEMCMP_OPC, - CY_CRYPTO_RSRC0_SHIFT, - CY_CRYPTO_RSRC4_SHIFT, - CY_CRYPTO_RSRC8_SHIFT); - - /* Wait until the STR instruction is complete */ - while (0uL != _FLD2VAL(CRYPTO_STATUS_STR_BUSY, REG_CRYPTO_STATUS(base))) + if (size != 0U) { + Cy_Crypto_SetReg3Instr(base, + (uint32_t)src0, + (uint32_t)src1, + (uint32_t)size); + + /* Issue the STR_MEMCMP instruction */ + Cy_Crypto_Run3ParamInstr(base, + CY_CRYPTO_V1_STR_MEMCMP_OPC, + CY_CRYPTO_RSRC0_SHIFT, + CY_CRYPTO_RSRC4_SHIFT, + CY_CRYPTO_RSRC8_SHIFT); + + /* Wait until the STR instruction is complete */ + while (0uL != _FLD2VAL(CRYPTO_STATUS_STR_BUSY, REG_CRYPTO_STATUS(base))) + { + } + + memResult = (uint32_t)(REG_CRYPTO_STR_RESULT(base)); } - return((uint32_t)(REG_CRYPTO_STR_RESULT(base))); + return memResult; } /******************************************************************************* @@ -189,23 +202,26 @@ uint32_t Cy_Crypto_Core_V1_MemCmp(CRYPTO_Type *base, void const *src0, void cons void Cy_Crypto_Core_V1_MemXor(CRYPTO_Type *base, void* dst, void const *src0, void const *src1, uint16_t size) { - Cy_Crypto_SetReg4Instr(base, - (uint32_t)src0, - (uint32_t)src1, - (uint32_t)size, - (uint32_t)dst); - - /* Issue the STR_MEMXOR instruction */ - Cy_Crypto_Run4ParamInstr(base, - CY_CRYPTO_V1_STR_MEMXOR_OPC, - CY_CRYPTO_RSRC0_SHIFT, - CY_CRYPTO_RSRC4_SHIFT, - CY_CRYPTO_RSRC8_SHIFT, - CY_CRYPTO_RSRC12_SHIFT); - - /* Wait until the STR instruction is complete */ - while (0uL != _FLD2VAL(CRYPTO_STATUS_STR_BUSY, REG_CRYPTO_STATUS(base))) + if (size != 0U) { + Cy_Crypto_SetReg4Instr(base, + (uint32_t)src0, + (uint32_t)src1, + (uint32_t)size, + (uint32_t)dst); + + /* Issue the STR_MEMXOR instruction */ + Cy_Crypto_Run4ParamInstr(base, + CY_CRYPTO_V1_STR_MEMXOR_OPC, + CY_CRYPTO_RSRC0_SHIFT, + CY_CRYPTO_RSRC4_SHIFT, + CY_CRYPTO_RSRC8_SHIFT, + CY_CRYPTO_RSRC12_SHIFT); + + /* Wait until the STR instruction is complete */ + while (0uL != _FLD2VAL(CRYPTO_STATUS_STR_BUSY, REG_CRYPTO_STATUS(base))) + { + } } } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_mem_v2.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_mem_v2.c index 487f912de8..708097b973 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_mem_v2.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_mem_v2.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_mem_v2.c -* \version 2.20 +* \version 2.30 * * \brief * This file provides the source code to the API for the PRNG @@ -56,21 +56,24 @@ *******************************************************************************/ void Cy_Crypto_Core_V2_MemCpy(CRYPTO_Type *base, void* dst, void const *src, uint16_t size) { - Cy_Crypto_Core_V2_FFContinue(base, CY_CRYPTO_V2_RB_FF_LOAD0, (const uint8_t*)src, (uint32_t)size); - Cy_Crypto_Core_V2_FFStart (base, CY_CRYPTO_V2_RB_FF_STORE, (const uint8_t*)dst, (uint32_t)size); - - while (size >= CY_CRYPTO_V2_DATA_FIFODEPTH) + if (size != 0U) { - Cy_Crypto_Core_V2_BlockMov(base, CY_CRYPTO_V2_RB_FF_STORE, CY_CRYPTO_V2_RB_FF_LOAD0, CY_CRYPTO_V2_DATA_FIFODEPTH); - size -= CY_CRYPTO_V2_DATA_FIFODEPTH; - } + Cy_Crypto_Core_V2_FFContinue(base, CY_CRYPTO_V2_RB_FF_LOAD0, (const uint8_t*)src, (uint32_t)size); + Cy_Crypto_Core_V2_FFStart (base, CY_CRYPTO_V2_RB_FF_STORE, (const uint8_t*)dst, (uint32_t)size); - if (size != 0u) - { - Cy_Crypto_Core_V2_BlockMov(base, CY_CRYPTO_V2_RB_FF_STORE, CY_CRYPTO_V2_RB_FF_LOAD0, (uint32_t)size); - } + while (size >= CY_CRYPTO_V2_DATA_FIFODEPTH) + { + Cy_Crypto_Core_V2_BlockMov(base, CY_CRYPTO_V2_RB_FF_STORE, CY_CRYPTO_V2_RB_FF_LOAD0, CY_CRYPTO_V2_DATA_FIFODEPTH); + size -= CY_CRYPTO_V2_DATA_FIFODEPTH; + } - Cy_Crypto_Core_V2_Sync(base); + if (size != 0u) + { + Cy_Crypto_Core_V2_BlockMov(base, CY_CRYPTO_V2_RB_FF_STORE, CY_CRYPTO_V2_RB_FF_LOAD0, (uint32_t)size); + } + + Cy_Crypto_Core_V2_Sync(base); + } } /******************************************************************************* @@ -95,20 +98,23 @@ void Cy_Crypto_Core_V2_MemCpy(CRYPTO_Type *base, void* dst, void const *src, uin *******************************************************************************/ void Cy_Crypto_Core_V2_MemSet(CRYPTO_Type *base, void* dst, uint8_t data, uint16_t size) { - Cy_Crypto_Core_V2_FFStart(base, CY_CRYPTO_V2_RB_FF_STORE, dst, (uint32_t)size); - - while (size >= CY_CRYPTO_V2_DATA_FIFODEPTH) + if (size != 0U) { - Cy_Crypto_Core_V2_BlockSet(base, CY_CRYPTO_V2_RB_FF_STORE, data, CY_CRYPTO_V2_DATA_FIFODEPTH); - size -= CY_CRYPTO_V2_DATA_FIFODEPTH; - } + Cy_Crypto_Core_V2_FFStart(base, CY_CRYPTO_V2_RB_FF_STORE, dst, (uint32_t)size); - if (size != 0u) - { - Cy_Crypto_Core_V2_BlockSet(base, CY_CRYPTO_V2_RB_FF_STORE, data, (uint32_t)size); - } + while (size >= CY_CRYPTO_V2_DATA_FIFODEPTH) + { + Cy_Crypto_Core_V2_BlockSet(base, CY_CRYPTO_V2_RB_FF_STORE, data, CY_CRYPTO_V2_DATA_FIFODEPTH); + size -= CY_CRYPTO_V2_DATA_FIFODEPTH; + } - Cy_Crypto_Core_V2_Sync(base); + if (size != 0u) + { + Cy_Crypto_Core_V2_BlockSet(base, CY_CRYPTO_V2_RB_FF_STORE, data, (uint32_t)size); + } + + Cy_Crypto_Core_V2_Sync(base); + } } /******************************************************************************* @@ -136,25 +142,32 @@ void Cy_Crypto_Core_V2_MemSet(CRYPTO_Type *base, void* dst, uint8_t data, uint16 *******************************************************************************/ uint32_t Cy_Crypto_Core_V2_MemCmp(CRYPTO_Type *base, void const *src0, void const *src1, uint16_t size) { - REG_CRYPTO_RESULT(base) = 0ul; + uint32_t memResult = 1U; - Cy_Crypto_Core_V2_FFContinue(base, CY_CRYPTO_V2_RB_FF_LOAD0, (const uint8_t*)src0, (uint32_t)size); - Cy_Crypto_Core_V2_FFContinue(base, CY_CRYPTO_V2_RB_FF_LOAD1, (const uint8_t*)src1, (uint32_t)size); - - while (size >= CY_CRYPTO_V2_DATA_FIFODEPTH) + if (size != 0U) { - Cy_Crypto_Core_V2_BlockCmp(base, CY_CRYPTO_V2_RB_FF_LOAD0, CY_CRYPTO_V2_RB_FF_LOAD1, CY_CRYPTO_V2_DATA_FIFODEPTH); - size -= CY_CRYPTO_V2_DATA_FIFODEPTH; + REG_CRYPTO_RESULT(base) = 0ul; + + Cy_Crypto_Core_V2_FFContinue(base, CY_CRYPTO_V2_RB_FF_LOAD0, (const uint8_t*)src0, (uint32_t)size); + Cy_Crypto_Core_V2_FFContinue(base, CY_CRYPTO_V2_RB_FF_LOAD1, (const uint8_t*)src1, (uint32_t)size); + + while (size >= CY_CRYPTO_V2_DATA_FIFODEPTH) + { + Cy_Crypto_Core_V2_BlockCmp(base, CY_CRYPTO_V2_RB_FF_LOAD0, CY_CRYPTO_V2_RB_FF_LOAD1, CY_CRYPTO_V2_DATA_FIFODEPTH); + size -= CY_CRYPTO_V2_DATA_FIFODEPTH; + } + + if (size != 0u) + { + Cy_Crypto_Core_V2_BlockCmp(base, CY_CRYPTO_V2_RB_FF_LOAD0, CY_CRYPTO_V2_RB_FF_LOAD1, (uint32_t)size); + } + + Cy_Crypto_Core_V2_Sync(base); + + memResult = (uint32_t)(REG_CRYPTO_RESULT(base)); } - if (size != 0u) - { - Cy_Crypto_Core_V2_BlockCmp(base, CY_CRYPTO_V2_RB_FF_LOAD0, CY_CRYPTO_V2_RB_FF_LOAD1, (uint32_t)size); - } - - Cy_Crypto_Core_V2_Sync(base); - - return((uint32_t)(REG_CRYPTO_RESULT(base))); + return memResult; } /******************************************************************************* @@ -184,25 +197,28 @@ uint32_t Cy_Crypto_Core_V2_MemCmp(CRYPTO_Type *base, void const *src0, void cons void Cy_Crypto_Core_V2_MemXor(CRYPTO_Type *base, void* dst, void const *src0, void const *src1, uint16_t size) { - Cy_Crypto_Core_V2_FFContinue(base, CY_CRYPTO_V2_RB_FF_LOAD0, (const uint8_t*)src0, (uint32_t)size); - Cy_Crypto_Core_V2_FFContinue(base, CY_CRYPTO_V2_RB_FF_LOAD1, (const uint8_t*)src1, (uint32_t)size); - Cy_Crypto_Core_V2_FFStart (base, CY_CRYPTO_V2_RB_FF_STORE, dst, (uint32_t)size); - - while (size >= CY_CRYPTO_V2_DATA_FIFODEPTH) + if (size != 0U) { - Cy_Crypto_Core_V2_BlockXor(base, CY_CRYPTO_V2_RB_FF_STORE, CY_CRYPTO_V2_RB_FF_LOAD0, - CY_CRYPTO_V2_RB_FF_LOAD1, CY_CRYPTO_V2_DATA_FIFODEPTH); + Cy_Crypto_Core_V2_FFContinue(base, CY_CRYPTO_V2_RB_FF_LOAD0, (const uint8_t*)src0, (uint32_t)size); + Cy_Crypto_Core_V2_FFContinue(base, CY_CRYPTO_V2_RB_FF_LOAD1, (const uint8_t*)src1, (uint32_t)size); + Cy_Crypto_Core_V2_FFStart (base, CY_CRYPTO_V2_RB_FF_STORE, dst, (uint32_t)size); - size -= CY_CRYPTO_V2_DATA_FIFODEPTH; + while (size >= CY_CRYPTO_V2_DATA_FIFODEPTH) + { + Cy_Crypto_Core_V2_BlockXor(base, CY_CRYPTO_V2_RB_FF_STORE, CY_CRYPTO_V2_RB_FF_LOAD0, + CY_CRYPTO_V2_RB_FF_LOAD1, CY_CRYPTO_V2_DATA_FIFODEPTH); + + size -= CY_CRYPTO_V2_DATA_FIFODEPTH; + } + + if (size != 0u) + { + Cy_Crypto_Core_V2_BlockXor(base, CY_CRYPTO_V2_RB_FF_STORE, CY_CRYPTO_V2_RB_FF_LOAD0, + CY_CRYPTO_V2_RB_FF_LOAD1, (uint32_t)size); + } + + Cy_Crypto_Core_V2_Sync(base); } - - if (size != 0u) - { - Cy_Crypto_Core_V2_BlockXor(base, CY_CRYPTO_V2_RB_FF_STORE, CY_CRYPTO_V2_RB_FF_LOAD0, - CY_CRYPTO_V2_RB_FF_LOAD1, (uint32_t)size); - } - - Cy_Crypto_Core_V2_Sync(base); } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_prng_v1.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_prng_v1.c index 53a1a90ea1..8085b29aa4 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_prng_v1.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_prng_v1.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_prng_v1.c -* \version 2.20 +* \version 2.30 * * \brief * This file provides the source code to the API for the PRNG diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_prng_v2.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_prng_v2.c index 867fcb0f46..ddc4d40607 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_prng_v2.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_prng_v2.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_prng_v2.c -* \version 2.20 +* \version 2.30 * * \brief * This file provides the source code to the API for the PRNG diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_rsa.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_rsa.c index 73578a6e85..fc73580f6d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_rsa.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_rsa.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_rsa.c -* \version 2.20 +* \version 2.30 * * \brief * This file provides the source code to the API to calculate @@ -348,7 +348,7 @@ static void Cy_Crypto_Core_Rsa_MontCoeff(CRYPTO_Type *base, uint32_t modDerReg, while (1) { - Cy_Crypto_Core_WaitForReady(base); + Cy_Crypto_Core_Vu_WaitForComplete(base); CY_CRYPTO_VU_TST(base, ra); @@ -589,7 +589,7 @@ static void Cy_Crypto_Core_Rsa_MontMul(CRYPTO_Type *base, CY_CRYPTO_VU_LSL (base, t, t, sh); CY_CRYPTO_VU_MOV_REG_TO_STATUS (base, status); - Cy_Crypto_Core_WaitForReady(base); + Cy_Crypto_Core_Vu_WaitForComplete(base); CY_CRYPTO_VU_XOR (base, tDouble, uDouble, t); CY_CRYPTO_VU_COND_SWAP_REG (base, CY_CRYPTO_VU_COND_CS, uDouble, tDouble); @@ -681,7 +681,6 @@ static void Cy_Crypto_Core_Rsa_expModByMont(CRYPTO_Type *base, CY_CRYPTO_VU_ALLOC_MEM(base, temp, size); Cy_Crypto_Core_Rsa_MontTransform(base, xBar, myX, barrett, myN, size); - Cy_Crypto_Core_WaitForReady(base); CY_CRYPTO_VU_MOV(base, temp, myE); CY_CRYPTO_VU_SET_TO_ZERO(base, myReg0); @@ -689,7 +688,7 @@ static void Cy_Crypto_Core_Rsa_expModByMont(CRYPTO_Type *base, CY_CRYPTO_VU_CLSAME(base, REG, temp, myReg0); /* This is needed, otherwise clsame is wrong */ - Cy_Crypto_Core_WaitForReady(base); + Cy_Crypto_Core_Vu_WaitForComplete(base); clsame = Cy_Crypto_Core_Vu_RegDataPtrRead(base, REG); @@ -709,21 +708,21 @@ static void Cy_Crypto_Core_Rsa_expModByMont(CRYPTO_Type *base, { /* myY = myY * xBar */ Cy_Crypto_Core_Rsa_MontMul(base, myY, myY, xBar, nPrime, myN, size); - Cy_Crypto_Core_WaitForReady(base); + Cy_Crypto_Core_Vu_WaitForComplete(base); /* xBar = xBar ^ 2 */ Cy_Crypto_Core_Rsa_MontMul(base, xBar, xBar, xBar, nPrime, myN, size); - Cy_Crypto_Core_WaitForReady(base); + Cy_Crypto_Core_Vu_WaitForComplete(base); } else { /* xBar = myY * xBar */ Cy_Crypto_Core_Rsa_MontMul(base, xBar, myY, xBar, nPrime, myN, size); - Cy_Crypto_Core_WaitForReady(base); + Cy_Crypto_Core_Vu_WaitForComplete(base); /* myY = myY ^ 2 */ Cy_Crypto_Core_Rsa_MontMul(base, myY, myY, myY, nPrime, myN, size); - Cy_Crypto_Core_WaitForReady(base); + Cy_Crypto_Core_Vu_WaitForComplete(base); } } @@ -733,6 +732,8 @@ static void Cy_Crypto_Core_Rsa_expModByMont(CRYPTO_Type *base, CY_CRYPTO_VU_FREE_MEM(base, CY_CRYPTO_VU_REG_BIT(myReg0) | CY_CRYPTO_VU_REG_BIT(xBar) | CY_CRYPTO_VU_REG_BIT(temp)); CY_CRYPTO_VU_POP_REG(base); + + Cy_Crypto_Core_Vu_WaitForComplete(base); } /** @@ -794,8 +795,8 @@ cy_en_crypto_status_t Cy_Crypto_Core_Rsa_Proc(CRYPTO_Type *base, uint32_t rBarReg = 11u; - /* Clear all Crypto SRAM before operations */ - Cy_Crypto_Core_MemSet(base, (void*)REG_CRYPTO_MEM_BUFF(base), 0x00u, (uint16_t)(cy_device->cryptoMemSize * 4u)); + /* Clear all Crypto Buffer before operations */ + Cy_Crypto_Core_MemSet(base, (void*)Cy_Crypto_Core_GetVuMemoryAddress(base), 0x00u, (uint16_t)Cy_Crypto_Core_GetVuMemorySize(base)); CY_CRYPTO_VU_ALLOC_MEM(base, yReg, nBitLength); CY_CRYPTO_VU_ALLOC_MEM(base, xReg, nBitLength); @@ -813,7 +814,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_Rsa_Proc(CRYPTO_Type *base, if (barretCoef == NULL) { Cy_Crypto_Core_Rsa_BarrettGetU(base, barrettReg, modReg, nBitLength); - Cy_Crypto_Core_WaitForReady(base); + Cy_Crypto_Core_Vu_WaitForComplete(base); } else { @@ -825,7 +826,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_Rsa_Proc(CRYPTO_Type *base, /* inverseModuloReg used here as temp variable */ CY_CRYPTO_VU_SET_TO_ONE(base, inverseModuloReg); Cy_Crypto_Core_Rsa_MontTransform(base, rBarReg, inverseModuloReg, barrettReg, modReg, nBitLength); - Cy_Crypto_Core_WaitForReady(base); + Cy_Crypto_Core_Vu_WaitForComplete(base); } else { @@ -835,7 +836,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_Rsa_Proc(CRYPTO_Type *base, if (inverseModulo == NULL) { Cy_Crypto_Core_Rsa_MontCoeff(base, inverseModuloReg, modReg, nBitLength); - Cy_Crypto_Core_WaitForReady(base); + Cy_Crypto_Core_Vu_WaitForComplete(base); } else { @@ -862,6 +863,8 @@ cy_en_crypto_status_t Cy_Crypto_Core_Rsa_Proc(CRYPTO_Type *base, CY_CRYPTO_VU_REG_BIT(inverseModuloReg) | CY_CRYPTO_VU_REG_BIT(barrettReg) | CY_CRYPTO_VU_REG_BIT(rBarReg)); + Cy_Crypto_Core_Vu_WaitForComplete(base); + return (tmpResult); } @@ -903,8 +906,8 @@ cy_en_crypto_status_t Cy_Crypto_Core_Rsa_Coef(CRYPTO_Type *base, uint32_t rBarReg = 14u; - /* Clear all Crypto SRAM before operations */ - Cy_Crypto_Core_MemSet(base, (void*)REG_CRYPTO_MEM_BUFF(base), 0x00u, (uint16_t)(cy_device->cryptoMemSize * 4u)); + /* Clear all Crypto Buffer before operations */ + Cy_Crypto_Core_MemSet(base, (void*)Cy_Crypto_Core_GetVuMemoryAddress(base), 0x00u, (uint16_t)Cy_Crypto_Core_GetVuMemorySize(base)); CY_CRYPTO_VU_ALLOC_MEM(base, modReg, nBitLength); CY_CRYPTO_VU_ALLOC_MEM(base, barrettReg, nBitLength + 1u); @@ -915,7 +918,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_Rsa_Coef(CRYPTO_Type *base, Cy_Crypto_Core_Vu_SetMemValue(base, modReg, nPtr, nBitLength); Cy_Crypto_Core_Rsa_BarrettGetU(base, barrettReg, modReg, nBitLength); - Cy_Crypto_Core_WaitForReady(base); + Cy_Crypto_Core_Vu_WaitForComplete(base); /* Copy calculated Barrett coefficient */ Cy_Crypto_Core_Vu_GetMemValue(base, barretCoef, barrettReg, nBitLength + 1u); @@ -923,19 +926,20 @@ cy_en_crypto_status_t Cy_Crypto_Core_Rsa_Coef(CRYPTO_Type *base, /* inverseModuloReg used here as temp variable */ CY_CRYPTO_VU_SET_TO_ONE(base, inverseModuloReg); Cy_Crypto_Core_Rsa_MontTransform(base, rBarReg, inverseModuloReg, barrettReg, modReg, nBitLength); - Cy_Crypto_Core_WaitForReady(base); + Cy_Crypto_Core_Vu_WaitForComplete(base); /* Copy calculated r-bar = (1 << size) mod modulo */ Cy_Crypto_Core_Vu_GetMemValue(base, rBar, rBarReg, nBitLength); Cy_Crypto_Core_Rsa_MontCoeff(base, inverseModuloReg, modReg, nBitLength); - Cy_Crypto_Core_WaitForReady(base); /* Copy calculated inverse modulo */ Cy_Crypto_Core_Vu_GetMemValue(base, inverseModulo, inverseModuloReg, nBitLength); CY_CRYPTO_VU_FREE_MEM(base, CY_CRYPTO_VU_REG_BIT(modReg) | CY_CRYPTO_VU_REG_BIT(inverseModuloReg) | CY_CRYPTO_VU_REG_BIT(barrettReg) | CY_CRYPTO_VU_REG_BIT(rBarReg)); + Cy_Crypto_Core_Vu_WaitForComplete(base); + return (tmpResult); } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_sha_v1.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_sha_v1.c index 6a185c0785..7c187f49a9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_sha_v1.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_sha_v1.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_sha_v1.c -* \version 2.20 +* \version 2.30 * * \brief * This file provides the source code to the API for the SHA method @@ -72,6 +72,9 @@ typedef enum void Cy_Crypto_Core_V1_Sha_ProcessBlock(CRYPTO_Type *base, cy_stc_crypto_sha_state_t *hashState, uint8_t const *block) { + /* Set the SHA mode */ + REG_CRYPTO_SHA_CTL(base) = (uint32_t)(_VAL2FLD(CRYPTO_SHA_CTL_MODE, (uint32_t)hashState->modeHw)); + Cy_Crypto_SetReg4Instr(base, (uint32_t)block, (uint32_t)hashState->hash, /* Initial hash */ @@ -181,24 +184,17 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Sha_Init(CRYPTO_Type *base, CY_ASSERT_L1((shaBuffers != NULL) && (hashState != NULL)); - cy_en_crypto_v1_sha_hw_mode_t shaHwMode; - - #if (CPUSS_CRYPTO_SHA512 == 1) - shaHwMode = CY_CRYPTO_V1_SHA_CTL_MODE_SHA512; - #endif /* #if (CPUSS_CRYPTO_SHA512 == 1) */ - switch (mode) { #if (CPUSS_CRYPTO_SHA1 == 1) case CY_CRYPTO_MODE_SHA1: - Cy_Crypto_Core_V1_MemSet(base, shaBuffers, 0x00U, sizeof(cy_stc_crypto_v1_sha1_buffers_t)); + hashState->block = (uint8_t*)((cy_stc_crypto_v1_sha1_buffers_t*)shaBuffers)->block; + hashState->hash = (uint8_t*)((cy_stc_crypto_v1_sha1_buffers_t*)shaBuffers)->hash; + hashState->roundMem = (uint8_t*)((cy_stc_crypto_v1_sha1_buffers_t*)shaBuffers)->roundMem; - hashState->block = (uint8_t*)((cy_stc_crypto_v1_sha1_buffers_t*)shaBuffers)->block; - hashState->hash = (uint8_t*)((cy_stc_crypto_v1_sha1_buffers_t*)shaBuffers)->hash; - hashState->roundMem = (uint8_t*)((cy_stc_crypto_v1_sha1_buffers_t*)shaBuffers)->roundMem; - - shaHwMode = CY_CRYPTO_V1_SHA_CTL_MODE_SHA1; + hashState->mode = (uint32_t)mode; + hashState->modeHw = (uint32_t)CY_CRYPTO_V1_SHA_CTL_MODE_SHA1; hashState->initialHash = (const uint8_t*)sha1InitHash; hashState->blockSize = CY_CRYPTO_SHA1_BLOCK_SIZE; hashState->hashSize = CY_CRYPTO_SHA1_HASH_SIZE; @@ -210,13 +206,12 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Sha_Init(CRYPTO_Type *base, #if (CPUSS_CRYPTO_SHA256 == 1) case CY_CRYPTO_MODE_SHA224: - Cy_Crypto_Core_V1_MemSet(base, shaBuffers, 0x00U, sizeof(cy_stc_crypto_v1_sha256_buffers_t)); + hashState->block = (uint8_t*)((cy_stc_crypto_v1_sha256_buffers_t*)shaBuffers)->block; + hashState->hash = (uint8_t*)((cy_stc_crypto_v1_sha256_buffers_t*)shaBuffers)->hash; + hashState->roundMem = (uint8_t*)((cy_stc_crypto_v1_sha256_buffers_t*)shaBuffers)->roundMem; - hashState->block = (uint8_t*)((cy_stc_crypto_v1_sha256_buffers_t*)shaBuffers)->block; - hashState->hash = (uint8_t*)((cy_stc_crypto_v1_sha256_buffers_t*)shaBuffers)->hash; - hashState->roundMem = (uint8_t*)((cy_stc_crypto_v1_sha256_buffers_t*)shaBuffers)->roundMem; - - shaHwMode = CY_CRYPTO_V1_SHA_CTL_MODE_SHA256; + hashState->mode = (uint32_t)mode; + hashState->modeHw = (uint32_t)CY_CRYPTO_V1_SHA_CTL_MODE_SHA256; hashState->initialHash = (const uint8_t*)sha224InitHash; hashState->blockSize = CY_CRYPTO_SHA256_BLOCK_SIZE; hashState->hashSize = CY_CRYPTO_SHA256_HASH_SIZE; @@ -225,13 +220,12 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Sha_Init(CRYPTO_Type *base, break; case CY_CRYPTO_MODE_SHA256: - Cy_Crypto_Core_V1_MemSet(base, shaBuffers, 0x00U, sizeof(cy_stc_crypto_v1_sha256_buffers_t)); + hashState->block = (uint8_t*)((cy_stc_crypto_v1_sha256_buffers_t*)shaBuffers)->block; + hashState->hash = (uint8_t*)((cy_stc_crypto_v1_sha256_buffers_t*)shaBuffers)->hash; + hashState->roundMem = (uint8_t*)((cy_stc_crypto_v1_sha256_buffers_t*)shaBuffers)->roundMem; - hashState->block = (uint8_t*)((cy_stc_crypto_v1_sha256_buffers_t*)shaBuffers)->block; - hashState->hash = (uint8_t*)((cy_stc_crypto_v1_sha256_buffers_t*)shaBuffers)->hash; - hashState->roundMem = (uint8_t*)((cy_stc_crypto_v1_sha256_buffers_t*)shaBuffers)->roundMem; - - shaHwMode = CY_CRYPTO_V1_SHA_CTL_MODE_SHA256; + hashState->mode = (uint32_t)mode; + hashState->modeHw = (uint32_t)CY_CRYPTO_V1_SHA_CTL_MODE_SHA256; hashState->initialHash = (const uint8_t*)sha256InitHash; hashState->blockSize = CY_CRYPTO_SHA256_BLOCK_SIZE; hashState->hashSize = CY_CRYPTO_SHA256_HASH_SIZE; @@ -243,12 +237,12 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Sha_Init(CRYPTO_Type *base, #if (CPUSS_CRYPTO_SHA512 == 1) case CY_CRYPTO_MODE_SHA384: - Cy_Crypto_Core_V1_MemSet(base, shaBuffers, 0x00U, sizeof(cy_stc_crypto_v1_sha512_buffers_t)); - - hashState->block = (uint8_t*)((cy_stc_crypto_v1_sha512_buffers_t*)shaBuffers)->block; - hashState->hash = (uint8_t*)((cy_stc_crypto_v1_sha512_buffers_t*)shaBuffers)->hash; - hashState->roundMem = (uint8_t*)((cy_stc_crypto_v1_sha512_buffers_t*)shaBuffers)->roundMem; + hashState->block = (uint8_t*)((cy_stc_crypto_v1_sha512_buffers_t*)shaBuffers)->block; + hashState->hash = (uint8_t*)((cy_stc_crypto_v1_sha512_buffers_t*)shaBuffers)->hash; + hashState->roundMem = (uint8_t*)((cy_stc_crypto_v1_sha512_buffers_t*)shaBuffers)->roundMem; + hashState->mode = (uint32_t)mode; + hashState->modeHw = (uint32_t)CY_CRYPTO_V1_SHA_CTL_MODE_SHA512; hashState->initialHash = (const uint8_t*)sha384InitHash; hashState->blockSize = CY_CRYPTO_SHA512_BLOCK_SIZE; hashState->hashSize = CY_CRYPTO_SHA512_HASH_SIZE; @@ -257,12 +251,12 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Sha_Init(CRYPTO_Type *base, break; case CY_CRYPTO_MODE_SHA512: - Cy_Crypto_Core_V1_MemSet(base, shaBuffers, 0x00U, sizeof(cy_stc_crypto_v1_sha512_buffers_t)); - - hashState->block = (uint8_t*)((cy_stc_crypto_v1_sha512_buffers_t*)shaBuffers)->block; - hashState->hash = (uint8_t*)((cy_stc_crypto_v1_sha512_buffers_t*)shaBuffers)->hash; - hashState->roundMem = (uint8_t*)((cy_stc_crypto_v1_sha512_buffers_t*)shaBuffers)->roundMem; + hashState->block = (uint8_t*)((cy_stc_crypto_v1_sha512_buffers_t*)shaBuffers)->block; + hashState->hash = (uint8_t*)((cy_stc_crypto_v1_sha512_buffers_t*)shaBuffers)->hash; + hashState->roundMem = (uint8_t*)((cy_stc_crypto_v1_sha512_buffers_t*)shaBuffers)->roundMem; + hashState->mode = (uint32_t)mode; + hashState->modeHw = (uint32_t)CY_CRYPTO_V1_SHA_CTL_MODE_SHA512; hashState->initialHash = (const uint8_t*)sha512InitHash; hashState->blockSize = CY_CRYPTO_SHA512_BLOCK_SIZE; hashState->hashSize = CY_CRYPTO_SHA512_HASH_SIZE; @@ -271,12 +265,12 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Sha_Init(CRYPTO_Type *base, break; case CY_CRYPTO_MODE_SHA512_224: - Cy_Crypto_Core_V1_MemSet(base, shaBuffers, 0x00U, sizeof(cy_stc_crypto_v1_sha512_buffers_t)); - - hashState->block = (uint8_t*)((cy_stc_crypto_v1_sha512_buffers_t*)shaBuffers)->block; - hashState->hash = (uint8_t*)((cy_stc_crypto_v1_sha512_buffers_t*)shaBuffers)->hash; - hashState->roundMem = (uint8_t*)((cy_stc_crypto_v1_sha512_buffers_t*)shaBuffers)->roundMem; + hashState->block = (uint8_t*)((cy_stc_crypto_v1_sha512_buffers_t*)shaBuffers)->block; + hashState->hash = (uint8_t*)((cy_stc_crypto_v1_sha512_buffers_t*)shaBuffers)->hash; + hashState->roundMem = (uint8_t*)((cy_stc_crypto_v1_sha512_buffers_t*)shaBuffers)->roundMem; + hashState->mode = (uint32_t)mode; + hashState->modeHw = (uint32_t)CY_CRYPTO_V1_SHA_CTL_MODE_SHA512; hashState->initialHash = (const uint8_t*)sha512_224InitHash; hashState->blockSize = CY_CRYPTO_SHA512_BLOCK_SIZE; hashState->hashSize = CY_CRYPTO_SHA512_HASH_SIZE; @@ -285,12 +279,12 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Sha_Init(CRYPTO_Type *base, break; case CY_CRYPTO_MODE_SHA512_256: - Cy_Crypto_Core_V1_MemSet(base, shaBuffers, 0x00U, sizeof(cy_stc_crypto_v1_sha512_buffers_t)); - - hashState->block = (uint8_t*)((cy_stc_crypto_v1_sha512_buffers_t*)shaBuffers)->block; - hashState->hash = (uint8_t*)((cy_stc_crypto_v1_sha512_buffers_t*)shaBuffers)->hash; - hashState->roundMem = (uint8_t*)((cy_stc_crypto_v1_sha512_buffers_t*)shaBuffers)->roundMem; + hashState->block = (uint8_t*)((cy_stc_crypto_v1_sha512_buffers_t*)shaBuffers)->block; + hashState->hash = (uint8_t*)((cy_stc_crypto_v1_sha512_buffers_t*)shaBuffers)->hash; + hashState->roundMem = (uint8_t*)((cy_stc_crypto_v1_sha512_buffers_t*)shaBuffers)->roundMem; + hashState->mode = (uint32_t)mode; + hashState->modeHw = (uint32_t)CY_CRYPTO_V1_SHA_CTL_MODE_SHA512; hashState->initialHash = (const uint8_t*)sha512_256InitHash; hashState->blockSize = CY_CRYPTO_SHA512_BLOCK_SIZE; hashState->hashSize = CY_CRYPTO_SHA512_HASH_SIZE; @@ -304,9 +298,6 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Sha_Init(CRYPTO_Type *base, break; } - /* Set the SHA mode */ - REG_CRYPTO_SHA_CTL(base) = (uint32_t)(_VAL2FLD(CRYPTO_SHA_CTL_MODE, (uint32_t)shaHwMode)); - return (tmpResult); } @@ -386,22 +377,34 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Sha_Update(CRYPTO_Type *base, { if (messageSize != 0U) { - uint32_t blockSizeTmp = hashState->blockSize; hashState->messageSize += messageSize; - while (messageSize >= blockSizeTmp) - { - Cy_Crypto_Core_V1_Sha_ProcessBlock(base, hashState, message); + uint32_t hashBlockIdx = hashState->blockIdx; + uint32_t hashBlockSize = hashState->blockSize; - message += blockSizeTmp; - messageSize -= blockSizeTmp; + /* Processing the fully filled blocks with remaining buffer data */ + while ((hashBlockIdx + messageSize) >= hashBlockSize) + { + uint32_t tempBlockSize = hashBlockSize - hashBlockIdx; + + Cy_Crypto_Core_V1_MemCpy(base, (void *)((uint32_t)hashState->block + hashBlockIdx), message, (uint16_t)tempBlockSize); + + Cy_Crypto_Core_V1_Sha_ProcessBlock(base, hashState, hashState->block); + + messageSize -= tempBlockSize; + message += tempBlockSize; + + hashBlockIdx = 0U; } /* The remaining block will be calculated in the Finish function. */ - hashState->blockIdx = messageSize; + hashState->blockIdx = hashBlockIdx + messageSize; /* Copy the end of the message to the block */ - Cy_Crypto_Core_V1_MemCpy(base, hashState->block, message, (uint16_t)(messageSize & (blockSizeTmp - 1u))); + if (messageSize != 0U) + { + Cy_Crypto_Core_V1_MemCpy(base, (void *)((uint32_t)hashState->block + hashBlockIdx), message, (uint16_t)messageSize); + } } tmpResult = CY_CRYPTO_SUCCESS; @@ -438,57 +441,57 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Sha_Finish(CRYPTO_Type *base, if ((hashState != NULL) && (digest != NULL)) { - uint8_t *hashTmp = hashState->hash; - uint8_t *blockTmp = hashState->block; - uint32_t blockSizeTmp = hashState->blockSize; - uint32_t blockIdxTmp = hashState->blockIdx; + uint8_t *hashPtr = hashState->hash; + uint8_t *blockPtr = hashState->block; + uint32_t hashBlockSize = hashState->blockSize; + uint32_t hashBlockIdx = hashState->blockIdx; uint64_t finalMessageSizeInBits = (uint64_t)hashState->messageSize * 8U; - uint32_t size; + uint32_t padSize; - if (CY_CRYPTO_SHA512_BLOCK_SIZE == blockSizeTmp) + if (CY_CRYPTO_SHA512_BLOCK_SIZE == hashBlockSize) { - size = CY_CRYPTO_SHA512_PAD_SIZE; /* Pad size = 112 */ + padSize = CY_CRYPTO_SHA512_PAD_SIZE; /* Pad size = 112 */ } else { - size = CY_CRYPTO_SHA256_PAD_SIZE; /* Pad size = 56 */ + padSize = CY_CRYPTO_SHA256_PAD_SIZE; /* Pad size = 56 */ } /* Append 1 bit to the end of the message */ - blockTmp[blockIdxTmp] = 0x80U; + blockPtr[hashBlockIdx] = 0x80U; /* Clear the rest of the block */ - Cy_Crypto_Core_V1_MemSet(base, (void* )&blockTmp[blockIdxTmp + 1U], 0x00U, (uint16_t)(blockSizeTmp - blockIdxTmp - 1U)); + Cy_Crypto_Core_V1_MemSet(base, (void* )&blockPtr[hashBlockIdx + 1U], 0x00U, (uint16_t)(hashBlockSize - hashBlockIdx - 1U)); - if (blockIdxTmp >= size) + if (hashBlockIdx >= padSize) { /* Here we need one additional last block to calculate SHA, prepare it: */ - Cy_Crypto_Core_V1_Sha_ProcessBlock(base, hashState, (uint8_t*)blockTmp); + Cy_Crypto_Core_V1_Sha_ProcessBlock(base, hashState, (uint8_t*)blockPtr); /* Clear the last block */ - Cy_Crypto_Core_V1_MemSet(base, blockTmp, 0x00u, (uint16_t)blockSizeTmp); + Cy_Crypto_Core_V1_MemSet(base, blockPtr, 0x00u, (uint16_t)hashBlockSize); } - blockTmp[blockSizeTmp - 4U] = (uint8_t)((finalMessageSizeInBits) >> 24U); - blockTmp[blockSizeTmp - 3U] = (uint8_t)((finalMessageSizeInBits) >> 16U); - blockTmp[blockSizeTmp - 2U] = (uint8_t)((finalMessageSizeInBits) >> 8U); - blockTmp[blockSizeTmp - 1U] = (uint8_t)(finalMessageSizeInBits); + blockPtr[hashBlockSize - 4U] = (uint8_t)((finalMessageSizeInBits) >> 24U); + blockPtr[hashBlockSize - 3U] = (uint8_t)((finalMessageSizeInBits) >> 16U); + blockPtr[hashBlockSize - 2U] = (uint8_t)((finalMessageSizeInBits) >> 8U); + blockPtr[hashBlockSize - 1U] = (uint8_t)(finalMessageSizeInBits); /* Process the last block */ - Cy_Crypto_Core_V1_Sha_ProcessBlock(base, hashState, (uint8_t*)blockTmp); + Cy_Crypto_Core_V1_Sha_ProcessBlock(base, hashState, (uint8_t*)blockPtr); - /* Invert endians of the hash and copy it to digest, re-use the size variable */ - size = (uint32_t)(hashState->digestSize / 4U); + /* Invert endians of the hash and copy it to digest, re-use the padSize variable */ + padSize = (uint32_t)(hashState->digestSize / 4U); - for(; size != 0U; size--) + for(; padSize != 0U; padSize--) { - *(digest) = *(hashTmp+3); - *(digest+1) = *(hashTmp+2); - *(digest+2) = *(hashTmp+1); - *(digest+3) = *(hashTmp); + *(digest) = *(hashPtr+3); + *(digest+1) = *(hashPtr+2); + *(digest+2) = *(hashPtr+1); + *(digest+3) = *(hashPtr); digest += 4U; - hashTmp += 4U; + hashPtr += 4U; } tmpResult = CY_CRYPTO_SUCCESS; @@ -564,7 +567,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Sha(CRYPTO_Type *base, { cy_en_crypto_status_t tmpResult = CY_CRYPTO_BAD_PARAMS; - void *shaBuffers = (void *)REG_CRYPTO_MEM_BUFF(base); + void *shaBuffers = (void *)Cy_Crypto_Core_GetVuMemoryAddress(base); cy_stc_crypto_sha_state_t myHashState = { 0 }; tmpResult = Cy_Crypto_Core_V1_Sha_Init (base, &myHashState, mode, shaBuffers); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_sha_v2.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_sha_v2.c index aced0299ef..a2a57f5fb9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_sha_v2.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_sha_v2.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_sha_v2.c -* \version 2.20 +* \version 2.30 * * \brief * This file provides the source code to the API for the SHA method @@ -149,16 +149,18 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Sha_Init(CRYPTO_Type *base, }; #endif /* #if (CPUSS_CRYPTO_SHA512 == 1) */ - CY_ASSERT_L1(hashState != NULL); - - Cy_Crypto_Core_V2_MemSet(base, hashState, 0x00U, sizeof(cy_stc_crypto_sha_state_t)); + CY_ASSERT_L1((shaBuffers != NULL) && (hashState != NULL)); switch (mode) { #if (CPUSS_CRYPTO_SHA1 == 1) case CY_CRYPTO_MODE_SHA1: - hashState->mode = CY_CRYPTO_V2_SHA1_OPC; - hashState->initialHash = sha1InitHash; + hashState->block = (uint8_t*)((cy_stc_crypto_v2_sha1_buffers_t*)shaBuffers)->block; + hashState->hash = (uint8_t*)((cy_stc_crypto_v2_sha1_buffers_t*)shaBuffers)->hash; + + hashState->mode = (uint32_t)mode; + hashState->modeHw = (uint32_t)CY_CRYPTO_V2_SHA1_OPC; + hashState->initialHash = (const uint8_t*)sha1InitHash; hashState->blockSize = CY_CRYPTO_SHA1_BLOCK_SIZE; hashState->hashSize = CY_CRYPTO_SHA1_HASH_SIZE; hashState->digestSize = CY_CRYPTO_SHA1_DIGEST_SIZE; @@ -166,15 +168,23 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Sha_Init(CRYPTO_Type *base, #endif /* #if (CPUSS_CRYPTO_SHA1 == 1) */ #if (CPUSS_CRYPTO_SHA256 == 1) case CY_CRYPTO_MODE_SHA256: - hashState->mode = CY_CRYPTO_V2_SHA2_256_OPC; - hashState->initialHash = sha256InitHash; + hashState->block = (uint8_t*)((cy_stc_crypto_v2_sha256_buffers_t*)shaBuffers)->block; + hashState->hash = (uint8_t*)((cy_stc_crypto_v2_sha256_buffers_t*)shaBuffers)->hash; + + hashState->mode = (uint32_t)mode; + hashState->modeHw = (uint32_t)CY_CRYPTO_V2_SHA2_256_OPC; + hashState->initialHash = (const uint8_t*)sha256InitHash; hashState->blockSize = CY_CRYPTO_SHA256_BLOCK_SIZE; hashState->hashSize = CY_CRYPTO_SHA256_HASH_SIZE; hashState->digestSize = CY_CRYPTO_SHA256_DIGEST_SIZE; break; case CY_CRYPTO_MODE_SHA224: - hashState->mode = CY_CRYPTO_V2_SHA2_256_OPC; - hashState->initialHash = sha224InitHash; + hashState->block = (uint8_t*)((cy_stc_crypto_v2_sha256_buffers_t*)shaBuffers)->block; + hashState->hash = (uint8_t*)((cy_stc_crypto_v2_sha256_buffers_t*)shaBuffers)->hash; + + hashState->mode = (uint32_t)mode; + hashState->modeHw = (uint32_t)CY_CRYPTO_V2_SHA2_256_OPC; + hashState->initialHash = (const uint8_t*)sha224InitHash; hashState->blockSize = CY_CRYPTO_SHA256_BLOCK_SIZE; hashState->hashSize = CY_CRYPTO_SHA256_HASH_SIZE; hashState->digestSize = CY_CRYPTO_SHA224_DIGEST_SIZE; @@ -182,29 +192,45 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Sha_Init(CRYPTO_Type *base, #endif /* #if (CPUSS_CRYPTO_SHA256 == 1) */ #if (CPUSS_CRYPTO_SHA512 == 1) case CY_CRYPTO_MODE_SHA512: - hashState->mode = CY_CRYPTO_V2_SHA2_512_OPC; - hashState->initialHash = sha512InitHash; + hashState->block = (uint8_t*)((cy_stc_crypto_v2_sha512_buffers_t*)shaBuffers)->block; + hashState->hash = (uint8_t*)((cy_stc_crypto_v2_sha512_buffers_t*)shaBuffers)->hash; + + hashState->mode = (uint32_t)mode; + hashState->modeHw = (uint32_t)CY_CRYPTO_V2_SHA2_512_OPC; + hashState->initialHash = (const uint8_t*)sha512InitHash; hashState->blockSize = CY_CRYPTO_SHA512_BLOCK_SIZE; hashState->hashSize = CY_CRYPTO_SHA512_HASH_SIZE; hashState->digestSize = CY_CRYPTO_SHA512_DIGEST_SIZE; break; case CY_CRYPTO_MODE_SHA384: - hashState->mode = CY_CRYPTO_V2_SHA2_512_OPC; - hashState->initialHash = sha384InitHash; + hashState->block = (uint8_t*)((cy_stc_crypto_v2_sha512_buffers_t*)shaBuffers)->block; + hashState->hash = (uint8_t*)((cy_stc_crypto_v2_sha512_buffers_t*)shaBuffers)->hash; + + hashState->mode = (uint32_t)mode; + hashState->modeHw = (uint32_t)CY_CRYPTO_V2_SHA2_512_OPC; + hashState->initialHash = (const uint8_t*)sha384InitHash; hashState->blockSize = CY_CRYPTO_SHA512_BLOCK_SIZE; hashState->hashSize = CY_CRYPTO_SHA512_HASH_SIZE; hashState->digestSize = CY_CRYPTO_SHA384_DIGEST_SIZE; break; case CY_CRYPTO_MODE_SHA512_256: - hashState->mode = CY_CRYPTO_V2_SHA2_512_OPC; - hashState->initialHash = sha512_256InitHash; + hashState->block = (uint8_t*)((cy_stc_crypto_v2_sha512_buffers_t*)shaBuffers)->block; + hashState->hash = (uint8_t*)((cy_stc_crypto_v2_sha512_buffers_t*)shaBuffers)->hash; + + hashState->mode = (uint32_t)mode; + hashState->modeHw = (uint32_t)CY_CRYPTO_V2_SHA2_512_OPC; + hashState->initialHash = (const uint8_t*)sha512_256InitHash; hashState->blockSize = CY_CRYPTO_SHA512_BLOCK_SIZE; hashState->hashSize = CY_CRYPTO_SHA512_HASH_SIZE; hashState->digestSize = CY_CRYPTO_SHA512_256_DIGEST_SIZE; break; case CY_CRYPTO_MODE_SHA512_224: - hashState->mode = CY_CRYPTO_V2_SHA2_512_OPC; - hashState->initialHash = sha512_224InitHash; + hashState->block = (uint8_t*)((cy_stc_crypto_v2_sha512_buffers_t*)shaBuffers)->block; + hashState->hash = (uint8_t*)((cy_stc_crypto_v2_sha512_buffers_t*)shaBuffers)->hash; + + hashState->mode = (uint32_t)mode; + hashState->modeHw = (uint32_t)CY_CRYPTO_V2_SHA2_512_OPC; + hashState->initialHash = (const uint8_t*)sha512_224InitHash; hashState->blockSize = CY_CRYPTO_SHA512_BLOCK_SIZE; hashState->hashSize = CY_CRYPTO_SHA512_HASH_SIZE; hashState->digestSize = CY_CRYPTO_SHA512_224_DIGEST_SIZE; @@ -245,13 +271,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Sha_Start(CRYPTO_Type *base, cy_stc_cryp if (hashState->hashSize != 0U) { - Cy_Crypto_Core_V2_RBClear(base); - Cy_Crypto_Core_V2_Sync(base); - - Cy_Crypto_Core_V2_FFStart(base, CY_CRYPTO_V2_RB_FF_LOAD0, hashState->initialHash, hashState->hashSize); - Cy_Crypto_Core_V2_RBXor(base, 0U, hashState->hashSize); - Cy_Crypto_Core_V2_Sync(base); - Cy_Crypto_Core_V2_RBSwap(base); + Cy_Crypto_Core_V2_MemCpy(base, hashState->hash, hashState->initialHash, (uint16_t)hashState->hashSize); tmpResult = CY_CRYPTO_SUCCESS; } @@ -302,19 +322,67 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Sha_Update(CRYPTO_Type *base, { hashState->messageSize += messageSize; - Cy_Crypto_Core_V2_FFContinue(base, CY_CRYPTO_V2_RB_FF_LOAD0, message, messageSize); + uint32_t hashBlockIdx = hashState->blockIdx; + uint32_t hashBlockSize = hashState->blockSize; - while (messageSize >= hashState->blockSize) + /* Load the calculated hash from the context buffer */ + Cy_Crypto_Core_V2_RBClear(base); + Cy_Crypto_Core_V2_Sync(base); + + Cy_Crypto_Core_V2_FFStart(base, CY_CRYPTO_V2_RB_FF_LOAD0, hashState->hash, hashState->hashSize); + Cy_Crypto_Core_V2_RBXor(base, 0U, hashState->hashSize); + Cy_Crypto_Core_V2_Sync(base); + Cy_Crypto_Core_V2_RBSwap(base); + + /* Load the remaining block from the context buffer */ + if (hashBlockIdx != 0U) { - Cy_Crypto_Core_V2_RBXor(base, 0U, hashState->blockSize); - - messageSize -= hashState->blockSize; - - Cy_Crypto_Core_V2_Run(base, hashState->mode); + Cy_Crypto_Core_V2_FFStart(base, CY_CRYPTO_V2_RB_FF_LOAD0, hashState->block, hashBlockIdx); + Cy_Crypto_Core_V2_RBXor(base, 0U, hashBlockIdx); + Cy_Crypto_Core_V2_Sync(base); } - /* Remaining block will be calculated Finish function */ - hashState->blockIdx = messageSize; + /* Start the hash calculating */ + Cy_Crypto_Core_V2_FFContinue(base, CY_CRYPTO_V2_RB_FF_LOAD0, message, messageSize); + + /* Processing the fully filled blocks with remaining buffer data */ + while ((hashBlockIdx + messageSize) >= hashBlockSize) + { + uint32_t tempBlockSize = hashBlockSize - hashBlockIdx; + + Cy_Crypto_Core_V2_RBXor(base, hashBlockIdx, tempBlockSize); + + Cy_Crypto_Core_V2_Run(base, hashState->modeHw); + + messageSize -= tempBlockSize; + + hashBlockIdx = 0U; + } + + /* The remaining block will be calculated in the Finish function */ + hashState->blockIdx = hashBlockIdx + messageSize; + + /* Load the end of the message (tail that less then block size) to the register buffer */ + if (messageSize != 0U) + { + Cy_Crypto_Core_V2_RBXor(base, hashBlockIdx, messageSize); + Cy_Crypto_Core_V2_Sync(base); + } + + /* Save the remaining data to the context buffer */ + if (hashState->blockIdx != 0U) + { + Cy_Crypto_Core_V2_FFStart(base, CY_CRYPTO_V2_RB_FF_STORE, hashState->block, hashState->blockIdx); + Cy_Crypto_Core_V2_RBStore(base, 0U, hashState->blockIdx); + Cy_Crypto_Core_V2_Sync(base); + } + + /* Store the calculated hash to the context buffer */ + Cy_Crypto_Core_V2_FFStart(base, CY_CRYPTO_V2_RB_FF_STORE, hashState->hash, hashState->hashSize); + Cy_Crypto_Core_V2_RBSwap(base); + Cy_Crypto_Core_V2_RBStore(base, 0U, hashState->hashSize); + Cy_Crypto_Core_V2_Sync(base); + Cy_Crypto_Core_V2_RBSwap(base); } tmpResult = CY_CRYPTO_SUCCESS; @@ -351,47 +419,57 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Sha_Finish(CRYPTO_Type *base, if ((hashState != NULL) && (digest != NULL)) { - uint32_t myBlockSize = hashState->blockSize; - uint32_t myBlockIdx = hashState->blockIdx; + uint32_t hashBlockSize = hashState->blockSize; + uint32_t hashBlockIdx = hashState->blockIdx; uint64_t finalMessageSizeInBits = (uint64_t)hashState->messageSize * 8U; - uint32_t size; + uint32_t padSize; - if (CY_CRYPTO_SHA512_BLOCK_SIZE == myBlockSize) + if (CY_CRYPTO_SHA512_BLOCK_SIZE == hashBlockSize) { - size = CY_CRYPTO_SHA512_PAD_SIZE; /* Pad size = 112 */ + padSize = CY_CRYPTO_SHA512_PAD_SIZE; /* Pad size = 112 */ } else { - size = CY_CRYPTO_SHA256_PAD_SIZE; /* Pad size = 56 */ + padSize = CY_CRYPTO_SHA256_PAD_SIZE; /* Pad size = 56 */ } + /* Load the calculated hash from the context buffer */ + Cy_Crypto_Core_V2_RBClear(base); + Cy_Crypto_Core_V2_Sync(base); + + Cy_Crypto_Core_V2_FFStart(base, CY_CRYPTO_V2_RB_FF_LOAD0, hashState->hash, hashState->hashSize); + Cy_Crypto_Core_V2_RBXor(base, 0U, hashState->hashSize); + Cy_Crypto_Core_V2_Sync(base); + Cy_Crypto_Core_V2_RBSwap(base); + /* Load the end of the message (tail that less then block size) to the register buffer */ - Cy_Crypto_Core_V2_RBXor(base, 0U, myBlockIdx); + Cy_Crypto_Core_V2_FFStart(base, CY_CRYPTO_V2_RB_FF_LOAD0, hashState->block, hashBlockIdx); + Cy_Crypto_Core_V2_RBXor(base, 0U, hashBlockIdx); /* Sync until XOR operation is completed */ Cy_Crypto_Core_V2_Sync(base); /* Append 1 bit to the end of the message */ - Cy_Crypto_Core_V2_RBSetByte(base, myBlockIdx, 0x80U); + Cy_Crypto_Core_V2_RBSetByte(base, hashBlockIdx, 0x80U); - if (myBlockIdx >= size) + if (hashBlockIdx >= padSize) { - Cy_Crypto_Core_V2_Run(base, hashState->mode); + Cy_Crypto_Core_V2_Run(base, hashState->modeHw); Cy_Crypto_Core_V2_Sync(base); } /* Append message size into last of the block */ /* In case of u32SizeInByte * 8 > u32Max */ - Cy_Crypto_Core_V2_RBSetByte(base, myBlockSize - 5U, (uint8_t)(finalMessageSizeInBits >> 32U)); + Cy_Crypto_Core_V2_RBSetByte(base, hashBlockSize - 5U, (uint8_t)(finalMessageSizeInBits >> 32U)); - Cy_Crypto_Core_V2_RBSetByte(base, myBlockSize - 4U, (uint8_t)(finalMessageSizeInBits >> 24U)); - Cy_Crypto_Core_V2_RBSetByte(base, myBlockSize - 3U, (uint8_t)(finalMessageSizeInBits >> 16U)); - Cy_Crypto_Core_V2_RBSetByte(base, myBlockSize - 2U, (uint8_t)(finalMessageSizeInBits >> 8U)); - Cy_Crypto_Core_V2_RBSetByte(base, myBlockSize - 1U, (uint8_t)(finalMessageSizeInBits)); + Cy_Crypto_Core_V2_RBSetByte(base, hashBlockSize - 4U, (uint8_t)(finalMessageSizeInBits >> 24U)); + Cy_Crypto_Core_V2_RBSetByte(base, hashBlockSize - 3U, (uint8_t)(finalMessageSizeInBits >> 16U)); + Cy_Crypto_Core_V2_RBSetByte(base, hashBlockSize - 2U, (uint8_t)(finalMessageSizeInBits >> 8U)); + Cy_Crypto_Core_V2_RBSetByte(base, hashBlockSize - 1U, (uint8_t)(finalMessageSizeInBits)); - Cy_Crypto_Core_V2_Run(base, hashState->mode); + Cy_Crypto_Core_V2_Run(base, hashState->modeHw); Cy_Crypto_Core_V2_Sync(base); /* Write digest. */ @@ -429,7 +507,12 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Sha_Free(CRYPTO_Type *base, cy_stc_crypt if (hashState != NULL) { - Cy_Crypto_Core_V2_MemSet(base, hashState, 0x00U, sizeof(cy_stc_crypto_sha_state_t)); + /* Clears the context buffers */ + Cy_Crypto_Core_V2_MemSet(base, hashState->block, 0x00U, (uint16_t)hashState->blockSize); + Cy_Crypto_Core_V2_MemSet(base, hashState->hash, 0x00U, (uint16_t)hashState->hashSize); + + /* Clears the hash state */ + Cy_Crypto_Core_V2_MemSet(base, hashState, 0x00U, (uint16_t)sizeof(cy_stc_crypto_sha_state_t)); /* Clears the memory buffer. */ Cy_Crypto_Core_V2_RBClear(base); @@ -474,11 +557,14 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Sha(CRYPTO_Type *base, { cy_en_crypto_status_t tmpResult = CY_CRYPTO_BAD_PARAMS; + /* Allocate maximal space for the structure which stores the SHA buffers */ + cy_stc_crypto_v2_sha512_buffers_t shaBuffers = {{ 0 }}; + /* Allocate space for the structure which stores the SHA context */ - cy_stc_crypto_sha_state_t hashState = { 0 }; + cy_stc_crypto_sha_state_t hashState = { 0 }; /* No buffers are needed for the Crypto_ver2 IP block. */ - tmpResult = Cy_Crypto_Core_V2_Sha_Init (base, &hashState, mode, NULL); + tmpResult = Cy_Crypto_Core_V2_Sha_Init (base, &hashState, mode, &shaBuffers); if (CY_CRYPTO_SUCCESS == tmpResult) { diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_trng_v1.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_trng_v1.c index 5275864895..bb4876adb0 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_trng_v1.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_trng_v1.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_trng_v1.c -* \version 2.20 +* \version 2.30 * * \brief * This file provides the source code to the API for the TRNG diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_trng_v2.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_trng_v2.c index 3c83ff2fae..0879044fd1 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_trng_v2.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_trng_v2.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_trng_v2.c -* \version 2.20 +* \version 2.30 * * \brief * This file provides the source code to the API for the TRNG diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_vu.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_vu.c index f1750927c1..a9d252cae5 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_vu.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_vu.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_vu.c -* \version 2.20 +* \version 2.30 * * \brief * This file provides the source code to the API for the Vector Unit helpers @@ -46,25 +46,23 @@ void Cy_Crypto_Core_Vu_SetMemValue(CRYPTO_Type *base, uint32_t dstReg, uint8_t c Cy_Crypto_Core_Vu_WaitForComplete(base); - if (CY_CRYPTO_HW_V1) + if (CY_CRYPTO_V1) { CY_CRYPTO_VU_SAVE_REG(base, CY_CRYPTO_VU_HW_REG0, ®0_data); CY_CRYPTO_VU_SAVE_REG(base, CY_CRYPTO_VU_HW_REG1, ®1_data); } /* Copy value to Crypto SRAM */ - uint16_t byteSize = (uint16_t)((size / 8u) & 0xFFFFu); - if ((size % 8u) != 0u) - { - ++byteSize; - } + uint16_t byteSize = (uint16_t)CY_CRYPTO_BYTE_SIZE_OF_BITS(size); + uint32_t destAddr = (uint32_t)Cy_Crypto_Core_Vu_RegMemPointer(base, dstReg); CY_ASSERT_L1(size <= Cy_Crypto_Core_Vu_RegBitSizeRead(base, dstReg)); + CY_ASSERT_L1( ((destAddr + byteSize) - 1u) < ((uint32_t)Cy_Crypto_Core_GetVuMemoryAddress(base) + Cy_Crypto_Core_GetVuMemorySize(base))); - CY_ASSERT_L1( (((uint32_t)Cy_Crypto_Core_Vu_RegMemPointer(base, dstReg) + byteSize) - 1u) < ((uint32_t)REG_CRYPTO_MEM_BUFF(base) + CY_CRYPTO_MEM_BUFF_SIZE)); - Cy_Crypto_Core_MemCpy(base, (void*)Cy_Crypto_Core_Vu_RegMemPointer(base, dstReg), (const void*)src, byteSize); + Cy_Crypto_Core_MemSet(base, (void*)destAddr, 0u, (uint16_t)CY_CRYPTO_WORD_SIZE_OF_BITS(size) * 4u); + Cy_Crypto_Core_MemCpy(base, (void*)destAddr, (const void*)src, byteSize); - if (CY_CRYPTO_HW_V1) + if (CY_CRYPTO_V1) { CY_CRYPTO_VU_RESTORE_REG(base, CY_CRYPTO_VU_HW_REG0, reg0_data); CY_CRYPTO_VU_RESTORE_REG(base, CY_CRYPTO_VU_HW_REG1, reg1_data); @@ -78,25 +76,22 @@ void Cy_Crypto_Core_Vu_GetMemValue(CRYPTO_Type *base, uint8_t *dst, uint32_t src Cy_Crypto_Core_Vu_WaitForComplete(base); - if (CY_CRYPTO_HW_V1) + if (CY_CRYPTO_V1) { CY_CRYPTO_VU_SAVE_REG(base, CY_CRYPTO_VU_HW_REG0, ®0_data); CY_CRYPTO_VU_SAVE_REG(base, CY_CRYPTO_VU_HW_REG1, ®1_data); } /* Copy value from Crypto SRAM */ - uint16_t byteSize = (uint16_t)((size / 8u) & 0xFFFFu); - if ((size % 8u) != 0u) - { - ++byteSize; - } + uint16_t byteSize = (uint16_t)CY_CRYPTO_BYTE_SIZE_OF_BITS(size); + uint32_t dataAddr = (uint32_t)Cy_Crypto_Core_Vu_RegMemPointer(base, srcReg); CY_ASSERT_L1(size <= Cy_Crypto_Core_Vu_RegBitSizeRead(base, srcReg)); - CY_ASSERT_L1((((uint32_t)Cy_Crypto_Core_Vu_RegMemPointer(base, srcReg) + byteSize) - 1u) < ((uint32_t)REG_CRYPTO_MEM_BUFF(base) + CY_CRYPTO_MEM_BUFF_SIZE) ); + CY_ASSERT_L1( ((dataAddr + byteSize) - 1u) < ((uint32_t)Cy_Crypto_Core_GetVuMemoryAddress(base) + Cy_Crypto_Core_GetVuMemorySize(base))); - Cy_Crypto_Core_MemCpy(base, (void*)dst, (void*)Cy_Crypto_Core_Vu_RegMemPointer(base, srcReg), byteSize); + Cy_Crypto_Core_MemCpy(base, (void*)dst, (void*)dataAddr, byteSize); - if (CY_CRYPTO_HW_V1) + if (CY_CRYPTO_V1) { CY_CRYPTO_VU_RESTORE_REG(base, CY_CRYPTO_VU_HW_REG0, reg0_data); CY_CRYPTO_VU_RESTORE_REG(base, CY_CRYPTO_VU_HW_REG1, reg1_data); @@ -105,9 +100,6 @@ void Cy_Crypto_Core_Vu_GetMemValue(CRYPTO_Type *base, uint8_t *dst, uint32_t src cy_en_crypto_status_t Cy_Crypto_Core_Cleanup(CRYPTO_Type *base) { - /* Set the stack pointer to the Crypto buff size, in words */ - CY_CRYPTO_VU_SET_REG(base, CY_CRYPTO_VU_HW_REG15, CY_CRYPTO_MEM_BUFF_SIZE_U32, 1u); - /* Clear whole register file */ Cy_Crypto_Core_ClearVuRegisters(base); @@ -129,7 +121,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_Cleanup(CRYPTO_Type *base) /* AES */ REG_CRYPTO_AES_CTL(base) = 0u; - if (CY_CRYPTO_HW_V1) + if (CY_CRYPTO_V1) { REG_CRYPTO_CRC_LFSR_CTL(base) = 0u; REG_CRYPTO_SHA_CTL(base) = 0u; @@ -145,7 +137,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_Cleanup(CRYPTO_Type *base) Cy_Crypto_Core_V2_RBClear(base); } - Cy_Crypto_Core_MemSet(base, (void *)REG_CRYPTO_MEM_BUFF(base), 0u, (uint16_t)CY_CRYPTO_MEM_BUFF_SIZE); + Cy_Crypto_Core_MemSet(base, (void *)Cy_Crypto_Core_GetVuMemoryAddress(base), 0u, (uint16_t)Cy_Crypto_Core_GetVuMemorySize(base)); return (CY_CRYPTO_SUCCESS); } @@ -210,6 +202,13 @@ bool Cy_Crypto_Core_Vu_IsRegLess(CRYPTO_Type *base, uint32_t srcReg0, uint32_t s return tmpResult; } +void Cy_Crypto_Core_VU_RegInvertEndianness(CRYPTO_Type *base, uint32_t srcReg) +{ + uint32_t byteSize = CY_CRYPTO_BYTE_SIZE_OF_BITS(Cy_Crypto_Core_Vu_RegBitSizeRead(base, srcReg)); + uint32_t *dataAddr = Cy_Crypto_Core_Vu_RegMemPointer(base, srcReg); + Cy_Crypto_Core_InvertEndianness(dataAddr, byteSize); +} + #endif /* #if (CPUSS_CRYPTO_VU == 1) */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_server.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_server.c index fda6402e14..35627b4219 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_server.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_server.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_server.c -* \version 2.20 +* \version 2.30 * * \brief * This file provides the source code to the API for Crypto Server @@ -41,6 +41,7 @@ #include "cy_crypto_core_crc.h" #include "cy_crypto_core_des.h" #include "cy_crypto_core_hw.h" +#include "cy_crypto_core_ecc.h" #include #include @@ -145,7 +146,7 @@ cy_en_crypto_status_t Cy_Crypto_Server_Start_Base(cy_stc_crypto_config_t const * NULL, /* Cy_Crypto_Core_RsaVerify, */ }; - if (cy_device->cryptoVersion == 1u) + if (CY_CRYPTO_V1) { cy_CryptoFunctionTable = &cryptoV1BaseFuncs; } @@ -211,7 +212,7 @@ cy_en_crypto_status_t Cy_Crypto_Server_Start_Extra(cy_stc_crypto_config_t const NULL, /* Cy_Crypto_Core_RsaVerify, */ }; - if (cy_device->cryptoVersion == 1u) + if (CY_CRYPTO_V1) { cy_CryptoFunctionTable = &cryptoV1ExtraFuncs; } @@ -277,7 +278,7 @@ cy_en_crypto_status_t Cy_Crypto_Server_Start_Full(cy_stc_crypto_config_t const * &Cy_Crypto_Core_Rsa_Verify, }; - if (cy_device->cryptoVersion == 1u) + if (CY_CRYPTO_V1) { cy_CryptoFunctionTable = &cryptoV1FullFuncs; } @@ -435,6 +436,30 @@ void Cy_Crypto_Server_Process(void) myData->resp = Cy_Crypto_Core_GetLibInfo((cy_en_crypto_lib_info_t*)myData->xdata); break; + /* MEM_BUFF memory management */ + case CY_CRYPTO_INSTR_MEMBUF_SET: + { + cy_stc_crypto_context_str_t *cfContext = myData->xdata; + myData->resp = Cy_Crypto_Core_SetVuMemoryAddress(CY_CRYPTO_BASE, cfContext->src0, cfContext->dataSize); + } + break; + + case CY_CRYPTO_INSTR_MEMBUF_ADDR: + { + cy_stc_crypto_context_str_t *cfContext = myData->xdata; + *(uint32_t *)(cfContext->dst) = (uint32_t)Cy_Crypto_Core_GetVuMemoryAddress(CY_CRYPTO_BASE); + myData->resp = CY_CRYPTO_SUCCESS; + } + break; + + case CY_CRYPTO_INSTR_MEMBUF_SIZE: + { + cy_stc_crypto_context_str_t *cfContext = myData->xdata; + *(uint32_t *)(cfContext->dst) = Cy_Crypto_Core_GetVuMemorySize(CY_CRYPTO_BASE); + myData->resp = CY_CRYPTO_SUCCESS; + } + break; + case CY_CRYPTO_INSTR_PRNG_INIT: if (NULL != cy_CryptoFunctionTable->prngInitFunc) { @@ -468,7 +493,7 @@ void Cy_Crypto_Server_Process(void) cy_stc_crypto_context_aes_t *cfContext = (cy_stc_crypto_context_aes_t *)myData->xdata; myData->resp = (cy_CryptoFunctionTable->aesInitFunc)(CY_CRYPTO_BASE, - (uint8_t*)cfContext->key, cfContext->keyLength, &cfContext->aesState); + (uint8_t*)cfContext->key, cfContext->keyLength, &cfContext->aesState, (cy_stc_crypto_aes_buffers_t *)(Cy_Crypto_Core_GetVuMemoryAddress(CY_CRYPTO_BASE))); } break; @@ -585,7 +610,7 @@ void Cy_Crypto_Server_Process(void) if (NULL != cy_CryptoFunctionTable->memCmpFunc) { cy_stc_crypto_context_str_t *cfContext = myData->xdata; - *(uint32_t* )(cfContext->dst) = + *(uint32_t *)(cfContext->dst) = (cy_CryptoFunctionTable->memCmpFunc)(CY_CRYPTO_BASE, cfContext->src0, cfContext->src1, (uint16_t)cfContext->dataSize); myData->resp = CY_CRYPTO_SUCCESS; @@ -665,6 +690,24 @@ void Cy_Crypto_Server_Process(void) } break; + case CY_CRYPTO_INSTR_ECDSA_SIGN: + { + cy_stc_crypto_context_ecc_t *cfContext = myData->xdata; + myData->resp = Cy_Crypto_Core_ECC_SignHash(CY_CRYPTO_BASE, + cfContext->src0, cfContext->datalen, cfContext->dst0, + cfContext->key, cfContext->src1); + } + break; + + case CY_CRYPTO_INSTR_ECDSA_VER: + { + cy_stc_crypto_context_ecc_t *cfContext = myData->xdata; + myData->resp = Cy_Crypto_Core_ECC_VerifyHash(CY_CRYPTO_BASE, + cfContext->src1, cfContext->src0, cfContext->datalen, + cfContext->dst0, cfContext->key); + } + break; + default: myData->resp = CY_CRYPTO_NOT_SUPPORTED; break; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_csd.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_csd.c index e55616830a..c43e41f3af 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_csd.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_csd.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_csd.c -* \version 1.0.1 +* \version 1.10 * * The source file of the CSD driver. * @@ -22,14 +22,13 @@ * limitations under the License. *******************************************************************************/ + #include #include "cy_device_headers.h" #include "cy_syslib.h" #include "cy_csd.h" -#if defined(__cplusplus) -extern "C" { -#endif +#if defined(CY_IP_MXCSDV2) /** @@ -306,5 +305,7 @@ uint32_t Cy_CSD_GetVrefTrim(uint32_t referenceVoltage) } #endif +#endif /* CY_IP_MXCSDV2 */ + /* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_device.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_device.c index adf74186c8..2a3d6e9a0f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_device.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_device.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_device.c -* \version 1.10 +* \version 2.0 * * This file provides the definitions for core and peripheral block HW base * addresses, versions, and parameters. @@ -49,21 +49,19 @@ const cy_stc_device_t cy_deviceIpBlockCfgPSoC6_01 = /* ipcBase */ 0x40230000UL, /* cryptoBase */ 0x40110000UL, - /* IP block versions */ - /* cpussVersion */ 1U, - /* cryptoVersion */ 1U, - /* dwVersion */ 1U, - /* flashcVersion */ 1U, - /* gpioVersion */ 1U, - /* hsiomVersion */ 1U, - /* ipcVersion */ 1U, - /* periVersion */ 1U, - /* protVersion */ 1U, + /* IP block versions [7:4] major, [3:0] minor */ + /* cpussVersion */ 0x10U, + /* cryptoVersion */ 0x10U, + /* dwVersion */ 0x10U, + /* ipcVersion */ 0x10U, + /* periVersion */ 0x10U, + /* srssVersion */ 0x10U, /* Parameters */ /* cpussIpcNr */ 16U, /* cpussIpcIrqNr */ 16U, - /* cpussDwChNr */ 16U, + /* cpussDw0ChNr */ 16U, + /* cpussDw1ChNr */ 16U, /* cpussFlashPaSize */ 128U, /* cpussIpc0Irq */ 25, /* cpussFmIrq */ 85, @@ -93,7 +91,7 @@ const cy_stc_device_t cy_deviceIpBlockCfgPSoC6_01 = /* Peripheral register offsets */ /* DW registers */ - /* dwChOffset */ offsetof(DW_V1_Type, CH_STRUCT), + /* dwChOffset */ (uint16_t)offsetof(DW_V1_Type, CH_STRUCT), /* dwChSize */ sizeof(DW_CH_STRUCT_V1_Type), /* dwChCtlPrioPos */ (uint8_t)DW_CH_STRUCT_CH_CTL_PRIO_Pos, /* dwChCtlPreemptablePos */ (uint8_t)DW_CH_STRUCT_CH_CTL_PREEMPTABLE_Pos, @@ -101,27 +99,27 @@ const cy_stc_device_t cy_deviceIpBlockCfgPSoC6_01 = /* dwStatusChIdxMsk */ DW_STATUS_CH_IDX_Msk, /* PERI registers */ - /* periTrCmdOffset */ offsetof(PERI_V1_Type, TR_CMD), - /* periTrCmdGrSelMsk */ PERI_TR_CMD_GROUP_SEL_Msk, - /* periTrGrOffset */ offsetof(PERI_V1_Type, TR_GR), + /* periTrCmdOffset */ (uint16_t)offsetof(PERI_V1_Type, TR_CMD), + /* periTrCmdGrSelMsk */ (uint16_t)PERI_TR_CMD_GROUP_SEL_Msk, + /* periTrGrOffset */ (uint16_t)offsetof(PERI_V1_Type, TR_GR), /* periTrGrSize */ sizeof(PERI_TR_GR_V1_Type), - /* periDivCmdDivSelMsk */ PERI_DIV_CMD_DIV_SEL_Msk, - /* periDivCmdTypeSelPos */ PERI_DIV_CMD_TYPE_SEL_Pos, - /* periDivCmdPaDivSelPos */ PERI_DIV_CMD_PA_DIV_SEL_Pos, - /* periDivCmdPaTypeSelPos */ PERI_DIV_CMD_PA_TYPE_SEL_Pos, + /* periDivCmdDivSelMsk */ (uint8_t)PERI_DIV_CMD_DIV_SEL_Msk, + /* periDivCmdTypeSelPos */ (uint8_t)PERI_DIV_CMD_TYPE_SEL_Pos, + /* periDivCmdPaDivSelPos */ (uint8_t)PERI_DIV_CMD_PA_DIV_SEL_Pos, + /* periDivCmdPaTypeSelPos */ (uint8_t)PERI_DIV_CMD_PA_TYPE_SEL_Pos, - /* periDiv8CtlOffset */ offsetof(PERI_V1_Type, DIV_8_CTL), - /* periDiv16CtlOffset */ offsetof(PERI_V1_Type, DIV_16_CTL), - /* periDiv16_5CtlOffset */ offsetof(PERI_V1_Type, DIV_16_5_CTL), - /* periDiv24_5CtlOffset */ offsetof(PERI_V1_Type, DIV_24_5_CTL), + /* periDiv8CtlOffset */ (uint16_t)offsetof(PERI_V1_Type, DIV_8_CTL), + /* periDiv16CtlOffset */ (uint16_t)offsetof(PERI_V1_Type, DIV_16_CTL), + /* periDiv16_5CtlOffset */ (uint16_t)offsetof(PERI_V1_Type, DIV_16_5_CTL), + /* periDiv24_5CtlOffset */ (uint16_t)offsetof(PERI_V1_Type, DIV_24_5_CTL), /* GPIO registers */ - /* gpioPrtIntrCfgOffset */ offsetof(GPIO_PRT_V1_Type, INTR_CFG), - /* gpioPrtCfgOffset */ offsetof(GPIO_PRT_V1_Type, CFG), - /* gpioPrtCfgInOffset */ offsetof(GPIO_PRT_V1_Type, CFG_IN), - /* gpioPrtCfgOutOffset */ offsetof(GPIO_PRT_V1_Type, CFG_OUT), - /* gpioPrtCfgSioOffset */ offsetof(GPIO_PRT_V1_Type, CFG_SIO), + /* gpioPrtIntrCfgOffset */ (uint8_t)offsetof(GPIO_PRT_V1_Type, INTR_CFG), + /* gpioPrtCfgOffset */ (uint8_t)offsetof(GPIO_PRT_V1_Type, CFG), + /* gpioPrtCfgInOffset */ (uint8_t)offsetof(GPIO_PRT_V1_Type, CFG_IN), + /* gpioPrtCfgOutOffset */ (uint8_t)offsetof(GPIO_PRT_V1_Type, CFG_OUT), + /* gpioPrtCfgSioOffset */ (uint8_t)offsetof(GPIO_PRT_V1_Type, CFG_SIO), /* CPUSS registers */ /* cpussCm0ClockCtlOffset */ offsetof(CPUSS_V1_Type, CM0_CLOCK_CTL), @@ -159,21 +157,19 @@ const cy_stc_device_t cy_deviceIpBlockCfgPSoC6_02 = /* ipcBase */ 0x40220000UL, /* cryptoBase */ 0x40100000UL, - /* IP block versions */ - /* cpussVersion */ 2U, - /* cryptoVersion */ 2U, - /* dwVersion */ 2U, - /* flashcVersion */ 2U, - /* gpioVersion */ 2U, - /* hsiomVersion */ 2U, - /* ipcVersion */ 2U, - /* periVersion */ 2U, - /* protVersion */ 2U, + /* IP block versions [7:4] major, [3:0] minor */ + /* cpussVersion */ 0x20U, + /* cryptoVersion */ 0x20U, + /* dwVersion */ 0x20U, + /* ipcVersion */ 0x20U, + /* periVersion */ 0x20U, + /* srssVersion */ 0x10U, /* Parameters */ /* cpussIpcNr */ 16U, /* cpussIpcIrqNr */ 16U, - /* cpussDwChNr */ 29U, + /* cpussDw0ChNr */ 29U, + /* cpussDw1ChNr */ 29U, /* cpussFlashPaSize */ 128U, /* cpussIpc0Irq */ 23, /* cpussFmIrq */ 117, @@ -203,7 +199,7 @@ const cy_stc_device_t cy_deviceIpBlockCfgPSoC6_02 = /* Peripheral register offsets */ /* DW registers */ - /* dwChOffset */ offsetof(DW_V2_Type, CH_STRUCT), + /* dwChOffset */ (uint16_t)offsetof(DW_V2_Type, CH_STRUCT), /* dwChSize */ sizeof(DW_CH_STRUCT_V2_Type), /* dwChCtlPrioPos */ (uint8_t)DW_CH_STRUCT_V2_CH_CTL_PRIO_Pos, /* dwChCtlPreemptablePos */ (uint8_t)DW_CH_STRUCT_V2_CH_CTL_PREEMPTABLE_Pos, @@ -211,9 +207,9 @@ const cy_stc_device_t cy_deviceIpBlockCfgPSoC6_02 = /* dwStatusChIdxMsk */ DW_V2_STATUS_CH_IDX_Msk, /* PERI registers */ - /* periTrCmdOffset */ offsetof(PERI_V2_Type, TR_CMD), - /* periTrCmdGrSelMsk */ PERI_V2_TR_CMD_GROUP_SEL_Msk, - /* periTrGrOffset */ offsetof(PERI_V2_Type, TR_GR), + /* periTrCmdOffset */ (uint16_t)offsetof(PERI_V2_Type, TR_CMD), + /* periTrCmdGrSelMsk */ (uint16_t)PERI_V2_TR_CMD_GROUP_SEL_Msk, + /* periTrGrOffset */ (uint16_t)offsetof(PERI_V2_Type, TR_GR), /* periTrGrSize */ sizeof(PERI_TR_GR_V2_Type), /* periDivCmdDivSelMsk */ (uint8_t)PERI_V2_DIV_CMD_DIV_SEL_Msk, @@ -221,17 +217,17 @@ const cy_stc_device_t cy_deviceIpBlockCfgPSoC6_02 = /* periDivCmdPaDivSelPos */ (uint8_t)PERI_V2_DIV_CMD_PA_DIV_SEL_Pos, /* periDivCmdPaTypeSelPos */ (uint8_t)PERI_V2_DIV_CMD_PA_TYPE_SEL_Pos, - /* periDiv8CtlOffset */ offsetof(PERI_V2_Type, DIV_8_CTL), - /* periDiv16CtlOffset */ offsetof(PERI_V2_Type, DIV_16_CTL), - /* periDiv16_5CtlOffset */ offsetof(PERI_V2_Type, DIV_16_5_CTL), - /* periDiv24_5CtlOffset */ offsetof(PERI_V2_Type, DIV_24_5_CTL), + /* periDiv8CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_8_CTL), + /* periDiv16CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_16_CTL), + /* periDiv16_5CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_16_5_CTL), + /* periDiv24_5CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_24_5_CTL), /* GPIO registers */ - /* gpioPrtIntrCfgOffset */ offsetof(GPIO_PRT_V2_Type, INTR_CFG), - /* gpioPrtCfgOffset */ offsetof(GPIO_PRT_V2_Type, CFG), - /* gpioPrtCfgInOffset */ offsetof(GPIO_PRT_V2_Type, CFG_IN), - /* gpioPrtCfgOutOffset */ offsetof(GPIO_PRT_V2_Type, CFG_OUT), - /* gpioPrtCfgSioOffset */ offsetof(GPIO_PRT_V2_Type, CFG_SIO), + /* gpioPrtIntrCfgOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, INTR_CFG), + /* gpioPrtCfgOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG), + /* gpioPrtCfgInOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG_IN), + /* gpioPrtCfgOutOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG_OUT), + /* gpioPrtCfgSioOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG_SIO), /* CPUSS registers */ /* cpussCm0ClockCtlOffset */ offsetof(CPUSS_V2_Type, CM0_CLOCK_CTL), @@ -268,21 +264,19 @@ const cy_stc_device_t cy_deviceIpBlockCfgPSoC6_03 = /* ipcBase */ 0x40220000UL, /* cryptoBase */ 0x40100000UL, - /* IP block versions */ - /* cpussVersion */ 2U, - /* cryptoVersion */ 2U, - /* dwVersion */ 2U, - /* flashcVersion */ 2U, - /* gpioVersion */ 2U, - /* hsiomVersion */ 2U, - /* ipcVersion */ 2U, - /* periVersion */ 2U, - /* protVersion */ 2U, + /* IP block versions [7:4] major, [3:0] minor */ + /* cpussVersion */ 0x20U, + /* cryptoVersion */ 0x20U, + /* dwVersion */ 0x20U, + /* ipcVersion */ 0x20U, + /* periVersion */ 0x20U, + /* srssVersion */ 0x13U, /* Parameters */ /* cpussIpcNr */ 16U, /* cpussIpcIrqNr */ 16U, - /* cpussDwChNr */ 22U, + /* cpussDw0ChNr */ 29U, + /* cpussDw1ChNr */ 32U, /* cpussFlashPaSize */ 128U, /* cpussIpc0Irq */ 23, /* cpussFmIrq */ 117, @@ -312,7 +306,7 @@ const cy_stc_device_t cy_deviceIpBlockCfgPSoC6_03 = /* Peripheral register offsets */ /* DW registers */ - /* dwChOffset */ offsetof(DW_V2_Type, CH_STRUCT), + /* dwChOffset */ (uint16_t)offsetof(DW_V2_Type, CH_STRUCT), /* dwChSize */ sizeof(DW_CH_STRUCT_V2_Type), /* dwChCtlPrioPos */ (uint8_t)DW_CH_STRUCT_V2_CH_CTL_PRIO_Pos, /* dwChCtlPreemptablePos */ (uint8_t)DW_CH_STRUCT_V2_CH_CTL_PREEMPTABLE_Pos, @@ -320,9 +314,9 @@ const cy_stc_device_t cy_deviceIpBlockCfgPSoC6_03 = /* dwStatusChIdxMsk */ DW_V2_STATUS_CH_IDX_Msk, /* PERI registers */ - /* periTrCmdOffset */ offsetof(PERI_V2_Type, TR_CMD), - /* periTrCmdGrSelMsk */ PERI_V2_TR_CMD_GROUP_SEL_Msk, - /* periTrGrOffset */ offsetof(PERI_V2_Type, TR_GR), + /* periTrCmdOffset */ (uint16_t)offsetof(PERI_V2_Type, TR_CMD), + /* periTrCmdGrSelMsk */ (uint16_t)PERI_V2_TR_CMD_GROUP_SEL_Msk, + /* periTrGrOffset */ (uint16_t)offsetof(PERI_V2_Type, TR_GR), /* periTrGrSize */ sizeof(PERI_TR_GR_V2_Type), /* periDivCmdDivSelMsk */ (uint8_t)PERI_V2_DIV_CMD_DIV_SEL_Msk, @@ -330,17 +324,17 @@ const cy_stc_device_t cy_deviceIpBlockCfgPSoC6_03 = /* periDivCmdPaDivSelPos */ (uint8_t)PERI_V2_DIV_CMD_PA_DIV_SEL_Pos, /* periDivCmdPaTypeSelPos */ (uint8_t)PERI_V2_DIV_CMD_PA_TYPE_SEL_Pos, - /* periDiv8CtlOffset */ offsetof(PERI_V2_Type, DIV_8_CTL), - /* periDiv16CtlOffset */ offsetof(PERI_V2_Type, DIV_16_CTL), - /* periDiv16_5CtlOffset */ offsetof(PERI_V2_Type, DIV_16_5_CTL), - /* periDiv24_5CtlOffset */ offsetof(PERI_V2_Type, DIV_24_5_CTL), + /* periDiv8CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_8_CTL), + /* periDiv16CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_16_CTL), + /* periDiv16_5CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_16_5_CTL), + /* periDiv24_5CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_24_5_CTL), /* GPIO registers */ - /* gpioPrtIntrCfgOffset */ offsetof(GPIO_PRT_V2_Type, INTR_CFG), - /* gpioPrtCfgOffset */ offsetof(GPIO_PRT_V2_Type, CFG), - /* gpioPrtCfgInOffset */ offsetof(GPIO_PRT_V2_Type, CFG_IN), - /* gpioPrtCfgOutOffset */ offsetof(GPIO_PRT_V2_Type, CFG_OUT), - /* gpioPrtCfgSioOffset */ offsetof(GPIO_PRT_V2_Type, CFG_SIO), + /* gpioPrtIntrCfgOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, INTR_CFG), + /* gpioPrtCfgOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG), + /* gpioPrtCfgInOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG_IN), + /* gpioPrtCfgOutOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG_OUT), + /* gpioPrtCfgSioOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG_SIO), /* CPUSS registers */ /* cpussCm0ClockCtlOffset */ offsetof(CPUSS_V2_Type, CM0_CLOCK_CTL), diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_dma.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_dma.c index cec3fe68e0..cd8ac0c097 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_dma.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_dma.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_dma.c -* \version 2.10 +* \version 2.20 * * \brief * The source code file for the DMA driver. @@ -42,7 +42,7 @@ * \return The status /ref cy_en_dma_status_t. * * \funcusage -* \snippet dma\2.10\snippet\main.c snippet_Cy_DMA_Crc_Init +* \snippet dma/snippet/main.c snippet_Cy_DMA_Crc_Init * *******************************************************************************/ cy_en_dma_status_t Cy_DMA_Crc_Init(DW_Type * base, cy_stc_dma_crc_config_t const * crcConfig) @@ -85,7 +85,7 @@ cy_en_dma_status_t Cy_DMA_Crc_Init(DW_Type * base, cy_stc_dma_crc_config_t const * The status /ref cy_en_dma_status_t. * * \funcusage -* \snippet dma\2.10\snippet\main.c snippet_Cy_DMA_Enable +* \snippet dma/snippet/main.c snippet_Cy_DMA_Enable * *******************************************************************************/ cy_en_dma_status_t Cy_DMA_Descriptor_Init(cy_stc_dma_descriptor_t * descriptor, const cy_stc_dma_descriptor_config_t * config) @@ -200,7 +200,7 @@ cy_en_dma_status_t Cy_DMA_Descriptor_Init(cy_stc_dma_descriptor_t * descriptor, * The descriptor structure instance declared by the user/component. * * \funcusage -* \snippet dma\2.10\snippet\main.c snippet_Cy_DMA_Descriptor_Deinit +* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_Deinit * *******************************************************************************/ void Cy_DMA_Descriptor_DeInit(cy_stc_dma_descriptor_t * descriptor) @@ -234,7 +234,7 @@ void Cy_DMA_Descriptor_DeInit(cy_stc_dma_descriptor_t * descriptor) * The status /ref cy_en_dma_status_t. * * \funcusage -* \snippet dma\2.10\snippet\main.c snippet_Cy_DMA_Enable +* \snippet dma/snippet/main.c snippet_Cy_DMA_Enable * *******************************************************************************/ cy_en_dma_status_t Cy_DMA_Channel_Init(DW_Type * base, uint32_t channel, cy_stc_dma_channel_config_t const * channelConfig) @@ -244,7 +244,7 @@ cy_en_dma_status_t Cy_DMA_Channel_Init(DW_Type * base, uint32_t channel, cy_stc_ if ((NULL != base) && (NULL != channelConfig) && (NULL != channelConfig->descriptor) && - (CY_DMA_IS_CH_NR_VALID(channel))) + (CY_DMA_IS_CH_NR_VALID(base, channel))) { CY_ASSERT_L2(CY_DMA_IS_PRIORITY_VALID(channelConfig->priority)); @@ -277,12 +277,12 @@ cy_en_dma_status_t Cy_DMA_Channel_Init(DW_Type * base, uint32_t channel, cy_stc_ * A channel number. * * \funcusage -* \snippet dma\2.10\snippet\main.c snippet_Cy_DMA_Disable +* \snippet dma/snippet/main.c snippet_Cy_DMA_Disable * *******************************************************************************/ void Cy_DMA_Channel_DeInit(DW_Type * base, uint32_t channel) { - CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(channel)); + CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel)); DW_CH_CTL(base, channel) = 0UL; DW_CH_IDX(base, channel) = 0UL; @@ -309,7 +309,7 @@ void Cy_DMA_Channel_DeInit(DW_Type * base, uint32_t channel) * The pointer to the next descriptor. * * \funcusage -* \snippet dma\2.10\snippet\main.c snippet_Cy_DMA_Descriptor_SetterFunctions +* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions * *******************************************************************************/ void Cy_DMA_Descriptor_SetNextDescriptor(cy_stc_dma_descriptor_t * descriptor, cy_stc_dma_descriptor_t const * nextDescriptor) @@ -354,7 +354,7 @@ void Cy_DMA_Descriptor_SetNextDescriptor(cy_stc_dma_descriptor_t * descriptor, c * The pointer to the next descriptor. * * \funcusage -* \snippet dma\2.10\snippet\main.c snippet_Cy_DMA_Descriptor_GetterFunctions +* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions * *******************************************************************************/ cy_stc_dma_descriptor_t * Cy_DMA_Descriptor_GetNextDescriptor(cy_stc_dma_descriptor_t const * descriptor) @@ -408,7 +408,7 @@ cy_stc_dma_descriptor_t * Cy_DMA_Descriptor_GetNextDescriptor(cy_stc_dma_descrip * The descriptor type \ref cy_en_dma_descriptor_type_t. * * \funcusage -* \snippet dma\2.10\snippet\main.c snippet_Cy_DMA_Descriptor_SetterFunctions +* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions * *******************************************************************************/ void Cy_DMA_Descriptor_SetDescriptorType(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_descriptor_type_t descriptorType) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_dmac.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_dmac.c index ce731127ea..2e2e351262 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_dmac.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_dmac.c @@ -47,7 +47,7 @@ * The status /ref cy_en_dmac_status_t. * * \funcusage -* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_Enable +* \snippet dmac/snippet/main.c snippet_Cy_DMAC_Enable * *******************************************************************************/ cy_en_dmac_status_t Cy_DMAC_Descriptor_Init(cy_stc_dmac_descriptor_t * descriptor, const cy_stc_dmac_descriptor_config_t * config) @@ -130,7 +130,7 @@ cy_en_dmac_status_t Cy_DMAC_Descriptor_Init(cy_stc_dmac_descriptor_t * descripto * The descriptor structure instance. * * \funcusage -* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_Descriptor_Deinit +* \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_Deinit * *******************************************************************************/ void Cy_DMAC_Descriptor_DeInit(cy_stc_dmac_descriptor_t * descriptor) @@ -166,7 +166,7 @@ void Cy_DMAC_Descriptor_DeInit(cy_stc_dmac_descriptor_t * descriptor) * The status /ref cy_en_dmac_status_t. * * \funcusage -* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_Enable +* \snippet dmac/snippet/main.c snippet_Cy_DMAC_Enable * *******************************************************************************/ cy_en_dmac_status_t Cy_DMAC_Channel_Init(DMAC_Type * base, uint32_t channel, cy_stc_dmac_channel_config_t const * config) @@ -204,7 +204,7 @@ cy_en_dmac_status_t Cy_DMAC_Channel_Init(DMAC_Type * base, uint32_t channel, cy_ * A channel number. * * \funcusage -* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_Disable +* \snippet dmac/snippet/main.c snippet_Cy_DMAC_Disable * *******************************************************************************/ void Cy_DMAC_Channel_DeInit(DMAC_Type * base, uint32_t channel) @@ -241,7 +241,7 @@ void Cy_DMAC_Channel_DeInit(DMAC_Type * base, uint32_t channel) * is specified by the data transfer size /ref cy_en_dmac_data_size_t. * * \funcusage -* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_Descriptor_GetterFunctions +* \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_GetterFunctions * *******************************************************************************/ uint32_t Cy_DMAC_Descriptor_GetXloopDataCount(cy_stc_dmac_descriptor_t const * descriptor) @@ -287,7 +287,7 @@ uint32_t Cy_DMAC_Descriptor_GetXloopDataCount(cy_stc_dmac_descriptor_t const * d * For all the rest of the descriptors (except single transfer), the valid range is 1...65536. * * \funcusage -* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_Descriptor_SetterFunctions +* \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_SetterFunctions * *******************************************************************************/ void Cy_DMAC_Descriptor_SetXloopDataCount(cy_stc_dmac_descriptor_t * descriptor, uint32_t xCount) @@ -331,7 +331,7 @@ void Cy_DMAC_Descriptor_SetXloopDataCount(cy_stc_dmac_descriptor_t * descriptor, * The pointer to the next descriptor. * * \funcusage -* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_Descriptor_SetterFunctions +* \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_SetterFunctions * *******************************************************************************/ void Cy_DMAC_Descriptor_SetNextDescriptor(cy_stc_dmac_descriptor_t * descriptor, cy_stc_dmac_descriptor_t const * nextDescriptor) @@ -385,7 +385,7 @@ void Cy_DMAC_Descriptor_SetNextDescriptor(cy_stc_dmac_descriptor_t * descriptor, * The pointer to the next descriptor. * * \funcusage -* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_Descriptor_GetterFunctions +* \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_GetterFunctions * *******************************************************************************/ cy_stc_dmac_descriptor_t * Cy_DMAC_Descriptor_GetNextDescriptor(cy_stc_dmac_descriptor_t const * descriptor) @@ -442,7 +442,7 @@ cy_stc_dmac_descriptor_t * Cy_DMAC_Descriptor_GetNextDescriptor(cy_stc_dmac_desc * The descriptor type \ref cy_en_dmac_descriptor_type_t. * * \funcusage -* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_Descriptor_SetterFunctions +* \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_SetterFunctions * *******************************************************************************/ void Cy_DMAC_Descriptor_SetDescriptorType(cy_stc_dmac_descriptor_t * descriptor, cy_en_dmac_descriptor_type_t descriptorType) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_flash.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_flash.c index 472b6276f0..ddd33d80a2 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_flash.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_flash.c @@ -803,7 +803,7 @@ cy_en_flashdrv_status_t Cy_Flash_EraseSector(uint32_t sectorAddr) * user must clear the flash cache with the Cy_SysLib_ClearFlashCacheAndBuffer() * function. * -* \param rowAddr Address of the flash row number. +* \param sectorAddr Address of the flash row number. * The Read-while-Write violation occurs when the flash read operation is * initiated in the same flash sector where the flash erase operation is * performing. Refer to the device datasheet for the details. @@ -861,7 +861,7 @@ cy_en_flashdrv_status_t Cy_Flash_StartEraseSector(uint32_t sectorAddr) * detect circuits should be configured to generate an interrupt instead of a * reset. Otherwise, portions of flash may undergo unexpected changes. * -* \param rowAddr Address of the flash row number. +* \param subSectorAddr Address of the flash row number. * The Read-while-Write violation occurs when the flash read operation is * initiated in the same flash sector where the flash write operation is * performing. Refer to the device datasheet for the details. @@ -916,7 +916,7 @@ cy_en_flashdrv_status_t Cy_Flash_EraseSubsector(uint32_t subSectorAddr) * user must clear the flash cache with the Cy_SysLib_ClearFlashCacheAndBuffer() * function. * -* \param rowAddr Address of the flash row number. +* \param subSectorAddr Address of the flash row number. * The Read-while-Write violation occurs when the flash read operation is * initiated in the same flash sector where the flash erase operation is * performing. Refer to the device datasheet for the details. @@ -1282,7 +1282,7 @@ cy_en_flashdrv_status_t Cy_Flash_RowChecksum (uint32_t rowAddr, uint32_t* checks { result = CY_FLASH_DRV_SUCCESS; - if (1u == cy_device->ipcVersion) + if (CY_IPC_V1) { *checksumPtr = flashContext.opcode & CY_FLASH_RESULT_MASK; } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_i2s.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_i2s.c index 4b7acb46de..f89905ba8f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_i2s.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_i2s.c @@ -43,7 +43,7 @@ * \return error / status code. See \ref cy_en_i2s_status_t. * * \funcusage -* \snippet i2s\2.10\snippet\main.c snippet_Cy_I2S_Init +* \snippet i2s/snippet/main.c snippet_Cy_I2S_Init * *******************************************************************************/ cy_en_i2s_status_t Cy_I2S_Init(I2S_Type * base, cy_stc_i2s_config_t const * config) @@ -193,7 +193,7 @@ cy_en_i2s_status_t Cy_I2S_Init(I2S_Type * base, cy_stc_i2s_config_t const * conf * \param base The pointer to the I2S instance address. * * \funcusage -* \snippet i2s\2.10\snippet\main.c snippet_Cy_I2S_DeInit +* \snippet i2s/snippet/main.c snippet_Cy_I2S_DeInit * *******************************************************************************/ void Cy_I2S_DeInit(I2S_Type * base) @@ -235,7 +235,7 @@ void Cy_I2S_DeInit(I2S_Type * base) * *context element of the \ref cy_stc_syspm_callback_params_t structure. * * \funcusage -* \snippet i2s\2.10\snippet\main.c snippet_Cy_I2S_DeepSleepCallback +* \snippet i2s/snippet/main.c snippet_Cy_I2S_DeepSleepCallback * *******************************************************************************/ cy_en_syspm_status_t Cy_I2S_DeepSleepCallback (cy_stc_syspm_callback_params_t *callbackParams, cy_en_syspm_callback_mode_t mode) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_ipc_drv.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_ipc_drv.c index 4c10701b78..c70eed7b77 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_ipc_drv.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_ipc_drv.c @@ -50,7 +50,7 @@ * function call. * * \funcusage -* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_ReadMsgPtr +* \snippet ipc/snippet/main.c snippet_Cy_IPC_Drv_ReadMsgPtr * *******************************************************************************/ cy_en_ipcdrv_status_t Cy_IPC_Drv_LockRelease (IPC_STRUCT_Type* base, uint32_t releaseEventIntr) @@ -101,7 +101,7 @@ cy_en_ipcdrv_status_t Cy_IPC_Drv_LockRelease (IPC_STRUCT_Type* base, uint32_t re * \retval CY_IPC_DRV_ERROR: The IPC channel is unavailable because it is already locked. * * \funcusage -* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_SendMsgWord +* \snippet ipc/snippet/main.c snippet_Cy_IPC_Drv_SendMsgWord * *******************************************************************************/ cy_en_ipcdrv_status_t Cy_IPC_Drv_SendMsgWord (IPC_STRUCT_Type* base, uint32_t notifyEventIntr, uint32_t message) @@ -153,7 +153,7 @@ cy_en_ipcdrv_status_t Cy_IPC_Drv_SendMsgWord (IPC_STRUCT_Type* base, uint32_t n * may be invalid. * * \funcusage -* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_ReadMsgWord +* \snippet ipc/snippet/main.c snippet_Cy_IPC_Drv_ReadMsgWord * *******************************************************************************/ cy_en_ipcdrv_status_t Cy_IPC_Drv_ReadMsgWord (IPC_STRUCT_Type const * base, uint32_t * message) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_ipc_pipe.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_ipc_pipe.c index 62047f5b96..5800baa614 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_ipc_pipe.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_ipc_pipe.c @@ -45,8 +45,8 @@ static cy_stc_ipc_pipe_ep_t * cy_ipc_pipe_epArray = NULL; * created and will be used to reference all endpoints. * * \funcusage -* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_myIpcPipeEpArray -* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Pipe_Config +* \snippet ipc/snippet/main.c snippet_myIpcPipeEpArray +* \snippet ipc/snippet/main.c snippet_Cy_IPC_Pipe_Config * *******************************************************************************/ void Cy_IPC_Pipe_Config(cy_stc_ipc_pipe_ep_t * theEpArray) @@ -74,9 +74,9 @@ void Cy_IPC_Pipe_Config(cy_stc_ipc_pipe_ep_t * theEpArray) * This is the pointer to the pipe configuration structure * * \funcusage -* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_myIpcPipeCbArray -* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_myIpcPipeEpConfig -* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Pipe_Init +* \snippet ipc/snippet/main.c snippet_myIpcPipeCbArray +* \snippet ipc/snippet/main.c snippet_myIpcPipeEpConfig +* \snippet ipc/snippet/main.c snippet_Cy_IPC_Pipe_Init * *******************************************************************************/ void Cy_IPC_Pipe_Init(cy_stc_ipc_pipe_config_t const *config) @@ -178,9 +178,9 @@ void Cy_IPC_Pipe_Init(cy_stc_ipc_pipe_config_t const *config) * This is a pointer to the endpoint interrupt description structure. * * \funcusage -* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_myIpcPipeCbArray -* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_myIpcPipeEpConfig -* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Pipe_EndpointInit +* \snippet ipc/snippet/main.c snippet_myIpcPipeCbArray +* \snippet ipc/snippet/main.c snippet_myIpcPipeEpConfig +* \snippet ipc/snippet/main.c snippet_Cy_IPC_Pipe_EndpointInit * *******************************************************************************/ void Cy_IPC_Pipe_EndpointInit(uint32_t epAddr, cy_ipc_pipe_callback_array_ptr_t cbArray, @@ -246,8 +246,8 @@ void Cy_IPC_Pipe_EndpointInit(uint32_t epAddr, cy_ipc_pipe_callback_array_ptr_t * CY_IPC_PIPE_ERROR_SEND_BUSY: The pipe is already busy sending a message * * \funcusage -* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_myReleaseCallback -* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Pipe_SendMessage +* \snippet ipc/snippet/main.c snippet_myReleaseCallback +* \snippet ipc/snippet/main.c snippet_Cy_IPC_Pipe_SendMessage * *******************************************************************************/ cy_en_ipc_pipe_status_t Cy_IPC_Pipe_SendMessage(uint32_t toAddr, uint32_t fromAddr, @@ -348,8 +348,8 @@ cy_en_ipc_pipe_status_t Cy_IPC_Pipe_SendMessage(uint32_t toAddr, uint32_t fromAd * CY_IPC_PIPE_ERROR_BAD_CLIENT: Client ID out of range, callback not registered. * * \funcusage -* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_myAcquireCallback -* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Pipe_RegisterCallback +* \snippet ipc/snippet/main.c snippet_myAcquireCallback +* \snippet ipc/snippet/main.c snippet_Cy_IPC_Pipe_RegisterCallback * *******************************************************************************/ cy_en_ipc_pipe_status_t Cy_IPC_Pipe_RegisterCallback(uint32_t epAddr, cy_ipc_pipe_callback_ptr_t callBackPtr, uint32_t clientId) @@ -399,8 +399,8 @@ cy_en_ipc_pipe_status_t Cy_IPC_Pipe_RegisterCallback(uint32_t epAddr, cy_ipc_pip * None * * \funcusage -* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_myDefaultReleaseCallback -* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Pipe_RegisterCallbackRel +* \snippet ipc/snippet/main.c snippet_myDefaultReleaseCallback +* \snippet ipc/snippet/main.c snippet_Cy_IPC_Pipe_RegisterCallbackRel * *******************************************************************************/ void Cy_IPC_Pipe_RegisterCallbackRel(uint32_t epAddr, cy_ipc_pipe_relcallback_ptr_t callBackPtr) @@ -432,8 +432,8 @@ void Cy_IPC_Pipe_RegisterCallbackRel(uint32_t epAddr, cy_ipc_pipe_relcallback_pt * next releases. * * \funcusage -* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_myIpcPipeEpArray -* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Pipe_ExecuteCallback +* \snippet ipc/snippet/main.c snippet_myIpcPipeEpArray +* \snippet ipc/snippet/main.c snippet_Cy_IPC_Pipe_ExecuteCallback * *******************************************************************************/ void Cy_IPC_Pipe_ExecuteCallback(uint32_t epAddr) @@ -555,7 +555,7 @@ void Cy_IPC_Pipe_ExecCallback(cy_stc_ipc_pipe_ep_t * endpoint) * CY_IPC_PIPE_SUCCESS: Callback registered successfully * * \funcusage -* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Pipe_EndpointPauseResume +* \snippet ipc/snippet/main.c snippet_Cy_IPC_Pipe_EndpointPauseResume * *******************************************************************************/ cy_en_ipc_pipe_status_t Cy_IPC_Pipe_EndpointPause(uint32_t epAddr) @@ -587,7 +587,7 @@ cy_en_ipc_pipe_status_t Cy_IPC_Pipe_EndpointPause(uint32_t epAddr) * CY_IPC_PIPE_SUCCESS: Callback registered successfully * * \funcusage -* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Pipe_EndpointPauseResume +* \snippet ipc/snippet/main.c snippet_Cy_IPC_Pipe_EndpointPauseResume * *******************************************************************************/ cy_en_ipc_pipe_status_t Cy_IPC_Pipe_EndpointResume(uint32_t epAddr) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_ipc_sema.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_ipc_sema.c index 2d4554bddd..b5120d15d6 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_ipc_sema.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_ipc_sema.c @@ -66,7 +66,7 @@ static IPC_STRUCT_Type* cy_semaIpcStruct; * \retval CY_IPC_SEMA_ERROR_LOCKED: Could not acquire semaphores IPC channel * * \funcusage -* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Sema_Init +* \snippet ipc/snippet/main.c snippet_Cy_IPC_Sema_Init * *******************************************************************************/ cy_en_ipcsema_status_t Cy_IPC_Sema_Init(uint32_t ipcChannel, @@ -223,7 +223,7 @@ cy_en_ipcsema_status_t Cy_IPC_Sema_InitExt(uint32_t ipcChannel, cy_stc_ipc_sema_ * \retval CY_IPC_SEMA_OUT_OF_RANGE: The semaphore number is not valid * * \funcusage -* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Sema_Set +* \snippet ipc/snippet/main.c snippet_Cy_IPC_Sema_Set * *******************************************************************************/ cy_en_ipcsema_status_t Cy_IPC_Sema_Set(uint32_t semaNumber, bool preemptable) @@ -311,7 +311,7 @@ cy_en_ipcsema_status_t Cy_IPC_Sema_Set(uint32_t semaNumber, bool preemptable) * \retval CY_IPC_SEMA_OUT_OF_RANGE: The semaphore number is not valid * * \funcusage -* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Sema_Clear +* \snippet ipc/snippet/main.c snippet_Cy_IPC_Sema_Clear * *******************************************************************************/ cy_en_ipcsema_status_t Cy_IPC_Sema_Clear(uint32_t semaNumber, bool preemptable) @@ -382,7 +382,7 @@ cy_en_ipcsema_status_t Cy_IPC_Sema_Clear(uint32_t semaNumber, bool preemptable) * \retval CY_IPC_SEMA_OUT_OF_RANGE: The semaphore number is not valid * * \funcusage -* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Sema_Status +* \snippet ipc/snippet/main.c snippet_Cy_IPC_Sema_Status * *******************************************************************************/ cy_en_ipcsema_status_t Cy_IPC_Sema_Status(uint32_t semaNumber) @@ -428,7 +428,7 @@ cy_en_ipcsema_status_t Cy_IPC_Sema_Status(uint32_t semaNumber) * Returns the semaphores quantity. * * \funcusage -* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Sema_GetMaxSems +* \snippet ipc/snippet/main.c snippet_Cy_IPC_Sema_GetMaxSems * *******************************************************************************/ uint32_t Cy_IPC_Sema_GetMaxSems(void) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_prot.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_prot.c index 92eb118c57..2e4051b790 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_prot.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_prot.c @@ -92,7 +92,7 @@ static cy_en_prot_status_t Prot_ConfigPpuAtt(volatile uint32_t * reg, uint16_t p * CY_PROT_FAILURE | The resource is locked. * * \funcusage -* \snippet prot/1.20/snippet/main.c snippet_Cy_Prot_ConfigBusMaster +* \snippet prot/snippet/main.c snippet_Cy_Prot_ConfigBusMaster * *******************************************************************************/ cy_en_prot_status_t Cy_Prot_ConfigBusMaster(en_prot_master_t busMaster, bool privileged, bool secure, uint32_t pcMask) @@ -158,7 +158,7 @@ cy_en_prot_status_t Cy_Prot_ConfigBusMaster(en_prot_master_t busMaster, bool pri * CY_PROT_FAILURE | The resource is locked. * * \funcusage -* \snippet prot/1.20/snippet/main.c snippet_Cy_Prot_SetActivePC +* \snippet prot/snippet/main.c snippet_Cy_Prot_SetActivePC * *******************************************************************************/ cy_en_prot_status_t Cy_Prot_SetActivePC(en_prot_master_t busMaster, uint32_t pc) @@ -191,7 +191,7 @@ cy_en_prot_status_t Cy_Prot_SetActivePC(en_prot_master_t busMaster, uint32_t pc) * Active protection context of the master \ref cy_en_prot_pc_t. * * \funcusage -* \snippet prot/1.20/snippet/main.c snippet_Cy_Prot_SetActivePC +* \snippet prot/snippet/main.c snippet_Cy_Prot_SetActivePC * *******************************************************************************/ uint32_t Cy_Prot_GetActivePC(en_prot_master_t busMaster) @@ -230,7 +230,7 @@ uint32_t Cy_Prot_GetActivePC(en_prot_master_t busMaster) * CY_PROT_FAILURE | Configuration failed due to a protection violation. * * \funcusage -* \snippet prot/1.20/snippet/main.c snippet_Cy_Prot_ConfigMpuStruct +* \snippet prot/snippet/main.c snippet_Cy_Prot_ConfigMpuStruct * *******************************************************************************/ cy_en_prot_status_t Cy_Prot_ConfigMpuStruct(PROT_MPU_MPU_STRUCT_Type* base, const cy_stc_mpu_cfg_t* config) @@ -279,7 +279,7 @@ cy_en_prot_status_t Cy_Prot_ConfigMpuStruct(PROT_MPU_MPU_STRUCT_Type* base, cons * CY_PROT_FAILURE | The MPU struct is disabled and possibly locked. * * \funcusage -* \snippet prot/1.20/snippet/main.c snippet_Cy_Prot_EnableMpuStruct +* \snippet prot/snippet/main.c snippet_Cy_Prot_EnableMpuStruct * *******************************************************************************/ cy_en_prot_status_t Cy_Prot_EnableMpuStruct(PROT_MPU_MPU_STRUCT_Type* base) @@ -317,7 +317,7 @@ cy_en_prot_status_t Cy_Prot_EnableMpuStruct(PROT_MPU_MPU_STRUCT_Type* base) * CY_PROT_FAILURE | The MPU struct is enabled and possibly locked. * * \funcusage -* \snippet prot/1.20/snippet/main.c snippet_Cy_Prot_DisableMpuStruct +* \snippet prot/snippet/main.c snippet_Cy_Prot_DisableMpuStruct * *******************************************************************************/ cy_en_prot_status_t Cy_Prot_DisableMpuStruct(PROT_MPU_MPU_STRUCT_Type* base) @@ -367,7 +367,7 @@ cy_en_prot_status_t Cy_Prot_DisableMpuStruct(PROT_MPU_MPU_STRUCT_Type* base) * CY_PROT_BAD_PARAM | An incorrect/invalid parameter was passed. * * \funcusage -* \snippet prot/1.20/snippet/main.c snippet_Cy_Prot_ConfigSmpuMasterStruct +* \snippet prot/snippet/main.c snippet_Cy_Prot_ConfigSmpuMasterStruct * *******************************************************************************/ cy_en_prot_status_t Cy_Prot_ConfigSmpuMasterStruct(PROT_SMPU_SMPU_STRUCT_Type* base, const cy_stc_smpu_cfg_t* config) @@ -438,7 +438,7 @@ cy_en_prot_status_t Cy_Prot_ConfigSmpuMasterStruct(PROT_SMPU_SMPU_STRUCT_Type* b * CY_PROT_BAD_PARAM | An incorrect/invalid parameter was passed. * * \funcusage -* \snippet prot/1.20/snippet/main.c snippet_Cy_Prot_ConfigSmpuSlaveStruct +* \snippet prot/snippet/main.c snippet_Cy_Prot_ConfigSmpuSlaveStruct * *******************************************************************************/ cy_en_prot_status_t Cy_Prot_ConfigSmpuSlaveStruct(PROT_SMPU_SMPU_STRUCT_Type* base, const cy_stc_smpu_cfg_t* config) @@ -501,7 +501,7 @@ cy_en_prot_status_t Cy_Prot_ConfigSmpuSlaveStruct(PROT_SMPU_SMPU_STRUCT_Type* ba * CY_PROT_FAILURE | The Master PU struct is disabled and possibly locked. * * \funcusage -* \snippet prot/1.20/snippet/main.c snippet_Cy_Prot_EnableSmpuMasterStruct +* \snippet prot/snippet/main.c snippet_Cy_Prot_EnableSmpuMasterStruct * *******************************************************************************/ cy_en_prot_status_t Cy_Prot_EnableSmpuMasterStruct(PROT_SMPU_SMPU_STRUCT_Type* base) @@ -541,7 +541,7 @@ cy_en_prot_status_t Cy_Prot_EnableSmpuMasterStruct(PROT_SMPU_SMPU_STRUCT_Type* b * CY_PROT_FAILURE | The Master PU struct is enabled and possibly locked. * * \funcusage -* \snippet prot/1.20/snippet/main.c snippet_Cy_Prot_DisableSmpuMasterStruct +* \snippet prot/snippet/main.c snippet_Cy_Prot_DisableSmpuMasterStruct * *******************************************************************************/ cy_en_prot_status_t Cy_Prot_DisableSmpuMasterStruct(PROT_SMPU_SMPU_STRUCT_Type* base) @@ -581,7 +581,7 @@ cy_en_prot_status_t Cy_Prot_DisableSmpuMasterStruct(PROT_SMPU_SMPU_STRUCT_Type* * CY_PROT_FAILURE | The Slave PU struct is disabled and possibly locked. * * \funcusage -* \snippet prot/1.20/snippet/main.c snippet_Cy_Prot_EnableSmpuSlaveStruct +* \snippet prot/snippet/main.c snippet_Cy_Prot_EnableSmpuSlaveStruct * *******************************************************************************/ cy_en_prot_status_t Cy_Prot_EnableSmpuSlaveStruct(PROT_SMPU_SMPU_STRUCT_Type* base) @@ -621,7 +621,7 @@ cy_en_prot_status_t Cy_Prot_EnableSmpuSlaveStruct(PROT_SMPU_SMPU_STRUCT_Type* ba * CY_PROT_FAILURE | The Slave PU struct is enabled and possibly locked. * * \funcusage -* \snippet prot/1.20/snippet/main.c snippet_Cy_Prot_DisableSmpuSlaveStruct +* \snippet prot/snippet/main.c snippet_Cy_Prot_DisableSmpuSlaveStruct * *******************************************************************************/ cy_en_prot_status_t Cy_Prot_DisableSmpuSlaveStruct(PROT_SMPU_SMPU_STRUCT_Type* base) @@ -681,7 +681,7 @@ cy_en_prot_status_t Cy_Prot_DisableSmpuSlaveStruct(PROT_SMPU_SMPU_STRUCT_Type* b * CY_PROT_UNAVAILABLE | The requested structure in use or there were no unused structures. * * \funcusage -* \snippet prot/1.20/snippet/main.c snippet_Cy_Prot_GetSmpuStruct +* \snippet prot/snippet/main.c snippet_Cy_Prot_GetSmpuStruct * *******************************************************************************/ cy_en_prot_status_t Cy_Prot_GetSmpuStruct(PROT_SMPU_SMPU_STRUCT_Type** base, @@ -921,7 +921,7 @@ static cy_en_prot_status_t Prot_ConfigPpuAtt(volatile uint32_t * reg, uint16_t p * \note PC0 accesses are read-only and are always enabled. * * \funcusage -* \snippet prot/1.20/snippet/main.c snippet_Cy_Prot_ConfigPpuProgMasterAtt +* \snippet prot/snippet/main.c snippet_Cy_Prot_ConfigPpuProgMasterAtt * *******************************************************************************/ cy_en_prot_status_t Cy_Prot_ConfigPpuProgMasterAtt(PERI_MS_PPU_PR_Type* base, uint16_t pcMask, @@ -1041,7 +1041,7 @@ cy_en_prot_status_t Cy_Prot_ConfigPpuProgSlaveAddr(PERI_MS_PPU_PR_Type* base, ui * \note PC0 accesses are read-only and are always enabled. * * \funcusage -* \snippet prot/1.20/snippet/main.c snippet_Cy_Prot_ConfigPpuProgSlaveAtt +* \snippet prot/snippet/main.c snippet_Cy_Prot_ConfigPpuProgSlaveAtt * *******************************************************************************/ cy_en_prot_status_t Cy_Prot_ConfigPpuProgSlaveAtt(PERI_MS_PPU_PR_Type* base, uint16_t pcMask, @@ -1127,7 +1127,7 @@ cy_en_prot_status_t Cy_Prot_EnablePpuProgSlaveRegion(PERI_MS_PPU_PR_Type* base) * CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version. * * \funcusage -* \snippet prot/1.20/snippet/main.c snippet_Cy_Prot_DisablePpuProgSlaveRegion +* \snippet prot/snippet/main.c snippet_Cy_Prot_DisablePpuProgSlaveRegion * *******************************************************************************/ cy_en_prot_status_t Cy_Prot_DisablePpuProgSlaveRegion(PERI_MS_PPU_PR_Type* base) @@ -1200,7 +1200,7 @@ cy_en_prot_status_t Cy_Prot_DisablePpuProgSlaveRegion(PERI_MS_PPU_PR_Type* base) * \note PC0 accesses are read-only and are always enabled. * * \funcusage -* \snippet prot/1.20/snippet/main.c snippet_Cy_Prot_ConfigPpuFixedMasterAtt +* \snippet prot/snippet/main.c snippet_Cy_Prot_ConfigPpuFixedMasterAtt * *******************************************************************************/ cy_en_prot_status_t Cy_Prot_ConfigPpuFixedMasterAtt(PERI_MS_PPU_FX_Type* base, uint16_t pcMask, @@ -1260,7 +1260,7 @@ cy_en_prot_status_t Cy_Prot_ConfigPpuFixedMasterAtt(PERI_MS_PPU_FX_Type* base, u * \note PC0 accesses are read-only and are always enabled. * * \funcusage -* \snippet prot/1.20/snippet/main.c snippet_Cy_Prot_ConfigPpuFixedSlaveAtt +* \snippet prot/snippet/main.c snippet_Cy_Prot_ConfigPpuFixedSlaveAtt * *******************************************************************************/ cy_en_prot_status_t Cy_Prot_ConfigPpuFixedSlaveAtt(PERI_MS_PPU_FX_Type* base, uint16_t pcMask, @@ -1309,7 +1309,7 @@ cy_en_prot_status_t Cy_Prot_ConfigPpuFixedSlaveAtt(PERI_MS_PPU_FX_Type* base, ui * CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version. * * \funcusage -* \snippet prot/1.20/snippet/main.c snippet_Cy_Prot_ConfigPpuProgMasterStruct +* \snippet prot/snippet/main.c snippet_Cy_Prot_ConfigPpuProgMasterStruct * *******************************************************************************/ cy_en_prot_status_t Cy_Prot_ConfigPpuProgMasterStruct(PERI_PPU_PR_Type* base, const cy_stc_ppu_prog_cfg_t* config) @@ -1386,7 +1386,7 @@ cy_en_prot_status_t Cy_Prot_ConfigPpuProgMasterStruct(PERI_PPU_PR_Type* base, co * CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version. * * \funcusage -* \snippet prot/1.20/snippet/main.c snippet_Cy_Prot_ConfigPpuProgSlaveStruct +* \snippet prot/snippet/main.c snippet_Cy_Prot_ConfigPpuProgSlaveStruct * *******************************************************************************/ cy_en_prot_status_t Cy_Prot_ConfigPpuProgSlaveStruct(PERI_PPU_PR_Type* base, const cy_stc_ppu_prog_cfg_t* config) @@ -1460,7 +1460,7 @@ cy_en_prot_status_t Cy_Prot_ConfigPpuProgSlaveStruct(PERI_PPU_PR_Type* base, con * CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version. * * \funcusage -* \snippet prot/1.20/snippet/main.c snippet_Cy_Prot_EnablePpuProgMasterStruct +* \snippet prot/snippet/main.c snippet_Cy_Prot_EnablePpuProgMasterStruct * *******************************************************************************/ cy_en_prot_status_t Cy_Prot_EnablePpuProgMasterStruct(PERI_PPU_PR_Type* base) @@ -1505,7 +1505,7 @@ cy_en_prot_status_t Cy_Prot_EnablePpuProgMasterStruct(PERI_PPU_PR_Type* base) * CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version. * * \funcusage -* \snippet prot/1.20/snippet/main.c snippet_Cy_Prot_DisablePpuProgMasterStruct +* \snippet prot/snippet/main.c snippet_Cy_Prot_DisablePpuProgMasterStruct * *******************************************************************************/ cy_en_prot_status_t Cy_Prot_DisablePpuProgMasterStruct(PERI_PPU_PR_Type* base) @@ -1549,7 +1549,7 @@ cy_en_prot_status_t Cy_Prot_DisablePpuProgMasterStruct(PERI_PPU_PR_Type* base) * CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version. * * \funcusage -* \snippet prot/1.20/snippet/main.c snippet_Cy_Prot_EnablePpuProgSlaveStruct +* \snippet prot/snippet/main.c snippet_Cy_Prot_EnablePpuProgSlaveStruct * *******************************************************************************/ cy_en_prot_status_t Cy_Prot_EnablePpuProgSlaveStruct(PERI_PPU_PR_Type* base) @@ -1594,7 +1594,7 @@ cy_en_prot_status_t Cy_Prot_EnablePpuProgSlaveStruct(PERI_PPU_PR_Type* base) * CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version. * * \funcusage -* \snippet prot/1.20/snippet/main.c snippet_Cy_Prot_DisablePpuProgSlaveStruct +* \snippet prot/snippet/main.c snippet_Cy_Prot_DisablePpuProgSlaveStruct * *******************************************************************************/ cy_en_prot_status_t Cy_Prot_DisablePpuProgSlaveStruct(PERI_PPU_PR_Type* base) @@ -1660,7 +1660,7 @@ cy_en_prot_status_t Cy_Prot_DisablePpuProgSlaveStruct(PERI_PPU_PR_Type* base) * CY_PROT_INVALID_STATE | Function was called on unsupported PERI HW version. * * \funcusage -* \snippet prot/1.20/snippet/main.c snippet_Cy_Prot_GetPpuProgStruct +* \snippet prot/snippet/main.c snippet_Cy_Prot_GetPpuProgStruct * *******************************************************************************/ cy_en_prot_status_t Cy_Prot_GetPpuProgStruct(PERI_PPU_PR_Type** base, cy_en_prot_req_mode_t reqMode, uint32_t ppuProgIndex) @@ -1785,7 +1785,7 @@ cy_en_prot_status_t Cy_Prot_GetPpuProgStruct(PERI_PPU_PR_Type** base, cy_en_prot * CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version. * * \funcusage -* \snippet prot/1.20/snippet/main.c snippet_Cy_Prot_ConfigPpuFixedGrMasterStruct +* \snippet prot/snippet/main.c snippet_Cy_Prot_ConfigPpuFixedGrMasterStruct * *******************************************************************************/ cy_en_prot_status_t Cy_Prot_ConfigPpuFixedGrMasterStruct(PERI_PPU_GR_Type* base, const cy_stc_ppu_gr_cfg_t* config) @@ -1867,7 +1867,7 @@ cy_en_prot_status_t Cy_Prot_ConfigPpuFixedGrMasterStruct(PERI_PPU_GR_Type* base, * CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version. * * \funcusage -* \snippet prot/1.20/snippet/main.c snippet_Cy_Prot_ConfigPpuFixedGrSlaveStruct +* \snippet prot/snippet/main.c snippet_Cy_Prot_ConfigPpuFixedGrSlaveStruct * *******************************************************************************/ cy_en_prot_status_t Cy_Prot_ConfigPpuFixedGrSlaveStruct(PERI_PPU_GR_Type* base, const cy_stc_ppu_gr_cfg_t* config) @@ -1936,7 +1936,7 @@ cy_en_prot_status_t Cy_Prot_ConfigPpuFixedGrSlaveStruct(PERI_PPU_GR_Type* base, * CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version. * * \funcusage -* \snippet prot/1.20/snippet/main.c snippet_Cy_Prot_EnablePpuFixedGrMasterStruct +* \snippet prot/snippet/main.c snippet_Cy_Prot_EnablePpuFixedGrMasterStruct * *******************************************************************************/ cy_en_prot_status_t Cy_Prot_EnablePpuFixedGrMasterStruct(PERI_PPU_GR_Type* base) @@ -1981,7 +1981,7 @@ cy_en_prot_status_t Cy_Prot_EnablePpuFixedGrMasterStruct(PERI_PPU_GR_Type* base) * CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version. * * \funcusage -* \snippet prot/1.20/snippet/main.c snippet_Cy_Prot_DisablePpuFixedGrMasterStruct +* \snippet prot/snippet/main.c snippet_Cy_Prot_DisablePpuFixedGrMasterStruct * *******************************************************************************/ cy_en_prot_status_t Cy_Prot_DisablePpuFixedGrMasterStruct(PERI_PPU_GR_Type* base) @@ -2025,7 +2025,7 @@ cy_en_prot_status_t Cy_Prot_DisablePpuFixedGrMasterStruct(PERI_PPU_GR_Type* base * CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version. * * \funcusage -* \snippet prot/1.20/snippet/main.c snippet_Cy_Prot_EnablePpuFixedGrSlaveStruct +* \snippet prot/snippet/main.c snippet_Cy_Prot_EnablePpuFixedGrSlaveStruct * *******************************************************************************/ cy_en_prot_status_t Cy_Prot_EnablePpuFixedGrSlaveStruct(PERI_PPU_GR_Type* base) @@ -2070,7 +2070,7 @@ cy_en_prot_status_t Cy_Prot_EnablePpuFixedGrSlaveStruct(PERI_PPU_GR_Type* base) * CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version. * * \funcusage -* \snippet prot/1.20/snippet/main.c snippet_Cy_Prot_DisablePpuFixedGrSlaveStruct +* \snippet prot/snippet/main.c snippet_Cy_Prot_DisablePpuFixedGrSlaveStruct * *******************************************************************************/ cy_en_prot_status_t Cy_Prot_DisablePpuFixedGrSlaveStruct(PERI_PPU_GR_Type* base) @@ -2124,7 +2124,7 @@ cy_en_prot_status_t Cy_Prot_DisablePpuFixedGrSlaveStruct(PERI_PPU_GR_Type* base) * CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version. * * \funcusage -* \snippet prot/1.20/snippet/main.c snippet_Cy_Prot_ConfigPpuFixedSlMasterStruct +* \snippet prot/snippet/main.c snippet_Cy_Prot_ConfigPpuFixedSlMasterStruct * *******************************************************************************/ cy_en_prot_status_t Cy_Prot_ConfigPpuFixedSlMasterStruct(PERI_GR_PPU_SL_Type* base, const cy_stc_ppu_sl_cfg_t* config) @@ -2205,7 +2205,7 @@ cy_en_prot_status_t Cy_Prot_ConfigPpuFixedSlMasterStruct(PERI_GR_PPU_SL_Type* ba * CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version. * * \funcusage -* \snippet prot/1.20/snippet/main.c snippet_Cy_Prot_ConfigPpuFixedSlSlaveStruct +* \snippet prot/snippet/main.c snippet_Cy_Prot_ConfigPpuFixedSlSlaveStruct * *******************************************************************************/ cy_en_prot_status_t Cy_Prot_ConfigPpuFixedSlSlaveStruct(PERI_GR_PPU_SL_Type* base, const cy_stc_ppu_sl_cfg_t* config) @@ -2274,7 +2274,7 @@ cy_en_prot_status_t Cy_Prot_ConfigPpuFixedSlSlaveStruct(PERI_GR_PPU_SL_Type* bas * CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version. * * \funcusage -* \snippet prot/1.20/snippet/main.c snippet_Cy_Prot_EnablePpuFixedSlMasterStruct +* \snippet prot/snippet/main.c snippet_Cy_Prot_EnablePpuFixedSlMasterStruct * *******************************************************************************/ cy_en_prot_status_t Cy_Prot_EnablePpuFixedSlMasterStruct(PERI_GR_PPU_SL_Type* base) @@ -2319,7 +2319,7 @@ cy_en_prot_status_t Cy_Prot_EnablePpuFixedSlMasterStruct(PERI_GR_PPU_SL_Type* ba * CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version. * * \funcusage -* \snippet prot/1.20/snippet/main.c snippet_Cy_Prot_DisablePpuFixedSlMasterStruct +* \snippet prot/snippet/main.c snippet_Cy_Prot_DisablePpuFixedSlMasterStruct * *******************************************************************************/ cy_en_prot_status_t Cy_Prot_DisablePpuFixedSlMasterStruct(PERI_GR_PPU_SL_Type* base) @@ -2363,7 +2363,7 @@ cy_en_prot_status_t Cy_Prot_DisablePpuFixedSlMasterStruct(PERI_GR_PPU_SL_Type* b * CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version. * * \funcusage -* \snippet prot/1.20/snippet/main.c snippet_Cy_Prot_EnablePpuFixedSlSlaveStruct +* \snippet prot/snippet/main.c snippet_Cy_Prot_EnablePpuFixedSlSlaveStruct * *******************************************************************************/ cy_en_prot_status_t Cy_Prot_EnablePpuFixedSlSlaveStruct(PERI_GR_PPU_SL_Type* base) @@ -2408,7 +2408,7 @@ cy_en_prot_status_t Cy_Prot_EnablePpuFixedSlSlaveStruct(PERI_GR_PPU_SL_Type* bas * CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version. * * \funcusage -* \snippet prot/1.20/snippet/main.c snippet_Cy_Prot_DisablePpuFixedSlSlaveStruct +* \snippet prot/snippet/main.c snippet_Cy_Prot_DisablePpuFixedSlSlaveStruct * *******************************************************************************/ cy_en_prot_status_t Cy_Prot_DisablePpuFixedSlSlaveStruct(PERI_GR_PPU_SL_Type* base) @@ -2462,7 +2462,7 @@ cy_en_prot_status_t Cy_Prot_DisablePpuFixedSlSlaveStruct(PERI_GR_PPU_SL_Type* ba * CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version. * * \funcusage -* \snippet prot/1.20/snippet/main.c snippet_Cy_Prot_ConfigPpuFixedRgMasterStruct +* \snippet prot/snippet/main.c snippet_Cy_Prot_ConfigPpuFixedRgMasterStruct * *******************************************************************************/ cy_en_prot_status_t Cy_Prot_ConfigPpuFixedRgMasterStruct(PERI_GR_PPU_RG_Type* base, const cy_stc_ppu_rg_cfg_t* config) @@ -2543,7 +2543,7 @@ cy_en_prot_status_t Cy_Prot_ConfigPpuFixedRgMasterStruct(PERI_GR_PPU_RG_Type* ba * CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version. * * \funcusage -* \snippet prot/1.20/snippet/main.c snippet_Cy_Prot_ConfigPpuFixedRgSlaveStruct +* \snippet prot/snippet/main.c snippet_Cy_Prot_ConfigPpuFixedRgSlaveStruct * *******************************************************************************/ cy_en_prot_status_t Cy_Prot_ConfigPpuFixedRgSlaveStruct(PERI_GR_PPU_RG_Type* base, const cy_stc_ppu_rg_cfg_t* config) @@ -2612,7 +2612,7 @@ cy_en_prot_status_t Cy_Prot_ConfigPpuFixedRgSlaveStruct(PERI_GR_PPU_RG_Type* bas * CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version. * * \funcusage -* \snippet prot/1.20/snippet/main.c snippet_Cy_Prot_EnablePpuFixedRgMasterStruct +* \snippet prot/snippet/main.c snippet_Cy_Prot_EnablePpuFixedRgMasterStruct * *******************************************************************************/ cy_en_prot_status_t Cy_Prot_EnablePpuFixedRgMasterStruct(PERI_GR_PPU_RG_Type* base) @@ -2655,7 +2655,7 @@ cy_en_prot_status_t Cy_Prot_EnablePpuFixedRgMasterStruct(PERI_GR_PPU_RG_Type* ba * CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version. * * \funcusage -* \snippet prot/1.20/snippet/main.c snippet_Cy_Prot_DisablePpuFixedRgMasterStruct +* \snippet prot/snippet/main.c snippet_Cy_Prot_DisablePpuFixedRgMasterStruct * *******************************************************************************/ cy_en_prot_status_t Cy_Prot_DisablePpuFixedRgMasterStruct(PERI_GR_PPU_RG_Type* base) @@ -2697,7 +2697,7 @@ cy_en_prot_status_t Cy_Prot_DisablePpuFixedRgMasterStruct(PERI_GR_PPU_RG_Type* b * CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version. * * \funcusage -* \snippet prot/1.20/snippet/main.c snippet_Cy_Prot_EnablePpuFixedRgSlaveStruct +* \snippet prot/snippet/main.c snippet_Cy_Prot_EnablePpuFixedRgSlaveStruct * *******************************************************************************/ cy_en_prot_status_t Cy_Prot_EnablePpuFixedRgSlaveStruct(PERI_GR_PPU_RG_Type* base) @@ -2740,7 +2740,7 @@ cy_en_prot_status_t Cy_Prot_EnablePpuFixedRgSlaveStruct(PERI_GR_PPU_RG_Type* bas * CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version. * * \funcusage -* \snippet prot/1.20/snippet/main.c snippet_Cy_Prot_DisablePpuFixedRgSlaveStruct +* \snippet prot/snippet/main.c snippet_Cy_Prot_DisablePpuFixedRgSlaveStruct * *******************************************************************************/ cy_en_prot_status_t Cy_Prot_DisablePpuFixedRgSlaveStruct(PERI_GR_PPU_RG_Type* base) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_common.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_common.c index 35f067ebc0..d9bb6a4ee1 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_common.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_common.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_scb_common.c -* \version 2.20 +* \version 2.30 * * Provides common API implementation of the SCB driver. * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_ezi2c.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_ezi2c.c index fbc4c90e3f..c12dac2007 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_ezi2c.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_ezi2c.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_scb_ezi2c.c -* \version 2.20 +* \version 2.30 * * Provides EZI2C API implementation of the SCB driver. * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_i2c.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_i2c.c index 72beee8ecc..f591fb35bb 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_i2c.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_i2c.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_scb_i2c.c -* \version 2.20 +* \version 2.30 * * Provides I2C API implementation of the SCB driver. * @@ -77,9 +77,6 @@ static uint32_t WaitOneUnit(uint32_t *timeout); *******************************************************************************/ cy_en_scb_i2c_status_t Cy_SCB_I2C_Init(CySCB_Type *base, cy_stc_scb_i2c_config_t const *config, cy_stc_scb_i2c_context_t *context) { - /* Enable digital filter for only for master modes */ - bool enableDigFilter = (CY_SCB_I2C_SLAVE != config->i2cMode) && (config->enableDigitalFilter); - /* Input parameters verification */ if ((NULL == base) || (NULL == config) || (NULL == context)) { @@ -102,13 +99,18 @@ cy_en_scb_i2c_status_t Cy_SCB_I2C_Init(CySCB_Type *base, cy_stc_scb_i2c_config_t _VAL2FLD(SCB_I2C_CTRL_HIGH_PHASE_OVS, (config->highPhaseDutyCycle - 1U)) | _VAL2FLD(SCB_I2C_CTRL_LOW_PHASE_OVS, (config->lowPhaseDutyCycle - 1U)) | _VAL2FLD(CY_SCB_I2C_CTRL_MODE, (uint32_t) config->i2cMode); + + { + /* Enable digital filter for only for master modes */ + bool enableDigFilter = (CY_SCB_I2C_SLAVE != config->i2cMode) && (config->enableDigitalFilter); + + /* Configure the RX direction */ + SCB_RX_CTRL(base) = _BOOL2FLD(SCB_RX_CTRL_MEDIAN, enableDigFilter) | + CY_SCB_I2C_RX_CTRL; - /* Configure the RX direction */ - SCB_RX_CTRL(base) = _BOOL2FLD(SCB_RX_CTRL_MEDIAN, enableDigFilter) | - CY_SCB_I2C_RX_CTRL; - - /* Configure an analog filter */ - SCB_I2C_CFG(base) = (enableDigFilter) ? CY_SCB_I2C_DISABLE_ANALOG_FITLER : CY_SCB_I2C_ENABLE_ANALOG_FITLER; + /* Configure an analog filter */ + SCB_I2C_CFG(base) = (enableDigFilter) ? CY_SCB_I2C_DISABLE_ANALOG_FITLER : CY_SCB_I2C_ENABLE_ANALOG_FITLER; + } SCB_RX_FIFO_CTRL(base) = (config->useRxFifo ? (CY_SCB_I2C_FIFO_SIZE - 1UL) : 0UL); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_spi.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_spi.c index 8cd5f1b3fc..58e30b4fb6 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_spi.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_spi.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_scb_spi.c -* \version 2.20 +* \version 2.30 * * Provides SPI API implementation of the SCB driver. * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_uart.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_uart.c index e71d15b3ea..cbdebe6ebd 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_uart.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_uart.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_scb_uart.c -* \version 2.20 +* \version 2.30 * * Provides UART API implementation of the SCB driver. * @@ -1131,6 +1131,17 @@ void Cy_SCB_UART_Interrupt(CySCB_Type *base, cy_stc_scb_uart_context_t *context) Cy_SCB_ClearRxInterrupt(base, CY_SCB_RX_INTR_LEVEL); } + + if (0UL != (CY_SCB_RX_INTR_NOT_EMPTY & Cy_SCB_GetRxInterruptStatusMasked(base))) + { + if (NULL != context->cbEvents) + { + context->cbEvents(CY_SCB_UART_RECEIVE_NOT_EMTPY); + } + + Cy_SCB_ClearRxInterrupt(base, CY_SCB_RX_INTR_NOT_EMPTY); + } + } if (0UL != (CY_SCB_TX_INTR & Cy_SCB_GetInterruptCause(base))) @@ -1171,6 +1182,17 @@ void Cy_SCB_UART_Interrupt(CySCB_Type *base, cy_stc_scb_uart_context_t *context) context->cbEvents(CY_SCB_UART_TRANSMIT_DONE_EVENT); } } + + if (0UL != (CY_SCB_UART_TX_EMPTY & Cy_SCB_GetTxInterruptStatusMasked(base))) + { + if (NULL != context->cbEvents) + { + context->cbEvents(CY_SCB_UART_TRANSMIT_EMTPY); + } + + Cy_SCB_ClearTxInterrupt(base, CY_SCB_UART_TX_EMPTY); + } + } } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_sd_host.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_sd_host.c index 4aa5f434ef..0ebb8516ca 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_sd_host.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_sd_host.c @@ -1,6 +1,6 @@ /******************************************************************************* * \file cy_sd_host.c -* \version 1.10 +* \version 1.20 * * \brief * This file provides the driver code to the API for the SD Host Controller @@ -4821,6 +4821,87 @@ uint32_t Cy_SD_Host_GetPresentState(SDHC_Type const *base) return ret; } + +/******************************************************************************* +* Function Name: Cy_SD_Host_DeepSleepCallback +****************************************************************************//** +* +* This function handles the transition of the SD Host into and out of +* Deep Sleep mode. It disables SD CLK before going to Deep Sleep mode and +* enables SD CLK after wake up from Deep Sleep mode. +* If the DAT line is active, or a read (write) transfer is being executed on +* the bus, the device cannot enter Deep Sleep mode. +* +* This function must be called during execution of \ref Cy_SysPm_CpuEnterDeepSleep. +* To do it, register this function as a callback before calling +* \ref Cy_SysPm_CpuEnterDeepSleep : specify \ref CY_SYSPM_DEEPSLEEP as the callback +* type and call \ref Cy_SysPm_RegisterCallback. +* +* \param callbackParams +* The pointer to the callback parameters structure +* \ref cy_stc_syspm_callback_params_t. +* +* \param mode +* Callback mode, see \ref cy_en_syspm_callback_mode_t +* +* \return +* \ref cy_en_syspm_status_t +* +*******************************************************************************/ +cy_en_syspm_status_t Cy_SD_Host_DeepSleepCallback(cy_stc_syspm_callback_params_t *callbackParams, + cy_en_syspm_callback_mode_t mode) +{ + cy_en_syspm_status_t ret = CY_SYSPM_FAIL; + SDHC_Type *locBase = (SDHC_Type *) (callbackParams->base); + + switch(mode) + { + case CY_SYSPM_CHECK_READY: + { + /* Check DAT Line Active */ + uint32_t pState = Cy_SD_Host_GetPresentState(locBase); + if ((CY_SD_HOST_DAT_LINE_ACTIVE != (pState & CY_SD_HOST_DAT_LINE_ACTIVE)) && + (CY_SD_HOST_CMD_CMD_INHIBIT_DAT != (pState & CY_SD_HOST_CMD_CMD_INHIBIT_DAT))) + { + ret = CY_SYSPM_SUCCESS; + } + } + break; + + case CY_SYSPM_CHECK_FAIL: + { + ret = CY_SYSPM_SUCCESS; + } + break; + + case CY_SYSPM_BEFORE_TRANSITION: + { + /* Disable SD CLK before going to Deep Sleep mode */ + Cy_SD_Host_DisableSdClk(locBase); + + ret = CY_SYSPM_SUCCESS; + } + break; + + case CY_SYSPM_AFTER_TRANSITION: + { + /* Enable SD CLK after wake up from Deep Sleep mode */ + Cy_SD_Host_EnableSdClk(locBase); + + /* Wait for the stable CLK */ + Cy_SysLib_Delay(CY_SD_HOST_CLK_RAMP_UP_TIME_MS); + + ret = CY_SYSPM_SUCCESS; + } + break; + + default: + break; + } + + return (ret); +} + #if defined(__cplusplus) } #endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_seglcd.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_seglcd.c new file mode 100644 index 0000000000..a236b0e4d9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_seglcd.c @@ -0,0 +1,969 @@ +/***************************************************************************//** +* \file cy_seglcd.c +* \version 1.0 +* +* \brief +* Provides an API implementation of the SegLCD driver +* +******************************************************************************** +* \copyright +* Copyright 2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#include "cy_seglcd.h" +#include "cy_sysclk.h" + +#if defined(CY_IP_MXLCD) + +#define CY_SEGLCD_ENABLE_Msk (LCD_CONTROL_LS_EN_Msk | LCD_CONTROL_HS_EN_Msk) +#define CY_SEGLCD_NIBBLE (4UL) + +#define CY_SEGLCD_DIV_MAX (0x0000FFFFUL) /* The max. divider values */ +#define CY_SEGLCD_DIV_MAX_LS_VER1 (0x000000FFUL) /* The max. divider values for Low Speed mode for MXLCD_ver1 */ + +#define CY_SEGLCD_SYM_BIT_IDX_Pos (0U) +#define CY_SEGLCD_SYM_BIT_IDX_Msk ((uint32_t) 0x00000007UL << CY_SEGLCD_SYM_BIT_IDX_Pos) +#define CY_SEGLCD_SYM_BYTE_IDX_Pos (3U) +#define CY_SEGLCD_SYM_BYTE_IDX_Msk ((uint32_t) 0x00001FFFUL << CY_SEGLCD_SYM_BYTE_IDX_Pos) + +#define CY_SEGLCD_PIX_Pos(pixel) ((CY_SEGLCD_EXTR_NBL(pixel) * CY_SEGLCD_NIBBLE) + \ + (CY_SEGLCD_EXTR_COM(pixel) % CY_SEGLCD_NIBBLE)) +#define CY_SEGLCD_PIX_Msk(pixel) ((uint32_t)(1UL << CY_SEGLCD_PIX_Pos(pixel))) + +#define CY_SEGLCD_REVISION(base) (_FLD2VAL(LCD_ID_REVISION, LCD_ID(base))) +#define CY_SEGLCD_REV_1(base) (1UL == CY_SEGLCD_REVISION(base)) +#define CY_SEGLCD_IS_ENABLED(base) (0UL != (LCD_CONTROL(base) & CY_SEGLCD_ENABLE_Msk)) +#define CY_SEGLCD_IS_MSK_VALID(pixel) (0UL == ((pixel) & ~(CY_SEGLCD_COM_Msk | CY_SEGLCD_OCT_Msk | CY_SEGLCD_NBL_Msk))) +#define CY_SEGLCD_IS_COM_VALID(pixel) (LCD_COM_NUM > CY_SEGLCD_EXTR_COM(pixel)) +#define CY_SEGLCD_IS_PIX_VALID(pixel) (CY_SEGLCD_IS_MSK_VALID(pixel) && CY_SEGLCD_IS_COM_VALID(pixel)) + + +#define CY_SEGLCD_COM_NUM_MIN (2U) +#define CY_SEGLCD_COM_NUM_MAX (LCD_COM_NUM) +#define CY_SEGLCD_IS_COM_NUM_VALID(num) ((CY_SEGLCD_COM_NUM_MIN <= (num)) && ((num) <= CY_SEGLCD_COM_NUM_MAX)) + +#define CY_SEGLCD_IS_BASIC(type) (((uint16_t)CY_SEGLCD_7SEG == (type)) || \ + ((uint16_t)CY_SEGLCD_14SEG == (type)) || \ + ((uint16_t)CY_SEGLCD_16SEG == (type)) || \ + ((uint16_t)CY_SEGLCD_5X8DM == (type))) + +#define CY_SEGLCD_IS_PIXMAP(disp) ((NULL != (disp)) && \ + (NULL != (disp)->pixMap)) + +#define CY_SEGLCD_IS_SYMBOLIC(disp, pos) (CY_SEGLCD_IS_PIXMAP(disp) && \ + (NULL != (disp)->font) && \ + (NULL != (disp)->font->fontMap) && \ + ((uint32_t)CY_SEGLCD_BAR < (disp)->type) && \ + (((pos) < (disp)->symNum))) + +#define CY_SEGLCD_IS_ASCII(disp, pos) (CY_SEGLCD_IS_SYMBOLIC(disp, pos) && \ + ((disp)->font->ascii)) + +#define CY_SEGLCD_IS_BARGRAPH(disp, pos) (CY_SEGLCD_IS_PIXMAP(disp) && \ + ((uint32_t)CY_SEGLCD_BAR == (disp)->type) && \ + (((pos) < (disp)->symNum))) + +#define CY_SEGLCD_IS_SPEED_VALID(speed) ((CY_SEGLCD_SPEED_LOW == (speed)) || \ + (CY_SEGLCD_SPEED_HIGH == (speed))) + +#define CY_SEGLCD_IS_WAVE_VALID(wave) ((CY_SEGLCD_TYPE_A == (wave)) || \ + (CY_SEGLCD_TYPE_B == (wave))) + +#define CY_SEGLCD_IS_DRIVE_VALID(drive) ((CY_SEGLCD_PWM == (drive)) || \ + (CY_SEGLCD_CORRELATION == (drive))) + +#define CY_SEGLCD_IS_BIAS_4_5_SUPPORTED(base,speed) ((CY_SEGLCD_REV_1(base)) ? (CY_SEGLCD_SPEED_HIGH == (speed)) : true) + +#define CY_SEGLCD_IS_BIAS_VALID(base,bias,speed) ((CY_SEGLCD_BIAS_HALF == (bias)) || \ + (CY_SEGLCD_BIAS_THIRD == (bias)) || \ + (CY_SEGLCD_IS_BIAS_4_5_SUPPORTED(base,speed) && (CY_SEGLCD_BIAS_FOURTH == (bias))) || \ + (CY_SEGLCD_IS_BIAS_4_5_SUPPORTED(base,speed) && (CY_SEGLCD_BIAS_FIFTH == (bias)))) + +#define CY_SEGLCD_IS_LSCLK_VALID(lsClk) ((CY_SEGLCD_LSCLK_LF == (lsClk)) || \ + (CY_SEGLCD_LSCLK_MF == (lsClk))) + +#define CY_SEGLCD_FR_RATE_MIN (30) +#define CY_SEGLCD_FR_RATE_MAX (150) +#define CY_SEGLCD_IS_RATE_VALID(frRate) (((frRate) >= CY_SEGLCD_FR_RATE_MIN) && ((frRate) <= CY_SEGLCD_FR_RATE_MAX)) + +#define CY_SEGLCD_CNTR_MAX (100UL) +#define CY_SEGLCD_IS_CNTR_VALID(contrast) (((uint32_t)(contrast)) <= CY_SEGLCD_CNTR_MAX) + +#define CY_SEGLCD_FREQ_MIN (10000) +#define CY_SEGLCD_FREQ_MAX (100000000) +#define CY_SEGLCD_IS_FREQ_VALID(freq) (((freq) >= CY_SEGLCD_FREQ_MIN) && ((freq) <= CY_SEGLCD_FREQ_MAX)) + +#define CY_SEGLCD_SPACE(disp) (((disp)->font->ascii) ? ' ' : CY_SEGLCD_NUM_BLANK) + +/* The timeout value for Low Speed mode enable/disable procedures, two ILO clock periods, in uSeconds */ +#define CY_SEGLCD_TIMEOUT ((2U * 1000000UL) / CY_SYSCLK_ILO_FREQ) + + +static volatile uint32_t * GetDataRegPtr(LCD_Type * base, uint32_t pixel); +static void InvClrData(LCD_Type * base, bool inv); +static char_t NumToChar(uint32_t value); + + +static const uint8_t fontMap7[] = /* Apparently the 7-segment font character code fits into a single byte so the 'font map symbol size' is not used here */ +/*'0' '1' '2' '3' '4' '5' '6' '7' '8' '9' 'A' 'B' 'C' 'D' 'E' 'F' 'blank'*/ +{0x3FU,0x06U,0x5BU,0x4FU,0x66U,0x6DU,0x7DU,0x07U,0x7FU,0x6FU,0x77U,0x7CU,0x39U,0x5EU,0x79U,0x71U,0x00U}; + +const cy_stc_seglcd_font_t cy_segLCD_7SegFont = +{ + .first = '\0', + .last = CY_SEGLCD_NUM_BLANK, + .ascii = false, + .fontMap = fontMap7 +}; + + +static const uint8_t fontMap14[][CY_SEGLCD_14SEG_FONTMAP_SIZE] = +{ + /* space ! " # $ % & ' */ + {0x00U,0x00U},{0x06U,0x00U},{0x20U,0x01U},{0xFFU,0x3FU},{0x6DU,0x15U},{0xE4U,0x2EU},{0x8DU,0x2AU},{0x00U,0x02U}, + /* ( ) * + , - . / */ + {0x00U,0x0AU},{0x80U,0x20U},{0xC0U,0x3FU},{0x40U,0x15U},{0x00U,0x20U},{0x40U,0x04U},{0x58U,0x10U},{0x00U,0x22U}, + /* 0 1 2 3 4 5 6 7 */ + {0x3FU,0x22U},{0x06U,0x02U},{0x5BU,0x04U},{0x0FU,0x04U},{0x66U,0x04U},{0x69U,0x08U},{0x7DU,0x04U},{0x01U,0x12U}, + /* 8 9 : ; < = > ? */ + {0x7FU,0x04U},{0x6FU,0x04U},{0x00U,0x11U},{0x00U,0x21U},{0x00U,0x0AU},{0x48U,0x04U},{0x80U,0x20U},{0x23U,0x14U}, + /* @ A B C D E F G */ + {0x3BU,0x05U},{0x77U,0x04U},{0x0FU,0x15U},{0x39U,0x00U},{0x0FU,0x11U},{0x79U,0x00U},{0x71U,0x00U},{0x3DU,0x04U}, + /* H I J K L M N O */ + {0x76U,0x04U},{0x00U,0x11U},{0x1EU,0x00U},{0x70U,0x0AU},{0x38U,0x00U},{0xB6U,0x02U},{0xB6U,0x08U},{0x3FU,0x00U}, + /* P Q R S T U V W */ + {0x73U,0x04U},{0x3FU,0x08U},{0x73U,0x0CU},{0x6DU,0x04U},{0x01U,0x11U},{0x3EU,0x00U},{0x30U,0x22U},{0x36U,0x28U}, + /* X Y Z [ \ ] ^ _ */ + {0x80U,0x2AU},{0x80U,0x12U},{0x09U,0x22U},{0x39U,0x00U},{0x80U,0x08U},{0x0FU,0x00U},{0x03U,0x00U},{0x08U,0x00U}, + /* ` a b c d e f g */ + {0x00U,0x02U},{0x77U,0x04U},{0x0FU,0x15U},{0x39U,0x00U},{0x0FU,0x11U},{0x79U,0x00U},{0x71U,0x00U},{0x3DU,0x04U}, + /* h i j k l m n o */ + {0x76U,0x04U},{0x00U,0x11U},{0x1EU,0x00U},{0x70U,0x0AU},{0x38U,0x00U},{0xB6U,0x02U},{0xB6U,0x08U},{0x3FU,0x00U}, + /* p q r s t u v w */ + {0x73U,0x04U},{0x3FU,0x08U},{0x73U,0x0CU},{0x6DU,0x04U},{0x01U,0x11U},{0x3EU,0x00U},{0x30U,0x22U},{0x36U,0x28U}, + /* x y z { | } ~ */ + {0x80U,0x2AU},{0x80U,0x12U},{0x09U,0x22U},{0x00U,0x0EU},{0x00U,0x11U},{0xC0U,0x20U},{0x52U,0x04U} +}; + +const cy_stc_seglcd_font_t cy_segLCD_14SegFont = +{ + .first = ' ', + .last = '~', + .ascii = true, + .fontMap = (uint8_t*)fontMap14 +}; + + +static const uint8_t fontMap16[][CY_SEGLCD_16SEG_FONTMAP_SIZE] = +{ + /* space ! " # $ % & ' */ + {0x00U,0x00U},{0x0CU,0x00U},{0x80U,0x04U},{0xFFU,0xFFU},{0xBBU,0x55U},{0x99U,0xDDU},{0x3BU,0xAAU},{0x00U,0x08U}, + /* ( ) * + , - . / */ + {0x00U,0x28U},{0x00U,0x82U},{0x00U,0xFFU},{0x00U,0x55U},{0x00U,0x80U},{0x00U,0x11U},{0x60U,0x41U},{0x00U,0x88U}, + /* 0 1 2 3 4 5 6 7 */ + {0xFFU,0x88U},{0x0CU,0x00U},{0x77U,0x11U},{0x3FU,0x10U},{0x8CU,0x11U},{0xB3U,0x21U},{0xFBU,0x11U},{0x03U,0x48U}, + /* 8 9 : ; < = > ? */ + {0xFFU,0x11U},{0xBFU,0x11U},{0x00U,0x44U},{0x00U,0x84U},{0x00U,0x28U},{0x30U,0x11U},{0x00U,0x82U},{0x87U,0x50U}, + /* @ A B C D E F G */ + {0xF7U,0x14U},{0xCFU,0x11U},{0x3FU,0x54U},{0xF3U,0x00U},{0x3FU,0x44U},{0xF3U,0x01U},{0xC3U,0x01U},{0xFBU,0x10U}, + /* H I J K L M N O */ + {0xCCU,0x11U},{0x00U,0x44U},{0x7EU,0x00U},{0xC0U,0x29U},{0xF0U,0x00U},{0xCCU,0x0AU},{0xCCU,0x22U},{0xFFU,0x00U}, + /* P Q R S T U V W */ + {0xC7U,0x11U},{0xFFU,0x20U},{0xC7U,0x31U},{0xBBU,0x11U},{0x03U,0x44U},{0xFCU,0x00U},{0xC0U,0x88U},{0xCCU,0xA0U}, + /* X Y Z [ \ ] ^ _ */ + {0x00U,0xAAU},{0x00U,0x4AU},{0x33U,0x88U},{0x12U,0x44U},{0x00U,0x22U},{0x21U,0x44U},{0x06U,0x00U},{0x30U,0x00U}, + /* ` a b c d e f g */ + {0x00U,0x08U},{0xCFU,0x11U},{0x3FU,0x54U},{0xF3U,0x00U},{0x3FU,0x44U},{0xF3U,0x01U},{0xC3U,0x01U},{0xFBU,0x10U}, + /* h i j k l m n o */ + {0xCCU,0x11U},{0x00U,0x44U},{0x7EU,0x00U},{0xC0U,0x29U},{0xF0U,0x00U},{0xCCU,0x0AU},{0xCCU,0x22U},{0xFFU,0x00U}, + /* p q r s t u v w */ + {0xC7U,0x11U},{0xFFU,0x20U},{0xC7U,0x31U},{0xBBU,0x11U},{0x03U,0x44U},{0xFCU,0x00U},{0xC0U,0x88U},{0xCCU,0xA0U}, + /* x y z { | } ~ */ + {0x00U,0xAAU},{0x00U,0x4AU},{0x33U,0x88U},{0x00U,0x38U},{0x00U,0x44U},{0x00U,0x83U},{0x44U,0x11U} +}; + +const cy_stc_seglcd_font_t cy_segLCD_16SegFont = +{ + .first = ' ', + .last = '~', + .ascii = true, + .fontMap = (uint8_t*)fontMap16 +}; + + +static const uint8_t fontMap5x8[][CY_SEGLCD_5X8DM_FONTMAP_SIZE] = +{ + /* space ! " # */ + {0x00U,0x00U,0x00U,0x00U,0x00U},{0x00U,0x00U,0x4FU,0x00U,0x00U},{0x00U,0x07U,0x00U,0x07U,0x00U},{0x14U,0x7FU,0x14U,0x7FU,0x14U}, + /* $ % & ' */ + {0x24U,0x2AU,0x7FU,0x2AU,0x12U},{0x23U,0x13U,0x08U,0x64U,0x62U},{0x36U,0x49U,0x55U,0x22U,0x50U},{0x00U,0x05U,0x03U,0x00U,0x00U}, + /* ( ) * + */ + {0x00U,0x1CU,0x22U,0x41U,0x00U},{0x00U,0x41U,0x22U,0x1CU,0x00U},{0x14U,0x08U,0x3EU,0x08U,0x14U},{0x08U,0x08U,0x3EU,0x08U,0x08U}, + /* , - . / */ + {0x00U,0x50U,0x30U,0x00U,0x00U},{0x08U,0x08U,0x08U,0x08U,0x08U},{0x00U,0x60U,0x60U,0x00U,0x00U},{0x20U,0x10U,0x08U,0x04U,0x02U}, + /* 0 1 2 3 */ + {0x3EU,0x51U,0x49U,0x45U,0x3EU},{0x00U,0x42U,0x7FU,0x40U,0x00U},{0x42U,0x61U,0x51U,0x49U,0x46U},{0x21U,0x41U,0x45U,0x4BU,0x31U}, + /* 4 5 6 7 */ + {0x18U,0x14U,0x12U,0x7FU,0x10U},{0x27U,0x45U,0x45U,0x45U,0x39U},{0x3CU,0x4AU,0x49U,0x49U,0x30U},{0x01U,0x71U,0x09U,0x05U,0x03U}, + /* 8 9 : ; */ + {0x36U,0x49U,0x49U,0x49U,0x36U},{0x06U,0x49U,0x49U,0x29U,0x1EU},{0x00U,0x36U,0x36U,0x00U,0x00U},{0x00U,0x56U,0x36U,0x00U,0x00U}, + /* < = > ? */ + {0x08U,0x14U,0x22U,0x41U,0x00U},{0x14U,0x14U,0x14U,0x14U,0x14U},{0x00U,0x41U,0x22U,0x14U,0x08U},{0x02U,0x01U,0x51U,0x09U,0x06U}, + /* @ A B C */ + {0x32U,0x49U,0x79U,0x41U,0x3EU},{0x7EU,0x11U,0x11U,0x11U,0x7EU},{0x7FU,0x49U,0x49U,0x49U,0x36U},{0x3EU,0x41U,0x41U,0x41U,0x22U}, + /* D E F G */ + {0x7FU,0x41U,0x41U,0x22U,0x1CU},{0x7FU,0x49U,0x49U,0x49U,0x41U},{0x7FU,0x09U,0x09U,0x09U,0x01U},{0x3EU,0x41U,0x49U,0x49U,0x3AU}, + /* H I J K */ + {0x7FU,0x08U,0x08U,0x08U,0x7FU},{0x00U,0x41U,0x7FU,0x41U,0x00U},{0x20U,0x40U,0x41U,0x3FU,0x01U},{0x7FU,0x08U,0x14U,0x22U,0x41U}, + /* L M N O */ + {0x7FU,0x40U,0x40U,0x40U,0x40U},{0x7FU,0x02U,0x0CU,0x02U,0x7FU},{0x7FU,0x04U,0x08U,0x10U,0x7FU},{0x3EU,0x41U,0x41U,0x41U,0x3EU}, + /* P Q R S */ + {0x7FU,0x09U,0x09U,0x09U,0x06U},{0x3EU,0x41U,0x51U,0x21U,0x5EU},{0x7FU,0x09U,0x19U,0x29U,0x46U},{0x46U,0x49U,0x49U,0x49U,0x31U}, + /* T U V W */ + {0x01U,0x01U,0x7FU,0x01U,0x01U},{0x3FU,0x40U,0x40U,0x40U,0x3FU},{0x1FU,0x20U,0x40U,0x20U,0x1FU},{0x3FU,0x40U,0x38U,0x40U,0x3FU}, + /* X Y Z [ */ + {0x63U,0x14U,0x08U,0x14U,0x63U},{0x07U,0x08U,0x70U,0x08U,0x07U},{0x61U,0x51U,0x49U,0x45U,0x43U},{0x00U,0x7FU,0x41U,0x41U,0x00U}, + /* \ ] ^ _ */ + {0x15U,0x16U,0x7CU,0x16U,0x15U},{0x00U,0x41U,0x41U,0x7FU,0x00U},{0x04U,0x02U,0x01U,0x02U,0x04U},{0x40U,0x40U,0x40U,0x40U,0x40U}, + /* ` a b c */ + {0x00U,0x01U,0x02U,0x04U,0x00U},{0x20U,0x54U,0x54U,0x54U,0x78U},{0x7FU,0x48U,0x44U,0x44U,0x38U},{0x38U,0x44U,0x44U,0x44U,0x40U}, + /* d e f g */ + {0x38U,0x44U,0x44U,0x48U,0x7FU},{0x38U,0x54U,0x54U,0x54U,0x18U},{0x08U,0x7EU,0x09U,0x01U,0x02U},{0x0CU,0x52U,0x52U,0x52U,0x3EU}, + /* h i j k */ + {0x7FU,0x08U,0x04U,0x04U,0x78U},{0x00U,0x44U,0x7DU,0x40U,0x00U},{0x20U,0x40U,0x40U,0x3DU,0x00U},{0x7FU,0x10U,0x28U,0x44U,0x00U}, + /* l m n o */ + {0x00U,0x41U,0x7FU,0x40U,0x00U},{0x7CU,0x04U,0x18U,0x04U,0x78U},{0x7CU,0x08U,0x04U,0x04U,0x78U},{0x38U,0x44U,0x44U,0x44U,0x38U}, + /* p q r s */ + {0x7CU,0x14U,0x14U,0x14U,0x08U},{0x08U,0x14U,0x14U,0x18U,0x7CU},{0x7CU,0x08U,0x04U,0x04U,0x08U},{0x48U,0x54U,0x54U,0x54U,0x20U}, + /* t u v w */ + {0x04U,0x3FU,0x44U,0x40U,0x20U},{0x3CU,0x40U,0x40U,0x20U,0x7CU},{0x1CU,0x20U,0x40U,0x20U,0x1CU},{0x3CU,0x40U,0x30U,0x40U,0x3CU}, + /* x y z { */ + {0x44U,0x28U,0x10U,0x28U,0x44U},{0x0CU,0x50U,0x50U,0x50U,0x3CU},{0x44U,0x64U,0x54U,0x4CU,0x44U},{0x00U,0x08U,0x36U,0x41U,0x00U}, + /* | } ~ */ + {0x00U,0x00U,0x7FU,0x00U,0x00U},{0x00U,0x41U,0x36U,0x08U,0x00U},{0x08U,0x04U,0x08U,0x10U,0x08U} +}; + +const cy_stc_seglcd_font_t cy_segLCD_5x8DmFont = +{ + .first = ' ', + .last = '~', + .ascii = true, + .fontMap = (uint8_t*)fontMap5x8 +}; + + +/******************************************************************************* +* Function Name: GetDataRegPtr +****************************************************************************//** +* +* Returns a pointer to the data frame register for a specified pixel. +* Used by \ref Cy_SegLCD_WritePixel and \ref Cy_SegLCD_ReadPixel functions. +* +* \param base The base pointer to the LCD instance registers. +* \param pixel The predefined packed number that points to the pixel location +* in the frame buffer. +* +*******************************************************************************/ +static volatile uint32_t * GetDataRegPtr(LCD_Type * base, uint32_t pixel) +{ + volatile uint32_t * locDataPtr[] = {LCD_DATA0(base), LCD_DATA1(base), LCD_DATA2(base), LCD_DATA3(base)}; + + return (&(locDataPtr[CY_SEGLCD_EXTR_COM(pixel) / CY_SEGLCD_NIBBLE][CY_SEGLCD_EXTR_OCT(pixel)])); +} + + +/******************************************************************************* +* Function Name: InvClrData +****************************************************************************//** +* +* Inverts or clears the Frame Data buffer. +* Used by \ref Cy_SegLCD_Deinit, +* \ref Cy_SegLCD_ClrFrame and +* \ref Cy_SegLCD_InvFrame functions. +* +* \param base The base pointer to the LCD instance registers. +* \param inv: +* - true - inverts the data buffer, +* - false - clears the data buffer. +* +*******************************************************************************/ +static void InvClrData(LCD_Type * base, bool inv) +{ + uint32_t i; + + for (i = 0UL; i < LCD_OCTET_NUM; i++) + { + LCD_DATA0(base)[i] = (inv) ? (~LCD_DATA0(base)[i]) : 0UL; + + if (0UL != LCD_OCTET_NUM_8) + { + LCD_DATA1(base)[i] = (inv) ? (~LCD_DATA1(base)[i]) : 0UL; + + if (0UL != LCD_OCTET_NUM_16) + { + LCD_DATA2(base)[i] = (inv) ? (~LCD_DATA2(base)[i]) : 0UL; + LCD_DATA3(base)[i] = (inv) ? (~LCD_DATA3(base)[i]) : 0UL; + } + } + } +} + + +/******************************************************************************* +* Function Name: NumToChar +****************************************************************************//** +* +* Converts an one-digit hexadecimal numbers 0x0...0xF +* into the ASCII character codes. +* Used by the \ref Cy_SegLCD_WriteNumber function. +* +* \param value The value to be converted. +* \return The ASCII code of the 'value' character. +* +*******************************************************************************/ +static char_t NumToChar(uint32_t value) +{ + char_t character; + + if (value < 10UL) /* For dec numbers 0...9 */ + { + character = (char_t)((uint32_t)'0' + value); + } + else if (value < 0x10UL) /* For hex numbers A...F */ + { + character = (char_t)(((uint32_t)'A' - 0xAUL) + value); + } + else + { + character = ' '; /* The blank/space character */ + } + + return (character); +} + + +/******************************************************************************* +* Function Name: Cy_SegLCD_Init +****************************************************************************//** +* +* Initializes/restores the default Segment LCD block configuration. +* +* \param base The base pointer to the LCD instance registers. +* \param config The pointer to a configuration structure. +* \return \ref cy_en_seglcd_status_t. +* +* Side Effects: The block is disabled to change the settings. +* +* \funcusage +* \snippet seglcd/snippet/SegLCD_Snpt.c snippet_Cy_SegLCD_Config +* \snippet seglcd/snippet/SegLCD_Snpt.c snippet_Cy_SegLCD_Init +* +*******************************************************************************/ +cy_en_seglcd_status_t Cy_SegLCD_Init(LCD_Type * base, cy_stc_seglcd_config_t const * config) +{ + cy_en_seglcd_status_t retVal = CY_SEGLCD_BAD_PARAM; + + if (NULL != base) + { + CY_ASSERT_L3(CY_SEGLCD_IS_SPEED_VALID(config->speed)); + CY_ASSERT_L3(CY_SEGLCD_IS_WAVE_VALID (config->wave)); + CY_ASSERT_L3(CY_SEGLCD_IS_DRIVE_VALID(config->drive)); + CY_ASSERT_L3(CY_SEGLCD_IS_BIAS_VALID (base, config->bias, config->speed)); + CY_ASSERT_L2(CY_SEGLCD_IS_LSCLK_VALID (config->lsClk)); + CY_ASSERT_L1(CY_SEGLCD_IS_COM_NUM_VALID(config->comNum)); + CY_ASSERT_L2(CY_SEGLCD_IS_RATE_VALID (config->frRate)); + CY_ASSERT_L2(CY_SEGLCD_IS_CNTR_VALID (config->contrast)); + CY_ASSERT_L2(CY_SEGLCD_IS_FREQ_VALID (config->clkFreq)); + + uint32_t locCheck = ((CY_SEGLCD_SPEED_LOW == config->speed) && (CY_SEGLCD_REV_1(base))) ? (CY_SEGLCD_DIV_MAX_LS_VER1) : (CY_SEGLCD_DIV_MAX); + uint32_t locSubfr = CY_SYSLIB_DIV_ROUND((CY_SYSLIB_DIV_ROUND(config->clkFreq, config->frRate * 4UL * config->comNum) - 1UL) * config->contrast, 100UL); + uint32_t locDead = CY_SYSLIB_DIV_ROUND(CY_SYSLIB_DIV_ROUND(config->clkFreq * ((uint32_t)(100UL - (uint32_t)config->contrast)), (uint32_t)config->frRate), 100UL); + + if ((locSubfr <= locCheck) && (locDead <= locCheck)) + { + uint32_t locLsClk = (uint32_t)((CY_SEGLCD_REV_1(base)) ? CY_SEGLCD_LSCLK_LF : config->lsClk); + + Cy_SegLCD_Disable(base); + + /* Calculate the sub-frame and dead-time dividers */ + LCD_DIVIDER(base) = _VAL2FLD(LCD_DIVIDER_SUBFR_DIV, locSubfr) | + _VAL2FLD(LCD_DIVIDER_DEAD_DIV, locDead); + + /* Set the rest of settings */ + LCD_CONTROL(base) = _VAL2FLD(LCD_CONTROL_LCD_MODE, config->speed) | + _VAL2FLD(LCD_CONTROL_TYPE, config->wave) | + _VAL2FLD(LCD_CONTROL_OP_MODE, config->drive) | + _VAL2FLD(LCD_CONTROL_BIAS, config->bias) | + _VAL2FLD(LCD_V2_CONTROL_CLOCK_LS_SEL, locLsClk) | + /* Convert the comNum from the user range (2-16) into the machine range (0-14). */ + _VAL2FLD(LCD_CONTROL_COM_NUM, config->comNum - 2UL); + + retVal = CY_SEGLCD_SUCCESS; + } + } + + return (retVal); +} + + +/******************************************************************************* +* Function Name: Cy_SegLCD_Contrast +****************************************************************************//** +* +* Sets a specified contrast. +* +* \param base The base pointer to the LCD instance registers. +* \param contrast The contrast value to be set. +* \param config The pointer to a configuration structure. +* \return \ref cy_en_seglcd_status_t. +* +* Side Effects: The configuration structure contrast value is also updated. +* +* \funcusage +* \snippet seglcd/snippet/SegLCD_Snpt.c snippet_Cy_SegLCD_ContrastInit +* \snippet seglcd/snippet/SegLCD_Snpt.c snippet_Cy_SegLCD_Contrast +* +*******************************************************************************/ +cy_en_seglcd_status_t Cy_SegLCD_Contrast(LCD_Type * base, uint32_t contrast, cy_stc_seglcd_config_t * config) +{ + cy_en_seglcd_status_t retVal = CY_SEGLCD_BAD_PARAM; + + if (CY_SEGLCD_IS_CNTR_VALID (contrast)) + { + bool enabled = CY_SEGLCD_IS_ENABLED(base); /* Store the block state */ + + config->contrast = (uint8_t)contrast; + + retVal = Cy_SegLCD_Init(base, config); + + if ((CY_SEGLCD_SUCCESS == retVal) && enabled) + { + Cy_SegLCD_Enable(base); /* Restore the block state */ + } + } + + return (retVal); +} + + +/******************************************************************************* +* Function Name: Cy_SegLCD_Deinit +****************************************************************************//** +* +* De-initializes the LCD block (resets the block registers to default state). +* +* \param base The base pointer to the LCD instance registers. +* +* \funcusage +* \snippet seglcd/snippet/SegLCD_Snpt.c snippet_Cy_SegLCD_Deinit +* +*******************************************************************************/ +void Cy_SegLCD_Deinit(LCD_Type * base) +{ + Cy_SegLCD_Disable(base); + + LCD_CONTROL(base) = 0UL; + LCD_DIVIDER(base) = 0UL; + + InvClrData(base, false); /* Clear the entire frame buffer to all zeroes */ +} + + +/******************************************************************************* +* Function Name: Cy_SegLCD_Enable +****************************************************************************//** +* +* Enables the Segment LCD block. +* +* \param base The base pointer to the LCD instance registers. +* +* \funcusage +* \snippet seglcd/snippet/SegLCD_Snpt.c snippet_Cy_SegLCD_Config +* \snippet seglcd/snippet/SegLCD_Snpt.c snippet_Cy_SegLCD_Init +* +*******************************************************************************/ +void Cy_SegLCD_Enable(LCD_Type * base) +{ + if (_FLD2BOOL(LCD_CONTROL_LCD_MODE, LCD_CONTROL(base))) + { + LCD_CONTROL(base) |= LCD_CONTROL_HS_EN_Msk; + } + else /* CY_SEGLCD_SPEED_HIGH */ + { + uint32_t timeout; + + LCD_CONTROL(base) |= LCD_CONTROL_LS_EN_Msk; + + for (timeout = CY_SEGLCD_TIMEOUT; (_FLD2BOOL(LCD_CONTROL_LS_EN_STAT, LCD_CONTROL(base))) && (0UL != timeout); timeout--) + { + /* Waiting for enabling takes effect in the ILO clock domain. + * The timeout status does not affect anything, + * the timeout is to avoid a deadlock here. + */ + Cy_SysLib_DelayUs(1U); + } + } +} + + +/******************************************************************************* +* Function Name: Cy_SegLCD_Disable +****************************************************************************//** +* +* Disables the Segment LCD block. +* +* \param base The base pointer to the LCD instance registers. +* +* \funcusage +* \snippet seglcd/snippet/SegLCD_Snpt.c snippet_Cy_SegLCD_Disable +* +*******************************************************************************/ +void Cy_SegLCD_Disable(LCD_Type * base) +{ + if (_FLD2BOOL(LCD_CONTROL_LCD_MODE, LCD_CONTROL(base))) /* CY_SEGLCD_SPEED_HIGH */ + { + LCD_CONTROL(base) &= ~LCD_CONTROL_HS_EN_Msk; + } + else /* CY_SEGLCD_SPEED_LOW */ + { + if (_FLD2BOOL(LCD_CONTROL_LS_EN, LCD_CONTROL(base))) + { + uint32_t timeout; + + for (timeout = CY_SEGLCD_TIMEOUT; (!_FLD2BOOL(LCD_CONTROL_LS_EN_STAT, LCD_CONTROL(base))) && (0UL != timeout); timeout--) + { + Cy_SysLib_DelayUs(1U); /* Waiting for enabling takes effect in the ILO clock domain. */ + } + + LCD_CONTROL(base) &= ~LCD_CONTROL_LS_EN_Msk; + + for (timeout = CY_SEGLCD_TIMEOUT; (_FLD2BOOL(LCD_CONTROL_LS_EN_STAT, LCD_CONTROL(base))) && (0UL != timeout); timeout--) + { + Cy_SysLib_DelayUs(1U); /* Waiting for disabling takes effect in the ILO clock domain. */ + } + + /* The timeout status does not affect anything, the timeout is to avoid a deadlock */ + } + } +} + + +/******************************************************************************* +* Function Name: Cy_SegLCD_ClrFrame +****************************************************************************//** +* +* Clears the frame buffer and initiates the common lines. +* In general case it is recommended to be called after \ref Cy_SegLCD_Init +* and before \ref Cy_SegLCD_Enable. +* +* \param base The base pointer to the LCD instance registers. +* \param commons The pointer to array of common lines. +* The array size is specified by \ref cy_stc_seglcd_config_t.comNum. +* Each common line value should be made using +* \ref CY_SEGLCD_COMMON macro. +* +* \return \ref cy_en_seglcd_status_t. +* +* \funcusage +* \snippet seglcd/snippet/SegLCD_Snpt.c snippet_Cy_SegLCD_Config +* \snippet seglcd/snippet/SegLCD_Snpt.c snippet_Cy_SegLCD_Init +* +*******************************************************************************/ +cy_en_seglcd_status_t Cy_SegLCD_ClrFrame(LCD_Type * base, uint32_t const * commons) +{ + uint32_t retVal = (uint32_t)CY_SEGLCD_BAD_PARAM; + + if (NULL != commons) + { + uint32_t i; + + InvClrData(base, false); /* Clear the entire frame buffer to all zeroes */ + + retVal = (uint32_t)CY_SEGLCD_SUCCESS; + + /* Re-initialize the commons */ + for (i = 0UL; i < CY_SEGLCD_COM_NUM(base); i++) + { + retVal |= (uint32_t)Cy_SegLCD_WritePixel(base, commons[i], true); + } + } + + return((cy_en_seglcd_status_t)retVal); +} + + +/******************************************************************************* +* Function Name: Cy_SegLCD_InvFrame +****************************************************************************//** +* +* Inverts the frame buffer (all the connected pixel states are inverted). +* +* \param base The base pointer to the LCD instance registers. +* \param commons The pointer to an array of common lines. +* The array size is specified by \ref cy_stc_seglcd_config_t.comNum. +* Each common line value should be made using +* \ref CY_SEGLCD_COMMON macro. +* +* \return \ref cy_en_seglcd_status_t. +* +* \funcusage +* \snippet seglcd/snippet/SegLCD_Snpt.c snippet_Cy_SegLCD_InvFrame +* +*******************************************************************************/ +cy_en_seglcd_status_t Cy_SegLCD_InvFrame(LCD_Type * base, uint32_t const * commons) +{ + uint32_t retVal = (uint32_t)CY_SEGLCD_BAD_PARAM; + + if (NULL != commons) + { + uint32_t i; + + InvClrData(base, true); /* Invert the entire frame buffer. */ + + retVal = (uint32_t)CY_SEGLCD_SUCCESS; + + /* Re-initialize the common lines */ + for (i = 0UL; i < CY_SEGLCD_COM_NUM(base); i++) + { + uint32_t locCom = commons[i] & ~CY_SEGLCD_COM_Msk; + uint32_t j = 0UL; + + /* Clear common lines data after frame buffer inverting */ + for (j = 0UL; j < CY_SEGLCD_COM_NUM(base); j++) + { + retVal |= (uint32_t)Cy_SegLCD_WritePixel(base, locCom | ((uint32_t)(j << CY_SEGLCD_COM_Pos)), false); + } + + /* Set data for the common lines */ + retVal |= (uint32_t)Cy_SegLCD_WritePixel(base, commons[i], true); + } + } + + return((cy_en_seglcd_status_t)retVal); +} + + +/******************************************************************************* +* Function Name: Cy_SegLCD_WritePixel +****************************************************************************//** +* +* Sets or clears a specified pixel. +* +* \param base The base pointer to the LCD instance registers. +* \param pixel The predefined packed number that points to the pixel location +* in the frame buffer. +* \param value Specifies the pixel on/off state. +* \return \ref cy_en_seglcd_status_t. +* +* \funcusage +* \snippet seglcd/snippet/SegLCD_Snpt.h snippet_Cy_SegLCD_DefPixel +* \snippet seglcd/snippet/SegLCD_Snpt.c snippet_Cy_SegLCD_ActPixel +* +*******************************************************************************/ +cy_en_seglcd_status_t Cy_SegLCD_WritePixel(LCD_Type * base, uint32_t pixel, bool value) +{ + cy_en_seglcd_status_t retVal = CY_SEGLCD_BAD_PIXEL; + + if (CY_SEGLCD_IS_PIX_VALID(pixel)) + { + /* Extract the pixel location. */ + uint32_t loc_Pos = CY_SEGLCD_PIX_Pos(pixel); + uint32_t loc_Msk = CY_SEGLCD_PIX_Msk(pixel); + + /* Write a new pixel value into the frame buffer. */ + CY_REG32_CLR_SET(*GetDataRegPtr(base, pixel), loc, value ? 1UL : 0UL); + + retVal = CY_SEGLCD_SUCCESS; + } + + return(retVal); +} + + +/******************************************************************************* +* Function Name: Cy_SegLCD_ReadPixel +****************************************************************************//** +* +* Gets the state of a specified pixel. +* +* \param base The base pointer to the LCD instance registers. +* \param pixel The predefined packed number that points to the pixel location +* in the frame buffer. Each pixel value should be made using +* \ref CY_SEGLCD_PIXEL macro. +* \return Boolean pixel state. +* If pixel value is invalid - the 'false' is returned. +* +* \funcusage +* \snippet seglcd/snippet/SegLCD_Snpt.h snippet_Cy_SegLCD_DefPixel +* \snippet seglcd/snippet/SegLCD_Snpt.c snippet_Cy_SegLCD_ActPixel +* +*******************************************************************************/ +bool Cy_SegLCD_ReadPixel(LCD_Type * base, uint32_t pixel) +{ + bool retVal = false; + + if (CY_SEGLCD_IS_PIX_VALID(pixel)) + { + /* Get the pixel value from the frame buffer */ + retVal = (0UL != (*GetDataRegPtr(base, pixel) & CY_SEGLCD_PIX_Msk(pixel))); + } + else + { + CY_ASSERT_L1(false); + } + + return (retVal); +} + + +/******************************************************************************* +* Function Name: Cy_SegLCD_WriteChar +****************************************************************************//** +* +* Writes a specified character onto a specified display. +* Supports all display types except \ref CY_SEGLCD_BAR. +* +* \param base The base pointer to the LCD instance registers. +* \param character The code of the character to display. +* Should be within the font symbol codes range specified by +* \ref cy_stc_seglcd_font_t.first and \ref cy_stc_seglcd_font_t.last +* \param position The position of the character/digit on display. +* Zero is the most left character/digit of the specified +* display \ref cy_stc_seglcd_disp_t. +* \param display The pointer to the display structure \ref cy_stc_seglcd_disp_t. +* \return \ref cy_en_seglcd_status_t. +* +* \funcusage +* \snippet seglcd/snippet/SegLCD_Snpt.c snippet_Cy_SegLCD_Char +* +*******************************************************************************/ +cy_en_seglcd_status_t Cy_SegLCD_WriteChar(LCD_Type * base, + char_t character, + uint32_t position, + cy_stc_seglcd_disp_t const * display) +{ + uint32_t retVal = (uint32_t)CY_SEGLCD_BAD_PARAM; + + if (CY_SEGLCD_IS_SYMBOLIC(display, position)) /* If the display is symbolic/numeric */ + { + uint32_t i; + retVal = CY_SEGLCD_IS_BASIC(display->type) ? (uint32_t)CY_SEGLCD_SUCCESS : (uint32_t)CY_SEGLCD_CUSTOM; + + if ((character < display->font->first) || (character > display->font->last)) /* if out of the font range */ + { + retVal |= (uint32_t)CY_SEGLCD_BAD_CHAR; + character = CY_SEGLCD_SPACE(display); /* The blank (space) character */ + } + + character = (char_t)(character - display->font->first); /* Shift to the font char map starting index */ + + for (i = 0UL; i < (uint32_t)display->type; i++) + { + uint32_t locPix = *(display->pixMap + (position * (uint32_t)display->type) + i); /* Current display pixel */ + uint32_t locIdx = _FLD2VAL(CY_SEGLCD_SYM_BYTE_IDX, i) + ((uint32_t)character * CY_SYSLIB_DIV_ROUNDUP((uint32_t)display->type, CY_SEGLCD_OCTET)); /* current symbol byte index */ + bool locVal = 0U != (display->font->fontMap[locIdx] & (uint8_t)(1U << _FLD2VAL(CY_SEGLCD_SYM_BIT_IDX, i))); /* current pixel value */ + + retVal |= (uint32_t)Cy_SegLCD_WritePixel(base, locPix, display->invert != locVal); + } + } + + return((cy_en_seglcd_status_t)retVal); +} + + +/******************************************************************************* +* Function Name: Cy_SegLCD_WriteNumber +****************************************************************************//** +* +* Displays an integer value onto a specified display. +* Supports all display types except \ref CY_SEGLCD_BAR. +* +* \note The sign conversion, sign display, decimal points, and other special segments +* outside the display symbols themselves should be handled on upper layer code. +* +* \param base The base pointer to the LCD instance registers. +* \param value The unsigned integer number to be displayed. +* \param position The position of the least significant digit of the number +* as counted left to right starting at 0 - the first symbol on the left +* of the specified display. +* If the specified display contains fewer symbols than the number +* requires to be displayed, the extra (more significant) digit(s) is(are) not +* displayed and the \ref CY_SEGLCD_EXCEED value is returned. +* \param display The pointer to the display structure \ref cy_stc_seglcd_disp_t. +* \param zeroes: +* - true - all the unused digits on the left of the displayed value are zeroes. +* - false - all the above mentioned digits are blank. +* \param hex: +* - true - the value is displayed in the hexadecimal format. +* - false - the value is displayed in the decimal format. +* \return \ref cy_en_seglcd_status_t. +* +* \funcusage +* \snippet seglcd/snippet/SegLCD_Snpt.c snippet_Cy_SegLCD_DecNum +* \snippet seglcd/snippet/SegLCD_Snpt.c snippet_Cy_SegLCD_HexNum +* +*******************************************************************************/ +cy_en_seglcd_status_t Cy_SegLCD_WriteNumber(LCD_Type * base, + uint32_t value, + uint32_t position, + cy_stc_seglcd_disp_t const * display, + bool zeroes, + bool hex) +{ + uint32_t retVal = (uint32_t)CY_SEGLCD_BAD_PARAM; + + if (CY_SEGLCD_IS_SYMBOLIC(display, position)) /* If the display is symbolic/numeric */ + { + uint32_t locNum; + uint32_t i = position + 1UL; + uint32_t locDiv = (hex) ? 0x10UL : 10UL; /* The digit weight for hex/dec counting systems */ + retVal = (uint32_t)CY_SEGLCD_SUCCESS; + + do + { + i--; + + if ((0UL == value) && (i != position) && (!zeroes)) + { + /* For 'not zeroes' mode each extra digit is cleared. */ + locNum = (uint32_t)CY_SEGLCD_NUM_BLANK; + } + else + { + /* Display the subsequent digit or '0' for 'zeroes' mode */ + locNum = value % locDiv; + } + + /* Calculate the next digit value */ + value = value / locDiv; + + retVal |= (uint32_t)Cy_SegLCD_WriteChar(base, (display->font->ascii) ? NumToChar(locNum) : (char_t)locNum, i, display); + } + while (i != 0UL); /* While the current digit position is in the range of the display, keep processing the output */ + + if (0UL != value) + { + retVal |= (uint32_t)CY_SEGLCD_EXCEED; + } + } + + return((cy_en_seglcd_status_t)retVal); +} + + +/******************************************************************************* +* Function Name: Cy_SegLCD_WriteString +****************************************************************************//** +* +* Writes a specified zero-terminated char string onto a specified display. +* Supports all display types except \ref CY_SEGLCD_BAR. +* +* \param base The base pointer to the LCD instance registers. +* \param string The pointer to the ASCII-coded null-terminated character string. +* \param position The position of the first string character at the display +* as counted left to right starting at 0 - the first symbol on the left +* of the specified display. +* If the specified display contains fewer symbols than the string +* requires to be displayed, the extra character(s) is(are) not displayed +* and the \ref CY_SEGLCD_EXCEED value is returned. +* \param display The pointer to the display structure \ref cy_stc_seglcd_disp_t. +* \return \ref cy_en_seglcd_status_t. +* +* \funcusage +* \snippet seglcd/snippet/SegLCD_Snpt.c snippet_Cy_SegLCD_String +* +*******************************************************************************/ +cy_en_seglcd_status_t Cy_SegLCD_WriteString(LCD_Type * base, + char_t const * string, + uint32_t position, + cy_stc_seglcd_disp_t const * display) +{ + uint32_t retVal = (uint32_t)CY_SEGLCD_BAD_PARAM; + + if (CY_SEGLCD_IS_ASCII(display, position)) /* If the display is symbolic/numeric and the font is ASCII-coded */ + { + uint32_t i; + retVal = (uint32_t)CY_SEGLCD_SUCCESS; + + for (i = 0UL; (i + position) < display->symNum; i++) + { + retVal |= (uint32_t)Cy_SegLCD_WriteChar(base, ('\0' != string[i]) ? string[i] : CY_SEGLCD_SPACE(display), i + position, display); + } + + if ('\0' != string[i]) + { + retVal |= (uint32_t)CY_SEGLCD_EXCEED; + } + } + + return((cy_en_seglcd_status_t)retVal); +} + + +/******************************************************************************* +* Function Name: Cy_SegLCD_BarGraph +****************************************************************************//** +* +* Draws a bar onto a specified bar graph / dial display. +* Only the \ref CY_SEGLCD_BAR display type is supported. +* +* \param base The base pointer to the LCD instance registers. +* \param value The length of the bar in pixels. +* \param position The position of the first bar pixel as counted from the +* beginning ('0' is the first pixel) of the specified display. +* If the specified display contains fewer pixels than the bar +* requires to be displayed, the extra pixel(s) is(are) not +* displayed and the \ref CY_SEGLCD_EXCEED value is returned. +* \param display The pointer to the display structure \ref cy_stc_seglcd_disp_t. +* \return \ref cy_en_seglcd_status_t. +* +* \funcusage +* \snippet seglcd/snippet/SegLCD_Snpt.h snippet_Cy_SegLCD_BarLength +* \snippet seglcd/snippet/SegLCD_Snpt.c snippet_Cy_SegLCD_BarGraphDisplay +* \snippet seglcd/snippet/SegLCD_Snpt.c snippet_Cy_SegLCD_BarGraphValue +* \snippet seglcd/snippet/SegLCD_Snpt.c snippet_Cy_SegLCD_BarGraph +* +*******************************************************************************/ +cy_en_seglcd_status_t Cy_SegLCD_BarGraph(LCD_Type * base, + uint32_t value, + uint32_t position, + cy_stc_seglcd_disp_t const * display) +{ + uint32_t retVal = (uint32_t)CY_SEGLCD_BAD_PARAM; + + if (CY_SEGLCD_IS_BARGRAPH(display, position)) /* If the display is bar graph / dial */ + { + uint32_t i; + retVal = (uint32_t)CY_SEGLCD_SUCCESS; + + for (i = position; i < display->symNum; i++) + { + retVal |= (uint32_t)Cy_SegLCD_WritePixel(base, *(display->pixMap + i), i < (position + value)); + } + + if (((uint32_t)CY_SEGLCD_BAD_PIXEL != retVal) && ((position + value) > display->symNum)) + { + retVal |= (uint32_t)CY_SEGLCD_EXCEED; + } + } + + return((cy_en_seglcd_status_t)retVal); +} + + +#endif /* CY_IP_MXLCD */ + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_smartio.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_smartio.c index 2cebdda5a3..9b9f120e12 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_smartio.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_smartio.c @@ -45,7 +45,7 @@ extern "C" { * Status of the initialization operation * * \funcusage -* \snippet smartio/1.0/snippet/main.c snippet_Cy_SmartIO_Init +* \snippet smartio/snippet/main.c snippet_Cy_SmartIO_Init * *******************************************************************************/ cy_en_smartio_status_t Cy_SmartIO_Init(SMARTIO_PRT_Type* base, const cy_stc_smartio_config_t* config) @@ -160,7 +160,7 @@ cy_en_smartio_status_t Cy_SmartIO_Init(SMARTIO_PRT_Type* base, const cy_stc_smar * Pointer to the Smart I/O base address * * \funcusage -* \snippet smartio/1.0/snippet/main.c snippet_Cy_SmartIO_Deinit +* \snippet smartio/snippet/main.c snippet_Cy_SmartIO_Deinit * *******************************************************************************/ void Cy_SmartIO_Deinit(SMARTIO_PRT_Type* base) @@ -191,7 +191,7 @@ void Cy_SmartIO_Deinit(SMARTIO_PRT_Type* base) * Pointer to the Smart I/O base address * * \funcusage -* \snippet smartio/1.0/snippet/main.c snippet_Cy_SmartIO_Enable +* \snippet smartio/snippet/main.c snippet_Cy_SmartIO_Enable * *******************************************************************************/ void Cy_SmartIO_Enable(SMARTIO_PRT_Type* base) @@ -215,7 +215,7 @@ void Cy_SmartIO_Enable(SMARTIO_PRT_Type* base) * Pointer to the Smart I/O base address * * \funcusage -* \snippet smartio/1.0/snippet/main.c snippet_Cy_SmartIO_Disable +* \snippet smartio/snippet/main.c snippet_Cy_SmartIO_Disable * *******************************************************************************/ void Cy_SmartIO_Disable(SMARTIO_PRT_Type* base) @@ -259,7 +259,7 @@ void Cy_SmartIO_Disable(SMARTIO_PRT_Type* base) * \note The Smart I/O block must be disabled before calling this function. * * \funcusage -* \snippet smartio/1.0/snippet/main.c snippet_Cy_SmartIO_SetChBypass +* \snippet smartio/snippet/main.c snippet_Cy_SmartIO_SetChBypass * *******************************************************************************/ cy_en_smartio_status_t Cy_SmartIO_SetChBypass(SMARTIO_PRT_Type* base, uint8_t bypassMask) @@ -296,7 +296,7 @@ cy_en_smartio_status_t Cy_SmartIO_SetChBypass(SMARTIO_PRT_Type* base, uint8_t by * \note The Smart I/O block must be disabled before calling this function. * * \funcusage -* \snippet smartio/1.0/snippet/main.c snippet_Cy_SmartIO_SetClock +* \snippet smartio/snippet/main.c snippet_Cy_SmartIO_SetClock * *******************************************************************************/ cy_en_smartio_status_t Cy_SmartIO_SetClock(SMARTIO_PRT_Type* base, cy_en_smartio_clksrc_t clkSrc) @@ -345,7 +345,7 @@ cy_en_smartio_status_t Cy_SmartIO_SetClock(SMARTIO_PRT_Type* base, cy_en_smartio * \note The Smart I/O block must be disabled before calling this function. * * \funcusage -* \snippet smartio/1.0/snippet/main.c snippet_Cy_SmartIO_SetIoSync +* \snippet smartio/snippet/main.c snippet_Cy_SmartIO_SetIoSync * *******************************************************************************/ cy_en_smartio_status_t Cy_SmartIO_SetIoSync(SMARTIO_PRT_Type* base, uint8_t ioSyncEn) @@ -394,7 +394,7 @@ cy_en_smartio_status_t Cy_SmartIO_SetIoSync(SMARTIO_PRT_Type* base, uint8_t ioSy * \note The Smart I/O block must be disabled before calling this function. * * \funcusage -* \snippet smartio/1.0/snippet/main.c snippet_Cy_SmartIO_SetChipSync +* \snippet smartio/snippet/main.c snippet_Cy_SmartIO_SetChipSync * *******************************************************************************/ cy_en_smartio_status_t Cy_SmartIO_SetChipSync(SMARTIO_PRT_Type* base, uint8_t chipSyncEn) @@ -438,7 +438,7 @@ cy_en_smartio_status_t Cy_SmartIO_SetChipSync(SMARTIO_PRT_Type* base, uint8_t ch * \note The Smart I/O block must be disabled before calling this function. * * \funcusage -* \snippet smartio/1.0/snippet/main.c snippet_Cy_SmartIO_HoldOverride +* \snippet smartio/snippet/main.c snippet_Cy_SmartIO_HoldOverride * *******************************************************************************/ cy_en_smartio_status_t Cy_SmartIO_HoldOverride(SMARTIO_PRT_Type* base, bool hldOvr) @@ -476,7 +476,7 @@ cy_en_smartio_status_t Cy_SmartIO_HoldOverride(SMARTIO_PRT_Type* base, bool hldO * LUT input trigger source * * \funcusage -* \snippet smartio/1.0/snippet/main.c snippet_Cy_SmartIO_GetLutTr +* \snippet smartio/snippet/main.c snippet_Cy_SmartIO_GetLutTr * *******************************************************************************/ cy_en_smartio_luttr_t Cy_SmartIO_GetLutTr(SMARTIO_PRT_Type* base, cy_en_smartio_lutnum_t lutNum, cy_en_smartio_trnum_t trNum) @@ -535,7 +535,7 @@ cy_en_smartio_luttr_t Cy_SmartIO_GetLutTr(SMARTIO_PRT_Type* base, cy_en_smartio_ * \note The Smart I/O block must be disabled before calling this function. * * \funcusage -* \snippet smartio/1.0/snippet/main.c snippet_Cy_SmartIO_SetLutTr +* \snippet smartio/snippet/main.c snippet_Cy_SmartIO_SetLutTr * *******************************************************************************/ cy_en_smartio_status_t Cy_SmartIO_SetLutTr(SMARTIO_PRT_Type* base, cy_en_smartio_lutnum_t lutNum, cy_en_smartio_trnum_t trNum, cy_en_smartio_luttr_t trSrc) @@ -599,7 +599,7 @@ cy_en_smartio_status_t Cy_SmartIO_SetLutTr(SMARTIO_PRT_Type* base, cy_en_smartio * \note The Smart I/O block must be disabled before calling this function. * * \funcusage -* \snippet smartio/1.0/snippet/main.c snippet_Cy_SmartIO_SetLutTrAll +* \snippet smartio/snippet/main.c snippet_Cy_SmartIO_SetLutTrAll * *******************************************************************************/ cy_en_smartio_status_t Cy_SmartIO_SetLutTrAll(SMARTIO_PRT_Type* base, cy_en_smartio_lutnum_t lutNum, cy_en_smartio_luttr_t trSrc) @@ -645,7 +645,7 @@ cy_en_smartio_status_t Cy_SmartIO_SetLutTrAll(SMARTIO_PRT_Type* base, cy_en_smar * \note The Smart I/O block must be disabled before calling this function. * * \funcusage -* \snippet smartio/1.0/snippet/main.c snippet_Cy_SmartIO_SetLutOpcode +* \snippet smartio/snippet/main.c snippet_Cy_SmartIO_SetLutOpcode * *******************************************************************************/ cy_en_smartio_status_t Cy_SmartIO_SetLutOpcode(SMARTIO_PRT_Type* base, cy_en_smartio_lutnum_t lutNum, cy_en_smartio_lutopc_t opcode) @@ -697,7 +697,7 @@ cy_en_smartio_status_t Cy_SmartIO_SetLutOpcode(SMARTIO_PRT_Type* base, cy_en_sma * \note The Smart I/O block must be disabled before calling this function. * * \funcusage -* \snippet smartio/1.0/snippet/main.c snippet_Cy_SmartIO_SetLutMap +* \snippet smartio/snippet/main.c snippet_Cy_SmartIO_SetLutMap * *******************************************************************************/ cy_en_smartio_status_t Cy_SmartIO_SetLutMap(SMARTIO_PRT_Type* base, cy_en_smartio_lutnum_t lutNum, uint8_t lutMap) @@ -732,7 +732,7 @@ cy_en_smartio_status_t Cy_SmartIO_SetLutMap(SMARTIO_PRT_Type* base, cy_en_smarti * Data unit input trigger source * * \funcusage -* \snippet smartio/1.0/snippet/main.c snippet_Cy_SmartIO_GetDuTr +* \snippet smartio/snippet/main.c snippet_Cy_SmartIO_GetDuTr * *******************************************************************************/ cy_en_smartio_dutr_t Cy_SmartIO_GetDuTr(SMARTIO_PRT_Type* base, cy_en_smartio_trnum_t trNum) @@ -788,7 +788,7 @@ cy_en_smartio_dutr_t Cy_SmartIO_GetDuTr(SMARTIO_PRT_Type* base, cy_en_smartio_tr * \note The Smart I/O block must be disabled before calling this function. * * \funcusage -* \snippet smartio/1.0/snippet/main.c snippet_Cy_SmartIO_SetDuTr +* \snippet smartio/snippet/main.c snippet_Cy_SmartIO_SetDuTr * *******************************************************************************/ cy_en_smartio_status_t Cy_SmartIO_SetDuTr(SMARTIO_PRT_Type* base, cy_en_smartio_trnum_t trNum, cy_en_smartio_dutr_t trSrc) @@ -849,7 +849,7 @@ cy_en_smartio_status_t Cy_SmartIO_SetDuTr(SMARTIO_PRT_Type* base, cy_en_smartio_ * \note The Smart I/O block must be disabled before calling this function. * * \funcusage -* \snippet smartio/1.0/snippet/main.c snippet_Cy_SmartIO_SetDuTrAll +* \snippet smartio/snippet/main.c snippet_Cy_SmartIO_SetDuTrAll * *******************************************************************************/ cy_en_smartio_status_t Cy_SmartIO_SetDuTrAll(SMARTIO_PRT_Type* base, cy_en_smartio_dutr_t trSrc) @@ -895,7 +895,7 @@ cy_en_smartio_status_t Cy_SmartIO_SetDuTrAll(SMARTIO_PRT_Type* base, cy_en_smart * \note The Smart I/O block must be disabled before calling this function. * * \funcusage -* \snippet smartio/1.0/snippet/main.c snippet_Cy_SmartIO_SetDuData +* \snippet smartio/snippet/main.c snippet_Cy_SmartIO_SetDuData * *******************************************************************************/ cy_en_smartio_status_t Cy_SmartIO_SetDuData(SMARTIO_PRT_Type* base, cy_en_smartio_datanum_t dataNum, cy_en_smartio_dudata_t dataSrc) @@ -943,7 +943,7 @@ cy_en_smartio_status_t Cy_SmartIO_SetDuData(SMARTIO_PRT_Type* base, cy_en_smarti * \note The Smart I/O block must be disabled before calling this function. * * \funcusage -* \snippet smartio/1.0/snippet/main.c snippet_Cy_SmartIO_SetDuOperation +* \snippet smartio/snippet/main.c snippet_Cy_SmartIO_SetDuOperation * *******************************************************************************/ cy_en_smartio_status_t Cy_SmartIO_SetDuOperation(SMARTIO_PRT_Type* base, cy_en_smartio_duopc_t opcode, cy_en_smartio_dusize_t size) @@ -979,7 +979,7 @@ cy_en_smartio_status_t Cy_SmartIO_SetDuOperation(SMARTIO_PRT_Type* base, cy_en_s * \note The Smart I/O block must be disabled before calling this function. * * \funcusage -* \snippet smartio/1.0/snippet/main.c snippet_Cy_SmartIO_SetDataReg +* \snippet smartio/snippet/main.c snippet_Cy_SmartIO_SetDataReg * *******************************************************************************/ cy_en_smartio_status_t Cy_SmartIO_SetDataReg(SMARTIO_PRT_Type* base, uint8_t dataReg) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_smif.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_smif.c index 166279a60f..6a74258384 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_smif.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_smif.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_smif.c -* \version 1.20.1 +* \version 1.30 * * \brief * This file provides the source code for the SMIF driver APIs. @@ -53,13 +53,12 @@ extern "C" { * \param config * Passes a configuration structure that configures the SMIF block for operation. * -* \param context -* Passes a configuration structure that contains the transfer parameters of the -* SMIF block. -* * \param timeout * A timeout in microseconds for blocking APIs in use. * +* \param context +* Passes a configuration structure that contains the transfer parameters of the +* SMIF block. * * \note Make sure that the interrupts are initialized and disabled. * @@ -381,10 +380,6 @@ cy_en_smif_status_t Cy_SMIF_TransmitCommand(SMIF_Type *base, * \param base * Holds the base address of the SMIF block registers. * -* \param context -* Passes a configuration structure that contains the transfer parameters of the -* SMIF block. -* * \param txBuffer * The pointer to the data to be transferred. If this pointer is a NULL, then the * function does not enable the interrupt. This use case is typically used when @@ -407,10 +402,13 @@ cy_en_smif_status_t Cy_SMIF_TransmitCommand(SMIF_Type *base, * The callback executed at the end of a transmission. NULL interpreted as no * callback. * +* \param context +* Passes a configuration structure that contains the transfer parameters of the +* SMIF block. +* * \return A status of a transmission. * - \ref CY_SMIF_SUCCESS * - \ref CY_SMIF_CMD_FIFO_FULL -* - \ref CY_SMIF_BAD_PARAM * *******************************************************************************/ cy_en_smif_status_t Cy_SMIF_TransmitData(SMIF_Type *base, @@ -421,38 +419,36 @@ cy_en_smif_status_t Cy_SMIF_TransmitData(SMIF_Type *base, cy_stc_smif_context_t *context) { /* The return variable */ - cy_en_smif_status_t result = CY_SMIF_BAD_PARAM; + cy_en_smif_status_t result = CY_SMIF_CMD_FIFO_FULL; /* Check input values */ CY_ASSERT_L3(CY_SMIF_TXFR_WIDTH_VALID(transferWidth)); + CY_ASSERT_L2(CY_SMIF_BUF_SIZE_VALID(size)); - if(size > 0U) + /* Check if there are enough free entries in TX_CMD_FIFO */ + if (Cy_SMIF_GetCmdFifoStatus(base) < CY_SMIF_TX_CMD_FIFO_STATUS_RANGE) { - result = CY_SMIF_CMD_FIFO_FULL; - /* Check if there are enough free entries in TX_CMD_FIFO */ - if (Cy_SMIF_GetCmdFifoStatus(base) < CY_SMIF_TX_CMD_FIFO_STATUS_RANGE) + /* Enter the transmitting mode */ + SMIF_TX_CMD_FIFO_WR(base) = + _VAL2FLD(CY_SMIF_CMD_FIFO_WR_MODE, CY_SMIF_CMD_FIFO_TX_COUNT_MODE) | + _VAL2FLD(CY_SMIF_CMD_FIFO_WR_WIDTH, (uint32_t)transferWidth) | + _VAL2FLD(CY_SMIF_CMD_FIFO_WR_TX_COUNT, (size - 1UL)); + + if (NULL != txBuffer) { - /* Enter the transmitting mode */ - SMIF_TX_CMD_FIFO_WR(base) = - _VAL2FLD(CY_SMIF_CMD_FIFO_WR_MODE, CY_SMIF_CMD_FIFO_TX_COUNT_MODE) | - _VAL2FLD(CY_SMIF_CMD_FIFO_WR_WIDTH, (uint32_t)transferWidth) | - _VAL2FLD(CY_SMIF_CMD_FIFO_WR_TX_COUNT, ((uint32_t)(size - 1U))); + /* Move the parameters to the global variables */ + context->txBufferAddress = (uint8_t*)txBuffer; + context->txBufferSize = size; + context->txBufferCounter = size; + context->txCmpltCb = TxCmpltCb; + context->transferStatus = (uint32_t) CY_SMIF_SEND_BUSY; - if (NULL != txBuffer) - { - /* Move the parameters to the global variables */ - context->txBufferAddress = (uint8_t*)txBuffer; - context->txBufferSize = size; - context->txBufferCounter = size; - context->txCmpltCb = TxCmpltCb; - context->transferStatus = (uint32_t) CY_SMIF_SEND_BUSY; - - /* Enable the TR_TX_REQ interrupt */ - Cy_SMIF_SetInterruptMask(base, - Cy_SMIF_GetInterruptMask(base) | SMIF_INTR_TR_TX_REQ_Msk); - } - result = CY_SMIF_SUCCESS; + /* Enable the TR_TX_REQ interrupt */ + Cy_SMIF_SetInterruptMask(base, + Cy_SMIF_GetInterruptMask(base) | + SMIF_INTR_TR_TX_REQ_Msk); } + result = CY_SMIF_SUCCESS; } return (result); @@ -475,10 +471,6 @@ cy_en_smif_status_t Cy_SMIF_TransmitData(SMIF_Type *base, * \param base * Holds the base address of the SMIF block registers. * -* \param context -* Passes a configuration structure that contains the transfer parameters of the -* SMIF block. -* * \param txBuffer * The pointer to the data to be transferred. If this pointer is a NULL, then the * function does not fill TX_FIFO. The user would handle the FIFO management in a @@ -495,6 +487,10 @@ cy_en_smif_status_t Cy_SMIF_TransmitData(SMIF_Type *base, * \param transferWidth * The width of transfer \ref cy_en_smif_txfr_width_t. * +* \param context +* Passes a configuration structure that contains the transfer parameters of the +* SMIF block. +* * \return A status of a transmission. * - \ref CY_SMIF_SUCCESS * - \ref CY_SMIF_CMD_FIFO_FULL @@ -524,7 +520,7 @@ cy_en_smif_status_t Cy_SMIF_TransmitDataBlocking(SMIF_Type *base, SMIF_TX_CMD_FIFO_WR(base) = _VAL2FLD(CY_SMIF_CMD_FIFO_WR_MODE, CY_SMIF_CMD_FIFO_TX_COUNT_MODE) | _VAL2FLD(CY_SMIF_CMD_FIFO_WR_WIDTH, (uint32_t)transferWidth) | - _VAL2FLD(CY_SMIF_CMD_FIFO_WR_TX_COUNT, ((uint32_t)(size - 1U))); + _VAL2FLD(CY_SMIF_CMD_FIFO_WR_TX_COUNT, (size - 1UL)); result = CY_SMIF_SUCCESS; @@ -577,10 +573,6 @@ cy_en_smif_status_t Cy_SMIF_TransmitDataBlocking(SMIF_Type *base, * \param base * Holds the base address of the SMIF block registers. * -* \param context -* Passes a configuration structure that contains the transfer parameters of the -* SMIF block. -* * \param rxBuffer * The pointer to the variable where the receive data is stored. If this pointer * is a NULL, then the function does not enable the interrupt. This use case is @@ -603,6 +595,10 @@ cy_en_smif_status_t Cy_SMIF_TransmitDataBlocking(SMIF_Type *base, * The callback executed at the end of a reception. NULL interpreted as no * callback. * +* \param context +* Passes a configuration structure that contains the transfer parameters of the +* SMIF block. +* * \return A status of a reception. * - \ref CY_SMIF_SUCCESS * - \ref CY_SMIF_CMD_FIFO_FULL @@ -634,7 +630,7 @@ cy_en_smif_status_t Cy_SMIF_ReceiveData(SMIF_Type *base, SMIF_TX_CMD_FIFO_WR(base) = _VAL2FLD(CY_SMIF_CMD_FIFO_WR_MODE, CY_SMIF_CMD_FIFO_RX_COUNT_MODE) | _VAL2FLD(CY_SMIF_CMD_FIFO_WR_WIDTH, (uint32_t)transferWidth) | - _VAL2FLD(CY_SMIF_CMD_FIFO_WR_RX_COUNT, ((uint32_t)(size - 1U))); + _VAL2FLD(CY_SMIF_CMD_FIFO_WR_RX_COUNT, (size - 1UL)); if (NULL != rxBuffer) { @@ -674,10 +670,6 @@ cy_en_smif_status_t Cy_SMIF_ReceiveData(SMIF_Type *base, * \param base * Holds the base address of the SMIF block registers. * -* \param context -* Passes a configuration structure that contains the transfer parameters of the -* SMIF block. -* * \param rxBuffer * The pointer to the variable where the receive data is stored. If this pointer * is a NULL, then the function does not enable the interrupt. This use case is @@ -696,6 +688,10 @@ cy_en_smif_status_t Cy_SMIF_ReceiveData(SMIF_Type *base, * \param transferWidth * The width of transfer \ref cy_en_smif_txfr_width_t. * +* \param context +* Passes a configuration structure that contains the transfer parameters of the +* SMIF block. +* * \return A status of a reception. * - \ref CY_SMIF_SUCCESS * - \ref CY_SMIF_CMD_FIFO_FULL @@ -727,12 +723,11 @@ cy_en_smif_status_t Cy_SMIF_ReceiveDataBlocking(SMIF_Type *base, SMIF_TX_CMD_FIFO_WR(base) = _VAL2FLD(CY_SMIF_CMD_FIFO_WR_MODE, CY_SMIF_CMD_FIFO_RX_COUNT_MODE) | _VAL2FLD(CY_SMIF_CMD_FIFO_WR_WIDTH, (uint32_t)transferWidth) | - _VAL2FLD(CY_SMIF_CMD_FIFO_WR_RX_COUNT, ((uint32_t)(size - 1U))); + _VAL2FLD(CY_SMIF_CMD_FIFO_WR_RX_COUNT, (size - 1UL)); result = CY_SMIF_SUCCESS; if (NULL != rxBuffer) { - uint32_t timeoutUnits = context->timeout; cy_stc_smif_context_t contextLoc; @@ -791,7 +786,7 @@ cy_en_smif_status_t Cy_SMIF_SendDummyCycles(SMIF_Type *base, /* Send the dummy bytes */ SMIF_TX_CMD_FIFO_WR(base) = _VAL2FLD(CY_SMIF_CMD_FIFO_WR_MODE, CY_SMIF_CMD_FIFO_DUMMY_COUNT_MODE) | - _VAL2FLD(CY_SMIF_CMD_FIFO_WR_DUMMY, ((uint32_t)(cycles-1U))); + _VAL2FLD(CY_SMIF_CMD_FIFO_WR_DUMMY, (cycles-1UL)); result = CY_SMIF_SUCCESS; } @@ -892,10 +887,6 @@ void Cy_SMIF_Enable(SMIF_Type *base, cy_stc_smif_context_t *context) * \param base * Holds the base address of the SMIF block registers. * -* \param context -* Passes a configuration structure that contains the transfer parameters of the -* SMIF block. -* * \param address * The address that gets encrypted is a masked 16-byte block address. The 32-bit * address with the last 4 bits masked is placed as the last 4 bytes in the @@ -917,11 +908,18 @@ void Cy_SMIF_Enable(SMIF_Type *base, cy_stc_smif_context_t *context) * \param size * Provides a size of the array. * +* \param context +* Passes a configuration structure that contains the transfer parameters of the +* SMIF block. +* * \return A status of the command transmit. * - \ref CY_SMIF_SUCCESS * - \ref CY_SMIF_EXCEED_TIMEOUT * - \ref CY_SMIF_BAD_PARAM * +* \funcusage +* \snippet smif/snippet/main.c snippet_Cy_SMIF_Encrypt +* *******************************************************************************/ cy_en_smif_status_t Cy_SMIF_Encrypt(SMIF_Type *base, uint32_t address, diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_smif_memslot.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_smif_memslot.c index 11429209ac..0fe4cdc8de 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_smif_memslot.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_smif_memslot.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_smif_memslot.c -* \version 1.20.1 +* \version 1.30 * * \brief * This file provides the source code for the memory-level APIs of the SMIF driver. @@ -37,7 +37,48 @@ extern "C" { /*************************************** * Internal Constants ***************************************/ -#define READ_ENHANCED_MODE_DISABLED (0xFFU) + +#define READ_ENHANCED_MODE_DISABLED (0xFFU) +#define BITS_IN_BYTE (8U) +#define BYTES_IN_DWORD (4U) +#define BITS_IN_BYTE_ABOVE_4GB (3U) /** Density of memory above 4GBit stored as poser of 2 */ +#define PARAM_HEADERS_NUM (CY_SMIF_SFDP_BFPT_BYTE_06) +#define FIRST_HEADER_OFFSET (0x08U) /** The offset of the 1-st Parameter Header */ +#define PARAM_ID_MSB_REL_OFFSET (0x07U) /** The relative offset of Parameter ID MSB + * in the SFDP Header table + */ +#define PARAM_MINOR_REV_REL_OFFSET (0x01U) /** The relative offset of Parameter Minor Revision + * in the SFDP Header table + */ +#define PARAM_MAJOR_REV_REL_OFFSET (0x02U) /** The relative offset of Parameter Major Revision + * in the SFDP Header table + */ +#define PARAM_ID_MSB_OFFSET (0x08U) /** The offset of Parameter ID MSB */ +#define PARAM_ID_LSB_MASK (0xFFUL) /** The mask of Parameter ID LSB */ +#define PARAM_TABLE_PRT_OFFSET (0x04UL) /** The relative offset of Parameter Table Pointer Byte 1 */ +#define PARAM_TABLE_LENGTH_OFFSET (0X03U) /** The offset of Parameter Table Length in the Header Table */ +#define PARAM_HEADER_NUM (6U) /** The supported number of the parameter headers */ +#define HEADER_LENGTH (0x8U) /**< The length of the SFDP header */ +#define HEADERS_LENGTH (HEADER_LENGTH + \ + (CY_SMIF_SFDP_PARAM_HEADER_LENGTH * PARAM_HEADER_NUM)) +#define TYPE_STEP (2UL) /** The Erase Type step in the Basic Flash Parameter Table */ +#define INSTRUCTION_NOT_SUPPORTED (0XFFU) /** The code for the not supported instruction */ +#define BASIC_SPI_ID_LSB (0X00UL) /** The JEDEC SFDP Basic SPI Flash Parameter ID LSB */ +#define BASIC_SPI_ID_MSB (0XFFUL) /** The JEDEC SFDP Basic SPI Flash Parameter ID MSB */ +#define ERASE_T_COUNT_Pos (0UL) /**< Erase Type X Erase, Typical time: count (Bits 4:0) */ +#define ERASE_T_COUNT_Msk (0x1FUL) /**< Erase Type X Erase, Typical time: count (Bitfield-Mask) */ +#define ERASE_T_UNITS_Pos (5UL) /**< Erase Type X Erase, Typical time: units (Bits 6:5) */ +#define ERASE_T_UNITS_Msk (0x60UL) /**< Erase Type X Erase, Typical time: units (Bitfield-Mask) */ +#define ERASE_T_COUNT_OFFSET (0x04U) /** The offset of the Erase count 10th DWORD */ +#define ERASE_T_LENGTH (0x07U) /** The Erase Type Typical time length */ +#define COMMAND_IS_NOT_FOUND (0x0U) +#define PARAMETER_IS_NOT_FOUND (0x0U) + +#define MEM_ADDR_VALID(addr, size) (0U == ((addr)%(size))) /* This address must be a multiple of + * the SMIF XIP memory size + */ +#define MEM_MAPPED_SIZE_VALID(size) (((size) >= 0x10000U) && (0U == ((size)&((size)-1U))) ) +#define MEM_ADDR_SIZE_VALID(addrSize) ((0U < (addrSize)) && ((addrSize) <= 4U)) /** \endcond*/ @@ -46,6 +87,46 @@ extern "C" { ***************************************/ static void XipRegInit(SMIF_DEVICE_Type volatile *dev, cy_stc_smif_mem_config_t const * memCfg); +static cy_en_smif_status_t SfdpReadBuffer(SMIF_Type *base, + cy_stc_smif_mem_cmd_t const *cmdSfdp, + uint8_t const sfdpAddress[], + cy_en_smif_slave_select_t slaveSelect, + uint32_t size, + uint8_t sfdpBuffer[], + cy_stc_smif_context_t *context); +static uint32_t SfdpFindParameterHeader(uint32_t id, uint8_t const sfdpBuffer[]); +static cy_en_smif_status_t SfdpFindParameterTableAddress(uint32_t id, + uint8_t const sfdpBuffer[], + uint8_t address[], + uint32_t *tableLength); +static uint32_t SfdpGetNumOfAddrBytes(uint8_t const sfdpBuffer[]); +static uint32_t SfdpGetMemoryDensity(uint8_t const sfdpBuffer[]); +static void SfdpGetReadCmd_1_4_4(uint8_t const sfdpBuffer[], + cy_stc_smif_mem_cmd_t* cmdRead); +static void SfdpGetReadCmd_1_1_4(uint8_t const sfdpBuffer[], + cy_stc_smif_mem_cmd_t* cmdRead); +static void SfdpGetReadCmd_1_2_2(uint8_t const sfdpBuffer[], + cy_stc_smif_mem_cmd_t* cmdRead); +static void SfdpGetReadCmd_1_1_2(uint8_t const sfdpBuffer[], + cy_stc_smif_mem_cmd_t* cmdRead); +static void SfdpGetReadCmd_1_1_1(uint8_t const sfdpBuffer[], + cy_stc_smif_mem_cmd_t* cmdRead); +static void SfdpGetReadCmdParams(uint8_t const sfdpBuffer[], + cy_en_smif_data_select_t dataSelect, + cy_stc_smif_mem_cmd_t* cmdRead); +static uint32_t SfdpGetPageSize(uint8_t const sfdpBuffer[]); +static uint32_t SfdpGetEraseTime(uint32_t const eraseOffset, uint8_t const sfdpBuffer[]); +static uint32_t SfdpGetChipEraseTime(uint8_t const sfdpBuffer[]); +static uint32_t SfdpGetPageProgramTime(uint8_t const sfdpBuffer[]); +static void SfdpSetWriteEnableCommand(cy_stc_smif_mem_cmd_t* cmdWriteEnable); +static void SfdpSetWriteDisableCommand(cy_stc_smif_mem_cmd_t* cmdWriteDisable); +static void SfdpSetProgramCommand(cy_stc_smif_mem_cmd_t* cmdProgram); +static void SfdpGetQuadEnableParameters(cy_stc_smif_mem_device_cfg_t *device, + uint8_t const sfdpBuffer[]); +static void SfdpSetChipEraseCommand(cy_stc_smif_mem_cmd_t* cmdChipErase); +static uint32_t SfdpGetSectorEraseCommand(cy_stc_smif_mem_cmd_t* cmdSectorErase, + uint8_t const sfdpBuffer[]); +static void SfdpSetWipStatusRegisterCommand(cy_stc_smif_mem_cmd_t* readStsRegWipCmd); /******************************************************************************* @@ -53,7 +134,9 @@ static void XipRegInit(SMIF_DEVICE_Type volatile *dev, ****************************************************************************//** * * This function initializes the slots of the memory device in the SMIF -* configuration. After this initialization, the memory slave devices are +* configuration. +* If the user applies the external memory as memory-mapped +* to PSoC (XIP mode), after such initialization, the memory slave devices are * automatically mapped into the PSoC memory map. The function needs the SMIF * to be running in the memory mode to have the memory mapped into the PSoC * address space. This function is typically called in the System initialization @@ -73,13 +156,13 @@ static void XipRegInit(SMIF_DEVICE_Type volatile *dev, * \param base * The address of the slave-slot device register to initialize. * -* \param context -* The SMIF internal context structure of the block. -* * \param blockConfig * The configuration structure array that configures the SMIF memory device to be * mapped into the PSoC memory map. \ref cy_stc_smif_mem_config_t * +* \param context +* The SMIF internal context structure of the block. +* * \return The memory slot initialization status. * - \ref CY_SMIF_SUCCESS * - \ref CY_SMIF_BAD_PARAM @@ -111,7 +194,7 @@ cy_en_smif_status_t Cy_SMIF_Memslot_Init(SMIF_Type *base, CY_ASSERT_L3(CY_SMIF_SLAVE_SEL_VALID(memCfg->slaveSelect)); CY_ASSERT_L3(CY_SMIF_DATA_SEL_VALID(memCfg->dataSelect)); CY_ASSERT_L1(NULL != memCfg->deviceCfg); - CY_ASSERT_L2(CY_SMIF_MEM_ADDR_SIZE_VALID(memCfg->deviceCfg->numOfAddrBytes)); + CY_ASSERT_L2(MEM_ADDR_SIZE_VALID(memCfg->deviceCfg->numOfAddrBytes)); device = Cy_SMIF_GetDeviceBySlot(base, memCfg->slaveSelect); if (NULL != device) @@ -138,8 +221,8 @@ cy_en_smif_status_t Cy_SMIF_Memslot_Init(SMIF_Type *base, (0U != (memCfg->flags & CY_SMIF_FLAG_MEMORY_MAPPED))) { /* Check valid parameters for XIP */ - CY_ASSERT_L3(CY_SMIF_MEM_ADDR_VALID( memCfg->baseAddress, memCfg->memMappedSize)); - CY_ASSERT_L3(CY_SMIF_MEM_MAPPED_SIZE_VALID( memCfg->memMappedSize)); + CY_ASSERT_L3(MEM_ADDR_VALID( memCfg->baseAddress, memCfg->memMappedSize)); + CY_ASSERT_L3(MEM_MAPPED_SIZE_VALID( memCfg->memMappedSize)); XipRegInit(device, memCfg); @@ -295,12 +378,12 @@ void Cy_SMIF_Memslot_DeInit(SMIF_Type *base) * \param base * Holds the base address of the SMIF block registers. * -* \param context -* The internal SMIF context data. \ref cy_stc_smif_context_t -* * \param memDevice * The device to which the command is sent. * +* \param context +* The internal SMIF context data. \ref cy_stc_smif_context_t +* * \return A status of the command transmission. * - \ref CY_SMIF_SUCCESS * - \ref CY_SMIF_EXCEED_TIMEOUT @@ -345,12 +428,12 @@ cy_en_smif_status_t Cy_SMIF_Memslot_CmdWriteEnable(SMIF_Type *base, * \param base * Holds the base address of the SMIF block registers. * -* \param context -* The internal SMIF context data. \ref cy_stc_smif_context_t -* * \param memDevice * The device to which the command is sent. * +* \param context +* The internal SMIF context data. \ref cy_stc_smif_context_t +* * \return A status of the command transmission. * - \ref CY_SMIF_SUCCESS * - \ref CY_SMIF_EXCEED_TIMEOUT @@ -396,12 +479,12 @@ cy_en_smif_status_t Cy_SMIF_Memslot_CmdWriteDisable(SMIF_Type *base, * \param base * Holds the base address of the SMIF block registers. * -* \param context -* The internal SMIF context data. -* * \param memDevice * The device to which the command is sent. * +* \param context +* The internal SMIF context data. +* * \return A status of the memory device. * - True - The device is busy or a timeout occurs. * - False - The device is not busy. @@ -446,12 +529,12 @@ bool Cy_SMIF_Memslot_IsBusy(SMIF_Type *base, cy_stc_smif_mem_config_t *memDevice * \param base * Holds the base address of the SMIF block registers. * -* \param context -* The internal SMIF context data. -* * \param memDevice * The device to which the command is sent. * +* \param context +* The internal SMIF context data. +* * \return A status of the command. * - \ref CY_SMIF_SUCCESS * - \ref CY_SMIF_NO_QE_BIT @@ -543,9 +626,6 @@ cy_en_smif_status_t Cy_SMIF_Memslot_QuadEnable(SMIF_Type *base, * \param base * Holds the base address of the SMIF block registers. * -* \param context -* The internal SMIF context data. -* * \param memDevice * The device to which the command is sent. * @@ -555,6 +635,9 @@ cy_en_smif_status_t Cy_SMIF_Memslot_QuadEnable(SMIF_Type *base, * \param command * The command required to read the status/configuration register. * +* \param context +* The internal SMIF context data. +* * \return A status of the command reception. * - \ref CY_SMIF_SUCCESS * - \ref CY_SMIF_CMD_FIFO_FULL @@ -602,9 +685,6 @@ cy_en_smif_status_t Cy_SMIF_Memslot_CmdReadSts(SMIF_Type *base, * \param base * Holds the base address of the SMIF block registers. * -* \param context -* The internal SMIF context data. \ref cy_stc_smif_context_t -* * \param memDevice * The device to which the command is sent. * @@ -612,7 +692,10 @@ cy_en_smif_status_t Cy_SMIF_Memslot_CmdReadSts(SMIF_Type *base, * The status to write into the status register. * * \param command -* The command to write into the status/configuration register. +* The command to write into the status/configuration register. +* +* \param context +* The internal SMIF context data. \ref cy_stc_smif_context_t * * \return A status of the command transmission. * - \ref CY_SMIF_SUCCESS @@ -662,12 +745,12 @@ cy_en_smif_status_t Cy_SMIF_Memslot_CmdWriteSts(SMIF_Type *base, * \param base * Holds the base address of the SMIF block registers. * -* \param context -* The internal SMIF context data. \ref cy_stc_smif_context_t -* * \param memDevice * The device to which the command is sent * +* \param context +* The internal SMIF context data. \ref cy_stc_smif_context_t +* * \return A status of the command transmission. * - \ref CY_SMIF_SUCCESS * - \ref CY_SMIF_EXCEED_TIMEOUT @@ -707,15 +790,15 @@ cy_en_smif_status_t Cy_SMIF_Memslot_CmdChipErase(SMIF_Type *base, * \param base * Holds the base address of the SMIF block registers. * -* \param context -* The internal SMIF context data. \ref cy_stc_smif_context_t -* * \param memDevice * The device to which the command is sent. * * \param sectorAddr * The sector address to erase. * +* \param context +* The internal SMIF context data. \ref cy_stc_smif_context_t +* * \return A status of the command transmission. * - \ref CY_SMIF_SUCCESS * - \ref CY_SMIF_BAD_PARAM @@ -765,9 +848,6 @@ cy_en_smif_status_t Cy_SMIF_Memslot_CmdSectorErase(SMIF_Type *base, * \param base * Holds the base address of the SMIF block registers. * -* \param context -* The internal SMIF context data. -* * \param memDevice * The device to which the command is sent. * @@ -784,7 +864,6 @@ cy_en_smif_status_t Cy_SMIF_Memslot_CmdSectorErase(SMIF_Type *base, * the FIFO transaction, this could either stall or timeout the operation * \ref Cy_SMIF_TransmitData(). * -* * \param size * The size of data to program. The user must ensure that the data size * does not exceed the page size. @@ -793,6 +872,9 @@ cy_en_smif_status_t Cy_SMIF_Memslot_CmdSectorErase(SMIF_Type *base, * The callback function to call after the transfer completion. NULL interpreted * as no callback. * +* \param context +* The internal SMIF context data. +* * \return A status of a transmission. * - \ref CY_SMIF_SUCCESS * - \ref CY_SMIF_CMD_FIFO_FULL @@ -871,9 +953,6 @@ cy_en_smif_status_t Cy_SMIF_Memslot_CmdProgram(SMIF_Type *base, * \param base * Holds the base address of the SMIF block registers. * -* \param context -* The internal SMIF context data. -* * \param memDevice * The device to which the command is sent. * @@ -897,6 +976,9 @@ cy_en_smif_status_t Cy_SMIF_Memslot_CmdProgram(SMIF_Type *base, * The callback function to call after the transfer completion. NULL interpreted * as no callback. * +* \param context +* The internal SMIF context data. +* * \return A status of the transmission. * - \ref CY_SMIF_SUCCESS * - \ref CY_SMIF_CMD_FIFO_FULL @@ -963,6 +1045,942 @@ cy_en_smif_status_t Cy_SMIF_Memslot_CmdRead(SMIF_Type *base, } +/******************************************************************************* +* Function Name: SfdpReadBuffer +****************************************************************************//** +* +* This function reads the tables in the SDFP database into the buffer. +* +* \note This function is a blocking function and blocks until the structure data +* is read and returned. This function uses \ref Cy_SMIF_TransmitCommand() +* +* \param *base +* Holds the base address of the SMIF block registers. +* +* \param *cmdSfdp +* The command structure to store the Read/Write command +* configuration. +* +* \param sfdpAddress +* The pointer to an array with the address bytes +* associated with the memory command. +* +* \param slaveSelect +* Denotes the number of the slave device to which the transfer is made. +* (0, 1, 2 or 4 - the bit defines which slave to enable). The two-bit enable +* is possible only for the Double Quad SPI mode. +* +* \param size +* The size of data to be received. Must be > 0 and not greater than 65536. +* +* \param sfdpBuffer +* The pointer to an array with the SDFP buffer. +* +* \param context +* Internal SMIF context data. +* +* \return A status of the transmission. +* - \ref CY_SMIF_SUCCESS +* - \ref CY_SMIF_CMD_FIFO_FULL +* - \ref CY_SMIF_NO_SFDP_SUPPORT +* - \ref CY_SMIF_EXCEED_TIMEOUT +* +*******************************************************************************/ +static cy_en_smif_status_t SfdpReadBuffer(SMIF_Type *base, + cy_stc_smif_mem_cmd_t const *cmdSfdp, + uint8_t const sfdpAddress[], + cy_en_smif_slave_select_t slaveSelect, + uint32_t size, + uint8_t sfdpBuffer[], + cy_stc_smif_context_t *context) +{ + cy_en_smif_status_t result = CY_SMIF_NO_SFDP_SUPPORT; + + result = Cy_SMIF_TransmitCommand( base, (uint8_t)cmdSfdp->command, + cmdSfdp->cmdWidth, sfdpAddress, CY_SMIF_SFDP_ADDRESS_LENGTH, + cmdSfdp->addrWidth, slaveSelect, CY_SMIF_TX_NOT_LAST_BYTE, + context); + + if(CY_SMIF_SUCCESS == result) + { + result = Cy_SMIF_SendDummyCycles(base, cmdSfdp->dummyCycles); + + /* Get data from SFDP and 1st Basic Flash Parameter Headers only */ + if(CY_SMIF_SUCCESS == result) + { + result = Cy_SMIF_ReceiveData( base, sfdpBuffer, size, + cmdSfdp->dataWidth, NULL, context); + + if (CY_SMIF_SUCCESS == result) + { + uint32_t cmdTimeout = context->timeout; + while (((uint32_t) CY_SMIF_REC_CMPLT != context->transferStatus) && + (CY_SMIF_EXCEED_TIMEOUT != result)) + { + /* Wait until the Read of the SFDP operation is completed */ + result = Cy_SMIF_TimeoutRun(&cmdTimeout); + } + } + } + } + + return(result); +} + + +/******************************************************************************* +* Function Name: SfdpFindParameterHeader +****************************************************************************//** +* +* Finds the Parameter Header offset from the JEDEC basic flash parameter table. +* +* \param sfdpBuffer +* The pointer to an array with the SDFP buffer. +* +* \param id +* The parameter ID. +* +* \return The relative parameter header offset in bytes. +* Returns 0 when the parameter header is not found. +* +*******************************************************************************/ +static uint32_t SfdpFindParameterHeader(uint32_t id, uint8_t const sfdpBuffer[]) +{ + uint32_t headerOffset = PARAMETER_IS_NOT_FOUND; + uint32_t maxMinorRevison = 0UL; + uint32_t sfdpAddress = FIRST_HEADER_OFFSET; /* Begin from 1st Parameter Header */ + + while (sfdpAddress <= (((uint32_t)sfdpBuffer[PARAM_HEADERS_NUM] * + HEADER_LENGTH) + + FIRST_HEADER_OFFSET)) + { + /* Check parameter ID */ + if (((id & PARAM_ID_LSB_MASK) == sfdpBuffer[sfdpAddress]) && /* Parameter ID LSB */ + (((id >> PARAM_ID_MSB_OFFSET) & PARAM_ID_LSB_MASK) == + sfdpBuffer[sfdpAddress + /* Parameter ID MSB */ + PARAM_ID_MSB_REL_OFFSET])) + { + /* Check parameter major and minor revisions */ + if ((sfdpBuffer[sfdpAddress + PARAM_MINOR_REV_REL_OFFSET] >= maxMinorRevison) && + (sfdpBuffer[sfdpAddress + PARAM_MAJOR_REV_REL_OFFSET] == CY_SMIF_SFDP_MAJOR_REV_1)) + { + /* Get the maximum minor revision */ + maxMinorRevison = sfdpBuffer[sfdpAddress + PARAM_MINOR_REV_REL_OFFSET]; + + /* Save the the Parameter Header offset with the maximum minor revision */ + headerOffset = sfdpAddress; + } + } + + sfdpAddress += HEADER_LENGTH; + } + + return(headerOffset); +} + + +/******************************************************************************* +* Function Name: SfdpFindParameterTableAddress +****************************************************************************//** +* +* Reads the address and length of the Parameter Table from +* the JEDEC basic flash parameter table. +* +* \param id +* The parameter ID. +* +* \param sfdpBuffer +* The pointer to an array with the SDFP buffer. +* +* \param address +* The Parameter Table address. +* +* \param *tableLength +* The Parameter Table length. +* +* \return The command reception status. +* - \ref CY_SMIF_SUCCESS +* - \ref CY_SMIF_CMD_NOT_FOUND +* +*******************************************************************************/ +static cy_en_smif_status_t SfdpFindParameterTableAddress(uint32_t id, + uint8_t const sfdpBuffer[], + uint8_t address[], + uint32_t *tableLength) +{ + cy_en_smif_status_t result = CY_SMIF_CMD_NOT_FOUND; + uint32_t headerOffset; + + headerOffset = SfdpFindParameterHeader(id, sfdpBuffer); + + if (PARAMETER_IS_NOT_FOUND != headerOffset) + { + /* The Parameter Table address */ + address[2] = sfdpBuffer[headerOffset + + PARAM_TABLE_PRT_OFFSET]; + address[1] = sfdpBuffer[headerOffset + + PARAM_TABLE_PRT_OFFSET + 1UL]; + address[0] = sfdpBuffer[headerOffset + + PARAM_TABLE_PRT_OFFSET + 2UL]; + + /* The Parameter Table length */ + *tableLength = (uint32_t)sfdpBuffer[headerOffset + PARAM_TABLE_LENGTH_OFFSET] * + BYTES_IN_DWORD; + + result = CY_SMIF_SUCCESS; + } + + return(result); +} + + +/******************************************************************************* +* Function Name: SfdpGetNumOfAddrBytes +****************************************************************************//** +* +* Reads the number of address bytes from the JEDEC basic flash parameter table. +* +* \param sfdpBuffer +* The pointer to an array with the SDFP buffer. +* +* \return The number of address bytes used by the memory slave device. +* +*******************************************************************************/ +static uint32_t SfdpGetNumOfAddrBytes(uint8_t const sfdpBuffer[]) +{ + uint32_t addrBytesNum = 0UL; + uint32_t sfdpAddrCode = _FLD2VAL(CY_SMIF_SFDP_ADDRESS_BYTES, + (uint32_t)sfdpBuffer + [CY_SMIF_SFDP_BFPT_BYTE_02]); + switch(sfdpAddrCode) + { + case CY_SMIF_SFDP_THREE_BYTES_ADDR_CODE: + addrBytesNum = CY_SMIF_THREE_BYTES_ADDR; + break; + case CY_SMIF_SFDP_THREE_OR_FOUR_BYTES_ADDR_CODE: + addrBytesNum = CY_SMIF_THREE_BYTES_ADDR; + break; + case CY_SMIF_SFDP_FOUR_BYTES_ADDR_CODE: + addrBytesNum = CY_SMIF_FOUR_BYTES_ADDR; + break; + default: + break; + } + + return(addrBytesNum); +} + + +/******************************************************************************* +* Function Name: SfdpGetMemoryDensity +****************************************************************************//** +* +* Reads the Memory Density from the JEDEC basic flash parameter table. +* +* \param sfdpBuffer +* The pointer to an array with the SDFP buffer. +* +* \return The external memory size: +* For densities of 2 gigabits or less - the size in bytes; +* For densities 4 gigabits and above - bit-31 is set to 1b to define that +* this memory is 4 gigabits and above; and other 30:0 bits define N where +* the density is computed as 2^N bytes. +* For example, 0x80000021 corresponds to 2^30 = 1 gigabyte. +* +*******************************************************************************/ +static uint32_t SfdpGetMemoryDensity(uint8_t const sfdpBuffer[]) +{ + uint32_t memorySize; + uint32_t locSize = Cy_SMIF_PackBytesArray(&sfdpBuffer[CY_SMIF_SFDP_BFPT_BYTE_04], true); + + if (0UL == (locSize & CY_SMIF_SFDP_SIZE_ABOVE_4GB_Msk)) + { + memorySize = (locSize + 1UL)/BITS_IN_BYTE; + } + else + { + memorySize = (locSize - BITS_IN_BYTE_ABOVE_4GB) | + CY_SMIF_SFDP_SIZE_ABOVE_4GB_Msk; + } + + return(memorySize); +} + + +/******************************************************************************* +* Function Name: SfdpGetReadCmd_1_4_4 +****************************************************************************//** +* +* Reads the FAST_READ_1_4_4 read command parameters from the JEDEC basic flash +* parameter table. +* +* \param sfdpBuffer +* The pointer to an array with the SDFP buffer. +* +* \param cmdRead +* The pointer to the read command parameters structure. +* +*******************************************************************************/ +static void SfdpGetReadCmd_1_4_4(uint8_t const sfdpBuffer[], + cy_stc_smif_mem_cmd_t* cmdRead) +{ + /* 8-bit command. 4 x I/O Read command */ + cmdRead->command = sfdpBuffer[CY_SMIF_SFDP_BFPT_BYTE_09]; + + /* The command transfer width */ + cmdRead->cmdWidth = CY_SMIF_WIDTH_SINGLE; + + /* The address transfer width */ + cmdRead->addrWidth = CY_SMIF_WIDTH_QUAD; + + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present */ + if (0U == (_FLD2VAL(CY_SMIF_SFDP_1_4_4_MODE_CYCLES, + (uint32_t) sfdpBuffer[CY_SMIF_SFDP_BFPT_BYTE_08]))) + { + cmdRead->mode = CY_SMIF_NO_COMMAND_OR_MODE; + } + else + { + cmdRead->mode = READ_ENHANCED_MODE_DISABLED; + cmdRead->modeWidth = CY_SMIF_WIDTH_QUAD; + } + + /* The dummy cycles number. A zero value suggests no dummy cycles */ + cmdRead->dummyCycles = _FLD2VAL(CY_SMIF_SFDP_1_4_4_DUMMY_CYCLES, + (uint32_t) sfdpBuffer[CY_SMIF_SFDP_BFPT_BYTE_08]); + + /* The data transfer width */ + cmdRead->dataWidth = CY_SMIF_WIDTH_QUAD; +} + + +/******************************************************************************* +* Function Name: SfdpGetReadCmd_1_1_4 +****************************************************************************//** +* +* Reads the FAST_READ_1_1_4 read command parameters from the JEDEC basic flash +* parameter table. +* +* \param sfdpBuffer +* The pointer to an array with the SDFP buffer. +* +* \param cmdRead +* The pointer to the read command parameters structure. +* +*******************************************************************************/ +static void SfdpGetReadCmd_1_1_4(uint8_t const sfdpBuffer[], + cy_stc_smif_mem_cmd_t* cmdRead) +{ + /* 8-bit command. 4 x I/O Read command */ + cmdRead->command = + sfdpBuffer[CY_SMIF_SFDP_BFPT_BYTE_0B]; + + /* The command transfer width */ + cmdRead->cmdWidth = CY_SMIF_WIDTH_SINGLE; + + /* The address transfer width */ + cmdRead->addrWidth = CY_SMIF_WIDTH_SINGLE; + + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present */ + if ((0U == _FLD2VAL(CY_SMIF_SFDP_1_1_4_MODE_CYCLES, (uint32_t) sfdpBuffer + [CY_SMIF_SFDP_BFPT_BYTE_0A]))) + { + cmdRead->mode = CY_SMIF_NO_COMMAND_OR_MODE; + } + else + { + cmdRead->mode = READ_ENHANCED_MODE_DISABLED; + cmdRead->modeWidth = CY_SMIF_WIDTH_SINGLE; + } + + /* The dummy cycles number. A zero value suggests no dummy cycles */ + cmdRead->dummyCycles = _FLD2VAL(CY_SMIF_SFDP_1_1_4_DUMMY_CYCLES, + (uint32_t)sfdpBuffer[CY_SMIF_SFDP_BFPT_BYTE_0A]); + + /* The data transfer width */ + cmdRead->dataWidth = CY_SMIF_WIDTH_QUAD; +} + + +/******************************************************************************* +* Function Name: SfdpGetReadCmd_1_2_2 +****************************************************************************//** +* +* Reads the FAST_READ_1_2_2 read command parameters from the JEDEC basic flash +* parameter table. +* +* \param sfdpBuffer +* The pointer to an array with the SDFP buffer. +* +* \param cmdRead +* The pointer to the read command parameters structure. +* +*******************************************************************************/ +static void SfdpGetReadCmd_1_2_2(uint8_t const sfdpBuffer[], + cy_stc_smif_mem_cmd_t* cmdRead) +{ + /* 8-bit command. 2 x I/O Read command */ + cmdRead->command = sfdpBuffer[CY_SMIF_SFDP_BFPT_BYTE_0F]; + + /* The command transfer width */ + cmdRead->cmdWidth = CY_SMIF_WIDTH_SINGLE; + + /* The address transfer width */ + cmdRead->addrWidth = CY_SMIF_WIDTH_DUAL; + + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present */ + if (0U == _FLD2VAL(CY_SMIF_SFDP_1_2_2_MODE_CYCLES, (uint32_t) + sfdpBuffer[CY_SMIF_SFDP_BFPT_BYTE_0E])) + { + cmdRead->mode = CY_SMIF_NO_COMMAND_OR_MODE; + } + else + { + cmdRead->mode = READ_ENHANCED_MODE_DISABLED; + cmdRead->modeWidth = CY_SMIF_WIDTH_DUAL; + } + + /* The dummy cycles number. A zero value suggests no dummy cycles. */ + cmdRead->dummyCycles = _FLD2VAL(CY_SMIF_SFDP_1_2_2_DUMMY_CYCLES, + (uint32_t) sfdpBuffer [CY_SMIF_SFDP_BFPT_BYTE_0E]); + + /* The data transfer width */ + cmdRead->dataWidth = CY_SMIF_WIDTH_DUAL; +} + + +/******************************************************************************* +* Function Name: SfdpGetReadCmd_1_1_2 +****************************************************************************//** +* +* Reads the FAST_READ_1_1_2 read command parameters from the JEDEC basic flash +* parameter table. +* +* \param sfdpBuffer +* The pointer to an array with the SDFP buffer. +* +* \param cmdRead +* The pointer to the read command parameters structure. +* +*******************************************************************************/ +static void SfdpGetReadCmd_1_1_2(uint8_t const sfdpBuffer[], + cy_stc_smif_mem_cmd_t* cmdRead) +{ + /* 8-bit command. 2 x I/O Read command */ + cmdRead->command = sfdpBuffer[CY_SMIF_SFDP_BFPT_BYTE_0D]; + + /* The command transfer width */ + cmdRead->cmdWidth = CY_SMIF_WIDTH_SINGLE; + + /* The address transfer width */ + cmdRead->addrWidth = CY_SMIF_WIDTH_SINGLE; + + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present */ + if ((_FLD2VAL(CY_SMIF_SFDP_1_1_2_MODE_CYCLES, (uint32_t) + sfdpBuffer[CY_SMIF_SFDP_BFPT_BYTE_0C])) == 0U) + { + cmdRead->mode = CY_SMIF_NO_COMMAND_OR_MODE; + } + else + { + cmdRead->mode = READ_ENHANCED_MODE_DISABLED; + cmdRead->modeWidth = CY_SMIF_WIDTH_SINGLE; + } + + /* The dummy cycles number. A zero value suggests no dummy cycles. */ + cmdRead->dummyCycles = _FLD2VAL(CY_SMIF_SFDP_1_1_2_DUMMY_CYCLES, + (uint32_t)sfdpBuffer[CY_SMIF_SFDP_BFPT_BYTE_0C]); + + /* The data transfer width */ + cmdRead->dataWidth = CY_SMIF_WIDTH_DUAL; +} + + +/******************************************************************************* +* Function Name: SfdpGetReadCmd_1_1_1 +****************************************************************************//** +* +* Reads the FAST_READ_1_1_1 read command parameters from the JEDEC basic flash +* parameter table. +* +* \param sfdpBuffer +* The pointer to an array with the SDFP buffer. +* +* \param cmdRead +* The pointer to the read command parameters structure. +* +*******************************************************************************/ +static void SfdpGetReadCmd_1_1_1(uint8_t const sfdpBuffer[], + cy_stc_smif_mem_cmd_t* cmdRead) +{ + /* 8-bit command. 1 x I/O Read command */ + cmdRead->command = CY_SMIF_SINGLE_READ_CMD; + + /* The command transfer width */ + cmdRead->cmdWidth = CY_SMIF_WIDTH_SINGLE; + + /* The address transfer width */ + cmdRead->addrWidth = CY_SMIF_WIDTH_SINGLE; + + /* The 8 bit-mode byte. This value is 0xFFFFFFFF when there is no mode present */ + cmdRead->mode = CY_SMIF_NO_COMMAND_OR_MODE; + + /* The dummy cycles number. A zero value suggests no dummy cycles. */ + cmdRead->dummyCycles = 0UL; + + /* The data transfer width */ + cmdRead->dataWidth = CY_SMIF_WIDTH_SINGLE; +} + + +/******************************************************************************* +* Function Name: SfdpGetReadCmdParams +****************************************************************************//** +* +* Reads the read command parameters from the JEDEC basic flash parameter table. +* +* \param sfdpBuffer +* The pointer to an array with the SDFP buffer. +* +* \param dataSelect +* The data line selection options for a slave device. +* +* \param cmdRead +* The pointer to the read command parameters structure. +* +*******************************************************************************/ +static void SfdpGetReadCmdParams(uint8_t const sfdpBuffer[], + cy_en_smif_data_select_t dataSelect, + cy_stc_smif_mem_cmd_t* cmdRead) +{ + uint32_t sfdpDataIndex = CY_SMIF_SFDP_BFPT_BYTE_02; + bool quadEnabled = ((CY_SMIF_DATA_SEL1 != dataSelect) && + (CY_SMIF_DATA_SEL3 != dataSelect)); + + if (quadEnabled) + { + if (1UL == _FLD2VAL(CY_SMIF_SFDP_FAST_READ_1_4_4, + ((uint32_t) sfdpBuffer[sfdpDataIndex]))) + + { + SfdpGetReadCmd_1_4_4(sfdpBuffer, cmdRead); + } + else if (1UL == _FLD2VAL(CY_SMIF_SFDP_FAST_READ_1_1_4, + ((uint32_t)sfdpBuffer[sfdpDataIndex]))) + { + SfdpGetReadCmd_1_1_4(sfdpBuffer, cmdRead); + } + else + { + /* Wrong mode */ + CY_ASSERT_L2(true); + } + } + else + { + if ((1UL == _FLD2VAL(CY_SMIF_SFDP_FAST_READ_1_2_2, + (uint32_t)sfdpBuffer[sfdpDataIndex]))) + { + SfdpGetReadCmd_1_2_2(sfdpBuffer, cmdRead); + } + else + { + if (1UL == _FLD2VAL(CY_SMIF_SFDP_FAST_READ_1_1_2, + (uint32_t)sfdpBuffer[sfdpDataIndex])) + { + SfdpGetReadCmd_1_1_2(sfdpBuffer, cmdRead); + } + else + { + SfdpGetReadCmd_1_1_1(sfdpBuffer, cmdRead); + } + } + } +} + + +/******************************************************************************* +* Function Name: SfdpGetPageSize +****************************************************************************//** +* +* Reads the page size from the JEDEC basic flash parameter table. +* +* \param sfdpBuffer +* The pointer to an array with the SDFP buffer. +* +* \return The page size in bytes. +* +*******************************************************************************/ +static uint32_t SfdpGetPageSize(uint8_t const sfdpBuffer[]) +{ + uint32_t size; + + /* The page size */ + size = 0x01UL << _FLD2VAL(CY_SMIF_SFDP_PAGE_SIZE, + (uint32_t) sfdpBuffer[CY_SMIF_SFDP_BFPT_BYTE_28]); + + return(size); +} + + +/******************************************************************************* +* Function Name: SfdpGetEraseTime +****************************************************************************//** +* +* Calculates erase time. +* +* \param eraseOffset +* The offset of the Sector Erase command in the SFDP buffer. +* +* \param sfdpBuffer +* The pointer to an array with the SDFP buffer. +* +* \return Erase time in us. +* +*******************************************************************************/ +static uint32_t SfdpGetEraseTime(uint32_t const eraseOffset, uint8_t const sfdpBuffer[]) +{ + /* Get the value of 10th DWORD from the JEDEC basic flash parameter table */ + uint32_t readEraseTime = ((uint32_t*)sfdpBuffer)[CY_SMIF_JEDEC_BFPT_10TH_DWORD]; + + uint32_t eraseTimeMax; + uint32_t eraseTimeIndex = (((eraseOffset - CY_SMIF_SFDP_BFPT_BYTE_1D) + TYPE_STEP) / TYPE_STEP); + uint32_t eraseUnits = _FLD2VAL(ERASE_T_UNITS, + (readEraseTime >> ((eraseTimeIndex - 1UL) * ERASE_T_LENGTH)) + >> ERASE_T_COUNT_OFFSET); + uint32_t eraseCount = _FLD2VAL(ERASE_T_COUNT, + (readEraseTime >> ((eraseTimeIndex - 1UL) * ERASE_T_LENGTH)) + >> ERASE_T_COUNT_OFFSET); + uint32_t eraseMul = _FLD2VAL(CY_SMIF_SFDP_ERASE_MUL_COUNT, readEraseTime); + uint32_t eraseMs = 0UL; + + switch (eraseUnits) + { + case CY_SMIF_SFDP_UNIT_0: + eraseMs = CY_SMIF_SFDP_ERASE_TIME_1MS; + break; + case CY_SMIF_SFDP_UNIT_1: + eraseMs = CY_SMIF_SFDP_ERASE_TIME_16MS; + break; + case CY_SMIF_SFDP_UNIT_2: + eraseMs = CY_SMIF_SFDP_ERASE_TIME_128MS; + break; + case CY_SMIF_SFDP_UNIT_3: + eraseMs = CY_SMIF_SFDP_ERASE_TIME_1S; + break; + default: + /* An unsupported SFDP value */ + break; + } + + /* Convert typical time to max time */ + eraseTimeMax = ((eraseCount + 1UL) * eraseMs) * (2UL * (eraseMul + 1UL)); + + return(eraseTimeMax); +} + + +/******************************************************************************* +* Function Name: SfdpGetChipEraseTime +****************************************************************************//** +* +* Calculates chip erase time. +* +* \param sfdpBuffer +* The pointer to an array with the SDFP buffer. +* +* \return Chip erase time in us. +* +*******************************************************************************/ +static uint32_t SfdpGetChipEraseTime(uint8_t const sfdpBuffer[]) +{ + /* Get the value of 10th DWORD from the JEDEC basic flash parameter table */ + uint32_t readEraseTime = ((uint32_t*)sfdpBuffer)[CY_SMIF_JEDEC_BFPT_10TH_DWORD]; + + /* Get the value of 11th DWORD from the JEDEC basic flash parameter table */ + uint32_t chipEraseProgTime = ((uint32_t*)sfdpBuffer)[CY_SMIF_JEDEC_BFPT_11TH_DWORD]; + + uint32_t chipEraseTimeMax; + uint32_t chipEraseUnits = _FLD2VAL(CY_SMIF_SFDP_CHIP_ERASE_UNITS, chipEraseProgTime); + uint32_t chipEraseCount = _FLD2VAL(CY_SMIF_SFDP_CHIP_ERASE_COUNT, chipEraseProgTime); + uint32_t chipEraseMs = 0UL; + uint32_t eraseMul = _FLD2VAL(CY_SMIF_SFDP_ERASE_MUL_COUNT, readEraseTime); + + switch (chipEraseUnits) + { + case CY_SMIF_SFDP_UNIT_0: + chipEraseMs = CY_SMIF_SFDP_CHIP_ERASE_TIME_16MS; + break; + case CY_SMIF_SFDP_UNIT_1: + chipEraseMs = CY_SMIF_SFDP_CHIP_ERASE_TIME_256MS; + break; + case CY_SMIF_SFDP_UNIT_2: + chipEraseMs = CY_SMIF_SFDP_CHIP_ERASE_TIME_4S; + break; + case CY_SMIF_SFDP_UNIT_3: + chipEraseMs = CY_SMIF_SFDP_CHIP_ERASE_TIME_64S; + break; + default: + /* An unsupported SFDP value*/ + break; + } + + /* Convert typical time to max time */ + chipEraseTimeMax = ((chipEraseCount + 1UL)*chipEraseMs) * (2UL *(eraseMul + 1UL)); + + return(chipEraseTimeMax); +} + + +/******************************************************************************* +* Function Name: SfdpGetPageProgramTime +****************************************************************************//** +* +* Calculates page program time. +* +* \param sfdpBuffer +* The pointer to an array with the SDFP buffer. +* +* \return Page program time in us. +* +*******************************************************************************/ +static uint32_t SfdpGetPageProgramTime(uint8_t const sfdpBuffer[]) +{ + /* Get the value of 11th DWORD from the JEDEC basic flash parameter table */ + uint32_t chipEraseProgTime = ((uint32_t*)sfdpBuffer)[CY_SMIF_JEDEC_BFPT_11TH_DWORD]; + uint32_t programTimeMax; + uint32_t programTimeUnits = _FLD2VAL(CY_SMIF_SFDP_PAGE_PROG_UNITS, chipEraseProgTime); + uint32_t programTimeCount = _FLD2VAL(CY_SMIF_SFDP_PAGE_PROG_COUNT, chipEraseProgTime); + uint32_t progMul = _FLD2VAL(CY_SMIF_SFDP_PROG_MUL_COUNT, chipEraseProgTime); + uint32_t progUs; + + if (CY_SMIF_SFDP_UNIT_0 == programTimeUnits) + { + progUs = CY_SMIF_SFDP_PROG_TIME_8US; + } + else + { + progUs = CY_SMIF_SFDP_PROG_TIME_64US; + } + + /* Convert typical time to max time */ + programTimeMax = ((programTimeCount + 1UL) * progUs) * (2UL * (progMul + 1UL)); + + return(programTimeMax); +} + + +/******************************************************************************* +* Function Name: SfdpSetWriteEnableCommand +****************************************************************************//** +* +* Sets the Write Enable command and the width of the command transfer. +* +* \param cmdWriteEnable +* The pointer to the Write Enable command parameters structure. +* +*******************************************************************************/ +static void SfdpSetWriteEnableCommand(cy_stc_smif_mem_cmd_t* cmdWriteEnable) +{ + /* 8-bit command. Write Enable */ + cmdWriteEnable->command = CY_SMIF_WR_ENABLE_CMD; + + /* The width of the command transfer */ + cmdWriteEnable->cmdWidth = CY_SMIF_WIDTH_SINGLE; +} + + +/******************************************************************************* +* Function Name: SfdpSetWriteDisableCommand +****************************************************************************//** +* +* Sets the Write Disable command and the width of the command transfer. +* +* \param cmdWriteDisable +* The pointer to the Write Disable command parameters structure. +* +*******************************************************************************/ +static void SfdpSetWriteDisableCommand(cy_stc_smif_mem_cmd_t* cmdWriteDisable) +{ + /* The 8-bit command. Write Disable */ + cmdWriteDisable->command = CY_SMIF_WR_DISABLE_CMD; + + /* The width of the command transfer */ + cmdWriteDisable->cmdWidth = CY_SMIF_WIDTH_SINGLE; +} + + +/******************************************************************************* +* Function Name: SfdpSetProgramCommand +****************************************************************************//** +* +* Sets the Program command parameters. +* +* \param cmdProgram +* The pointer to the Program command parameters structure. +* +*******************************************************************************/ +static void SfdpSetProgramCommand(cy_stc_smif_mem_cmd_t* cmdProgram) +{ + /* 8-bit command. 1 x I/O Program command */ + cmdProgram->command = CY_SMIF_SINGLE_PROGRAM_CMD; + /* The command transfer width */ + cmdProgram->cmdWidth = CY_SMIF_WIDTH_SINGLE; + /* The address transfer width */ + cmdProgram->addrWidth = CY_SMIF_WIDTH_SINGLE; + /* 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present */ + cmdProgram->mode = CY_SMIF_NO_COMMAND_OR_MODE; + /* The dummy cycles number. A zero value suggests no dummy cycles */ + cmdProgram->dummyCycles = 0UL; + /* The data transfer width */ + cmdProgram->dataWidth = CY_SMIF_WIDTH_SINGLE; +} + + +/******************************************************************************* +* Function Name: SfdpSetWipStatusRegisterCommand +****************************************************************************//** +* +* Sets the WIP-containing status register command and +* the width of the command transfer. +* +* \param readStsRegWipCmd +* The pointer to the WIP-containing status register command parameters structure. +* +*******************************************************************************/ +static void SfdpSetWipStatusRegisterCommand(cy_stc_smif_mem_cmd_t* readStsRegWipCmd) +{ + /* 8-bit command. WIP RDSR */ + readStsRegWipCmd->command = CY_SMIF_RD_STS_REG1_CMD; + /* The command transfer width */ + readStsRegWipCmd->cmdWidth = CY_SMIF_WIDTH_SINGLE; +} + + +/******************************************************************************* +* Function Name: SfdpGetQuadEnableParameters +****************************************************************************//** +* +* Gets the Quad Enable parameters. +* +* \param device +* The device structure instance declared by the user. This is where the detected +* parameters are stored and returned. +* +* \param sfdpBuffer +* The pointer to an array with the SDFP buffer. +* +*******************************************************************************/ +static void SfdpGetQuadEnableParameters(cy_stc_smif_mem_device_cfg_t *device, + uint8_t const sfdpBuffer[]) +{ + /* The command transfer width */ + device->writeStsRegQeCmd->cmdWidth = CY_SMIF_WIDTH_SINGLE; + + /* The QE mask for the status registers */ + switch (_FLD2VAL(CY_SMIF_SFDP_QE_REQUIREMENTS, (uint32_t)sfdpBuffer + [CY_SMIF_SFDP_BFPT_BYTE_3A])) + { + case CY_SMIF_SFDP_QER_0: + device->stsRegQuadEnableMask = CY_SMIF_NO_COMMAND_OR_MODE; + device->writeStsRegQeCmd->command = CY_SMIF_NO_COMMAND_OR_MODE; + device->readStsRegQeCmd->command = CY_SMIF_NO_COMMAND_OR_MODE; + break; + case CY_SMIF_SFDP_QER_1: + case CY_SMIF_SFDP_QER_4: + case CY_SMIF_SFDP_QER_5: + device->stsRegQuadEnableMask = CY_SMIF_SFDP_QE_BIT_1_OF_SR_2; + + /* The command to write into the QE-containing status register */ + /* The 8-bit command. QE WRSR */ + device->writeStsRegQeCmd->command = CY_SMIF_WR_STS_REG1_CMD; + device->readStsRegQeCmd->command = CY_SMIF_RD_STS_REG2_T1_CMD; + break; + case CY_SMIF_SFDP_QER_2: + device->stsRegQuadEnableMask = CY_SMIF_SFDP_QE_BIT_6_OF_SR_1; + + /* The command to write into the QE-containing status register */ + /* The 8-bit command. QE WRSR */ + device->writeStsRegQeCmd->command = CY_SMIF_WR_STS_REG1_CMD; + device->readStsRegQeCmd->command = CY_SMIF_RD_STS_REG1_CMD; + break; + case CY_SMIF_SFDP_QER_3: + device->stsRegQuadEnableMask = CY_SMIF_SFDP_QE_BIT_7_OF_SR_2; + + /* The command to write into the QE-containing status register */ + /* The 8-bit command. QE WRSR */ + device->writeStsRegQeCmd->command = CY_SMIF_WR_STS_REG2_CMD; + device->readStsRegQeCmd->command = CY_SMIF_RD_STS_REG2_T2_CMD; + break; + default: + break; + } +} + + +/******************************************************************************* +* Function Name: SfdpSetChipEraseCommand +****************************************************************************//** +* +* Sets the Chip Erase command and the width of the command transfer. +* +* \param cmdChipErase +* The pointer to the Chip Erase command parameters structure. +* +* \param sfdpBuffer +* The pointer to an array with the SDFP buffer. +* +*******************************************************************************/ +static void SfdpSetChipEraseCommand(cy_stc_smif_mem_cmd_t* cmdChipErase) +{ + /* 8-bit command. Chip Erase */ + cmdChipErase->command = CY_SMIF_CHIP_ERASE_CMD; + /* The width of the command transfer */ + cmdChipErase->cmdWidth = CY_SMIF_WIDTH_SINGLE; +} + + +/******************************************************************************* +* Function Name: SfdpGetSectorEraseCommand +****************************************************************************//** +* +* Sets the Sector Erase command and the width of the command transfer. +* +* \param cmdSectorErase +* The pointer to the Sector Erase command parameters structure. +* +* \return The offset of the Sector Erase command in the SFDP buffer. +* Returns 0 when the Sector Erase command is not found. +* +*******************************************************************************/ +static uint32_t SfdpGetSectorEraseCommand(cy_stc_smif_mem_cmd_t* cmdSectorErase, + uint8_t const sfdpBuffer[]) +{ + uint32_t eraseOffset = CY_SMIF_SFDP_BFPT_BYTE_1D; + while (INSTRUCTION_NOT_SUPPORTED == sfdpBuffer[eraseOffset]) + { + if (eraseOffset >= CY_SMIF_SFDP_BFPT_BYTE_23) + { + /* The Sector Erase command is not found */ + eraseOffset = COMMAND_IS_NOT_FOUND; + break; + } + eraseOffset += TYPE_STEP; /* Check the next Erase Type */ + } + + /* Get the sector Erase command from the JEDEC basic flash parameter table */ + cmdSectorErase->command = sfdpBuffer[eraseOffset]; + + /* The command transfer width */ + cmdSectorErase->cmdWidth = CY_SMIF_WIDTH_SINGLE; + + /* The address transfer width */ + cmdSectorErase->addrWidth = CY_SMIF_WIDTH_SINGLE; + + return(eraseOffset); +} + + /******************************************************************************* * Function Name: Cy_SMIF_Memslot_SfdpDetect ****************************************************************************//** @@ -988,9 +2006,6 @@ cy_en_smif_status_t Cy_SMIF_Memslot_CmdRead(SMIF_Type *base, * \param base * Holds the base address of the SMIF block registers. * -* \param context -* The internal SMIF context data. -* * \param device * The device structure instance declared by the user. This is where the detected * parameters are stored and returned. @@ -1001,6 +2016,9 @@ cy_en_smif_status_t Cy_SMIF_Memslot_CmdRead(SMIF_Type *base, * \param dataSelect * The data line selection options for a slave device. * +* \param context +* Internal SMIF context data. +* * \return A status of the transmission. * - \ref CY_SMIF_SUCCESS * - \ref CY_SMIF_CMD_FIFO_FULL @@ -1014,7 +2032,7 @@ cy_en_smif_status_t Cy_SMIF_Memslot_SfdpDetect(SMIF_Type *base, cy_en_smif_data_select_t dataSelect, cy_stc_smif_context_t *context) { - /* Check input parameters */ + /* Check the input parameters */ CY_ASSERT_L1(NULL != device); uint8_t sfdpBuffer[CY_SMIF_SFDP_LENGTH]; @@ -1022,37 +2040,32 @@ cy_en_smif_status_t Cy_SMIF_Memslot_SfdpDetect(SMIF_Type *base, cy_en_smif_status_t result = CY_SMIF_NO_SFDP_SUPPORT; cy_stc_smif_mem_cmd_t *cmdSfdp = device->readSfdpCmd; + /* Initialize the SFDP buffer */ + for (uint32_t i = 0U; i < CY_SMIF_SFDP_LENGTH; i++) + { + sfdpBuffer[i] = 0U; + } + /* Slave slot initialization */ Cy_SMIF_SetDataSelect(base, slaveSelect, dataSelect); - if(NULL != cmdSfdp) + if (NULL != cmdSfdp) { - result = Cy_SMIF_TransmitCommand( base, (uint8_t)cmdSfdp->command, - cmdSfdp->cmdWidth, sfdpAddress, CY_SMIF_SFDP_ADDRESS_LENGTH, - cmdSfdp->addrWidth, slaveSelect, CY_SMIF_TX_NOT_LAST_BYTE, - context); + /* Get the SDFP header and all parameter headers content into sfdpBuffer[] */ + result = SfdpReadBuffer(base, + cmdSfdp, + sfdpAddress, + slaveSelect, + HEADERS_LENGTH, + sfdpBuffer, + context); } - - if(CY_SMIF_SUCCESS == result) + + /* Check if we support all parameter headers */ + if ((CY_SMIF_SUCCESS == result) && + (sfdpBuffer[PARAM_HEADERS_NUM] > PARAM_HEADER_NUM)) { - result = Cy_SMIF_SendDummyCycles(base, cmdSfdp->dummyCycles); - } - - if(CY_SMIF_SUCCESS == result) - { - result = Cy_SMIF_ReceiveData( base, sfdpBuffer, CY_SMIF_SFDP_LENGTH, - cmdSfdp->dataWidth, NULL, context); - } - - if (CY_SMIF_SUCCESS == result) - { - uint32_t cmdTimeout = context->timeout; - while (((uint32_t) CY_SMIF_REC_CMPLT != context->transferStatus) && - (CY_SMIF_EXCEED_TIMEOUT != result)) - { - /* Wait until the Read of the SFDP operation is completed. */ - result = Cy_SMIF_TimeoutRun(&cmdTimeout); - } + result = CY_SMIF_NO_SFDP_SUPPORT; } if (CY_SMIF_SUCCESS == result) @@ -1064,378 +2077,75 @@ cy_en_smif_status_t Cy_SMIF_Memslot_SfdpDetect(SMIF_Type *base, (sfdpBuffer[CY_SMIF_SFDP_MINOR_REV] >= CY_SMIF_SFDP_JEDEC_REV_B) && (sfdpBuffer[CY_SMIF_SFDP_MAJOR_REV] == CY_SMIF_SFDP_MAJOR_REV_1)) { - /* The address of the JEDEC basic flash parameter table */ - uint8_t offset = sfdpBuffer[CY_SMIF_SFDP_PARAM_TABLE_PTR]; - cy_stc_smif_mem_cmd_t *cmdRead = device->readCmd; + /* Find JEDEC SFDP Basic SPI Flash Parameter Header */ + uint32_t id = (BASIC_SPI_ID_MSB << BITS_IN_BYTE) | + BASIC_SPI_ID_LSB; + uint32_t basicSpiTableLength; + result = SfdpFindParameterTableAddress(id, + sfdpBuffer, + sfdpAddress, + &basicSpiTableLength); + + if (CY_SMIF_SUCCESS == result) + { + /* Get the JEDEC basic flash parameter table content into sfdpBuffer[] */ + result = SfdpReadBuffer(base, + cmdSfdp, + sfdpAddress, + slaveSelect, + basicSpiTableLength, + sfdpBuffer, + context); - /* The number of address bytes used by the memory slave device */ - uint32_t sfdpDataIndex = CY_SMIF_SFDP_BFPT_BYTE_02 + (uint32_t)offset; - uint32_t sfdpAddrCode = _FLD2VAL(CY_SMIF_SFDP_ADDRESS_BYTES, - (uint32_t)sfdpBuffer - [sfdpDataIndex]); - switch(sfdpAddrCode) - { - case CY_SMIF_SFDP_THREE_BYTES_ADDR_CODE: - device->numOfAddrBytes = CY_SMIF_THREE_BYTES_ADDR; - break; - case CY_SMIF_SFDP_THREE_OR_FOUR_BYTES_ADDR_CODE: - device->numOfAddrBytes = CY_SMIF_THREE_BYTES_ADDR; - break; - case CY_SMIF_SFDP_FOUR_BYTES_ADDR_CODE: - device->numOfAddrBytes = CY_SMIF_FOUR_BYTES_ADDR; - break; - default: - break; - } + /* The number of address bytes used by the memory slave device */ + device->numOfAddrBytes = SfdpGetNumOfAddrBytes(sfdpBuffer); - /* Erase Time Type 1*/ - uint32_t readEraseTime = ((uint32_t*)sfdpBuffer)[(offset/CY_SMIF_BYTES_IN_WORD) + - CY_SMIF_JEDEC_BFPT_10TH_DWORD]; - uint32_t eraseUnits = _FLD2VAL(CY_SMIF_SFDP_ERASE_T1_UNITS, readEraseTime); - uint32_t eraseCount = _FLD2VAL(CY_SMIF_SFDP_ERASE_T1_COUNT, readEraseTime); - uint32_t eraseMul = _FLD2VAL(CY_SMIF_SFDP_ERASE_MUL_COUNT, readEraseTime); - uint32_t eraseMs = 0U; + /* The external memory size */ + device->memSize = SfdpGetMemoryDensity(sfdpBuffer); + + /* The page size */ + device->programSize = SfdpGetPageSize(sfdpBuffer); - switch (eraseUnits) - { - case CY_SMIF_SFDP_UNIT_0: - eraseMs = CY_SMIF_SFDP_ERASE_TIME_1MS; - break; - case CY_SMIF_SFDP_UNIT_1: - eraseMs = CY_SMIF_SFDP_ERASE_TIME_16MS; - break; - case CY_SMIF_SFDP_UNIT_2: - eraseMs = CY_SMIF_SFDP_ERASE_TIME_128MS; - break; - case CY_SMIF_SFDP_UNIT_3: - eraseMs = CY_SMIF_SFDP_ERASE_TIME_1S; - break; - default: - /* An unsupported SFDP value */ - break; - } - /* Convert typical time to max time */ - device->eraseTime = ((eraseCount + 1U) * eraseMs) * (2U * (eraseMul + 1U)); + /* This specifies the Read command. The preference order Quad>Dual>SPI */ + cy_stc_smif_mem_cmd_t *cmdRead = device->readCmd; + SfdpGetReadCmdParams(sfdpBuffer, dataSelect, cmdRead); + /* The Write Enable command */ + SfdpSetWriteEnableCommand(device->writeEnCmd); - /* Chip Erase Time*/ - uint32_t chipEraseProgTime = ((uint32_t*)sfdpBuffer)[(offset/CY_SMIF_BYTES_IN_WORD) + - CY_SMIF_JEDEC_BFPT_11TH_DWORD]; - uint32_t chipEraseUnits = _FLD2VAL(CY_SMIF_SFDP_CHIP_ERASE_UNITS, chipEraseProgTime); - uint32_t chipEraseCount = _FLD2VAL(CY_SMIF_SFDP_CHIP_ERASE_COUNT, chipEraseProgTime); - uint32_t chipEraseMs = 0U; + /* The Write Disable command */ + SfdpSetWriteDisableCommand(device->writeDisCmd); + + /* The program command */ + SfdpSetProgramCommand(device->programCmd); - switch (chipEraseUnits) - { - case CY_SMIF_SFDP_UNIT_0: - chipEraseMs = CY_SMIF_SFDP_CHIP_ERASE_TIME_16MS; - break; - case CY_SMIF_SFDP_UNIT_1: - chipEraseMs = CY_SMIF_SFDP_CHIP_ERASE_TIME_256MS; - break; - case CY_SMIF_SFDP_UNIT_2: - chipEraseMs = CY_SMIF_SFDP_CHIP_ERASE_TIME_4S; - break; - case CY_SMIF_SFDP_UNIT_3: - chipEraseMs = CY_SMIF_SFDP_CHIP_ERASE_TIME_64S; - break; - default: - /* An unsupported SFDP value*/ - break; - } - /* Convert typical time to max time */ - device->chipEraseTime = ((chipEraseCount + 1U)*chipEraseMs) * (2U *(eraseMul + 1U)); + /* The busy mask for the status registers */ + device->stsRegBusyMask = CY_SMIF_STS_REG_BUSY_MASK; + + /* The command to read the WIP-containing status register */ + SfdpSetWipStatusRegisterCommand(device->readStsRegWipCmd); - /* Page Program Time*/ - uint32_t programTimeUnits = _FLD2VAL(CY_SMIF_SFDP_PAGE_PROG_UNITS, chipEraseProgTime); - uint32_t programTimeCount = _FLD2VAL(CY_SMIF_SFDP_PAGE_PROG_COUNT, chipEraseProgTime); - uint32_t progMul = _FLD2VAL(CY_SMIF_SFDP_PROG_MUL_COUNT, chipEraseProgTime); - uint32_t progUs; + /* The command to write into the QE-containing status register */ + SfdpGetQuadEnableParameters(device, sfdpBuffer); - if (CY_SMIF_SFDP_UNIT_0 == programTimeUnits) - { - progUs = CY_SMIF_SFDP_PROG_TIME_8US; - } - else - { - progUs = CY_SMIF_SFDP_PROG_TIME_64US; - } - /* Convert typical time to max time */ - device->programTime = ((programTimeCount + 1U) * progUs) * (2U * (progMul + 1U)); + /* Chip Erase command */ + SfdpSetChipEraseCommand(device->chipEraseCmd); + + /* Find the sector Erase command type with 3-bytes addressing */ + uint32_t eraseTypeOffset; + eraseTypeOffset = SfdpGetSectorEraseCommand(device->eraseCmd, sfdpBuffer); + + /* The Erase sector size */ + device->eraseSize = (0x01UL << (uint32_t)sfdpBuffer[eraseTypeOffset - 1UL]); + /* Erase Time Type */ + device->eraseTime = SfdpGetEraseTime(eraseTypeOffset, sfdpBuffer); + + /* Chip Erase Time */ + device->chipEraseTime = SfdpGetChipEraseTime(sfdpBuffer); - /* The size of the external memory */ - uint32_t locSize = Cy_SMIF_PackBytesArray(&sfdpBuffer[CY_SMIF_SFDP_BFPT_BYTE_04 + - offset], true); - - if (0UL == (locSize & CY_SMIF_SFDP_SIZE_ABOVE_4GB_Msk)) - { - device->memSize = (locSize + 1UL)/CY_SMIF_BITS_IN_BYTE; - } - else - { - device->memSize = (locSize - CY_SMIF_BITS_IN_BYTE_ABOVE_4GB) | - CY_SMIF_SFDP_SIZE_ABOVE_4GB_Msk; - } - - /* The page size */ - device->programSize = 0x01UL << _FLD2VAL(CY_SMIF_SFDP_PAGE_SIZE, - (uint32_t) sfdpBuffer[CY_SMIF_SFDP_BFPT_BYTE_28 + offset]); - - /* The size of the Erase sector */ - device->eraseSize = (0x01UL << (uint32_t)sfdpBuffer[CY_SMIF_SFDP_BFPT_BYTE_1C + offset]); - - /* This specifies the Read command. The preference order Quad>Dual>SPI */ - if ((_FLD2VAL(CY_SMIF_SFDP_FAST_READ_1_4_4, - ((uint32_t) sfdpBuffer[sfdpDataIndex])) == 1UL) && - (CY_SMIF_DATA_SEL1 != dataSelect) && - (CY_SMIF_DATA_SEL3 != dataSelect)) - { - /* The 8-bit command. 4 x I/O Read command */ - cmdRead->command = sfdpBuffer[CY_SMIF_SFDP_BFPT_BYTE_09 + offset]; - - /* The width of the command transfer */ - cmdRead->cmdWidth = CY_SMIF_WIDTH_SINGLE; - - /* The width of the address transfer */ - cmdRead->addrWidth = CY_SMIF_WIDTH_QUAD; - - /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present */ - if ((_FLD2VAL(CY_SMIF_SFDP_1_4_4_MODE_CYCLES, - (uint32_t) sfdpBuffer[CY_SMIF_SFDP_BFPT_BYTE_08 + offset])) == 0U) - { - cmdRead->mode = CY_SMIF_NO_COMMAND_OR_MODE; - } - else - { - cmdRead->mode = READ_ENHANCED_MODE_DISABLED; - cmdRead->modeWidth = CY_SMIF_WIDTH_QUAD; - } - - /* The number of the dummy cycles. A zero value suggests no dummy cycles */ - cmdRead->dummyCycles = _FLD2VAL(CY_SMIF_SFDP_1_4_4_DUMMY_CYCLES, (uint32_t) sfdpBuffer - [CY_SMIF_SFDP_BFPT_BYTE_08 + offset]); - - /* The width of the data transfer*/ - cmdRead->dataWidth = CY_SMIF_WIDTH_QUAD; - } - else - { - if ((_FLD2VAL(CY_SMIF_SFDP_FAST_READ_1_1_4, - ((uint32_t)sfdpBuffer[sfdpDataIndex])) == 1UL) && - (CY_SMIF_DATA_SEL1 != dataSelect) && - (CY_SMIF_DATA_SEL3 != dataSelect)) - { - /* The 8-bit command. 4 x I/O Read command */ - cmdRead->command = - sfdpBuffer[CY_SMIF_SFDP_BFPT_BYTE_0B + offset]; - - /* The width of the command transfer */ - cmdRead->cmdWidth = CY_SMIF_WIDTH_SINGLE; - - /* The width of the address transfer */ - cmdRead->addrWidth = CY_SMIF_WIDTH_SINGLE; - - /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present */ - if ((_FLD2VAL(CY_SMIF_SFDP_1_1_4_MODE_CYCLES, (uint32_t) sfdpBuffer - [CY_SMIF_SFDP_BFPT_BYTE_0A + offset])) == 0U) - { - cmdRead->mode = CY_SMIF_NO_COMMAND_OR_MODE; - } - else - { - cmdRead->mode = READ_ENHANCED_MODE_DISABLED; - cmdRead->modeWidth = CY_SMIF_WIDTH_SINGLE; - } - - /* The number of the dummy cycles. A zero value suggests no dummy cycles */ - cmdRead->dummyCycles = _FLD2VAL(CY_SMIF_SFDP_1_1_4_DUMMY_CYCLES, - (uint32_t)sfdpBuffer[CY_SMIF_SFDP_BFPT_BYTE_0A + offset]); - - /* The width of the data transfer*/ - cmdRead->dataWidth = CY_SMIF_WIDTH_QUAD; - } - else - { - if ((_FLD2VAL(CY_SMIF_SFDP_FAST_READ_1_2_2, - (uint32_t)sfdpBuffer[sfdpDataIndex])) == 1UL) - { - /* The 8-bit command. 2 x I/O Read command */ - cmdRead->command = sfdpBuffer[CY_SMIF_SFDP_BFPT_BYTE_0F + offset]; - - /* The width of the command transfer */ - cmdRead->cmdWidth = CY_SMIF_WIDTH_SINGLE; - - /* The width of the address transfer */ - cmdRead->addrWidth = CY_SMIF_WIDTH_DUAL; - - /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present */ - if ((_FLD2VAL(CY_SMIF_SFDP_1_2_2_MODE_CYCLES, (uint32_t) - sfdpBuffer[CY_SMIF_SFDP_BFPT_BYTE_0E + offset])) == 0U) - { - cmdRead->mode = CY_SMIF_NO_COMMAND_OR_MODE; - } - else - { - cmdRead->mode = READ_ENHANCED_MODE_DISABLED; - cmdRead->modeWidth = CY_SMIF_WIDTH_DUAL; - } - - /* The number of the dummy cycles. A zero value suggests no dummy cycles */ - cmdRead->dummyCycles = _FLD2VAL(CY_SMIF_SFDP_1_2_2_DUMMY_CYCLES, - (uint32_t) sfdpBuffer [CY_SMIF_SFDP_BFPT_BYTE_0E + offset]); - - /* The width of the data transfer*/ - cmdRead->dataWidth = CY_SMIF_WIDTH_DUAL; - } - else - { - if ((_FLD2VAL(CY_SMIF_SFDP_FAST_READ_1_1_2, - (uint32_t)sfdpBuffer[sfdpDataIndex])) == 1UL) - { - /* The 8-bit command. 2 x I/O Read command */ - cmdRead->command = sfdpBuffer[CY_SMIF_SFDP_BFPT_BYTE_0D + offset]; - - /* The width of the command transfer */ - cmdRead->cmdWidth = CY_SMIF_WIDTH_SINGLE; - - /* The width of the address transfer */ - cmdRead->addrWidth = CY_SMIF_WIDTH_SINGLE; - - /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present */ - if ((_FLD2VAL(CY_SMIF_SFDP_1_1_2_MODE_CYCLES, (uint32_t) - sfdpBuffer[CY_SMIF_SFDP_BFPT_BYTE_0C + offset])) == 0U) - { - cmdRead->mode = CY_SMIF_NO_COMMAND_OR_MODE; - } - else - { - cmdRead->mode = READ_ENHANCED_MODE_DISABLED; - cmdRead->modeWidth = CY_SMIF_WIDTH_SINGLE; - } - - /* The number of the dummy cycles. A zero value suggests no dummy cycles */ - cmdRead->dummyCycles = _FLD2VAL(CY_SMIF_SFDP_1_1_2_DUMMY_CYCLES, - (uint32_t)sfdpBuffer[CY_SMIF_SFDP_BFPT_BYTE_0C + offset]); - - /* The width of the data transfer*/ - cmdRead->dataWidth = CY_SMIF_WIDTH_DUAL; - } - else - { - /* The 8-bit command. 1 x I/O Read command */ - cmdRead->command = CY_SMIF_SINGLE_READ_CMD; - - /* The width of the command transfer */ - cmdRead->cmdWidth = CY_SMIF_WIDTH_SINGLE; - - /* The width of the address transfer */ - cmdRead->addrWidth = CY_SMIF_WIDTH_SINGLE; - - /* The 8 bit-mode byte. This value is 0xFFFFFFFF when there is no mode present */ - cmdRead->mode = CY_SMIF_NO_COMMAND_OR_MODE; - - /* The number of the dummy cycles. A zero value suggests no dummy cycles */ - cmdRead->dummyCycles = 0U; - - /* The width of the data transfer*/ - cmdRead->dataWidth = CY_SMIF_WIDTH_SINGLE; - } - } - } - } - - /* The Write Enable command */ - /* The 8-bit command. Write Enable */ - device->writeEnCmd->command = CY_SMIF_WR_ENABLE_CMD; - /* The width of the command transfer */ - device->writeEnCmd->cmdWidth = CY_SMIF_WIDTH_SINGLE; - - /* The Write Disable command */ - /* The 8-bit command. Write Disable */ - device->writeDisCmd->command = CY_SMIF_WR_DISABLE_CMD; - /* The width of the command transfer */ - device->writeDisCmd->cmdWidth = CY_SMIF_WIDTH_SINGLE; - - /* The chip Erase command */ - /* The 8-bit command. Chip Erase */ - device->chipEraseCmd->command = CY_SMIF_CHIP_ERASE_CMD; - /* The width of the command transfer */ - device->chipEraseCmd->cmdWidth = CY_SMIF_WIDTH_SINGLE; - - /* The sector Erase command */ - /* The 8-bit command. The sector Erase */ - device->eraseCmd->command = - sfdpBuffer[CY_SMIF_SFDP_BFPT_BYTE_1D + offset]; - /* The width of the command transfer */ - device->eraseCmd->cmdWidth = CY_SMIF_WIDTH_SINGLE; - /* The width of the address transfer */ - device->eraseCmd->addrWidth = CY_SMIF_WIDTH_SINGLE; - - /* This specifies the program command */ - /* The 8-bit command. 1 x I/O Program command */ - device->programCmd->command = CY_SMIF_SINGLE_PROGRAM_CMD; - /* The width of the command transfer */ - device->programCmd->cmdWidth = CY_SMIF_WIDTH_SINGLE; - /* The width of the address transfer */ - device->programCmd->addrWidth = CY_SMIF_WIDTH_SINGLE; - /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present */ - device->programCmd->mode = CY_SMIF_NO_COMMAND_OR_MODE; - /* The number of the dummy cycles. A zero value suggests no dummy cycles */ - device->programCmd->dummyCycles = 0U; - /* The width of the data transfer*/ - device->programCmd->dataWidth = CY_SMIF_WIDTH_SINGLE; - - /* The busy mask for the status registers */ - device->stsRegBusyMask = CY_SMIF_STS_REG_BUSY_MASK; - - /* The command to read the WIP-containing status register */ - /* The 8-bit command. WIP RDSR */ - device->readStsRegWipCmd->command = CY_SMIF_RD_STS_REG1_CMD; - /* The width of the command transfer */ - device->readStsRegWipCmd->cmdWidth = CY_SMIF_WIDTH_SINGLE; - - /* The command to write into the QE-containing status register */ - /* The width of the command transfer */ - device->writeStsRegQeCmd->cmdWidth = CY_SMIF_WIDTH_SINGLE; - - /* The QE mask for the status registers */ - switch (_FLD2VAL(CY_SMIF_SFDP_QE_REQUIREMENTS, (uint32_t)sfdpBuffer - [CY_SMIF_SFDP_BFPT_BYTE_3A + offset])) - { - case CY_SMIF_SFDP_QER_0: - device->stsRegQuadEnableMask = CY_SMIF_NO_COMMAND_OR_MODE; - device->writeStsRegQeCmd->command = CY_SMIF_NO_COMMAND_OR_MODE; - device->readStsRegQeCmd->command = CY_SMIF_NO_COMMAND_OR_MODE; - break; - case CY_SMIF_SFDP_QER_1: - case CY_SMIF_SFDP_QER_4: - case CY_SMIF_SFDP_QER_5: - device->stsRegQuadEnableMask = CY_SMIF_SFDP_QE_BIT_1_OF_SR_2; - - /* The command to write into the QE-containing status register */ - /* The 8-bit command. QE WRSR */ - device->writeStsRegQeCmd->command = CY_SMIF_WR_STS_REG1_CMD; - device->readStsRegQeCmd->command = CY_SMIF_RD_STS_REG2_T1_CMD; - break; - case CY_SMIF_SFDP_QER_2: - device->stsRegQuadEnableMask = CY_SMIF_SFDP_QE_BIT_6_OF_SR_1; - - /* The command to write into the QE-containing status register */ - /* The 8-bit command. QE WRSR */ - device->writeStsRegQeCmd->command = CY_SMIF_WR_STS_REG1_CMD; - device->readStsRegQeCmd->command = CY_SMIF_RD_STS_REG1_CMD; - break; - case CY_SMIF_SFDP_QER_3: - device->stsRegQuadEnableMask = CY_SMIF_SFDP_QE_BIT_7_OF_SR_2; - - /* The command to write into the QE-containing status register */ - /* The 8-bit command. QE WRSR */ - device->writeStsRegQeCmd->command = CY_SMIF_WR_STS_REG2_CMD; - device->readStsRegQeCmd->command = CY_SMIF_RD_STS_REG2_T2_CMD; - break; - default: - break; + /* Page Program Time */ + device->programTime = SfdpGetPageProgramTime(sfdpBuffer); } } else diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_sysclk.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_sysclk.c index f22507f51b..242ec970f0 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_sysclk.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_sysclk.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_sysclk.c -* \version 1.30 +* \version 1.40 * * Provides an API implementation of the sysclk driver. * @@ -28,8 +28,43 @@ #include -/* # of elements in an array */ -#define CY_SYSCLK_N_ELMTS(a) (sizeof(a) / sizeof((a)[0])) +/* ========================================================================== */ +/* ========================= EXTCLK SECTION =========================== */ +/* ========================================================================== */ + +/** \cond INTERNAL */ +static uint32_t extFreq = 0UL; /* Internal storage for external clock frequency user setting */ + +#define CY_SYSCLK_EXTCLK_MAX_FREQ (100000000UL) /* 100 MHz */ +/** \endcond */ + +/** +* \addtogroup group_sysclk_ext_funcs +* \{ +*/ + +/******************************************************************************* +* Function Name: Cy_SysClk_ExtClkSetFrequency +****************************************************************************//** +* +* Sets the signal frequency of the External Clock Source (EXTCLK) into the +* internal storage to be used in \ref Cy_SysClk_ClkHfGetFrequency. +* +* \param freq The frequency of the External Clock Source. +* +* \funcusage +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ExtClkSetFrequency +* +*******************************************************************************/ +void Cy_SysClk_ExtClkSetFrequency(uint32_t freq) +{ + if (freq <= CY_SYSCLK_EXTCLK_MAX_FREQ) + { + extFreq = freq; + } +} +/** \} group_sysclk_ext_funcs */ + /* ========================================================================== */ /* =========================== ECO SECTION ============================ */ @@ -42,7 +77,7 @@ SRSS_CLK_TRIM_ECO_CTL_RTRIM_Msk | \ SRSS_CLK_TRIM_ECO_CTL_GTRIM_Msk) - + /******************************************************************************* * Function Name: cy_sqrt * Calculates square root. @@ -69,8 +104,9 @@ static uint32_t cy_sqrt(uint64_t x) return (res); } -/** \endcond */ +static uint32_t ecoFreq = 0UL; /* Internal storage for ECO frequency user setting */ +/** \endcond */ /** * \addtogroup group_sysclk_eco_funcs @@ -139,7 +175,7 @@ static uint32_t cy_sqrt(uint64_t x) * * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_EcoConfigure +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_EcoConfigure * *******************************************************************************/ cy_en_sysclk_status_t Cy_SysClk_EcoConfigure(uint32_t freq, uint32_t cLoad, uint32_t esr, uint32_t driveLevel) @@ -149,11 +185,11 @@ cy_en_sysclk_status_t Cy_SysClk_EcoConfigure(uint32_t freq, uint32_t cLoad, uint if (0UL == (SRSS_CLK_ECO_CONFIG_ECO_EN_Msk & SRSS_CLK_ECO_CONFIG)) { /* calculate intermediate values */ - uint32_t maxAmplitude = (uint32_t)CY_SYSCLK_DIV_ROUND((1000000000000ULL * /* 1000000.0f * 1000.0f * 10^3 */ - cy_sqrt(CY_SYSCLK_DIV_ROUND(500000ULL * (uint64_t)driveLevel, (uint64_t)esr))), + uint32_t maxAmplitude = (uint32_t)CY_SYSLIB_DIV_ROUND((1000000000000ULL * /* 1000000.0f * 1000.0f * 10^3 */ + cy_sqrt(CY_SYSLIB_DIV_ROUND(500000ULL * (uint64_t)driveLevel, (uint64_t)esr))), (3141ULL * (uint64_t)freq * (uint64_t)cLoad)); /* The result is scaled by 10^3 */ - uint32_t nAmpSections = (uint32_t)CY_SYSCLK_DIV_ROUND((uint64_t)freq * + uint32_t nAmpSections = (uint32_t)CY_SYSLIB_DIV_ROUND((uint64_t)freq * (uint64_t)freq * (uint64_t)cLoad * (uint64_t)cLoad, 5704868154158ULL); /* (4.5 * (10^15) / 788.8), the result is scaled by 10^6 */ @@ -174,7 +210,7 @@ cy_en_sysclk_status_t Cy_SysClk_EcoConfigure(uint32_t freq, uint32_t cLoad, uint uint32_t wdtrim = (maxAmplitude < 1200UL) ? ((maxAmplitude / 100UL) - 4UL) : 6UL; - uint32_t gtrim = ((nAmpSections > 1000000UL) ? CY_SYSCLK_DIV_ROUND(nAmpSections, 1000000UL) : + uint32_t gtrim = ((nAmpSections > 1000000UL) ? CY_SYSLIB_DIV_ROUND(nAmpSections, 1000000UL) : ((nAmpSections == 1000000UL) ? 0UL : 1UL)); uint32_t rtrim = ((freq > 26800000UL) ? 0UL : @@ -190,6 +226,8 @@ cy_en_sysclk_status_t Cy_SysClk_EcoConfigure(uint32_t freq, uint32_t cLoad, uint CY_REG32_CLR_SET(SRSS_CLK_TRIM_ECO_CTL, CY_SYSCLK_TRIM_ECO, reg); + ecoFreq = freq; /* Store ECO frequency */ + retVal = CY_SYSCLK_SUCCESS; } /* if valid parameters */ } /* if ECO not enabled */ @@ -217,7 +255,7 @@ cy_en_sysclk_status_t Cy_SysClk_EcoConfigure(uint32_t freq, uint32_t cLoad, uint * if it affects the CLK_HF0 frequency. * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_EcoEnable +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_EcoEnable * *******************************************************************************/ cy_en_sysclk_status_t Cy_SysClk_EcoEnable(uint32_t timeoutus) @@ -283,7 +321,7 @@ cy_en_sysclk_status_t Cy_SysClk_EcoEnable(uint32_t timeoutus) * it affects the CLK_HF0 frequency and the frequency is decreasing. * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_ClkPathSetSource +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPathSetSource * *******************************************************************************/ cy_en_sysclk_status_t Cy_SysClk_ClkPathSetSource(uint32_t clkPath, cy_en_clkpath_in_sources_t source) @@ -319,7 +357,7 @@ cy_en_sysclk_status_t Cy_SysClk_ClkPathSetSource(uint32_t clkPath, cy_en_clkpath * \return \ref cy_en_clkpath_in_sources_t * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_ClkPathGetSource +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPathGetSource * *******************************************************************************/ cy_en_clkpath_in_sources_t Cy_SysClk_ClkPathGetSource(uint32_t clkPath) @@ -406,7 +444,7 @@ cy_en_clkpath_in_sources_t Cy_SysClk_ClkPathGetSource(uint32_t clkPath) * the FLL is the source of CLK_HF0 and the FLL frequency is decreasing. * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_FllConfigure +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_FllConfigure * *******************************************************************************/ cy_en_sysclk_status_t Cy_SysClk_FllConfigure(uint32_t inputFreq, uint32_t outputFreq, cy_en_fll_pll_output_mode_t outputMode) @@ -444,17 +482,17 @@ cy_en_sysclk_status_t Cy_SysClk_FllConfigure(uint32_t inputFreq, uint32_t output /* 4. Compute the FLL reference divider value. refDiv is a constant if the WCO is the FLL source, otherwise the formula is refDiv = ROUNDUP((inputFreq / outputFreq) * 250) */ - config.refDiv = wcoSource ? 19U : (uint16_t)CY_SYSCLK_DIV_ROUNDUP((uint64_t)inputFreq * 250ULL, (uint64_t)outputFreq); + config.refDiv = wcoSource ? 19U : (uint16_t)CY_SYSLIB_DIV_ROUNDUP((uint64_t)inputFreq * 250ULL, (uint64_t)outputFreq); /* 5. Compute the FLL multiplier value. Formula is fllMult = ccoFreq / (inputFreq / refDiv) */ - config.fllMult = (uint32_t)CY_SYSCLK_DIV_ROUNDUP((uint64_t)ccoFreq * (uint64_t)config.refDiv, (uint64_t)inputFreq); + config.fllMult = (uint32_t)CY_SYSLIB_DIV_ROUNDUP((uint64_t)ccoFreq * (uint64_t)config.refDiv, (uint64_t)inputFreq); /* 6. Compute the lock tolerance. Formula is lock tolerance = 1.5 * fllMult * (((1 + CCO accuracy) / (1 - source clock accuracy)) - 1) We assume CCO accuracy is 0.25%. We assume the source clock accuracy = 1%. This is the accuracy of the IMO. Therefore the formula is lock tolerance = 1.5 * fllMult * 0.012626 = 0.018939 * fllMult */ - config.lockTolerance = (uint16_t)CY_SYSCLK_DIV_ROUNDUP(config.fllMult * 18939UL, 1000000UL); + config.lockTolerance = (uint16_t)CY_SYSLIB_DIV_ROUNDUP(config.fllMult * 18939UL, 1000000UL); { /* constants indexed by ccoRange */ @@ -464,7 +502,7 @@ cy_en_sysclk_status_t Cy_SysClk_FllConfigure(uint32_t inputFreq, uint32_t output { /* intermediate parameters */ uint32_t kcco = (trimSteps[config.ccoRange] * margin[config.ccoRange]); - uint32_t ki_p = (uint32_t)CY_SYSCLK_DIV_ROUND(850ULL * CY_SYSCLK_FLL_INT_COEF * inputFreq, (uint64_t)kcco * (uint64_t)config.refDiv); + uint32_t ki_p = (uint32_t)CY_SYSLIB_DIV_ROUND(850ULL * CY_SYSCLK_FLL_INT_COEF * inputFreq, (uint64_t)kcco * (uint64_t)config.refDiv); /* find the largest IGAIN value that is less than or equal to ki_p */ uint32_t locigain = CY_SYSCLK_FLL_GAIN_VAL; @@ -496,7 +534,7 @@ cy_en_sysclk_status_t Cy_SysClk_FllConfigure(uint32_t inputFreq, uint32_t output /* 8. Compute the CCO_FREQ bits in CLK_FLL_CONFIG4 register */ { - uint64_t cmp = CY_SYSCLK_DIV_ROUND(((TRIM_STEPS_SCALE / MARGIN_SCALE) * (uint64_t)ccoFreq), (uint64_t)margin[config.ccoRange]); + uint64_t cmp = CY_SYSLIB_DIV_ROUND(((TRIM_STEPS_SCALE / MARGIN_SCALE) * (uint64_t)ccoFreq), (uint64_t)margin[config.ccoRange]); uint64_t mlt = TRIM_STEPS_SCALE + (uint64_t)trimSteps[config.ccoRange]; uint64_t res = mlt; @@ -513,9 +551,9 @@ cy_en_sysclk_status_t Cy_SysClk_FllConfigure(uint32_t inputFreq, uint32_t output /* 9. Compute the settling count, using a 1 usec settling time. Use a constant if the WCO is the FLL source */ { - uint64_t fref = CY_SYSCLK_DIV_ROUND(6000ULL * (uint64_t)inputFreq, (uint64_t)config.refDiv); - uint32_t divval = CY_SYSCLK_DIV_ROUNDUP(inputFreq, 1000000UL); - uint32_t altval = (uint32_t)CY_SYSCLK_DIV_ROUNDUP((uint64_t)divval * fref, 6000000ULL) + 1UL; + uint64_t fref = CY_SYSLIB_DIV_ROUND(6000ULL * (uint64_t)inputFreq, (uint64_t)config.refDiv); + uint32_t divval = CY_SYSLIB_DIV_ROUNDUP(inputFreq, 1000000UL); + uint32_t altval = (uint32_t)CY_SYSLIB_DIV_ROUNDUP((uint64_t)divval * fref, 6000000ULL) + 1UL; config.settlingCount = wcoSource ? 200U : (uint16_t) ((outputFreq < fref) ? divval : @@ -566,7 +604,7 @@ cy_en_sysclk_status_t Cy_SysClk_FllConfigure(uint32_t inputFreq, uint32_t output * the FLL is the source of CLK_HF0 and the FLL frequency is decreasing. * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_FllManualConfigure +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_FllManualConfigure * *******************************************************************************/ cy_en_sysclk_status_t Cy_SysClk_FllManualConfigure(const cy_stc_fll_manual_config_t *config) @@ -576,7 +614,7 @@ cy_en_sysclk_status_t Cy_SysClk_FllManualConfigure(const cy_stc_fll_manual_confi /* Check for errors */ CY_ASSERT_L1(config != NULL); - if (!_FLD2BOOL(SRSS_CLK_FLL_CONFIG_FLL_ENABLE, SRSS_CLK_FLL_CONFIG)) /* If disabled */ + if (!Cy_SysClk_FllIsEnabled()) /* If disabled */ { /* update CLK_FLL_CONFIG register with 2 parameters; FLL_ENABLE is already 0 */ /* asserts just check for bitfield overflow */ @@ -627,7 +665,7 @@ cy_en_sysclk_status_t Cy_SysClk_FllManualConfigure(const cy_stc_fll_manual_confi * \param config \ref cy_stc_fll_manual_config_t * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_FllGetConfiguration +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_FllGetConfiguration * *******************************************************************************/ void Cy_SysClk_FllGetConfiguration(cy_stc_fll_manual_config_t *config) @@ -680,7 +718,7 @@ void Cy_SysClk_FllGetConfiguration(cy_stc_fll_manual_config_t *config) * the FLL is the source of CLK_HF0 and the CLK_HF0 frequency is increasing. * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_FllEnable +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_FllEnable * *******************************************************************************/ cy_en_sysclk_status_t Cy_SysClk_FllEnable(uint32_t timeoutus) @@ -815,7 +853,7 @@ cy_en_sysclk_status_t Cy_SysClk_FllEnable(uint32_t timeoutus) * the PLL is the source of CLK_HF0 and the PLL frequency is decreasing. * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_PllConfigure +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PllConfigure * *******************************************************************************/ cy_en_sysclk_status_t Cy_SysClk_PllConfigure(uint32_t clkPath, const cy_stc_pll_config_t *config) @@ -830,13 +868,9 @@ cy_en_sysclk_status_t Cy_SysClk_PllConfigure(uint32_t clkPath, const cy_stc_pll_ else { cy_stc_pll_manual_config_t manualConfig; - manualConfig.feedbackDiv = 0U; - manualConfig.referenceDiv = 0U; - manualConfig.outputDiv = 0U; - /* If output mode is bypass (input routed directly to output), then done. - The output frequency equals the input frequency regardless of the - frequency parameters. */ + /* If output mode is not bypass (input routed directly to output), then + calculate new parameters. */ if (config->outputMode != CY_SYSCLK_FLLPLL_OUTPUT_INPUT) { /* for each possible value of OUTPUT_DIV and REFERENCE_DIV (Q), try @@ -874,10 +908,18 @@ cy_en_sysclk_status_t Cy_SysClk_PllConfigure(uint32_t clkPath, const cy_stc_pll_ } } /* exit loops if foutBest equals outputFreq */ + + manualConfig.lfMode = config->lfMode; } /* if not, bypass output mode */ + /* If output mode is bypass (input routed directly to output), then + use old parameters. */ + else + { + (void)Cy_SysClk_PllGetConfiguration(clkPath, &manualConfig); + } /* configure PLL based on calculated values */ - manualConfig.lfMode = config->lfMode; + manualConfig.outputMode = config->outputMode; retVal = Cy_SysClk_PllManualConfigure(clkPath, &manualConfig); @@ -922,19 +964,19 @@ cy_en_sysclk_status_t Cy_SysClk_PllConfigure(uint32_t clkPath, const cy_stc_pll_ * the PLL is the source of CLK_HF0 and the PLL frequency is decreasing. * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_PllManualConfigure +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PllManualConfigure * *******************************************************************************/ cy_en_sysclk_status_t Cy_SysClk_PllManualConfigure(uint32_t clkPath, const cy_stc_pll_manual_config_t *config) { cy_en_sysclk_status_t retVal = CY_SYSCLK_SUCCESS; - clkPath--; /* to correctly access PLL config registers structure */ + /* check for errors */ - if (clkPath >= CY_SRSS_NUM_PLL) /* invalid clock path number */ + if (clkPath > CY_SRSS_NUM_PLL) /* invalid clock path number */ { retVal = CY_SYSCLK_BAD_PARAM; } - else if (_FLD2BOOL(SRSS_CLK_PLL_CONFIG_ENABLE, SRSS_CLK_PLL_CONFIG[clkPath])) + else if (Cy_SysClk_PllIsEnabled(clkPath)) { retVal = CY_SYSCLK_INVALID_STATE; } @@ -947,6 +989,7 @@ cy_en_sysclk_status_t Cy_SysClk_PllManualConfigure(uint32_t clkPath, const cy_st } else /* no errors */ { + clkPath--; /* to correctly access PLL config registers structure */ /* If output mode is bypass (input routed directly to output), then done. The output frequency equals the input frequency regardless of the frequency parameters. */ if (config->outputMode != CY_SYSCLK_FLLPLL_OUTPUT_INPUT) @@ -979,7 +1022,7 @@ cy_en_sysclk_status_t Cy_SysClk_PllManualConfigure(uint32_t clkPath, const cy_st * CY_SYSCLK_BAD_PARAM - invalid clock path number * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_PllGetConfiguration +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PllGetConfiguration * *******************************************************************************/ cy_en_sysclk_status_t Cy_SysClk_PllGetConfiguration(uint32_t clkPath, cy_stc_pll_manual_config_t *config) @@ -1029,12 +1072,13 @@ cy_en_sysclk_status_t Cy_SysClk_PllGetConfiguration(uint32_t clkPath, cy_stc_pll * the PLL is the source of CLK_HF0 and the CLK_HF0 frequency is decreasing. * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_PllEnable +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PllEnable * *******************************************************************************/ cy_en_sysclk_status_t Cy_SysClk_PllEnable(uint32_t clkPath, uint32_t timeoutus) { cy_en_sysclk_status_t retVal = CY_SYSCLK_BAD_PARAM; + bool nonZeroTimeout = (timeoutus != 0ul); clkPath--; /* to correctly access PLL config and status registers structures */ if (clkPath < CY_SRSS_NUM_PLL) { @@ -1048,7 +1092,7 @@ cy_en_sysclk_status_t Cy_SysClk_PllEnable(uint32_t clkPath, uint32_t timeoutus) { Cy_SysLib_DelayUs(1U); } - retVal = ((timeoutus == 0UL) ? CY_SYSCLK_TIMEOUT : CY_SYSCLK_SUCCESS); + retVal = ((nonZeroTimeout && (timeoutus == 0ul)) ? CY_SYSCLK_TIMEOUT : CY_SYSCLK_SUCCESS); } return (retVal); } @@ -1133,7 +1177,7 @@ static bool preventCounting = false; * the measured clock frequency may not be accurate. * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_StartClkMeasurementCounters +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_StartClkMeasurementCounters * *******************************************************************************/ cy_en_sysclk_status_t Cy_SysClk_StartClkMeasurementCounters(cy_en_meas_clks_t clock1, uint32_t count1, cy_en_meas_clks_t clock2) @@ -1320,11 +1364,11 @@ uint32_t Cy_SysClk_ClkMeasurementCountersGetFreq(bool measuredClock, uint32_t re { if (!measuredClock) { /* clock1 is the measured clock */ - retVal = (uint32_t)CY_SYSCLK_DIV_ROUND((uint64_t)clk1Count1 * (uint64_t)refClkFreq, (uint64_t)retVal); + retVal = (uint32_t)CY_SYSLIB_DIV_ROUND((uint64_t)clk1Count1 * (uint64_t)refClkFreq, (uint64_t)retVal); } else { /* clock2 is the measured clock */ - retVal = (uint32_t)CY_SYSCLK_DIV_ROUND((uint64_t)retVal * (uint64_t)refClkFreq, (uint64_t)clk1Count1); + retVal = (uint32_t)CY_SYSLIB_DIV_ROUND((uint64_t)retVal * (uint64_t)refClkFreq, (uint64_t)clk1Count1); } } else @@ -1360,14 +1404,14 @@ uint32_t Cy_SysClk_ClkMeasurementCountersGetFreq(bool measuredClock, uint32_t re * \note The watchdog timer (WDT) must be unlocked before calling this function. * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_IloTrim +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_IloTrim * *******************************************************************************/ /** \cond INTERNAL */ /* target frequency */ #define CY_SYSCLK_ILO_TARGET_FREQ (32768UL) /* Nominal trim step size is 1.5% of "the frequency". Using the target frequency */ -#define CY_SYSCLK_ILO_TRIM_STEP (CY_SYSCLK_DIV_ROUND(CY_SYSCLK_ILO_TARGET_FREQ * 15UL, 1000UL)) +#define CY_SYSCLK_ILO_TRIM_STEP (CY_SYSLIB_DIV_ROUND(CY_SYSCLK_ILO_TARGET_FREQ * 15UL, 1000UL)) /** \endcond */ int32_t Cy_SysClk_IloTrim(uint32_t iloFreq) @@ -1395,7 +1439,7 @@ int32_t Cy_SysClk_IloTrim(uint32_t iloFreq) /* Get current trim value */ uint32_t trim = _FLD2VAL(SRSS_CLK_TRIM_ILO_CTL_ILO_FTRIM, SRSS_CLK_TRIM_ILO_CTL); - diff = CY_SYSCLK_DIV_ROUND(diff, CY_SYSCLK_ILO_TRIM_STEP); + diff = CY_SYSLIB_DIV_ROUND(diff, CY_SYSCLK_ILO_TRIM_STEP); if(sign) { @@ -1425,7 +1469,7 @@ int32_t Cy_SysClk_IloTrim(uint32_t iloFreq) * \return Change in trim value; 0 if done, that is, no change in trim value. * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_PiloTrim +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PiloTrim * *******************************************************************************/ /** \cond INTERNAL */ @@ -1460,7 +1504,7 @@ int32_t Cy_SysClk_PiloTrim(uint32_t piloFreq) /* Get current trim value */ uint32_t trim = Cy_SysClk_PiloGetTrim(); - diff = CY_SYSCLK_DIV_ROUND(diff, CY_SYSCLK_PILO_TRIM_STEP); + diff = CY_SYSLIB_DIV_ROUND(diff, CY_SYSCLK_PILO_TRIM_STEP); if(sign) {/* piloFreq too low. Increase the trim value */ @@ -1550,7 +1594,7 @@ int32_t Cy_SysClk_PiloTrim(uint32_t piloFreq) * or PLL to get stable / regain its frequency lock. * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_DeepSleepCallback +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_DeepSleepCallback * *******************************************************************************/ cy_en_syspm_status_t Cy_SysClk_DeepSleepCallback(cy_stc_syspm_callback_params_t * callbackParams, cy_en_syspm_callback_mode_t mode) @@ -1596,8 +1640,7 @@ cy_en_syspm_status_t Cy_SysClk_DeepSleepCallback(cy_stc_syspm_callback_params_t for (fllpll = 0UL; fllpll <= CY_SRSS_NUM_PLL; fllpll++) { /* If FLL or PLL is enabled */ - if ((0UL == fllpll) ? (_FLD2BOOL(SRSS_CLK_FLL_CONFIG_FLL_ENABLE, SRSS_CLK_FLL_CONFIG)) : - (_FLD2BOOL(SRSS_CLK_PLL_CONFIG_ENABLE, SRSS_CLK_PLL_CONFIG[fllpll - 1UL]))) + if ((0UL == fllpll) ? Cy_SysClk_FllIsEnabled() : Cy_SysClk_PllIsEnabled(fllpll)) { /* And the FLL/PLL has ECO as a source */ if (Cy_SysClk_ClkPathGetSource(fllpll) == CY_SYSCLK_CLKPATH_IN_ECO) @@ -1710,7 +1753,7 @@ cy_en_syspm_status_t Cy_SysClk_DeepSleepCallback(cy_stc_syspm_callback_params_t } } } - else if (_FLD2BOOL(SRSS_CLK_FLL_CONFIG_FLL_ENABLE, SRSS_CLK_FLL_CONFIG)) + else if (Cy_SysClk_FllIsEnabled()) { /* Timeout wait for FLL to regain lock */ while ((!Cy_SysClk_FllLocked()) && (0UL != timeout)) @@ -1742,6 +1785,123 @@ cy_en_syspm_status_t Cy_SysClk_DeepSleepCallback(cy_stc_syspm_callback_params_t } /** \} group_sysclk_pm_funcs */ +/* ========================================================================== */ +/* ========================= clkHf[n] SECTION ========================= */ +/* ========================================================================== */ + +/** \cond INTERNAL */ +uint32_t altHfFreq = 0UL; /* Internal storage for BLE ECO frequency user setting */ +/** \endcond */ + +/** +* \addtogroup group_sysclk_clk_hf_funcs +* \{ +*/ + + +/******************************************************************************* +* Function Name: Cy_SysClk_ClkHfGetFrequency +****************************************************************************//** +* +* Reports the frequency of the selected clkHf +* +* \param clkHf Selects the clkHf +* +* \return The frequency, in Hz. +* +* \note +* The reported frequency may be zero, which indicates unknown. This happens if +* the source input is dsi_out or clk_altlf. +* +* \funcusage +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkHfSetDivider +* +*******************************************************************************/ +uint32_t Cy_SysClk_ClkHfGetFrequency(uint32_t clkHf) +{ + /* variables holding intermediate clock frequencies, dividers and FLL/PLL settings */ + bool enabled = false; /* FLL or PLL enable status; n/a for direct */ + uint32_t freq = 0UL; /* path (FLL, PLL, or direct) frequency, in Hz, 0 = unknown frequency */ + uint32_t fDiv = 0UL; /* FLL/PLL multiplier/feedback divider */ + uint32_t rDiv = 0UL; /* FLL/PLL reference divider */ + uint32_t oDiv = 0UL; /* FLL/PLL output divider */ + uint32_t pDiv = 1UL << (uint32_t)Cy_SysClk_ClkHfGetDivider(clkHf); /* root prescaler (1/2/4/8) */ + uint32_t path = (uint32_t) Cy_SysClk_ClkHfGetSource(clkHf); /* path input for root 0 (clkHf[0]) */ + cy_en_clkpath_in_sources_t source = Cy_SysClk_ClkPathGetSource((uint32_t)path); /* source input for path (FLL, PLL, or direct) */ + + /* get the frequency of the source, i.e., the path mux input */ + switch(source) + { + case CY_SYSCLK_CLKPATH_IN_IMO: /* IMO frequency is fixed at 8 MHz */ + freq = CY_SYSCLK_IMO_FREQ; + break; + + case CY_SYSCLK_CLKPATH_IN_EXT: + freq = extFreq; + break; + + case CY_SYSCLK_CLKPATH_IN_ECO: + freq = (CY_SYSCLK_ECOSTAT_STABLE == Cy_SysClk_EcoGetStatus()) ? ecoFreq : 0UL; + break; + + case CY_SYSCLK_CLKPATH_IN_ALTHF: + freq = altHfFreq; + break; + + case CY_SYSCLK_CLKPATH_IN_ILO: + freq = (0UL != (SRSS_CLK_ILO_CONFIG & SRSS_CLK_ILO_CONFIG_ENABLE_Msk)) ? CY_SYSCLK_ILO_FREQ : 0UL; + break; + + case CY_SYSCLK_CLKPATH_IN_WCO: + freq = (Cy_SysClk_WcoOkay()) ? CY_SYSCLK_WCO_FREQ : 0UL; + break; + + case CY_SYSCLK_CLKPATH_IN_PILO: + freq = (0UL != (SRSS_CLK_PILO_CONFIG & SRSS_CLK_PILO_CONFIG_PILO_EN_Msk)) ? CY_SYSCLK_PILO_FREQ : 0UL; + break; + + default: + /* don't know the frequency of dsi_out, or clk_altlf */ + freq = 0UL; /* unknown frequency */ + break; + } + + if (path == (uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH0) /* FLL? (always path 0) */ + { + cy_stc_fll_manual_config_t fllCfg = {0UL,0U,CY_SYSCLK_FLL_CCO_RANGE0,false,0U,0U,0U,0U,CY_SYSCLK_FLLPLL_OUTPUT_AUTO,0U}; + Cy_SysClk_FllGetConfiguration(&fllCfg); + enabled = (Cy_SysClk_FllIsEnabled()) && (CY_SYSCLK_FLLPLL_OUTPUT_INPUT != fllCfg.outputMode); + fDiv = fllCfg.fllMult; + rDiv = fllCfg.refDiv; + oDiv = (fllCfg.enableOutputDiv) ? 2UL : 1UL; + } + else if (path <= CY_SRSS_NUM_PLL) /* PLL? (always path 1...N)*/ + { + cy_stc_pll_manual_config_t pllcfg = {0U,0U,0U,false,CY_SYSCLK_FLLPLL_OUTPUT_AUTO}; + (void)Cy_SysClk_PllGetConfiguration(path, &pllcfg); + enabled = (Cy_SysClk_PllIsEnabled(path)) && (CY_SYSCLK_FLLPLL_OUTPUT_INPUT != pllcfg.outputMode); + fDiv = pllcfg.feedbackDiv; + rDiv = pllcfg.referenceDiv; + oDiv = pllcfg.outputDiv; + } + else + { + /* Direct select path */ + } + + if (enabled) /* if FLL or PLL enabled and not bypassed */ + { + freq = (uint32_t)CY_SYSLIB_DIV_ROUND(((uint64_t)freq * (uint64_t)fDiv), + ((uint64_t)rDiv * (uint64_t)oDiv)); + } + + /* Divide the path input frequency down and return the result */ + return (CY_SYSLIB_DIV_ROUND(freq, pDiv)); +} + +/** \} group_sysclk_clk_hf_funcs */ + + /* ========================================================================== */ /* ===================== clk_peripherals SECTION ====================== */ @@ -1766,110 +1926,48 @@ cy_en_syspm_status_t Cy_SysClk_DeepSleepCallback(cy_stc_syspm_callback_params_t * * \note * The reported frequency may be zero, which indicates unknown. This happens if -* the source input is clk_ext, ECO, clk_althf, dsi_out, or clk_altlf. +* the source input is dsi_out or clk_altlf. * * \funcusage -* \snippet sysclk/1.30/snippet/main.c snippet_Cy_SysClk_PeriphGetFrequency +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PeriphGetFrequency * *******************************************************************************/ uint32_t Cy_SysClk_PeriphGetFrequency(cy_en_divider_types_t dividerType, uint32_t dividerNum) { - /* variables holding intermediate clock frequencies, dividers and FLL/PLL settings */ - bool enabled = false; /* FLL or PLL enable status; n/a for direct */ - uint32_t freq = 0UL; /* path (FLL, PLL, or direct) frequency, in Hz, 0 = unknown frequency */ - uint32_t rootDiv = 0UL; /* root prescaler (1/2/4/8) */ - uint32_t periDiv = 0UL; /* predivider to clk_peri */ - uint32_t fDiv = 0UL; /* FLL/PLL multiplier/feedback divider */ - uint32_t rDiv = 0UL; /* FLL/PLL reference divider */ - uint32_t oDiv = 0UL; /* FLL/PLL output divider */ uint32_t integer = 0UL; /* Integer part of peripheral divider */ - uint32_t frac = 0UL; /* Fractional part of peripheral divider */ - cy_en_clkhf_in_sources_t path = Cy_SysClk_ClkHfGetSource(0UL); /* path input for root 0 (clkHf[0]) */ - cy_en_clkpath_in_sources_t source = Cy_SysClk_ClkPathGetSource((uint32_t)path); /* source input for path (FLL, PLL, or direct) */ + uint32_t freq = Cy_SysClk_ClkPeriGetFrequency(); /* Get Peri frequency */ CY_ASSERT_L1(((dividerType == CY_SYSCLK_DIV_8_BIT) && (dividerNum < PERI_DIV_8_NR)) || ((dividerType == CY_SYSCLK_DIV_16_BIT) && (dividerNum < PERI_DIV_16_NR)) || ((dividerType == CY_SYSCLK_DIV_16_5_BIT) && (dividerNum < PERI_DIV_16_5_NR)) || ((dividerType == CY_SYSCLK_DIV_24_5_BIT) && (dividerNum < PERI_DIV_24_5_NR))); - /* get the frequency of the source, i.e., the path mux input */ - switch(source) - { - case CY_SYSCLK_CLKPATH_IN_IMO: /* IMO frequency is fixed at 8 MHz */ - freq = CY_SYSCLK_IMO_FREQ; - break; - case CY_SYSCLK_CLKPATH_IN_ILO: /* ILO, WCO and PILO frequencies are nominally 32.768 kHz */ - case CY_SYSCLK_CLKPATH_IN_WCO: - case CY_SYSCLK_CLKPATH_IN_PILO: - freq = CY_SYSCLK_ILO_FREQ; - break; - default: - /* don't know the frequency of clk_ext, ECO, clk_althf, dsi_out, or clk_altlf */ - freq = 0UL; /* unknown frequency */ - break; - } - - if (path == CY_SYSCLK_CLKHF_IN_CLKPATH0) /* FLL? (always path 0) */ - { - cy_stc_fll_manual_config_t fllCfg = {0UL,0U,CY_SYSCLK_FLL_CCO_RANGE0,false,0U,0U,0U,0U,CY_SYSCLK_FLLPLL_OUTPUT_AUTO,0U}; - Cy_SysClk_FllGetConfiguration(&fllCfg); - enabled = (_FLD2BOOL(SRSS_CLK_FLL_CONFIG_FLL_ENABLE, SRSS_CLK_FLL_CONFIG)) && (fllCfg.outputMode != CY_SYSCLK_FLLPLL_OUTPUT_INPUT); - fDiv = fllCfg.fllMult; - rDiv = fllCfg.refDiv; - oDiv = (fllCfg.enableOutputDiv) ? 2UL : 1UL; - } - else if ((uint32_t)path <= CY_SRSS_NUM_PLL) /* PLL? (always path 1...N)*/ - { - cy_stc_pll_manual_config_t pllcfg = {0U,0U,0U,false,CY_SYSCLK_FLLPLL_OUTPUT_AUTO}; - (void)Cy_SysClk_PllGetConfiguration((uint32_t)path, &pllcfg); - enabled = (_FLD2BOOL(SRSS_CLK_PLL_CONFIG_ENABLE, SRSS_CLK_PLL_CONFIG[(uint32_t)path - 1UL])) && (pllcfg.outputMode != CY_SYSCLK_FLLPLL_OUTPUT_INPUT); - fDiv = pllcfg.feedbackDiv; - rDiv = pllcfg.referenceDiv; - oDiv = pllcfg.outputDiv; - } - else - { - /* Direct select path */ - } - - if (enabled) /* if FLL or PLL enabled and not bypassed */ - { - freq = (uint32_t)(((uint64_t)freq * (uint64_t)fDiv) / - ((uint64_t)rDiv * (uint64_t)oDiv)); - } - - /* get the prescaler value for root 0, or clkHf[0]: 1/2/4/8 */ - rootDiv = 1UL << (uint32_t)Cy_SysClk_ClkHfGetDivider(0UL); - - /* get the predivider value for clkHf[0] to clk_peri */ - periDiv = 1UL + (uint32_t)Cy_SysClk_ClkPeriGetDivider(); - - /* Divide the path input frequency down and return the result. - Stepping through the following code shows the frequency at each stage. - */ - freq /= (rootDiv * periDiv); /* clk_peri frequency */ - /* get the divider value for clk_peri to the selected peripheral clock */ switch(dividerType) { case CY_SYSCLK_DIV_8_BIT: case CY_SYSCLK_DIV_16_BIT: - integer = (uint32_t)Cy_SysClk_PeriphGetDivider(dividerType, dividerNum); - /* frac = 0 means it is an integer divider */ + integer = 1UL + Cy_SysClk_PeriphGetDivider(dividerType, dividerNum); + freq = CY_SYSLIB_DIV_ROUND(freq, integer); break; + case CY_SYSCLK_DIV_16_5_BIT: case CY_SYSCLK_DIV_24_5_BIT: - (void)Cy_SysClk_PeriphGetFracDivider(dividerType, dividerNum, &integer, &frac); + { + uint32_t locFrac; + uint32_t locDiv; + uint64_t locFreq = freq * 32ULL; + Cy_SysClk_PeriphGetFracDivider(dividerType, dividerNum, &integer, &locFrac); + /* For fractional dividers, the divider is (int + 1) + frac/32 */ + locDiv = ((1UL + integer) * 32UL) + locFrac; + freq = (uint32_t) CY_SYSLIB_DIV_ROUND(locFreq, (uint64_t)locDiv); + } break; + default: break; } - /* For fractional dividers, the divider is (int + 1) + frac/32. - * Use the fractional value to round the divider to the nearest integer. - */ - freq /= (integer + 1UL + ((frac >= 16UL) ? 1UL : 0UL)); /* peripheral divider output frequency */ - return (freq); } /** \} group_sysclk_clk_peripheral_funcs */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_sysint.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_sysint.c index e3fe447707..af8b9987e2 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_sysint.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_sysint.c @@ -48,7 +48,7 @@ * moved to __ramVectors in SRAM. Otherwise it is ignored. * * \funcusage -* \snippet sysint\1.20\snippet\main.c snippet_Cy_SysInt_Init +* \snippet sysint/snippet/main.c snippet_Cy_SysInt_Init * *******************************************************************************/ cy_en_sysint_status_t Cy_SysInt_Init(const cy_stc_sysint_t* config, cy_israddress userIsr) @@ -107,7 +107,7 @@ cy_en_sysint_status_t Cy_SysInt_Init(const cy_stc_sysint_t* config, cy_israddres * \note This function is available for CM0+ core only. * * \funcusage -* \snippet sysint\1.20\snippet\main.c snippet_Cy_SysInt_SetInterruptSource +* \snippet sysint/snippet/main.c snippet_Cy_SysInt_SetInterruptSource * *******************************************************************************/ void Cy_SysInt_SetInterruptSource(IRQn_Type IRQn, cy_en_intr_t devIntrSrc) @@ -150,7 +150,7 @@ void Cy_SysInt_SetInterruptSource(IRQn_Type IRQn, cy_en_intr_t devIntrSrc) * \note This function is available for CM0+ core only. * * \funcusage -* \snippet sysint\1.20\snippet\main.c snippet_Cy_SysInt_DisconnectInterruptSource +* \snippet sysint/snippet/main.c snippet_Cy_SysInt_DisconnectInterruptSource * *******************************************************************************/ void Cy_SysInt_DisconnectInterruptSource(IRQn_Type IRQn, cy_en_intr_t devIntrSrc) @@ -185,7 +185,7 @@ void Cy_SysInt_DisconnectInterruptSource(IRQn_Type IRQn, cy_en_intr_t devIntrSrc * other devices, use the Cy_SysInt_GetNvicConnection() function. * * \funcusage -* \snippet sysint\1.20\snippet\main.c snippet_Cy_SysInt_SetInterruptSource +* \snippet sysint/snippet/main.c snippet_Cy_SysInt_SetInterruptSource * *******************************************************************************/ cy_en_intr_t Cy_SysInt_GetInterruptSource(IRQn_Type IRQn) @@ -226,7 +226,7 @@ cy_en_intr_t Cy_SysInt_GetInterruptSource(IRQn_Type IRQn) * \note This function supports only devices using CPUSS_ver2 or higher. * * \funcusage -* \snippet sysint\1.20\snippet\main.c snippet_Cy_SysInt_SetInterruptSource +* \snippet sysint/snippet/main.c snippet_Cy_SysInt_SetInterruptSource * *******************************************************************************/ IRQn_Type Cy_SysInt_GetNvicConnection(cy_en_intr_t devIntrSrc) @@ -267,7 +267,7 @@ IRQn_Type Cy_SysInt_GetNvicConnection(cy_en_intr_t devIntrSrc) * \note This function supports only devices using CPUSS_ver2 or higher. * * \funcusage -* \snippet sysint\1.20\snippet\main.c snippet_Cy_SysInt_GetInterruptActive +* \snippet sysint/snippet/main.c snippet_Cy_SysInt_GetInterruptActive * *******************************************************************************/ cy_en_intr_t Cy_SysInt_GetInterruptActive(IRQn_Type IRQn) @@ -308,7 +308,7 @@ cy_en_intr_t Cy_SysInt_GetInterruptActive(IRQn_Type IRQn) * channel on the NVIC. * * \funcusage -* \snippet sysint\1.20\snippet\main.c snippet_Cy_SysInt_SetVector +* \snippet sysint/snippet/main.c snippet_Cy_SysInt_SetVector * *******************************************************************************/ cy_israddress Cy_SysInt_SetVector(IRQn_Type IRQn, cy_israddress userIsr) @@ -352,7 +352,7 @@ cy_israddress Cy_SysInt_SetVector(IRQn_Type IRQn, cy_israddress userIsr) * channel on the NVIC. * * \funcusage -* \snippet sysint\1.20\snippet\main.c snippet_Cy_SysInt_SetVector +* \snippet sysint/snippet/main.c snippet_Cy_SysInt_SetVector * *******************************************************************************/ cy_israddress Cy_SysInt_GetVector(IRQn_Type IRQn) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_syslib.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_syslib.c index 82487fc3ce..4f67b4d187 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_syslib.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_syslib.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_syslib.c -* \version 2.30 +* \version 2.40 * * Description: * Provides system API implementation for the SysLib driver. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_syspm.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_syspm.c index 7b3fa13216..8dbeb3ed63 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_syspm.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_syspm.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_syspm.c -* \version 4.10 +* \version 4.20 * * This driver provides the source code for API power management. * @@ -275,6 +275,9 @@ typedef void (*cy_cb_syspm_deep_sleep_t)(cy_en_syspm_waitfor_t waitFor, bool *wa /* Array of the callback roots */ static cy_stc_syspm_callback_t* pmCallbackRoot[CALLBACK_ROOT_NR] = {NULL, NULL, NULL, NULL, NULL}; +/* The array of the pointers to failed callback */ +static cy_stc_syspm_callback_t* failedCallback[CALLBACK_ROOT_NR] = {NULL, NULL, NULL, NULL, NULL}; + /* Structure for registers that should retain while Deep Sleep mode */ static cy_stc_syspm_backup_regs_t bkpRegs; @@ -294,7 +297,7 @@ static cy_stc_syspm_backup_regs_t bkpRegs; * The current power mode. See \ref group_syspm_return_status. * * \funcusage -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_ReadStatus +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_ReadStatus * *******************************************************************************/ uint32_t Cy_SysPm_ReadStatus(void) @@ -448,7 +451,7 @@ uint32_t Cy_SysPm_ReadStatus(void) * CM4 CPU after wakeup from WFE. * * \funcusage -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_CpuEnterSleep +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_CpuEnterSleep * *******************************************************************************/ cy_en_syspm_status_t Cy_SysPm_CpuEnterSleep(cy_en_syspm_waitfor_t waitFor) @@ -675,7 +678,7 @@ cy_en_syspm_status_t Cy_SysPm_CpuEnterSleep(cy_en_syspm_waitfor_t waitFor) * is settled prior executing the WFI/WFE instruction. * * \funcusage -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_CpuEnterDeepSleep +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_CpuEnterDeepSleep * *******************************************************************************/ cy_en_syspm_status_t Cy_SysPm_CpuEnterDeepSleep(cy_en_syspm_waitfor_t waitFor) @@ -900,7 +903,7 @@ cy_en_syspm_status_t Cy_SysPm_CpuEnterDeepSleep(cy_en_syspm_waitfor_t waitFor) * Entered status, see \ref cy_en_syspm_status_t. * * \funcusage -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_SystemEnterHibernate +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_SystemEnterHibernate * *******************************************************************************/ cy_en_syspm_status_t Cy_SysPm_SystemEnterHibernate(void) @@ -1042,7 +1045,7 @@ he LP mode * - CY_SYSPM_FAIL - The system LP mode is not entered. * * \funcusage -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_SystemEnterLp +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_SystemEnterLp * *******************************************************************************/ cy_en_syspm_status_t Cy_SysPm_SystemEnterLp(void) @@ -1184,7 +1187,7 @@ cy_en_syspm_status_t Cy_SysPm_SystemEnterLp(void) * - CY_SYSPM_FAIL - The system ULP mode is not entered. * * \funcusage -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_SystemEnterUlp +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_SystemEnterUlp * *******************************************************************************/ cy_en_syspm_status_t Cy_SysPm_SystemEnterUlp(void) @@ -1295,7 +1298,7 @@ cy_en_syspm_status_t Cy_SysPm_SystemEnterUlp(void) * current mode. * * \funcusage -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_SystemSetMinRegulatorCurrent +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_SystemSetMinRegulatorCurrent * *******************************************************************************/ cy_en_syspm_status_t Cy_SysPm_SystemSetMinRegulatorCurrent(void) @@ -1358,7 +1361,7 @@ cy_en_syspm_status_t Cy_SysPm_SystemSetMinRegulatorCurrent(void) * ready to enter into the normal regulator current mode * * \funcusage -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_SystemSetNormalRegulatorCurrent +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_SystemSetNormalRegulatorCurrent * *******************************************************************************/ cy_en_syspm_status_t Cy_SysPm_SystemSetNormalRegulatorCurrent(void) @@ -1431,7 +1434,7 @@ cy_en_syspm_status_t Cy_SysPm_SystemSetNormalRegulatorCurrent(void) * - False if disable sleep-on-exit feature. * * \funcusage -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_CpuSleepOnExit +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_CpuSleepOnExit * *******************************************************************************/ void Cy_SysPm_CpuSleepOnExit(bool enable) @@ -1503,7 +1506,7 @@ void Cy_SysPm_CpuSleepOnExit(bool enable) * Cy_SysPm_SetHibernateWakeupSource(CY_SYSPM_HIBERNATE_LPCOMP0_LOW, CY_SYSPM_HIBERNATE_LPCOMP0_HIGH); * * \funcusage -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_SetHibernateWakeupSource +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_SetHibernateWakeupSource * *******************************************************************************/ void Cy_SysPm_SetHibernateWakeupSource(uint32_t wakeupSource) @@ -1557,7 +1560,7 @@ void Cy_SysPm_SetHibernateWakeupSource(uint32_t wakeupSource) * Cy_SysPm_ClearHibernateWakeupSource(CY_SYSPM_HIBERNATE_LPCOMP0_HIGH | CY_SYSPM_HIBERNATE_WDT). * * \funcusage -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_ClearHibernateWakeupSource +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_ClearHibernateWakeupSource * *******************************************************************************/ void Cy_SysPm_ClearHibernateWakeupSource(uint32_t wakeupSource) @@ -1676,7 +1679,7 @@ void Cy_SysPm_ClearHibernateWakeupSource(uint32_t wakeupSource) * switch. * * \funcusage -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_BuckEnable +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_BuckEnable * *******************************************************************************/ cy_en_syspm_status_t Cy_SysPm_BuckEnable(cy_en_syspm_buck_voltage1_t voltage) @@ -1838,7 +1841,7 @@ cy_en_syspm_status_t Cy_SysPm_BuckEnable(cy_en_syspm_buck_voltage1_t voltage) * the function returns CY_SYSPM_SUCCESS. See \ref cy_en_syspm_status_t. * * \funcusage -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_VoltageRegulator +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_VoltageRegulator * *******************************************************************************/ cy_en_syspm_status_t Cy_SysPm_BuckSetVoltage1(cy_en_syspm_buck_voltage1_t voltage) @@ -1934,7 +1937,7 @@ cy_en_syspm_status_t Cy_SysPm_BuckSetVoltage1(cy_en_syspm_buck_voltage1_t voltag * - False if the requested output is disabled. * * \funcusage -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_BuckIsOutputEnabled +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_BuckIsOutputEnabled * *******************************************************************************/ bool Cy_SysPm_BuckIsOutputEnabled(cy_en_syspm_buck_out_t output) @@ -1986,7 +1989,7 @@ bool Cy_SysPm_BuckIsOutputEnabled(cy_en_syspm_buck_out_t output) * the SIMO Buck. * * \funcusage -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_BuckEnableVoltage2 +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_BuckEnableVoltage2 * *******************************************************************************/ void Cy_SysPm_BuckEnableVoltage2(void) @@ -2035,7 +2038,7 @@ void Cy_SysPm_BuckEnableVoltage2(void) * SIMO Buck. * * \funcusage -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_BuckSetVoltage2 +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_BuckSetVoltage2 * *******************************************************************************/ void Cy_SysPm_BuckSetVoltage2(cy_en_syspm_buck_voltage2_t voltage, bool waitToSettle) @@ -2124,7 +2127,7 @@ void Cy_SysPm_BuckSetVoltage2(cy_en_syspm_buck_voltage2_t voltage, bool waitToSe * the function returns CY_SYSPM_SUCCESS. See \ref cy_en_syspm_status_t. * * \funcusage -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_VoltageRegulator +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_VoltageRegulator * *******************************************************************************/ cy_en_syspm_status_t Cy_SysPm_LdoSetVoltage(cy_en_syspm_ldo_voltage_t voltage) @@ -2346,65 +2349,77 @@ cy_en_syspm_ldo_mode_t Cy_SysPm_LdoGetMode(void) * allocated during power mode transition. * * \funcusage -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_Callback_Func_Declaration -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_Callback_Params_Declaration -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_Callback_Structure_Declaration -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_Callback_Func_Implementation -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_RegisterCallback +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_Callback_Func_Declaration +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_Callback_Params_Declaration +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_Callback_Structure_Declaration +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_Callback_Func_Implementation +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_RegisterCallback * *******************************************************************************/ bool Cy_SysPm_RegisterCallback(cy_stc_syspm_callback_t* handler) { bool retVal = false; - /* Verify input */ + /* Verify the input parameters. */ if ((handler != NULL) && (handler->callbackParams != NULL) && (handler->callback != NULL)) { uint32_t callbackRootIdx = (uint32_t) handler->type; - retVal = true; - /* Get the required power mode root */ - cy_stc_syspm_callback_t* curCallback = pmCallbackRoot[callbackRootIdx]; - cy_stc_syspm_callback_t* lastRegCallback = NULL; - - /* Search last registered callback item */ - while (curCallback != NULL) + /* If the callback list is not empty. */ + if (pmCallbackRoot[callbackRootIdx] != NULL) { - if (curCallback == handler) + cy_stc_syspm_callback_t* curCallback = pmCallbackRoot[callbackRootIdx]; + cy_stc_syspm_callback_t* insertPos = curCallback; + + /* Find the callback after which the new callback is to be + * inserted. Ensure the given callback has not been registered. + */ + while ((NULL != curCallback->nextItm) && (curCallback != handler)) { - /* Do not register already registered callback item */ - retVal = false; - break; + curCallback = curCallback->nextItm; + /* Callbacks with the same order value are stored in the order + * they are registered. + */ + if (curCallback->order <= handler->order) + { + insertPos = curCallback; + } } + /* If the callback has not been registered. */ + if (curCallback != handler) + { + /* If the callback is to be inserted at the beginning of the list. */ + if ((insertPos->prevItm == NULL) && (handler->order < insertPos->order)) + { + handler->nextItm = insertPos; + handler->prevItm = NULL; + handler->nextItm->prevItm = handler; + pmCallbackRoot[callbackRootIdx] = handler; + } + else + { + handler->nextItm = insertPos->nextItm; + handler->prevItm = insertPos; - /* Safe callback before switching into the next item */ - lastRegCallback = curCallback; - - curCallback = curCallback->nextItm; + /* If the callback is not inserted at the end of the list. */ + if (handler->nextItm != NULL) + { + handler->nextItm->prevItm = handler; + } + insertPos->nextItm = handler; + } + retVal = true; + } } - - /* Link requested callback item to the linked list */ - if (retVal) + else { - if (pmCallbackRoot[callbackRootIdx] == NULL) - { - /* Link first callback item to the linked list */ - pmCallbackRoot[callbackRootIdx] = handler; - } - else - { - /* Link requested item to previous item */ - lastRegCallback->nextItm = handler; - } - - /* Update links to next and previous callback items of requested - * callback item - */ - handler->prevItm = lastRegCallback; + /* The callback list is empty. */ + pmCallbackRoot[callbackRootIdx] = handler; handler->nextItm = NULL; + handler->prevItm = NULL; + retVal = true; } } - return retVal; } @@ -2426,7 +2441,7 @@ bool Cy_SysPm_RegisterCallback(cy_stc_syspm_callback_t* handler) * - False if it was not unregistered or no callbacks are registered. * * \funcusage -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_UnregisterCallback +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_UnregisterCallback * *******************************************************************************/ bool Cy_SysPm_UnregisterCallback(cy_stc_syspm_callback_t const *handler) @@ -2526,7 +2541,7 @@ bool Cy_SysPm_UnregisterCallback(cy_stc_syspm_callback_t const *handler) * - CY_SYSPM_FAIL one of the executed callback(s) returned fail. * * \funcusage -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_ExecuteCallback +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_ExecuteCallback * *******************************************************************************/ cy_en_syspm_status_t Cy_SysPm_ExecuteCallback(cy_en_syspm_callback_type_t type, cy_en_syspm_callback_mode_t mode) @@ -2566,6 +2581,23 @@ cy_en_syspm_status_t Cy_SysPm_ExecuteCallback(cy_en_syspm_callback_type_t type, } curCallback = curCallback->nextItm; } + + if (mode == CY_SYSPM_CHECK_READY) + { + /* Update the pointer to the failed callback with the result of the callback execution. + * If the callback fails, the value of the pointer will be updated + * with the address of the callback which returned CY_SYSPM_FAIL, else, + * it will be updated with NULL. + */ + if(retVal == CY_SYSPM_FAIL) + { + failedCallback[(uint32_t) type] = lastExecutedCallback; + } + else + { + failedCallback[(uint32_t) type] = NULL; + } + } } else { @@ -2615,6 +2647,37 @@ cy_en_syspm_status_t Cy_SysPm_ExecuteCallback(cy_en_syspm_callback_type_t type, } +/******************************************************************************* +* Function Name: Cy_SysPm_GetFailedCallback +****************************************************************************//** +* +* Reads the result of the callback execution after the power mode functions +* execution. +* +* This function reads the value of the pointer that stores the result of callback +* execution. It takes power mode as the parameter and returns the address of the +* callback configuration structure in the case of failure or NULL in the case of +* success. This address of the failed callback allows finding the callback that +* blocks entering power mode. +* +* \param type +* Power mode for which a callback execution result is required. +* +* \return +* - The address of the callback configuration structure if the callback handler +* function failed. +* - NULL if the callback skipped or executed successfully. +* +* \funcusage +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_GetFailedCallback +* +*******************************************************************************/ +cy_stc_syspm_callback_t* Cy_SysPm_GetFailedCallback(cy_en_syspm_callback_type_t type) +{ + return failedCallback[(uint32_t) type]; +} + + /******************************************************************************* * Function Name: Cy_SysPm_IoUnfreeze ****************************************************************************//** @@ -2635,7 +2698,7 @@ cy_en_syspm_status_t Cy_SysPm_ExecuteCallback(cy_en_syspm_callback_type_t type, * configuration becomes effective only after the pins are unfrozen. * * \funcusage -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_IoUnfreeze +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_IoUnfreeze * *******************************************************************************/ void Cy_SysPm_IoUnfreeze(void) @@ -2680,7 +2743,7 @@ void Cy_SysPm_IoUnfreeze(void) * the function returns CY_SYSPM_SUCCESS. See \ref cy_en_syspm_status_t. * * \funcusage -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_WriteVoltageBitForFlash +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_WriteVoltageBitForFlash * *******************************************************************************/ cy_en_syspm_status_t Cy_SysPm_WriteVoltageBitForFlash(cy_en_syspm_flash_voltage_bit_t value) @@ -2765,7 +2828,7 @@ cy_en_syspm_status_t Cy_SysPm_WriteVoltageBitForFlash(cy_en_syspm_flash_voltage_ * The structure where the registers are saved. * * \funcusage -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_SaveRestoreRegisters +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_SaveRestoreRegisters * *******************************************************************************/ void Cy_SysPm_SaveRegisters(cy_stc_syspm_backup_regs_t *regs) @@ -2805,7 +2868,7 @@ void Cy_SysPm_SaveRegisters(cy_stc_syspm_backup_regs_t *regs) * required non-retained registers after Deep Sleep. * * \funcusage -* \snippet syspm/4.0/snippet/main.c snippet_Cy_SysPm_SaveRestoreRegisters +* \snippet syspm/snippet/main.c snippet_Cy_SysPm_SaveRestoreRegisters * *******************************************************************************/ void Cy_SysPm_RestoreRegisters(cy_stc_syspm_backup_regs_t const *regs) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_tcpwm_counter.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_tcpwm_counter.c index 333da1d726..f211f6d8eb 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_tcpwm_counter.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_tcpwm_counter.c @@ -50,8 +50,8 @@ extern "C" { * \return error / status code. See \ref cy_en_tcpwm_status_t. * * \funcusage -* \snippet tcpwm\1.10\counter\snippet\main.c snippet_Cy_TCPWM_Counter_Config -* \snippet tcpwm\1.10\counter\snippet\main.c snippet_Cy_TCPWM_Counter_Init +* \snippet tcpwm/counter/snippet/main.c snippet_Cy_TCPWM_Counter_Config +* \snippet tcpwm/counter/snippet/main.c snippet_Cy_TCPWM_Counter_Init * *******************************************************************************/ cy_en_tcpwm_status_t Cy_TCPWM_Counter_Init(TCPWM_Type *base, uint32_t cntNum, @@ -129,7 +129,7 @@ cy_en_tcpwm_status_t Cy_TCPWM_Counter_Init(TCPWM_Type *base, uint32_t cntNum, * The pointer to configuration structure. See \ref cy_stc_tcpwm_counter_config_t. * * \funcusage -* \snippet tcpwm\1.10\counter\snippet\main.c snippet_Cy_TCPWM_Counter_DeInit +* \snippet tcpwm/counter/snippet/main.c snippet_Cy_TCPWM_Counter_DeInit * *******************************************************************************/ void Cy_TCPWM_Counter_DeInit(TCPWM_Type *base, uint32_t cntNum, cy_stc_tcpwm_counter_config_t const *config) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_tcpwm_pwm.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_tcpwm_pwm.c index bb77dfd139..852963a655 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_tcpwm_pwm.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_tcpwm_pwm.c @@ -50,8 +50,8 @@ extern "C" { * \return error / status code. See \ref cy_en_tcpwm_status_t. * * \funcusage -* \snippet tcpwm\1.10\pwm\snippet\main.c snippet_Cy_TCPWM_PWM_Config -* \snippet tcpwm\1.10\pwm\snippet\main.c snippet_Cy_TCPWM_PWM_Init +* \snippet tcpwm/pwm/snippet/main.c snippet_Cy_TCPWM_PWM_Config +* \snippet tcpwm/pwm/snippet/main.c snippet_Cy_TCPWM_PWM_Init * *******************************************************************************/ cy_en_tcpwm_status_t Cy_TCPWM_PWM_Init(TCPWM_Type *base, uint32_t cntNum, cy_stc_tcpwm_pwm_config_t const *config) @@ -140,7 +140,7 @@ cy_en_tcpwm_status_t Cy_TCPWM_PWM_Init(TCPWM_Type *base, uint32_t cntNum, cy_st * The pointer to a configuration structure. See \ref cy_stc_tcpwm_pwm_config_t. * * \funcusage -* \snippet tcpwm\1.10\pwm\snippet\main.c snippet_Cy_TCPWM_PWM_DeInit +* \snippet tcpwm/pwm/snippet/main.c snippet_Cy_TCPWM_PWM_DeInit * *******************************************************************************/ void Cy_TCPWM_PWM_DeInit(TCPWM_Type *base, uint32_t cntNum, cy_stc_tcpwm_pwm_config_t const *config) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_tcpwm_quaddec.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_tcpwm_quaddec.c index 85f57ceb11..9d345eb5e8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_tcpwm_quaddec.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_tcpwm_quaddec.c @@ -50,8 +50,8 @@ extern "C" { * \return error / status code. See \ref cy_en_tcpwm_status_t. * * \funcusage -* \snippet tcpwm\1.10\quaddec\snippet\main.c snippet_Cy_TCPWM_QuadDec_Config -* \snippet tcpwm\1.10\quaddec\snippet\main.c snippet_Cy_TCPWM_QuadDec_Init +* \snippet tcpwm/quaddec/snippet/main.c snippet_Cy_TCPWM_QuadDec_Config +* \snippet tcpwm/quaddec/snippet/main.c snippet_Cy_TCPWM_QuadDec_Init * *******************************************************************************/ cy_en_tcpwm_status_t Cy_TCPWM_QuadDec_Init(TCPWM_Type *base, uint32_t cntNum, @@ -104,7 +104,7 @@ cy_en_tcpwm_status_t Cy_TCPWM_QuadDec_Init(TCPWM_Type *base, uint32_t cntNum, * The pointer to a configuration structure. See \ref cy_stc_tcpwm_quaddec_config_t. * * \funcusage -* \snippet tcpwm\1.10\quaddec\snippet\main.c snippet_Cy_TCPWM_QuadDec_DeInit +* \snippet tcpwm/quaddec/snippet/main.c snippet_Cy_TCPWM_QuadDec_DeInit * *******************************************************************************/ void Cy_TCPWM_QuadDec_DeInit(TCPWM_Type *base, uint32_t cntNum, cy_stc_tcpwm_quaddec_config_t const *config) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_trigmux.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_trigmux.c index 5eb5784ae1..6956f61ef1 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_trigmux.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_trigmux.c @@ -92,7 +92,7 @@ * - CY_TRIGMUX_BAD_PARAM: Some parameter is invalid. * * \funcusage -* \snippet trigmux\1.20\snippet\main.c snippet_Cy_TrigMux_Connect +* \snippet trigmux/snippet/main.c snippet_Cy_TrigMux_Connect * *******************************************************************************/ cy_en_trigmux_status_t Cy_TrigMux_Connect(uint32_t inTrig, uint32_t outTrig, bool invert, en_trig_type_t trigType) @@ -151,7 +151,7 @@ cy_en_trigmux_status_t Cy_TrigMux_Connect(uint32_t inTrig, uint32_t outTrig, boo * - CY_TRIGMUX_BAD_PARAM: Some parameter is invalid. * * \funcusage -* \snippet trigmux\1.20\snippet\main.c snippet_Cy_TrigMux_Select +* \snippet trigmux/snippet/main.c snippet_Cy_TrigMux_Select * *******************************************************************************/ cy_en_trigmux_status_t Cy_TrigMux_Select(uint32_t outTrig, bool invert, en_trig_type_t trigType) @@ -201,7 +201,7 @@ cy_en_trigmux_status_t Cy_TrigMux_Select(uint32_t outTrig, bool invert, en_trig_ * - CY_TRIGMUX_BAD_PARAM: Some parameter is invalid. * * \funcusage -* \snippet trigmux\1.20\snippet\main.c snippet_Cy_TrigMux_Deselect +* \snippet trigmux/snippet/main.c snippet_Cy_TrigMux_Deselect * *******************************************************************************/ cy_en_trigmux_status_t Cy_TrigMux_Deselect(uint32_t outTrig) @@ -251,7 +251,7 @@ cy_en_trigmux_status_t Cy_TrigMux_Deselect(uint32_t outTrig) * - CY_TRIGMUX_BAD_PARAM: The outTrig parameter is invalid. * * \funcusage -* \snippet trigmux\1.20\snippet\main.c snippet_Cy_TrigMux_SetDebugFreeze +* \snippet trigmux/snippet/main.c snippet_Cy_TrigMux_SetDebugFreeze * *******************************************************************************/ cy_en_trigmux_status_t Cy_TrigMux_SetDebugFreeze(uint32_t outTrig, bool enable) @@ -322,7 +322,7 @@ cy_en_trigmux_status_t Cy_TrigMux_SetDebugFreeze(uint32_t outTrig, bool enable) * - CY_TRIGMUX_BAD_PARAM: Some parameter is invalid. * * \funcusage -* \snippet trigmux\1.20\snippet\main.c snippet_Cy_TrigMux_SwTrigger +* \snippet trigmux/snippet/main.c snippet_Cy_TrigMux_SwTrigger * *******************************************************************************/ cy_en_trigmux_status_t Cy_TrigMux_SwTrigger(uint32_t trigLine, uint32_t cycles) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_usbfs_dev_drv.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_usbfs_dev_drv.c index 9940ab3909..3dc72b8072 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_usbfs_dev_drv.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_usbfs_dev_drv.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_usbfs_dev_drv.c -* \version 1.10 +* \version 2.0 * * Provides general API implementation of the USBFS driver. * @@ -35,10 +35,10 @@ extern "C" { * Internal Constants *******************************************************************************/ -/* After suspend, disable wait 2 us per MKAD-172 */ +/* After suspend, disable wait 2 us */ #define WAIT_SUSPEND_DISABLE (2U) -/* The bus reset counter is driven by 100 kHz clock and detects bus reset +/* The bus reset counter is driven by the 100 kHz clock and detects a bus reset * condition after 100 us. */ #define BUS_RESET_PERIOD (10UL) @@ -60,6 +60,10 @@ static uint32_t ReadEp0Buffer (USBFS_Type const *base, uint8_t *buffer, uint32_t static void RestoreDeviceConfiguration(USBFS_Type *base, cy_stc_usbfs_dev_drv_context_t *context); +static void EndpointTransferComplete(USBFS_Type *base, uint32_t endpoint, + cy_stc_usbfs_dev_drv_endpoint_data_t *endpointData, + cy_stc_usbfs_dev_drv_context_t *context); + /******************************************************************************* * Function Name: Cy_USBFS_Dev_Drv_Init ****************************************************************************//** @@ -79,7 +83,7 @@ static void RestoreDeviceConfiguration(USBFS_Type *base, cy_stc_usbfs_dev_drv_co * modify anything in this structure. * * \return -* Status code of the function execution \ref cy_en_usbfs_dev_drv_status_t. +* The status code of the function execution \ref cy_en_usbfs_dev_drv_status_t. * *******************************************************************************/ cy_en_usbfs_dev_drv_status_t Cy_USBFS_Dev_Drv_Init(USBFS_Type *base, @@ -96,13 +100,13 @@ cy_en_usbfs_dev_drv_status_t Cy_USBFS_Dev_Drv_Init(USBFS_Type *base, CY_ASSERT_L3(CY_USBFS_DEV_DRV_IS_MODE_VALID(config->mode)); - /* Enable clock to mxusb IP */ + /* Enables clock to mxusb IP */ USBFS_DEV_USB_CLK_EN(base) = CY_USBFS_DEV_DRV_WRITE_ODD(USBFS_USBDEV_USB_CLK_EN_CSR_CLK_EN_Msk); - /* Clear register (except reserved): the IOMODE = 0 means usb IP controls the usb pins */ + /* Clears register (except reserved): the IOMODE = 0 means usb IP controls the usb pins */ USBFS_DEV_USBIO_CR1(base) = (USBFS_DEV_USBIO_CR1(base) & USBFS_USBDEV_USBIO_CR1_RESERVED_2_Msk); - /* Set number of clocks (divided version of Clk_Peri) to detect bus reset */ + /* Sets the number of clocks (divided version of Clk_Peri) to detect bus reset */ USBFS_DEV_BUS_RST_CNT(base) = BUS_RESET_PERIOD; /* Enable PHY detector and single-ended and differential receivers */ @@ -111,39 +115,39 @@ cy_en_usbfs_dev_drv_status_t Cy_USBFS_Dev_Drv_Init(USBFS_Type *base, USBFS_USBLPM_POWER_CTL_ENABLE_DMO_Msk); (void) USBFS_DEV_LPM_POWER_CTL(base); - /* Suspend clear sequence */ + /* Suspends a clear sequence */ Cy_SysLib_DelayUs(WAIT_SUSPEND_DISABLE); USBFS_DEV_LPM_POWER_CTL(base) &= ~USBFS_USBLPM_POWER_CTL_SUSPEND_Msk; (void) USBFS_DEV_LPM_POWER_CTL(base); - /* Clear register (except reserved) and enable IMO lock */ + /* Clears the register (except reserved) and enable IMO lock */ USBFS_DEV_CR1(base) = USBFS_USBDEV_CR1_ENABLE_LOCK_Msk | (USBFS_DEV_CR1(base) & USBFS_USBDEV_CR1_RESERVED_3_Msk); - /* Configure level selection (HI, MED, LO) for each interrupt source */ + /* Configures the level selection (HI, MED, LO) for each interrupt source */ USBFS_DEV_LPM_INTR_LVL_SEL(base) = config->intrLevelSel; - /* Enable interrupt sources: Bus Reset and EP0 */ + /* Enables the interrupt sources: Bus Reset and EP0 */ USBFS_DEV_LPM_INTR_SIE_MASK(base) = (USBFS_USBLPM_INTR_SIE_BUS_RESET_INTR_Msk | USBFS_USBLPM_INTR_SIE_EP0_INTR_Msk); - /* Clear LPM register (disable LPM response) */ + /* Clears the LPM register (disable LPM response) */ USBFS_DEV_LPM_LPM_CTL(base) = 0UL; if (config->enableLpm) { - /* Enable device to ACK LPM requests */ + /* Enables the device to ACK LPM requests */ USBFS_DEV_LPM_LPM_CTL(base) = (USBFS_USBLPM_LPM_CTL_LPM_EN_Msk | USBFS_USBLPM_LPM_CTL_LPM_ACK_RESP_Msk); } - /* Copy configuration in the context */ + /* Copies the configuration in the context */ context->mode = config->mode; context->useReg16 = (config->epAccess == CY_USBFS_DEV_DRV_USE_16_BITS_DR); context->epSharedBuf = config->epBuffer; context->epSharedBufSize = config->epBufferSize; - /* Initialize pointers to functions that work with data endpoint */ + /* Initializes the pointers to functions that work with data endpoint */ switch(config->mode) { case CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU: @@ -187,9 +191,9 @@ cy_en_usbfs_dev_drv_status_t Cy_USBFS_Dev_Drv_Init(USBFS_Type *base, } /* Configure DMA and store info about DMA channels */ - if (context->mode != CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU) + if (CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU != context->mode) { - retStatus = DmaInit(config, context); + retStatus = DmaInit(config, context); } return retStatus; @@ -254,23 +258,22 @@ void Cy_USBFS_Dev_Drv_DeInit(USBFS_Type *base, cy_stc_usbfs_dev_drv_context_t *c USBFS_DEV_SIE_EP_INT_EN(base) = 0UL; USBFS_DEV_SIE_EP_INT_SR(base) = 0UL; - for (endpoint = 0UL; endpoint < CY_USBFS_DEV_DRV_NUM_EPS_MAX; ++endpoint) { - /* Set SIE endpoint register into the default state */ + /* Sets the SIE endpoint register into the default state */ USBFS_DEV_SIE_EP_CR0(base, endpoint) = 0UL; USBFS_DEV_SIE_EP_CNT0(base, endpoint) = 0UL; USBFS_DEV_SIE_EP_CNT1(base, endpoint) = 0UL; - /* Set ARBITER endpoint register into the default state */ + /* Sets the ARBITER endpoint register into the default state */ USBFS_DEV_ARB_EP_CFG(base, endpoint) = 0UL; USBFS_DEV_ARB_EP_INT_EN(base, endpoint) = 0UL; USBFS_DEV_ARB_RW_WA16(base, endpoint) = 0UL; USBFS_DEV_ARB_RW_RA16(base, endpoint) = 0UL; } - /* Clean-up context callbacks */ + /* Cleans the context callbacks */ context->cbSof = NULL; context->cbLpm = NULL; @@ -288,7 +291,7 @@ void Cy_USBFS_Dev_Drv_DeInit(USBFS_Type *base, cy_stc_usbfs_dev_drv_context_t *c * Function Name: Cy_USBFS_Dev_Drv_Enable ****************************************************************************//** * -* Enable the USBFS Device operation. +* Enables the USBFS Device operation. * * \param base * The pointer to the USBFS instance. @@ -302,16 +305,16 @@ void Cy_USBFS_Dev_Drv_DeInit(USBFS_Type *base, cy_stc_usbfs_dev_drv_context_t *c *******************************************************************************/ void Cy_USBFS_Dev_Drv_Enable(USBFS_Type *base, cy_stc_usbfs_dev_drv_context_t const *context) { - /* Suppress a compiler warning about unused variables */ + /* Suppresses a compiler warning about unused variables */ (void) context; - /* Clear EP0 count register */ + /* Clears the EP0 count register */ USBFS_DEV_EP0_CNT(base) = CY_USBFS_DEV_DRV_WRITE_ODD(0UL); - /* Set EP0.CR: ACK Setup, NAK IN/OUT */ + /* Sets EP0.CR: ACK Setup, NAK IN/OUT */ USBFS_DEV_EP0_CR(base) = CY_USBFS_DEV_DRV_EP_CR_NAK_INOUT; - /* Enable D+ pull-up, the device appears on the bus */ + /* Enables D+ pull-up, the device appears on the bus */ USBFS_DEV_LPM_POWER_CTL(base) |= USBFS_USBLPM_POWER_CTL_DP_UP_EN_Msk; (void) USBFS_DEV_LPM_POWER_CTL(base); } @@ -335,17 +338,17 @@ void Cy_USBFS_Dev_Drv_Enable(USBFS_Type *base, cy_stc_usbfs_dev_drv_context_t co *******************************************************************************/ void Cy_USBFS_Dev_Drv_Disable(USBFS_Type *base, cy_stc_usbfs_dev_drv_context_t *context) { - /* Suppress a compiler warning about unused variables */ + /* Suppresses a compiler warning about unused variables */ (void) context; - /* Disable D+ pull-up */ + /* Disables D+ pull-up */ USBFS_DEV_LPM_POWER_CTL(base) &= ~USBFS_USBLPM_POWER_CTL_DP_UP_EN_Msk; (void) USBFS_DEV_LPM_POWER_CTL(base); - /* Disable device to respond to usb traffic */ + /* Disables the device to respond to usb traffic */ USBFS_DEV_CR0(base) &= ~USBFS_USBDEV_CR0_USB_ENABLE_Msk; - /* Disable DMA channels */ + /* Disables the DMA channels */ if (CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU != context->mode) { DmaDisable(context); @@ -421,69 +424,89 @@ static void SofIntrHandler(USBFS_Type *base, cy_stc_usbfs_dev_drv_context_t *con *******************************************************************************/ static void Ep0IntrHandler(USBFS_Type *base, cy_stc_usbfs_dev_drv_context_t *context) { - /* Read CR register */ - uint32_t ep0Cr = USBFS_DEV_EP0_CR(base); + /* Reads the CR register */ + uint32_t ep0Cr = Cy_USBFS_Dev_Drv_ReadEp0Mode(base); - /* Check whether packet was ACKed */ + /* Checks whether the packet was ACKed */ if (0U != (ep0Cr & USBFS_USBDEV_EP0_CR_ACKED_TXN_Msk)) { - bool updateCr0 = false; - - /* Check packet direction */ + /* Checks the packet direction */ if (_FLD2BOOL(USBFS_USBDEV_EP0_CR_SETUP_RCVD, ep0Cr)) { - /* Handle SETUP */ + /* A setup packet received */ + context->ep0CtrlState = CY_USBFS_DEV_DRV_EP0_CTRL_STATE_SETUP; + + /* Handles SETUP */ if (_FLD2VAL(USBFS_USBDEV_EP0_CR_MODE, ep0Cr) == CY_USBFS_DEV_DRV_EP_CR_NAK_INOUT) { - /* Try to unlock CR0 register: read and then write. + /* Tries to unlock the CR0 register: read and then write. * The success write clears 8-4 bits in the register. */ - ep0Cr = USBFS_DEV_EP0_CR(base); - USBFS_DEV_EP0_CR(base) = ep0Cr; + Cy_USBFS_Dev_Drv_WriteEp0Mode(base, ep0Cr); - /* Check whether CR0 register unlocked (bits cleared) */ - ep0Cr = USBFS_DEV_EP0_CR(base); + /* Checks whether the CR0 register unlocked (bits cleared) */ + ep0Cr = Cy_USBFS_Dev_Drv_ReadEp0Mode(base); if (false == _FLD2BOOL(USBFS_USBDEV_EP0_CR_SETUP_RCVD, ep0Cr)) { - /* Reset EP0 CNT register (data toggle 0) */ - context->ep0CntReg = 0UL; + /* Resets the EP0 data toggle */ + context->ep0DataToggle = 0U; - /* Call Device layer to service request */ + /* Calls Device layer to service a request */ context->ep0Setup(base, context); - - updateCr0 = true; + } + else + { + /* CR0 is still locked, sets an interrupt pending to retry */ + Cy_USBFS_Dev_Drv_SetSieInterrupt(base, USBFS_USBLPM_INTR_CAUSE_EP0_INTR_Msk); } } } - /* Handle IN */ + /* Handles IN */ else if (_FLD2BOOL(USBFS_USBDEV_EP0_CR_IN_RCVD, ep0Cr)) { - context->ep0In(base, context); - updateCr0 = true; + if (CY_USBFS_DEV_DRV_EP0_CTRL_STATE_DATA == context->ep0CtrlState) + { + /* Data stage: invokes a callback to proceed the control transfer */ + context->ep0In(base, context); + } + else if (CY_USBFS_DEV_DRV_EP0_CTRL_STATE_STATUS_IN == context->ep0CtrlState) + { + /* Sets an address after the Status stage completion */ + if (context->setAddress) + { + Cy_USBFS_Dev_Drv_SetDeviceAddress(base, context->address); + context->setAddress = false; + } + + /* Completes the control transfer */ + context->ep0CtrlState = CY_USBFS_DEV_DRV_EP0_CTRL_STATE_IDLE; + } + else if (CY_USBFS_DEV_DRV_EP0_CTRL_STATE_STATUS_OUT == context->ep0CtrlState) + { + /* Updates the CNT and CR registers to continue the IN/OUT transfer */ + Cy_USBFS_Dev_Drv_SetEp0Count (base, 0U, USBFS_USBDEV_EP0_CNT_DATA_TOGGLE_Msk); + Cy_USBFS_Dev_Drv_WriteEp0Mode(base, CY_USBFS_DEV_DRV_EP_CR_STATUS_OUT_ONLY); + + /* The transfer is completed */ + context->ep0CtrlState = CY_USBFS_DEV_DRV_EP0_CTRL_STATE_IDLE; + } + else + { + /* Nothing to handle in this state */ + } } + /* Handles OUT */ else if (_FLD2BOOL(USBFS_USBDEV_EP0_CR_OUT_RCVD, ep0Cr)) { - /* Handle OUT */ - context->ep0Out(base, context); - updateCr0 = true; + if (CY_USBFS_DEV_DRV_EP0_CTRL_STATE_DATA == context->ep0CtrlState) + { + /* Data stage: invokes a callback to proceed the control transfer */ + context->ep0Out(base, context); + } } else { - /* Do nothing - unknown source */ - } - - if (updateCr0) - { - /* Check whether CR0 register unlocked (bits are cleared) */ - ep0Cr = USBFS_DEV_EP0_CR(base); - - if (false == _FLD2BOOL(USBFS_USBDEV_EP0_CR_SETUP_RCVD, ep0Cr)) - { - /* Update count and mode registers */ - USBFS_DEV_EP0_CNT(base) = CY_USBFS_DEV_DRV_WRITE_ODD(context->ep0CntReg); - USBFS_DEV_EP0_CR(base) = context->ep0ModeReg; - USBFS_DEV_EP0_CR(base); - } + /* Does nothing - an unknown source */ } } } @@ -507,20 +530,27 @@ static void Ep0IntrHandler(USBFS_Type *base, cy_stc_usbfs_dev_drv_context_t *con *******************************************************************************/ static void BusResetIntrHandler(USBFS_Type *base, cy_stc_usbfs_dev_drv_context_t *context) { - /* Reset driver variables if any */ + /* Resets the driver variables if any */ /* Cypress ID# 293217: write CR0 when pull-up is enabled */ if (_FLD2BOOL(USBFS_USBLPM_POWER_CTL_DP_UP_EN, USBFS_DEV_LPM_POWER_CTL(base))) { - /* Pass event to the Device layer */ + /* Passes an event to the Device layer */ context->busReset(base, context); - /* Clear EP0 count register */ + /* Clears the EP0 count register */ USBFS_DEV_EP0_CNT(base) = CY_USBFS_DEV_DRV_WRITE_ODD(0UL); - /* Set EP0.CR: ACK Setup, NAK IN/OUT */ + /* Sets EP0.CR: ACK Setup, NAK IN/OUT */ USBFS_DEV_EP0_CR(base) = CY_USBFS_DEV_DRV_EP_CR_NAK_INOUT; + /* Resets the driver context variables into the default state */ + context->setAddress = false; + context->ep0CtrlState = CY_USBFS_DEV_DRV_EP0_CTRL_STATE_IDLE; + context->curBufAddr = 0U; + context->activeEpMask = 0U; + context->epAbortMask = 0U; + /* Enable device to responds to USB traffic with address 0 */ USBFS_DEV_CR0(base) = USBFS_USBDEV_CR0_USB_ENABLE_Msk; (void) USBFS_DEV_CR0(base); @@ -528,6 +558,76 @@ static void BusResetIntrHandler(USBFS_Type *base, cy_stc_usbfs_dev_drv_context_t } +/******************************************************************************* +* Function Name: EndpointTransferComplete +****************************************************************************//** +* +* Handles the endpoint transfer complete: updates the endpoint state, +* calls a transfer completion callback, handles the abort. +* +* \param base +* The pointer to the USBFS instance. +* +* \param endpoint +* The data endpoint index. +* +* \param endpointData +* The pointer to the endpoint data structure. +* +* \param context +* The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t +* allocated by the user. The structure is used during the USBFS Device +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. +* +*******************************************************************************/ +static void EndpointTransferComplete(USBFS_Type *base, uint32_t endpoint, + cy_stc_usbfs_dev_drv_endpoint_data_t *endpointData, + cy_stc_usbfs_dev_drv_context_t *context) +{ + /* Updates the toggle (exclude ISOC endpoints) */ + if (false == IS_EP_ISOC(endpointData->sieMode)) + { + endpointData->toggle ^= (uint8_t) USBFS_USBDEV_SIE_EP_DATA_TOGGLE_Msk; + } + + if (0U != (context->epAbortMask & EP2MASK(endpoint))) + { + /* Clears the endpoint abort: Do not invoke callback, the state was set to idle */ + context->epAbortMask &= (uint8_t) ~EP2MASK(endpoint); + } + else + { + /* Data has been transferred to the bus set-endpoint complete state */ + endpointData->state = CY_USB_DEV_EP_COMPLETED; + + /* Involves a callback if it is registered */ + if (NULL != endpointData->epComplete) + { + uint32_t errorType = 0UL; + + /* Checks transfer errors (detect by hardware) */ + if (0U != Cy_USBFS_Dev_Drv_GetSieEpError(base, endpoint)) + { + errorType = CY_USBFS_DEV_ENDPOINT_TRANSFER_ERROR; + } + + /* Checks the data toggle bit of current transfer (exclude ISOC endpoints) */ + if (false == IS_EP_ISOC(endpointData->sieMode)) + { + if (endpointData->toggle == Cy_USBFS_Dev_Drv_GetSieEpToggle(base, endpoint)) + { + errorType |= CY_USBFS_DEV_ENDPOINT_SAME_DATA_TOGGLE; + } + } + + /* Calls the endpoint complete callback */ + endpointData->epComplete(base, (uint32_t) endpointData->address, errorType, context); + } + } +} + + /******************************************************************************* * Function Name: ArbiterIntrHandler ****************************************************************************//** @@ -554,10 +654,10 @@ static void ArbiterIntrHandler(USBFS_Type *base, cy_stc_usbfs_dev_drv_context_t { if (0U != (intrMask & 0x01U)) { - /* Get endpoint enable interrupt sources */ + /* Get the endpoint enable interrupt sources */ uint32_t sourceMask = Cy_USBFS_Dev_Drv_GetArbEpInterruptStatusMasked(base, endpoint); - /* Get pointer to endpoint data */ + /* Gets the pointer to the endpoint data */ cy_stc_usbfs_dev_drv_endpoint_data_t *endpointData = &context->epPool[endpoint]; Cy_USBFS_Dev_Drv_ClearArbEpInterrupt(base, endpoint, sourceMask); @@ -569,8 +669,8 @@ static void ArbiterIntrHandler(USBFS_Type *base, cy_stc_usbfs_dev_drv_context_t { Cy_USBFS_Dev_Drv_ClearArbCfgEpInReady(base, endpoint); - /* Mode 2: notify the user that data has been copied into endpoint buffer. - * Mode 3: the endpoint pending state is set before in LoadInEndpointDmaAuto (no impact). + /* Mode 2: Notifies the LoadInEndpointDma function that data has been copied into the endpoint buffer. + * Mode 3: No impact, the endpoint pending state is set in LoadInEndpointDmaAuto before. */ endpointData->state = CY_USB_DEV_EP_PENDING; @@ -581,55 +681,27 @@ static void ArbiterIntrHandler(USBFS_Type *base, cy_stc_usbfs_dev_drv_context_t /* Mode 2: Handle DMA completion event for OUT endpoints */ if (0U != (sourceMask & USBFS_USBDEV_ARB_EP_DMA_GNT_Msk)) { - /* Notify the user that data has been copied from endpoint buffer */ + /* Notifies the ReadOutEndpointDma function that the data has been copied from endpoint buffer + * into the user buffer. + */ endpointData->state = CY_USB_DEV_EP_COMPLETED; } - /* Mode 3: Handle DMA completion event for OUT endpoints */ + /* Mode 3: Handles a DMA completion event for OUT endpoints */ if (0U != (sourceMask & USBFS_USBDEV_ARB_EP_DMA_TERMIN_Msk)) { - /* Set DMA channel to start new transfer */ + /* Sets a DMA channel to start a new transfer */ DmaOutEndpointRestore(endpointData); - /* Update toggle (exclude ISOC endpoints) */ - if (false == IS_EP_ISOC(endpointData->sieMode)) - { - endpointData->toggle ^= (uint8_t) USBFS_USBDEV_SIE_EP_DATA_TOGGLE_Msk; - } - - /* Set complete event and update data toggle */ - endpointData->state = CY_USB_DEV_EP_COMPLETED; - - /* Involve callback if registered */ - if (endpointData->epComplete != NULL) - { - uint32_t errorType = 0UL; - - /* Check transfer errors (detect by hardware) */ - if (0U != Cy_USBFS_Dev_Drv_GetSieEpError(base, endpoint)) - { - errorType |= CY_USBFS_DEV_ENDPOINT_TRANSFER_ERROR; - } - - /* Check data toggle bit of current transfer (exclude ISOC endpoints) */ - if (false == IS_EP_ISOC(endpointData->sieMode)) - { - if (endpointData->toggle == Cy_USBFS_Dev_Drv_GetSieEpToggle(base, endpoint)) - { - errorType |= CY_USBFS_DEV_ENDPOINT_SAME_DATA_TOGGLE; - } - } - - /* Call endpoint complete callback */ - endpointData->epComplete(base, errorType, context); - } + /* Completes an endpoint transfer */ + EndpointTransferComplete(base, endpoint, endpointData, context); } /* This error condition indicates system failure */ if (0U != (sourceMask & USBFS_USBDEV_ARB_EP_BUF_OVER_Msk)) { - /* The DMA is not capable of moving data from the mxusbfs IP - * hardware buffer fast enough and so caused overflow. Give DMA + /* The DMA cannot move the data from the mxusbfs IP + * hardware buffer fast enough and so caused an overflow. Give a DMA * channel for this endpoint greater priority or increase the clock * at which it operates. */ @@ -639,8 +711,8 @@ static void ArbiterIntrHandler(USBFS_Type *base, cy_stc_usbfs_dev_drv_context_t /* This error condition indicates system failure */ if (0U != (sourceMask & USBFS_USBDEV_ARB_EP_BUF_UNDER_Msk)) { - /* The DMA is not capable of moving data into the mxusbfs IP - * hardware buffer fast enough and so caused underflow. Give DMA + /* The DMA cannot move the data into the mxusbfs IP + * hardware buffer fast enough and so caused an underflow. Give a DMA * channel for this endpoint greater priority or increase the clock * at which it operates. */ @@ -648,7 +720,7 @@ static void ArbiterIntrHandler(USBFS_Type *base, cy_stc_usbfs_dev_drv_context_t } } - /* Move to next endpoint */ + /* Moves to a next endpoint */ intrMask >>= 1UL; ++endpoint; } @@ -678,56 +750,31 @@ static void ArbiterIntrHandler(USBFS_Type *base, cy_stc_usbfs_dev_drv_context_t static void SieEnpointIntrHandler(USBFS_Type *base, uint32_t endpoint, cy_stc_usbfs_dev_drv_context_t *context) { - bool inEnpoint; + bool modeDmaAuto; + bool inEndpoint; bool zeroLengthPacket; - /* Get pointer to endpoint data */ + /* Gets the pointer to endpoint data */ cy_stc_usbfs_dev_drv_endpoint_data_t *endpointData = &context->epPool[endpoint]; Cy_USBFS_Dev_Drv_ClearSieEpInterrupt(base, endpoint); - /* Special case: DMA Auto - * IN endpoints: complete transfer when SIE triggers complete. - * OUT endpoints complete transfer when DMA complete (Arbiter Interrupt, source DMA_TERMIN). - * In case of zero length packet complete transfer when SIE triggers complete. + /* + * DMA Auto requires special processing: + * IN endpoints: Updates the endpoint state here to complete the transfer (includes a zero-length packet). + * OUT endpoints: Updates the endpoint state in ArbiterIntrHandler when DMA is done to complete the transfer + * (interrupt source DMA_TERMIN). + * In the case of a zero-length packet, updates the endpoint state here to complete the transfer. + * Other modes (CPU mode and DMA mode): Updates the endpoint state here to complete the transfer for the IN and OUT endpoints. */ + modeDmaAuto = (CY_USBFS_DEV_DRV_EP_MANAGEMENT_DMA_AUTO == context->mode); + inEndpoint = CY_USBFS_DEV_DRV_IS_EP_DIR_IN(endpointData->address); zeroLengthPacket = (0U == Cy_USBFS_Dev_Drv_GetSieEpCount(base, endpoint)); - inEnpoint = (0U == (Cy_USBFS_Dev_Drv_GetArbEpInterruptMask(base, endpoint) & USBFS_USBDEV_ARB_EP_DMA_TERMIN_Msk)); - if (inEnpoint || zeroLengthPacket) + if ( (!modeDmaAuto) || + (modeDmaAuto && (inEndpoint || zeroLengthPacket)) ) { - /* Update toggle (exclude ISOC endpoints) */ - if (false == IS_EP_ISOC(endpointData->sieMode)) - { - endpointData->toggle ^= (uint8_t) USBFS_USBDEV_SIE_EP_DATA_TOGGLE_Msk; - } - - /* Set complete event and update data toggle */ - endpointData->state = CY_USB_DEV_EP_COMPLETED; - - /* Involve callback if it is registered */ - if (endpointData->epComplete != NULL) - { - uint32_t errorType = 0UL; - - /* Check transfer errors (detect by hardware) */ - if (0U != Cy_USBFS_Dev_Drv_GetSieEpError(base, endpoint)) - { - errorType |= CY_USBFS_DEV_ENDPOINT_TRANSFER_ERROR; - } - - /* Check data toggle bit of current transfer (exclude ISOC endpoints) */ - if (false == IS_EP_ISOC(endpointData->sieMode)) - { - if (endpointData->toggle == Cy_USBFS_Dev_Drv_GetSieEpToggle(base, endpoint)) - { - errorType |= CY_USBFS_DEV_ENDPOINT_SAME_DATA_TOGGLE; - } - } - - /* Call endpoint complete callback */ - endpointData->epComplete(base, errorType, context); - } + EndpointTransferComplete(base, endpoint, endpointData, context); } } @@ -736,7 +783,7 @@ static void SieEnpointIntrHandler(USBFS_Type *base, uint32_t endpoint, * Function Name: Cy_USBFS_Dev_Drv_Interrupt ****************************************************************************//** * -* Process interrupt events generated by the USBFS Device. +* Processes interrupt events generated by the USBFS Device. * The interrupts are mandatory for USBFS Device operation and this function * must be called inside the user-defined interrupt service routine. * @@ -760,57 +807,56 @@ static void SieEnpointIntrHandler(USBFS_Type *base, uint32_t endpoint, void Cy_USBFS_Dev_Drv_Interrupt(USBFS_Type *base, uint32_t intrCause, cy_stc_usbfs_dev_drv_context_t *context) { - uint32_t endpoint = 0u; + uint32_t endpoint = 0U; + uint32_t intrCauseEp; - /* Clear SIE interrupts while are served below */ + /* Clears the SIE interrupts while the below are served */ Cy_USBFS_Dev_Drv_ClearSieInterrupt(base, intrCause); /* LPM */ - if (0u != (intrCause & USBFS_USBLPM_INTR_CAUSE_LPM_INTR_Msk)) + if (0U != (intrCause & USBFS_USBLPM_INTR_CAUSE_LPM_INTR_Msk)) { LpmIntrHandler(base, context); } /* Arbiter: Data endpoints */ - if (0u != (intrCause & USBFS_USBLPM_INTR_CAUSE_ARB_EP_INTR_Msk)) + if (0U != (intrCause & USBFS_USBLPM_INTR_CAUSE_ARB_EP_INTR_Msk)) { /* This interrupt is cleared inside the handler */ ArbiterIntrHandler(base, context); } - /* Control EP0 */ - if (0u != (intrCause & USBFS_USBLPM_INTR_CAUSE_EP0_INTR_Msk)) - { - Ep0IntrHandler(base, context); - } - - /* SOF */ - if (0u != (intrCause & USBFS_USBLPM_INTR_CAUSE_SOF_INTR_Msk)) - { - SofIntrHandler(base, context); - } - - /* Bus Reset */ - if (0u != (intrCause & USBFS_USBLPM_INTR_CAUSE_BUS_RESET_INTR_Msk)) - { - BusResetIntrHandler(base, context); - } - - /* Remove handled interrupt statuses */ - intrCause >>= USBFS_USBLPM_INTR_CAUSE_EP1_INTR_Pos; - /* SIE: Data endpoints */ - while (0u != intrCause) + intrCauseEp = (intrCause >> USBFS_USBLPM_INTR_CAUSE_EP1_INTR_Pos); + while (0U != intrCauseEp) { - if (0u != (intrCause & 0x1u)) + if (0u != (intrCauseEp & 0x1U)) { /* These interrupts are cleared inside the handler */ SieEnpointIntrHandler(base, endpoint, context); } - intrCause >>= 1u; + intrCauseEp >>= 1U; ++endpoint; } + + /* SOF */ + if (0U != (intrCause & USBFS_USBLPM_INTR_CAUSE_SOF_INTR_Msk)) + { + SofIntrHandler(base, context); + } + + /* Controls EP0 */ + if (0U != (intrCause & USBFS_USBLPM_INTR_CAUSE_EP0_INTR_Msk)) + { + Ep0IntrHandler(base, context); + } + + /* Bus Reset */ + if (0U != (intrCause & USBFS_USBLPM_INTR_CAUSE_BUS_RESET_INTR_Msk)) + { + BusResetIntrHandler(base, context); + } } @@ -838,24 +884,16 @@ static uint32_t WriteEp0Buffer(USBFS_Type *base, uint8_t const *buffer, uint32_t { uint32_t idx; - /* Cut message size if too many bytes are requested to write */ + /* Cuts the message size if too many bytes are requested to write */ if (size > CY_USBFS_DEV_DRV_EP0_BUFFER_SIZE) { size = CY_USBFS_DEV_DRV_EP0_BUFFER_SIZE; } - /* Write data into the hardware buffer */ + /* Writes data into the hardware buffer */ for (idx = 0UL; idx < size; ++idx) { - if (0U == (idx & 0x1U)) - { - USBFS_DEV_EP0_DR(base, idx) = buffer[idx]; - } - else - { - /* Apply special write for odd offset registers */ - USBFS_DEV_EP0_DR(base, idx) = CY_USBFS_DEV_DRV_WRITE_ODD(buffer[idx]); - } + Cy_USBFS_Dev_Drv_WriteEp0Data(base, idx, (uint32_t) buffer[idx]); } return idx; @@ -885,27 +923,19 @@ static uint32_t ReadEp0Buffer(USBFS_Type const *base, uint8_t *buffer, uint32_t { uint32_t idx; - /* Get number of received bytes */ + /* Gets the number of received bytes */ uint32_t numToCopy = Cy_USBFS_Dev_Drv_GetEp0Count(base); - /* Read only received bytes */ + /* Reads received bytes only */ if (size > numToCopy) { size = numToCopy; } - /* Get data from the buffer */ + /* Gets the data from the buffer */ for (idx = 0UL; idx < size; ++idx) { - if (0U == (idx & 0x1U)) - { - buffer[idx] = (uint8_t) USBFS_DEV_EP0_DR(base, idx); - } - else - { - /* Apply special write for odd offset registers */ - buffer[idx] = (uint8_t) CY_USBFS_DEV_READ_ODD(USBFS_DEV_EP0_DR(base, idx)); - } + buffer[idx] = (uint8_t) Cy_USBFS_Dev_Drv_ReadEp0Data(base, idx); } return idx; @@ -916,7 +946,7 @@ static uint32_t ReadEp0Buffer(USBFS_Type const *base, uint8_t *buffer, uint32_t * Function Name: Cy_USBFS_Dev_Drv_Ep0GetSetup ****************************************************************************//** * -* Reads setup packed from Endpoint 0 hardware buffer. +* Reads the setup packed from the Endpoint 0 hardware buffer. * * \param base * The pointer to the USBFS instance. @@ -934,7 +964,7 @@ static uint32_t ReadEp0Buffer(USBFS_Type const *base, uint8_t *buffer, uint32_t void Cy_USBFS_Dev_Drv_Ep0GetSetup(USBFS_Type const *base, uint8_t *buffer, cy_stc_usbfs_dev_drv_context_t const *context) { - /* Suppress a compiler warning about unused variables */ + /* Suppresses a compiler warning about unused variables */ (void) context; (void) ReadEp0Buffer(base, buffer, CY_USBFS_DEV_DRV_EP0_BUFFER_SIZE); @@ -953,10 +983,11 @@ void Cy_USBFS_Dev_Drv_Ep0GetSetup(USBFS_Type const *base, uint8_t *buffer, * * \param buffer * The pointer to the buffer containing data bytes to write. +* To switch a transfer from the data stage to status, pass NULL as a pointer. * * \param size * The number of bytes to write. -* This value must be less than or equal to endpoint 0 maximum packet size. +* Setting the size to zero sends to the bus zero-length data packet. * * \param context * The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t @@ -969,31 +1000,38 @@ void Cy_USBFS_Dev_Drv_Ep0GetSetup(USBFS_Type const *base, uint8_t *buffer, * *******************************************************************************/ uint32_t Cy_USBFS_Dev_Drv_Ep0Write(USBFS_Type *base, uint8_t const *buffer, uint32_t size, - cy_stc_usbfs_dev_drv_context_t *context) + cy_stc_usbfs_dev_drv_context_t *context) { - CY_ASSERT_L1((size > 0U) ? (NULL != buffer) : true); - uint32_t numBytes = 0UL; - if (buffer != NULL) + if (NULL != buffer) { - /* DATA stage (IN direction): load data to be sent (include zero length packet) */ - - /* Put data into the buffer */ - numBytes = WriteEp0Buffer(base, buffer, size); + /* Data stage (IN): Loads data to be sent */ - /* Update data toggle and counter */ - context->ep0CntReg ^= USBFS_USBDEV_EP0_CNT_DATA_TOGGLE_Msk; - context->ep0CntReg = _CLR_SET_FLD32U(context->ep0CntReg, USBFS_USBDEV_EP0_CNT_BYTE_COUNT, numBytes); + /* Puts the data into the buffer */ + if (size > 0U) + { + numBytes = WriteEp0Buffer(base, buffer, size); + } + + /* Updates the data toggle and counter */ + context->ep0DataToggle ^= (uint8_t) USBFS_USBDEV_EP0_CNT_DATA_TOGGLE_Msk; - /* Update EP0 mode register to continue transfer */ - context->ep0ModeReg = CY_USBFS_DEV_DRV_EP_CR_ACK_IN_STATUS_OUT; + /* Updates the CNT and CR registers to continue the IN transfer */ + Cy_USBFS_Dev_Drv_SetEp0Count (base, numBytes, (uint32_t) context->ep0DataToggle); + Cy_USBFS_Dev_Drv_WriteEp0Mode(base, CY_USBFS_DEV_DRV_EP_CR_ACK_IN_STATUS_OUT); + + context->ep0CtrlState = CY_USBFS_DEV_DRV_EP0_CTRL_STATE_DATA; } else { - /* STATUS stage (IN direction): prepare return zero-length and get ACK response */ - context->ep0CntReg = USBFS_USBDEV_EP0_CNT_DATA_TOGGLE_Msk; - context->ep0ModeReg = CY_USBFS_DEV_DRV_EP_CR_STATUS_IN_ONLY; + /* Status stage (IN): Completes the status stage, sends an ACK handshake */ + + /* Updates the CNT and CR registers to continue the IN transfer */ + Cy_USBFS_Dev_Drv_SetEp0Count (base, numBytes, USBFS_USBDEV_EP0_CNT_DATA_TOGGLE_Msk); + Cy_USBFS_Dev_Drv_WriteEp0Mode(base, CY_USBFS_DEV_DRV_EP_CR_STATUS_IN_ONLY); + + context->ep0CtrlState = CY_USBFS_DEV_DRV_EP0_CTRL_STATE_STATUS_IN; } return numBytes; @@ -1004,7 +1042,7 @@ uint32_t Cy_USBFS_Dev_Drv_Ep0Write(USBFS_Type *base, uint8_t const *buffer, uint * Function Name: Cy_USBFS_Dev_Drv_Ep0Read ****************************************************************************//** * -* Reads data from Endpoint 0 hardware and returns how many bytes were read. +* Start receiving a packet into the Endpoint 0 hardware buffer. * * \param base * The pointer to the USBFS instance. @@ -1014,6 +1052,48 @@ uint32_t Cy_USBFS_Dev_Drv_Ep0Write(USBFS_Type *base, uint8_t const *buffer, uint * * \param size * The number of bytes to read. +* Reading zero bytes switch control transfer to status stage. +* +* \param context +* The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t +* allocated by the user. The structure is used during the USBFS Device +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. +* +*******************************************************************************/ +void Cy_USBFS_Dev_Drv_Ep0Read(USBFS_Type *base, uint8_t *buffer, uint32_t size, + cy_stc_usbfs_dev_drv_context_t *context) +{ + if (0U != size) + { + /* Data stage (OUT): Prepares to receive data */ + + /* Stores the Endpoint 0 buffer to put read operation results */ + context->ep0Buffer = buffer; + context->ep0BufferSize = (uint8_t) size; /* The Endpoint 0 max packet is 8 bytes */ + + /* Updates the CNT and CR registers to continue the OUT transfer */ + Cy_USBFS_Dev_Drv_SetEp0Count (base, 0U, 0U); + Cy_USBFS_Dev_Drv_WriteEp0Mode(base, CY_USBFS_DEV_DRV_EP_CR_ACK_OUT_STATUS_IN); + + context->ep0CtrlState = CY_USBFS_DEV_DRV_EP0_CTRL_STATE_DATA; + } + else + { + /* Status stage (OUT): prepare to complete status stage after IN transfer is finished */ + context->ep0CtrlState = CY_USBFS_DEV_DRV_EP0_CTRL_STATE_STATUS_OUT; + } +} + + +/******************************************************************************* +* Function Name: Cy_USBFS_Dev_Drv_Ep0ReadResult +****************************************************************************//** +* +* Reads data from the Endpoint 0 hardware and returns the number of read bytes. +* +* \param base +* The pointer to the USBFS instance. * * \param context * The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t @@ -1022,33 +1102,13 @@ uint32_t Cy_USBFS_Dev_Drv_Ep0Write(USBFS_Type *base, uint8_t const *buffer, uint * modify anything in this structure. * * \return -* The number of bytes which were read. +* The number of read bytes. * *******************************************************************************/ -uint32_t Cy_USBFS_Dev_Drv_Ep0Read(USBFS_Type const *base, uint8_t *buffer, uint32_t size, - cy_stc_usbfs_dev_drv_context_t *context) -{ - uint32_t numBytes = 0UL; - - if (buffer != NULL) - { - /* DATA stage (OUT direction): get receive data and continue */ - - /* Get received data */ - numBytes = ReadEp0Buffer(base, buffer, size); - - /* Update EP0 registers to continue transfer */ - context->ep0CntReg ^= USBFS_USBDEV_EP0_CNT_DATA_TOGGLE_Msk; - context->ep0ModeReg = CY_USBFS_DEV_DRV_EP_CR_ACK_OUT_STATUS_IN; - } - else - { - /* STATUS stage (OUT direction): prepare to send ACK handshake */ - context->ep0CntReg = USBFS_USBDEV_EP0_CNT_DATA_TOGGLE_Msk; - context->ep0ModeReg = CY_USBFS_DEV_DRV_EP_CR_STATUS_OUT_ONLY; - } - - return numBytes; +uint32_t Cy_USBFS_Dev_Drv_Ep0ReadResult(USBFS_Type const *base, cy_stc_usbfs_dev_drv_context_t *context) +{ + /* Stores received data to the buffer */ + return ReadEp0Buffer(base, context->ep0Buffer, (uint32_t) context->ep0BufferSize); } @@ -1076,7 +1136,7 @@ uint32_t Cy_USBFS_Dev_Drv_Ep0Read(USBFS_Type const *base, uint8_t *buffer, uint3 * modify anything in this structure. * * \return -* Status code of the function execution \ref cy_en_usbfs_dev_drv_status_t. +* The status code of the function execution \ref cy_en_usbfs_dev_drv_status_t. * *******************************************************************************/ void Cy_USBFS_Dev_Drv_RegisterServiceCallback(USBFS_Type const *base, @@ -1084,7 +1144,7 @@ void Cy_USBFS_Dev_Drv_RegisterServiceCallback(USBFS_Type const *base, cy_cb_usbfs_dev_drv_callback_t callback, cy_stc_usbfs_dev_drv_context_t *context) { - /* Suppress a compiler warning about unused variables */ + /* Suppresses a compiler warning about unused variables */ (void) base; switch(source) @@ -1130,16 +1190,15 @@ void Cy_USBFS_Dev_Drv_RegisterServiceCallback(USBFS_Type const *base, static void RestoreDeviceConfiguration(USBFS_Type *base, cy_stc_usbfs_dev_drv_context_t *context) { - uint32_t endpoint = 0U; + uint32_t endpoint; - /* Set default device configuration */ - Cy_USBFS_Dev_Drv_ConfigDevice(base, context); + /* Due to Deep Sleep, non-retention registers are set to the default state */ for (endpoint = 0U; endpoint < CY_USBFS_DEV_DRV_NUM_EPS_MAX; ++endpoint) { if (0U != context->epPool[endpoint].address) { - /* Restore endpoint configuration */ + /* Restores the endpoint configuration */ if (CY_USBFS_DEV_DRV_EP_MANAGEMENT_DMA_AUTO == context->mode) { RestoreEndpointRamBuffer(base, &context->epPool[endpoint]); @@ -1151,8 +1210,8 @@ static void RestoreDeviceConfiguration(USBFS_Type *base, } } - /* Complete configuration */ - Cy_USBFS_Dev_Drv_ConfigDeviceComplete(base, context); + /* Completes the device configuration */ + Cy_USBFS_Dev_Drv_ConfigDevice(base, context); } @@ -1173,18 +1232,18 @@ static void RestoreDeviceConfiguration(USBFS_Type *base, * * \note * After entering low-power mode, the data that is left in the IN or OUT -* endpoint buffers is not restored after wakeup, and is lost. Therefore, it should -* be stored in the SRAM for OUT endpoint or read by the host for IN endpoint +* endpoint buffers is not restored after a wakeup, and is lost. Therefore, it should +* be stored in the SRAM for OUT endpoint or read by the host for the IN endpoint * before entering low-power mode. * *******************************************************************************/ void Cy_USBFS_Dev_Drv_Suspend(USBFS_Type *base, cy_stc_usbfs_dev_drv_context_t *context) { - /* Put PHY to suspend mode */ + /* Puts PHY to suspend mode */ USBFS_DEV_LPM_POWER_CTL(base) |= USBFS_USBLPM_POWER_CTL_SUSPEND_Msk; (void) USBFS_DEV_LPM_POWER_CTL(base); - /* Disable all DMA channels: DMA registers are retention */ + /* Disables all DMA channels: DMA registers are retention */ if (CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU != context->mode) { DmaDisable(context); @@ -1210,19 +1269,19 @@ void Cy_USBFS_Dev_Drv_Suspend(USBFS_Type *base, cy_stc_usbfs_dev_drv_context_t * *******************************************************************************/ void Cy_USBFS_Dev_Drv_Resume(USBFS_Type *base, cy_stc_usbfs_dev_drv_context_t *context) { - /* Enable clock to mxusbfs IP */ + /* Enables the clock to mxusbfs IP */ USBFS_DEV_USB_CLK_EN(base) = CY_USBFS_DEV_DRV_WRITE_ODD(USBFS_USBDEV_USB_CLK_EN_CSR_CLK_EN_Msk); - /* Set number of clocks (divided version of Clk_Peri) to detect bus reset */ + /* Sets the number of clocks (divided version of Clk_Peri) to detect bus reset */ USBFS_DEV_BUS_RST_CNT(base) = BUS_RESET_PERIOD; - /* Set EP0.CR: ACK Setup, NAK IN/OUT */ + /* Sets EP0.CR: ACK Setup, NAK IN/OUT */ USBFS_DEV_EP0_CR(base) = CY_USBFS_DEV_DRV_EP_CR_NAK_INOUT; - /* Restore data endpoints configuration */ + /* Restores the data endpoints configuration */ RestoreDeviceConfiguration(base, context); - /* Release PHY from suspend mode */ + /* Releases PHY from suspend mode */ USBFS_DEV_LPM_POWER_CTL(base) &= ~USBFS_USBLPM_POWER_CTL_SUSPEND_Msk; (void) USBFS_DEV_LPM_POWER_CTL(base); } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_usbfs_dev_drv_io.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_usbfs_dev_drv_io.c index a02a5aaf5f..3f917588a0 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_usbfs_dev_drv_io.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_usbfs_dev_drv_io.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_usbfs_dev_drv_io.c -* \version 1.10 +* \version 2.0 * * Provides data transfer API implementation of the USBFS driver. * @@ -35,10 +35,15 @@ extern "C" { * Internal Constants *******************************************************************************/ +/* The time to wait (in milliseconds) for completion of a BULK or INTERRUPT transfer (max packet 64 bytes). +* The transfer takes 48.5 us = (1/ 12) * (32 (IN/OUT) + (64 * 8 + 32) (DATA) + 16 (ACK) + 6 (EOPs)), used 50 us. +*/ +#define WAIT_TRANSFER_COMPLETE (50U) + /* Dedicated IN and OUT endpoints buffer: 32 bytes (2^5) */ #define ENDPOINTS_BUFFER_SIZE (0x55UL) -/* Number of bytes transferred by 1 Y-loop */ +/* The number of bytes transferred by 1 Y-loop */ #define DMA_YLOOP_INCREMENT (32UL) /* All arbiter interrupt sources */ @@ -73,7 +78,7 @@ static void DisableEndpoint(USBFS_Type *base, uint32_t endpoint, cy_stc_usbfs_de * Function Name: DisableEndpoint ****************************************************************************//** * -* Disables endpoint operation. +* Disables the endpoint operation. * * \param base * The pointer to the USBFS instance. @@ -90,7 +95,7 @@ static void DisableEndpoint(USBFS_Type *base, uint32_t endpoint, cy_stc_usbfs_de *******************************************************************************/ static void DisableEndpoint(USBFS_Type *base, uint32_t endpoint, cy_stc_usbfs_dev_drv_context_t *context) { - /* Disable endpoint SIE mode and set appropriate state */ + /* Disables endpoint SIE mode and sets the appropriate state */ Cy_USBFS_Dev_Drv_SetSieEpMode(base, endpoint, CY_USBFS_DEV_DRV_EP_CR_DISABLE); context->epPool[endpoint].state = CY_USB_DEV_EP_DISABLED; } @@ -100,8 +105,9 @@ static void DisableEndpoint(USBFS_Type *base, uint32_t endpoint, cy_stc_usbfs_de * Function Name: Cy_USBFS_Dev_Drv_ConfigDevice ****************************************************************************//** * -* Set basic device configuration (clears previous configuration). -* Call this function before configuring endpoints for operation. +* Sets the basic device configuration (clears previous configuration). +* Call this function after the endpoints were configured to complete the +* device configuration. * * \param base * The pointer to the USBFS instance. @@ -115,49 +121,26 @@ static void DisableEndpoint(USBFS_Type *base, uint32_t endpoint, cy_stc_usbfs_de *******************************************************************************/ void Cy_USBFS_Dev_Drv_ConfigDevice(USBFS_Type *base, cy_stc_usbfs_dev_drv_context_t *context) { - uint32_t endpoint; - - /* Clear buffer pointer */ - context->curBufAddr = 0U; - - /* Disable SIE and Arbiter interrupts */ - USBFS_DEV_SIE_EP_INT_EN(base) = 0UL; - USBFS_DEV_ARB_INT_EN(base) = 0UL; - - /* Prepare endpoints for configuration */ - for (endpoint = 0U; endpoint < CY_USBFS_DEV_DRV_NUM_EPS_MAX; ++endpoint) - { - /* Disable endpoint operation */ - DisableEndpoint(base, endpoint, context); - - /* Set default arbiter configuration */ - Cy_USBFS_Dev_Drv_SetArbEpConfig(base, endpoint, (USBFS_USBDEV_ARB_EP1_CFG_CRC_BYPASS_Msk | - USBFS_USBDEV_ARB_EP1_CFG_RESET_PTR_Msk)); - } - if (CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU != context->mode) { - uint32_t regVal = _VAL2FLD(USBFS_USBDEV_ARB_CFG_DMA_CFG, context->mode); + uint32_t autoMemMask = 0U; if (CY_USBFS_DEV_DRV_EP_MANAGEMENT_DMA_AUTO == context->mode) { - regVal |= USBFS_USBDEV_ARB_CFG_AUTO_MEM_Msk; - } - - /* Allow re-configuration: clear configuration complete bit */ - USBFS_DEV_ARB_CFG(base) = regVal; - (void) USBFS_DEV_ARB_CFG(base); - - if (CY_USBFS_DEV_DRV_EP_MANAGEMENT_DMA_AUTO == context->mode) - { - /* Reset configuration registers */ - USBFS_DEV_EP_ACTIVE(base) = 0UL; - USBFS_DEV_EP_TYPE(base) = CY_USBFS_DEV_DRV_WRITE_ODD(0UL); - + autoMemMask = USBFS_USBDEV_ARB_CFG_AUTO_MEM_Msk; + /* Configure DMA burst size */ - USBFS_DEV_BUF_SIZE(base) = ENDPOINTS_BUFFER_SIZE; USBFS_DEV_DMA_THRES16(base) = DMA_YLOOP_INCREMENT; + USBFS_DEV_BUF_SIZE(base) = ENDPOINTS_BUFFER_SIZE; + + /* USBFS_DEV_EP_ACTIVE and USBFS_DEV_EP_TYPE are set when endpoint is added */ } + + /* The configuration completes: Generates a rising edge for the USBDEV_ARB_CFG.CFG_CMP bit */ + USBFS_DEV_ARB_CFG(base) = _VAL2FLD(USBFS_USBDEV_ARB_CFG_DMA_CFG, context->mode) | + autoMemMask; + USBFS_DEV_ARB_CFG(base) |= USBFS_USBDEV_ARB_CFG_CFG_CMP_Msk; + (void) USBFS_DEV_ARB_CFG(base); } } @@ -166,8 +149,10 @@ void Cy_USBFS_Dev_Drv_ConfigDevice(USBFS_Type *base, cy_stc_usbfs_dev_drv_contex * Function Name: Cy_USBFS_Dev_Drv_UnConfigureDevice ****************************************************************************//** * -* Clear device configuration. -* Call this function if endpoints configuration fail. +* Clears device configuration. +* Call this function before setting a configuration or a configuration failure +* to set the configuration into the default state. +* Alternately, call \ref Cy_USBFS_Dev_Drv_RemoveEndpoint for each active endpoint. * * \param base * The pointer to the USBFS instance. @@ -183,6 +168,16 @@ void Cy_USBFS_Dev_Drv_UnConfigureDevice(USBFS_Type *base, cy_stc_usbfs_dev_drv_c { uint32_t endpoint; + /* Clears the buffer pointer */ + context->curBufAddr = 0U; + + /* Removes all active endpoints */ + context->activeEpMask = 0U; + + /* Disables the SIE and Arbiter interrupts */ + USBFS_DEV_SIE_EP_INT_EN(base) = 0UL; + USBFS_DEV_ARB_INT_EN(base) = 0UL; + /* Clear endpoints configuration */ for (endpoint = 0U; endpoint < CY_USBFS_DEV_DRV_NUM_EPS_MAX; ++endpoint) { @@ -192,43 +187,17 @@ void Cy_USBFS_Dev_Drv_UnConfigureDevice(USBFS_Type *base, cy_stc_usbfs_dev_drv_c } -/******************************************************************************* -* Function Name: Cy_USBFS_Dev_Drv_ConfigDeviceComplete -****************************************************************************//** -* -* Locks device configuration before following operation. -* -* \param base -* The pointer to the USBFS instance. -* -* \param context -* The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t -* allocated by the user. The structure is used during the USBFS Device -* operation for internal configuration and data retention. The user must not -* modify anything in this structure. -* -*******************************************************************************/ -void Cy_USBFS_Dev_Drv_ConfigDeviceComplete(USBFS_Type *base, cy_stc_usbfs_dev_drv_context_t const *context) -{ - if (CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU != context->mode) - { - /* Configuration complete: set configuration complete bit (generate rising edge) */ - USBFS_DEV_ARB_CFG(base) |= USBFS_USBDEV_ARB_CFG_CFG_CMP_Msk; - } -} - - /******************************************************************************* * Function Name: GetEndpointBuffer ****************************************************************************//** * -* Returns start position in the allocated buffer for data endpoint. +* Returns a start position in the allocated buffer for the data endpoint. * * \param size -* Data endpoint buffer size. +* The data endpoint buffer size. * * \param idx -* Start position of the allocated endpoint buffer. +* The start position of the allocated endpoint buffer. * * \param context * The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t @@ -237,7 +206,7 @@ void Cy_USBFS_Dev_Drv_ConfigDeviceComplete(USBFS_Type *base, cy_stc_usbfs_dev_dr * modify anything in this structure. * * \return -* Status code of the function execution \ref cy_en_usbfs_dev_drv_status_t. +* The status code of the function execution \ref cy_en_usbfs_dev_drv_status_t. * *******************************************************************************/ cy_en_usbfs_dev_drv_status_t GetEndpointBuffer(uint32_t size, uint32_t *idx, cy_stc_usbfs_dev_drv_context_t *context) @@ -251,14 +220,14 @@ cy_en_usbfs_dev_drv_status_t GetEndpointBuffer(uint32_t size, uint32_t *idx, cy_ CY_USBFS_DEV_DRV_HW_BUFFER_SIZE : context->epSharedBufSize; - /* Get next buffer address. Note the end buffer size must be even for 16-bit access */ + /* Gets a next buffer address. Note: the end buffer size must be even for the 16-bit access. */ nextBufAddr = (context->curBufAddr + size); nextBufAddr += (context->useReg16) ? (size & 0x01U) : 0U; - /* Check whether there is enough space in the buffer */ + /* Checks whether there is enough space in the buffer. */ if (nextBufAddr <= bufSize) { - /* Update pointers */ + /* Updates the pointers */ *idx = context->curBufAddr; context->curBufAddr = (uint16_t) nextBufAddr; @@ -273,15 +242,18 @@ cy_en_usbfs_dev_drv_status_t GetEndpointBuffer(uint32_t size, uint32_t *idx, cy_ * Function Name: RestoreEndpointHwBuffer ****************************************************************************//** * -* Restores endpoint active configuration for +* Restores the endpoint active configuration for * \ref CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU and * \ref CY_USBFS_DEV_DRV_EP_MANAGEMENT_DMA modes. * * \param base * The pointer to the USBFS instance. * -* \param endpoint -* The OUT data endpoint number. +* \param mode +* Endpoints management mode. +* +* \param endpointData +* The pointer to the endpoint data structure. * * \param context * The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t @@ -297,35 +269,39 @@ void RestoreEndpointHwBuffer(USBFS_Type *base, bool inDirection = IS_EP_DIR_IN(endpointData->address); uint32_t endpoint = EPADDR2PHY(endpointData->address); - /* Clear state: MEM_DATA is not non-retention */ + /* Clears the state: MEM_DATA is not non-retention */ endpointData->state = CY_USB_DEV_EP_IDLE; - /* Set Arbiter read and write pointers */ + /* Sets the Arbiter read and write pointers */ Cy_USBFS_Dev_Drv_SetArbWriteAddr(base, endpoint, (uint32_t) endpointData->startBuf); Cy_USBFS_Dev_Drv_SetArbReadAddr (base, endpoint, (uint32_t) endpointData->startBuf); - /* Enable endpoint Arbiter interrupt sources */ + /* Enables the endpoint Arbiter interrupt sources */ if (CY_USBFS_DEV_DRV_EP_MANAGEMENT_DMA == mode) { - /* Enable Arbiter interrupt sources for endpoint */ + /* Enables the Arbiter interrupt sources for endpoint */ Cy_USBFS_Dev_Drv_SetArbEpInterruptMask(base, endpoint, (inDirection ? IN_ENDPOINT_ARB_INTR_SOURCES_DMA : OUT_ENDPOINT_ARB_INTR_SOURCES_DMA)); - /* Enable Arbiter interrupt for endpoint */ + /* Enables the Arbiter interrupt for endpoint */ Cy_USBFS_Dev_Drv_EnableArbEpInterrupt(base, endpoint); - /* Enable DMA channel */ + /* Enables the DMA channel */ Cy_DMA_Channel_Enable(endpointData->base, endpointData->chNum); } else { - /* Enable error interrupt triggered by SIE */ + /* Enables the error interrupt triggered by SIE */ Cy_USBFS_Dev_Drv_SetArbEpInterruptMask(base, endpoint, ENDPOINT_ARB_INTR_SOURCES_CPU); } - /* Enable SIE interrupt for endpoint */ - Cy_USBFS_Dev_Drv_EnableSieEpInterrupt(base, endpoint); + /* Enables the SIE interrupt for the endpoint */ + Cy_USBFS_Dev_Drv_EnableSieEpInterrupt(base, endpoint); + + /* Sets an arbiter configuration */ + Cy_USBFS_Dev_Drv_SetArbEpConfig(base, endpoint, (USBFS_USBDEV_ARB_EP1_CFG_CRC_BYPASS_Msk | + USBFS_USBDEV_ARB_EP1_CFG_RESET_PTR_Msk)); /* Set endpoint mode to not respond to host */ Cy_USBFS_Dev_Drv_SetSieEpMode(base, endpoint, GetEndpointInactiveMode((uint32_t) endpointData->sieMode)); @@ -353,7 +329,7 @@ void RestoreEndpointHwBuffer(USBFS_Type *base, * modify anything in this structure. * * \return -* Status code of the function execution \ref cy_en_usbfs_dev_drv_status_t. +* The status code of the function execution \ref cy_en_usbfs_dev_drv_status_t. * *******************************************************************************/ cy_en_usbfs_dev_drv_status_t AddEndpointHwBuffer(USBFS_Type *base, @@ -362,33 +338,33 @@ cy_en_usbfs_dev_drv_status_t AddEndpointHwBuffer(USBFS_Type *base, { uint32_t endpoint = EPADDR2PHY(config->endpointAddr); - /* Get pointer to endpoint data */ + /* Gets a pointer to the endpoint data */ cy_stc_usbfs_dev_drv_endpoint_data_t *endpointData = &context->epPool[endpoint]; - /* Get buffer for endpoint using hardware buffer */ + /* Gets a buffer for the endpoint using the hardware buffer */ if (config->allocBuffer) { uint32_t bufOffset; - /* Get buffer for endpoint */ + /* Gets a buffer for the endpoint */ cy_en_usbfs_dev_drv_status_t retStatus = GetEndpointBuffer((uint32_t) config->bufferSize, &bufOffset, context); if (CY_USBFS_DEV_DRV_SUCCESS != retStatus) { return retStatus; } - /* Set Arbiter read and write pointers */ + /* Sets the Arbiter read and write pointers */ endpointData->startBuf = (uint16_t) bufOffset; Cy_USBFS_Dev_Drv_SetArbWriteAddr(base, endpoint, bufOffset); Cy_USBFS_Dev_Drv_SetArbReadAddr (base, endpoint, bufOffset); } - /* Enable endpoint for the operation */ + /* Enables the endpoint for the operation */ if (config->enableEndpoint) { bool inDirection = IS_EP_DIR_IN(config->endpointAddr); - /* Configure endpoint */ + /* Configures the endpoint */ endpointData->state = CY_USB_DEV_EP_IDLE; endpointData->address = config->endpointAddr; endpointData->toggle = 0U; @@ -396,8 +372,12 @@ cy_en_usbfs_dev_drv_status_t AddEndpointHwBuffer(USBFS_Type *base, endpointData->sieMode = GetEndpointActiveMode(inDirection, config->attributes); endpointData->isPending = false; - /* Flush IN endpoint buffer to discard loaded data. - * It happens when: alternate settings change is requested and IN + /* Sets an arbiter configuration (clears DMA requests) */ + Cy_USBFS_Dev_Drv_SetArbEpConfig(base, endpoint, (USBFS_USBDEV_ARB_EP1_CFG_CRC_BYPASS_Msk | + USBFS_USBDEV_ARB_EP1_CFG_RESET_PTR_Msk)); + + /* Flushes the IN endpoint buffer to discard the loaded data. + * It happens when: an alternate settings change is requested and the IN * endpoint buffer is full (not read by the Host). */ if (inDirection) @@ -405,34 +385,34 @@ cy_en_usbfs_dev_drv_status_t AddEndpointHwBuffer(USBFS_Type *base, Cy_USBFS_Dev_Drv_FlushInBuffer(base, endpoint); } - /* Enable endpoint arbiter interrupt sources */ + /* Enables the endpoint arbiter interrupt sources */ if (CY_USBFS_DEV_DRV_EP_MANAGEMENT_DMA == context->mode) { - /* Configure DMA based on endpoint direction */ + /* Configures the DMA based on the endpoint direction */ cy_en_usbfs_dev_drv_status_t retStatus = DmaEndpointInit(base, context->mode, context->useReg16, &context->epPool[endpoint]); if (CY_USBFS_DEV_DRV_SUCCESS != retStatus) { return retStatus; } - /* Enable arbiter interrupt sources for endpoint */ + /* Enables the arbiter interrupt sources for the endpoint */ Cy_USBFS_Dev_Drv_SetArbEpInterruptMask(base, endpoint, (inDirection ? IN_ENDPOINT_ARB_INTR_SOURCES_DMA : OUT_ENDPOINT_ARB_INTR_SOURCES_DMA)); - /* Enable arbiter interrupt for endpoint */ + /* Enables the arbiter interrupt for the endpoint */ Cy_USBFS_Dev_Drv_EnableArbEpInterrupt(base, endpoint); } else { - /* Enable error interrupt triggered by SIE */ + /* Enables the error interrupt triggered by SIE */ Cy_USBFS_Dev_Drv_SetArbEpInterruptMask(base, endpoint, ENDPOINT_ARB_INTR_SOURCES_CPU); } - /* Enable SIE interrupt for endpoint */ + /* Enables the SIE interrupt for the endpoint */ Cy_USBFS_Dev_Drv_EnableSieEpInterrupt(base, endpoint); - /* Set endpoint mode to not respond to host */ + /* Sets endpoint mode to not respond to the host */ Cy_USBFS_Dev_Drv_SetSieEpMode(base, endpoint, GetEndpointInactiveMode((uint32_t) endpointData->sieMode)); } @@ -444,7 +424,7 @@ cy_en_usbfs_dev_drv_status_t AddEndpointHwBuffer(USBFS_Type *base, * Function Name: Cy_USBFS_Dev_Drv_RemoveEndpoint ****************************************************************************//** * -* Removes data endpoint (release hardware resources allocated by data endpoint). +* Removes a data endpoint (release hardware resources allocated by data endpoint). * * \param base * The pointer to the USBFS instance. @@ -466,7 +446,15 @@ cy_en_usbfs_dev_drv_status_t Cy_USBFS_Dev_Drv_RemoveEndpoint(USBFS_Type *base, uint32_t endpointAddr, cy_stc_usbfs_dev_drv_context_t *context) { - uint32_t endpoint = EPADDR2PHY(endpointAddr); + uint32_t endpoint = EPADDR2EP(endpointAddr); + + /* Checks if the endpoint is supported by the driver */ + if (false == IS_EP_VALID(endpoint)) + { + return CY_USBFS_DEV_DRV_BAD_PARAM; + } + + endpoint = EP2PHY(endpoint); /* Disable endpoint operation */ DisableEndpoint(base, endpoint, context); @@ -479,6 +467,12 @@ cy_en_usbfs_dev_drv_status_t Cy_USBFS_Dev_Drv_RemoveEndpoint(USBFS_Type *base, Cy_USBFS_Dev_Drv_ClearSieEpInterrupt(base, endpoint); Cy_USBFS_Dev_Drv_ClearArbEpInterrupt(base, endpoint, ENDPOINT_ARB_INTR_SOURCES_ALL); + /* Removes the active endpoint */ + context->activeEpMask &= (uint8_t) ~EP2MASK(endpont); + + /* Clear abort mask for endpoint */ + context->epAbortMask &= (uint8_t) ~EP2MASK(endpoint); + return CY_USBFS_DEV_DRV_SUCCESS; } @@ -521,7 +515,10 @@ void Cy_USBFS_Dev_Drv_EnableOutEndpoint(USBFS_Type *base, /* Get pointer to endpoint data */ cy_stc_usbfs_dev_drv_endpoint_data_t *endpointData = &context->epPool[endpoint]; - /* Clear transfer complete notification */ + /* Clear abort mask for the endpoint (there is no transfer during abort) */ + context->epAbortMask &= (uint8_t) ~EP2MASK(endpoint); + + /* Endpoint pending: Waits for the host write data after exiting this function */ endpointData->state = CY_USB_DEV_EP_PENDING; /* Arm endpoint: Host is allowed to write data */ @@ -574,7 +571,10 @@ cy_en_usbfs_dev_drv_status_t LoadInEndpointCpu(USBFS_Type *base, return CY_USBFS_DEV_DRV_BAD_PARAM; } - /* Clear transfer completion notification */ + /* Clear abort mask for the endpoint (there is no transfer during abort) */ + context->epAbortMask &= (uint8_t) ~EP2MASK(endpoint); + + /* Endpoint pending: Waits for the host read data after exiting this function */ endpointData->state = CY_USB_DEV_EP_PENDING; /* Set count and data toggle */ @@ -598,7 +598,7 @@ cy_en_usbfs_dev_drv_status_t LoadInEndpointCpu(USBFS_Type *base, size = GET_SIZE16(size); /* Copy data from the user buffer into the hardware buffer */ - for (idx = 0u; idx < size; ++idx) + for (idx = 0U; idx < size; ++idx) { Cy_USBFS_Dev_Drv_WriteData16(base, endpoint, ptr[idx]); } @@ -607,7 +607,7 @@ cy_en_usbfs_dev_drv_status_t LoadInEndpointCpu(USBFS_Type *base, { /* Copy data from the user buffer into the hardware buffer */ - for (idx = 0u; idx < size; ++idx) + for (idx = 0U; idx < size; ++idx) { Cy_USBFS_Dev_Drv_WriteData(base, endpoint, buffer[idx]); } @@ -719,12 +719,13 @@ cy_en_usbfs_dev_drv_status_t ReadOutEndpointCpu(USBFS_Type *base, * Function Name: Cy_USBFS_Dev_Drv_Abort ****************************************************************************//** * -* Starts abort operation for data endpoint. -* If this function returns \ref CY_USB_DEV_EP_PENDING state, the firmware must -* wait for 1 millisecond to allow the USB Host to complete a possible on-going transfer. -* After this time is passed, call \ref Cy_USBFS_Dev_Drv_GetEndpointState to -* define endpoint state. If endpoint is still pending, call -* \ref Cy_USBFS_Dev_Drv_AbortComplete to complete abort operation. +* Abort operation for data endpoint. +* If there is any bus activity after the abort operation requested, the function +* waits for its completion or a timeout. A timeout is the time to transfer the +* bulk or an interrupt packet of the maximum playload size. If this bus activity is +* a transfer to the aborting endpoint, the received data is lost and the endpoint +* transfer completion callbacks are not invoked. +* After the function returns a new read or write, the endpoint operation can be submitted. * * \param base * The pointer to the USBFS instance. @@ -742,120 +743,144 @@ cy_en_usbfs_dev_drv_status_t ReadOutEndpointCpu(USBFS_Type *base, * Data endpoint state \ref cy_en_usb_dev_ep_state_t after abort was applied. * * \note -* This abort operation is not supported for ISOC endpoints because -* these endpoints do not have handshake and are always accessible to the -* USB Host. Therefore, abort can cause unexpected behavior. +* - This abort operation is not supported for the ISOC endpoints because +* these endpoints do not have a handshake and are always accessible to the +* USB Host. Therefore, an abort can cause unexpected behavior. +* - The function uses the critical section to protect from the endpoint transfer +* complete interrupt. * *******************************************************************************/ -cy_en_usb_dev_ep_state_t Cy_USBFS_Dev_Drv_Abort(USBFS_Type *base, - uint32_t endpoint, - cy_stc_usbfs_dev_drv_context_t const *context) -{ - cy_en_usb_dev_ep_state_t epState = CY_USB_DEV_EP_INVALID; - - CY_ASSERT_L1(CY_USBFS_DEV_DRV_IS_EP_VALID(endpoint)); - - endpoint = EP2PHY(endpoint); - - /* Get endpoint state */ - epState = context->epPool[endpoint].state; - - switch(Cy_USBFS_Dev_Drv_GetSieEpMode(base, endpoint)) - { - case CY_USBFS_DEV_DRV_EP_CR_ISO_OUT: - case CY_USBFS_DEV_DRV_EP_CR_ISO_IN: - /* ISOC endpoint do not support abort operation */ - epState = CY_USB_DEV_EP_INVALID; - break; - - case CY_USBFS_DEV_DRV_EP_CR_ACK_OUT: - /* State must be CY_USB_DEV_EP_PENDING */ - Cy_USBFS_Dev_Drv_SetSieEpMode(base, endpoint, CY_USBFS_DEV_DRV_EP_CR_NAK_OUT); - break; - - case CY_USBFS_DEV_DRV_EP_CR_ACK_IN: - /* State must be CY_USB_DEV_EP_PENDING */ - Cy_USBFS_Dev_Drv_SetSieEpMode(base, endpoint, CY_USBFS_DEV_DRV_EP_CR_NAK_IN); - break; - - case CY_USBFS_DEV_DRV_EP_CR_NAK_OUT: - case CY_USBFS_DEV_DRV_EP_CR_NAK_IN: - /* State must be CY_USB_DEV_EP_COMPLETED or CY_USB_DEV_EP_IDLE */ - break; - - default: - epState = CY_USB_DEV_EP_INVALID; - break; - } - - return (epState); -} - - -/******************************************************************************* -* Function Name: Cy_USBFS_Dev_Drv_AbortComplete -****************************************************************************//** -* -* Completes abort operation for data endpoint when endpoint is still in pending -* state. Find the details of the abort procedure in the \ref Cy_USBFS_Dev_Drv_Abort -* function description. -* -* \param base -* The pointer to the USBFS instance. -* -* \param endpoint -* The data endpoint number. -* -* \param context -* The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t -* allocated by the user. The structure is used during the USBFS Device -* operation for internal configuration and data retention. The user must not -* modify anything in this structure. -* -*******************************************************************************/ -cy_en_usbfs_dev_drv_status_t Cy_USBFS_Dev_Drv_AbortComplete(USBFS_Type *base, - uint32_t endpoint, - cy_stc_usbfs_dev_drv_context_t *context) +cy_en_usbfs_dev_drv_status_t Cy_USBFS_Dev_Drv_Abort(USBFS_Type *base, + uint32_t endpoint, + cy_stc_usbfs_dev_drv_context_t *context) { cy_en_usbfs_dev_drv_status_t retStatus = CY_USBFS_DEV_DRV_BAD_PARAM; - bool inDirection; + cy_stc_usbfs_dev_drv_endpoint_data_t *endpointData; + bool flushBuffer = true; + uint32_t intrState; - endpoint = EP2PHY(endpoint); - inDirection = IS_EP_DIR_IN(context->epPool[endpoint].address); - - /* Initialize pointers to functions that work with data endpoint */ - switch(context->mode) + /* Checks if the endpoint is supported by the driver */ + if (false == IS_EP_VALID(endpoint)) { - case CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU: - case CY_USBFS_DEV_DRV_EP_MANAGEMENT_DMA: - { - /* IN endpoint: flush buffer to discard loaded data. - * OUT endpoint: leave written data in the buffer. - */ - if (inDirection) - { - Cy_USBFS_Dev_Drv_FlushInBuffer(base, endpoint); - } - - retStatus = CY_USBFS_DEV_DRV_SUCCESS; - } - break; - - case CY_USBFS_DEV_DRV_EP_MANAGEMENT_DMA_AUTO: - { - /* IN endpoint: flush buffer to discard loaded data. - * OUT endpoint: wait for DMA complete if transfer was started. - */ - retStatus = DynamicEndpointReConfiguration(base, inDirection, endpoint); - } - break; - - default: - break; + return retStatus; } - /* Abort operation was successful: set endpoint idle state */ - context->epPool[endpoint].state = CY_USB_DEV_EP_IDLE; + endpoint = EP2PHY(endpoint); + endpointData = &context->epPool[endpoint]; + + /* Locks from the context modification by the endpoint completion interrupt */ + intrState = Cy_SysLib_EnterCriticalSection(); + + /* Checks whether the endpoint is configured */ + if (CY_USB_DEV_EP_DISABLED == endpointData->state) + { + return retStatus; + } + else if (CY_USB_DEV_EP_STALLED == endpointData->state) + { + /* Aborts a pending transfer if the endpoint is stalled */ + context->epAbortMask |= (uint8_t) EP2MASK(endpoint); + endpointData->isPending = false; + } + else if (CY_USB_DEV_EP_PENDING == endpointData->state) + { + bool isocEp = false; + + /* Sets an abort mask to discard the completion events */ + context->epAbortMask |= (uint8_t) EP2MASK(endpoint); + endpointData->state = CY_USB_DEV_EP_IDLE; + + /* Clears the bus busy activity */ + (void) Cy_USBFS_Dev_Drv_CheckActivity(base); + + if (endpointData->sieMode == CY_USBFS_DEV_DRV_EP_CR_ACK_IN) + { + Cy_USBFS_Dev_Drv_SetSieEpMode(base, endpoint, CY_USBFS_DEV_DRV_EP_CR_NAK_IN); + } + else if (endpointData->sieMode == CY_USBFS_DEV_DRV_EP_CR_ACK_OUT) + { + Cy_USBFS_Dev_Drv_SetSieEpMode(base, endpoint, CY_USBFS_DEV_DRV_EP_CR_NAK_OUT); + } + else + { + /* Does not wait for the ISOC endpoint */ + isocEp = true; + } + + if (false == isocEp) + { + /* If there is a bus activity, it could be a transfer to the aborted endpoint */ + if (Cy_USBFS_Dev_Drv_CheckActivity(base)) + { + /* Releases the lock */ + Cy_SysLib_ExitCriticalSection(intrState); + + uint32_t timeout = WAIT_TRANSFER_COMPLETE; + + /* Waits for BULK or INTERRUPT transfer completion or a NACK interrupt */ + while ( (timeout != 0U) && + (0U != (context->epAbortMask & EP2MASK(endpoint))) ) + { + if (false == Cy_USBFS_Dev_Drv_CheckActivity(base)) + { + break; + } + + Cy_SysLib_DelayUs(1U); + --timeout; + } + } + } + + /* The abort mask is cleared in the endpoint completion interrupt OR + * on a following call of the endpoint Remove, LoadIn or EnableOut function. + */ + } + else + { + /* Does nothing for all other states: CY_USB_DEV_EP_IDLE or CY_USB_DEV_EP_COMPLETED */ + flushBuffer = false; + retStatus = CY_USBFS_DEV_DRV_SUCCESS; + } + + /* Releases the lock */ + Cy_SysLib_ExitCriticalSection(intrState); + + if (flushBuffer) + { + bool inDirection = IS_EP_DIR_IN(endpointData->address); + + /* Initializes the pointers to functions that work with the data endpoint */ + switch(context->mode) + { + case CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU: + case CY_USBFS_DEV_DRV_EP_MANAGEMENT_DMA: + { + /* IN endpoint: Flushes the buffer to discard the loaded data. + * OUT endpoint: Leaves the written data in the buffer. + */ + if (inDirection) + { + Cy_USBFS_Dev_Drv_FlushInBuffer(base, endpoint); + } + + retStatus = CY_USBFS_DEV_DRV_SUCCESS; + } + break; + + case CY_USBFS_DEV_DRV_EP_MANAGEMENT_DMA_AUTO: + { + /* IN endpoint: Flushes the buffer to discard the loaded data. + * OUT endpoint: Waits for DMA to complete if a transfer has been started. + */ + retStatus = DynamicEndpointReConfiguration(base, inDirection, endpoint); + } + break; + + default: + break; + } + } return retStatus; } @@ -904,7 +929,6 @@ cy_en_usbfs_dev_drv_status_t Cy_USBFS_Dev_Drv_StallEndpoint(USBFS_Type *base, return CY_USBFS_DEV_DRV_BAD_PARAM; } - /* Store current endpoint state to restore it after Stall clear */ endpointData->isPending = (CY_USB_DEV_EP_PENDING == endpointData->state); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_usbfs_dev_drv_io_dma.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_usbfs_dev_drv_io_dma.c index 7316eb373c..340d217187 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_usbfs_dev_drv_io_dma.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_usbfs_dev_drv_io_dma.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_usbfs_dev_drv_io_dma.c -* \version 1.10 +* \version 2.0 * * Provides data transfer API implementation of the USBFS driver. * @@ -670,7 +670,8 @@ cy_en_usbfs_dev_drv_status_t AddEndpointRamBuffer(USBFS_Type *base, uint32_t startBufIdx; /* Configure active endpoint */ - USBFS_DEV_EP_ACTIVE(base) |= EP2MASK(endpont); + context->activeEpMask |= (uint8_t) EP2MASK(endpont); + USBFS_DEV_EP_ACTIVE(base) = context->activeEpMask; /* Allocate buffer for endpoint */ retStatus = GetEndpointBuffer((uint32_t) config->bufferSize, &startBufIdx, context); @@ -695,7 +696,11 @@ cy_en_usbfs_dev_drv_status_t AddEndpointRamBuffer(USBFS_Type *base, endpointData->bufferSize = config->maxPacketSize; endpointData->sieMode = GetEndpointActiveMode(inDirection, config->attributes); endpointData->isPending = false; - + + /* Set arbiter configuration (clears DMA requests) */ + Cy_USBFS_Dev_Drv_SetArbEpConfig(base, endpoint, (USBFS_USBDEV_ARB_EP1_CFG_CRC_BYPASS_Msk | + USBFS_USBDEV_ARB_EP1_CFG_RESET_PTR_Msk)); + /* Performs dynamic reconfiguration to make sure that the DMA has completed the data transfer. * Also it flushes endpoint pre-fetch buffer (useful for IN endpoints). */ @@ -716,7 +721,7 @@ cy_en_usbfs_dev_drv_status_t AddEndpointRamBuffer(USBFS_Type *base, Cy_USBFS_Dev_Drv_SetArbEpInterruptMask(base, endpoint,(inDirection ? IN_ENDPOINT_ARB_INTR_SOURCES : OUT_ENDPOINT_ARB_INTR_SOURCES)); - + /* Enable SIE and arbiter interrupt for endpoint */ Cy_USBFS_Dev_Drv_EnableSieEpInterrupt(base, endpoint); Cy_USBFS_Dev_Drv_EnableArbEpInterrupt(base, endpoint); @@ -739,8 +744,8 @@ cy_en_usbfs_dev_drv_status_t AddEndpointRamBuffer(USBFS_Type *base, * \param base * The pointer to the USBFS instance. * -* \param endpoint -* The OUT data endpoint number. +* \param endpointData +* The pointer to the endpoint data structure. * * \param context * The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t @@ -781,6 +786,10 @@ void RestoreEndpointRamBuffer(USBFS_Type *base, Cy_DMA_Channel_Enable(endpointData->base, endpointData->chNum); } + /* Sets an arbiter configuration */ + Cy_USBFS_Dev_Drv_SetArbEpConfig(base, endpoint, (USBFS_USBDEV_ARB_EP1_CFG_CRC_BYPASS_Msk | + USBFS_USBDEV_ARB_EP1_CFG_RESET_PTR_Msk)); + /* Set SIE mode to respond to host */ Cy_USBFS_Dev_Drv_SetSieEpMode(base, endpoint, GetEndpointInactiveMode((uint32_t) endpointData->sieMode)); } @@ -832,13 +841,16 @@ cy_en_usbfs_dev_drv_status_t LoadInEndpointDma(USBFS_Type *base, { return CY_USBFS_DEV_DRV_BAD_PARAM; } - + + /* Clears the abort mask for the endpoint (there is no transfer during abort) */ + context->epAbortMask &= (uint8_t) ~EP2MASK(endpoint); + /* Set count and data toggle */ Cy_USBFS_Dev_Drv_SetSieEpCount(base, endpoint, size, (uint32_t) endpointData->toggle); if (0U == size) { - /* Clear transfer complete notification */ + /* Endpoint pending: Waits for the host read data after exiting this function */ endpointData->state = CY_USB_DEV_EP_PENDING; /* Arm endpoint: Host is allowed to read data */ @@ -867,7 +879,10 @@ cy_en_usbfs_dev_drv_status_t LoadInEndpointDma(USBFS_Type *base, */ Cy_USBFS_Dev_Drv_TriggerArbCfgEpDmaReq(base, endpoint); - /* Wait until DMA complete write operation */ + /* Waits until DMA completes the write operation. The current endpoint state is + * idle or completed and DMA completion interrupt changes state to pending + * (endpoint waits for the host read data). + */ while ((CY_USB_DEV_EP_PENDING != endpointData->state) && (timeout > 0U)) { @@ -964,14 +979,16 @@ cy_en_usbfs_dev_drv_status_t ReadOutEndpointDma(USBFS_Type *base, /* Enable DMA channel: configuration complete */ Cy_DMA_Channel_Enable(endpointData->base, endpointData->chNum); - /* Clear completion to track DMA read complete */ + /* The current endpoint state is completed, changes the state to pending to + * track DMA read completion. + */ endpointData->state = CY_USB_DEV_EP_PENDING; /* Generate DMA request to read data from hardware buffer */ Cy_USBFS_Dev_Drv_TriggerArbCfgEpDmaReq(base, endpoint); - /* Wait until DMA complete read operation */ - while ((CY_USB_DEV_EP_PENDING == endpointData->state) && + /* Waits until DMA completes the read operation */ + while ((CY_USB_DEV_EP_COMPLETED != endpointData->state) && (timeout > 0U)) { Cy_SysLib_DelayUs(DMA_READ_REQUEST_ONE_TICK); @@ -1034,13 +1051,16 @@ cy_en_usbfs_dev_drv_status_t LoadInEndpointDmaAuto(USBFS_Type *base, { return CY_USBFS_DEV_DRV_BAD_PARAM; } + + /* Clears the abort mask for the endpoint (there is no transfer during abort) */ + context->epAbortMask &= (uint8_t) ~EP2MASK(endpoint); + + /* Endpoint pending: Waits for the host read data after exiting this function */ + endpointData->state = CY_USB_DEV_EP_PENDING; /* Set count and data toggle */ Cy_USBFS_Dev_Drv_SetSieEpCount(base, endpoint, size, (uint32_t) endpointData->toggle); - /* Clear transfer completion */ - endpointData->state = CY_USB_DEV_EP_PENDING; - if (0U == size) { /* Arm endpoint: Host is allowed to read data */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/version.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/version.xml new file mode 100644 index 0000000000..5075a3a72b --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/version.xml @@ -0,0 +1 @@ +1.2.0.730